- UINT64 DisablePState:1; /// Bit52, Disable P-states. When 1, the PAL\r
- /// P-state procedures (PAL_PSTATE_INFO,\r
- /// PAL_SET_PSTATE, PAL_GET_PSTATE) will\r
- /// return with a status of -1\r
- /// (Unimplemented procedure).\r
-\r
- UINT64 EnableMcaOnDataPoisoning:1; /// Bit53, Enable MCA signaling\r
- /// on data-poisoning event\r
- /// detection. When 0, a CMCI\r
- /// will be signaled on error\r
- /// detection. When 1, an MCA\r
- /// will be signaled on error\r
- /// detection. If this feature\r
- /// is not supported, then the\r
- /// corresponding argument is\r
- /// ignored when calling\r
- /// PAL_PROC_SET_FEATURES. Note\r
- /// that the functionality of\r
- /// this bit is independent of\r
- /// the setting in bit 60\r
- /// (Enable CMCI promotion), and\r
- /// that the bit 60 setting does\r
- /// not affect CMCI signaling\r
- /// for data-poisoning related\r
- /// events. Volume 2: Processor\r
- /// Abstraction Layer 2:431\r
- /// PAL_PROC_GET_FEATURES\r
-\r
- UINT64 EnableVmsw:1; /// Bit54, Enable the use of the vmsw\r
- /// instruction. When 0, the vmsw instruction\r
- /// causes a Virtualization fault when\r
- /// executed at the most privileged level.\r
- /// When 1, this bit will enable normal\r
- /// operation of the vmsw instruction.\r
-\r
- UINT64 EnableEnvNotification:1; /// Bit55, Enable external\r
- /// notification when the processor\r
- /// detects hardware errors caused\r
- /// by environmental factors that\r
- /// could cause loss of\r
- /// deterministic behavior of the\r
- /// processor. When 1, this bit will\r
- /// enable external notification,\r
- /// when 0 external notification is\r
- /// not provided. The type of\r
- /// external notification of these\r
- /// errors is processor-dependent. A\r
- /// loss of processor deterministic\r
- /// behavior is considered to have\r
- /// occurred if these\r
- /// environmentally induced errors\r
- /// cause the processor to deviate\r
- /// from its normal execution and\r
- /// eventually causes different\r
- /// behavior which can be observed\r
- /// at the processor bus pins.\r
- /// Processor errors that do not\r
- /// have this effects (i.e.,\r
- /// software induced machine checks)\r
- /// may or may not be promoted\r
- /// depending on the processor\r
- /// implementation.\r
-\r
- UINT64 DisableBinitWithTimeout:1; /// Bit56, Disable a BINIT on\r
- /// internal processor time-out.\r
- /// When 0, the processor may\r
- /// generate a BINIT on an\r
- /// internal processor time-out.\r
- /// When 1, the processor will not\r
- /// generate a BINIT on an\r
- /// internal processor time-out.\r
- /// The event is silently ignored.\r
-\r
- UINT64 DisableDPM:1; /// Bit57, Disable Dynamic Power Management\r
- /// (DPM). When 0, the hardware may reduce\r
- /// power consumption by removing the clock\r
- /// input from idle functional units. When 1,\r
- /// all functional units will receive clock\r
- /// input, even when idle.\r
-\r
- UINT64 DisableCoherency:1; /// Bit58, Disable Coherency. When 0,\r
- /// the processor uses normal coherency\r
- /// requests and responses. When 1, the\r
- /// processor answers all requests as if\r
- /// the line were not present.\r
-\r
- UINT64 DisableCache:1; /// Bit59, Disable Cache. When 0, the\r
- /// processor performs cast outs on\r
- /// cacheable pages and issues and responds\r
- /// to coherency requests normally. When 1,\r
- /// the processor performs a memory access\r
- /// for each reference regardless of cache\r
- /// contents and issues no coherence\r
- /// requests and responds as if the line\r
- /// were not present. Cache contents cannot\r
- /// be relied upon when the cache is\r
- /// disabled. WARNING: Semaphore\r
- /// instructions may not be atomic or may\r
- /// cause Unsupported Data Reference faults\r
- /// if caches are disabled.\r
-\r
- UINT64 EnableCmciPromotion:1; /// Bit60, Enable CMCI promotion When\r
- /// 1, Corrected Machine Check\r
- /// Interrupts (CMCI) are promoted to\r
- /// MCAs. They are also further\r
- /// promoted to BERR if bit 39, Enable\r
- /// MCA promotion, is also set and\r
- /// they are promoted to BINIT if bit\r
- /// 38, Enable MCA to BINIT promotion,\r
- /// is also set. This bit has no\r
- /// effect if MCA signalling is\r
- /// disabled (see\r
- /// PAL_BUS_GET/SET_FEATURES)\r
-\r
- UINT64 EnableMcaToBinitPromotion:1; /// Bit61, Enable MCA to BINIT\r
- /// promotion. When 1, machine\r
- /// check aborts (MCAs) are\r
- /// promoted to the Bus\r
- /// Initialization signal, and\r
- /// the BINIT pin is assert on\r
- /// each occurrence of an MCA.\r
- /// Setting this bit has no\r
- /// effect if BINIT signalling\r
- /// is disabled. (See\r
- /// PAL_BUS_GET/SET_FEATURES)\r
-\r
- UINT64 EnableMcaPromotion:1; /// Bit62, Enable MCA promotion. When\r
- /// 1, machine check aborts (MCAs) are\r
- /// promoted to the Bus Error signal,\r
- /// and the BERR pin is assert on each\r
- /// occurrence of an MCA. Setting this\r
- /// bit has no effect if BERR\r
- /// signalling is disabled. (See\r
- /// PAL_BUS_GET/SET_FEATURES)\r
+ UINT64 DisablePState:1; ///< Bit52, Disable P-states. When 1, the PAL\r
+ ///< P-state procedures (PAL_PSTATE_INFO,\r
+ ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will\r
+ ///< return with a status of -1\r
+ ///< (Unimplemented procedure).\r
+\r
+ UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA signaling\r
+ ///< on data-poisoning event\r
+ ///< detection. When 0, a CMCI\r
+ ///< will be signaled on error\r
+ ///< detection. When 1, an MCA\r
+ ///< will be signaled on error\r
+ ///< detection. If this feature\r
+ ///< is not supported, then the\r
+ ///< corresponding argument is\r
+ ///< ignored when calling\r
+ ///< PAL_PROC_SET_FEATURES. Note\r
+ ///< that the functionality of\r
+ ///< this bit is independent of\r
+ ///< the setting in bit 60\r
+ ///< (Enable CMCI promotion), and\r
+ ///< that the bit 60 setting does\r
+ ///< not affect CMCI signaling\r
+ ///< for data-poisoning related\r
+ ///< events. Volume 2: Processor\r
+ ///< Abstraction Layer 2:431\r
+ ///< PAL_PROC_GET_FEATURES\r
+\r
+ UINT64 EnableVmsw:1; ///< Bit54, Enable the use of the vmsw\r
+ ///< instruction. When 0, the vmsw instruction\r
+ ///< causes a Virtualization fault when\r
+ ///< executed at the most privileged level.\r
+ ///< When 1, this bit will enable normal\r
+ ///< operation of the vmsw instruction.\r
+\r
+ UINT64 EnableEnvNotification:1; ///< Bit55, Enable external\r
+ ///< notification when the processor\r
+ ///< detects hardware errors caused\r
+ ///< by environmental factors that\r
+ ///< could cause loss of\r
+ ///< deterministic behavior of the\r
+ ///< processor. When 1, this bit will\r
+ ///< enable external notification,\r
+ ///< when 0 external notification is\r
+ ///< not provided. The type of\r
+ ///< external notification of these\r
+ ///< errors is processor-dependent. A\r
+ ///< loss of processor deterministic\r
+ ///< behavior is considered to have\r
+ ///< occurred if these\r
+ ///< environmentally induced errors\r
+ ///< cause the processor to deviate\r
+ ///< from its normal execution and\r
+ ///< eventually causes different\r
+ ///< behavior which can be observed\r
+ ///< at the processor bus pins.\r
+ ///< Processor errors that do not\r
+ ///< have this effects (i.e.,\r
+ ///< software induced machine checks)\r
+ ///< may or may not be promoted\r
+ ///< depending on the processor\r
+ ///< implementation.\r
+\r
+ UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINIT on\r
+ ///< internal processor time-out.\r
+ ///< When 0, the processor may\r
+ ///< generate a BINIT on an\r
+ ///< internal processor time-out.\r
+ ///< When 1, the processor will not\r
+ ///< generate a BINIT on an\r
+ ///< internal processor time-out.\r
+ ///< The event is silently ignored.\r
+\r
+ UINT64 DisableDPM:1; ///< Bit57, Disable Dynamic Power Management\r
+ ///< (DPM). When 0, the hardware may reduce\r
+ ///< power consumption by removing the clock\r
+ ///< input from idle functional units. When 1,\r
+ ///< all functional units will receive clock\r
+ ///< input, even when idle.\r
+\r
+ UINT64 DisableCoherency:1; ///< Bit58, Disable Coherency. When 0,\r
+ ///< the processor uses normal coherency\r
+ ///< requests and responses. When 1, the\r
+ ///< processor answers all requests as if\r
+ ///< the line were not present.\r
+\r
+ UINT64 DisableCache:1; ///< Bit59, Disable Cache. When 0, the\r
+ ///< processor performs cast outs on\r
+ ///< cacheable pages and issues and responds\r
+ ///< to coherency requests normally. When 1,\r
+ ///< the processor performs a memory access\r
+ ///< for each reference regardless of cache\r
+ ///< contents and issues no coherence\r
+ ///< requests and responds as if the line\r
+ ///< were not present. Cache contents cannot\r
+ ///< be relied upon when the cache is\r
+ ///< disabled. WARNING: Semaphore\r
+ ///< instructions may not be atomic or may\r
+ ///< cause Unsupported Data Reference faults\r
+ ///< if caches are disabled.\r
+\r
+ UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI promotion When\r
+ ///< 1, Corrected Machine Check\r
+ ///< Interrupts (CMCI) are promoted to\r
+ ///< MCAs. They are also further\r
+ ///< promoted to BERR if bit 39, Enable\r
+ ///< MCA promotion, is also set and\r
+ ///< they are promoted to BINIT if bit\r
+ ///< 38, Enable MCA to BINIT promotion,\r
+ ///< is also set. This bit has no\r
+ ///< effect if MCA signalling is\r
+ ///< disabled (see\r
+ ///< PAL_BUS_GET/SET_FEATURES)\r
+\r
+ UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to BINIT\r
+ ///< promotion. When 1, machine\r
+ ///< check aborts (MCAs) are\r
+ ///< promoted to the Bus\r
+ ///< Initialization signal, and\r
+ ///< the BINIT pin is assert on\r
+ ///< each occurrence of an MCA.\r
+ ///< Setting this bit has no\r
+ ///< effect if BINIT signalling\r
+ ///< is disabled. (See\r
+ ///< PAL_BUS_GET/SET_FEATURES)\r
+\r
+ UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA promotion. When\r
+ ///< 1, machine check aborts (MCAs) are\r
+ ///< promoted to the Bus Error signal,\r
+ ///< and the BERR pin is assert on each\r
+ ///< occurrence of an MCA. Setting this\r
+ ///< bit has no effect if BERR\r
+ ///< signalling is disabled. (See\r
+ ///< PAL_BUS_GET/SET_FEATURES)\r
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