ArmPlatformPkg: remove old PL111/HdLcd driver code

Now that LcdGraphicsOutputDxe has been refactored, remove the old code
that is no longer used.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPlatformPkg/ArmPlatformPkg.dsc b/ArmPlatformPkg/ArmPlatformPkg.dsc
index 69ae9b67bc79e093f8f60957bf924911b6212193..82adb9ef8891b7ba1628ede2f8eb124c25c2774a 100644 (file)
--- a/ArmPlatformPkg/ArmPlatformPkg.dsc
+++ b/ArmPlatformPkg/ArmPlatformPkg.dsc
@@ -93,9 +93,7 @@
   PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf\r
 \r
 [Components.common]\r
   PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf\r
 \r
 [Components.common]\r

-  ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf\r

   ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf\r
   ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/LcdGraphicsOutputDxe.inf\r

-  ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r

   ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
   ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf\r
   ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
   ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
   ArmPlatformPkg/Drivers/PL061GpioDxe/PL061GpioDxe.inf\r
   ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c
deleted file mode 100644 (file)
index f5d7b53..0000000
--- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/** @file  Lcd.c\r
-\r
-  Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/LcdPlatformLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include "HdLcd.h"\r
-#include "LcdGraphicsOutputDxe.h"\r
-\r
-/**********************************************************************\r
- *\r
- *  This file contains all the bits of the Lcd that are\r
- *  platform independent.\r
- *\r
- **********************************************************************/\r
-\r
-EFI_STATUS\r
-LcdInitialize (\r
-  IN EFI_PHYSICAL_ADDRESS   VramBaseAddress\r
-  )\r
-{\r
-  // Disable the controller\r
-  MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);\r
-\r
-  // Disable all interrupts\r
-  MmioWrite32(HDLCD_REG_INT_MASK, 0);\r
-\r
-  // Define start of the VRAM. This never changes for any graphics mode\r
-  MmioWrite32(HDLCD_REG_FB_BASE, (UINT32) VramBaseAddress);\r
-\r
-  // Setup various registers that never change\r
-  MmioWrite32(HDLCD_REG_BUS_OPTIONS,  (4 << 8) | HDLCD_BURST_8);\r
-  MmioWrite32(HDLCD_REG_POLARITIES,   HDLCD_PXCLK_LOW | HDLCD_DATA_HIGH | HDLCD_DATEN_HIGH | HDLCD_HSYNC_LOW | HDLCD_VSYNC_HIGH);\r
-  MmioWrite32(HDLCD_REG_PIXEL_FORMAT, HDLCD_LITTLE_ENDIAN | HDLCD_4BYTES_PER_PIXEL);\r
-  MmioWrite32(HDLCD_REG_RED_SELECT,   (0 << 16 | 8 << 8 |  0));\r
-  MmioWrite32(HDLCD_REG_GREEN_SELECT, (0 << 16 | 8 << 8 |  8));\r
-  MmioWrite32(HDLCD_REG_BLUE_SELECT,  (0 << 16 | 8 << 8 | 16));\r
-\r
-  return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-LcdSetMode (\r
-  IN UINT32  ModeNumber\r
-  )\r
-{\r
-  EFI_STATUS        Status;\r
-  UINT32            HRes;\r
-  UINT32            HSync;\r
-  UINT32            HBackPorch;\r
-  UINT32            HFrontPorch;\r
-  UINT32            VRes;\r
-  UINT32            VSync;\r
-  UINT32            VBackPorch;\r
-  UINT32            VFrontPorch;\r
-  UINT32            BytesPerPixel;\r
-  LCD_BPP           LcdBpp;\r
-\r
-\r
-  // Set the video mode timings and other relevant information\r
-  Status = LcdPlatformGetTimings (ModeNumber,\r
-                                  &HRes,&HSync,&HBackPorch,&HFrontPorch,\r
-                                  &VRes,&VSync,&VBackPorch,&VFrontPorch);\r
-  ASSERT_EFI_ERROR (Status);\r
-  if (EFI_ERROR( Status )) {\r
-    return EFI_DEVICE_ERROR;\r
-  }\r
-\r
-  Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);\r
-  ASSERT_EFI_ERROR (Status);\r
-  if (EFI_ERROR( Status )) {\r
-    return EFI_DEVICE_ERROR;\r
-  }\r
-\r
-  BytesPerPixel = GetBytesPerPixel(LcdBpp);\r
-\r
-  // Disable the controller\r
-  MmioWrite32(HDLCD_REG_COMMAND, HDLCD_DISABLE);\r
-\r
-  // Update the frame buffer information with the new settings\r
-  MmioWrite32(HDLCD_REG_FB_LINE_LENGTH, HRes * BytesPerPixel);\r
-  MmioWrite32(HDLCD_REG_FB_LINE_PITCH,  HRes * BytesPerPixel);\r
-  MmioWrite32(HDLCD_REG_FB_LINE_COUNT,  VRes - 1);\r
-\r
-  // Set the vertical timing information\r
-  MmioWrite32(HDLCD_REG_V_SYNC,         VSync);\r
-  MmioWrite32(HDLCD_REG_V_BACK_PORCH,   VBackPorch);\r
-  MmioWrite32(HDLCD_REG_V_DATA,         VRes - 1);\r
-  MmioWrite32(HDLCD_REG_V_FRONT_PORCH,  VFrontPorch);\r
-\r
-  // Set the horizontal timing information\r
-  MmioWrite32(HDLCD_REG_H_SYNC,         HSync);\r
-  MmioWrite32(HDLCD_REG_H_BACK_PORCH,   HBackPorch);\r
-  MmioWrite32(HDLCD_REG_H_DATA,         HRes - 1);\r
-  MmioWrite32(HDLCD_REG_H_FRONT_PORCH,  HFrontPorch);\r
-\r
-  // Enable the controller\r
-  MmioWrite32(HDLCD_REG_COMMAND, HDLCD_ENABLE);\r
-\r
-  return EFI_SUCCESS;\r
-}\r
-\r
-VOID\r
-LcdShutdown (\r
-  VOID\r
-  )\r
-{\r
-  // Disable the controller\r
-  MmioWrite32 (HDLCD_REG_COMMAND, HDLCD_DISABLE);\r
-}\r
-\r
-EFI_STATUS\r
-LcdIdentify (\r
-  VOID\r
-  )\r
-{\r
-  return EFI_SUCCESS;\r
-}\r

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h
deleted file mode 100644 (file)
index 6df97a9..0000000
--- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcd.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/** @file  HDLcd.h\r
-\r
- Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution.  The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- **/\r
-\r
-#ifndef _HDLCD_H_\r
-#define _HDLCD_H_\r
-\r
-//\r
-// HDLCD Controller Register Offsets\r
-//\r
-\r
-#define HDLCD_REG_VERSION                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x000)\r
-#define HDLCD_REG_INT_RAWSTAT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x010)\r
-#define HDLCD_REG_INT_CLEAR               ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x014)\r
-#define HDLCD_REG_INT_MASK                ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x018)\r
-#define HDLCD_REG_INT_STATUS              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x01C)\r
-#define HDLCD_REG_FB_BASE                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x100)\r
-#define HDLCD_REG_FB_LINE_LENGTH          ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x104)\r
-#define HDLCD_REG_FB_LINE_COUNT           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x108)\r
-#define HDLCD_REG_FB_LINE_PITCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x10C)\r
-#define HDLCD_REG_BUS_OPTIONS             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x110)\r
-#define HDLCD_REG_V_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x200)\r
-#define HDLCD_REG_V_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x204)\r
-#define HDLCD_REG_V_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x208)\r
-#define HDLCD_REG_V_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x20C)\r
-#define HDLCD_REG_H_SYNC                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x210)\r
-#define HDLCD_REG_H_BACK_PORCH            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x214)\r
-#define HDLCD_REG_H_DATA                  ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x218)\r
-#define HDLCD_REG_H_FRONT_PORCH           ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x21C)\r
-#define HDLCD_REG_POLARITIES              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x220)\r
-#define HDLCD_REG_COMMAND                 ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x230)\r
-#define HDLCD_REG_PIXEL_FORMAT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x240)\r
-#define HDLCD_REG_RED_SELECT              ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x244)\r
-#define HDLCD_REG_GREEN_SELECT            ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x248)\r
-#define HDLCD_REG_BLUE_SELECT             ((UINTN)PcdGet32 (PcdArmHdLcdBase) + 0x24C)\r
-\r
-\r
-//\r
-// HDLCD Values of registers\r
-//\r
-\r
-// HDLCD Interrupt mask, clear and status register\r
-#define HDLCD_DMA_END                     BIT0    /* DMA has finished reading a frame */\r
-#define HDLCD_BUS_ERROR                   BIT1    /* DMA bus error */\r
-#define HDLCD_SYNC                        BIT2    /* Vertical sync */\r
-#define HDLCD_UNDERRUN                    BIT3    /* No Data available while DATAEN active */\r
-\r
-// CLCD_CONTROL Control register\r
-#define HDLCD_DISABLE                     0\r
-#define HDLCD_ENABLE                      BIT0\r
-\r
-// Bus Options\r
-#define HDLCD_BURST_1                     BIT0\r
-#define HDLCD_BURST_2                     BIT1\r
-#define HDLCD_BURST_4                     BIT2\r
-#define HDLCD_BURST_8                     BIT3\r
-#define HDLCD_BURST_16                    BIT4\r
-\r
-// Polarities - HIGH\r
-#define HDLCD_VSYNC_HIGH                  BIT0\r
-#define HDLCD_HSYNC_HIGH                  BIT1\r
-#define HDLCD_DATEN_HIGH                  BIT2\r
-#define HDLCD_DATA_HIGH                   BIT3\r
-#define HDLCD_PXCLK_HIGH                  BIT4\r
-// Polarities - LOW (for completion and for ease of understanding the hardware settings)\r
-#define HDLCD_VSYNC_LOW                   0\r
-#define HDLCD_HSYNC_LOW                   0\r
-#define HDLCD_DATEN_LOW                   0\r
-#define HDLCD_DATA_LOW                    0\r
-#define HDLCD_PXCLK_LOW                   0\r
-\r
-// Pixel Format\r
-#define HDLCD_LITTLE_ENDIAN              (0 << 31)\r
-#define HDLCD_BIG_ENDIAN                 (1 << 31)\r
-\r
-// Number of bytes per pixel\r
-#define HDLCD_4BYTES_PER_PIXEL           ((4 - 1) << 3)\r
-\r
-#endif /* _HDLCD_H_ */\r

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf
deleted file mode 100644 (file)
index 896fc58..0000000
--- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf
+++ /dev/null
@@ -1,62 +0,0 @@
-#/** @file\r
-#\r
-#  Component description file for HDLCD module\r
-#\r
-#  Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-#\r
-#  This program and the accompanying materials\r
-#  are licensed and made available under the terms and conditions of the BSD License\r
-#  which accompanies this distribution.  The full text of the license may be found at\r
-#  http://opensource.org/licenses/bsd-license.php\r
-#\r
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
-  INF_VERSION                    = 0x00010005\r
-  BASE_NAME                      = HdLcdGraphicsDxe\r
-  FILE_GUID                      = ce660500-824d-11e0-ac72-0002a5d5c51b\r
-  MODULE_TYPE                    = DXE_DRIVER\r
-  VERSION_STRING                 = 1.0\r
-  ENTRY_POINT                    = LcdGraphicsOutputDxeInitialize\r
-\r
-[Sources.common]\r
-  LcdGraphicsOutputDxe.c\r
-  LcdGraphicsOutputBlt.c\r
-  HdLcd.c\r
-\r
-[Packages]\r
-  MdePkg/MdePkg.dec\r
-  MdeModulePkg/MdeModulePkg.dec\r
-  ArmPkg/ArmPkg.dec\r
-  ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
-  ArmLib\r
-  UefiLib\r
-  BaseLib\r
-  DebugLib\r
-  TimerLib\r
-  UefiDriverEntryPoint\r
-  UefiBootServicesTableLib\r
-  IoLib\r
-  BaseMemoryLib\r
-  LcdPlatformLib\r
-\r
-[Protocols]\r
-  gEfiDevicePathProtocolGuid\r
-  gEfiGraphicsOutputProtocolGuid                # Produced\r
-  gEfiEdidDiscoveredProtocolGuid                # Produced\r
-  gEfiEdidActiveProtocolGuid                    # Produced\r
-  gEfiEdidOverrideProtocolGuid                  # Produced\r
-\r
-[FixedPcd]\r
-  gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase\r
-\r
-[FeaturePcd]\r
-  gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices\r
-\r
-[Depex]\r
-  gEfiCpuArchProtocolGuid\r

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c
deleted file mode 100644 (file)
index a9ce60c..0000000
--- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/** @file  PL111Lcd.c\r
-\r
-  Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-\r
-  This program and the accompanying materials\r
-  are licensed and made available under the terms and conditions of the BSD License\r
-  which accompanies this distribution.  The full text of the license may be found at\r
-  http://opensource.org/licenses/bsd-license.php\r
-\r
-  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/MemoryAllocationLib.h>\r
-\r
-#include "LcdGraphicsOutputDxe.h"\r
-#include "PL111Lcd.h"\r
-\r
-/**********************************************************************\r
- *\r
- *  This file contains all the bits of the PL111 that are\r
- *  platform independent.\r
- *\r
- **********************************************************************/\r
-\r
-EFI_STATUS\r
-LcdIdentify (\r
-  VOID\r
-  )\r
-{\r
-  DEBUG ((EFI_D_WARN, "Probing ID registers at 0x%lx for a PL111\n",\r
-    PL111_REG_CLCD_PERIPH_ID_0));\r
-\r
-  // Check if this is a PL111\r
-  if (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_0) == PL111_CLCD_PERIPH_ID_0 &&\r
-      MmioRead8 (PL111_REG_CLCD_PERIPH_ID_1) == PL111_CLCD_PERIPH_ID_1 &&\r
-     (MmioRead8 (PL111_REG_CLCD_PERIPH_ID_2) & 0xf) == PL111_CLCD_PERIPH_ID_2 &&\r
-      MmioRead8 (PL111_REG_CLCD_PERIPH_ID_3) == PL111_CLCD_PERIPH_ID_3 &&\r
-      MmioRead8 (PL111_REG_CLCD_P_CELL_ID_0) == PL111_CLCD_P_CELL_ID_0 &&\r
-      MmioRead8 (PL111_REG_CLCD_P_CELL_ID_1) == PL111_CLCD_P_CELL_ID_1 &&\r
-      MmioRead8 (PL111_REG_CLCD_P_CELL_ID_2) == PL111_CLCD_P_CELL_ID_2 &&\r
-      MmioRead8 (PL111_REG_CLCD_P_CELL_ID_3) == PL111_CLCD_P_CELL_ID_3) {\r
-    return EFI_SUCCESS;\r
-  }\r
-  return EFI_NOT_FOUND;\r
-}\r
-\r
-EFI_STATUS\r
-LcdInitialize (\r
-  IN EFI_PHYSICAL_ADDRESS   VramBaseAddress\r
-  )\r
-{\r
-  // Define start of the VRAM. This never changes for any graphics mode\r
-  MmioWrite32(PL111_REG_LCD_UP_BASE, (UINT32) VramBaseAddress);\r
-  MmioWrite32(PL111_REG_LCD_LP_BASE, 0); // We are not using a double buffer\r
-\r
-  // Disable all interrupts from the PL111\r
-  MmioWrite32(PL111_REG_LCD_IMSC, 0);\r
-\r
-  return EFI_SUCCESS;\r
-}\r
-\r
-EFI_STATUS\r
-LcdSetMode (\r
-  IN UINT32  ModeNumber\r
-  )\r
-{\r
-  EFI_STATUS        Status;\r
-  UINT32            HRes;\r
-  UINT32            HSync;\r
-  UINT32            HBackPorch;\r
-  UINT32            HFrontPorch;\r
-  UINT32            VRes;\r
-  UINT32            VSync;\r
-  UINT32            VBackPorch;\r
-  UINT32            VFrontPorch;\r
-  UINT32            LcdControl;\r
-  LCD_BPP           LcdBpp;\r
-\r
-  // Set the video mode timings and other relevant information\r
-  Status = LcdPlatformGetTimings (ModeNumber,\r
-                                  &HRes,&HSync,&HBackPorch,&HFrontPorch,\r
-                                  &VRes,&VSync,&VBackPorch,&VFrontPorch);\r
-  ASSERT_EFI_ERROR (Status);\r
-  if (EFI_ERROR( Status )) {\r
-    return EFI_DEVICE_ERROR;\r
-  }\r
-\r
-  Status = LcdPlatformGetBpp (ModeNumber,&LcdBpp);\r
-  ASSERT_EFI_ERROR (Status);\r
-  if (EFI_ERROR( Status )) {\r
-    return EFI_DEVICE_ERROR;\r
-  }\r
-\r
-  // Disable the CLCD_LcdEn bit\r
-  LcdControl = MmioRead32( PL111_REG_LCD_CONTROL);\r
-  MmioWrite32(PL111_REG_LCD_CONTROL,  LcdControl & ~1);\r
-\r
-  // Set Timings\r
-  MmioWrite32 (PL111_REG_LCD_TIMING_0, HOR_AXIS_PANEL(HBackPorch, HFrontPorch, HSync, HRes));\r
-  MmioWrite32 (PL111_REG_LCD_TIMING_1, VER_AXIS_PANEL(VBackPorch, VFrontPorch, VSync, VRes));\r
-  MmioWrite32 (PL111_REG_LCD_TIMING_2, CLK_SIG_POLARITY(HRes));\r
-  MmioWrite32 (PL111_REG_LCD_TIMING_3, 0);\r
-\r
-  // PL111_REG_LCD_CONTROL\r
-  LcdControl = PL111_CTRL_LCD_EN | PL111_CTRL_LCD_BPP(LcdBpp) | PL111_CTRL_LCD_TFT | PL111_CTRL_BGR;\r
-  MmioWrite32(PL111_REG_LCD_CONTROL,  LcdControl);\r
-\r
-  // Turn on power to the LCD Panel\r
-  LcdControl |= PL111_CTRL_LCD_PWR;\r
-  MmioWrite32(PL111_REG_LCD_CONTROL,  LcdControl);\r
-\r
-  return EFI_SUCCESS;\r
-}\r
-\r
-VOID\r
-LcdShutdown (\r
-  VOID\r
-  )\r
-{\r
-  // Disable the controller\r
-  MmioAnd32 (PL111_REG_LCD_CONTROL, ~PL111_CTRL_LCD_EN);\r
-}\r

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h
deleted file mode 100644 (file)
index 18e28af..0000000
--- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111Lcd.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/** @file  PL111Lcd.h\r
-\r
- Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution.  The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
- **/\r
-\r
-#ifndef _PL111LCD_H__\r
-#define _PL111LCD_H__\r
-\r
-/**********************************************************************\r
- *\r
- *  This header file contains all the bits of the PL111 that are\r
- *  platform independent.\r
- *\r
- **********************************************************************/\r
-\r
-// Controller Register Offsets\r
-#define PL111_REG_LCD_TIMING_0            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x000)\r
-#define PL111_REG_LCD_TIMING_1            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x004)\r
-#define PL111_REG_LCD_TIMING_2            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x008)\r
-#define PL111_REG_LCD_TIMING_3            ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x00C)\r
-#define PL111_REG_LCD_UP_BASE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x010)\r
-#define PL111_REG_LCD_LP_BASE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x014)\r
-#define PL111_REG_LCD_CONTROL             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x018)\r
-#define PL111_REG_LCD_IMSC                ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x01C)\r
-#define PL111_REG_LCD_RIS                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x020)\r
-#define PL111_REG_LCD_MIS                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x024)\r
-#define PL111_REG_LCD_ICR                 ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x028)\r
-#define PL111_REG_LCD_UP_CURR             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x02C)\r
-#define PL111_REG_LCD_LP_CURR             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x030)\r
-#define PL111_REG_LCD_PALETTE             ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0x200)\r
-\r
-// Identification Register Offsets\r
-#define PL111_REG_CLCD_PERIPH_ID_0        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE0)\r
-#define PL111_REG_CLCD_PERIPH_ID_1        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE4)\r
-#define PL111_REG_CLCD_PERIPH_ID_2        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFE8)\r
-#define PL111_REG_CLCD_PERIPH_ID_3        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFEC)\r
-#define PL111_REG_CLCD_P_CELL_ID_0        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF0)\r
-#define PL111_REG_CLCD_P_CELL_ID_1        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF4)\r
-#define PL111_REG_CLCD_P_CELL_ID_2        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFF8)\r
-#define PL111_REG_CLCD_P_CELL_ID_3        ((UINTN)PcdGet32 (PcdPL111LcdBase) + 0xFFC)\r
-\r
-#define PL111_CLCD_PERIPH_ID_0            0x11\r
-#define PL111_CLCD_PERIPH_ID_1            0x11\r
-#define PL111_CLCD_PERIPH_ID_2            0x04\r
-#define PL111_CLCD_PERIPH_ID_3            0x00\r
-#define PL111_CLCD_P_CELL_ID_0            0x0D\r
-#define PL111_CLCD_P_CELL_ID_1            0xF0\r
-#define PL111_CLCD_P_CELL_ID_2            0x05\r
-#define PL111_CLCD_P_CELL_ID_3            0xB1\r
-\r
-/**********************************************************************/\r
-\r
-// Register components (register bits)\r
-\r
-// This should make life easier to program specific settings in the different registers\r
-// by simplifying the setting up of the individual bits of each register\r
-// and then assembling the final register value.\r
-\r
-/**********************************************************************/\r
-\r
-// Register: PL111_REG_LCD_TIMING_0\r
-#define HOR_AXIS_PANEL(hbp,hfp,hsw,hor_res) (UINT32)(((UINT32)(hbp) << 24) | ((UINT32)(hfp) << 16) | ((UINT32)(hsw) << 8) | (((UINT32)((hor_res)/16)-1) << 2))\r
-\r
-// Register: PL111_REG_LCD_TIMING_1\r
-#define VER_AXIS_PANEL(vbp,vfp,vsw,ver_res) (UINT32)(((UINT32)(vbp) << 24) | ((UINT32)(vfp) << 16) | ((UINT32)(vsw) << 10) | ((ver_res)-1))\r
-\r
-// Register: PL111_REG_LCD_TIMING_2\r
-#define PL111_BIT_SHIFT_PCD_HI            27\r
-#define PL111_BIT_SHIFT_BCD               26\r
-#define PL111_BIT_SHIFT_CPL               16\r
-#define PL111_BIT_SHIFT_IOE               14\r
-#define PL111_BIT_SHIFT_IPC               13\r
-#define PL111_BIT_SHIFT_IHS               12\r
-#define PL111_BIT_SHIFT_IVS               11\r
-#define PL111_BIT_SHIFT_ACB               6\r
-#define PL111_BIT_SHIFT_CLKSEL            5\r
-#define PL111_BIT_SHIFT_PCD_LO            0\r
-\r
-#define PL111_BCD                         (1 << 26)\r
-#define PL111_IPC                         (1 << 13)\r
-#define PL111_IHS                         (1 << 12)\r
-#define PL111_IVS                         (1 << 11)\r
-\r
-#define CLK_SIG_POLARITY(hor_res)         (UINT32)(PL111_BCD | PL111_IPC | PL111_IHS | PL111_IVS | (((hor_res)-1) << 16))\r
-\r
-// Register: PL111_REG_LCD_TIMING_3\r
-#define PL111_BIT_SHIFT_LEE               16\r
-#define PL111_BIT_SHIFT_LED               0\r
-\r
-#define PL111_CTRL_WATERMARK              (1 << 16)\r
-#define PL111_CTRL_LCD_V_COMP             (1 << 12)\r
-#define PL111_CTRL_LCD_PWR                (1 << 11)\r
-#define PL111_CTRL_BEPO                   (1 << 10)\r
-#define PL111_CTRL_BEBO                   (1 << 9)\r
-#define PL111_CTRL_BGR                    (1 << 8)\r
-#define PL111_CTRL_LCD_DUAL               (1 << 7)\r
-#define PL111_CTRL_LCD_MONO_8             (1 << 6)\r
-#define PL111_CTRL_LCD_TFT                (1 << 5)\r
-#define PL111_CTRL_LCD_BW                 (1 << 4)\r
-#define PL111_CTRL_LCD_1BPP               (0 << 1)\r
-#define PL111_CTRL_LCD_2BPP               (1 << 1)\r
-#define PL111_CTRL_LCD_4BPP               (2 << 1)\r
-#define PL111_CTRL_LCD_8BPP               (3 << 1)\r
-#define PL111_CTRL_LCD_16BPP              (4 << 1)\r
-#define PL111_CTRL_LCD_24BPP              (5 << 1)\r
-#define PL111_CTRL_LCD_16BPP_565          (6 << 1)\r
-#define PL111_CTRL_LCD_12BPP_444          (7 << 1)\r
-#define PL111_CTRL_LCD_BPP(Bpp)           ((Bpp) << 1)\r
-#define PL111_CTRL_LCD_EN                 1\r
-\r
-/**********************************************************************/\r
-\r
-// Register: PL111_REG_LCD_TIMING_0\r
-#define PL111_LCD_TIMING_0_HBP(hbp)       (((hbp) & 0xFF) << 24)\r
-#define PL111_LCD_TIMING_0_HFP(hfp)       (((hfp) & 0xFF) << 16)\r
-#define PL111_LCD_TIMING_0_HSW(hsw)       (((hsw) & 0xFF) << 8)\r
-#define PL111_LCD_TIMING_0_PPL(ppl)       (((hsw) & 0x3F) << 2)\r
-\r
-// Register: PL111_REG_LCD_TIMING_1\r
-#define PL111_LCD_TIMING_1_VBP(vbp)       (((vbp) & 0xFF) << 24)\r
-#define PL111_LCD_TIMING_1_VFP(vfp)       (((vfp) & 0xFF) << 16)\r
-#define PL111_LCD_TIMING_1_VSW(vsw)       (((vsw) & 0x3F) << 10)\r
-#define PL111_LCD_TIMING_1_LPP(lpp)        ((lpp) & 0xFC)\r
-\r
-// Register: PL111_REG_LCD_TIMING_2\r
-#define PL111_BIT_MASK_PCD_HI             0xF8000000\r
-#define PL111_BIT_MASK_BCD                0x04000000\r
-#define PL111_BIT_MASK_CPL                0x03FF0000\r
-#define PL111_BIT_MASK_IOE                0x00004000\r
-#define PL111_BIT_MASK_IPC                0x00002000\r
-#define PL111_BIT_MASK_IHS                0x00001000\r
-#define PL111_BIT_MASK_IVS                0x00000800\r
-#define PL111_BIT_MASK_ACB                0x000007C0\r
-#define PL111_BIT_MASK_CLKSEL             0x00000020\r
-#define PL111_BIT_MASK_PCD_LO             0x0000001F\r
-\r
-// Register: PL111_REG_LCD_TIMING_3\r
-#define PL111_BIT_MASK_LEE                0x00010000\r
-#define PL111_BIT_MASK_LED                0x0000007F\r
-\r
-#endif /* _PL111LCD_H__ */\r

diff --git a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf b/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
deleted file mode 100644 (file)
index 39e42bc..0000000
--- a/ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf
+++ /dev/null
@@ -1,58 +0,0 @@
-#/** @file\r
-#\r
-#  Component description file for PL111LcdGraphicsOutputDxe module\r
-#\r
-#  Copyright (c) 2011-2012, ARM Ltd. All rights reserved.<BR>\r
-#  This program and the accompanying materials\r
-#  are licensed and made available under the terms and conditions of the BSD License\r
-#  which accompanies this distribution.  The full text of the license may be found at\r
-#  http://opensource.org/licenses/bsd-license.php\r
-#\r
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
-  INF_VERSION                    = 0x00010005\r
-  BASE_NAME                      = PL111LcdGraphicsDxe\r
-  FILE_GUID                      = 407B4008-BF5B-11DF-9547-CF16E0D72085\r
-  MODULE_TYPE                    = DXE_DRIVER\r
-  VERSION_STRING                 = 1.0\r
-  ENTRY_POINT                    = LcdGraphicsOutputDxeInitialize\r
-\r
-[Sources.common]\r
-  LcdGraphicsOutputDxe.c\r
-  LcdGraphicsOutputBlt.c\r
-  PL111Lcd.c\r
-\r
-[Packages]\r
-  MdePkg/MdePkg.dec\r
-  MdeModulePkg/MdeModulePkg.dec\r
-  ArmPkg/ArmPkg.dec\r
-  ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
-  ArmLib\r
-  UefiLib\r
-  BaseLib\r
-  DebugLib\r
-  TimerLib\r
-  UefiDriverEntryPoint\r
-  UefiBootServicesTableLib\r
-  IoLib\r
-  BaseMemoryLib\r
-  LcdPlatformLib\r
-\r
-[Protocols]\r
-  gEfiDevicePathProtocolGuid\r
-  gEfiGraphicsOutputProtocolGuid\r
-\r
-[FixedPcd]\r
-  gArmPlatformTokenSpaceGuid.PcdPL111LcdBase\r
-\r
-[FeaturePcd]\r
-  gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices\r
-\r
-[Depex]\r
-  gEfiCpuArchProtocolGuid\r