MdeModulePkg: Enable port power if port power control feature is supported by EHCI

signed-off-by: erictian
reviewed-by: li-elvin

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12725 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
index 77aba643ab8a5d6e1980b9a1d4506501ebf781d2..c141803c388071bab53b82cb7c7ade936e588abf 100644 (file)
--- a/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/Ehci.c
@@ -469,9 +469,12 @@ EhcSetRootHubPortFeature (
 \r
   case EfiUsbPortPower:\r
     //\r
-    // Not supported, ignore the operation\r
+    // Set port power bit when PPC is 1\r
     //\r
-    Status = EFI_SUCCESS;\r
+    if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {\r
+      State |= PORTSC_POWER;\r
+      EhcWriteOpReg (Ehc, Offset, State);\r
+    }\r
     break;\r
 \r
   case EfiUsbPortOwner:\r
@@ -598,6 +601,14 @@ EhcClearRootHubPortFeature (
     break;\r
 \r
   case EfiUsbPortPower:\r
+    //\r
+    // Clear port power bit when PPC is 1\r
+    //\r
+    if ((Ehc->HcCapParams & HCSP_PPC) == HCSP_PPC) {\r
+      State &= ~PORTSC_POWER;\r
+      EhcWriteOpReg (Ehc, Offset, State);\r
+    }\r
+    break;\r
   case EfiUsbPortSuspendChange:\r
   case EfiUsbPortResetChange:\r
     //\r

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
index a79bd48390af5e9f56d2a00b6653d450d7fdd082..252e3d5fa2dc1f0a9976f33899385afeb5ed6969 100644 (file)
--- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.c
@@ -2,7 +2,7 @@
 \r
   The EHCI register operation routines.\r
 \r
-Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -554,6 +554,7 @@ EhcInitHC (
   )\r
 {\r
   EFI_STATUS              Status;\r
+  UINT32                  Index;\r
 \r
   // This ASSERT crashes the BeagleBoard. There is some issue in the USB stack.\r
   // This ASSERT needs to be removed so the BeagleBoard will boot. When we fix\r
@@ -580,21 +581,29 @@ EhcInitHC (
   EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);\r
 \r
   //\r
-  // 2. Program periodic frame list, already done in EhcInitSched\r
-  // 3. Start the Host Controller\r
+  // 2. Start the Host Controller\r
   //\r
   EhcSetOpRegBit (Ehc, EHC_USBCMD_OFFSET, USBCMD_RUN);\r
 \r
   //\r
-  // 4. Set all ports routing to EHC\r
+  // 3. Power up all ports if EHCI has Port Power Control (PPC) support\r
   //\r
-  EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+  if (Ehc->HcStructParams & HCSP_PPC) {\r
+    for (Index = 0; Index < (UINT8) (Ehc->HcStructParams & HCSP_NPORTS); Index++) {\r
+      EhcSetOpRegBit (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), PORTSC_POWER);\r
+    }\r
+  }\r
 \r
   //\r
   // Wait roothub port power stable\r
   //\r
   gBS->Stall (EHC_ROOT_PORT_RECOVERY_STALL);\r
 \r
+  //\r
+  // 4. Set all ports routing to EHC\r
+  //\r
+  EhcSetOpRegBit (Ehc, EHC_CONFIG_FLAG_OFFSET, CONFIGFLAG_ROUTE_EHC);\r
+\r
   Status = EhcEnablePeriodSchd (Ehc, EHC_GENERIC_TIMEOUT);\r
 \r
   if (EFI_ERROR (Status)) {\r

diff --git a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
index 98c2915b45f2be497b9e26be98d5431d85548a73..d1f38d38f0e3d77521553dfd927ee5b84f965ae9 100644 (file)
--- a/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
+++ b/MdeModulePkg/Bus/Pci/EhciDxe/EhciReg.h
@@ -2,7 +2,7 @@
 \r
   This file contains the definination for host controller register operation routines.\r
 \r
-Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2007 - 2011, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -32,6 +32,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 // Capability register bit definition\r
 //\r
 #define HCSP_NPORTS             0x0F // Number of root hub port\r
+#define HCSP_PPC                0x10 // Port Power Control\r
 #define HCCP_64BIT              0x01 // 64-bit addressing capability\r
 \r
 //\r