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f25c0ae1 CLG |
1 | /* |
2 | * ASPEED SoC 2600 family | |
3 | * | |
4 | * Copyright (c) 2016-2019, IBM Corporation. | |
5 | * | |
6 | * This code is licensed under the GPL version 2 or later. See | |
7 | * the COPYING file in the top-level directory. | |
8 | */ | |
9 | ||
10 | #include "qemu/osdep.h" | |
11 | #include "qapi/error.h" | |
f25c0ae1 CLG |
12 | #include "hw/misc/unimp.h" |
13 | #include "hw/arm/aspeed_soc.h" | |
f25c0ae1 CLG |
14 | #include "qemu/module.h" |
15 | #include "qemu/error-report.h" | |
16 | #include "hw/i2c/aspeed_i2c.h" | |
17 | #include "net/net.h" | |
18 | #include "sysemu/sysemu.h" | |
d780d056 | 19 | #include "target/arm/cpu-qom.h" |
f25c0ae1 CLG |
20 | |
21 | #define ASPEED_SOC_IOMEM_SIZE 0x00200000 | |
d9e9cd59 | 22 | #define ASPEED_SOC_DPMCU_SIZE 0x00040000 |
f25c0ae1 CLG |
23 | |
24 | static const hwaddr aspeed_soc_ast2600_memmap[] = { | |
5aa281d7 | 25 | [ASPEED_DEV_SPI_BOOT] = ASPEED_SOC_SPI_BOOT_ADDR, |
347df6f8 | 26 | [ASPEED_DEV_SRAM] = 0x10000000, |
d9e9cd59 | 27 | [ASPEED_DEV_DPMCU] = 0x18000000, |
f25c0ae1 | 28 | /* 0x16000000 0x17FFFFFF : AHB BUS do LPC Bus bridge */ |
347df6f8 EH |
29 | [ASPEED_DEV_IOMEM] = 0x1E600000, |
30 | [ASPEED_DEV_PWM] = 0x1E610000, | |
31 | [ASPEED_DEV_FMC] = 0x1E620000, | |
32 | [ASPEED_DEV_SPI1] = 0x1E630000, | |
08048cbd | 33 | [ASPEED_DEV_SPI2] = 0x1E631000, |
347df6f8 EH |
34 | [ASPEED_DEV_EHCI1] = 0x1E6A1000, |
35 | [ASPEED_DEV_EHCI2] = 0x1E6A3000, | |
36 | [ASPEED_DEV_MII1] = 0x1E650000, | |
37 | [ASPEED_DEV_MII2] = 0x1E650008, | |
38 | [ASPEED_DEV_MII3] = 0x1E650010, | |
39 | [ASPEED_DEV_MII4] = 0x1E650018, | |
40 | [ASPEED_DEV_ETH1] = 0x1E660000, | |
41 | [ASPEED_DEV_ETH3] = 0x1E670000, | |
42 | [ASPEED_DEV_ETH2] = 0x1E680000, | |
43 | [ASPEED_DEV_ETH4] = 0x1E690000, | |
44 | [ASPEED_DEV_VIC] = 0x1E6C0000, | |
a3888d75 | 45 | [ASPEED_DEV_HACE] = 0x1E6D0000, |
347df6f8 EH |
46 | [ASPEED_DEV_SDMC] = 0x1E6E0000, |
47 | [ASPEED_DEV_SCU] = 0x1E6E2000, | |
48 | [ASPEED_DEV_XDMA] = 0x1E6E7000, | |
49 | [ASPEED_DEV_ADC] = 0x1E6E9000, | |
d9e9cd59 | 50 | [ASPEED_DEV_DP] = 0x1E6EB000, |
e1acf581 | 51 | [ASPEED_DEV_SBC] = 0x1E6F2000, |
fe31a2ec | 52 | [ASPEED_DEV_EMMC_BC] = 0x1E6f5000, |
347df6f8 EH |
53 | [ASPEED_DEV_VIDEO] = 0x1E700000, |
54 | [ASPEED_DEV_SDHCI] = 0x1E740000, | |
55 | [ASPEED_DEV_EMMC] = 0x1E750000, | |
56 | [ASPEED_DEV_GPIO] = 0x1E780000, | |
57 | [ASPEED_DEV_GPIO_1_8V] = 0x1E780800, | |
58 | [ASPEED_DEV_RTC] = 0x1E781000, | |
59 | [ASPEED_DEV_TIMER1] = 0x1E782000, | |
60 | [ASPEED_DEV_WDT] = 0x1E785000, | |
61 | [ASPEED_DEV_LPC] = 0x1E789000, | |
62 | [ASPEED_DEV_IBT] = 0x1E789140, | |
63 | [ASPEED_DEV_I2C] = 0x1E78A000, | |
55c57023 | 64 | [ASPEED_DEV_PECI] = 0x1E78B000, |
347df6f8 | 65 | [ASPEED_DEV_UART1] = 0x1E783000, |
ab5e8605 PD |
66 | [ASPEED_DEV_UART2] = 0x1E78D000, |
67 | [ASPEED_DEV_UART3] = 0x1E78E000, | |
68 | [ASPEED_DEV_UART4] = 0x1E78F000, | |
347df6f8 | 69 | [ASPEED_DEV_UART5] = 0x1E784000, |
ab5e8605 PD |
70 | [ASPEED_DEV_UART6] = 0x1E790000, |
71 | [ASPEED_DEV_UART7] = 0x1E790100, | |
72 | [ASPEED_DEV_UART8] = 0x1E790200, | |
73 | [ASPEED_DEV_UART9] = 0x1E790300, | |
74 | [ASPEED_DEV_UART10] = 0x1E790400, | |
75 | [ASPEED_DEV_UART11] = 0x1E790500, | |
76 | [ASPEED_DEV_UART12] = 0x1E790600, | |
77 | [ASPEED_DEV_UART13] = 0x1E790700, | |
347df6f8 | 78 | [ASPEED_DEV_VUART] = 0x1E787000, |
3fd941f3 NP |
79 | [ASPEED_DEV_FSI1] = 0x1E79B000, |
80 | [ASPEED_DEV_FSI2] = 0x1E79B100, | |
3222165d | 81 | [ASPEED_DEV_I3C] = 0x1E7A0000, |
347df6f8 | 82 | [ASPEED_DEV_SDRAM] = 0x80000000, |
f25c0ae1 CLG |
83 | }; |
84 | ||
85 | #define ASPEED_A7MPCORE_ADDR 0x40460000 | |
86 | ||
b151de69 | 87 | #define AST2600_MAX_IRQ 197 |
f25c0ae1 | 88 | |
a29e3e12 | 89 | /* Shared Peripheral Interrupt values below are offset by -32 from datasheet */ |
f25c0ae1 | 90 | static const int aspeed_soc_ast2600_irqmap[] = { |
347df6f8 EH |
91 | [ASPEED_DEV_UART1] = 47, |
92 | [ASPEED_DEV_UART2] = 48, | |
93 | [ASPEED_DEV_UART3] = 49, | |
94 | [ASPEED_DEV_UART4] = 50, | |
95 | [ASPEED_DEV_UART5] = 8, | |
ab5e8605 PD |
96 | [ASPEED_DEV_UART6] = 57, |
97 | [ASPEED_DEV_UART7] = 58, | |
98 | [ASPEED_DEV_UART8] = 59, | |
99 | [ASPEED_DEV_UART9] = 60, | |
100 | [ASPEED_DEV_UART10] = 61, | |
101 | [ASPEED_DEV_UART11] = 62, | |
102 | [ASPEED_DEV_UART12] = 63, | |
103 | [ASPEED_DEV_UART13] = 64, | |
347df6f8 EH |
104 | [ASPEED_DEV_VUART] = 8, |
105 | [ASPEED_DEV_FMC] = 39, | |
106 | [ASPEED_DEV_SDMC] = 0, | |
107 | [ASPEED_DEV_SCU] = 12, | |
108 | [ASPEED_DEV_ADC] = 78, | |
109 | [ASPEED_DEV_XDMA] = 6, | |
110 | [ASPEED_DEV_SDHCI] = 43, | |
111 | [ASPEED_DEV_EHCI1] = 5, | |
112 | [ASPEED_DEV_EHCI2] = 9, | |
113 | [ASPEED_DEV_EMMC] = 15, | |
114 | [ASPEED_DEV_GPIO] = 40, | |
115 | [ASPEED_DEV_GPIO_1_8V] = 11, | |
116 | [ASPEED_DEV_RTC] = 13, | |
117 | [ASPEED_DEV_TIMER1] = 16, | |
118 | [ASPEED_DEV_TIMER2] = 17, | |
119 | [ASPEED_DEV_TIMER3] = 18, | |
120 | [ASPEED_DEV_TIMER4] = 19, | |
121 | [ASPEED_DEV_TIMER5] = 20, | |
122 | [ASPEED_DEV_TIMER6] = 21, | |
123 | [ASPEED_DEV_TIMER7] = 22, | |
124 | [ASPEED_DEV_TIMER8] = 23, | |
125 | [ASPEED_DEV_WDT] = 24, | |
126 | [ASPEED_DEV_PWM] = 44, | |
127 | [ASPEED_DEV_LPC] = 35, | |
6820588e | 128 | [ASPEED_DEV_IBT] = 143, |
347df6f8 | 129 | [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ |
55c57023 | 130 | [ASPEED_DEV_PECI] = 38, |
347df6f8 EH |
131 | [ASPEED_DEV_ETH1] = 2, |
132 | [ASPEED_DEV_ETH2] = 3, | |
a3888d75 | 133 | [ASPEED_DEV_HACE] = 4, |
347df6f8 EH |
134 | [ASPEED_DEV_ETH3] = 32, |
135 | [ASPEED_DEV_ETH4] = 33, | |
c59f781e | 136 | [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ |
d9e9cd59 | 137 | [ASPEED_DEV_DP] = 62, |
3fd941f3 NP |
138 | [ASPEED_DEV_FSI1] = 100, |
139 | [ASPEED_DEV_FSI2] = 101, | |
3222165d | 140 | [ASPEED_DEV_I3C] = 102, /* 102 -> 107 */ |
f25c0ae1 CLG |
141 | }; |
142 | ||
699db715 | 143 | static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) |
f25c0ae1 | 144 | { |
c17fc025 | 145 | Aspeed2600SoCState *a = ASPEED2600_SOC(s); |
f25c0ae1 CLG |
146 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); |
147 | ||
c17fc025 | 148 | return qdev_get_gpio_in(DEVICE(&a->a7mpcore), sc->irqmap[dev]); |
f25c0ae1 CLG |
149 | } |
150 | ||
151 | static void aspeed_soc_ast2600_init(Object *obj) | |
152 | { | |
c17fc025 | 153 | Aspeed2600SoCState *a = ASPEED2600_SOC(obj); |
f25c0ae1 CLG |
154 | AspeedSoCState *s = ASPEED_SOC(obj); |
155 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
156 | int i; | |
157 | char socname[8]; | |
158 | char typename[64]; | |
159 | ||
160 | if (sscanf(sc->name, "%7s", socname) != 1) { | |
161 | g_assert_not_reached(); | |
162 | } | |
163 | ||
164 | for (i = 0; i < sc->num_cpus; i++) { | |
d815649c PMD |
165 | object_initialize_child(obj, "cpu[*]", &a->cpu[i], |
166 | aspeed_soc_cpu_type(sc)); | |
f25c0ae1 CLG |
167 | } |
168 | ||
169 | snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); | |
db873cc5 | 170 | object_initialize_child(obj, "scu", &s->scu, typename); |
f25c0ae1 CLG |
171 | qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", |
172 | sc->silicon_rev); | |
173 | object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), | |
d2623129 | 174 | "hw-strap1"); |
f25c0ae1 | 175 | object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu), |
d2623129 | 176 | "hw-strap2"); |
f25c0ae1 | 177 | object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu), |
d2623129 | 178 | "hw-prot-key"); |
f25c0ae1 | 179 | |
c17fc025 | 180 | object_initialize_child(obj, "a7mpcore", &a->a7mpcore, |
db873cc5 | 181 | TYPE_A15MPCORE_PRIV); |
f25c0ae1 | 182 | |
db873cc5 | 183 | object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC); |
f25c0ae1 CLG |
184 | |
185 | snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname); | |
db873cc5 | 186 | object_initialize_child(obj, "timerctrl", &s->timerctrl, typename); |
f25c0ae1 | 187 | |
199fd623 AJ |
188 | snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname); |
189 | object_initialize_child(obj, "adc", &s->adc, typename); | |
190 | ||
f25c0ae1 | 191 | snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname); |
db873cc5 | 192 | object_initialize_child(obj, "i2c", &s->i2c, typename); |
f25c0ae1 | 193 | |
55c57023 PD |
194 | object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); |
195 | ||
f25c0ae1 | 196 | snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); |
db873cc5 | 197 | object_initialize_child(obj, "fmc", &s->fmc, typename); |
f25c0ae1 CLG |
198 | |
199 | for (i = 0; i < sc->spis_num; i++) { | |
200 | snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); | |
db873cc5 | 201 | object_initialize_child(obj, "spi[*]", &s->spi[i], typename); |
f25c0ae1 CLG |
202 | } |
203 | ||
917940ce | 204 | for (i = 0; i < sc->ehcis_num; i++) { |
db873cc5 MA |
205 | object_initialize_child(obj, "ehci[*]", &s->ehci[i], |
206 | TYPE_PLATFORM_EHCI); | |
917940ce GR |
207 | } |
208 | ||
f25c0ae1 | 209 | snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname); |
db873cc5 | 210 | object_initialize_child(obj, "sdmc", &s->sdmc, typename); |
f25c0ae1 | 211 | object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc), |
d2623129 | 212 | "ram-size"); |
f25c0ae1 CLG |
213 | |
214 | for (i = 0; i < sc->wdts_num; i++) { | |
215 | snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); | |
db873cc5 | 216 | object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); |
f25c0ae1 CLG |
217 | } |
218 | ||
d300db02 | 219 | for (i = 0; i < sc->macs_num; i++) { |
db873cc5 MA |
220 | object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i], |
221 | TYPE_FTGMAC100); | |
289251b0 | 222 | |
db873cc5 | 223 | object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); |
f25c0ae1 CLG |
224 | } |
225 | ||
d2b3eaef PD |
226 | for (i = 0; i < sc->uarts_num; i++) { |
227 | object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM); | |
228 | } | |
229 | ||
8efbee28 CLG |
230 | snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); |
231 | object_initialize_child(obj, "xdma", &s->xdma, typename); | |
f25c0ae1 CLG |
232 | |
233 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); | |
db873cc5 | 234 | object_initialize_child(obj, "gpio", &s->gpio, typename); |
f25c0ae1 CLG |
235 | |
236 | snprintf(typename, sizeof(typename), "aspeed.gpio-%s-1_8v", socname); | |
db873cc5 | 237 | object_initialize_child(obj, "gpio_1_8v", &s->gpio_1_8v, typename); |
f25c0ae1 | 238 | |
db873cc5 MA |
239 | object_initialize_child(obj, "sd-controller", &s->sdhci, |
240 | TYPE_ASPEED_SDHCI); | |
f25c0ae1 | 241 | |
5325cc34 | 242 | object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort); |
0e2c24c6 | 243 | |
f25c0ae1 CLG |
244 | /* Init sd card slot class here so that they're under the correct parent */ |
245 | for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) { | |
7089e0cc MA |
246 | object_initialize_child(obj, "sd-controller.sdhci[*]", |
247 | &s->sdhci.slots[i], TYPE_SYSBUS_SDHCI); | |
f25c0ae1 | 248 | } |
a29e3e12 | 249 | |
db873cc5 MA |
250 | object_initialize_child(obj, "emmc-controller", &s->emmc, |
251 | TYPE_ASPEED_SDHCI); | |
a29e3e12 | 252 | |
5325cc34 | 253 | object_property_set_int(OBJECT(&s->emmc), "num-slots", 1, &error_abort); |
a29e3e12 | 254 | |
7089e0cc MA |
255 | object_initialize_child(obj, "emmc-controller.sdhci", &s->emmc.slots[0], |
256 | TYPE_SYSBUS_SDHCI); | |
2ecf1726 CLG |
257 | |
258 | object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); | |
a3888d75 JS |
259 | |
260 | snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); | |
261 | object_initialize_child(obj, "hace", &s->hace, typename); | |
3222165d TL |
262 | |
263 | object_initialize_child(obj, "i3c", &s->i3c, TYPE_ASPEED_I3C); | |
e1acf581 JS |
264 | |
265 | object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_SBC); | |
80beb085 PD |
266 | |
267 | object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE); | |
268 | object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE); | |
269 | object_initialize_child(obj, "dpmcu", &s->dpmcu, TYPE_UNIMPLEMENTED_DEVICE); | |
270 | object_initialize_child(obj, "emmc-boot-controller", | |
271 | &s->emmc_boot_controller, | |
272 | TYPE_UNIMPLEMENTED_DEVICE); | |
3fd941f3 NP |
273 | |
274 | for (i = 0; i < ASPEED_FSI_NUM; i++) { | |
275 | object_initialize_child(obj, "fsi[*]", &s->fsi[i], TYPE_ASPEED_APB2OPB); | |
276 | } | |
f25c0ae1 CLG |
277 | } |
278 | ||
279 | /* | |
280 | * ASPEED ast2600 has 0xf as cluster ID | |
281 | * | |
932a8d1f | 282 | * https://developer.arm.com/documentation/ddi0388/e/the-system-control-coprocessors/summary-of-system-control-coprocessor-registers/multiprocessor-affinity-register |
f25c0ae1 CLG |
283 | */ |
284 | static uint64_t aspeed_calc_affinity(int cpu) | |
285 | { | |
286 | return (0xf << ARM_AFF1_SHIFT) | cpu; | |
287 | } | |
288 | ||
289 | static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) | |
290 | { | |
291 | int i; | |
c17fc025 | 292 | Aspeed2600SoCState *a = ASPEED2600_SOC(dev); |
f25c0ae1 CLG |
293 | AspeedSoCState *s = ASPEED_SOC(dev); |
294 | AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); | |
f25c0ae1 | 295 | qemu_irq irq; |
72a7c473 | 296 | g_autofree char *sram_name = NULL; |
f25c0ae1 | 297 | |
5aa281d7 CLG |
298 | /* Default boot region (SPI memory or ROMs) */ |
299 | memory_region_init(&s->spi_boot_container, OBJECT(s), | |
300 | "aspeed.spi_boot_container", 0x10000000); | |
301 | memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], | |
302 | &s->spi_boot_container); | |
303 | ||
f25c0ae1 | 304 | /* IO space */ |
80beb085 PD |
305 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io", |
306 | sc->memmap[ASPEED_DEV_IOMEM], | |
307 | ASPEED_SOC_IOMEM_SIZE); | |
f25c0ae1 | 308 | |
514bcf6f | 309 | /* Video engine stub */ |
80beb085 PD |
310 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video", |
311 | sc->memmap[ASPEED_DEV_VIDEO], 0x1000); | |
514bcf6f | 312 | |
fe31a2ec | 313 | /* eMMC Boot Controller stub */ |
80beb085 PD |
314 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->emmc_boot_controller), |
315 | "aspeed.emmc-boot-controller", | |
316 | sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); | |
fe31a2ec | 317 | |
f25c0ae1 | 318 | /* CPU */ |
b7f1a0cb | 319 | for (i = 0; i < sc->num_cpus; i++) { |
b7f1a0cb | 320 | if (sc->num_cpus > 1) { |
c17fc025 | 321 | object_property_set_int(OBJECT(&a->cpu[i]), "reset-cbar", |
5325cc34 | 322 | ASPEED_A7MPCORE_ADDR, &error_abort); |
f25c0ae1 | 323 | } |
c17fc025 | 324 | object_property_set_int(OBJECT(&a->cpu[i]), "mp-affinity", |
5325cc34 | 325 | aspeed_calc_affinity(i), &error_abort); |
f25c0ae1 | 326 | |
c17fc025 | 327 | object_property_set_int(OBJECT(&a->cpu[i]), "cntfrq", 1125000000, |
058d0955 | 328 | &error_abort); |
c17fc025 | 329 | object_property_set_bool(OBJECT(&a->cpu[i]), "neon", false, |
e5c1b489 | 330 | &error_abort); |
c17fc025 | 331 | object_property_set_bool(OBJECT(&a->cpu[i]), "vfp-d32", false, |
42bea956 | 332 | &error_abort); |
c17fc025 | 333 | object_property_set_link(OBJECT(&a->cpu[i]), "memory", |
4dd9d554 | 334 | OBJECT(s->memory), &error_abort); |
058d0955 | 335 | |
c17fc025 | 336 | if (!qdev_realize(DEVICE(&a->cpu[i]), NULL, errp)) { |
f25c0ae1 CLG |
337 | return; |
338 | } | |
339 | } | |
340 | ||
341 | /* A7MPCORE */ | |
c17fc025 | 342 | object_property_set_int(OBJECT(&a->a7mpcore), "num-cpu", sc->num_cpus, |
f25c0ae1 | 343 | &error_abort); |
c17fc025 | 344 | object_property_set_int(OBJECT(&a->a7mpcore), "num-irq", |
957ad79f | 345 | ROUND_UP(AST2600_MAX_IRQ + GIC_INTERNAL, 32), |
5325cc34 | 346 | &error_abort); |
f25c0ae1 | 347 | |
c17fc025 PMD |
348 | sysbus_realize(SYS_BUS_DEVICE(&a->a7mpcore), &error_abort); |
349 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->a7mpcore), 0, ASPEED_A7MPCORE_ADDR); | |
f25c0ae1 | 350 | |
b7f1a0cb | 351 | for (i = 0; i < sc->num_cpus; i++) { |
c17fc025 PMD |
352 | SysBusDevice *sbd = SYS_BUS_DEVICE(&a->a7mpcore); |
353 | DeviceState *d = DEVICE(&a->cpu[i]); | |
f25c0ae1 CLG |
354 | |
355 | irq = qdev_get_gpio_in(d, ARM_CPU_IRQ); | |
356 | sysbus_connect_irq(sbd, i, irq); | |
357 | irq = qdev_get_gpio_in(d, ARM_CPU_FIQ); | |
b7f1a0cb | 358 | sysbus_connect_irq(sbd, i + sc->num_cpus, irq); |
f25c0ae1 | 359 | irq = qdev_get_gpio_in(d, ARM_CPU_VIRQ); |
b7f1a0cb | 360 | sysbus_connect_irq(sbd, i + 2 * sc->num_cpus, irq); |
f25c0ae1 | 361 | irq = qdev_get_gpio_in(d, ARM_CPU_VFIQ); |
b7f1a0cb | 362 | sysbus_connect_irq(sbd, i + 3 * sc->num_cpus, irq); |
f25c0ae1 CLG |
363 | } |
364 | ||
365 | /* SRAM */ | |
c17fc025 | 366 | sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&a->cpu[0])->cpu_index); |
2198f5f0 PMD |
367 | if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, |
368 | errp)) { | |
f25c0ae1 CLG |
369 | return; |
370 | } | |
4dd9d554 | 371 | memory_region_add_subregion(s->memory, |
347df6f8 | 372 | sc->memmap[ASPEED_DEV_SRAM], &s->sram); |
f25c0ae1 | 373 | |
d9e9cd59 | 374 | /* DPMCU */ |
80beb085 PD |
375 | aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->dpmcu), "aspeed.dpmcu", |
376 | sc->memmap[ASPEED_DEV_DPMCU], | |
377 | ASPEED_SOC_DPMCU_SIZE); | |
d9e9cd59 | 378 | |
f25c0ae1 | 379 | /* SCU */ |
668f62ec | 380 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { |
f25c0ae1 CLG |
381 | return; |
382 | } | |
5bfcbda7 | 383 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); |
f25c0ae1 CLG |
384 | |
385 | /* RTC */ | |
668f62ec | 386 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) { |
f25c0ae1 CLG |
387 | return; |
388 | } | |
5bfcbda7 | 389 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); |
f25c0ae1 | 390 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0, |
347df6f8 | 391 | aspeed_soc_get_irq(s, ASPEED_DEV_RTC)); |
f25c0ae1 CLG |
392 | |
393 | /* Timer */ | |
5325cc34 MA |
394 | object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), |
395 | &error_abort); | |
668f62ec | 396 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { |
f25c0ae1 CLG |
397 | return; |
398 | } | |
5bfcbda7 | 399 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0, |
347df6f8 | 400 | sc->memmap[ASPEED_DEV_TIMER1]); |
f25c0ae1 | 401 | for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) { |
e8874c06 | 402 | irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i); |
f25c0ae1 CLG |
403 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq); |
404 | } | |
405 | ||
199fd623 AJ |
406 | /* ADC */ |
407 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { | |
408 | return; | |
409 | } | |
5bfcbda7 | 410 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); |
199fd623 AJ |
411 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, |
412 | aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); | |
413 | ||
470253b6 | 414 | /* UART */ |
d2b3eaef PD |
415 | if (!aspeed_soc_uart_realize(s, errp)) { |
416 | return; | |
417 | } | |
f25c0ae1 CLG |
418 | |
419 | /* I2C */ | |
5325cc34 | 420 | object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), |
c24d9716 | 421 | &error_abort); |
668f62ec | 422 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { |
f25c0ae1 CLG |
423 | return; |
424 | } | |
5bfcbda7 | 425 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); |
f25c0ae1 | 426 | for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { |
c17fc025 | 427 | irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
e8874c06 | 428 | sc->irqmap[ASPEED_DEV_I2C] + i); |
60261038 CLG |
429 | /* The AST2600 I2C controller has one IRQ per bus. */ |
430 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); | |
f25c0ae1 CLG |
431 | } |
432 | ||
55c57023 PD |
433 | /* PECI */ |
434 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { | |
435 | return; | |
436 | } | |
437 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0, | |
438 | sc->memmap[ASPEED_DEV_PECI]); | |
439 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, | |
440 | aspeed_soc_get_irq(s, ASPEED_DEV_PECI)); | |
441 | ||
f25c0ae1 | 442 | /* FMC, The number of CS is set at the board level */ |
5325cc34 | 443 | object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), |
c24d9716 | 444 | &error_abort); |
668f62ec | 445 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { |
f25c0ae1 CLG |
446 | return; |
447 | } | |
5bfcbda7 PD |
448 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); |
449 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1, | |
30b6852c | 450 | ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base); |
f25c0ae1 | 451 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0, |
347df6f8 | 452 | aspeed_soc_get_irq(s, ASPEED_DEV_FMC)); |
f25c0ae1 | 453 | |
5aa281d7 CLG |
454 | /* Set up an alias on the FMC CE0 region (boot default) */ |
455 | MemoryRegion *fmc0_mmio = &s->fmc.flashes[0].mmio; | |
456 | memory_region_init_alias(&s->spi_boot, OBJECT(s), "aspeed.spi_boot", | |
457 | fmc0_mmio, 0, memory_region_size(fmc0_mmio)); | |
458 | memory_region_add_subregion(&s->spi_boot_container, 0x0, &s->spi_boot); | |
459 | ||
f25c0ae1 CLG |
460 | /* SPI */ |
461 | for (i = 0; i < sc->spis_num; i++) { | |
5325cc34 MA |
462 | object_property_set_link(OBJECT(&s->spi[i]), "dram", |
463 | OBJECT(s->dram_mr), &error_abort); | |
668f62ec | 464 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { |
f25c0ae1 CLG |
465 | return; |
466 | } | |
5bfcbda7 | 467 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0, |
347df6f8 | 468 | sc->memmap[ASPEED_DEV_SPI1 + i]); |
5bfcbda7 | 469 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1, |
30b6852c | 470 | ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base); |
f25c0ae1 CLG |
471 | } |
472 | ||
917940ce GR |
473 | /* EHCI */ |
474 | for (i = 0; i < sc->ehcis_num; i++) { | |
668f62ec | 475 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) { |
917940ce GR |
476 | return; |
477 | } | |
5bfcbda7 | 478 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 479 | sc->memmap[ASPEED_DEV_EHCI1 + i]); |
917940ce | 480 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, |
347df6f8 | 481 | aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i)); |
917940ce GR |
482 | } |
483 | ||
f25c0ae1 | 484 | /* SDMC - SDRAM Memory Controller */ |
668f62ec | 485 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) { |
f25c0ae1 CLG |
486 | return; |
487 | } | |
5bfcbda7 PD |
488 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0, |
489 | sc->memmap[ASPEED_DEV_SDMC]); | |
f25c0ae1 CLG |
490 | |
491 | /* Watch dog */ | |
492 | for (i = 0; i < sc->wdts_num; i++) { | |
493 | AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]); | |
6fdb4381 | 494 | hwaddr wdt_offset = sc->memmap[ASPEED_DEV_WDT] + i * awc->iosize; |
f25c0ae1 | 495 | |
5325cc34 MA |
496 | object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu), |
497 | &error_abort); | |
668f62ec | 498 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { |
f25c0ae1 CLG |
499 | return; |
500 | } | |
6fdb4381 | 501 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offset); |
f25c0ae1 CLG |
502 | } |
503 | ||
346160cb CLG |
504 | /* RAM */ |
505 | if (!aspeed_soc_dram_init(s, errp)) { | |
506 | return; | |
507 | } | |
508 | ||
f25c0ae1 | 509 | /* Net */ |
d3bad7e7 | 510 | for (i = 0; i < sc->macs_num; i++) { |
5325cc34 | 511 | object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true, |
2255f6b7 | 512 | &error_abort); |
668f62ec | 513 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) { |
123327d1 | 514 | return; |
f25c0ae1 | 515 | } |
5bfcbda7 | 516 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 517 | sc->memmap[ASPEED_DEV_ETH1 + i]); |
f25c0ae1 | 518 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0, |
347df6f8 | 519 | aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i)); |
289251b0 | 520 | |
5325cc34 MA |
521 | object_property_set_link(OBJECT(&s->mii[i]), "nic", |
522 | OBJECT(&s->ftgmac100[i]), &error_abort); | |
668f62ec | 523 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->mii[i]), errp)) { |
289251b0 CLG |
524 | return; |
525 | } | |
526 | ||
5bfcbda7 | 527 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->mii[i]), 0, |
347df6f8 | 528 | sc->memmap[ASPEED_DEV_MII1 + i]); |
f25c0ae1 CLG |
529 | } |
530 | ||
531 | /* XDMA */ | |
668f62ec | 532 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) { |
f25c0ae1 CLG |
533 | return; |
534 | } | |
5bfcbda7 | 535 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 536 | sc->memmap[ASPEED_DEV_XDMA]); |
f25c0ae1 | 537 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, |
347df6f8 | 538 | aspeed_soc_get_irq(s, ASPEED_DEV_XDMA)); |
f25c0ae1 CLG |
539 | |
540 | /* GPIO */ | |
668f62ec | 541 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { |
f25c0ae1 CLG |
542 | return; |
543 | } | |
5bfcbda7 | 544 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); |
f25c0ae1 | 545 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, |
347df6f8 | 546 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); |
f25c0ae1 | 547 | |
668f62ec | 548 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio_1_8v), errp)) { |
f25c0ae1 CLG |
549 | return; |
550 | } | |
5bfcbda7 | 551 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
347df6f8 | 552 | sc->memmap[ASPEED_DEV_GPIO_1_8V]); |
f25c0ae1 | 553 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio_1_8v), 0, |
347df6f8 | 554 | aspeed_soc_get_irq(s, ASPEED_DEV_GPIO_1_8V)); |
f25c0ae1 CLG |
555 | |
556 | /* SDHCI */ | |
668f62ec | 557 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) { |
f25c0ae1 CLG |
558 | return; |
559 | } | |
5bfcbda7 | 560 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 561 | sc->memmap[ASPEED_DEV_SDHCI]); |
f25c0ae1 | 562 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, |
347df6f8 | 563 | aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI)); |
a29e3e12 AJ |
564 | |
565 | /* eMMC */ | |
668f62ec | 566 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->emmc), errp)) { |
a29e3e12 AJ |
567 | return; |
568 | } | |
5bfcbda7 PD |
569 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->emmc), 0, |
570 | sc->memmap[ASPEED_DEV_EMMC]); | |
a29e3e12 | 571 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->emmc), 0, |
347df6f8 | 572 | aspeed_soc_get_irq(s, ASPEED_DEV_EMMC)); |
2ecf1726 CLG |
573 | |
574 | /* LPC */ | |
575 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { | |
576 | return; | |
577 | } | |
5bfcbda7 | 578 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); |
c59f781e AJ |
579 | |
580 | /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ | |
2ecf1726 CLG |
581 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, |
582 | aspeed_soc_get_irq(s, ASPEED_DEV_LPC)); | |
c59f781e AJ |
583 | |
584 | /* | |
585 | * On the AST2600 LPC subdevice IRQs are connected straight to the GIC. | |
586 | * | |
587 | * LPC subdevice IRQ sources are offset from 1 because the LPC model caters | |
588 | * to the AST2400 and AST2500. SoCs before the AST2600 have one LPC IRQ | |
589 | * shared across the subdevices, and the shared IRQ output to the VIC is at | |
590 | * offset 0. | |
591 | */ | |
592 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, | |
c17fc025 | 593 | qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
c59f781e AJ |
594 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_1)); |
595 | ||
596 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, | |
c17fc025 | 597 | qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
c59f781e AJ |
598 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_2)); |
599 | ||
600 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, | |
c17fc025 | 601 | qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
c59f781e AJ |
602 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_3)); |
603 | ||
604 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, | |
c17fc025 | 605 | qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
c59f781e | 606 | sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); |
a3888d75 JS |
607 | |
608 | /* HACE */ | |
609 | object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), | |
610 | &error_abort); | |
611 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { | |
612 | return; | |
613 | } | |
5bfcbda7 PD |
614 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0, |
615 | sc->memmap[ASPEED_DEV_HACE]); | |
a3888d75 JS |
616 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, |
617 | aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); | |
3222165d TL |
618 | |
619 | /* I3C */ | |
620 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { | |
621 | return; | |
622 | } | |
5bfcbda7 | 623 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); |
3222165d | 624 | for (i = 0; i < ASPEED_I3C_NR_DEVICES; i++) { |
c17fc025 | 625 | irq = qdev_get_gpio_in(DEVICE(&a->a7mpcore), |
e8874c06 | 626 | sc->irqmap[ASPEED_DEV_I3C] + i); |
3222165d TL |
627 | /* The AST2600 I3C controller has one IRQ per bus. */ |
628 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); | |
629 | } | |
e1acf581 JS |
630 | |
631 | /* Secure Boot Controller */ | |
632 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { | |
633 | return; | |
634 | } | |
5bfcbda7 | 635 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); |
3fd941f3 NP |
636 | |
637 | /* FSI */ | |
638 | for (i = 0; i < ASPEED_FSI_NUM; i++) { | |
639 | if (!sysbus_realize(SYS_BUS_DEVICE(&s->fsi[i]), errp)) { | |
640 | return; | |
641 | } | |
642 | aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fsi[i]), 0, | |
643 | sc->memmap[ASPEED_DEV_FSI1 + i]); | |
644 | sysbus_connect_irq(SYS_BUS_DEVICE(&s->fsi[i]), 0, | |
645 | aspeed_soc_get_irq(s, ASPEED_DEV_FSI1 + i)); | |
646 | } | |
f25c0ae1 CLG |
647 | } |
648 | ||
649 | static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) | |
650 | { | |
dc13909e PMD |
651 | static const char * const valid_cpu_types[] = { |
652 | ARM_CPU_TYPE_NAME("cortex-a7"), | |
653 | NULL | |
654 | }; | |
f25c0ae1 CLG |
655 | DeviceClass *dc = DEVICE_CLASS(oc); |
656 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc); | |
657 | ||
658 | dc->realize = aspeed_soc_ast2600_realize; | |
659 | ||
c5811bb3 | 660 | sc->name = "ast2600-a3"; |
dc13909e | 661 | sc->valid_cpu_types = valid_cpu_types; |
c5811bb3 | 662 | sc->silicon_rev = AST2600_A3_SILICON_REV; |
e01b4d5b | 663 | sc->sram_size = 0x16400; |
f25c0ae1 | 664 | sc->spis_num = 2; |
917940ce | 665 | sc->ehcis_num = 2; |
f25c0ae1 | 666 | sc->wdts_num = 4; |
d300db02 | 667 | sc->macs_num = 4; |
c5e1bdb9 | 668 | sc->uarts_num = 13; |
f25c0ae1 CLG |
669 | sc->irqmap = aspeed_soc_ast2600_irqmap; |
670 | sc->memmap = aspeed_soc_ast2600_memmap; | |
671 | sc->num_cpus = 2; | |
699db715 | 672 | sc->get_irq = aspeed_soc_ast2600_get_irq; |
f25c0ae1 CLG |
673 | } |
674 | ||
4fc5e806 PMD |
675 | static const TypeInfo aspeed_soc_ast2600_types[] = { |
676 | { | |
677 | .name = TYPE_ASPEED2600_SOC, | |
678 | .parent = TYPE_ASPEED_SOC, | |
679 | .instance_size = sizeof(Aspeed2600SoCState), | |
680 | .abstract = true, | |
681 | }, { | |
682 | .name = "ast2600-a3", | |
683 | .parent = TYPE_ASPEED2600_SOC, | |
684 | .instance_init = aspeed_soc_ast2600_init, | |
685 | .class_init = aspeed_soc_ast2600_class_init, | |
686 | }, | |
f25c0ae1 CLG |
687 | }; |
688 | ||
4fc5e806 | 689 | DEFINE_TYPES(aspeed_soc_ast2600_types) |