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intel-iommu: Redefine macros to enable supporting 48 bit address width
[mirror_qemu.git] / hw / i386 / intel_iommu.c
CommitLineData
1da12ec4
LT		 1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
b6a0aa05 22#include "qemu/osdep.h"
4684a204 23#include "qemu/error-report.h"
6333e93c 24#include "qapi/error.h"
1da12ec4
LT		 25#include "hw/sysbus.h"
26#include "exec/address-spaces.h"
27#include "intel_iommu_internal.h"
7df953bd 28#include "hw/pci/pci.h"
3cb3b154 29#include "hw/pci/pci_bus.h"
621d983a 30#include "hw/i386/pc.h"
dea651a9 31#include "hw/i386/apic-msidef.h"
04af0e18
PX		 32#include "hw/boards.h"
33#include "hw/i386/x86-iommu.h"
cb135f59 34#include "hw/pci-host/q35.h"
4684a204 35#include "sysemu/kvm.h"
32946019 36#include "hw/i386/apic_internal.h"
fb506e70 37#include "kvm_i386.h"
bc535e59 38#include "trace.h"
1da12ec4 39
1da12ec4
LT		 40static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
41 uint64_t wmask, uint64_t w1cmask)
42{
43 stq_le_p(&s->csr[addr], val);
44 stq_le_p(&s->wmask[addr], wmask);
45 stq_le_p(&s->w1cmask[addr], w1cmask);
46}
47
48static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask)
49{
50 stq_le_p(&s->womask[addr], mask);
51}
52
53static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val,
54 uint32_t wmask, uint32_t w1cmask)
55{
56 stl_le_p(&s->csr[addr], val);
57 stl_le_p(&s->wmask[addr], wmask);
58 stl_le_p(&s->w1cmask[addr], w1cmask);
59}
60
61static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask)
62{
63 stl_le_p(&s->womask[addr], mask);
64}
65
66/* "External" get/set operations */
67static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val)
68{
69 uint64_t oldval = ldq_le_p(&s->csr[addr]);
70 uint64_t wmask = ldq_le_p(&s->wmask[addr]);
71 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]);
72 stq_le_p(&s->csr[addr],
73 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
74}
75
76static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val)
77{
78 uint32_t oldval = ldl_le_p(&s->csr[addr]);
79 uint32_t wmask = ldl_le_p(&s->wmask[addr]);
80 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]);
81 stl_le_p(&s->csr[addr],
82 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
83}
84
85static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr)
86{
87 uint64_t val = ldq_le_p(&s->csr[addr]);
88 uint64_t womask = ldq_le_p(&s->womask[addr]);
89 return val & ~womask;
90}
91
92static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr)
93{
94 uint32_t val = ldl_le_p(&s->csr[addr]);
95 uint32_t womask = ldl_le_p(&s->womask[addr]);
96 return val & ~womask;
97}
98
99/* "Internal" get/set operations */
100static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr)
101{
102 return ldq_le_p(&s->csr[addr]);
103}
104
105static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr)
106{
107 return ldl_le_p(&s->csr[addr]);
108}
109
110static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val)
111{
112 stq_le_p(&s->csr[addr], val);
113}
114
115static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr,
116 uint32_t clear, uint32_t mask)
117{
118 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask;
119 stl_le_p(&s->csr[addr], new_val);
120 return new_val;
121}
122
123static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,
124 uint64_t clear, uint64_t mask)
125{
126 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask;
127 stq_le_p(&s->csr[addr], new_val);
128 return new_val;
129}
130
b5a280c0
LT		 131/* GHashTable functions */
132static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)
133{
134 return *((const uint64_t *)v1) == *((const uint64_t *)v2);
135}
136
137static guint vtd_uint64_hash(gconstpointer v)
138{
139 return (guint)*(const uint64_t *)v;
140}
141
142static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
143 gpointer user_data)
144{
145 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
146 uint16_t domain_id = *(uint16_t *)user_data;
147 return entry->domain_id == domain_id;
148}
149
d66b969b
JW		 150/* The shift of an addr for a certain level of paging structure */
151static inline uint32_t vtd_slpt_level_shift(uint32_t level)
152{
7e58326a 153 assert(level != 0);
d66b969b
JW		 154 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
155}
156
157static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
158{
159 return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
160}
161
b5a280c0
LT		 162static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
163 gpointer user_data)
164{
165 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
166 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
d66b969b
JW		 167 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
168 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
b5a280c0 169 return (entry->domain_id == info->domain_id) &&
d66b969b
JW		 170 (((entry->gfn & info->mask) == gfn) ||
171 (entry->gfn == gfn_tlb));
b5a280c0
LT		 172}
173
d92fa2dc
LT		 174/* Reset all the gen of VTDAddressSpace to zero and set the gen of
175 * IntelIOMMUState to 1.
176 */
177static void vtd_reset_context_cache(IntelIOMMUState *s)
178{
d92fa2dc 179 VTDAddressSpace *vtd_as;
7df953bd
KO		 180 VTDBus *vtd_bus;
181 GHashTableIter bus_it;
d92fa2dc
LT		 182 uint32_t devfn_it;
183
7feb51b7
PX		 184 trace_vtd_context_cache_reset();
185
7df953bd
KO		 186 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
187
7df953bd 188 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
bf33cc75 189 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 190 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc
LT		 191 if (!vtd_as) {
192 continue;
193 }
194 vtd_as->context_cache_entry.context_cache_gen = 0;
195 }
196 }
197 s->context_cache_gen = 1;
198}
199
b5a280c0
LT		 200static void vtd_reset_iotlb(IntelIOMMUState *s)
201{
202 assert(s->iotlb);
203 g_hash_table_remove_all(s->iotlb);
204}
205
bacabb0a 206static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id,
d66b969b
JW		 207 uint32_t level)
208{
209 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) |
210 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT);
211}
212
213static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
214{
215 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
216}
217
b5a280c0
LT		 218static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
219 hwaddr addr)
220{
d66b969b 221 VTDIOTLBEntry *entry;
b5a280c0 222 uint64_t key;
d66b969b
JW		 223 int level;
224
225 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
226 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level),
227 source_id, level);
228 entry = g_hash_table_lookup(s->iotlb, &key);
229 if (entry) {
230 goto out;
231 }
232 }
b5a280c0 233
d66b969b
JW		 234out:
235 return entry;
b5a280c0
LT		 236}
237
238static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
239 uint16_t domain_id, hwaddr addr, uint64_t slpte,
07f7b733 240 uint8_t access_flags, uint32_t level)
b5a280c0
LT		 241{
242 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
243 uint64_t *key = g_malloc(sizeof(*key));
d66b969b 244 uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
b5a280c0 245
6c441e1d 246 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id);
b5a280c0 247 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
6c441e1d 248 trace_vtd_iotlb_reset("iotlb exceeds size limit");
b5a280c0
LT		 249 vtd_reset_iotlb(s);
250 }
251
252 entry->gfn = gfn;
253 entry->domain_id = domain_id;
254 entry->slpte = slpte;
07f7b733 255 entry->access_flags = access_flags;
d66b969b
JW		 256 entry->mask = vtd_slpt_level_page_mask(level);
257 *key = vtd_get_iotlb_key(gfn, source_id, level);
b5a280c0
LT		 258 g_hash_table_replace(s->iotlb, key, entry);
259}
260
1da12ec4
LT		 261/* Given the reg addr of both the message data and address, generate an
262 * interrupt via MSI.
263 */
264static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
265 hwaddr mesg_data_reg)
266{
32946019 267 MSIMessage msi;
1da12ec4
LT		 268
269 assert(mesg_data_reg < DMAR_REG_SIZE);
270 assert(mesg_addr_reg < DMAR_REG_SIZE);
271
32946019
RK		 272 msi.address = vtd_get_long_raw(s, mesg_addr_reg);
273 msi.data = vtd_get_long_raw(s, mesg_data_reg);
1da12ec4 274
7feb51b7
PX		 275 trace_vtd_irq_generate(msi.address, msi.data);
276
32946019 277 apic_get_class()->send_msi(&msi);
1da12ec4
LT		 278}
279
280/* Generate a fault event to software via MSI if conditions are met.
281 * Notice that the value of FSTS_REG being passed to it should be the one
282 * before any update.
283 */
284static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
285{
286 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
287 pre_fsts & VTD_FSTS_IQE) {
7feb51b7
PX		 288 trace_vtd_err("There are previous interrupt conditions "
289 "to be serviced by software, fault event "
290 "is not generated.");
1da12ec4
LT		 291 return;
292 }
293 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
294 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
7feb51b7 295 trace_vtd_err("Interrupt Mask set, irq is not generated.");
1da12ec4
LT		 296 } else {
297 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
298 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
299 }
300}
301
302/* Check if the Fault (F) field of the Fault Recording Register referenced by
303 * @index is Set.
304 */
305static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index)
306{
307 /* Each reg is 128-bit */
308 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
309 addr += 8; /* Access the high 64-bit half */
310
311 assert(index < DMAR_FRCD_REG_NR);
312
313 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F;
314}
315
316/* Update the PPF field of Fault Status Register.
317 * Should be called whenever change the F field of any fault recording
318 * registers.
319 */
320static void vtd_update_fsts_ppf(IntelIOMMUState *s)
321{
322 uint32_t i;
323 uint32_t ppf_mask = 0;
324
325 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
326 if (vtd_is_frcd_set(s, i)) {
327 ppf_mask = VTD_FSTS_PPF;
328 break;
329 }
330 }
331 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask);
7feb51b7 332 trace_vtd_fsts_ppf(!!ppf_mask);
1da12ec4
LT		 333}
334
335static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
336{
337 /* Each reg is 128-bit */
338 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
339 addr += 8; /* Access the high 64-bit half */
340
341 assert(index < DMAR_FRCD_REG_NR);
342
343 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F);
344 vtd_update_fsts_ppf(s);
345}
346
347/* Must not update F field now, should be done later */
348static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
349 uint16_t source_id, hwaddr addr,
350 VTDFaultReason fault, bool is_write)
351{
352 uint64_t hi = 0, lo;
353 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
354
355 assert(index < DMAR_FRCD_REG_NR);
356
357 lo = VTD_FRCD_FI(addr);
358 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
359 if (!is_write) {
360 hi |= VTD_FRCD_T;
361 }
362 vtd_set_quad_raw(s, frcd_reg_addr, lo);
363 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
7feb51b7
PX		 364
365 trace_vtd_frr_new(index, hi, lo);
1da12ec4
LT		 366}
367
368/* Try to collapse multiple pending faults from the same requester */
369static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
370{
371 uint32_t i;
372 uint64_t frcd_reg;
373 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */
374
375 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
376 frcd_reg = vtd_get_quad_raw(s, addr);
1da12ec4
LT		 377 if ((frcd_reg & VTD_FRCD_F) &&
378 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) {
379 return true;
380 }
381 addr += 16; /* 128-bit for each */
382 }
383 return false;
384}
385
386/* Log and report an DMAR (address translation) fault to software */
387static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
388 hwaddr addr, VTDFaultReason fault,
389 bool is_write)
390{
391 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
392
393 assert(fault < VTD_FR_MAX);
394
395 if (fault == VTD_FR_RESERVED_ERR) {
396 /* This is not a normal fault reason case. Drop it. */
397 return;
398 }
7feb51b7
PX		 399
400 trace_vtd_dmar_fault(source_id, fault, addr, is_write);
401
1da12ec4 402 if (fsts_reg & VTD_FSTS_PFO) {
7feb51b7
PX		 403 trace_vtd_err("New fault is not recorded due to "
404 "Primary Fault Overflow.");
1da12ec4
LT		 405 return;
406 }
7feb51b7 407
1da12ec4 408 if (vtd_try_collapse_fault(s, source_id)) {
7feb51b7
PX		 409 trace_vtd_err("New fault is not recorded due to "
410 "compression of faults.");
1da12ec4
LT		 411 return;
412 }
7feb51b7 413
1da12ec4 414 if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
7feb51b7
PX		 415 trace_vtd_err("Next Fault Recording Reg is used, "
416 "new fault is not recorded, set PFO field.");
1da12ec4
LT		 417 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
418 return;
419 }
420
421 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
422
423 if (fsts_reg & VTD_FSTS_PPF) {
7feb51b7
PX		 424 trace_vtd_err("There are pending faults already, "
425 "fault event is not generated.");
1da12ec4
LT		 426 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
427 s->next_frcd_reg++;
428 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
429 s->next_frcd_reg = 0;
430 }
431 } else {
432 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK,
433 VTD_FSTS_FRI(s->next_frcd_reg));
434 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */
435 s->next_frcd_reg++;
436 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
437 s->next_frcd_reg = 0;
438 }
439 /* This case actually cause the PPF to be Set.
440 * So generate fault event (interrupt).
441 */
442 vtd_generate_fault_event(s, fsts_reg);
443 }
444}
445
ed7b8fbc
LT		 446/* Handle Invalidation Queue Errors of queued invalidation interface error
447 * conditions.
448 */
449static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
450{
451 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
452
453 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE);
454 vtd_generate_fault_event(s, fsts_reg);
455}
456
457/* Set the IWC field and try to generate an invalidation completion interrupt */
458static void vtd_generate_completion_event(IntelIOMMUState *s)
459{
ed7b8fbc 460 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
bc535e59 461 trace_vtd_inv_desc_wait_irq("One pending, skip current");
ed7b8fbc
LT		 462 return;
463 }
464 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
465 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
466 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
bc535e59
PX		 467 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
468 "new event not generated");
ed7b8fbc
LT		 469 return;
470 } else {
471 /* Generate the interrupt event */
bc535e59 472 trace_vtd_inv_desc_wait_irq("Generating complete event");
ed7b8fbc
LT		 473 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
474 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
475 }
476}
477
1da12ec4
LT		 478static inline bool vtd_root_entry_present(VTDRootEntry *root)
479{
480 return root->val & VTD_ROOT_ENTRY_P;
481}
482
483static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index,
484 VTDRootEntry *re)
485{
486 dma_addr_t addr;
487
488 addr = s->root + index * sizeof(*re);
489 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {
6c441e1d 490 trace_vtd_re_invalid(re->rsvd, re->val);
1da12ec4
LT		 491 re->val = 0;
492 return -VTD_FR_ROOT_TABLE_INV;
493 }
494 re->val = le64_to_cpu(re->val);
495 return 0;
496}
497
8f7d7161 498static inline bool vtd_ce_present(VTDContextEntry *context)
1da12ec4
LT		 499{
500 return context->lo & VTD_CONTEXT_ENTRY_P;
501}
502
503static int vtd_get_context_entry_from_root(VTDRootEntry *root, uint8_t index,
504 VTDContextEntry *ce)
505{
506 dma_addr_t addr;
507
6c441e1d 508 /* we have checked that root entry is present */
1da12ec4
LT		 509 addr = (root->val & VTD_ROOT_ENTRY_CTP) + index * sizeof(*ce);
510 if (dma_memory_read(&address_space_memory, addr, ce, sizeof(*ce))) {
6c441e1d 511 trace_vtd_re_invalid(root->rsvd, root->val);
1da12ec4
LT		 512 return -VTD_FR_CONTEXT_TABLE_INV;
513 }
514 ce->lo = le64_to_cpu(ce->lo);
515 ce->hi = le64_to_cpu(ce->hi);
516 return 0;
517}
518
8f7d7161 519static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce)
1da12ec4
LT		 520{
521 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
522}
523
1da12ec4
LT		 524static inline uint64_t vtd_get_slpte_addr(uint64_t slpte)
525{
92e5d85e 526 return slpte & VTD_SL_PT_BASE_ADDR_MASK(VTD_HOST_ADDRESS_WIDTH);
1da12ec4
LT		 527}
528
529/* Whether the pte indicates the address of the page frame */
530static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
531{
532 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
533}
534
535/* Get the content of a spte located in @base_addr[@index] */
536static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
537{
538 uint64_t slpte;
539
540 assert(index < VTD_SL_PT_ENTRY_NR);
541
542 if (dma_memory_read(&address_space_memory,
543 base_addr + index * sizeof(slpte), &slpte,
544 sizeof(slpte))) {
545 slpte = (uint64_t)-1;
546 return slpte;
547 }
548 slpte = le64_to_cpu(slpte);
549 return slpte;
550}
551
6e905564
PX		 552/* Given an iova and the level of paging structure, return the offset
553 * of current level.
1da12ec4 554 */
6e905564 555static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level)
1da12ec4 556{
6e905564 557 return (iova >> vtd_slpt_level_shift(level)) &
1da12ec4
LT		 558 ((1ULL << VTD_SL_LEVEL_BITS) - 1);
559}
560
561/* Check Capability Register to see if the @level of page-table is supported */
562static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
563{
564 return VTD_CAP_SAGAW_MASK & s->cap &
565 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
566}
567
568/* Get the page-table level that hardware should use for the second-level
569 * page-table walk from the Address Width field of context-entry.
570 */
8f7d7161 571static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce)
1da12ec4
LT		 572{
573 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
574}
575
8f7d7161 576static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce)
1da12ec4
LT		 577{
578 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
579}
580
127ff5c3
PX		 581static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce)
582{
583 return ce->lo & VTD_CONTEXT_ENTRY_TT;
584}
585
f80c9874
PX		 586/* Return true if check passed, otherwise false */
587static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu,
588 VTDContextEntry *ce)
589{
590 switch (vtd_ce_get_type(ce)) {
591 case VTD_CONTEXT_TT_MULTI_LEVEL:
592 /* Always supported */
593 break;
594 case VTD_CONTEXT_TT_DEV_IOTLB:
595 if (!x86_iommu->dt_supported) {
596 return false;
597 }
598 break;
dbaabb25
PX		 599 case VTD_CONTEXT_TT_PASS_THROUGH:
600 if (!x86_iommu->pt_supported) {
601 return false;
602 }
603 break;
f80c9874
PX		 604 default:
605 /* Unknwon type */
606 return false;
607 }
608 return true;
609}
610
f06a696d
PX		 611static inline uint64_t vtd_iova_limit(VTDContextEntry *ce)
612{
8f7d7161 613 uint32_t ce_agaw = vtd_ce_get_agaw(ce);
f06a696d
PX		 614 return 1ULL << MIN(ce_agaw, VTD_MGAW);
615}
616
617/* Return true if IOVA passes range check, otherwise false. */
618static inline bool vtd_iova_range_check(uint64_t iova, VTDContextEntry *ce)
619{
620 /*
621 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
622 * in CAP_REG and AW in context-entry.
623 */
624 return !(iova & ~(vtd_iova_limit(ce) - 1));
625}
626
92e5d85e
PS		 627/*
628 * Rsvd field masks for spte:
629 * Index [1] to [4] 4k pages
630 * Index [5] to [8] large pages
631 */
632static uint64_t vtd_paging_entry_rsvd_field[9];
1da12ec4
LT		 633
634static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
635{
636 if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
637 /* Maybe large page */
638 return slpte & vtd_paging_entry_rsvd_field[level + 4];
639 } else {
640 return slpte & vtd_paging_entry_rsvd_field[level];
641 }
642}
643
dbaabb25
PX		 644/* Find the VTD address space associated with a given bus number */
645static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
646{
647 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
648 if (!vtd_bus) {
649 /*
650 * Iterate over the registered buses to find the one which
651 * currently hold this bus number, and update the bus_num
652 * lookup table:
653 */
654 GHashTableIter iter;
655
656 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
657 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
658 if (pci_bus_num(vtd_bus->bus) == bus_num) {
659 s->vtd_as_by_bus_num[bus_num] = vtd_bus;
660 return vtd_bus;
661 }
662 }
663 }
664 return vtd_bus;
665}
666
6e905564 667/* Given the @iova, get relevant @slptep. @slpte_level will be the last level
1da12ec4
LT		 668 * of the translation, can be used for deciding the size of large page.
669 */
6e905564
PX		 670static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
671 uint64_t *slptep, uint32_t *slpte_level,
672 bool *reads, bool *writes)
1da12ec4 673{
8f7d7161
PX		 674 dma_addr_t addr = vtd_ce_get_slpt_base(ce);
675 uint32_t level = vtd_ce_get_level(ce);
1da12ec4
LT		 676 uint32_t offset;
677 uint64_t slpte;
1da12ec4
LT		 678 uint64_t access_right_check;
679
f06a696d 680 if (!vtd_iova_range_check(iova, ce)) {
7feb51b7 681 trace_vtd_err_dmar_iova_overflow(iova);
1da12ec4
LT		 682 return -VTD_FR_ADDR_BEYOND_MGAW;
683 }
684
685 /* FIXME: what is the Atomics request here? */
686 access_right_check = is_write ? VTD_SL_W : VTD_SL_R;
687
688 while (true) {
6e905564 689 offset = vtd_iova_level_offset(iova, level);
1da12ec4
LT		 690 slpte = vtd_get_slpte(addr, offset);
691
692 if (slpte == (uint64_t)-1) {
7feb51b7 693 trace_vtd_err_dmar_slpte_read_error(iova, level);
8f7d7161 694 if (level == vtd_ce_get_level(ce)) {
1da12ec4
LT		 695 /* Invalid programming of context-entry */
696 return -VTD_FR_CONTEXT_ENTRY_INV;
697 } else {
698 return -VTD_FR_PAGING_ENTRY_INV;
699 }
700 }
701 *reads = (*reads) && (slpte & VTD_SL_R);
702 *writes = (*writes) && (slpte & VTD_SL_W);
703 if (!(slpte & access_right_check)) {
7feb51b7 704 trace_vtd_err_dmar_slpte_perm_error(iova, level, slpte, is_write);
1da12ec4
LT		 705 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
706 }
707 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
7feb51b7 708 trace_vtd_err_dmar_slpte_resv_error(iova, level, slpte);
1da12ec4
LT		 709 return -VTD_FR_PAGING_ENTRY_RSVD;
710 }
711
712 if (vtd_is_last_slpte(slpte, level)) {
713 *slptep = slpte;
714 *slpte_level = level;
715 return 0;
716 }
717 addr = vtd_get_slpte_addr(slpte);
718 level--;
719 }
720}
721
f06a696d
PX		 722typedef int (*vtd_page_walk_hook)(IOMMUTLBEntry *entry, void *private);
723
724/**
725 * vtd_page_walk_level - walk over specific level for IOVA range
726 *
727 * @addr: base GPA addr to start the walk
728 * @start: IOVA range start address
729 * @end: IOVA range end address (start <= addr < end)
730 * @hook_fn: hook func to be called when detected page
731 * @private: private data to be passed into hook func
732 * @read: whether parent level has read permission
733 * @write: whether parent level has write permission
734 * @notify_unmap: whether we should notify invalid entries
735 */
736static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
737 uint64_t end, vtd_page_walk_hook hook_fn,
738 void *private, uint32_t level,
739 bool read, bool write, bool notify_unmap)
740{
741 bool read_cur, write_cur, entry_valid;
742 uint32_t offset;
743 uint64_t slpte;
744 uint64_t subpage_size, subpage_mask;
745 IOMMUTLBEntry entry;
746 uint64_t iova = start;
747 uint64_t iova_next;
748 int ret = 0;
749
750 trace_vtd_page_walk_level(addr, level, start, end);
751
752 subpage_size = 1ULL << vtd_slpt_level_shift(level);
753 subpage_mask = vtd_slpt_level_page_mask(level);
754
755 while (iova < end) {
756 iova_next = (iova & subpage_mask) + subpage_size;
757
758 offset = vtd_iova_level_offset(iova, level);
759 slpte = vtd_get_slpte(addr, offset);
760
761 if (slpte == (uint64_t)-1) {
762 trace_vtd_page_walk_skip_read(iova, iova_next);
763 goto next;
764 }
765
766 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
767 trace_vtd_page_walk_skip_reserve(iova, iova_next);
768 goto next;
769 }
770
771 /* Permissions are stacked with parents' */
772 read_cur = read && (slpte & VTD_SL_R);
773 write_cur = write && (slpte & VTD_SL_W);
774
775 /*
776 * As long as we have either read/write permission, this is a
777 * valid entry. The rule works for both page entries and page
778 * table entries.
779 */
780 entry_valid = read_cur | write_cur;
781
782 if (vtd_is_last_slpte(slpte, level)) {
783 entry.target_as = &address_space_memory;
784 entry.iova = iova & subpage_mask;
785 /* NOTE: this is only meaningful if entry_valid == true */
786 entry.translated_addr = vtd_get_slpte_addr(slpte);
787 entry.addr_mask = ~subpage_mask;
788 entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
789 if (!entry_valid && !notify_unmap) {
790 trace_vtd_page_walk_skip_perm(iova, iova_next);
791 goto next;
792 }
793 trace_vtd_page_walk_one(level, entry.iova, entry.translated_addr,
794 entry.addr_mask, entry.perm);
795 if (hook_fn) {
796 ret = hook_fn(&entry, private);
797 if (ret < 0) {
798 return ret;
799 }
800 }
801 } else {
802 if (!entry_valid) {
803 trace_vtd_page_walk_skip_perm(iova, iova_next);
804 goto next;
805 }
806 ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte), iova,
807 MIN(iova_next, end), hook_fn, private,
808 level - 1, read_cur, write_cur,
809 notify_unmap);
810 if (ret < 0) {
811 return ret;
812 }
813 }
814
815next:
816 iova = iova_next;
817 }
818
819 return 0;
820}
821
822/**
823 * vtd_page_walk - walk specific IOVA range, and call the hook
824 *
825 * @ce: context entry to walk upon
826 * @start: IOVA address to start the walk
827 * @end: IOVA range end address (start <= addr < end)
828 * @hook_fn: the hook that to be called for each detected area
829 * @private: private data for the hook function
830 */
831static int vtd_page_walk(VTDContextEntry *ce, uint64_t start, uint64_t end,
dd4d607e
PX		 832 vtd_page_walk_hook hook_fn, void *private,
833 bool notify_unmap)
f06a696d 834{
8f7d7161
PX		 835 dma_addr_t addr = vtd_ce_get_slpt_base(ce);
836 uint32_t level = vtd_ce_get_level(ce);
f06a696d
PX		 837
838 if (!vtd_iova_range_check(start, ce)) {
839 return -VTD_FR_ADDR_BEYOND_MGAW;
840 }
841
842 if (!vtd_iova_range_check(end, ce)) {
843 /* Fix end so that it reaches the maximum */
844 end = vtd_iova_limit(ce);
845 }
846
847 return vtd_page_walk_level(addr, start, end, hook_fn, private,
dd4d607e 848 level, true, true, notify_unmap);
f06a696d
PX		 849}
850
1da12ec4
LT		 851/* Map a device to its corresponding domain (context-entry) */
852static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
853 uint8_t devfn, VTDContextEntry *ce)
854{
855 VTDRootEntry re;
856 int ret_fr;
f80c9874 857 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
1da12ec4
LT		 858
859 ret_fr = vtd_get_root_entry(s, bus_num, &re);
860 if (ret_fr) {
861 return ret_fr;
862 }
863
864 if (!vtd_root_entry_present(&re)) {
6c441e1d
PX		 865 /* Not error - it's okay we don't have root entry. */
866 trace_vtd_re_not_present(bus_num);
1da12ec4 867 return -VTD_FR_ROOT_ENTRY_P;
f80c9874
PX		 868 }
869
92e5d85e 870 if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD(VTD_HOST_ADDRESS_WIDTH))) {
6c441e1d 871 trace_vtd_re_invalid(re.rsvd, re.val);
1da12ec4
LT		 872 return -VTD_FR_ROOT_ENTRY_RSVD;
873 }
874
875 ret_fr = vtd_get_context_entry_from_root(&re, devfn, ce);
876 if (ret_fr) {
877 return ret_fr;
878 }
879
8f7d7161 880 if (!vtd_ce_present(ce)) {
6c441e1d
PX		 881 /* Not error - it's okay we don't have context entry. */
882 trace_vtd_ce_not_present(bus_num, devfn);
1da12ec4 883 return -VTD_FR_CONTEXT_ENTRY_P;
f80c9874
PX		 884 }
885
886 if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) ||
92e5d85e 887 (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(VTD_HOST_ADDRESS_WIDTH))) {
6c441e1d 888 trace_vtd_ce_invalid(ce->hi, ce->lo);
1da12ec4
LT		 889 return -VTD_FR_CONTEXT_ENTRY_RSVD;
890 }
f80c9874 891
1da12ec4 892 /* Check if the programming of context-entry is valid */
8f7d7161 893 if (!vtd_is_level_supported(s, vtd_ce_get_level(ce))) {
6c441e1d 894 trace_vtd_ce_invalid(ce->hi, ce->lo);
1da12ec4 895 return -VTD_FR_CONTEXT_ENTRY_INV;
1da12ec4 896 }
f80c9874
PX		 897
898 /* Do translation type check */
899 if (!vtd_ce_type_check(x86_iommu, ce)) {
900 trace_vtd_ce_invalid(ce->hi, ce->lo);
901 return -VTD_FR_CONTEXT_ENTRY_INV;
902 }
903
1da12ec4
LT		 904 return 0;
905}
906
dbaabb25
PX		 907/*
908 * Fetch translation type for specific device. Returns <0 if error
909 * happens, otherwise return the shifted type to check against
910 * VTD_CONTEXT_TT_*.
911 */
912static int vtd_dev_get_trans_type(VTDAddressSpace *as)
913{
914 IntelIOMMUState *s;
915 VTDContextEntry ce;
916 int ret;
917
918 s = as->iommu_state;
919
920 ret = vtd_dev_to_context_entry(s, pci_bus_num(as->bus),
921 as->devfn, &ce);
922 if (ret) {
923 return ret;
924 }
925
926 return vtd_ce_get_type(&ce);
927}
928
929static bool vtd_dev_pt_enabled(VTDAddressSpace *as)
930{
931 int ret;
932
933 assert(as);
934
935 ret = vtd_dev_get_trans_type(as);
936 if (ret < 0) {
937 /*
938 * Possibly failed to parse the context entry for some reason
939 * (e.g., during init, or any guest configuration errors on
940 * context entries). We should assume PT not enabled for
941 * safety.
942 */
943 return false;
944 }
945
946 return ret == VTD_CONTEXT_TT_PASS_THROUGH;
947}
948
949/* Return whether the device is using IOMMU translation. */
950static bool vtd_switch_address_space(VTDAddressSpace *as)
951{
952 bool use_iommu;
66a4a031
PX		 953 /* Whether we need to take the BQL on our own */
954 bool take_bql = !qemu_mutex_iothread_locked();
dbaabb25
PX		 955
956 assert(as);
957
958 use_iommu = as->iommu_state->dmar_enabled & !vtd_dev_pt_enabled(as);
959
960 trace_vtd_switch_address_space(pci_bus_num(as->bus),
961 VTD_PCI_SLOT(as->devfn),
962 VTD_PCI_FUNC(as->devfn),
963 use_iommu);
964
66a4a031
PX		 965 /*
966 * It's possible that we reach here without BQL, e.g., when called
967 * from vtd_pt_enable_fast_path(). However the memory APIs need
968 * it. We'd better make sure we have had it already, or, take it.
969 */
970 if (take_bql) {
971 qemu_mutex_lock_iothread();
972 }
973
dbaabb25
PX		 974 /* Turn off first then on the other */
975 if (use_iommu) {
976 memory_region_set_enabled(&as->sys_alias, false);
3df9d748 977 memory_region_set_enabled(MEMORY_REGION(&as->iommu), true);
dbaabb25 978 } else {
3df9d748 979 memory_region_set_enabled(MEMORY_REGION(&as->iommu), false);
dbaabb25
PX		 980 memory_region_set_enabled(&as->sys_alias, true);
981 }
982
66a4a031
PX		 983 if (take_bql) {
984 qemu_mutex_unlock_iothread();
985 }
986
dbaabb25
PX		 987 return use_iommu;
988}
989
990static void vtd_switch_address_space_all(IntelIOMMUState *s)
991{
992 GHashTableIter iter;
993 VTDBus *vtd_bus;
994 int i;
995
996 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
997 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
bf33cc75 998 for (i = 0; i < PCI_DEVFN_MAX; i++) {
dbaabb25
PX		 999 if (!vtd_bus->dev_as[i]) {
1000 continue;
1001 }
1002 vtd_switch_address_space(vtd_bus->dev_as[i]);
1003 }
1004 }
1005}
1006
1da12ec4
LT		 1007static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
1008{
1009 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
1010}
1011
1012static const bool vtd_qualified_faults[] = {
1013 [VTD_FR_RESERVED] = false,
1014 [VTD_FR_ROOT_ENTRY_P] = false,
1015 [VTD_FR_CONTEXT_ENTRY_P] = true,
1016 [VTD_FR_CONTEXT_ENTRY_INV] = true,
1017 [VTD_FR_ADDR_BEYOND_MGAW] = true,
1018 [VTD_FR_WRITE] = true,
1019 [VTD_FR_READ] = true,
1020 [VTD_FR_PAGING_ENTRY_INV] = true,
1021 [VTD_FR_ROOT_TABLE_INV] = false,
1022 [VTD_FR_CONTEXT_TABLE_INV] = false,
1023 [VTD_FR_ROOT_ENTRY_RSVD] = false,
1024 [VTD_FR_PAGING_ENTRY_RSVD] = true,
1025 [VTD_FR_CONTEXT_ENTRY_TT] = true,
1026 [VTD_FR_RESERVED_ERR] = false,
1027 [VTD_FR_MAX] = false,
1028};
1029
1030/* To see if a fault condition is "qualified", which is reported to software
1031 * only if the FPD field in the context-entry used to process the faulting
1032 * request is 0.
1033 */
1034static inline bool vtd_is_qualified_fault(VTDFaultReason fault)
1035{
1036 return vtd_qualified_faults[fault];
1037}
1038
1039static inline bool vtd_is_interrupt_addr(hwaddr addr)
1040{
1041 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
1042}
1043
dbaabb25
PX		 1044static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
1045{
1046 VTDBus *vtd_bus;
1047 VTDAddressSpace *vtd_as;
1048 bool success = false;
1049
1050 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
1051 if (!vtd_bus) {
1052 goto out;
1053 }
1054
1055 vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)];
1056 if (!vtd_as) {
1057 goto out;
1058 }
1059
1060 if (vtd_switch_address_space(vtd_as) == false) {
1061 /* We switched off IOMMU region successfully. */
1062 success = true;
1063 }
1064
1065out:
1066 trace_vtd_pt_enable_fast_path(source_id, success);
1067}
1068
1da12ec4
LT		 1069/* Map dev to context-entry then do a paging-structures walk to do a iommu
1070 * translation.
79e2b9ae
PB		 1071 *
1072 * Called from RCU critical section.
1073 *
1da12ec4
LT		 1074 * @bus_num: The bus number
1075 * @devfn: The devfn, which is the combined of device and function number
1076 * @is_write: The access is a write operation
1077 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
b9313021
PX		 1078 *
1079 * Returns true if translation is successful, otherwise false.
1da12ec4 1080 */
b9313021 1081static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
1da12ec4
LT		 1082 uint8_t devfn, hwaddr addr, bool is_write,
1083 IOMMUTLBEntry *entry)
1084{
d92fa2dc 1085 IntelIOMMUState *s = vtd_as->iommu_state;
1da12ec4 1086 VTDContextEntry ce;
7df953bd 1087 uint8_t bus_num = pci_bus_num(bus);
d92fa2dc 1088 VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry;
d66b969b 1089 uint64_t slpte, page_mask;
1da12ec4
LT		 1090 uint32_t level;
1091 uint16_t source_id = vtd_make_source_id(bus_num, devfn);
1092 int ret_fr;
1093 bool is_fpd_set = false;
1094 bool reads = true;
1095 bool writes = true;
07f7b733 1096 uint8_t access_flags;
b5a280c0 1097 VTDIOTLBEntry *iotlb_entry;
1da12ec4 1098
046ab7e9
PX		 1099 /*
1100 * We have standalone memory region for interrupt addresses, we
1101 * should never receive translation requests in this region.
1102 */
1103 assert(!vtd_is_interrupt_addr(addr));
1104
b5a280c0
LT		 1105 /* Try to fetch slpte form IOTLB */
1106 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);
1107 if (iotlb_entry) {
6c441e1d
PX		 1108 trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte,
1109 iotlb_entry->domain_id);
b5a280c0 1110 slpte = iotlb_entry->slpte;
07f7b733 1111 access_flags = iotlb_entry->access_flags;
d66b969b 1112 page_mask = iotlb_entry->mask;
b5a280c0
LT		 1113 goto out;
1114 }
b9313021 1115
d92fa2dc
LT		 1116 /* Try to fetch context-entry from cache first */
1117 if (cc_entry->context_cache_gen == s->context_cache_gen) {
6c441e1d
PX		 1118 trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi,
1119 cc_entry->context_entry.lo,
1120 cc_entry->context_cache_gen);
d92fa2dc
LT		 1121 ce = cc_entry->context_entry;
1122 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1123 } else {
1124 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
1125 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1126 if (ret_fr) {
1127 ret_fr = -ret_fr;
1128 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
6c441e1d 1129 trace_vtd_fault_disabled();
d92fa2dc
LT		 1130 } else {
1131 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
1132 }
b9313021 1133 goto error;
1da12ec4 1134 }
d92fa2dc 1135 /* Update context-cache */
6c441e1d
PX		 1136 trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo,
1137 cc_entry->context_cache_gen,
1138 s->context_cache_gen);
d92fa2dc
LT		 1139 cc_entry->context_entry = ce;
1140 cc_entry->context_cache_gen = s->context_cache_gen;
1da12ec4
LT		 1141 }
1142
dbaabb25
PX		 1143 /*
1144 * We don't need to translate for pass-through context entries.
1145 * Also, let's ignore IOTLB caching as well for PT devices.
1146 */
1147 if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) {
892721d9 1148 entry->iova = addr & VTD_PAGE_MASK_4K;
dbaabb25 1149 entry->translated_addr = entry->iova;
892721d9 1150 entry->addr_mask = ~VTD_PAGE_MASK_4K;
dbaabb25
PX		 1151 entry->perm = IOMMU_RW;
1152 trace_vtd_translate_pt(source_id, entry->iova);
1153
1154 /*
1155 * When this happens, it means firstly caching-mode is not
1156 * enabled, and this is the first passthrough translation for
1157 * the device. Let's enable the fast path for passthrough.
1158 *
1159 * When passthrough is disabled again for the device, we can
1160 * capture it via the context entry invalidation, then the
1161 * IOMMU region can be swapped back.
1162 */
1163 vtd_pt_enable_fast_path(s, source_id);
1164
b9313021 1165 return true;
dbaabb25
PX		 1166 }
1167
6e905564
PX		 1168 ret_fr = vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level,
1169 &reads, &writes);
1da12ec4
LT		 1170 if (ret_fr) {
1171 ret_fr = -ret_fr;
1172 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
6c441e1d 1173 trace_vtd_fault_disabled();
1da12ec4
LT		 1174 } else {
1175 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
1176 }
b9313021 1177 goto error;
1da12ec4
LT		 1178 }
1179
d66b969b 1180 page_mask = vtd_slpt_level_page_mask(level);
07f7b733 1181 access_flags = IOMMU_ACCESS_FLAG(reads, writes);
b5a280c0 1182 vtd_update_iotlb(s, source_id, VTD_CONTEXT_ENTRY_DID(ce.hi), addr, slpte,
07f7b733 1183 access_flags, level);
b5a280c0 1184out:
d66b969b
JW		 1185 entry->iova = addr & page_mask;
1186 entry->translated_addr = vtd_get_slpte_addr(slpte) & page_mask;
1187 entry->addr_mask = ~page_mask;
07f7b733 1188 entry->perm = access_flags;
b9313021
PX		 1189 return true;
1190
1191error:
1192 entry->iova = 0;
1193 entry->translated_addr = 0;
1194 entry->addr_mask = 0;
1195 entry->perm = IOMMU_NONE;
1196 return false;
1da12ec4
LT		 1197}
1198
1199static void vtd_root_table_setup(IntelIOMMUState *s)
1200{
1201 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
1202 s->root_extended = s->root & VTD_RTADDR_RTT;
92e5d85e 1203 s->root &= VTD_RTADDR_ADDR_MASK(VTD_HOST_ADDRESS_WIDTH);
1da12ec4 1204
7feb51b7 1205 trace_vtd_reg_dmar_root(s->root, s->root_extended);
1da12ec4
LT		 1206}
1207
02a2cbc8
PX		 1208static void vtd_iec_notify_all(IntelIOMMUState *s, bool global,
1209 uint32_t index, uint32_t mask)
1210{
1211 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask);
1212}
1213
a5861439
PX		 1214static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
1215{
1216 uint64_t value = 0;
1217 value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
1218 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
92e5d85e 1219 s->intr_root = value & VTD_IRTA_ADDR_MASK(VTD_HOST_ADDRESS_WIDTH);
28589311 1220 s->intr_eime = value & VTD_IRTA_EIME;
a5861439 1221
02a2cbc8
PX		 1222 /* Notify global invalidation */
1223 vtd_iec_notify_all(s, true, 0, 0);
a5861439 1224
7feb51b7 1225 trace_vtd_reg_ir_root(s->intr_root, s->intr_size);
a5861439
PX		 1226}
1227
dd4d607e
PX		 1228static void vtd_iommu_replay_all(IntelIOMMUState *s)
1229{
1230 IntelIOMMUNotifierNode *node;
1231
1232 QLIST_FOREACH(node, &s->notifiers_list, next) {
1233 memory_region_iommu_replay_all(&node->vtd_as->iommu);
1234 }
1235}
1236
d92fa2dc
LT		 1237static void vtd_context_global_invalidate(IntelIOMMUState *s)
1238{
bc535e59 1239 trace_vtd_inv_desc_cc_global();
d92fa2dc
LT		 1240 s->context_cache_gen++;
1241 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
1242 vtd_reset_context_cache(s);
1243 }
dbaabb25 1244 vtd_switch_address_space_all(s);
dd4d607e
PX		 1245 /*
1246 * From VT-d spec 6.5.2.1, a global context entry invalidation
1247 * should be followed by a IOTLB global invalidation, so we should
1248 * be safe even without this. Hoewever, let's replay the region as
1249 * well to be safer, and go back here when we need finer tunes for
1250 * VT-d emulation codes.
1251 */
1252 vtd_iommu_replay_all(s);
d92fa2dc
LT		 1253}
1254
1255/* Do a context-cache device-selective invalidation.
1256 * @func_mask: FM field after shifting
1257 */
1258static void vtd_context_device_invalidate(IntelIOMMUState *s,
1259 uint16_t source_id,
1260 uint16_t func_mask)
1261{
1262 uint16_t mask;
7df953bd 1263 VTDBus *vtd_bus;
d92fa2dc 1264 VTDAddressSpace *vtd_as;
bc535e59 1265 uint8_t bus_n, devfn;
d92fa2dc
LT		 1266 uint16_t devfn_it;
1267
bc535e59
PX		 1268 trace_vtd_inv_desc_cc_devices(source_id, func_mask);
1269
d92fa2dc
LT		 1270 switch (func_mask & 3) {
1271 case 0:
1272 mask = 0; /* No bits in the SID field masked */
1273 break;
1274 case 1:
1275 mask = 4; /* Mask bit 2 in the SID field */
1276 break;
1277 case 2:
1278 mask = 6; /* Mask bit 2:1 in the SID field */
1279 break;
1280 case 3:
1281 mask = 7; /* Mask bit 2:0 in the SID field */
1282 break;
1283 }
6cb99acc 1284 mask = ~mask;
bc535e59
PX		 1285
1286 bus_n = VTD_SID_TO_BUS(source_id);
1287 vtd_bus = vtd_find_as_from_bus_num(s, bus_n);
7df953bd 1288 if (vtd_bus) {
d92fa2dc 1289 devfn = VTD_SID_TO_DEVFN(source_id);
bf33cc75 1290 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 1291 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc 1292 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
bc535e59
PX		 1293 trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
1294 VTD_PCI_FUNC(devfn_it));
d92fa2dc 1295 vtd_as->context_cache_entry.context_cache_gen = 0;
dbaabb25
PX		 1296 /*
1297 * Do switch address space when needed, in case if the
1298 * device passthrough bit is switched.
1299 */
1300 vtd_switch_address_space(vtd_as);
dd4d607e
PX		 1301 /*
1302 * So a device is moving out of (or moving into) a
1303 * domain, a replay() suites here to notify all the
1304 * IOMMU_NOTIFIER_MAP registers about this change.
1305 * This won't bring bad even if we have no such
1306 * notifier registered - the IOMMU notification
1307 * framework will skip MAP notifications if that
1308 * happened.
1309 */
1310 memory_region_iommu_replay_all(&vtd_as->iommu);
d92fa2dc
LT		 1311 }
1312 }
1313 }
1314}
1315
1da12ec4
LT		 1316/* Context-cache invalidation
1317 * Returns the Context Actual Invalidation Granularity.
1318 * @val: the content of the CCMD_REG
1319 */
1320static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
1321{
1322 uint64_t caig;
1323 uint64_t type = val & VTD_CCMD_CIRG_MASK;
1324
1325 switch (type) {
d92fa2dc 1326 case VTD_CCMD_DOMAIN_INVL:
d92fa2dc 1327 /* Fall through */
1da12ec4 1328 case VTD_CCMD_GLOBAL_INVL:
1da12ec4 1329 caig = VTD_CCMD_GLOBAL_INVL_A;
d92fa2dc 1330 vtd_context_global_invalidate(s);
1da12ec4
LT		 1331 break;
1332
1333 case VTD_CCMD_DEVICE_INVL:
1da12ec4 1334 caig = VTD_CCMD_DEVICE_INVL_A;
d92fa2dc 1335 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
1da12ec4
LT		 1336 break;
1337
1338 default:
7feb51b7 1339 trace_vtd_err("Context cache invalidate type error.");
1da12ec4
LT		 1340 caig = 0;
1341 }
1342 return caig;
1343}
1344
b5a280c0
LT		 1345static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)
1346{
7feb51b7 1347 trace_vtd_inv_desc_iotlb_global();
b5a280c0 1348 vtd_reset_iotlb(s);
dd4d607e 1349 vtd_iommu_replay_all(s);
b5a280c0
LT		 1350}
1351
1352static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
1353{
dd4d607e
PX		 1354 IntelIOMMUNotifierNode *node;
1355 VTDContextEntry ce;
1356 VTDAddressSpace *vtd_as;
1357
7feb51b7
PX		 1358 trace_vtd_inv_desc_iotlb_domain(domain_id);
1359
b5a280c0
LT		 1360 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,
1361 &domain_id);
dd4d607e
PX		 1362
1363 QLIST_FOREACH(node, &s->notifiers_list, next) {
1364 vtd_as = node->vtd_as;
1365 if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1366 vtd_as->devfn, &ce) &&
1367 domain_id == VTD_CONTEXT_ENTRY_DID(ce.hi)) {
1368 memory_region_iommu_replay_all(&vtd_as->iommu);
1369 }
1370 }
1371}
1372
1373static int vtd_page_invalidate_notify_hook(IOMMUTLBEntry *entry,
1374 void *private)
1375{
3df9d748 1376 memory_region_notify_iommu((IOMMUMemoryRegion *)private, *entry);
dd4d607e
PX		 1377 return 0;
1378}
1379
1380static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
1381 uint16_t domain_id, hwaddr addr,
1382 uint8_t am)
1383{
1384 IntelIOMMUNotifierNode *node;
1385 VTDContextEntry ce;
1386 int ret;
1387
1388 QLIST_FOREACH(node, &(s->notifiers_list), next) {
1389 VTDAddressSpace *vtd_as = node->vtd_as;
1390 ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1391 vtd_as->devfn, &ce);
1392 if (!ret && domain_id == VTD_CONTEXT_ENTRY_DID(ce.hi)) {
1393 vtd_page_walk(&ce, addr, addr + (1 << am) * VTD_PAGE_SIZE,
1394 vtd_page_invalidate_notify_hook,
1395 (void *)&vtd_as->iommu, true);
1396 }
1397 }
b5a280c0
LT		 1398}
1399
1400static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
1401 hwaddr addr, uint8_t am)
1402{
1403 VTDIOTLBPageInvInfo info;
1404
7feb51b7
PX		 1405 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am);
1406
b5a280c0
LT		 1407 assert(am <= VTD_MAMV);
1408 info.domain_id = domain_id;
d66b969b 1409 info.addr = addr;
b5a280c0
LT		 1410 info.mask = ~((1 << am) - 1);
1411 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
dd4d607e 1412 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am);
b5a280c0
LT		 1413}
1414
1da12ec4
LT		 1415/* Flush IOTLB
1416 * Returns the IOTLB Actual Invalidation Granularity.
1417 * @val: the content of the IOTLB_REG
1418 */
1419static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
1420{
1421 uint64_t iaig;
1422 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK;
b5a280c0
LT		 1423 uint16_t domain_id;
1424 hwaddr addr;
1425 uint8_t am;
1da12ec4
LT		 1426
1427 switch (type) {
1428 case VTD_TLB_GLOBAL_FLUSH:
1da12ec4 1429 iaig = VTD_TLB_GLOBAL_FLUSH_A;
b5a280c0 1430 vtd_iotlb_global_invalidate(s);
1da12ec4
LT		 1431 break;
1432
1433 case VTD_TLB_DSI_FLUSH:
b5a280c0 1434 domain_id = VTD_TLB_DID(val);
1da12ec4 1435 iaig = VTD_TLB_DSI_FLUSH_A;
b5a280c0 1436 vtd_iotlb_domain_invalidate(s, domain_id);
1da12ec4
LT		 1437 break;
1438
1439 case VTD_TLB_PSI_FLUSH:
b5a280c0
LT		 1440 domain_id = VTD_TLB_DID(val);
1441 addr = vtd_get_quad_raw(s, DMAR_IVA_REG);
1442 am = VTD_IVA_AM(addr);
1443 addr = VTD_IVA_ADDR(addr);
b5a280c0 1444 if (am > VTD_MAMV) {
7feb51b7 1445 trace_vtd_err("IOTLB PSI flush: address mask overflow.");
b5a280c0
LT		 1446 iaig = 0;
1447 break;
1448 }
1da12ec4 1449 iaig = VTD_TLB_PSI_FLUSH_A;
b5a280c0 1450 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1da12ec4
LT		 1451 break;
1452
1453 default:
7feb51b7 1454 trace_vtd_err("IOTLB flush: invalid granularity.");
1da12ec4
LT		 1455 iaig = 0;
1456 }
1457 return iaig;
1458}
1459
8991c460 1460static void vtd_fetch_inv_desc(IntelIOMMUState *s);
ed7b8fbc
LT		 1461
1462static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
1463{
1464 return s->qi_enabled && (s->iq_tail == s->iq_head) &&
1465 (s->iq_last_desc_type == VTD_INV_DESC_WAIT);
1466}
1467
1468static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
1469{
1470 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG);
1471
7feb51b7
PX		 1472 trace_vtd_inv_qi_enable(en);
1473
ed7b8fbc 1474 if (en) {
92e5d85e 1475 s->iq = iqa_val & VTD_IQA_IQA_MASK(VTD_HOST_ADDRESS_WIDTH);
8991c460
LP		 1476 /* 2^(x+8) entries */
1477 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
1478 s->qi_enabled = true;
1479 trace_vtd_inv_qi_setup(s->iq, s->iq_size);
1480 /* Ok - report back to driver */
1481 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
1482
1483 if (s->iq_tail != 0) {
1484 /*
1485 * This is a spec violation but Windows guests are known to set up
1486 * Queued Invalidation this way so we allow the write and process
1487 * Invalidation Descriptors right away.
1488 */
1489 trace_vtd_warn_invalid_qi_tail(s->iq_tail);
1490 if (!(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
1491 vtd_fetch_inv_desc(s);
1492 }
ed7b8fbc
LT		 1493 }
1494 } else {
1495 if (vtd_queued_inv_disable_check(s)) {
1496 /* disable Queued Invalidation */
1497 vtd_set_quad_raw(s, DMAR_IQH_REG, 0);
1498 s->iq_head = 0;
1499 s->qi_enabled = false;
1500 /* Ok - report back to driver */
1501 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
1502 } else {
7feb51b7 1503 trace_vtd_err_qi_disable(s->iq_head, s->iq_tail, s->iq_last_desc_type);
ed7b8fbc
LT		 1504 }
1505 }
1506}
1507
1da12ec4
LT		 1508/* Set Root Table Pointer */
1509static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
1510{
1da12ec4
LT		 1511 vtd_root_table_setup(s);
1512 /* Ok - report back to driver */
1513 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
1514}
1515
a5861439
PX		 1516/* Set Interrupt Remap Table Pointer */
1517static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
1518{
a5861439
PX		 1519 vtd_interrupt_remap_table_setup(s);
1520 /* Ok - report back to driver */
1521 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
1522}
1523
1da12ec4
LT		 1524/* Handle Translation Enable/Disable */
1525static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
1526{
558e0024
PX		 1527 if (s->dmar_enabled == en) {
1528 return;
1529 }
1530
7feb51b7 1531 trace_vtd_dmar_enable(en);
1da12ec4
LT		 1532
1533 if (en) {
1534 s->dmar_enabled = true;
1535 /* Ok - report back to driver */
1536 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES);
1537 } else {
1538 s->dmar_enabled = false;
1539
1540 /* Clear the index of Fault Recording Register */
1541 s->next_frcd_reg = 0;
1542 /* Ok - report back to driver */
1543 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
1544 }
558e0024
PX		 1545
1546 vtd_switch_address_space_all(s);
1da12ec4
LT		 1547}
1548
80de52ba
PX		 1549/* Handle Interrupt Remap Enable/Disable */
1550static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
1551{
7feb51b7 1552 trace_vtd_ir_enable(en);
80de52ba
PX		 1553
1554 if (en) {
1555 s->intr_enabled = true;
1556 /* Ok - report back to driver */
1557 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
1558 } else {
1559 s->intr_enabled = false;
1560 /* Ok - report back to driver */
1561 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
1562 }
1563}
1564
1da12ec4
LT		 1565/* Handle write to Global Command Register */
1566static void vtd_handle_gcmd_write(IntelIOMMUState *s)
1567{
1568 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
1569 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
1570 uint32_t changed = status ^ val;
1571
7feb51b7 1572 trace_vtd_reg_write_gcmd(status, val);
1da12ec4
LT		 1573 if (changed & VTD_GCMD_TE) {
1574 /* Translation enable/disable */
1575 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
1576 }
1577 if (val & VTD_GCMD_SRTP) {
1578 /* Set/update the root-table pointer */
1579 vtd_handle_gcmd_srtp(s);
1580 }
ed7b8fbc
LT		 1581 if (changed & VTD_GCMD_QIE) {
1582 /* Queued Invalidation Enable */
1583 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
1584 }
a5861439
PX		 1585 if (val & VTD_GCMD_SIRTP) {
1586 /* Set/update the interrupt remapping root-table pointer */
1587 vtd_handle_gcmd_sirtp(s);
1588 }
80de52ba
PX		 1589 if (changed & VTD_GCMD_IRE) {
1590 /* Interrupt remap enable/disable */
1591 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
1592 }
1da12ec4
LT		 1593}
1594
1595/* Handle write to Context Command Register */
1596static void vtd_handle_ccmd_write(IntelIOMMUState *s)
1597{
1598 uint64_t ret;
1599 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
1600
1601 /* Context-cache invalidation request */
1602 if (val & VTD_CCMD_ICC) {
ed7b8fbc 1603 if (s->qi_enabled) {
7feb51b7
PX		 1604 trace_vtd_err("Queued Invalidation enabled, "
1605 "should not use register-based invalidation");
ed7b8fbc
LT		 1606 return;
1607 }
1da12ec4
LT		 1608 ret = vtd_context_cache_invalidate(s, val);
1609 /* Invalidation completed. Change something to show */
1610 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL);
1611 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK,
1612 ret);
1da12ec4
LT		 1613 }
1614}
1615
1616/* Handle write to IOTLB Invalidation Register */
1617static void vtd_handle_iotlb_write(IntelIOMMUState *s)
1618{
1619 uint64_t ret;
1620 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG);
1621
1622 /* IOTLB invalidation request */
1623 if (val & VTD_TLB_IVT) {
ed7b8fbc 1624 if (s->qi_enabled) {
7feb51b7
PX		 1625 trace_vtd_err("Queued Invalidation enabled, "
1626 "should not use register-based invalidation.");
ed7b8fbc
LT		 1627 return;
1628 }
1da12ec4
LT		 1629 ret = vtd_iotlb_flush(s, val);
1630 /* Invalidation completed. Change something to show */
1631 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL);
1632 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG,
1633 VTD_TLB_FLUSH_GRANU_MASK_A, ret);
1da12ec4
LT		 1634 }
1635}
1636
ed7b8fbc
LT		 1637/* Fetch an Invalidation Descriptor from the Invalidation Queue */
1638static bool vtd_get_inv_desc(dma_addr_t base_addr, uint32_t offset,
1639 VTDInvDesc *inv_desc)
1640{
1641 dma_addr_t addr = base_addr + offset * sizeof(*inv_desc);
1642 if (dma_memory_read(&address_space_memory, addr, inv_desc,
1643 sizeof(*inv_desc))) {
7feb51b7 1644 trace_vtd_err("Read INV DESC failed.");
ed7b8fbc
LT		 1645 inv_desc->lo = 0;
1646 inv_desc->hi = 0;
ed7b8fbc
LT		 1647 return false;
1648 }
1649 inv_desc->lo = le64_to_cpu(inv_desc->lo);
1650 inv_desc->hi = le64_to_cpu(inv_desc->hi);
1651 return true;
1652}
1653
1654static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1655{
1656 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
1657 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
bc535e59 1658 trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1659 return false;
1660 }
1661 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
1662 /* Status Write */
1663 uint32_t status_data = (uint32_t)(inv_desc->lo >>
1664 VTD_INV_DESC_WAIT_DATA_SHIFT);
1665
1666 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF));
1667
1668 /* FIXME: need to be masked with HAW? */
1669 dma_addr_t status_addr = inv_desc->hi;
bc535e59 1670 trace_vtd_inv_desc_wait_sw(status_addr, status_data);
ed7b8fbc
LT		 1671 status_data = cpu_to_le32(status_data);
1672 if (dma_memory_write(&address_space_memory, status_addr, &status_data,
1673 sizeof(status_data))) {
bc535e59 1674 trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1675 return false;
1676 }
1677 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
1678 /* Interrupt flag */
ed7b8fbc
LT		 1679 vtd_generate_completion_event(s);
1680 } else {
bc535e59 1681 trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1682 return false;
1683 }
1684 return true;
1685}
1686
d92fa2dc
LT		 1687static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
1688 VTDInvDesc *inv_desc)
1689{
bc535e59
PX		 1690 uint16_t sid, fmask;
1691
d92fa2dc 1692 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
bc535e59 1693 trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
d92fa2dc
LT		 1694 return false;
1695 }
1696 switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
1697 case VTD_INV_DESC_CC_DOMAIN:
bc535e59
PX		 1698 trace_vtd_inv_desc_cc_domain(
1699 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
d92fa2dc
LT		 1700 /* Fall through */
1701 case VTD_INV_DESC_CC_GLOBAL:
d92fa2dc
LT		 1702 vtd_context_global_invalidate(s);
1703 break;
1704
1705 case VTD_INV_DESC_CC_DEVICE:
bc535e59
PX		 1706 sid = VTD_INV_DESC_CC_SID(inv_desc->lo);
1707 fmask = VTD_INV_DESC_CC_FM(inv_desc->lo);
1708 vtd_context_device_invalidate(s, sid, fmask);
d92fa2dc
LT		 1709 break;
1710
1711 default:
bc535e59 1712 trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
d92fa2dc
LT		 1713 return false;
1714 }
1715 return true;
1716}
1717
b5a280c0
LT		 1718static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1719{
1720 uint16_t domain_id;
1721 uint8_t am;
1722 hwaddr addr;
1723
1724 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
1725 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
bc535e59 1726 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1727 return false;
1728 }
1729
1730 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
1731 case VTD_INV_DESC_IOTLB_GLOBAL:
b5a280c0
LT		 1732 vtd_iotlb_global_invalidate(s);
1733 break;
1734
1735 case VTD_INV_DESC_IOTLB_DOMAIN:
1736 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
b5a280c0
LT		 1737 vtd_iotlb_domain_invalidate(s, domain_id);
1738 break;
1739
1740 case VTD_INV_DESC_IOTLB_PAGE:
1741 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1742 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
1743 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
b5a280c0 1744 if (am > VTD_MAMV) {
bc535e59 1745 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1746 return false;
1747 }
1748 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1749 break;
1750
1751 default:
bc535e59 1752 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1753 return false;
1754 }
1755 return true;
1756}
1757
02a2cbc8
PX		 1758static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
1759 VTDInvDesc *inv_desc)
1760{
7feb51b7
PX		 1761 trace_vtd_inv_desc_iec(inv_desc->iec.granularity,
1762 inv_desc->iec.index,
1763 inv_desc->iec.index_mask);
02a2cbc8
PX		 1764
1765 vtd_iec_notify_all(s, !inv_desc->iec.granularity,
1766 inv_desc->iec.index,
1767 inv_desc->iec.index_mask);
554f5e16
JW		 1768 return true;
1769}
1770
1771static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
1772 VTDInvDesc *inv_desc)
1773{
1774 VTDAddressSpace *vtd_dev_as;
1775 IOMMUTLBEntry entry;
1776 struct VTDBus *vtd_bus;
1777 hwaddr addr;
1778 uint64_t sz;
1779 uint16_t sid;
1780 uint8_t devfn;
1781 bool size;
1782 uint8_t bus_num;
1783
1784 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
1785 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
1786 devfn = sid & 0xff;
1787 bus_num = sid >> 8;
1788 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi);
1789
1790 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) ||
1791 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) {
7feb51b7 1792 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
554f5e16
JW		 1793 return false;
1794 }
1795
1796 vtd_bus = vtd_find_as_from_bus_num(s, bus_num);
1797 if (!vtd_bus) {
1798 goto done;
1799 }
1800
1801 vtd_dev_as = vtd_bus->dev_as[devfn];
1802 if (!vtd_dev_as) {
1803 goto done;
1804 }
1805
04eb6247
JW		 1806 /* According to ATS spec table 2.4:
1807 * S = 0, bits 15:12 = xxxx range size: 4K
1808 * S = 1, bits 15:12 = xxx0 range size: 8K
1809 * S = 1, bits 15:12 = xx01 range size: 16K
1810 * S = 1, bits 15:12 = x011 range size: 32K
1811 * S = 1, bits 15:12 = 0111 range size: 64K
1812 * ...
1813 */
554f5e16 1814 if (size) {
04eb6247 1815 sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
554f5e16
JW		 1816 addr &= ~(sz - 1);
1817 } else {
1818 sz = VTD_PAGE_SIZE;
1819 }
02a2cbc8 1820
554f5e16
JW		 1821 entry.target_as = &vtd_dev_as->as;
1822 entry.addr_mask = sz - 1;
1823 entry.iova = addr;
1824 entry.perm = IOMMU_NONE;
1825 entry.translated_addr = 0;
10315b9b 1826 memory_region_notify_iommu(&vtd_dev_as->iommu, entry);
554f5e16
JW		 1827
1828done:
02a2cbc8
PX		 1829 return true;
1830}
1831
ed7b8fbc
LT		 1832static bool vtd_process_inv_desc(IntelIOMMUState *s)
1833{
1834 VTDInvDesc inv_desc;
1835 uint8_t desc_type;
1836
7feb51b7 1837 trace_vtd_inv_qi_head(s->iq_head);
ed7b8fbc
LT		 1838 if (!vtd_get_inv_desc(s->iq, s->iq_head, &inv_desc)) {
1839 s->iq_last_desc_type = VTD_INV_DESC_NONE;
1840 return false;
1841 }
1842 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE;
1843 /* FIXME: should update at first or at last? */
1844 s->iq_last_desc_type = desc_type;
1845
1846 switch (desc_type) {
1847 case VTD_INV_DESC_CC:
bc535e59 1848 trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo);
d92fa2dc
LT		 1849 if (!vtd_process_context_cache_desc(s, &inv_desc)) {
1850 return false;
1851 }
ed7b8fbc
LT		 1852 break;
1853
1854 case VTD_INV_DESC_IOTLB:
bc535e59 1855 trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo);
b5a280c0
LT		 1856 if (!vtd_process_iotlb_desc(s, &inv_desc)) {
1857 return false;
1858 }
ed7b8fbc
LT		 1859 break;
1860
1861 case VTD_INV_DESC_WAIT:
bc535e59 1862 trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo);
ed7b8fbc
LT		 1863 if (!vtd_process_wait_desc(s, &inv_desc)) {
1864 return false;
1865 }
1866 break;
1867
b7910472 1868 case VTD_INV_DESC_IEC:
bc535e59 1869 trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo);
02a2cbc8
PX		 1870 if (!vtd_process_inv_iec_desc(s, &inv_desc)) {
1871 return false;
1872 }
b7910472
PX		 1873 break;
1874
554f5e16 1875 case VTD_INV_DESC_DEVICE:
7feb51b7 1876 trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo);
554f5e16
JW		 1877 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
1878 return false;
1879 }
1880 break;
1881
ed7b8fbc 1882 default:
bc535e59 1883 trace_vtd_inv_desc_invalid(inv_desc.hi, inv_desc.lo);
ed7b8fbc
LT		 1884 return false;
1885 }
1886 s->iq_head++;
1887 if (s->iq_head == s->iq_size) {
1888 s->iq_head = 0;
1889 }
1890 return true;
1891}
1892
1893/* Try to fetch and process more Invalidation Descriptors */
1894static void vtd_fetch_inv_desc(IntelIOMMUState *s)
1895{
7feb51b7
PX		 1896 trace_vtd_inv_qi_fetch();
1897
ed7b8fbc
LT		 1898 if (s->iq_tail >= s->iq_size) {
1899 /* Detects an invalid Tail pointer */
7feb51b7 1900 trace_vtd_err_qi_tail(s->iq_tail, s->iq_size);
ed7b8fbc
LT		 1901 vtd_handle_inv_queue_error(s);
1902 return;
1903 }
1904 while (s->iq_head != s->iq_tail) {
1905 if (!vtd_process_inv_desc(s)) {
1906 /* Invalidation Queue Errors */
1907 vtd_handle_inv_queue_error(s);
1908 break;
1909 }
1910 /* Must update the IQH_REG in time */
1911 vtd_set_quad_raw(s, DMAR_IQH_REG,
1912 (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &
1913 VTD_IQH_QH_MASK);
1914 }
1915}
1916
1917/* Handle write to Invalidation Queue Tail Register */
1918static void vtd_handle_iqt_write(IntelIOMMUState *s)
1919{
1920 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG);
1921
1922 s->iq_tail = VTD_IQT_QT(val);
7feb51b7
PX		 1923 trace_vtd_inv_qi_tail(s->iq_tail);
1924
ed7b8fbc
LT		 1925 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
1926 /* Process Invalidation Queue here */
1927 vtd_fetch_inv_desc(s);
1928 }
1929}
1930
1da12ec4
LT		 1931static void vtd_handle_fsts_write(IntelIOMMUState *s)
1932{
1933 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
1934 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1935 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE;
1936
1937 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) {
1938 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
7feb51b7 1939 trace_vtd_fsts_clear_ip();
1da12ec4 1940 }
ed7b8fbc
LT		 1941 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
1942 * Descriptors if there are any when Queued Invalidation is enabled?
1943 */
1da12ec4
LT		 1944}
1945
1946static void vtd_handle_fectl_write(IntelIOMMUState *s)
1947{
1948 uint32_t fectl_reg;
1949 /* FIXME: when software clears the IM field, check the IP field. But do we
1950 * need to compare the old value and the new value to conclude that
1951 * software clears the IM field? Or just check if the IM field is zero?
1952 */
1953 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
7feb51b7
PX		 1954
1955 trace_vtd_reg_write_fectl(fectl_reg);
1956
1da12ec4
LT		 1957 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) {
1958 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
1959 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1da12ec4
LT		 1960 }
1961}
1962
ed7b8fbc
LT		 1963static void vtd_handle_ics_write(IntelIOMMUState *s)
1964{
1965 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG);
1966 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1967
1968 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) {
7feb51b7 1969 trace_vtd_reg_ics_clear_ip();
ed7b8fbc 1970 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
ed7b8fbc
LT		 1971 }
1972}
1973
1974static void vtd_handle_iectl_write(IntelIOMMUState *s)
1975{
1976 uint32_t iectl_reg;
1977 /* FIXME: when software clears the IM field, check the IP field. But do we
1978 * need to compare the old value and the new value to conclude that
1979 * software clears the IM field? Or just check if the IM field is zero?
1980 */
1981 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
7feb51b7
PX		 1982
1983 trace_vtd_reg_write_iectl(iectl_reg);
1984
ed7b8fbc
LT		 1985 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) {
1986 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
1987 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
ed7b8fbc
LT		 1988 }
1989}
1990
1da12ec4
LT		 1991static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
1992{
1993 IntelIOMMUState *s = opaque;
1994 uint64_t val;
1995
7feb51b7
PX		 1996 trace_vtd_reg_read(addr, size);
1997
1da12ec4 1998 if (addr + size > DMAR_REG_SIZE) {
7feb51b7 1999 trace_vtd_err("Read MMIO over range.");
1da12ec4
LT		 2000 return (uint64_t)-1;
2001 }
2002
2003 switch (addr) {
2004 /* Root Table Address Register, 64-bit */
2005 case DMAR_RTADDR_REG:
2006 if (size == 4) {
2007 val = s->root & ((1ULL << 32) - 1);
2008 } else {
2009 val = s->root;
2010 }
2011 break;
2012
2013 case DMAR_RTADDR_REG_HI:
2014 assert(size == 4);
2015 val = s->root >> 32;
2016 break;
2017
ed7b8fbc
LT		 2018 /* Invalidation Queue Address Register, 64-bit */
2019 case DMAR_IQA_REG:
2020 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
2021 if (size == 4) {
2022 val = val & ((1ULL << 32) - 1);
2023 }
2024 break;
2025
2026 case DMAR_IQA_REG_HI:
2027 assert(size == 4);
2028 val = s->iq >> 32;
2029 break;
2030
1da12ec4
LT		 2031 default:
2032 if (size == 4) {
2033 val = vtd_get_long(s, addr);
2034 } else {
2035 val = vtd_get_quad(s, addr);
2036 }
2037 }
7feb51b7 2038
1da12ec4
LT		 2039 return val;
2040}
2041
2042static void vtd_mem_write(void *opaque, hwaddr addr,
2043 uint64_t val, unsigned size)
2044{
2045 IntelIOMMUState *s = opaque;
2046
7feb51b7
PX		 2047 trace_vtd_reg_write(addr, size, val);
2048
1da12ec4 2049 if (addr + size > DMAR_REG_SIZE) {
7feb51b7 2050 trace_vtd_err("Write MMIO over range.");
1da12ec4
LT		 2051 return;
2052 }
2053
2054 switch (addr) {
2055 /* Global Command Register, 32-bit */
2056 case DMAR_GCMD_REG:
1da12ec4
LT		 2057 vtd_set_long(s, addr, val);
2058 vtd_handle_gcmd_write(s);
2059 break;
2060
2061 /* Context Command Register, 64-bit */
2062 case DMAR_CCMD_REG:
1da12ec4
LT		 2063 if (size == 4) {
2064 vtd_set_long(s, addr, val);
2065 } else {
2066 vtd_set_quad(s, addr, val);
2067 vtd_handle_ccmd_write(s);
2068 }
2069 break;
2070
2071 case DMAR_CCMD_REG_HI:
1da12ec4
LT		 2072 assert(size == 4);
2073 vtd_set_long(s, addr, val);
2074 vtd_handle_ccmd_write(s);
2075 break;
2076
2077 /* IOTLB Invalidation Register, 64-bit */
2078 case DMAR_IOTLB_REG:
1da12ec4
LT		 2079 if (size == 4) {
2080 vtd_set_long(s, addr, val);
2081 } else {
2082 vtd_set_quad(s, addr, val);
2083 vtd_handle_iotlb_write(s);
2084 }
2085 break;
2086
2087 case DMAR_IOTLB_REG_HI:
1da12ec4
LT		 2088 assert(size == 4);
2089 vtd_set_long(s, addr, val);
2090 vtd_handle_iotlb_write(s);
2091 break;
2092
b5a280c0
LT		 2093 /* Invalidate Address Register, 64-bit */
2094 case DMAR_IVA_REG:
b5a280c0
LT		 2095 if (size == 4) {
2096 vtd_set_long(s, addr, val);
2097 } else {
2098 vtd_set_quad(s, addr, val);
2099 }
2100 break;
2101
2102 case DMAR_IVA_REG_HI:
b5a280c0
LT		 2103 assert(size == 4);
2104 vtd_set_long(s, addr, val);
2105 break;
2106
1da12ec4
LT		 2107 /* Fault Status Register, 32-bit */
2108 case DMAR_FSTS_REG:
1da12ec4
LT		 2109 assert(size == 4);
2110 vtd_set_long(s, addr, val);
2111 vtd_handle_fsts_write(s);
2112 break;
2113
2114 /* Fault Event Control Register, 32-bit */
2115 case DMAR_FECTL_REG:
1da12ec4
LT		 2116 assert(size == 4);
2117 vtd_set_long(s, addr, val);
2118 vtd_handle_fectl_write(s);
2119 break;
2120
2121 /* Fault Event Data Register, 32-bit */
2122 case DMAR_FEDATA_REG:
1da12ec4
LT		 2123 assert(size == 4);
2124 vtd_set_long(s, addr, val);
2125 break;
2126
2127 /* Fault Event Address Register, 32-bit */
2128 case DMAR_FEADDR_REG:
1da12ec4
LT		 2129 assert(size == 4);
2130 vtd_set_long(s, addr, val);
2131 break;
2132
2133 /* Fault Event Upper Address Register, 32-bit */
2134 case DMAR_FEUADDR_REG:
1da12ec4
LT		 2135 assert(size == 4);
2136 vtd_set_long(s, addr, val);
2137 break;
2138
2139 /* Protected Memory Enable Register, 32-bit */
2140 case DMAR_PMEN_REG:
1da12ec4
LT		 2141 assert(size == 4);
2142 vtd_set_long(s, addr, val);
2143 break;
2144
2145 /* Root Table Address Register, 64-bit */
2146 case DMAR_RTADDR_REG:
1da12ec4
LT		 2147 if (size == 4) {
2148 vtd_set_long(s, addr, val);
2149 } else {
2150 vtd_set_quad(s, addr, val);
2151 }
2152 break;
2153
2154 case DMAR_RTADDR_REG_HI:
1da12ec4
LT		 2155 assert(size == 4);
2156 vtd_set_long(s, addr, val);
2157 break;
2158
ed7b8fbc
LT		 2159 /* Invalidation Queue Tail Register, 64-bit */
2160 case DMAR_IQT_REG:
ed7b8fbc
LT		 2161 if (size == 4) {
2162 vtd_set_long(s, addr, val);
2163 } else {
2164 vtd_set_quad(s, addr, val);
2165 }
2166 vtd_handle_iqt_write(s);
2167 break;
2168
2169 case DMAR_IQT_REG_HI:
ed7b8fbc
LT		 2170 assert(size == 4);
2171 vtd_set_long(s, addr, val);
2172 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2173 break;
2174
2175 /* Invalidation Queue Address Register, 64-bit */
2176 case DMAR_IQA_REG:
ed7b8fbc
LT		 2177 if (size == 4) {
2178 vtd_set_long(s, addr, val);
2179 } else {
2180 vtd_set_quad(s, addr, val);
2181 }
2182 break;
2183
2184 case DMAR_IQA_REG_HI:
ed7b8fbc
LT		 2185 assert(size == 4);
2186 vtd_set_long(s, addr, val);
2187 break;
2188
2189 /* Invalidation Completion Status Register, 32-bit */
2190 case DMAR_ICS_REG:
ed7b8fbc
LT		 2191 assert(size == 4);
2192 vtd_set_long(s, addr, val);
2193 vtd_handle_ics_write(s);
2194 break;
2195
2196 /* Invalidation Event Control Register, 32-bit */
2197 case DMAR_IECTL_REG:
ed7b8fbc
LT		 2198 assert(size == 4);
2199 vtd_set_long(s, addr, val);
2200 vtd_handle_iectl_write(s);
2201 break;
2202
2203 /* Invalidation Event Data Register, 32-bit */
2204 case DMAR_IEDATA_REG:
ed7b8fbc
LT		 2205 assert(size == 4);
2206 vtd_set_long(s, addr, val);
2207 break;
2208
2209 /* Invalidation Event Address Register, 32-bit */
2210 case DMAR_IEADDR_REG:
ed7b8fbc
LT		 2211 assert(size == 4);
2212 vtd_set_long(s, addr, val);
2213 break;
2214
2215 /* Invalidation Event Upper Address Register, 32-bit */
2216 case DMAR_IEUADDR_REG:
ed7b8fbc
LT		 2217 assert(size == 4);
2218 vtd_set_long(s, addr, val);
2219 break;
2220
1da12ec4
LT		 2221 /* Fault Recording Registers, 128-bit */
2222 case DMAR_FRCD_REG_0_0:
1da12ec4
LT		 2223 if (size == 4) {
2224 vtd_set_long(s, addr, val);
2225 } else {
2226 vtd_set_quad(s, addr, val);
2227 }
2228 break;
2229
2230 case DMAR_FRCD_REG_0_1:
1da12ec4
LT		 2231 assert(size == 4);
2232 vtd_set_long(s, addr, val);
2233 break;
2234
2235 case DMAR_FRCD_REG_0_2:
1da12ec4
LT		 2236 if (size == 4) {
2237 vtd_set_long(s, addr, val);
2238 } else {
2239 vtd_set_quad(s, addr, val);
2240 /* May clear bit 127 (Fault), update PPF */
2241 vtd_update_fsts_ppf(s);
2242 }
2243 break;
2244
2245 case DMAR_FRCD_REG_0_3:
1da12ec4
LT		 2246 assert(size == 4);
2247 vtd_set_long(s, addr, val);
2248 /* May clear bit 127 (Fault), update PPF */
2249 vtd_update_fsts_ppf(s);
2250 break;
2251
a5861439 2252 case DMAR_IRTA_REG:
a5861439
PX		 2253 if (size == 4) {
2254 vtd_set_long(s, addr, val);
2255 } else {
2256 vtd_set_quad(s, addr, val);
2257 }
2258 break;
2259
2260 case DMAR_IRTA_REG_HI:
a5861439
PX		 2261 assert(size == 4);
2262 vtd_set_long(s, addr, val);
2263 break;
2264
1da12ec4 2265 default:
1da12ec4
LT		 2266 if (size == 4) {
2267 vtd_set_long(s, addr, val);
2268 } else {
2269 vtd_set_quad(s, addr, val);
2270 }
2271 }
2272}
2273
3df9d748 2274static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
bf55b7af 2275 IOMMUAccessFlags flag)
1da12ec4
LT		 2276{
2277 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
2278 IntelIOMMUState *s = vtd_as->iommu_state;
b9313021
PX		 2279 IOMMUTLBEntry iotlb = {
2280 /* We'll fill in the rest later. */
1da12ec4 2281 .target_as = &address_space_memory,
1da12ec4 2282 };
b9313021 2283 bool success;
1da12ec4 2284
b9313021
PX		 2285 if (likely(s->dmar_enabled)) {
2286 success = vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn,
2287 addr, flag & IOMMU_WO, &iotlb);
2288 } else {
1da12ec4 2289 /* DMAR disabled, passthrough, use 4k-page*/
b9313021
PX		 2290 iotlb.iova = addr & VTD_PAGE_MASK_4K;
2291 iotlb.translated_addr = addr & VTD_PAGE_MASK_4K;
2292 iotlb.addr_mask = ~VTD_PAGE_MASK_4K;
2293 iotlb.perm = IOMMU_RW;
2294 success = true;
1da12ec4
LT		 2295 }
2296
b9313021
PX		 2297 if (likely(success)) {
2298 trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus),
2299 VTD_PCI_SLOT(vtd_as->devfn),
2300 VTD_PCI_FUNC(vtd_as->devfn),
2301 iotlb.iova, iotlb.translated_addr,
2302 iotlb.addr_mask);
2303 } else {
2304 trace_vtd_err_dmar_translate(pci_bus_num(vtd_as->bus),
2305 VTD_PCI_SLOT(vtd_as->devfn),
2306 VTD_PCI_FUNC(vtd_as->devfn),
2307 iotlb.iova);
2308 }
7feb51b7 2309
b9313021 2310 return iotlb;
1da12ec4
LT		 2311}
2312
3df9d748 2313static void vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu,
5bf3d319
PX		 2314 IOMMUNotifierFlag old,
2315 IOMMUNotifierFlag new)
3cb3b154
AW		 2316{
2317 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
dd4d607e
PX		 2318 IntelIOMMUState *s = vtd_as->iommu_state;
2319 IntelIOMMUNotifierNode *node = NULL;
2320 IntelIOMMUNotifierNode *next_node = NULL;
3cb3b154 2321
dd4d607e 2322 if (!s->caching_mode && new & IOMMU_NOTIFIER_MAP) {
4c427a4c 2323 error_report("We need to set caching-mode=1 for intel-iommu to enable "
dd4d607e 2324 "device assignment with IOMMU protection.");
a3276f78
PX		 2325 exit(1);
2326 }
dd4d607e
PX		 2327
2328 if (old == IOMMU_NOTIFIER_NONE) {
2329 node = g_malloc0(sizeof(*node));
2330 node->vtd_as = vtd_as;
2331 QLIST_INSERT_HEAD(&s->notifiers_list, node, next);
2332 return;
2333 }
2334
2335 /* update notifier node with new flags */
2336 QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) {
2337 if (node->vtd_as == vtd_as) {
2338 if (new == IOMMU_NOTIFIER_NONE) {
2339 QLIST_REMOVE(node, next);
2340 g_free(node);
2341 }
2342 return;
2343 }
2344 }
3cb3b154
AW		 2345}
2346
552a1e01
PX		 2347static int vtd_post_load(void *opaque, int version_id)
2348{
2349 IntelIOMMUState *iommu = opaque;
2350
2351 /*
2352 * Memory regions are dynamically turned on/off depending on
2353 * context entry configurations from the guest. After migration,
2354 * we need to make sure the memory regions are still correct.
2355 */
2356 vtd_switch_address_space_all(iommu);
2357
2358 return 0;
2359}
2360
1da12ec4
LT		 2361static const VMStateDescription vtd_vmstate = {
2362 .name = "iommu-intel",
8cdcf3c1
PX		 2363 .version_id = 1,
2364 .minimum_version_id = 1,
2365 .priority = MIG_PRI_IOMMU,
552a1e01 2366 .post_load = vtd_post_load,
8cdcf3c1
PX		 2367 .fields = (VMStateField[]) {
2368 VMSTATE_UINT64(root, IntelIOMMUState),
2369 VMSTATE_UINT64(intr_root, IntelIOMMUState),
2370 VMSTATE_UINT64(iq, IntelIOMMUState),
2371 VMSTATE_UINT32(intr_size, IntelIOMMUState),
2372 VMSTATE_UINT16(iq_head, IntelIOMMUState),
2373 VMSTATE_UINT16(iq_tail, IntelIOMMUState),
2374 VMSTATE_UINT16(iq_size, IntelIOMMUState),
2375 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState),
2376 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE),
2377 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState),
2378 VMSTATE_BOOL(root_extended, IntelIOMMUState),
2379 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState),
2380 VMSTATE_BOOL(qi_enabled, IntelIOMMUState),
2381 VMSTATE_BOOL(intr_enabled, IntelIOMMUState),
2382 VMSTATE_BOOL(intr_eime, IntelIOMMUState),
2383 VMSTATE_END_OF_LIST()
2384 }
1da12ec4
LT		 2385};
2386
2387static const MemoryRegionOps vtd_mem_ops = {
2388 .read = vtd_mem_read,
2389 .write = vtd_mem_write,
2390 .endianness = DEVICE_LITTLE_ENDIAN,
2391 .impl = {
2392 .min_access_size = 4,
2393 .max_access_size = 8,
2394 },
2395 .valid = {
2396 .min_access_size = 4,
2397 .max_access_size = 8,
2398 },
2399};
2400
2401static Property vtd_properties[] = {
2402 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0),
e6b6af05
RK		 2403 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim,
2404 ON_OFF_AUTO_AUTO),
fb506e70 2405 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
3b40f0e5 2406 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
1da12ec4
LT		 2407 DEFINE_PROP_END_OF_LIST(),
2408};
2409
651e4cef
PX		 2410/* Read IRTE entry with specific index */
2411static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
bc38ee10 2412 VTD_IR_TableEntry *entry, uint16_t sid)
651e4cef 2413{
ede9c94a
PX		 2414 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
2415 {0xffff, 0xfffb, 0xfff9, 0xfff8};
651e4cef 2416 dma_addr_t addr = 0x00;
ede9c94a
PX		 2417 uint16_t mask, source_id;
2418 uint8_t bus, bus_max, bus_min;
651e4cef
PX		 2419
2420 addr = iommu->intr_root + index * sizeof(*entry);
2421 if (dma_memory_read(&address_space_memory, addr, entry,
2422 sizeof(*entry))) {
7feb51b7 2423 trace_vtd_err("Memory read failed for IRTE.");
651e4cef
PX		 2424 return -VTD_FR_IR_ROOT_INVAL;
2425 }
2426
7feb51b7
PX		 2427 trace_vtd_ir_irte_get(index, le64_to_cpu(entry->data[1]),
2428 le64_to_cpu(entry->data[0]));
2429
bc38ee10 2430 if (!entry->irte.present) {
7feb51b7
PX		 2431 trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]),
2432 le64_to_cpu(entry->data[0]));
651e4cef
PX		 2433 return -VTD_FR_IR_ENTRY_P;
2434 }
2435
bc38ee10
MT		 2436 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
2437 entry->irte.__reserved_2) {
7feb51b7
PX		 2438 trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]),
2439 le64_to_cpu(entry->data[0]));
651e4cef
PX		 2440 return -VTD_FR_IR_IRTE_RSVD;
2441 }
2442
ede9c94a
PX		 2443 if (sid != X86_IOMMU_SID_INVALID) {
2444 /* Validate IRTE SID */
bc38ee10
MT		 2445 source_id = le32_to_cpu(entry->irte.source_id);
2446 switch (entry->irte.sid_vtype) {
ede9c94a 2447 case VTD_SVT_NONE:
ede9c94a
PX		 2448 break;
2449
2450 case VTD_SVT_ALL:
bc38ee10 2451 mask = vtd_svt_mask[entry->irte.sid_q];
ede9c94a 2452 if ((source_id & mask) != (sid & mask)) {
7feb51b7 2453 trace_vtd_err_irte_sid(index, sid, source_id);
ede9c94a
PX		 2454 return -VTD_FR_IR_SID_ERR;
2455 }
2456 break;
2457
2458 case VTD_SVT_BUS:
2459 bus_max = source_id >> 8;
2460 bus_min = source_id & 0xff;
2461 bus = sid >> 8;
2462 if (bus > bus_max || bus < bus_min) {
7feb51b7 2463 trace_vtd_err_irte_sid_bus(index, bus, bus_min, bus_max);
ede9c94a
PX		 2464 return -VTD_FR_IR_SID_ERR;
2465 }
2466 break;
2467
2468 default:
7feb51b7 2469 trace_vtd_err_irte_svt(index, entry->irte.sid_vtype);
ede9c94a
PX		 2470 /* Take this as verification failure. */
2471 return -VTD_FR_IR_SID_ERR;
2472 break;
2473 }
2474 }
651e4cef
PX		 2475
2476 return 0;
2477}
2478
2479/* Fetch IRQ information of specific IR index */
ede9c94a
PX		 2480static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
2481 VTDIrq *irq, uint16_t sid)
651e4cef 2482{
bc38ee10 2483 VTD_IR_TableEntry irte = {};
651e4cef
PX		 2484 int ret = 0;
2485
ede9c94a 2486 ret = vtd_irte_get(iommu, index, &irte, sid);
651e4cef
PX		 2487 if (ret) {
2488 return ret;
2489 }
2490
bc38ee10
MT		 2491 irq->trigger_mode = irte.irte.trigger_mode;
2492 irq->vector = irte.irte.vector;
2493 irq->delivery_mode = irte.irte.delivery_mode;
2494 irq->dest = le32_to_cpu(irte.irte.dest_id);
28589311 2495 if (!iommu->intr_eime) {
651e4cef
PX		 2496#define VTD_IR_APIC_DEST_MASK (0xff00ULL)
2497#define VTD_IR_APIC_DEST_SHIFT (8)
28589311
JK		 2498 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
2499 VTD_IR_APIC_DEST_SHIFT;
2500 }
bc38ee10
MT		 2501 irq->dest_mode = irte.irte.dest_mode;
2502 irq->redir_hint = irte.irte.redir_hint;
651e4cef 2503
7feb51b7
PX		 2504 trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector,
2505 irq->delivery_mode, irq->dest, irq->dest_mode);
651e4cef
PX		 2506
2507 return 0;
2508}
2509
2510/* Generate one MSI message from VTDIrq info */
2511static void vtd_generate_msi_message(VTDIrq *irq, MSIMessage *msg_out)
2512{
2513 VTD_MSIMessage msg = {};
2514
2515 /* Generate address bits */
2516 msg.dest_mode = irq->dest_mode;
2517 msg.redir_hint = irq->redir_hint;
2518 msg.dest = irq->dest;
32946019 2519 msg.__addr_hi = irq->dest & 0xffffff00;
651e4cef
PX		 2520 msg.__addr_head = cpu_to_le32(0xfee);
2521 /* Keep this from original MSI address bits */
2522 msg.__not_used = irq->msi_addr_last_bits;
2523
2524 /* Generate data bits */
2525 msg.vector = irq->vector;
2526 msg.delivery_mode = irq->delivery_mode;
2527 msg.level = 1;
2528 msg.trigger_mode = irq->trigger_mode;
2529
2530 msg_out->address = msg.msi_addr;
2531 msg_out->data = msg.msi_data;
2532}
2533
2534/* Interrupt remapping for MSI/MSI-X entry */
2535static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
2536 MSIMessage *origin,
ede9c94a
PX		 2537 MSIMessage *translated,
2538 uint16_t sid)
651e4cef
PX		 2539{
2540 int ret = 0;
2541 VTD_IR_MSIAddress addr;
2542 uint16_t index;
09cd058a 2543 VTDIrq irq = {};
651e4cef
PX		 2544
2545 assert(origin && translated);
2546
7feb51b7
PX		 2547 trace_vtd_ir_remap_msi_req(origin->address, origin->data);
2548
651e4cef 2549 if (!iommu || !iommu->intr_enabled) {
e7a3b91f
PX		 2550 memcpy(translated, origin, sizeof(*origin));
2551 goto out;
651e4cef
PX		 2552 }
2553
2554 if (origin->address & VTD_MSI_ADDR_HI_MASK) {
7feb51b7
PX		 2555 trace_vtd_err("MSI address high 32 bits non-zero when "
2556 "Interrupt Remapping enabled.");
651e4cef
PX		 2557 return -VTD_FR_IR_REQ_RSVD;
2558 }
2559
2560 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
1a43713b 2561 if (addr.addr.__head != 0xfee) {
7feb51b7 2562 trace_vtd_err("MSI addr low 32 bit invalid.");
651e4cef
PX		 2563 return -VTD_FR_IR_REQ_RSVD;
2564 }
2565
2566 /* This is compatible mode. */
bc38ee10 2567 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
e7a3b91f
PX		 2568 memcpy(translated, origin, sizeof(*origin));
2569 goto out;
651e4cef
PX		 2570 }
2571
bc38ee10 2572 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l);
651e4cef
PX		 2573
2574#define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
2575#define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
2576
bc38ee10 2577 if (addr.addr.sub_valid) {
651e4cef
PX		 2578 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2579 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
2580 }
2581
ede9c94a 2582 ret = vtd_remap_irq_get(iommu, index, &irq, sid);
651e4cef
PX		 2583 if (ret) {
2584 return ret;
2585 }
2586
bc38ee10 2587 if (addr.addr.sub_valid) {
7feb51b7 2588 trace_vtd_ir_remap_type("MSI");
651e4cef 2589 if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
7feb51b7 2590 trace_vtd_err_ir_msi_invalid(sid, origin->address, origin->data);
651e4cef
PX		 2591 return -VTD_FR_IR_REQ_RSVD;
2592 }
2593 } else {
2594 uint8_t vector = origin->data & 0xff;
dea651a9
FW		 2595 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
2596
7feb51b7 2597 trace_vtd_ir_remap_type("IOAPIC");
651e4cef
PX		 2598 /* IOAPIC entry vector should be aligned with IRTE vector
2599 * (see vt-d spec 5.1.5.1). */
2600 if (vector != irq.vector) {
7feb51b7 2601 trace_vtd_warn_ir_vector(sid, index, vector, irq.vector);
651e4cef 2602 }
dea651a9
FW		 2603
2604 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
2605 * (see vt-d spec 5.1.5.1). */
2606 if (trigger_mode != irq.trigger_mode) {
7feb51b7
PX		 2607 trace_vtd_warn_ir_trigger(sid, index, trigger_mode,
2608 irq.trigger_mode);
dea651a9 2609 }
651e4cef
PX		 2610 }
2611
2612 /*
2613 * We'd better keep the last two bits, assuming that guest OS
2614 * might modify it. Keep it does not hurt after all.
2615 */
bc38ee10 2616 irq.msi_addr_last_bits = addr.addr.__not_care;
651e4cef
PX		 2617
2618 /* Translate VTDIrq to MSI message */
2619 vtd_generate_msi_message(&irq, translated);
2620
e7a3b91f 2621out:
7feb51b7
PX		 2622 trace_vtd_ir_remap_msi(origin->address, origin->data,
2623 translated->address, translated->data);
651e4cef
PX		 2624 return 0;
2625}
2626
8b5ed7df
PX		 2627static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
2628 MSIMessage *dst, uint16_t sid)
2629{
ede9c94a
PX		 2630 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu),
2631 src, dst, sid);
8b5ed7df
PX		 2632}
2633
651e4cef
PX		 2634static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
2635 uint64_t *data, unsigned size,
2636 MemTxAttrs attrs)
2637{
2638 return MEMTX_OK;
2639}
2640
2641static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
2642 uint64_t value, unsigned size,
2643 MemTxAttrs attrs)
2644{
2645 int ret = 0;
09cd058a 2646 MSIMessage from = {}, to = {};
ede9c94a 2647 uint16_t sid = X86_IOMMU_SID_INVALID;
651e4cef
PX		 2648
2649 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
2650 from.data = (uint32_t) value;
2651
ede9c94a
PX		 2652 if (!attrs.unspecified) {
2653 /* We have explicit Source ID */
2654 sid = attrs.requester_id;
2655 }
2656
2657 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
651e4cef
PX		 2658 if (ret) {
2659 /* TODO: report error */
651e4cef
PX		 2660 /* Drop this interrupt */
2661 return MEMTX_ERROR;
2662 }
2663
32946019 2664 apic_get_class()->send_msi(&to);
651e4cef
PX		 2665
2666 return MEMTX_OK;
2667}
2668
2669static const MemoryRegionOps vtd_mem_ir_ops = {
2670 .read_with_attrs = vtd_mem_ir_read,
2671 .write_with_attrs = vtd_mem_ir_write,
2672 .endianness = DEVICE_LITTLE_ENDIAN,
2673 .impl = {
2674 .min_access_size = 4,
2675 .max_access_size = 4,
2676 },
2677 .valid = {
2678 .min_access_size = 4,
2679 .max_access_size = 4,
2680 },
2681};
7df953bd
KO		 2682
2683VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
2684{
2685 uintptr_t key = (uintptr_t)bus;
2686 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
2687 VTDAddressSpace *vtd_dev_as;
e0a3c8cc 2688 char name[128];
7df953bd
KO		 2689
2690 if (!vtd_bus) {
2d3fc581
JW		 2691 uintptr_t *new_key = g_malloc(sizeof(*new_key));
2692 *new_key = (uintptr_t)bus;
7df953bd 2693 /* No corresponding free() */
04af0e18 2694 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
bf33cc75 2695 PCI_DEVFN_MAX);
7df953bd 2696 vtd_bus->bus = bus;
2d3fc581 2697 g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus);
7df953bd
KO		 2698 }
2699
2700 vtd_dev_as = vtd_bus->dev_as[devfn];
2701
2702 if (!vtd_dev_as) {
e0a3c8cc 2703 snprintf(name, sizeof(name), "intel_iommu_devfn_%d", devfn);
7df953bd
KO		 2704 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace));
2705
2706 vtd_dev_as->bus = bus;
2707 vtd_dev_as->devfn = (uint8_t)devfn;
2708 vtd_dev_as->iommu_state = s;
2709 vtd_dev_as->context_cache_entry.context_cache_gen = 0;
558e0024
PX		 2710
2711 /*
2712 * Memory region relationships looks like (Address range shows
2713 * only lower 32 bits to make it short in length...):
2714 *
2715 * |-----------------+-------------------+----------|
2716 * | Name | Address range | Priority |
2717 * |-----------------+-------------------+----------+
2718 * | vtd_root | 00000000-ffffffff | 0 |
2719 * | intel_iommu | 00000000-ffffffff | 1 |
2720 * | vtd_sys_alias | 00000000-ffffffff | 1 |
2721 * | intel_iommu_ir | fee00000-feefffff | 64 |
2722 * |-----------------+-------------------+----------|
2723 *
2724 * We enable/disable DMAR by switching enablement for
2725 * vtd_sys_alias and intel_iommu regions. IR region is always
2726 * enabled.
2727 */
1221a474
AK		 2728 memory_region_init_iommu(&vtd_dev_as->iommu, sizeof(vtd_dev_as->iommu),
2729 TYPE_INTEL_IOMMU_MEMORY_REGION, OBJECT(s),
2730 "intel_iommu_dmar",
558e0024
PX		 2731 UINT64_MAX);
2732 memory_region_init_alias(&vtd_dev_as->sys_alias, OBJECT(s),
2733 "vtd_sys_alias", get_system_memory(),
2734 0, memory_region_size(get_system_memory()));
651e4cef
PX		 2735 memory_region_init_io(&vtd_dev_as->iommu_ir, OBJECT(s),
2736 &vtd_mem_ir_ops, s, "intel_iommu_ir",
2737 VTD_INTERRUPT_ADDR_SIZE);
558e0024
PX		 2738 memory_region_init(&vtd_dev_as->root, OBJECT(s),
2739 "vtd_root", UINT64_MAX);
2740 memory_region_add_subregion_overlap(&vtd_dev_as->root,
2741 VTD_INTERRUPT_ADDR_FIRST,
2742 &vtd_dev_as->iommu_ir, 64);
2743 address_space_init(&vtd_dev_as->as, &vtd_dev_as->root, name);
2744 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
2745 &vtd_dev_as->sys_alias, 1);
2746 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
3df9d748
AK		 2747 MEMORY_REGION(&vtd_dev_as->iommu),
2748 1);
558e0024 2749 vtd_switch_address_space(vtd_dev_as);
7df953bd
KO		 2750 }
2751 return vtd_dev_as;
2752}
2753
dd4d607e
PX		 2754/* Unmap the whole range in the notifier's scope. */
2755static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
2756{
2757 IOMMUTLBEntry entry;
2758 hwaddr size;
2759 hwaddr start = n->start;
2760 hwaddr end = n->end;
2761
2762 /*
2763 * Note: all the codes in this function has a assumption that IOVA
2764 * bits are no more than VTD_MGAW bits (which is restricted by
2765 * VT-d spec), otherwise we need to consider overflow of 64 bits.
2766 */
2767
92e5d85e 2768 if (end > VTD_ADDRESS_SIZE(VTD_HOST_ADDRESS_WIDTH)) {
dd4d607e
PX		 2769 /*
2770 * Don't need to unmap regions that is bigger than the whole
2771 * VT-d supported address space size
2772 */
92e5d85e 2773 end = VTD_ADDRESS_SIZE(VTD_HOST_ADDRESS_WIDTH);
dd4d607e
PX		 2774 }
2775
2776 assert(start <= end);
2777 size = end - start;
2778
2779 if (ctpop64(size) != 1) {
2780 /*
2781 * This size cannot format a correct mask. Let's enlarge it to
2782 * suite the minimum available mask.
2783 */
2784 int n = 64 - clz64(size);
2785 if (n > VTD_MGAW) {
2786 /* should not happen, but in case it happens, limit it */
2787 n = VTD_MGAW;
2788 }
2789 size = 1ULL << n;
2790 }
2791
2792 entry.target_as = &address_space_memory;
2793 /* Adjust iova for the size */
2794 entry.iova = n->start & ~(size - 1);
2795 /* This field is meaningless for unmap */
2796 entry.translated_addr = 0;
2797 entry.perm = IOMMU_NONE;
2798 entry.addr_mask = size - 1;
2799
2800 trace_vtd_as_unmap_whole(pci_bus_num(as->bus),
2801 VTD_PCI_SLOT(as->devfn),
2802 VTD_PCI_FUNC(as->devfn),
2803 entry.iova, size);
2804
2805 memory_region_notify_one(n, &entry);
2806}
2807
2808static void vtd_address_space_unmap_all(IntelIOMMUState *s)
2809{
2810 IntelIOMMUNotifierNode *node;
2811 VTDAddressSpace *vtd_as;
2812 IOMMUNotifier *n;
2813
2814 QLIST_FOREACH(node, &s->notifiers_list, next) {
2815 vtd_as = node->vtd_as;
2816 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) {
2817 vtd_address_space_unmap(vtd_as, n);
2818 }
2819 }
2820}
2821
f06a696d
PX		 2822static int vtd_replay_hook(IOMMUTLBEntry *entry, void *private)
2823{
2824 memory_region_notify_one((IOMMUNotifier *)private, entry);
2825 return 0;
2826}
2827
3df9d748 2828static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f06a696d 2829{
3df9d748 2830 VTDAddressSpace *vtd_as = container_of(iommu_mr, VTDAddressSpace, iommu);
f06a696d
PX		 2831 IntelIOMMUState *s = vtd_as->iommu_state;
2832 uint8_t bus_n = pci_bus_num(vtd_as->bus);
2833 VTDContextEntry ce;
2834
dd4d607e
PX		 2835 /*
2836 * The replay can be triggered by either a invalidation or a newly
2837 * created entry. No matter what, we release existing mappings
2838 * (it means flushing caches for UNMAP-only registers).
2839 */
2840 vtd_address_space_unmap(vtd_as, n);
2841
f06a696d 2842 if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) {
f06a696d
PX		 2843 trace_vtd_replay_ce_valid(bus_n, PCI_SLOT(vtd_as->devfn),
2844 PCI_FUNC(vtd_as->devfn),
2845 VTD_CONTEXT_ENTRY_DID(ce.hi),
2846 ce.hi, ce.lo);
dd4d607e 2847 vtd_page_walk(&ce, 0, ~0ULL, vtd_replay_hook, (void *)n, false);
f06a696d
PX		 2848 } else {
2849 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn),
2850 PCI_FUNC(vtd_as->devfn));
2851 }
2852
2853 return;
2854}
2855
1da12ec4
LT		 2856/* Do the initialization. It will also be called when reset, so pay
2857 * attention when adding new initialization stuff.
2858 */
2859static void vtd_init(IntelIOMMUState *s)
2860{
d54bd7f8 2861 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
92e5d85e 2862 uint8_t aw_bits = VTD_HOST_ADDRESS_WIDTH;
d54bd7f8 2863
1da12ec4
LT		 2864 memset(s->csr, 0, DMAR_REG_SIZE);
2865 memset(s->wmask, 0, DMAR_REG_SIZE);
2866 memset(s->w1cmask, 0, DMAR_REG_SIZE);
2867 memset(s->womask, 0, DMAR_REG_SIZE);
2868
1da12ec4
LT		 2869 s->root = 0;
2870 s->root_extended = false;
2871 s->dmar_enabled = false;
2872 s->iq_head = 0;
2873 s->iq_tail = 0;
2874 s->iq = 0;
2875 s->iq_size = 0;
2876 s->qi_enabled = false;
2877 s->iq_last_desc_type = VTD_INV_DESC_NONE;
2878 s->next_frcd_reg = 0;
92e5d85e
PS		 2879 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
2880 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS |
2881 VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(VTD_HOST_ADDRESS_WIDTH);
ed7b8fbc 2882 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
1da12ec4 2883
92e5d85e
PS		 2884 /*
2885 * Rsvd field masks for spte
2886 */
2887 vtd_paging_entry_rsvd_field[0] = ~0ULL;
2888 vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(aw_bits);
2889 vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(aw_bits);
2890 vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(aw_bits);
2891 vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(aw_bits);
2892 vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(aw_bits);
2893 vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(aw_bits);
2894 vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(aw_bits);
2895 vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(aw_bits);
2896
d54bd7f8 2897 if (x86_iommu->intr_supported) {
e6b6af05
RK		 2898 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
2899 if (s->intr_eim == ON_OFF_AUTO_ON) {
2900 s->ecap |= VTD_ECAP_EIM;
2901 }
2902 assert(s->intr_eim != ON_OFF_AUTO_AUTO);
d54bd7f8
PX		 2903 }
2904
554f5e16
JW		 2905 if (x86_iommu->dt_supported) {
2906 s->ecap |= VTD_ECAP_DT;
2907 }
2908
dbaabb25
PX		 2909 if (x86_iommu->pt_supported) {
2910 s->ecap |= VTD_ECAP_PT;
2911 }
2912
3b40f0e5
ABD		 2913 if (s->caching_mode) {
2914 s->cap |= VTD_CAP_CM;
2915 }
2916
d92fa2dc 2917 vtd_reset_context_cache(s);
b5a280c0 2918 vtd_reset_iotlb(s);
d92fa2dc 2919
1da12ec4
LT		 2920 /* Define registers with default values and bit semantics */
2921 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
2922 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
2923 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
2924 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
2925 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);
2926 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0);
2927 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffff000ULL, 0);
2928 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0);
2929 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL);
2930
2931 /* Advanced Fault Logging not supported */
2932 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL);
2933 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2934 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0);
2935 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0);
2936
2937 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
2938 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
2939 */
2940 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0);
2941
2942 /* Treated as RO for implementations that PLMR and PHMR fields reported
2943 * as Clear in the CAP_REG.
2944 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
2945 */
2946 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0);
2947
ed7b8fbc
LT		 2948 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0);
2949 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0);
2950 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff007ULL, 0);
2951 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL);
2952 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2953 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0);
2954 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0);
2955 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
2956 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0);
2957
1da12ec4
LT		 2958 /* IOTLB registers */
2959 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0);
2960 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0);
2961 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL);
2962
2963 /* Fault Recording Registers, 128-bit */
2964 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0);
2965 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL);
a5861439
PX		 2966
2967 /*
28589311 2968 * Interrupt remapping registers.
a5861439 2969 */
28589311 2970 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0);
1da12ec4
LT		 2971}
2972
2973/* Should not reset address_spaces when reset because devices will still use
2974 * the address space they got at first (won't ask the bus again).
2975 */
2976static void vtd_reset(DeviceState *dev)
2977{
2978 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
2979
1da12ec4 2980 vtd_init(s);
dd4d607e
PX		 2981
2982 /*
2983 * When device reset, throw away all mappings and external caches
2984 */
2985 vtd_address_space_unmap_all(s);
1da12ec4
LT		 2986}
2987
621d983a
MA		 2988static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
2989{
2990 IntelIOMMUState *s = opaque;
2991 VTDAddressSpace *vtd_as;
2992
bf33cc75 2993 assert(0 <= devfn && devfn < PCI_DEVFN_MAX);
621d983a
MA		 2994
2995 vtd_as = vtd_find_add_as(s, bus, devfn);
2996 return &vtd_as->as;
2997}
2998
e6b6af05 2999static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
6333e93c 3000{
e6b6af05
RK		 3001 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
3002
6333e93c
RK		 3003 /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */
3004 if (x86_iommu->intr_supported && kvm_irqchip_in_kernel() &&
3005 !kvm_irqchip_is_split()) {
3006 error_setg(errp, "Intel Interrupt Remapping cannot work with "
3007 "kernel-irqchip=on, please use 'split|off'.");
3008 return false;
3009 }
e6b6af05
RK		 3010 if (s->intr_eim == ON_OFF_AUTO_ON && !x86_iommu->intr_supported) {
3011 error_setg(errp, "eim=on cannot be selected without intremap=on");
3012 return false;
3013 }
3014
3015 if (s->intr_eim == ON_OFF_AUTO_AUTO) {
fb506e70
RK		 3016 s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim)
3017 && x86_iommu->intr_supported ?
e6b6af05
RK		 3018 ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
3019 }
fb506e70
RK		 3020 if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) {
3021 if (!kvm_irqchip_in_kernel()) {
3022 error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split");
3023 return false;
3024 }
3025 if (!kvm_enable_x2apic()) {
3026 error_setg(errp, "eim=on requires support on the KVM side"
3027 "(X2APIC_API, first shipped in v4.7)");
3028 return false;
3029 }
3030 }
e6b6af05 3031
6333e93c
RK		 3032 return true;
3033}
3034
1da12ec4
LT		 3035static void vtd_realize(DeviceState *dev, Error **errp)
3036{
ef0e8fc7
EH		 3037 MachineState *ms = MACHINE(qdev_get_machine());
3038 MachineClass *mc = MACHINE_GET_CLASS(ms);
3039 PCMachineState *pcms =
3040 PC_MACHINE(object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE));
3041 PCIBus *bus;
1da12ec4 3042 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
4684a204 3043 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
1da12ec4 3044
ef0e8fc7
EH		 3045 if (!pcms) {
3046 error_setg(errp, "Machine-type '%s' not supported by intel-iommu",
3047 mc->name);
3048 return;
3049 }
3050
3051 bus = pcms->bus;
fb9f5926 3052 x86_iommu->type = TYPE_INTEL;
6333e93c 3053
e6b6af05 3054 if (!vtd_decide_config(s, errp)) {
6333e93c
RK		 3055 return;
3056 }
3057
dd4d607e 3058 QLIST_INIT(&s->notifiers_list);
7df953bd 3059 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
1da12ec4
LT		 3060 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
3061 "intel_iommu", DMAR_REG_SIZE);
3062 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem);
b5a280c0
LT		 3063 /* No corresponding destroy */
3064 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3065 g_free, g_free);
7df953bd
KO		 3066 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3067 g_free, g_free);
1da12ec4 3068 vtd_init(s);
621d983a
MA		 3069 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
3070 pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
cb135f59
PX		 3071 /* Pseudo address space under root PCI bus. */
3072 pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
1da12ec4
LT		 3073}
3074
3075static void vtd_class_init(ObjectClass *klass, void *data)
3076{
3077 DeviceClass *dc = DEVICE_CLASS(klass);
1c7955c4 3078 X86IOMMUClass *x86_class = X86_IOMMU_CLASS(klass);
1da12ec4
LT		 3079
3080 dc->reset = vtd_reset;
1da12ec4
LT		 3081 dc->vmsd = &vtd_vmstate;
3082 dc->props = vtd_properties;
621d983a 3083 dc->hotpluggable = false;
1c7955c4 3084 x86_class->realize = vtd_realize;
8b5ed7df 3085 x86_class->int_remap = vtd_int_remap;
8ab5700c 3086 /* Supported by the pc-q35-* machine types */
e4f4fb1e 3087 dc->user_creatable = true;
1da12ec4
LT		 3088}
3089
3090static const TypeInfo vtd_info = {
3091 .name = TYPE_INTEL_IOMMU_DEVICE,
1c7955c4 3092 .parent = TYPE_X86_IOMMU_DEVICE,
1da12ec4
LT		 3093 .instance_size = sizeof(IntelIOMMUState),
3094 .class_init = vtd_class_init,
3095};
3096
1221a474
AK		 3097static void vtd_iommu_memory_region_class_init(ObjectClass *klass,
3098 void *data)
3099{
3100 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
3101
3102 imrc->translate = vtd_iommu_translate;
3103 imrc->notify_flag_changed = vtd_iommu_notify_flag_changed;
3104 imrc->replay = vtd_iommu_replay;
3105}
3106
3107static const TypeInfo vtd_iommu_memory_region_info = {
3108 .parent = TYPE_IOMMU_MEMORY_REGION,
3109 .name = TYPE_INTEL_IOMMU_MEMORY_REGION,
3110 .class_init = vtd_iommu_memory_region_class_init,
3111};
3112
1da12ec4
LT		 3113static void vtd_register_types(void)
3114{
1da12ec4 3115 type_register_static(&vtd_info);
1221a474 3116 type_register_static(&vtd_iommu_memory_region_info);
1da12ec4
LT		 3117}
3118
3119type_init(vtd_register_types)
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