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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
db5ebe5f | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
83c9f4ca PB |
26 | #include "hw/hw.h" |
27 | #include "hw/pci/pci.h" | |
0d09e41a PB |
28 | #include "hw/pci-host/apb.h" |
29 | #include "hw/i386/pc.h" | |
30 | #include "hw/char/serial.h" | |
31 | #include "hw/timer/m48t59.h" | |
32 | #include "hw/block/fdc.h" | |
1422e32d | 33 | #include "net/net.h" |
1de7afc9 | 34 | #include "qemu/timer.h" |
9c17d615 | 35 | #include "sysemu/sysemu.h" |
83c9f4ca | 36 | #include "hw/boards.h" |
ec0503b4 | 37 | #include "hw/nvram/openbios_firmware_abi.h" |
0d09e41a | 38 | #include "hw/nvram/fw_cfg.h" |
83c9f4ca PB |
39 | #include "hw/sysbus.h" |
40 | #include "hw/ide.h" | |
41 | #include "hw/loader.h" | |
ca20cf32 | 42 | #include "elf.h" |
4be74634 | 43 | #include "sysemu/block-backend.h" |
022c62cb | 44 | #include "exec/address-spaces.h" |
3475187d | 45 | |
9d926598 | 46 | //#define DEBUG_IRQ |
b430a225 | 47 | //#define DEBUG_EBUS |
8f4efc55 | 48 | //#define DEBUG_TIMER |
9d926598 BS |
49 | |
50 | #ifdef DEBUG_IRQ | |
b430a225 | 51 | #define CPUIRQ_DPRINTF(fmt, ...) \ |
001faf32 | 52 | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
9d926598 | 53 | #else |
b430a225 BS |
54 | #define CPUIRQ_DPRINTF(fmt, ...) |
55 | #endif | |
56 | ||
57 | #ifdef DEBUG_EBUS | |
58 | #define EBUS_DPRINTF(fmt, ...) \ | |
59 | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) | |
60 | #else | |
61 | #define EBUS_DPRINTF(fmt, ...) | |
9d926598 BS |
62 | #endif |
63 | ||
8f4efc55 IK |
64 | #ifdef DEBUG_TIMER |
65 | #define TIMER_DPRINTF(fmt, ...) \ | |
66 | do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) | |
67 | #else | |
68 | #define TIMER_DPRINTF(fmt, ...) | |
69 | #endif | |
70 | ||
83469015 FB |
71 | #define KERNEL_LOAD_ADDR 0x00404000 |
72 | #define CMDLINE_ADDR 0x003ff000 | |
ac2e9d66 | 73 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 74 | #define PROM_VADDR 0x000ffd00000ULL |
83469015 | 75 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e | 76 | #define APB_MEM_BASE 0x1ff00000000ULL |
d63baf92 | 77 | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
f930d07e | 78 | #define PROM_FILENAME "openbios-sparc64" |
83469015 | 79 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 80 | #define MAX_IDE_BUS 2 |
3cce6243 | 81 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
82 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
83 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
84 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 85 | |
852e82f3 | 86 | #define IVEC_MAX 0x40 |
9d926598 | 87 | |
8fa211e8 BS |
88 | #define TICK_MAX 0x7fffffffffffffffULL |
89 | ||
c7ba218d BS |
90 | struct hwdef { |
91 | const char * const default_cpu_model; | |
905fdcb5 | 92 | uint16_t machine_id; |
e87231d4 BS |
93 | uint64_t prom_addr; |
94 | uint64_t console_serial_base; | |
c7ba218d BS |
95 | }; |
96 | ||
c5e6fb7e AK |
97 | typedef struct EbusState { |
98 | PCIDevice pci_dev; | |
99 | MemoryRegion bar0; | |
100 | MemoryRegion bar1; | |
101 | } EbusState; | |
102 | ||
57146941 | 103 | void DMA_init(ISABus *bus, int high_page_enable) |
4556bd8b BS |
104 | { |
105 | } | |
106 | ||
ddcd5531 GA |
107 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
108 | Error **errp) | |
81864572 | 109 | { |
48779e50 | 110 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
111 | } |
112 | ||
31688246 | 113 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, |
43a34704 BS |
114 | const char *arch, ram_addr_t RAM_size, |
115 | const char *boot_devices, | |
116 | uint32_t kernel_image, uint32_t kernel_size, | |
117 | const char *cmdline, | |
118 | uint32_t initrd_image, uint32_t initrd_size, | |
119 | uint32_t NVRAM_image, | |
120 | int width, int height, int depth, | |
121 | const uint8_t *macaddr) | |
83469015 | 122 | { |
66508601 BS |
123 | unsigned int i; |
124 | uint32_t start, end; | |
d2c63fc1 | 125 | uint8_t image[0x1ff0]; |
d2c63fc1 | 126 | struct OpenBIOS_nvpart_v1 *part_header; |
31688246 | 127 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
128 | |
129 | memset(image, '\0', sizeof(image)); | |
130 | ||
513f789f | 131 | start = 0; |
83469015 | 132 | |
66508601 BS |
133 | // OpenBIOS nvram variables |
134 | // Variable partition | |
d2c63fc1 BS |
135 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
136 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
363a37d5 | 137 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
66508601 | 138 | |
d2c63fc1 | 139 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 140 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
141 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
142 | ||
143 | // End marker | |
144 | image[end++] = '\0'; | |
66508601 | 145 | |
66508601 | 146 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 147 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
148 | |
149 | // free partition | |
150 | start = end; | |
d2c63fc1 BS |
151 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
152 | part_header->signature = OPENBIOS_PART_FREE; | |
363a37d5 | 153 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
66508601 BS |
154 | |
155 | end = 0x1fd0; | |
d2c63fc1 BS |
156 | OpenBIOS_finish_partition(part_header, end - start); |
157 | ||
0d31cb99 BS |
158 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
159 | ||
31688246 HP |
160 | for (i = 0; i < sizeof(image); i++) { |
161 | (k->write)(nvram, i, image[i]); | |
162 | } | |
66508601 | 163 | |
83469015 | 164 | return 0; |
3475187d | 165 | } |
5f2bf0fe BS |
166 | |
167 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
168 | const char *initrd_filename, | |
169 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
170 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
171 | uint64_t *kernel_entry) | |
636aa70a BS |
172 | { |
173 | int linux_boot; | |
174 | unsigned int i; | |
175 | long kernel_size; | |
6908d9ce | 176 | uint8_t *ptr; |
5f2bf0fe | 177 | uint64_t kernel_top; |
636aa70a BS |
178 | |
179 | linux_boot = (kernel_filename != NULL); | |
180 | ||
181 | kernel_size = 0; | |
182 | if (linux_boot) { | |
ca20cf32 BS |
183 | int bswap_needed; |
184 | ||
185 | #ifdef BSWAP_NEEDED | |
186 | bswap_needed = 1; | |
187 | #else | |
188 | bswap_needed = 0; | |
189 | #endif | |
5f2bf0fe | 190 | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
7ef295ea | 191 | kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); |
5f2bf0fe BS |
192 | if (kernel_size < 0) { |
193 | *kernel_addr = KERNEL_LOAD_ADDR; | |
194 | *kernel_entry = KERNEL_LOAD_ADDR; | |
636aa70a | 195 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
196 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
197 | TARGET_PAGE_SIZE); | |
5f2bf0fe BS |
198 | } |
199 | if (kernel_size < 0) { | |
636aa70a BS |
200 | kernel_size = load_image_targphys(kernel_filename, |
201 | KERNEL_LOAD_ADDR, | |
202 | RAM_size - KERNEL_LOAD_ADDR); | |
5f2bf0fe | 203 | } |
636aa70a BS |
204 | if (kernel_size < 0) { |
205 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
206 | kernel_filename); | |
207 | exit(1); | |
208 | } | |
5f2bf0fe | 209 | /* load initrd above kernel */ |
636aa70a BS |
210 | *initrd_size = 0; |
211 | if (initrd_filename) { | |
5f2bf0fe BS |
212 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
213 | ||
636aa70a | 214 | *initrd_size = load_image_targphys(initrd_filename, |
5f2bf0fe BS |
215 | *initrd_addr, |
216 | RAM_size - *initrd_addr); | |
217 | if ((int)*initrd_size < 0) { | |
636aa70a BS |
218 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
219 | initrd_filename); | |
220 | exit(1); | |
221 | } | |
222 | } | |
223 | if (*initrd_size > 0) { | |
224 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
5f2bf0fe | 225 | ptr = rom_ptr(*kernel_addr + i); |
6908d9ce | 226 | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
5f2bf0fe | 227 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); |
6908d9ce | 228 | stl_p(ptr + 28, *initrd_size); |
636aa70a BS |
229 | break; |
230 | } | |
231 | } | |
232 | } | |
233 | } | |
234 | return kernel_size; | |
235 | } | |
3475187d | 236 | |
98cec4a2 | 237 | void cpu_check_irqs(CPUSPARCState *env) |
9d926598 | 238 | { |
259186a7 | 239 | CPUState *cs; |
d532b26c IK |
240 | uint32_t pil = env->pil_in | |
241 | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); | |
242 | ||
a7be9bad AT |
243 | /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ |
244 | if (env->ivec_status & 0x20) { | |
245 | return; | |
246 | } | |
259186a7 | 247 | cs = CPU(sparc_env_get_cpu(env)); |
d532b26c IK |
248 | /* check if TM or SM in SOFTINT are set |
249 | setting these also causes interrupt 14 */ | |
250 | if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { | |
251 | pil |= 1 << 14; | |
252 | } | |
253 | ||
9f94778c AT |
254 | /* The bit corresponding to psrpil is (1<< psrpil), the next bit |
255 | is (2 << psrpil). */ | |
256 | if (pil < (2 << env->psrpil)){ | |
259186a7 | 257 | if (cs->interrupt_request & CPU_INTERRUPT_HARD) { |
d532b26c IK |
258 | CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", |
259 | env->interrupt_index); | |
260 | env->interrupt_index = 0; | |
d8ed887b | 261 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
d532b26c IK |
262 | } |
263 | return; | |
264 | } | |
265 | ||
266 | if (cpu_interrupts_enabled(env)) { | |
9d926598 | 267 | |
9d926598 BS |
268 | unsigned int i; |
269 | ||
d532b26c | 270 | for (i = 15; i > env->psrpil; i--) { |
9d926598 BS |
271 | if (pil & (1 << i)) { |
272 | int old_interrupt = env->interrupt_index; | |
d532b26c IK |
273 | int new_interrupt = TT_EXTINT | i; |
274 | ||
a7be9bad AT |
275 | if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt |
276 | && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { | |
d532b26c IK |
277 | CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " |
278 | "current %x >= pending %x\n", | |
279 | env->tl, cpu_tsptr(env)->tt, new_interrupt); | |
280 | } else if (old_interrupt != new_interrupt) { | |
281 | env->interrupt_index = new_interrupt; | |
282 | CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, | |
283 | old_interrupt, new_interrupt); | |
c3affe56 | 284 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
9d926598 BS |
285 | } |
286 | break; | |
287 | } | |
288 | } | |
259186a7 | 289 | } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { |
d532b26c IK |
290 | CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " |
291 | "current interrupt %x\n", | |
292 | pil, env->pil_in, env->softint, env->interrupt_index); | |
9f94778c | 293 | env->interrupt_index = 0; |
d8ed887b | 294 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
9d926598 BS |
295 | } |
296 | } | |
297 | ||
ce18c558 | 298 | static void cpu_kick_irq(SPARCCPU *cpu) |
8f4efc55 | 299 | { |
259186a7 | 300 | CPUState *cs = CPU(cpu); |
ce18c558 AF |
301 | CPUSPARCState *env = &cpu->env; |
302 | ||
259186a7 | 303 | cs->halted = 0; |
8f4efc55 | 304 | cpu_check_irqs(env); |
259186a7 | 305 | qemu_cpu_kick(cs); |
8f4efc55 IK |
306 | } |
307 | ||
361dea40 | 308 | static void cpu_set_ivec_irq(void *opaque, int irq, int level) |
9d926598 | 309 | { |
b64ba4b2 AF |
310 | SPARCCPU *cpu = opaque; |
311 | CPUSPARCState *env = &cpu->env; | |
259186a7 | 312 | CPUState *cs; |
9d926598 BS |
313 | |
314 | if (level) { | |
23cf96e1 AT |
315 | if (!(env->ivec_status & 0x20)) { |
316 | CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); | |
259186a7 AF |
317 | cs = CPU(cpu); |
318 | cs->halted = 0; | |
23cf96e1 AT |
319 | env->interrupt_index = TT_IVEC; |
320 | env->ivec_status |= 0x20; | |
321 | env->ivec_data[0] = (0x1f << 6) | irq; | |
322 | env->ivec_data[1] = 0; | |
323 | env->ivec_data[2] = 0; | |
c3affe56 | 324 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
23cf96e1 AT |
325 | } |
326 | } else { | |
327 | if (env->ivec_status & 0x20) { | |
328 | CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); | |
d8ed887b | 329 | cs = CPU(cpu); |
23cf96e1 | 330 | env->ivec_status &= ~0x20; |
d8ed887b | 331 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
23cf96e1 | 332 | } |
9d926598 BS |
333 | } |
334 | } | |
335 | ||
e87231d4 | 336 | typedef struct ResetData { |
403d7a2d | 337 | SPARCCPU *cpu; |
44a99354 | 338 | uint64_t prom_addr; |
e87231d4 BS |
339 | } ResetData; |
340 | ||
6b678e1f | 341 | static CPUTimer *cpu_timer_create(const char *name, SPARCCPU *cpu, |
8f4efc55 | 342 | QEMUBHFunc *cb, uint32_t frequency, |
e913cac7 | 343 | uint64_t disabled_mask, uint64_t npt_mask) |
8f4efc55 | 344 | { |
7267c094 | 345 | CPUTimer *timer = g_malloc0(sizeof (CPUTimer)); |
8f4efc55 IK |
346 | |
347 | timer->name = name; | |
348 | timer->frequency = frequency; | |
349 | timer->disabled_mask = disabled_mask; | |
e913cac7 | 350 | timer->npt_mask = npt_mask; |
8f4efc55 IK |
351 | |
352 | timer->disabled = 1; | |
e913cac7 | 353 | timer->npt = 1; |
bc72ad67 | 354 | timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
8f4efc55 | 355 | |
bc72ad67 | 356 | timer->qtimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, cb, cpu); |
8f4efc55 IK |
357 | |
358 | return timer; | |
359 | } | |
360 | ||
361 | static void cpu_timer_reset(CPUTimer *timer) | |
362 | { | |
363 | timer->disabled = 1; | |
bc72ad67 | 364 | timer->clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
8f4efc55 | 365 | |
bc72ad67 | 366 | timer_del(timer->qtimer); |
8f4efc55 IK |
367 | } |
368 | ||
c68ea704 FB |
369 | static void main_cpu_reset(void *opaque) |
370 | { | |
e87231d4 | 371 | ResetData *s = (ResetData *)opaque; |
403d7a2d | 372 | CPUSPARCState *env = &s->cpu->env; |
44a99354 | 373 | static unsigned int nr_resets; |
20c9f095 | 374 | |
403d7a2d | 375 | cpu_reset(CPU(s->cpu)); |
8f4efc55 IK |
376 | |
377 | cpu_timer_reset(env->tick); | |
378 | cpu_timer_reset(env->stick); | |
379 | cpu_timer_reset(env->hstick); | |
380 | ||
e87231d4 BS |
381 | env->gregs[1] = 0; // Memory start |
382 | env->gregs[2] = ram_size; // Memory size | |
383 | env->gregs[3] = 0; // Machine description XXX | |
44a99354 BS |
384 | if (nr_resets++ == 0) { |
385 | /* Power on reset */ | |
386 | env->pc = s->prom_addr + 0x20ULL; | |
387 | } else { | |
388 | env->pc = s->prom_addr + 0x40ULL; | |
389 | } | |
e87231d4 | 390 | env->npc = env->pc + 4; |
20c9f095 BS |
391 | } |
392 | ||
22548760 | 393 | static void tick_irq(void *opaque) |
20c9f095 | 394 | { |
6b678e1f AF |
395 | SPARCCPU *cpu = opaque; |
396 | CPUSPARCState *env = &cpu->env; | |
20c9f095 | 397 | |
8f4efc55 IK |
398 | CPUTimer* timer = env->tick; |
399 | ||
400 | if (timer->disabled) { | |
401 | CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); | |
402 | return; | |
403 | } else { | |
404 | CPUIRQ_DPRINTF("tick: fire\n"); | |
8fa211e8 | 405 | } |
8f4efc55 IK |
406 | |
407 | env->softint |= SOFTINT_TIMER; | |
ce18c558 | 408 | cpu_kick_irq(cpu); |
20c9f095 BS |
409 | } |
410 | ||
22548760 | 411 | static void stick_irq(void *opaque) |
20c9f095 | 412 | { |
6b678e1f AF |
413 | SPARCCPU *cpu = opaque; |
414 | CPUSPARCState *env = &cpu->env; | |
20c9f095 | 415 | |
8f4efc55 IK |
416 | CPUTimer* timer = env->stick; |
417 | ||
418 | if (timer->disabled) { | |
419 | CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); | |
420 | return; | |
421 | } else { | |
422 | CPUIRQ_DPRINTF("stick: fire\n"); | |
8fa211e8 | 423 | } |
8f4efc55 IK |
424 | |
425 | env->softint |= SOFTINT_STIMER; | |
ce18c558 | 426 | cpu_kick_irq(cpu); |
20c9f095 BS |
427 | } |
428 | ||
22548760 | 429 | static void hstick_irq(void *opaque) |
20c9f095 | 430 | { |
6b678e1f AF |
431 | SPARCCPU *cpu = opaque; |
432 | CPUSPARCState *env = &cpu->env; | |
20c9f095 | 433 | |
8f4efc55 IK |
434 | CPUTimer* timer = env->hstick; |
435 | ||
436 | if (timer->disabled) { | |
437 | CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); | |
438 | return; | |
439 | } else { | |
440 | CPUIRQ_DPRINTF("hstick: fire\n"); | |
8fa211e8 | 441 | } |
8f4efc55 IK |
442 | |
443 | env->softint |= SOFTINT_STIMER; | |
ce18c558 | 444 | cpu_kick_irq(cpu); |
8f4efc55 IK |
445 | } |
446 | ||
447 | static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency) | |
448 | { | |
449 | return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency); | |
450 | } | |
451 | ||
452 | static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency) | |
453 | { | |
454 | return muldiv64(timer_ticks, frequency, get_ticks_per_sec()); | |
c68ea704 FB |
455 | } |
456 | ||
8f4efc55 | 457 | void cpu_tick_set_count(CPUTimer *timer, uint64_t count) |
f4b1a842 | 458 | { |
bf43330a MCA |
459 | uint64_t real_count = count & ~timer->npt_mask; |
460 | uint64_t npt_bit = count & timer->npt_mask; | |
8f4efc55 | 461 | |
bc72ad67 | 462 | int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - |
8f4efc55 IK |
463 | cpu_to_timer_ticks(real_count, timer->frequency); |
464 | ||
bf43330a | 465 | TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n", |
8f4efc55 | 466 | timer->name, real_count, |
bf43330a | 467 | timer->npt ? "disabled" : "enabled", timer); |
8f4efc55 | 468 | |
bf43330a | 469 | timer->npt = npt_bit ? 1 : 0; |
8f4efc55 | 470 | timer->clock_offset = vm_clock_offset; |
f4b1a842 BS |
471 | } |
472 | ||
8f4efc55 | 473 | uint64_t cpu_tick_get_count(CPUTimer *timer) |
f4b1a842 | 474 | { |
8f4efc55 | 475 | uint64_t real_count = timer_to_cpu_ticks( |
bc72ad67 | 476 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, |
8f4efc55 IK |
477 | timer->frequency); |
478 | ||
bf43330a | 479 | TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n", |
8f4efc55 | 480 | timer->name, real_count, |
bf43330a | 481 | timer->npt ? "disabled" : "enabled", timer); |
8f4efc55 | 482 | |
bf43330a MCA |
483 | if (timer->npt) { |
484 | real_count |= timer->npt_mask; | |
485 | } | |
8f4efc55 IK |
486 | |
487 | return real_count; | |
f4b1a842 BS |
488 | } |
489 | ||
8f4efc55 | 490 | void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) |
f4b1a842 | 491 | { |
bc72ad67 | 492 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
8f4efc55 IK |
493 | |
494 | uint64_t real_limit = limit & ~timer->disabled_mask; | |
495 | timer->disabled = (limit & timer->disabled_mask) ? 1 : 0; | |
496 | ||
497 | int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) + | |
498 | timer->clock_offset; | |
499 | ||
500 | if (expires < now) { | |
501 | expires = now + 1; | |
502 | } | |
503 | ||
504 | TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " | |
505 | "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", | |
506 | timer->name, real_limit, | |
507 | timer->disabled?"disabled":"enabled", | |
508 | timer, limit, | |
509 | timer_to_cpu_ticks(now - timer->clock_offset, | |
510 | timer->frequency), | |
511 | timer_to_cpu_ticks(expires - now, timer->frequency)); | |
512 | ||
513 | if (!real_limit) { | |
514 | TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", | |
515 | timer->name); | |
bc72ad67 | 516 | timer_del(timer->qtimer); |
8f4efc55 | 517 | } else if (timer->disabled) { |
bc72ad67 | 518 | timer_del(timer->qtimer); |
8f4efc55 | 519 | } else { |
bc72ad67 | 520 | timer_mod(timer->qtimer, expires); |
8f4efc55 | 521 | } |
f4b1a842 BS |
522 | } |
523 | ||
361dea40 | 524 | static void isa_irq_handler(void *opaque, int n, int level) |
1387fe4a | 525 | { |
361dea40 BS |
526 | static const int isa_irq_to_ivec[16] = { |
527 | [1] = 0x29, /* keyboard */ | |
528 | [4] = 0x2b, /* serial */ | |
529 | [6] = 0x27, /* floppy */ | |
530 | [7] = 0x22, /* parallel */ | |
531 | [12] = 0x2a, /* mouse */ | |
532 | }; | |
533 | qemu_irq *irqs = opaque; | |
534 | int ivec; | |
535 | ||
536 | assert(n < 16); | |
537 | ivec = isa_irq_to_ivec[n]; | |
538 | EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); | |
539 | if (ivec) { | |
540 | qemu_set_irq(irqs[ivec], level); | |
541 | } | |
1387fe4a BS |
542 | } |
543 | ||
c190ea07 | 544 | /* EBUS (Eight bit bus) bridge */ |
48a18b3c | 545 | static ISABus * |
361dea40 | 546 | pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs) |
c190ea07 | 547 | { |
1387fe4a | 548 | qemu_irq *isa_irq; |
ab953e28 | 549 | PCIDevice *pci_dev; |
48a18b3c | 550 | ISABus *isa_bus; |
1387fe4a | 551 | |
ab953e28 | 552 | pci_dev = pci_create_simple(bus, devfn, "ebus"); |
2ae0e48d | 553 | isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); |
361dea40 | 554 | isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); |
48a18b3c HP |
555 | isa_bus_irqs(isa_bus, isa_irq); |
556 | return isa_bus; | |
53e3c4f9 | 557 | } |
c190ea07 | 558 | |
3a80cead | 559 | static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) |
53e3c4f9 | 560 | { |
c5e6fb7e AK |
561 | EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); |
562 | ||
d10e5432 MA |
563 | if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), |
564 | pci_address_space_io(pci_dev), errp)) { | |
565 | return; | |
566 | } | |
c5e6fb7e AK |
567 | |
568 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem | |
569 | pci_dev->config[0x05] = 0x00; | |
570 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
571 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
572 | pci_dev->config[0x09] = 0x00; // programming i/f | |
573 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
574 | ||
0a70e094 PB |
575 | memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), |
576 | 0, 0x1000000); | |
e824b2cc | 577 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
0a70e094 | 578 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), |
f3b18f35 | 579 | 0, 0x4000); |
a1cf8be5 | 580 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); |
c190ea07 BS |
581 | } |
582 | ||
40021f08 AL |
583 | static void ebus_class_init(ObjectClass *klass, void *data) |
584 | { | |
585 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
586 | ||
3a80cead | 587 | k->realize = pci_ebus_realize; |
40021f08 AL |
588 | k->vendor_id = PCI_VENDOR_ID_SUN; |
589 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
590 | k->revision = 0x01; | |
591 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
592 | } | |
593 | ||
8c43a6f0 | 594 | static const TypeInfo ebus_info = { |
39bffca2 AL |
595 | .name = "ebus", |
596 | .parent = TYPE_PCI_DEVICE, | |
597 | .instance_size = sizeof(EbusState), | |
598 | .class_init = ebus_class_init, | |
53e3c4f9 BS |
599 | }; |
600 | ||
13575cf6 AF |
601 | #define TYPE_OPENPROM "openprom" |
602 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
603 | ||
d4edce38 | 604 | typedef struct PROMState { |
13575cf6 AF |
605 | SysBusDevice parent_obj; |
606 | ||
d4edce38 AK |
607 | MemoryRegion prom; |
608 | } PROMState; | |
609 | ||
409dbce5 AJ |
610 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
611 | { | |
a8170e5e | 612 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
613 | return addr + *base_addr - PROM_VADDR; |
614 | } | |
615 | ||
1baffa46 | 616 | /* Boot PROM (OpenBIOS) */ |
a8170e5e | 617 | static void prom_init(hwaddr addr, const char *bios_name) |
1baffa46 BS |
618 | { |
619 | DeviceState *dev; | |
620 | SysBusDevice *s; | |
621 | char *filename; | |
622 | int ret; | |
623 | ||
13575cf6 | 624 | dev = qdev_create(NULL, TYPE_OPENPROM); |
e23a1b33 | 625 | qdev_init_nofail(dev); |
1356b98d | 626 | s = SYS_BUS_DEVICE(dev); |
1baffa46 BS |
627 | |
628 | sysbus_mmio_map(s, 0, addr); | |
629 | ||
630 | /* load boot prom */ | |
631 | if (bios_name == NULL) { | |
632 | bios_name = PROM_FILENAME; | |
633 | } | |
634 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
635 | if (filename) { | |
409dbce5 | 636 | ret = load_elf(filename, translate_prom_address, &addr, |
7ef295ea | 637 | NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); |
1baffa46 BS |
638 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
639 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
640 | } | |
7267c094 | 641 | g_free(filename); |
1baffa46 BS |
642 | } else { |
643 | ret = -1; | |
644 | } | |
645 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
646 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
647 | exit(1); | |
648 | } | |
649 | } | |
650 | ||
81a322d4 | 651 | static int prom_init1(SysBusDevice *dev) |
1baffa46 | 652 | { |
13575cf6 | 653 | PROMState *s = OPENPROM(dev); |
1baffa46 | 654 | |
49946538 | 655 | memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX, |
f8ed85ac | 656 | &error_fatal); |
c5705a77 | 657 | vmstate_register_ram_global(&s->prom); |
d4edce38 | 658 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 659 | sysbus_init_mmio(dev, &s->prom); |
81a322d4 | 660 | return 0; |
1baffa46 BS |
661 | } |
662 | ||
999e12bb AL |
663 | static Property prom_properties[] = { |
664 | {/* end of property list */}, | |
665 | }; | |
666 | ||
667 | static void prom_class_init(ObjectClass *klass, void *data) | |
668 | { | |
39bffca2 | 669 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
670 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
671 | ||
672 | k->init = prom_init1; | |
39bffca2 | 673 | dc->props = prom_properties; |
999e12bb AL |
674 | } |
675 | ||
8c43a6f0 | 676 | static const TypeInfo prom_info = { |
13575cf6 | 677 | .name = TYPE_OPENPROM, |
39bffca2 AL |
678 | .parent = TYPE_SYS_BUS_DEVICE, |
679 | .instance_size = sizeof(PROMState), | |
680 | .class_init = prom_class_init, | |
1baffa46 BS |
681 | }; |
682 | ||
bda42033 | 683 | |
88c034d5 AF |
684 | #define TYPE_SUN4U_MEMORY "memory" |
685 | #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) | |
686 | ||
687 | typedef struct RamDevice { | |
688 | SysBusDevice parent_obj; | |
689 | ||
d4edce38 | 690 | MemoryRegion ram; |
04843626 | 691 | uint64_t size; |
bda42033 BS |
692 | } RamDevice; |
693 | ||
694 | /* System RAM */ | |
81a322d4 | 695 | static int ram_init1(SysBusDevice *dev) |
bda42033 | 696 | { |
88c034d5 | 697 | RamDevice *d = SUN4U_RAM(dev); |
bda42033 | 698 | |
49946538 | 699 | memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size, |
f8ed85ac | 700 | &error_fatal); |
c5705a77 | 701 | vmstate_register_ram_global(&d->ram); |
750ecd44 | 702 | sysbus_init_mmio(dev, &d->ram); |
81a322d4 | 703 | return 0; |
bda42033 BS |
704 | } |
705 | ||
a8170e5e | 706 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
bda42033 BS |
707 | { |
708 | DeviceState *dev; | |
709 | SysBusDevice *s; | |
710 | RamDevice *d; | |
711 | ||
712 | /* allocate RAM */ | |
88c034d5 | 713 | dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); |
1356b98d | 714 | s = SYS_BUS_DEVICE(dev); |
bda42033 | 715 | |
88c034d5 | 716 | d = SUN4U_RAM(dev); |
bda42033 | 717 | d->size = RAM_size; |
e23a1b33 | 718 | qdev_init_nofail(dev); |
bda42033 BS |
719 | |
720 | sysbus_mmio_map(s, 0, addr); | |
721 | } | |
722 | ||
999e12bb AL |
723 | static Property ram_properties[] = { |
724 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
725 | DEFINE_PROP_END_OF_LIST(), | |
726 | }; | |
727 | ||
728 | static void ram_class_init(ObjectClass *klass, void *data) | |
729 | { | |
39bffca2 | 730 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
731 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
732 | ||
733 | k->init = ram_init1; | |
39bffca2 | 734 | dc->props = ram_properties; |
999e12bb AL |
735 | } |
736 | ||
8c43a6f0 | 737 | static const TypeInfo ram_info = { |
88c034d5 | 738 | .name = TYPE_SUN4U_MEMORY, |
39bffca2 AL |
739 | .parent = TYPE_SYS_BUS_DEVICE, |
740 | .instance_size = sizeof(RamDevice), | |
741 | .class_init = ram_class_init, | |
bda42033 BS |
742 | }; |
743 | ||
f9d1465f | 744 | static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) |
3475187d | 745 | { |
8ebdf9dc | 746 | SPARCCPU *cpu; |
98cec4a2 | 747 | CPUSPARCState *env; |
e87231d4 | 748 | ResetData *reset_info; |
3475187d | 749 | |
8f4efc55 IK |
750 | uint32_t tick_frequency = 100*1000000; |
751 | uint32_t stick_frequency = 100*1000000; | |
752 | uint32_t hstick_frequency = 100*1000000; | |
753 | ||
8ebdf9dc | 754 | if (cpu_model == NULL) { |
c7ba218d | 755 | cpu_model = hwdef->default_cpu_model; |
8ebdf9dc AF |
756 | } |
757 | cpu = cpu_sparc_init(cpu_model); | |
758 | if (cpu == NULL) { | |
62724a37 BS |
759 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); |
760 | exit(1); | |
761 | } | |
8ebdf9dc | 762 | env = &cpu->env; |
20c9f095 | 763 | |
6b678e1f | 764 | env->tick = cpu_timer_create("tick", cpu, tick_irq, |
e913cac7 MCA |
765 | tick_frequency, TICK_INT_DIS, |
766 | TICK_NPT_MASK); | |
8f4efc55 | 767 | |
6b678e1f | 768 | env->stick = cpu_timer_create("stick", cpu, stick_irq, |
e913cac7 MCA |
769 | stick_frequency, TICK_INT_DIS, |
770 | TICK_NPT_MASK); | |
20c9f095 | 771 | |
6b678e1f | 772 | env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, |
e913cac7 MCA |
773 | hstick_frequency, TICK_INT_DIS, |
774 | TICK_NPT_MASK); | |
e87231d4 | 775 | |
7267c094 | 776 | reset_info = g_malloc0(sizeof(ResetData)); |
403d7a2d | 777 | reset_info->cpu = cpu; |
44a99354 | 778 | reset_info->prom_addr = hwdef->prom_addr; |
a08d4367 | 779 | qemu_register_reset(main_cpu_reset, reset_info); |
c68ea704 | 780 | |
f9d1465f | 781 | return cpu; |
7b833f5b BS |
782 | } |
783 | ||
38bc50f7 | 784 | static void sun4uv_init(MemoryRegion *address_space_mem, |
3ef96221 | 785 | MachineState *machine, |
7b833f5b BS |
786 | const struct hwdef *hwdef) |
787 | { | |
f9d1465f | 788 | SPARCCPU *cpu; |
31688246 | 789 | Nvram *nvram; |
7b833f5b | 790 | unsigned int i; |
5f2bf0fe | 791 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
7b833f5b | 792 | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
48a18b3c | 793 | ISABus *isa_bus; |
f3b18f35 | 794 | SysBusDevice *s; |
361dea40 | 795 | qemu_irq *ivec_irqs, *pbm_irqs; |
f455e98c | 796 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 797 | DriveInfo *fd[MAX_FD]; |
c3ae40e1 | 798 | DeviceState *dev; |
a88b362c | 799 | FWCfgState *fw_cfg; |
7b833f5b | 800 | |
7b833f5b | 801 | /* init CPUs */ |
3ef96221 | 802 | cpu = cpu_devinit(machine->cpu_model, hwdef); |
7b833f5b | 803 | |
bda42033 | 804 | /* set up devices */ |
3ef96221 | 805 | ram_init(0, machine->ram_size); |
3475187d | 806 | |
1baffa46 | 807 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 808 | |
b64ba4b2 | 809 | ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, cpu, IVEC_MAX); |
361dea40 BS |
810 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2, |
811 | &pci_bus3, &pbm_irqs); | |
f2898771 | 812 | pci_vga_init(pci_bus); |
83469015 | 813 | |
c190ea07 | 814 | // XXX Should be pci_bus3 |
361dea40 | 815 | isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs); |
c190ea07 | 816 | |
e87231d4 BS |
817 | i = 0; |
818 | if (hwdef->console_serial_base) { | |
38bc50f7 | 819 | serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, |
39186d8a | 820 | NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); |
e87231d4 BS |
821 | i++; |
822 | } | |
83469015 | 823 | |
b6607a1a | 824 | serial_hds_isa_init(isa_bus, MAX_SERIAL_PORTS); |
07dc7880 | 825 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
83469015 | 826 | |
cb457d76 | 827 | for(i = 0; i < nb_nics; i++) |
29b358f9 | 828 | pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL); |
83469015 | 829 | |
d8f94e1b | 830 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
e4bcb14c | 831 | |
3b898dda BS |
832 | pci_cmd646_ide_init(pci_bus, hd, 1); |
833 | ||
48a18b3c | 834 | isa_create_simple(isa_bus, "i8042"); |
c3ae40e1 HP |
835 | |
836 | /* Floppy */ | |
e4bcb14c | 837 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 838 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 839 | } |
c3ae40e1 HP |
840 | dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); |
841 | if (fd[0]) { | |
842 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), | |
843 | &error_abort); | |
844 | } | |
845 | if (fd[1]) { | |
846 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), | |
847 | &error_abort); | |
848 | } | |
849 | qdev_prop_set_uint32(dev, "dma", -1); | |
850 | qdev_init_nofail(dev); | |
636aa70a | 851 | |
f3b18f35 MCA |
852 | /* Map NVRAM into I/O (ebus) space */ |
853 | nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); | |
854 | s = SYS_BUS_DEVICE(nvram); | |
855 | memory_region_add_subregion(get_system_io(), 0x2000, | |
856 | sysbus_mmio_get_region(s, 0)); | |
857 | ||
636aa70a | 858 | initrd_size = 0; |
5f2bf0fe | 859 | initrd_addr = 0; |
3ef96221 MA |
860 | kernel_size = sun4u_load_kernel(machine->kernel_filename, |
861 | machine->initrd_filename, | |
5f2bf0fe BS |
862 | ram_size, &initrd_size, &initrd_addr, |
863 | &kernel_addr, &kernel_entry); | |
636aa70a | 864 | |
3ef96221 MA |
865 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, |
866 | machine->boot_order, | |
5f2bf0fe | 867 | kernel_addr, kernel_size, |
3ef96221 | 868 | machine->kernel_cmdline, |
5f2bf0fe | 869 | initrd_addr, initrd_size, |
0d31cb99 BS |
870 | /* XXX: need an option to load a NVRAM image */ |
871 | 0, | |
872 | graphic_width, graphic_height, graphic_depth, | |
873 | (uint8_t *)&nd_table[0].macaddr); | |
83469015 | 874 | |
66708822 | 875 | fw_cfg = fw_cfg_init_io(BIOS_CFG_IOPORT); |
70db9222 | 876 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
905fdcb5 BS |
877 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
878 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
5f2bf0fe BS |
879 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
880 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 881 | if (machine->kernel_cmdline) { |
9c9b0512 | 882 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 MA |
883 | strlen(machine->kernel_cmdline) + 1); |
884 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
513f789f | 885 | } else { |
9c9b0512 | 886 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f | 887 | } |
5f2bf0fe BS |
888 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
889 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
3ef96221 | 890 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
7589690c BS |
891 | |
892 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
893 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
894 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
895 | ||
513f789f | 896 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
897 | } |
898 | ||
905fdcb5 BS |
899 | enum { |
900 | sun4u_id = 0, | |
901 | sun4v_id = 64, | |
e87231d4 | 902 | niagara_id, |
905fdcb5 BS |
903 | }; |
904 | ||
c7ba218d BS |
905 | static const struct hwdef hwdefs[] = { |
906 | /* Sun4u generic PC-like machine */ | |
907 | { | |
5910b047 | 908 | .default_cpu_model = "TI UltraSparc IIi", |
905fdcb5 | 909 | .machine_id = sun4u_id, |
e87231d4 BS |
910 | .prom_addr = 0x1fff0000000ULL, |
911 | .console_serial_base = 0, | |
c7ba218d BS |
912 | }, |
913 | /* Sun4v generic PC-like machine */ | |
914 | { | |
915 | .default_cpu_model = "Sun UltraSparc T1", | |
905fdcb5 | 916 | .machine_id = sun4v_id, |
e87231d4 BS |
917 | .prom_addr = 0x1fff0000000ULL, |
918 | .console_serial_base = 0, | |
919 | }, | |
920 | /* Sun4v generic Niagara machine */ | |
921 | { | |
922 | .default_cpu_model = "Sun UltraSparc T1", | |
923 | .machine_id = niagara_id, | |
924 | .prom_addr = 0xfff0000000ULL, | |
925 | .console_serial_base = 0xfff0c2c000ULL, | |
c7ba218d BS |
926 | }, |
927 | }; | |
928 | ||
929 | /* Sun4u hardware initialisation */ | |
3ef96221 | 930 | static void sun4u_init(MachineState *machine) |
5f072e1f | 931 | { |
3ef96221 | 932 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); |
c7ba218d BS |
933 | } |
934 | ||
935 | /* Sun4v hardware initialisation */ | |
3ef96221 | 936 | static void sun4v_init(MachineState *machine) |
5f072e1f | 937 | { |
3ef96221 | 938 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); |
c7ba218d BS |
939 | } |
940 | ||
e87231d4 | 941 | /* Niagara hardware initialisation */ |
3ef96221 | 942 | static void niagara_init(MachineState *machine) |
5f072e1f | 943 | { |
3ef96221 | 944 | sun4uv_init(get_system_memory(), machine, &hwdefs[2]); |
e87231d4 BS |
945 | } |
946 | ||
8a661aea | 947 | static void sun4u_class_init(ObjectClass *oc, void *data) |
e264d29d | 948 | { |
8a661aea AF |
949 | MachineClass *mc = MACHINE_CLASS(oc); |
950 | ||
e264d29d EH |
951 | mc->desc = "Sun4u platform"; |
952 | mc->init = sun4u_init; | |
953 | mc->max_cpus = 1; /* XXX for now */ | |
954 | mc->is_default = 1; | |
955 | mc->default_boot_order = "c"; | |
956 | } | |
c7ba218d | 957 | |
8a661aea AF |
958 | static const TypeInfo sun4u_type = { |
959 | .name = MACHINE_TYPE_NAME("sun4u"), | |
960 | .parent = TYPE_MACHINE, | |
961 | .class_init = sun4u_class_init, | |
962 | }; | |
e87231d4 | 963 | |
8a661aea | 964 | static void sun4v_class_init(ObjectClass *oc, void *data) |
e264d29d | 965 | { |
8a661aea AF |
966 | MachineClass *mc = MACHINE_CLASS(oc); |
967 | ||
e264d29d EH |
968 | mc->desc = "Sun4v platform"; |
969 | mc->init = sun4v_init; | |
970 | mc->max_cpus = 1; /* XXX for now */ | |
971 | mc->default_boot_order = "c"; | |
972 | } | |
973 | ||
8a661aea AF |
974 | static const TypeInfo sun4v_type = { |
975 | .name = MACHINE_TYPE_NAME("sun4v"), | |
976 | .parent = TYPE_MACHINE, | |
977 | .class_init = sun4v_class_init, | |
978 | }; | |
e264d29d | 979 | |
8a661aea | 980 | static void niagara_class_init(ObjectClass *oc, void *data) |
e264d29d | 981 | { |
8a661aea AF |
982 | MachineClass *mc = MACHINE_CLASS(oc); |
983 | ||
e264d29d EH |
984 | mc->desc = "Sun4v platform, Niagara"; |
985 | mc->init = niagara_init; | |
986 | mc->max_cpus = 1; /* XXX for now */ | |
987 | mc->default_boot_order = "c"; | |
988 | } | |
989 | ||
8a661aea AF |
990 | static const TypeInfo niagara_type = { |
991 | .name = MACHINE_TYPE_NAME("Niagara"), | |
992 | .parent = TYPE_MACHINE, | |
993 | .class_init = niagara_class_init, | |
994 | }; | |
f80f9ec9 | 995 | |
83f7d43a AF |
996 | static void sun4u_register_types(void) |
997 | { | |
998 | type_register_static(&ebus_info); | |
999 | type_register_static(&prom_info); | |
1000 | type_register_static(&ram_info); | |
83f7d43a | 1001 | |
8a661aea AF |
1002 | type_register_static(&sun4u_type); |
1003 | type_register_static(&sun4v_type); | |
1004 | type_register_static(&niagara_type); | |
1005 | } | |
1006 | ||
83f7d43a | 1007 | type_init(sun4u_register_types) |