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target-i386: Add "stepping" property to X86CPU
[mirror_qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
71ad61d3
AF		 30#include "qapi/qapi-visit-core.h"
31
28f52cc0
VR		 32#include "hyperv.h"
33
c6dc6f63
AP		 34/* feature flags taken from "Intel Processor Identification and the CPUID
35 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
36 * between feature naming conventions, aliases may be added.
37 */
38static const char *feature_name[] = {
39 "fpu", "vme", "de", "pse",
40 "tsc", "msr", "pae", "mce",
41 "cx8", "apic", NULL, "sep",
42 "mtrr", "pge", "mca", "cmov",
43 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
44 NULL, "ds" /* Intel dts */, "acpi", "mmx",
45 "fxsr", "sse", "sse2", "ss",
46 "ht" /* Intel htt */, "tm", "ia64", "pbe",
47};
48static const char *ext_feature_name[] = {
f370be3c 49 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 50 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 51 "tm2", "ssse3", "cid", NULL,
e117f772 52 "fma", "cx16", "xtpr", "pdcm",
c6dc6f63 53 NULL, NULL, "dca", "sse4.1|sse4_1",
e117f772 54 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 55 "tsc-deadline", "aes", "xsave", "osxsave",
e117f772 56 "avx", NULL, NULL, "hypervisor",
c6dc6f63
AP		 57};
58static const char *ext2_feature_name[] = {
59 "fpu", "vme", "de", "pse",
60 "tsc", "msr", "pae", "mce",
61 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
62 "mtrr", "pge", "mca", "cmov",
63 "pat", "pse36", NULL, NULL /* Linux mp */,
3ac8ebfe 64 "nx|xd", NULL, "mmxext", "mmx",
f370be3c 65 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
3ac8ebfe 66 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 67};
68static const char *ext3_feature_name[] = {
69 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
70 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 71 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 72 "skinit", "wdt", NULL, NULL,
e117f772 73 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 74 NULL, NULL, NULL, NULL,
75 NULL, NULL, NULL, NULL,
76 NULL, NULL, NULL, NULL,
77};
78
79static const char *kvm_feature_name[] = {
642258c6 80 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL,
c6dc6f63
AP		 81 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
82 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
83 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
84};
85
296acb64
JR		 86static const char *svm_feature_name[] = {
87 "npt", "lbrv", "svm_lock", "nrip_save",
88 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
89 NULL, NULL, "pause_filter", NULL,
90 "pfthreshold", NULL, NULL, NULL,
91 NULL, NULL, NULL, NULL,
92 NULL, NULL, NULL, NULL,
93 NULL, NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95};
96
c6dc6f63
AP		 97/* collects per-function cpuid data
98 */
99typedef struct model_features_t {
100 uint32_t *guest_feat;
101 uint32_t *host_feat;
102 uint32_t check_feat;
103 const char **flag_names;
104 uint32_t cpuid;
105 } model_features_t;
106
107int check_cpuid = 0;
108int enforce_cpuid = 0;
109
bb44e0d1
JK		 110void host_cpuid(uint32_t function, uint32_t count,
111 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 112{
113#if defined(CONFIG_KVM)
a1fd24af
AL		 114 uint32_t vec[4];
115
116#ifdef __x86_64__
117 asm volatile("cpuid"
118 : "=a"(vec[0]), "=b"(vec[1]),
119 "=c"(vec[2]), "=d"(vec[3])
120 : "0"(function), "c"(count) : "cc");
121#else
122 asm volatile("pusha \n\t"
123 "cpuid \n\t"
124 "mov %%eax, 0(%2) \n\t"
125 "mov %%ebx, 4(%2) \n\t"
126 "mov %%ecx, 8(%2) \n\t"
127 "mov %%edx, 12(%2) \n\t"
128 "popa"
129 : : "a"(function), "c"(count), "S"(vec)
130 : "memory", "cc");
131#endif
132
bdde476a 133 if (eax)
a1fd24af 134 *eax = vec[0];
bdde476a 135 if (ebx)
a1fd24af 136 *ebx = vec[1];
bdde476a 137 if (ecx)
a1fd24af 138 *ecx = vec[2];
bdde476a 139 if (edx)
a1fd24af 140 *edx = vec[3];
bdde476a
AP		 141#endif
142}
c6dc6f63
AP		 143
144#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
145
146/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
147 * a substring. ex if !NULL points to the first char after a substring,
148 * otherwise the string is assumed to sized by a terminating nul.
149 * Return lexical ordering of *s1:*s2.
150 */
151static int sstrcmp(const char *s1, const char *e1, const char *s2,
152 const char *e2)
153{
154 for (;;) {
155 if (!*s1 || !*s2 || *s1 != *s2)
156 return (*s1 - *s2);
157 ++s1, ++s2;
158 if (s1 == e1 && s2 == e2)
159 return (0);
160 else if (s1 == e1)
161 return (*s2);
162 else if (s2 == e2)
163 return (*s1);
164 }
165}
166
167/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
168 * '|' delimited (possibly empty) strings in which case search for a match
169 * within the alternatives proceeds left to right. Return 0 for success,
170 * non-zero otherwise.
171 */
172static int altcmp(const char *s, const char *e, const char *altstr)
173{
174 const char *p, *q;
175
176 for (q = p = altstr; ; ) {
177 while (*p && *p != '|')
178 ++p;
179 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
180 return (0);
181 if (!*p)
182 return (1);
183 else
184 q = ++p;
185 }
186}
187
188/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 189 * *pval and return true, otherwise return false
c6dc6f63 190 */
e41e0fc6
JK		 191static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
192 const char **featureset)
c6dc6f63
AP		 193{
194 uint32_t mask;
195 const char **ppc;
e41e0fc6 196 bool found = false;
c6dc6f63 197
e41e0fc6 198 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 199 if (*ppc && !altcmp(s, e, *ppc)) {
200 *pval |= mask;
e41e0fc6 201 found = true;
c6dc6f63 202 }
e41e0fc6
JK		 203 }
204 return found;
c6dc6f63
AP		 205}
206
207static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
208 uint32_t *ext_features,
209 uint32_t *ext2_features,
210 uint32_t *ext3_features,
296acb64
JR		 211 uint32_t *kvm_features,
212 uint32_t *svm_features)
c6dc6f63
AP		 213{
214 if (!lookup_feature(features, flagname, NULL, feature_name) &&
215 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
216 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
217 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 218 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
219 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 220 fprintf(stderr, "CPU feature %s not found\n", flagname);
221}
222
223typedef struct x86_def_t {
224 struct x86_def_t *next;
225 const char *name;
226 uint32_t level;
227 uint32_t vendor1, vendor2, vendor3;
228 int family;
229 int model;
230 int stepping;
b862d1fe 231 int tsc_khz;
296acb64
JR		 232 uint32_t features, ext_features, ext2_features, ext3_features;
233 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 234 uint32_t xlevel;
235 char model_id[48];
236 int vendor_override;
237 uint32_t flags;
b3baa152
BW		 238 /* Store the results of Centaur's CPUID instructions */
239 uint32_t ext4_features;
240 uint32_t xlevel2;
c6dc6f63
AP		 241} x86_def_t;
242
243#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
244#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
245 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
246#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
247 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
248 CPUID_PSE36 | CPUID_FXSR)
249#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
250#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
251 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
252 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
253 CPUID_PAE | CPUID_SEP | CPUID_APIC)
42673936 254#define EXT2_FEATURE_MASK 0x0183F3FF
c6dc6f63 255
551a2dec
AP		 256#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
257 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
258 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
259 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
260 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 261 /* partly implemented:
262 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
263 CPUID_PSE36 (needed for Solaris) */
264 /* missing:
265 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 266#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 267 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 268 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 269 /* missing:
270 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 271 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
551a2dec
AP		 272#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
273 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
274 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 275 /* missing:
276 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 277#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
278 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 279#define TCG_SVM_FEATURES 0
551a2dec 280
c6dc6f63
AP		 281/* maintains list of cpu model definitions
282 */
283static x86_def_t *x86_defs = {NULL};
284
285/* built-in cpu model definitions (deprecated)
286 */
287static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 288 {
289 .name = "qemu64",
290 .level = 4,
291 .vendor1 = CPUID_VENDOR_AMD_1,
292 .vendor2 = CPUID_VENDOR_AMD_2,
293 .vendor3 = CPUID_VENDOR_AMD_3,
294 .family = 6,
295 .model = 2,
296 .stepping = 3,
297 .features = PPRO_FEATURES |
c6dc6f63 298 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 299 CPUID_PSE36,
300 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
42673936 301 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 302 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
303 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
304 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
305 .xlevel = 0x8000000A,
306 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
307 },
308 {
309 .name = "phenom",
310 .level = 5,
311 .vendor1 = CPUID_VENDOR_AMD_1,
312 .vendor2 = CPUID_VENDOR_AMD_2,
313 .vendor3 = CPUID_VENDOR_AMD_3,
314 .family = 16,
315 .model = 2,
316 .stepping = 3,
c6dc6f63
AP		 317 .features = PPRO_FEATURES |
318 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 319 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 320 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
321 CPUID_EXT_POPCNT,
42673936 322 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 323 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
324 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 325 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 326 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
327 CPUID_EXT3_CR8LEG,
328 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
329 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
330 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
331 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 332 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 333 .xlevel = 0x8000001A,
334 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
335 },
336 {
337 .name = "core2duo",
338 .level = 10,
339 .family = 6,
340 .model = 15,
341 .stepping = 11,
c6dc6f63
AP		 342 .features = PPRO_FEATURES |
343 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 344 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
345 CPUID_HT | CPUID_TM | CPUID_PBE,
346 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
347 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
348 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 349 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
350 .ext3_features = CPUID_EXT3_LAHF_LM,
351 .xlevel = 0x80000008,
352 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
353 },
354 {
355 .name = "kvm64",
356 .level = 5,
357 .vendor1 = CPUID_VENDOR_INTEL_1,
358 .vendor2 = CPUID_VENDOR_INTEL_2,
359 .vendor3 = CPUID_VENDOR_INTEL_3,
360 .family = 15,
361 .model = 6,
362 .stepping = 1,
363 /* Missing: CPUID_VME, CPUID_HT */
364 .features = PPRO_FEATURES |
365 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
366 CPUID_PSE36,
367 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
368 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
369 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
42673936 370 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 371 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
372 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
373 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
374 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
375 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
376 .ext3_features = 0,
377 .xlevel = 0x80000008,
378 .model_id = "Common KVM processor"
379 },
c6dc6f63
AP		 380 {
381 .name = "qemu32",
382 .level = 4,
383 .family = 6,
384 .model = 3,
385 .stepping = 3,
386 .features = PPRO_FEATURES,
387 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 388 .xlevel = 0x80000004,
c6dc6f63
AP		 389 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
390 },
eafaf1e5
AP		 391 {
392 .name = "kvm32",
393 .level = 5,
394 .family = 15,
395 .model = 6,
396 .stepping = 1,
397 .features = PPRO_FEATURES |
398 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
399 .ext_features = CPUID_EXT_SSE3,
400 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
401 .ext3_features = 0,
402 .xlevel = 0x80000008,
403 .model_id = "Common 32-bit KVM processor"
404 },
c6dc6f63
AP		 405 {
406 .name = "coreduo",
407 .level = 10,
408 .family = 6,
409 .model = 14,
410 .stepping = 8,
c6dc6f63 411 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 412 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
413 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
414 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
415 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 416 .ext2_features = CPUID_EXT2_NX,
417 .xlevel = 0x80000008,
418 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
419 },
420 {
421 .name = "486",
58012d66 422 .level = 1,
c6dc6f63
AP		 423 .family = 4,
424 .model = 0,
425 .stepping = 0,
426 .features = I486_FEATURES,
427 .xlevel = 0,
428 },
429 {
430 .name = "pentium",
431 .level = 1,
432 .family = 5,
433 .model = 4,
434 .stepping = 3,
435 .features = PENTIUM_FEATURES,
436 .xlevel = 0,
437 },
438 {
439 .name = "pentium2",
440 .level = 2,
441 .family = 6,
442 .model = 5,
443 .stepping = 2,
444 .features = PENTIUM2_FEATURES,
445 .xlevel = 0,
446 },
447 {
448 .name = "pentium3",
449 .level = 2,
450 .family = 6,
451 .model = 7,
452 .stepping = 3,
453 .features = PENTIUM3_FEATURES,
454 .xlevel = 0,
455 },
456 {
457 .name = "athlon",
458 .level = 2,
459 .vendor1 = CPUID_VENDOR_AMD_1,
460 .vendor2 = CPUID_VENDOR_AMD_2,
461 .vendor3 = CPUID_VENDOR_AMD_3,
462 .family = 6,
463 .model = 2,
464 .stepping = 3,
465 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
42673936 466 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63
AP		 467 .xlevel = 0x80000008,
468 /* XXX: put another string ? */
469 .model_id = "QEMU Virtual CPU version " QEMU_VERSION,
470 },
471 {
472 .name = "n270",
473 /* original is on level 10 */
474 .level = 5,
475 .family = 6,
476 .model = 28,
477 .stepping = 2,
478 .features = PPRO_FEATURES |
8560efed
AJ		 479 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
480 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 481 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 482 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
483 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
42673936 484 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
8560efed 485 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 486 .xlevel = 0x8000000A,
487 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
488 },
489};
490
491static int cpu_x86_fill_model_id(char *str)
492{
493 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
494 int i;
495
496 for (i = 0; i < 3; i++) {
497 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
498 memcpy(str + i * 16 + 0, &eax, 4);
499 memcpy(str + i * 16 + 4, &ebx, 4);
500 memcpy(str + i * 16 + 8, &ecx, 4);
501 memcpy(str + i * 16 + 12, &edx, 4);
502 }
503 return 0;
504}
505
506static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
507{
508 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
509
510 x86_cpu_def->name = "host";
511 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
512 x86_cpu_def->level = eax;
513 x86_cpu_def->vendor1 = ebx;
514 x86_cpu_def->vendor2 = edx;
515 x86_cpu_def->vendor3 = ecx;
516
517 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
518 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
519 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
520 x86_cpu_def->stepping = eax & 0x0F;
521 x86_cpu_def->ext_features = ecx;
522 x86_cpu_def->features = edx;
523
524 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
525 x86_cpu_def->xlevel = eax;
526
527 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
528 x86_cpu_def->ext2_features = edx;
529 x86_cpu_def->ext3_features = ecx;
530 cpu_x86_fill_model_id(x86_cpu_def->model_id);
531 x86_cpu_def->vendor_override = 0;
532
b3baa152
BW		 533 /* Call Centaur's CPUID instruction. */
534 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
535 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
536 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
537 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
538 if (eax >= 0xC0000001) {
539 /* Support VIA max extended level */
540 x86_cpu_def->xlevel2 = eax;
541 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
542 x86_cpu_def->ext4_features = edx;
543 }
544 }
296acb64
JR		 545
546 /*
547 * Every SVM feature requires emulation support in KVM - so we can't just
548 * read the host features here. KVM might even support SVM features not
549 * available on the host hardware. Just set all bits and mask out the
550 * unsupported ones later.
551 */
552 x86_cpu_def->svm_features = -1;
553
c6dc6f63
AP		 554 return 0;
555}
556
557static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
558{
559 int i;
560
561 for (i = 0; i < 32; ++i)
562 if (1 << i & mask) {
563 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
564 " flag '%s' [0x%08x]\n",
565 f->cpuid >> 16, f->cpuid & 0xffff,
566 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
567 break;
568 }
569 return 0;
570}
571
572/* best effort attempt to inform user requested cpu flags aren't making
573 * their way to the guest. Note: ft[].check_feat ideally should be
574 * specified via a guest_def field to suppress report of extraneous flags.
575 */
576static int check_features_against_host(x86_def_t *guest_def)
577{
578 x86_def_t host_def;
579 uint32_t mask;
580 int rv, i;
581 struct model_features_t ft[] = {
582 {&guest_def->features, &host_def.features,
583 ~0, feature_name, 0x00000000},
584 {&guest_def->ext_features, &host_def.ext_features,
585 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
586 {&guest_def->ext2_features, &host_def.ext2_features,
587 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
588 {&guest_def->ext3_features, &host_def.ext3_features,
589 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
590
591 cpu_x86_fill_host(&host_def);
66fe09ee 592 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 593 for (mask = 1; mask; mask <<= 1)
594 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
595 !(*ft[i].host_feat & mask)) {
596 unavailable_host_feature(&ft[i], mask);
597 rv = 1;
598 }
599 return rv;
600}
601
71ad61d3
AF		 602static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
603 const char *name, Error **errp)
ed5e1ec3 604{
71ad61d3
AF		 605 X86CPU *cpu = X86_CPU(obj);
606 CPUX86State *env = &cpu->env;
607 const int64_t min = 0;
608 const int64_t max = 0xff + 0xf;
609 int64_t value;
610
611 visit_type_int(v, &value, name, errp);
612 if (error_is_set(errp)) {
613 return;
614 }
615 if (value < min || value > max) {
616 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
617 name ? name : "null", value, min, max);
618 return;
619 }
620
ed5e1ec3 621 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 622 if (value > 0x0f) {
623 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 624 } else {
71ad61d3 625 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 626 }
627}
628
c5291a4f
AF		 629static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
630 const char *name, Error **errp)
b0704cbd 631{
c5291a4f
AF		 632 X86CPU *cpu = X86_CPU(obj);
633 CPUX86State *env = &cpu->env;
634 const int64_t min = 0;
635 const int64_t max = 0xff;
636 int64_t value;
637
638 visit_type_int(v, &value, name, errp);
639 if (error_is_set(errp)) {
640 return;
641 }
642 if (value < min || value > max) {
643 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
644 name ? name : "null", value, min, max);
645 return;
646 }
647
b0704cbd 648 env->cpuid_version &= ~0xf00f0;
c5291a4f 649 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 650}
651
036e2222
AF		 652static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
653 void *opaque, const char *name,
654 Error **errp)
38c3dc46 655{
036e2222
AF		 656 X86CPU *cpu = X86_CPU(obj);
657 CPUX86State *env = &cpu->env;
658 const int64_t min = 0;
659 const int64_t max = 0xf;
660 int64_t value;
661
662 visit_type_int(v, &value, name, errp);
663 if (error_is_set(errp)) {
664 return;
665 }
666 if (value < min || value > max) {
667 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
668 name ? name : "null", value, min, max);
669 return;
670 }
671
38c3dc46 672 env->cpuid_version &= ~0xf;
036e2222 673 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 674}
675
dcce6675
AF		 676static void x86_cpuid_set_model_id(CPUX86State *env, const char *model_id)
677{
678 int c, len, i;
679
680 if (model_id == NULL) {
681 model_id = "";
682 }
683 len = strlen(model_id);
d0a6acf4 684 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 685 for (i = 0; i < 48; i++) {
686 if (i >= len) {
687 c = '\0';
688 } else {
689 c = (uint8_t)model_id[i];
690 }
691 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
692 }
693}
694
c6dc6f63
AP		 695static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
696{
697 unsigned int i;
698 x86_def_t *def;
699
d3c481b3 700 char *s = g_strdup(cpu_model);
c6dc6f63 701 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 702 /* Features to be added*/
703 uint32_t plus_features = 0, plus_ext_features = 0;
704 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
705 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
706 /* Features to be removed */
707 uint32_t minus_features = 0, minus_ext_features = 0;
708 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
709 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 710 uint32_t numvalue;
711
712 for (def = x86_defs; def; def = def->next)
04c5b17a 713 if (name && !strcmp(name, def->name))
c6dc6f63 714 break;
04c5b17a 715 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 716 cpu_x86_fill_host(x86_cpu_def);
717 } else if (!def) {
718 goto error;
719 } else {
720 memcpy(x86_cpu_def, def, sizeof(*def));
721 }
722
723 plus_kvm_features = ~0; /* not supported bits will be filtered out later */
724
725 add_flagname_to_bitmaps("hypervisor", &plus_features,
726 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 727 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 728
729 featurestr = strtok(NULL, ",");
730
731 while (featurestr) {
732 char *val;
733 if (featurestr[0] == '+') {
296acb64
JR		 734 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
735 &plus_ext_features, &plus_ext2_features,
736 &plus_ext3_features, &plus_kvm_features,
737 &plus_svm_features);
c6dc6f63 738 } else if (featurestr[0] == '-') {
296acb64
JR		 739 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
740 &minus_ext_features, &minus_ext2_features,
741 &minus_ext3_features, &minus_kvm_features,
742 &minus_svm_features);
c6dc6f63
AP		 743 } else if ((val = strchr(featurestr, '='))) {
744 *val = 0; val++;
745 if (!strcmp(featurestr, "family")) {
746 char *err;
747 numvalue = strtoul(val, &err, 0);
a88a677f 748 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 749 fprintf(stderr, "bad numerical value %s\n", val);
750 goto error;
751 }
752 x86_cpu_def->family = numvalue;
753 } else if (!strcmp(featurestr, "model")) {
754 char *err;
755 numvalue = strtoul(val, &err, 0);
756 if (!*val || *err || numvalue > 0xff) {
757 fprintf(stderr, "bad numerical value %s\n", val);
758 goto error;
759 }
760 x86_cpu_def->model = numvalue;
761 } else if (!strcmp(featurestr, "stepping")) {
762 char *err;
763 numvalue = strtoul(val, &err, 0);
764 if (!*val || *err || numvalue > 0xf) {
765 fprintf(stderr, "bad numerical value %s\n", val);
766 goto error;
767 }
768 x86_cpu_def->stepping = numvalue ;
769 } else if (!strcmp(featurestr, "level")) {
770 char *err;
771 numvalue = strtoul(val, &err, 0);
772 if (!*val || *err) {
773 fprintf(stderr, "bad numerical value %s\n", val);
774 goto error;
775 }
776 x86_cpu_def->level = numvalue;
777 } else if (!strcmp(featurestr, "xlevel")) {
778 char *err;
779 numvalue = strtoul(val, &err, 0);
780 if (!*val || *err) {
781 fprintf(stderr, "bad numerical value %s\n", val);
782 goto error;
783 }
784 if (numvalue < 0x80000000) {
2f7a21c4 785 numvalue += 0x80000000;
c6dc6f63
AP		 786 }
787 x86_cpu_def->xlevel = numvalue;
788 } else if (!strcmp(featurestr, "vendor")) {
789 if (strlen(val) != 12) {
790 fprintf(stderr, "vendor string must be 12 chars long\n");
791 goto error;
792 }
793 x86_cpu_def->vendor1 = 0;
794 x86_cpu_def->vendor2 = 0;
795 x86_cpu_def->vendor3 = 0;
796 for(i = 0; i < 4; i++) {
797 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
798 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
799 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
800 }
801 x86_cpu_def->vendor_override = 1;
802 } else if (!strcmp(featurestr, "model_id")) {
803 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
804 val);
b862d1fe
JR		 805 } else if (!strcmp(featurestr, "tsc_freq")) {
806 int64_t tsc_freq;
807 char *err;
808
809 tsc_freq = strtosz_suffix_unit(val, &err,
810 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 811 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 812 fprintf(stderr, "bad numerical value %s\n", val);
813 goto error;
814 }
815 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 816 } else if (!strcmp(featurestr, "hv_spinlocks")) {
817 char *err;
818 numvalue = strtoul(val, &err, 0);
819 if (!*val || *err) {
820 fprintf(stderr, "bad numerical value %s\n", val);
821 goto error;
822 }
823 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 824 } else {
825 fprintf(stderr, "unrecognized feature %s\n", featurestr);
826 goto error;
827 }
828 } else if (!strcmp(featurestr, "check")) {
829 check_cpuid = 1;
830 } else if (!strcmp(featurestr, "enforce")) {
831 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 832 } else if (!strcmp(featurestr, "hv_relaxed")) {
833 hyperv_enable_relaxed_timing(true);
834 } else if (!strcmp(featurestr, "hv_vapic")) {
835 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 836 } else {
837 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
838 goto error;
839 }
840 featurestr = strtok(NULL, ",");
841 }
842 x86_cpu_def->features |= plus_features;
843 x86_cpu_def->ext_features |= plus_ext_features;
844 x86_cpu_def->ext2_features |= plus_ext2_features;
845 x86_cpu_def->ext3_features |= plus_ext3_features;
846 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 847 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 848 x86_cpu_def->features &= ~minus_features;
849 x86_cpu_def->ext_features &= ~minus_ext_features;
850 x86_cpu_def->ext2_features &= ~minus_ext2_features;
851 x86_cpu_def->ext3_features &= ~minus_ext3_features;
852 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 853 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 854 if (check_cpuid) {
855 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
856 goto error;
857 }
d3c481b3 858 g_free(s);
c6dc6f63
AP		 859 return 0;
860
861error:
d3c481b3 862 g_free(s);
c6dc6f63
AP		 863 return -1;
864}
865
866/* generate a composite string into buf of all cpuid names in featureset
867 * selected by fbits. indicate truncation at bufsize in the event of overflow.
868 * if flags, suppress names undefined in featureset.
869 */
870static void listflags(char *buf, int bufsize, uint32_t fbits,
871 const char **featureset, uint32_t flags)
872{
873 const char **p = &featureset[31];
874 char *q, *b, bit;
875 int nc;
876
877 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
878 *buf = '\0';
879 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
880 if (fbits & 1 << bit && (*p || !flags)) {
881 if (*p)
882 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
883 else
884 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
885 if (bufsize <= nc) {
886 if (b) {
887 memcpy(b, "...", sizeof("..."));
888 }
889 return;
890 }
891 q += nc;
892 bufsize -= nc;
893 }
894}
895
896/* generate CPU information:
897 * -? list model names
898 * -?model list model names/IDs
899 * -?dump output all model (x86_def_t) data
900 * -?cpuid list all recognized cpuid flag names
901 */
9a78eead 902void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
c6dc6f63
AP		 903{
904 unsigned char model = !strcmp("?model", optarg);
905 unsigned char dump = !strcmp("?dump", optarg);
906 unsigned char cpuid = !strcmp("?cpuid", optarg);
907 x86_def_t *def;
908 char buf[256];
909
910 if (cpuid) {
911 (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
912 listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
913 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
914 listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
915 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
916 listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
917 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
918 listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
919 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
920 return;
921 }
922 for (def = x86_defs; def; def = def->next) {
923 snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
924 if (model || dump) {
925 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
926 } else {
927 (*cpu_fprintf)(f, "x86 %16s\n", buf);
928 }
929 if (dump) {
930 memcpy(buf, &def->vendor1, sizeof (def->vendor1));
931 memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
932 memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
933 buf[12] = '\0';
934 (*cpu_fprintf)(f,
935 " family %d model %d stepping %d level %d xlevel 0x%x"
936 " vendor \"%s\"\n",
937 def->family, def->model, def->stepping, def->level,
938 def->xlevel, buf);
939 listflags(buf, sizeof (buf), def->features, feature_name, 0);
940 (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
941 buf);
942 listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
943 0);
944 (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
945 buf);
946 listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
947 0);
948 (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
949 def->ext2_features, buf);
950 listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
951 0);
952 (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
953 def->ext3_features, buf);
954 (*cpu_fprintf)(f, "\n");
955 }
956 }
ed2c54d4
AP		 957 if (kvm_enabled()) {
958 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
959 }
c6dc6f63
AP		 960}
961
61dcd775 962int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 963{
61dcd775 964 CPUX86State *env = &cpu->env;
c6dc6f63 965 x86_def_t def1, *def = &def1;
71ad61d3 966 Error *error = NULL;
c6dc6f63 967
db0ad1ba
JR		 968 memset(def, 0, sizeof(*def));
969
c6dc6f63
AP		 970 if (cpu_x86_find_by_name(def, cpu_model) < 0)
971 return -1;
972 if (def->vendor1) {
973 env->cpuid_vendor1 = def->vendor1;
974 env->cpuid_vendor2 = def->vendor2;
975 env->cpuid_vendor3 = def->vendor3;
976 } else {
977 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
978 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
979 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
980 }
981 env->cpuid_vendor_override = def->vendor_override;
982 env->cpuid_level = def->level;
71ad61d3 983 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 984 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 985 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 986 env->cpuid_features = def->features;
c6dc6f63
AP		 987 env->cpuid_ext_features = def->ext_features;
988 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 989 env->cpuid_ext3_features = def->ext3_features;
c6dc6f63
AP		 990 env->cpuid_xlevel = def->xlevel;
991 env->cpuid_kvm_features = def->kvm_features;
296acb64 992 env->cpuid_svm_features = def->svm_features;
b3baa152
BW		 993 env->cpuid_ext4_features = def->ext4_features;
994 env->cpuid_xlevel2 = def->xlevel2;
b862d1fe 995 env->tsc_khz = def->tsc_khz;
551a2dec
AP		 996 if (!kvm_enabled()) {
997 env->cpuid_features &= TCG_FEATURES;
998 env->cpuid_ext_features &= TCG_EXT_FEATURES;
999 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1000#ifdef TARGET_X86_64
1001 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1002#endif
1003 );
1004 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 1005 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 1006 }
dcce6675 1007 x86_cpuid_set_model_id(env, def->model_id);
71ad61d3
AF		 1008 if (error_is_set(&error)) {
1009 error_free(error);
1010 return -1;
1011 }
c6dc6f63
AP		 1012 return 0;
1013}
1014
1015#if !defined(CONFIG_USER_ONLY)
1016/* copy vendor id string to 32 bit register, nul pad as needed
1017 */
1018static void cpyid(const char *s, uint32_t *id)
1019{
1020 char *d = (char *)id;
1021 char i;
1022
1023 for (i = sizeof (*id); i--; )
1024 *d++ = *s ? *s++ : '\0';
1025}
1026
1027/* interpret radix and convert from string to arbitrary scalar,
1028 * otherwise flag failure
1029 */
1030#define setscalar(pval, str, perr) \
1031{ \
1032 char *pend; \
1033 unsigned long ul; \
1034 \
1035 ul = strtoul(str, &pend, 0); \
1036 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1037}
1038
1039/* map cpuid options to feature bits, otherwise return failure
1040 * (option tags in *str are delimited by whitespace)
1041 */
1042static void setfeatures(uint32_t *pval, const char *str,
1043 const char **featureset, int *perr)
1044{
1045 const char *p, *q;
1046
1047 for (q = p = str; *p || *q; q = p) {
1048 while (iswhite(*p))
1049 q = ++p;
1050 while (*p && !iswhite(*p))
1051 ++p;
1052 if (!*q && !*p)
1053 return;
1054 if (!lookup_feature(pval, q, p, featureset)) {
1055 fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
1056 (int)(p - q), q);
1057 *perr = 1;
1058 return;
1059 }
1060 }
1061}
1062
1063/* map config file options to x86_def_t form
1064 */
1065static int cpudef_setfield(const char *name, const char *str, void *opaque)
1066{
1067 x86_def_t *def = opaque;
1068 int err = 0;
1069
1070 if (!strcmp(name, "name")) {
99e1dec0 1071 g_free((void *)def->name);
d3c481b3 1072 def->name = g_strdup(str);
c6dc6f63
AP		 1073 } else if (!strcmp(name, "model_id")) {
1074 strncpy(def->model_id, str, sizeof (def->model_id));
1075 } else if (!strcmp(name, "level")) {
1076 setscalar(&def->level, str, &err)
1077 } else if (!strcmp(name, "vendor")) {
1078 cpyid(&str[0], &def->vendor1);
1079 cpyid(&str[4], &def->vendor2);
1080 cpyid(&str[8], &def->vendor3);
1081 } else if (!strcmp(name, "family")) {
1082 setscalar(&def->family, str, &err)
1083 } else if (!strcmp(name, "model")) {
1084 setscalar(&def->model, str, &err)
1085 } else if (!strcmp(name, "stepping")) {
1086 setscalar(&def->stepping, str, &err)
1087 } else if (!strcmp(name, "feature_edx")) {
1088 setfeatures(&def->features, str, feature_name, &err);
1089 } else if (!strcmp(name, "feature_ecx")) {
1090 setfeatures(&def->ext_features, str, ext_feature_name, &err);
1091 } else if (!strcmp(name, "extfeature_edx")) {
1092 setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
1093 } else if (!strcmp(name, "extfeature_ecx")) {
1094 setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
1095 } else if (!strcmp(name, "xlevel")) {
1096 setscalar(&def->xlevel, str, &err)
1097 } else {
1098 fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
1099 return (1);
1100 }
1101 if (err) {
1102 fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
1103 return (1);
1104 }
1105 return (0);
1106}
1107
1108/* register config file entry as x86_def_t
1109 */
1110static int cpudef_register(QemuOpts *opts, void *opaque)
1111{
7267c094 1112 x86_def_t *def = g_malloc0(sizeof (x86_def_t));
c6dc6f63
AP		 1113
1114 qemu_opt_foreach(opts, cpudef_setfield, def, 1);
1115 def->next = x86_defs;
1116 x86_defs = def;
1117 return (0);
1118}
0e26b7b8
BS		 1119
1120void cpu_clear_apic_feature(CPUX86State *env)
1121{
1122 env->cpuid_features &= ~CPUID_APIC;
1123}
1124
c6dc6f63
AP		 1125#endif /* !CONFIG_USER_ONLY */
1126
1127/* register "cpudef" models defined in configuration file. Here we first
1128 * preload any built-in definitions
1129 */
1130void x86_cpudef_setup(void)
1131{
1132 int i;
1133
1134 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1135 builtin_x86_defs[i].next = x86_defs;
1136 builtin_x86_defs[i].flags = 1;
1137 x86_defs = &builtin_x86_defs[i];
1138 }
1139#if !defined(CONFIG_USER_ONLY)
3329f07b 1140 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
c6dc6f63
AP		 1141#endif
1142}
1143
c6dc6f63
AP		 1144static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1145 uint32_t *ecx, uint32_t *edx)
1146{
1147 *ebx = env->cpuid_vendor1;
1148 *edx = env->cpuid_vendor2;
1149 *ecx = env->cpuid_vendor3;
1150
1151 /* sysenter isn't supported on compatibility mode on AMD, syscall
1152 * isn't supported in compatibility mode on Intel.
1153 * Normally we advertise the actual cpu vendor, but you can override
1154 * this if you want to use KVM's sysenter/syscall emulation
1155 * in compatibility mode and when doing cross vendor migration
1156 */
89354998 1157 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1158 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1159 }
1160}
1161
1162void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1163 uint32_t *eax, uint32_t *ebx,
1164 uint32_t *ecx, uint32_t *edx)
1165{
1166 /* test if maximum index reached */
1167 if (index & 0x80000000) {
b3baa152
BW		 1168 if (index > env->cpuid_xlevel) {
1169 if (env->cpuid_xlevel2 > 0) {
1170 /* Handle the Centaur's CPUID instruction. */
1171 if (index > env->cpuid_xlevel2) {
1172 index = env->cpuid_xlevel2;
1173 } else if (index < 0xC0000000) {
1174 index = env->cpuid_xlevel;
1175 }
1176 } else {
1177 index = env->cpuid_xlevel;
1178 }
1179 }
c6dc6f63
AP		 1180 } else {
1181 if (index > env->cpuid_level)
1182 index = env->cpuid_level;
1183 }
1184
1185 switch(index) {
1186 case 0:
1187 *eax = env->cpuid_level;
1188 get_cpuid_vendor(env, ebx, ecx, edx);
1189 break;
1190 case 1:
1191 *eax = env->cpuid_version;
1192 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1193 *ecx = env->cpuid_ext_features;
1194 *edx = env->cpuid_features;
1195 if (env->nr_cores * env->nr_threads > 1) {
1196 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1197 *edx |= 1 << 28; /* HTT bit */
1198 }
1199 break;
1200 case 2:
1201 /* cache info: needed for Pentium Pro compatibility */
1202 *eax = 1;
1203 *ebx = 0;
1204 *ecx = 0;
1205 *edx = 0x2c307d;
1206 break;
1207 case 4:
1208 /* cache info: needed for Core compatibility */
1209 if (env->nr_cores > 1) {
2f7a21c4 1210 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1211 } else {
2f7a21c4 1212 *eax = 0;
c6dc6f63
AP		 1213 }
1214 switch (count) {
1215 case 0: /* L1 dcache info */
1216 *eax |= 0x0000121;
1217 *ebx = 0x1c0003f;
1218 *ecx = 0x000003f;
1219 *edx = 0x0000001;
1220 break;
1221 case 1: /* L1 icache info */
1222 *eax |= 0x0000122;
1223 *ebx = 0x1c0003f;
1224 *ecx = 0x000003f;
1225 *edx = 0x0000001;
1226 break;
1227 case 2: /* L2 cache info */
1228 *eax |= 0x0000143;
1229 if (env->nr_threads > 1) {
1230 *eax |= (env->nr_threads - 1) << 14;
1231 }
1232 *ebx = 0x3c0003f;
1233 *ecx = 0x0000fff;
1234 *edx = 0x0000001;
1235 break;
1236 default: /* end of info */
1237 *eax = 0;
1238 *ebx = 0;
1239 *ecx = 0;
1240 *edx = 0;
1241 break;
1242 }
1243 break;
1244 case 5:
1245 /* mwait info: needed for Core compatibility */
1246 *eax = 0; /* Smallest monitor-line size in bytes */
1247 *ebx = 0; /* Largest monitor-line size in bytes */
1248 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1249 *edx = 0;
1250 break;
1251 case 6:
1252 /* Thermal and Power Leaf */
1253 *eax = 0;
1254 *ebx = 0;
1255 *ecx = 0;
1256 *edx = 0;
1257 break;
f7911686
YW		 1258 case 7:
1259 if (kvm_enabled()) {
ba9bc59e
JK		 1260 KVMState *s = env->kvm_state;
1261
1262 *eax = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EAX);
1263 *ebx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EBX);
1264 *ecx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_ECX);
1265 *edx = kvm_arch_get_supported_cpuid(s, 0x7, count, R_EDX);
f7911686
YW		 1266 } else {
1267 *eax = 0;
1268 *ebx = 0;
1269 *ecx = 0;
1270 *edx = 0;
1271 }
1272 break;
c6dc6f63
AP		 1273 case 9:
1274 /* Direct Cache Access Information Leaf */
1275 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1276 *ebx = 0;
1277 *ecx = 0;
1278 *edx = 0;
1279 break;
1280 case 0xA:
1281 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1282 if (kvm_enabled()) {
1283 KVMState *s = env->kvm_state;
1284
1285 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1286 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1287 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1288 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1289 } else {
1290 *eax = 0;
1291 *ebx = 0;
1292 *ecx = 0;
1293 *edx = 0;
1294 }
c6dc6f63 1295 break;
51e49430
SY		 1296 case 0xD:
1297 /* Processor Extended State */
1298 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1299 *eax = 0;
1300 *ebx = 0;
1301 *ecx = 0;
1302 *edx = 0;
1303 break;
1304 }
1305 if (kvm_enabled()) {
ba9bc59e
JK		 1306 KVMState *s = env->kvm_state;
1307
1308 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1309 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1310 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1311 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1312 } else {
1313 *eax = 0;
1314 *ebx = 0;
1315 *ecx = 0;
1316 *edx = 0;
1317 }
1318 break;
c6dc6f63
AP		 1319 case 0x80000000:
1320 *eax = env->cpuid_xlevel;
1321 *ebx = env->cpuid_vendor1;
1322 *edx = env->cpuid_vendor2;
1323 *ecx = env->cpuid_vendor3;
1324 break;
1325 case 0x80000001:
1326 *eax = env->cpuid_version;
1327 *ebx = 0;
1328 *ecx = env->cpuid_ext3_features;
1329 *edx = env->cpuid_ext2_features;
1330
1331 /* The Linux kernel checks for the CMPLegacy bit and
1332 * discards multiple thread information if it is set.
1333 * So dont set it here for Intel to make Linux guests happy.
1334 */
1335 if (env->nr_cores * env->nr_threads > 1) {
1336 uint32_t tebx, tecx, tedx;
1337 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1338 if (tebx != CPUID_VENDOR_INTEL_1 ||
1339 tedx != CPUID_VENDOR_INTEL_2 ||
1340 tecx != CPUID_VENDOR_INTEL_3) {
1341 *ecx |= 1 << 1; /* CmpLegacy bit */
1342 }
1343 }
c6dc6f63
AP		 1344 break;
1345 case 0x80000002:
1346 case 0x80000003:
1347 case 0x80000004:
1348 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1349 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1350 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1351 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1352 break;
1353 case 0x80000005:
1354 /* cache info (L1 cache) */
1355 *eax = 0x01ff01ff;
1356 *ebx = 0x01ff01ff;
1357 *ecx = 0x40020140;
1358 *edx = 0x40020140;
1359 break;
1360 case 0x80000006:
1361 /* cache info (L2 cache) */
1362 *eax = 0;
1363 *ebx = 0x42004200;
1364 *ecx = 0x02008140;
1365 *edx = 0;
1366 break;
1367 case 0x80000008:
1368 /* virtual & phys address size in low 2 bytes. */
1369/* XXX: This value must match the one used in the MMU code. */
1370 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1371 /* 64 bit processor */
1372/* XXX: The physical address space is limited to 42 bits in exec.c. */
1373 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1374 } else {
1375 if (env->cpuid_features & CPUID_PSE36)
1376 *eax = 0x00000024; /* 36 bits physical */
1377 else
1378 *eax = 0x00000020; /* 32 bits physical */
1379 }
1380 *ebx = 0;
1381 *ecx = 0;
1382 *edx = 0;
1383 if (env->nr_cores * env->nr_threads > 1) {
1384 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1385 }
1386 break;
1387 case 0x8000000A:
296acb64
JR		 1388 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1389 *eax = 0x00000001; /* SVM Revision */
1390 *ebx = 0x00000010; /* nr of ASIDs */
1391 *ecx = 0;
1392 *edx = env->cpuid_svm_features; /* optional features */
1393 } else {
1394 *eax = 0;
1395 *ebx = 0;
1396 *ecx = 0;
1397 *edx = 0;
1398 }
c6dc6f63 1399 break;
b3baa152
BW		 1400 case 0xC0000000:
1401 *eax = env->cpuid_xlevel2;
1402 *ebx = 0;
1403 *ecx = 0;
1404 *edx = 0;
1405 break;
1406 case 0xC0000001:
1407 /* Support for VIA CPU's CPUID instruction */
1408 *eax = env->cpuid_version;
1409 *ebx = 0;
1410 *ecx = 0;
1411 *edx = env->cpuid_ext4_features;
1412 break;
1413 case 0xC0000002:
1414 case 0xC0000003:
1415 case 0xC0000004:
1416 /* Reserved for the future, and now filled with zero */
1417 *eax = 0;
1418 *ebx = 0;
1419 *ecx = 0;
1420 *edx = 0;
1421 break;
c6dc6f63
AP		 1422 default:
1423 /* reserved values: zero */
1424 *eax = 0;
1425 *ebx = 0;
1426 *ecx = 0;
1427 *edx = 0;
1428 break;
1429 }
1430}
5fd2087a
AF		 1431
1432/* CPUClass::reset() */
1433static void x86_cpu_reset(CPUState *s)
1434{
1435 X86CPU *cpu = X86_CPU(s);
1436 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1437 CPUX86State *env = &cpu->env;
c1958aea
AF		 1438 int i;
1439
1440 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1441 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1442 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1443 }
5fd2087a
AF		 1444
1445 xcc->parent_reset(s);
1446
c1958aea
AF		 1447
1448 memset(env, 0, offsetof(CPUX86State, breakpoints));
1449
1450 tlb_flush(env, 1);
1451
1452 env->old_exception = -1;
1453
1454 /* init to reset state */
1455
1456#ifdef CONFIG_SOFTMMU
1457 env->hflags |= HF_SOFTMMU_MASK;
1458#endif
1459 env->hflags2 |= HF2_GIF_MASK;
1460
1461 cpu_x86_update_cr0(env, 0x60000010);
1462 env->a20_mask = ~0x0;
1463 env->smbase = 0x30000;
1464
1465 env->idt.limit = 0xffff;
1466 env->gdt.limit = 0xffff;
1467 env->ldt.limit = 0xffff;
1468 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1469 env->tr.limit = 0xffff;
1470 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1471
1472 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1473 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1474 DESC_R_MASK | DESC_A_MASK);
1475 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1476 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1477 DESC_A_MASK);
1478 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1479 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1480 DESC_A_MASK);
1481 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1482 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1483 DESC_A_MASK);
1484 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1485 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1486 DESC_A_MASK);
1487 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1488 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1489 DESC_A_MASK);
1490
1491 env->eip = 0xfff0;
1492 env->regs[R_EDX] = env->cpuid_version;
1493
1494 env->eflags = 0x2;
1495
1496 /* FPU init */
1497 for (i = 0; i < 8; i++) {
1498 env->fptags[i] = 1;
1499 }
1500 env->fpuc = 0x37f;
1501
1502 env->mxcsr = 0x1f80;
1503
1504 env->pat = 0x0007040600070406ULL;
1505 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1506
1507 memset(env->dr, 0, sizeof(env->dr));
1508 env->dr[6] = DR6_FIXED_1;
1509 env->dr[7] = DR7_FIXED_1;
1510 cpu_breakpoint_remove_all(env, BP_CPU);
1511 cpu_watchpoint_remove_all(env, BP_CPU);
5fd2087a
AF		 1512}
1513
de024815
AF		 1514static void mce_init(X86CPU *cpu)
1515{
1516 CPUX86State *cenv = &cpu->env;
1517 unsigned int bank;
1518
1519 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1520 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1521 (CPUID_MCE | CPUID_MCA)) {
1522 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1523 cenv->mcg_ctl = ~(uint64_t)0;
1524 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1525 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1526 }
1527 }
1528}
1529
1530static void x86_cpu_initfn(Object *obj)
1531{
1532 X86CPU *cpu = X86_CPU(obj);
1533 CPUX86State *env = &cpu->env;
1534
1535 cpu_exec_init(env);
71ad61d3
AF		 1536
1537 object_property_add(obj, "family", "int",
1538 NULL,
1539 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f
AF		 1540 object_property_add(obj, "model", "int",
1541 NULL,
1542 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222
AF		 1543 object_property_add(obj, "stepping", "int",
1544 NULL,
1545 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
71ad61d3 1546
de024815
AF		 1547 env->cpuid_apic_id = env->cpu_index;
1548 mce_init(cpu);
1549}
1550
5fd2087a
AF		 1551static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1552{
1553 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1554 CPUClass *cc = CPU_CLASS(oc);
1555
1556 xcc->parent_reset = cc->reset;
1557 cc->reset = x86_cpu_reset;
1558}
1559
1560static const TypeInfo x86_cpu_type_info = {
1561 .name = TYPE_X86_CPU,
1562 .parent = TYPE_CPU,
1563 .instance_size = sizeof(X86CPU),
de024815 1564 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 1565 .abstract = false,
1566 .class_size = sizeof(X86CPUClass),
1567 .class_init = x86_cpu_common_class_init,
1568};
1569
1570static void x86_cpu_register_types(void)
1571{
1572 type_register_static(&x86_cpu_type_info);
1573}
1574
1575type_init(x86_cpu_register_types)
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