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cpus: unify qemu_*_wait_io_event
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
022c62cb 43#include "exec/ioport.h"
a2cb15b0 44#include "hw/pci/pci.h"
15eafc2e 45#include "hw/pci/msi.h"
fd563564 46#include "hw/pci/msix.h"
795c40b8 47#include "migration/blocker.h"
4c663752 48#include "exec/memattrs.h"
8b5ed7df 49#include "trace.h"
05330448
AL		 50
51//#define DEBUG_KVM
52
53#ifdef DEBUG_KVM
8c0d577e 54#define DPRINTF(fmt, ...) \
05330448
AL		 55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56#else
8c0d577e 57#define DPRINTF(fmt, ...) \
05330448
AL		 58 do { } while (0)
59#endif
60
1a03675d
GC		 61#define MSR_KVM_WALL_CLOCK 0x11
62#define MSR_KVM_SYSTEM_TIME 0x12
63
d1138251
EH		 64/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66#define MSR_BUF_SIZE 4096
d71b62a1 67
94a8d39a
JK		 68const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73};
25d2e361 74
c3a3a7d3
JK		 75static bool has_msr_star;
76static bool has_msr_hsave_pa;
c9b8f6b6 77static bool has_msr_tsc_aux;
f28558d3 78static bool has_msr_tsc_adjust;
aa82ba54 79static bool has_msr_tsc_deadline;
df67696e 80static bool has_msr_feature_control;
21e87c46 81static bool has_msr_misc_enable;
fc12d72e 82static bool has_msr_smbase;
79e9ebeb 83static bool has_msr_bndcfgs;
25d2e361 84static int lm_capable_kernel;
7bc3d711 85static bool has_msr_hv_hypercall;
f2a53c9e 86static bool has_msr_hv_crash;
744b8a94 87static bool has_msr_hv_reset;
8c145d7c 88static bool has_msr_hv_vpindex;
46eb8f98 89static bool has_msr_hv_runtime;
866eea9a 90static bool has_msr_hv_synic;
ff99aa64 91static bool has_msr_hv_stimer;
d72bc7f6 92static bool has_msr_hv_frequencies;
18cd2c17 93static bool has_msr_xss;
b827df58 94
0b368a10
JD		 95static uint32_t has_architectural_pmu_version;
96static uint32_t num_architectural_pmu_gp_counters;
97static uint32_t num_architectural_pmu_fixed_counters;
0d894367 98
28143b40
TH		 99static int has_xsave;
100static int has_xcrs;
101static int has_pit_state2;
102
87f8b626
AR		 103static bool has_msr_mcg_ext_ctl;
104
494e95e9
CP		 105static struct kvm_cpuid2 *cpuid_cache;
106
28143b40
TH		 107int kvm_has_pit_state2(void)
108{
109 return has_pit_state2;
110}
111
355023f2
PB		 112bool kvm_has_smm(void)
113{
114 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
115}
116
6053a86f
MT		 117bool kvm_has_adjust_clock_stable(void)
118{
119 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
120
121 return (ret == KVM_CLOCK_TSC_STABLE);
122}
123
1d31f66b
PM		 124bool kvm_allows_irq0_override(void)
125{
126 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
127}
128
fb506e70
RK		 129static bool kvm_x2apic_api_set_flags(uint64_t flags)
130{
131 KVMState *s = KVM_STATE(current_machine->accelerator);
132
133 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
134}
135
e391c009 136#define MEMORIZE(fn, _result) \
2a138ec3 137 ({ \
2a138ec3
RK		 138 static bool _memorized; \
139 \
140 if (_memorized) { \
141 return _result; \
142 } \
143 _memorized = true; \
144 _result = fn; \
145 })
146
e391c009
IM		 147static bool has_x2apic_api;
148
149bool kvm_has_x2apic_api(void)
150{
151 return has_x2apic_api;
152}
153
fb506e70
RK		 154bool kvm_enable_x2apic(void)
155{
2a138ec3
RK		 156 return MEMORIZE(
157 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 158 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
159 has_x2apic_api);
fb506e70
RK		 160}
161
0fd7e098
LL		 162static int kvm_get_tsc(CPUState *cs)
163{
164 X86CPU *cpu = X86_CPU(cs);
165 CPUX86State *env = &cpu->env;
166 struct {
167 struct kvm_msrs info;
168 struct kvm_msr_entry entries[1];
169 } msr_data;
170 int ret;
171
172 if (env->tsc_valid) {
173 return 0;
174 }
175
176 msr_data.info.nmsrs = 1;
177 msr_data.entries[0].index = MSR_IA32_TSC;
178 env->tsc_valid = !runstate_is_running();
179
180 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
181 if (ret < 0) {
182 return ret;
183 }
184
48e1a45c 185 assert(ret == 1);
0fd7e098
LL		 186 env->tsc = msr_data.entries[0].data;
187 return 0;
188}
189
14e6fe12 190static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 191{
0fd7e098
LL		 192 kvm_get_tsc(cpu);
193}
194
195void kvm_synchronize_all_tsc(void)
196{
197 CPUState *cpu;
198
199 if (kvm_enabled()) {
200 CPU_FOREACH(cpu) {
14e6fe12 201 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 202 }
203 }
204}
205
b827df58
AK		 206static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
207{
208 struct kvm_cpuid2 *cpuid;
209 int r, size;
210
211 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 212 cpuid = g_malloc0(size);
b827df58
AK		 213 cpuid->nent = max;
214 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 215 if (r == 0 && cpuid->nent >= max) {
216 r = -E2BIG;
217 }
b827df58
AK		 218 if (r < 0) {
219 if (r == -E2BIG) {
7267c094 220 g_free(cpuid);
b827df58
AK		 221 return NULL;
222 } else {
223 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
224 strerror(-r));
225 exit(1);
226 }
227 }
228 return cpuid;
229}
230
dd87f8a6
EH		 231/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
232 * for all entries.
233 */
234static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
235{
236 struct kvm_cpuid2 *cpuid;
237 int max = 1;
494e95e9
CP		 238
239 if (cpuid_cache != NULL) {
240 return cpuid_cache;
241 }
dd87f8a6
EH		 242 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
243 max *= 2;
244 }
494e95e9 245 cpuid_cache = cpuid;
dd87f8a6
EH		 246 return cpuid;
247}
248
a443bc34 249static const struct kvm_para_features {
0c31b744
GC		 250 int cap;
251 int feature;
252} para_features[] = {
253 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
254 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
255 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 256 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 257};
258
ba9bc59e 259static int get_para_features(KVMState *s)
0c31b744
GC		 260{
261 int i, features = 0;
262
8e03c100 263 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 264 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 265 features |= (1 << para_features[i].feature);
266 }
267 }
268
269 return features;
270}
0c31b744 271
40e80ee4
EH		 272static bool host_tsx_blacklisted(void)
273{
274 int family, model, stepping;\
275 char vendor[CPUID_VENDOR_SZ + 1];
276
277 host_vendor_fms(vendor, &family, &model, &stepping);
278
279 /* Check if we are running on a Haswell host known to have broken TSX */
280 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
281 (family == 6) &&
282 ((model == 63 && stepping < 4) ||
283 model == 60 || model == 69 || model == 70);
284}
0c31b744 285
829ae2f9
EH		 286/* Returns the value for a specific register on the cpuid entry
287 */
288static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
289{
290 uint32_t ret = 0;
291 switch (reg) {
292 case R_EAX:
293 ret = entry->eax;
294 break;
295 case R_EBX:
296 ret = entry->ebx;
297 break;
298 case R_ECX:
299 ret = entry->ecx;
300 break;
301 case R_EDX:
302 ret = entry->edx;
303 break;
304 }
305 return ret;
306}
307
4fb73f1d
EH		 308/* Find matching entry for function/index on kvm_cpuid2 struct
309 */
310static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
311 uint32_t function,
312 uint32_t index)
313{
314 int i;
315 for (i = 0; i < cpuid->nent; ++i) {
316 if (cpuid->entries[i].function == function &&
317 cpuid->entries[i].index == index) {
318 return &cpuid->entries[i];
319 }
320 }
321 /* not found: */
322 return NULL;
323}
324
ba9bc59e 325uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 326 uint32_t index, int reg)
b827df58
AK		 327{
328 struct kvm_cpuid2 *cpuid;
b827df58
AK		 329 uint32_t ret = 0;
330 uint32_t cpuid_1_edx;
8c723b79 331 bool found = false;
b827df58 332
dd87f8a6 333 cpuid = get_supported_cpuid(s);
b827df58 334
4fb73f1d
EH		 335 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
336 if (entry) {
337 found = true;
338 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 339 }
340
7b46e5ce
EH		 341 /* Fixups for the data returned by KVM, below */
342
c2acb022
EH		 343 if (function == 1 && reg == R_EDX) {
344 /* KVM before 2.6.30 misreports the following features */
345 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 346 } else if (function == 1 && reg == R_ECX) {
347 /* We can set the hypervisor flag, even if KVM does not return it on
348 * GET_SUPPORTED_CPUID
349 */
350 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 351 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
352 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
353 * and the irqchip is in the kernel.
354 */
355 if (kvm_irqchip_in_kernel() &&
356 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
357 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
358 }
41e5e76d
EH		 359
360 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
361 * without the in-kernel irqchip
362 */
363 if (!kvm_irqchip_in_kernel()) {
364 ret &= ~CPUID_EXT_X2APIC;
b827df58 365 }
28b8e4d0
JK		 366 } else if (function == 6 && reg == R_EAX) {
367 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 368 } else if (function == 7 && index == 0 && reg == R_EBX) {
369 if (host_tsx_blacklisted()) {
370 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
371 }
c2acb022
EH		 372 } else if (function == 0x80000001 && reg == R_EDX) {
373 /* On Intel, kvm returns cpuid according to the Intel spec,
374 * so add missing bits according to the AMD spec:
375 */
376 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
377 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 378 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
379 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
380 * be enabled without the in-kernel irqchip
381 */
382 if (!kvm_irqchip_in_kernel()) {
383 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
384 }
b827df58
AK		 385 }
386
0c31b744 387 /* fallback for older kernels */
8c723b79 388 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 389 ret = get_para_features(s);
b9bec74b 390 }
0c31b744
GC		 391
392 return ret;
bb0300dc 393}
bb0300dc 394
3c85e74f
HY		 395typedef struct HWPoisonPage {
396 ram_addr_t ram_addr;
397 QLIST_ENTRY(HWPoisonPage) list;
398} HWPoisonPage;
399
400static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
401 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
402
403static void kvm_unpoison_all(void *param)
404{
405 HWPoisonPage *page, *next_page;
406
407 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
408 QLIST_REMOVE(page, list);
409 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 410 g_free(page);
3c85e74f
HY		 411 }
412}
413
3c85e74f
HY		 414static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
415{
416 HWPoisonPage *page;
417
418 QLIST_FOREACH(page, &hwpoison_page_list, list) {
419 if (page->ram_addr == ram_addr) {
420 return;
421 }
422 }
ab3ad07f 423 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 424 page->ram_addr = ram_addr;
425 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
426}
427
e7701825
MT		 428static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
429 int *max_banks)
430{
431 int r;
432
14a09518 433 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 434 if (r > 0) {
435 *max_banks = r;
436 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
437 }
438 return -ENOSYS;
439}
440
bee615d4 441static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 442{
87f8b626 443 CPUState *cs = CPU(cpu);
bee615d4 444 CPUX86State *env = &cpu->env;
c34d440a
JK		 445 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
446 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
447 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 448 int flags = 0;
e7701825 449
c34d440a
JK		 450 if (code == BUS_MCEERR_AR) {
451 status |= MCI_STATUS_AR | 0x134;
452 mcg_status |= MCG_STATUS_EIPV;
453 } else {
454 status |= 0xc0;
455 mcg_status |= MCG_STATUS_RIPV;
419fb20a 456 }
87f8b626
AR		 457
458 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
459 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
460 * guest kernel back into env->mcg_ext_ctl.
461 */
462 cpu_synchronize_state(cs);
463 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
464 mcg_status |= MCG_STATUS_LMCE;
465 flags = 0;
466 }
467
8c5cf3b6 468 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 469 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 470}
419fb20a
JK		 471
472static void hardware_memory_error(void)
473{
474 fprintf(stderr, "Hardware memory error!\n");
475 exit(1);
476}
477
2ae41db2 478void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 479{
20d695a9
AF		 480 X86CPU *cpu = X86_CPU(c);
481 CPUX86State *env = &cpu->env;
419fb20a 482 ram_addr_t ram_addr;
a8170e5e 483 hwaddr paddr;
419fb20a 484
4d39892c
PB		 485 /* If we get an action required MCE, it has been injected by KVM
486 * while the VM was running. An action optional MCE instead should
487 * be coming from the main thread, which qemu_init_sigbus identifies
488 * as the "early kill" thread.
489 */
a16fc07e 490 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 491
20e0ff59 492 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 493 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 494 if (ram_addr != RAM_ADDR_INVALID &&
495 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
496 kvm_hwpoison_page_add(ram_addr);
497 kvm_mce_inject(cpu, paddr, code);
2ae41db2 498 return;
419fb20a 499 }
20e0ff59
PB		 500
501 fprintf(stderr, "Hardware memory error for memory used by "
502 "QEMU itself instead of guest system!\n");
419fb20a 503 }
20e0ff59
PB		 504
505 if (code == BUS_MCEERR_AR) {
506 hardware_memory_error();
507 }
508
509 /* Hope we are lucky for AO MCE */
419fb20a
JK		 510}
511
1bc22652 512static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 513{
1bc22652
AF		 514 CPUX86State *env = &cpu->env;
515
ab443475
JK		 516 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
517 unsigned int bank, bank_num = env->mcg_cap & 0xff;
518 struct kvm_x86_mce mce;
519
520 env->exception_injected = -1;
521
522 /*
523 * There must be at least one bank in use if an MCE is pending.
524 * Find it and use its values for the event injection.
525 */
526 for (bank = 0; bank < bank_num; bank++) {
527 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
528 break;
529 }
530 }
531 assert(bank < bank_num);
532
533 mce.bank = bank;
534 mce.status = env->mce_banks[bank * 4 + 1];
535 mce.mcg_status = env->mcg_status;
536 mce.addr = env->mce_banks[bank * 4 + 2];
537 mce.misc = env->mce_banks[bank * 4 + 3];
538
1bc22652 539 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 540 }
ab443475
JK		 541 return 0;
542}
543
1dfb4dd9 544static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 545{
317ac620 546 CPUX86State *env = opaque;
b8cc45d6
GC		 547
548 if (running) {
549 env->tsc_valid = false;
550 }
551}
552
83b17af5 553unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 554{
83b17af5 555 X86CPU *cpu = X86_CPU(cs);
7e72a45c 556 return cpu->apic_id;
b164e48e
EH		 557}
558
92067bf4
IM		 559#ifndef KVM_CPUID_SIGNATURE_NEXT
560#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
561#endif
562
563static bool hyperv_hypercall_available(X86CPU *cpu)
564{
565 return cpu->hyperv_vapic ||
566 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
567}
568
569static bool hyperv_enabled(X86CPU *cpu)
570{
7bc3d711
PB		 571 CPUState *cs = CPU(cpu);
572 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
573 (hyperv_hypercall_available(cpu) ||
48a5f3bc 574 cpu->hyperv_time ||
f2a53c9e 575 cpu->hyperv_relaxed_timing ||
744b8a94 576 cpu->hyperv_crash ||
8c145d7c 577 cpu->hyperv_reset ||
46eb8f98 578 cpu->hyperv_vpindex ||
866eea9a 579 cpu->hyperv_runtime ||
ff99aa64
AS		 580 cpu->hyperv_synic ||
581 cpu->hyperv_stimer);
92067bf4
IM		 582}
583
5031283d
HZ		 584static int kvm_arch_set_tsc_khz(CPUState *cs)
585{
586 X86CPU *cpu = X86_CPU(cs);
587 CPUX86State *env = &cpu->env;
588 int r;
589
590 if (!env->tsc_khz) {
591 return 0;
592 }
593
594 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
595 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
596 -ENOTSUP;
597 if (r < 0) {
598 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
599 * TSC frequency doesn't match the one we want.
600 */
601 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
602 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
603 -ENOTSUP;
604 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 605 warn_report("TSC frequency mismatch between "
606 "VM (%" PRId64 " kHz) and host (%d kHz), "
607 "and TSC scaling unavailable",
608 env->tsc_khz, cur_freq);
5031283d
HZ		 609 return r;
610 }
611 }
612
613 return 0;
614}
615
4bb95b82
LP		 616static bool tsc_is_stable_and_known(CPUX86State *env)
617{
618 if (!env->tsc_khz) {
619 return false;
620 }
621 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
622 || env->user_tsc_khz;
623}
624
c35bd19a
EY		 625static int hyperv_handle_properties(CPUState *cs)
626{
627 X86CPU *cpu = X86_CPU(cs);
628 CPUX86State *env = &cpu->env;
629
3ddcd2ed
EH		 630 if (cpu->hyperv_time &&
631 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
632 cpu->hyperv_time = false;
633 }
634
c35bd19a 635 if (cpu->hyperv_relaxed_timing) {
5e953812 636 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 637 }
638 if (cpu->hyperv_vapic) {
5e953812
RK		 639 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
640 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 641 }
3ddcd2ed 642 if (cpu->hyperv_time) {
5e953812
RK		 643 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
644 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
645 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
d72bc7f6
LP		 646
647 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
5e953812
RK		 648 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
649 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
d72bc7f6 650 }
c35bd19a
EY		 651 }
652 if (cpu->hyperv_crash && has_msr_hv_crash) {
5e953812 653 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 654 }
5e953812 655 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
c35bd19a 656 if (cpu->hyperv_reset && has_msr_hv_reset) {
5e953812 657 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a
EY		 658 }
659 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
5e953812 660 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a
EY		 661 }
662 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
5e953812 663 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 664 }
665 if (cpu->hyperv_synic) {
c35bd19a
EY		 666 if (!has_msr_hv_synic ||
667 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
668 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
669 return -ENOSYS;
670 }
671
5e953812 672 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a
EY		 673 }
674 if (cpu->hyperv_stimer) {
675 if (!has_msr_hv_stimer) {
676 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
677 return -ENOSYS;
678 }
5e953812 679 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a
EY		 680 }
681 return 0;
682}
683
68bfd0ad
MT		 684static Error *invtsc_mig_blocker;
685
f8bb0565 686#define KVM_MAX_CPUID_ENTRIES 100
0893d460 687
20d695a9 688int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 689{
690 struct {
486bd5a2 691 struct kvm_cpuid2 cpuid;
f8bb0565 692 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 693 } QEMU_PACKED cpuid_data;
20d695a9
AF		 694 X86CPU *cpu = X86_CPU(cs);
695 CPUX86State *env = &cpu->env;
486bd5a2 696 uint32_t limit, i, j, cpuid_i;
a33609ca 697 uint32_t unused;
bb0300dc 698 struct kvm_cpuid_entry2 *c;
bb0300dc 699 uint32_t signature[3];
234cc647 700 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 701 int r;
fe44dc91 702 Error *local_err = NULL;
05330448 703
ef4cbe14
SW		 704 memset(&cpuid_data, 0, sizeof(cpuid_data));
705
05330448
AL		 706 cpuid_i = 0;
707
ddb98b5a
LP		 708 r = kvm_arch_set_tsc_khz(cs);
709 if (r < 0) {
710 goto fail;
711 }
712
713 /* vcpu's TSC frequency is either specified by user, or following
714 * the value used by KVM if the former is not present. In the
715 * latter case, we query it from KVM and record in env->tsc_khz,
716 * so that vcpu's TSC frequency can be migrated later via this field.
717 */
718 if (!env->tsc_khz) {
719 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
720 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
721 -ENOTSUP;
722 if (r > 0) {
723 env->tsc_khz = r;
724 }
725 }
726
bb0300dc 727 /* Paravirtualization CPUIDs */
234cc647
PB		 728 if (hyperv_enabled(cpu)) {
729 c = &cpuid_data.entries[cpuid_i++];
5e953812 730 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 731 if (!cpu->hyperv_vendor_id) {
732 memcpy(signature, "Microsoft Hv", 12);
733 } else {
734 size_t len = strlen(cpu->hyperv_vendor_id);
735
736 if (len > 12) {
737 error_report("hv-vendor-id truncated to 12 characters");
738 len = 12;
739 }
740 memset(signature, 0, 12);
741 memcpy(signature, cpu->hyperv_vendor_id, len);
742 }
5e953812 743 c->eax = HV_CPUID_MIN;
234cc647
PB		 744 c->ebx = signature[0];
745 c->ecx = signature[1];
746 c->edx = signature[2];
0c31b744 747
234cc647 748 c = &cpuid_data.entries[cpuid_i++];
5e953812 749 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 750 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
751 c->eax = signature[0];
234cc647
PB		 752 c->ebx = 0;
753 c->ecx = 0;
754 c->edx = 0;
eab70139
VR		 755
756 c = &cpuid_data.entries[cpuid_i++];
5e953812 757 c->function = HV_CPUID_VERSION;
eab70139
VR		 758 c->eax = 0x00001bbc;
759 c->ebx = 0x00060001;
760
761 c = &cpuid_data.entries[cpuid_i++];
5e953812 762 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 763 r = hyperv_handle_properties(cs);
764 if (r) {
765 return r;
46eb8f98 766 }
c35bd19a
EY		 767 c->eax = env->features[FEAT_HYPERV_EAX];
768 c->ebx = env->features[FEAT_HYPERV_EBX];
769 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 770
eab70139 771 c = &cpuid_data.entries[cpuid_i++];
5e953812 772 c->function = HV_CPUID_ENLIGHTMENT_INFO;
92067bf4 773 if (cpu->hyperv_relaxed_timing) {
5e953812 774 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
eab70139 775 }
2d5aa872 776 if (cpu->hyperv_vapic) {
5e953812 777 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
eab70139 778 }
92067bf4 779 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 780
781 c = &cpuid_data.entries[cpuid_i++];
5e953812 782 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 783
784 c->eax = cpu->hv_max_vps;
eab70139
VR		 785 c->ebx = 0x40;
786
234cc647 787 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 788 has_msr_hv_hypercall = true;
eab70139
VR		 789 }
790
f522d2ac
AW		 791 if (cpu->expose_kvm) {
792 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
793 c = &cpuid_data.entries[cpuid_i++];
794 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 795 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 796 c->ebx = signature[0];
797 c->ecx = signature[1];
798 c->edx = signature[2];
234cc647 799
f522d2ac
AW		 800 c = &cpuid_data.entries[cpuid_i++];
801 c->function = KVM_CPUID_FEATURES | kvm_base;
802 c->eax = env->features[FEAT_KVM];
f522d2ac 803 }
917367aa 804
a33609ca 805 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 806
807 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 808 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
809 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
810 abort();
811 }
bb0300dc 812 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 813
814 switch (i) {
a36b1029
AL		 815 case 2: {
816 /* Keep reading function 2 till all the input is received */
817 int times;
818
a36b1029 819 c->function = i;
a33609ca
AL		 820 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
821 KVM_CPUID_FLAG_STATE_READ_NEXT;
822 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
823 times = c->eax & 0xff;
a36b1029
AL		 824
825 for (j = 1; j < times; ++j) {
f8bb0565
IM		 826 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
827 fprintf(stderr, "cpuid_data is full, no space for "
828 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
829 abort();
830 }
a33609ca 831 c = &cpuid_data.entries[cpuid_i++];
a36b1029 832 c->function = i;
a33609ca
AL		 833 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
834 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 835 }
836 break;
837 }
486bd5a2
AL		 838 case 4:
839 case 0xb:
840 case 0xd:
841 for (j = 0; ; j++) {
31e8c696
AP		 842 if (i == 0xd && j == 64) {
843 break;
844 }
486bd5a2
AL		 845 c->function = i;
846 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
847 c->index = j;
a33609ca 848 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 849
b9bec74b 850 if (i == 4 && c->eax == 0) {
486bd5a2 851 break;
b9bec74b
JK		 852 }
853 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 854 break;
b9bec74b
JK		 855 }
856 if (i == 0xd && c->eax == 0) {
31e8c696 857 continue;
b9bec74b 858 }
f8bb0565
IM		 859 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
860 fprintf(stderr, "cpuid_data is full, no space for "
861 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
862 abort();
863 }
a33609ca 864 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 865 }
866 break;
867 default:
486bd5a2 868 c->function = i;
a33609ca
AL		 869 c->flags = 0;
870 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 871 break;
872 }
05330448 873 }
0d894367
PB		 874
875 if (limit >= 0x0a) {
0b368a10 876 uint32_t eax, edx;
0d894367 877
0b368a10
JD		 878 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
879
880 has_architectural_pmu_version = eax & 0xff;
881 if (has_architectural_pmu_version > 0) {
882 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 883
884 /* Shouldn't be more than 32, since that's the number of bits
885 * available in EBX to tell us _which_ counters are available.
886 * Play it safe.
887 */
0b368a10
JD		 888 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
889 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
890 }
891
892 if (has_architectural_pmu_version > 1) {
893 num_architectural_pmu_fixed_counters = edx & 0x1f;
894
895 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
896 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
897 }
0d894367
PB		 898 }
899 }
900 }
901
a33609ca 902 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 903
904 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 905 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
906 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
907 abort();
908 }
bb0300dc 909 c = &cpuid_data.entries[cpuid_i++];
05330448 910
05330448 911 c->function = i;
a33609ca
AL		 912 c->flags = 0;
913 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 914 }
915
b3baa152
BW		 916 /* Call Centaur's CPUID instructions they are supported. */
917 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 918 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
919
920 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 921 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
922 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
923 abort();
924 }
b3baa152
BW		 925 c = &cpuid_data.entries[cpuid_i++];
926
927 c->function = i;
928 c->flags = 0;
929 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
930 }
931 }
932
05330448
AL		 933 cpuid_data.cpuid.nent = cpuid_i;
934
e7701825 935 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 936 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 937 (CPUID_MCE | CPUID_MCA)
a60f24b5 938 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 939 uint64_t mcg_cap, unsupported_caps;
e7701825 940 int banks;
32a42024 941 int ret;
e7701825 942
a60f24b5 943 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 944 if (ret < 0) {
945 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
946 return ret;
e7701825 947 }
75d49497 948
2590f15b 949 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 950 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 951 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 952 return -ENOTSUP;
75d49497 953 }
49b69cbf 954
5120901a
EH		 955 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
956 if (unsupported_caps) {
87f8b626
AR		 957 if (unsupported_caps & MCG_LMCE_P) {
958 error_report("kvm: LMCE not supported");
959 return -ENOTSUP;
960 }
3dc6f869
AF		 961 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
962 unsupported_caps);
5120901a
EH		 963 }
964
2590f15b
EH		 965 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
966 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 967 if (ret < 0) {
968 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
969 return ret;
970 }
e7701825 971 }
e7701825 972
b8cc45d6
GC		 973 qemu_add_vm_change_state_handler(cpu_update_state, env);
974
df67696e
LJ		 975 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
976 if (c) {
977 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
978 !!(c->ecx & CPUID_EXT_SMX);
979 }
980
87f8b626
AR		 981 if (env->mcg_cap & MCG_LMCE_P) {
982 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
983 }
984
d99569d9
EH		 985 if (!env->user_tsc_khz) {
986 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
987 invtsc_mig_blocker == NULL) {
988 /* for migration */
989 error_setg(&invtsc_mig_blocker,
990 "State blocked by non-migratable CPU device"
991 " (invtsc flag)");
fe44dc91
AA		 992 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
993 if (local_err) {
994 error_report_err(local_err);
995 error_free(invtsc_mig_blocker);
996 goto fail;
997 }
d99569d9
EH		 998 /* for savevm */
999 vmstate_x86_cpu.unmigratable = 1;
1000 }
68bfd0ad
MT		 1001 }
1002
9954a158
PDJ		 1003 if (cpu->vmware_cpuid_freq
1004 /* Guests depend on 0x40000000 to detect this feature, so only expose
1005 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1006 && cpu->expose_kvm
1007 && kvm_base == KVM_CPUID_SIGNATURE
1008 /* TSC clock must be stable and known for this feature. */
4bb95b82 1009 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1010
1011 c = &cpuid_data.entries[cpuid_i++];
1012 c->function = KVM_CPUID_SIGNATURE | 0x10;
1013 c->eax = env->tsc_khz;
1014 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1015 * APIC_BUS_CYCLE_NS */
1016 c->ebx = 1000000;
1017 c->ecx = c->edx = 0;
1018
1019 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1020 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1021 }
1022
1023 cpuid_data.cpuid.nent = cpuid_i;
1024
1025 cpuid_data.cpuid.padding = 0;
1026 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1027 if (r) {
1028 goto fail;
1029 }
1030
28143b40 1031 if (has_xsave) {
fabacc0f
JK		 1032 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1033 }
d71b62a1 1034 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1035
273c515c
PB		 1036 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1037 has_msr_tsc_aux = false;
1038 }
d1ae67f6 1039
e7429073 1040 return 0;
fe44dc91
AA		 1041
1042 fail:
1043 migrate_del_blocker(invtsc_mig_blocker);
1044 return r;
05330448
AL		 1045}
1046
50a2c6e5 1047void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1048{
20d695a9 1049 CPUX86State *env = &cpu->env;
dd673288 1050
1a5e9d2f 1051 env->xcr0 = 1;
ddced198 1052 if (kvm_irqchip_in_kernel()) {
dd673288 1053 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1054 KVM_MP_STATE_UNINITIALIZED;
1055 } else {
1056 env->mp_state = KVM_MP_STATE_RUNNABLE;
1057 }
689141dd
RK		 1058
1059 if (cpu->hyperv_synic) {
1060 int i;
1061 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1062 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1063 }
1064 }
caa5af0f
JK		 1065}
1066
e0723c45
PB		 1067void kvm_arch_do_init_vcpu(X86CPU *cpu)
1068{
1069 CPUX86State *env = &cpu->env;
1070
1071 /* APs get directly into wait-for-SIPI state. */
1072 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1073 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1074 }
1075}
1076
c3a3a7d3 1077static int kvm_get_supported_msrs(KVMState *s)
05330448 1078{
75b10c43 1079 static int kvm_supported_msrs;
c3a3a7d3 1080 int ret = 0;
05330448
AL		 1081
1082 /* first time */
75b10c43 1083 if (kvm_supported_msrs == 0) {
05330448
AL		 1084 struct kvm_msr_list msr_list, *kvm_msr_list;
1085
75b10c43 1086 kvm_supported_msrs = -1;
05330448
AL		 1087
1088 /* Obtain MSR list from KVM. These are the MSRs that we must
1089 * save/restore */
4c9f7372 1090 msr_list.nmsrs = 0;
c3a3a7d3 1091 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1092 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1093 return ret;
6fb6d245 1094 }
d9db889f
JK		 1095 /* Old kernel modules had a bug and could write beyond the provided
1096 memory. Allocate at least a safe amount of 1K. */
7267c094 1097 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1098 msr_list.nmsrs *
1099 sizeof(msr_list.indices[0])));
05330448 1100
55308450 1101 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1102 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1103 if (ret >= 0) {
1104 int i;
1105
1106 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1107 switch (kvm_msr_list->indices[i]) {
1108 case MSR_STAR:
c3a3a7d3 1109 has_msr_star = true;
1d268dec
LP		 1110 break;
1111 case MSR_VM_HSAVE_PA:
c3a3a7d3 1112 has_msr_hsave_pa = true;
1d268dec
LP		 1113 break;
1114 case MSR_TSC_AUX:
c9b8f6b6 1115 has_msr_tsc_aux = true;
1d268dec
LP		 1116 break;
1117 case MSR_TSC_ADJUST:
f28558d3 1118 has_msr_tsc_adjust = true;
1d268dec
LP		 1119 break;
1120 case MSR_IA32_TSCDEADLINE:
aa82ba54 1121 has_msr_tsc_deadline = true;
1d268dec
LP		 1122 break;
1123 case MSR_IA32_SMBASE:
fc12d72e 1124 has_msr_smbase = true;
1d268dec
LP		 1125 break;
1126 case MSR_IA32_MISC_ENABLE:
21e87c46 1127 has_msr_misc_enable = true;
1d268dec
LP		 1128 break;
1129 case MSR_IA32_BNDCFGS:
79e9ebeb 1130 has_msr_bndcfgs = true;
1d268dec
LP		 1131 break;
1132 case MSR_IA32_XSS:
18cd2c17 1133 has_msr_xss = true;
3c254ab8 1134 break;
1d268dec 1135 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1136 has_msr_hv_crash = true;
1d268dec
LP		 1137 break;
1138 case HV_X64_MSR_RESET:
744b8a94 1139 has_msr_hv_reset = true;
1d268dec
LP		 1140 break;
1141 case HV_X64_MSR_VP_INDEX:
8c145d7c 1142 has_msr_hv_vpindex = true;
1d268dec
LP		 1143 break;
1144 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1145 has_msr_hv_runtime = true;
1d268dec
LP		 1146 break;
1147 case HV_X64_MSR_SCONTROL:
866eea9a 1148 has_msr_hv_synic = true;
1d268dec
LP		 1149 break;
1150 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1151 has_msr_hv_stimer = true;
1d268dec 1152 break;
d72bc7f6
LP		 1153 case HV_X64_MSR_TSC_FREQUENCY:
1154 has_msr_hv_frequencies = true;
1155 break;
ff99aa64 1156 }
05330448
AL		 1157 }
1158 }
1159
7267c094 1160 g_free(kvm_msr_list);
05330448
AL		 1161 }
1162
c3a3a7d3 1163 return ret;
05330448
AL		 1164}
1165
6410848b
PB		 1166static Notifier smram_machine_done;
1167static KVMMemoryListener smram_listener;
1168static AddressSpace smram_address_space;
1169static MemoryRegion smram_as_root;
1170static MemoryRegion smram_as_mem;
1171
1172static void register_smram_listener(Notifier *n, void *unused)
1173{
1174 MemoryRegion *smram =
1175 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1176
1177 /* Outer container... */
1178 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1179 memory_region_set_enabled(&smram_as_root, true);
1180
1181 /* ... with two regions inside: normal system memory with low
1182 * priority, and...
1183 */
1184 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1185 get_system_memory(), 0, ~0ull);
1186 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1187 memory_region_set_enabled(&smram_as_mem, true);
1188
1189 if (smram) {
1190 /* ... SMRAM with higher priority */
1191 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1192 memory_region_set_enabled(smram, true);
1193 }
1194
1195 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1196 kvm_memory_listener_register(kvm_state, &smram_listener,
1197 &smram_address_space, 1);
1198}
1199
b16565b3 1200int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1201{
11076198 1202 uint64_t identity_base = 0xfffbc000;
39d6960a 1203 uint64_t shadow_mem;
20420430 1204 int ret;
25d2e361 1205 struct utsname utsname;
20420430 1206
28143b40
TH		 1207#ifdef KVM_CAP_XSAVE
1208 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1209#endif
1210
1211#ifdef KVM_CAP_XCRS
1212 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1213#endif
1214
1215#ifdef KVM_CAP_PIT_STATE2
1216 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1217#endif
1218
c3a3a7d3 1219 ret = kvm_get_supported_msrs(s);
20420430 1220 if (ret < 0) {
20420430
SY		 1221 return ret;
1222 }
25d2e361
MT		 1223
1224 uname(&utsname);
1225 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1226
4c5b10b7 1227 /*
11076198
JK		 1228 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1229 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1230 * Since these must be part of guest physical memory, we need to allocate
1231 * them, both by setting their start addresses in the kernel and by
1232 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1233 *
1234 * Older KVM versions may not support setting the identity map base. In
1235 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1236 * size.
4c5b10b7 1237 */
11076198
JK		 1238 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1239 /* Allows up to 16M BIOSes. */
1240 identity_base = 0xfeffc000;
1241
1242 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1243 if (ret < 0) {
1244 return ret;
1245 }
4c5b10b7 1246 }
e56ff191 1247
11076198
JK		 1248 /* Set TSS base one page after EPT identity map. */
1249 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1250 if (ret < 0) {
1251 return ret;
1252 }
1253
11076198
JK		 1254 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1255 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1256 if (ret < 0) {
11076198 1257 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1258 return ret;
1259 }
3c85e74f 1260 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1261
4689b77b 1262 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1263 if (shadow_mem != -1) {
1264 shadow_mem /= 4096;
1265 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1266 if (ret < 0) {
1267 return ret;
39d6960a
JK		 1268 }
1269 }
6410848b 1270
d870cfde
GA		 1271 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1272 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1273 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1274 smram_machine_done.notify = register_smram_listener;
1275 qemu_add_machine_init_done_notifier(&smram_machine_done);
1276 }
11076198 1277 return 0;
05330448 1278}
b9bec74b 1279
05330448
AL		 1280static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1281{
1282 lhs->selector = rhs->selector;
1283 lhs->base = rhs->base;
1284 lhs->limit = rhs->limit;
1285 lhs->type = 3;
1286 lhs->present = 1;
1287 lhs->dpl = 3;
1288 lhs->db = 0;
1289 lhs->s = 1;
1290 lhs->l = 0;
1291 lhs->g = 0;
1292 lhs->avl = 0;
1293 lhs->unusable = 0;
1294}
1295
1296static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1297{
1298 unsigned flags = rhs->flags;
1299 lhs->selector = rhs->selector;
1300 lhs->base = rhs->base;
1301 lhs->limit = rhs->limit;
1302 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1303 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1304 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1305 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1306 lhs->s = (flags & DESC_S_MASK) != 0;
1307 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1308 lhs->g = (flags & DESC_G_MASK) != 0;
1309 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1310 lhs->unusable = !lhs->present;
7e680753 1311 lhs->padding = 0;
05330448
AL		 1312}
1313
1314static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1315{
1316 lhs->selector = rhs->selector;
1317 lhs->base = rhs->base;
1318 lhs->limit = rhs->limit;
d45fc087
RP		 1319 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1320 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1321 (rhs->dpl << DESC_DPL_SHIFT) |
1322 (rhs->db << DESC_B_SHIFT) |
1323 (rhs->s * DESC_S_MASK) |
1324 (rhs->l << DESC_L_SHIFT) |
1325 (rhs->g * DESC_G_MASK) |
1326 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1327}
1328
1329static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1330{
b9bec74b 1331 if (set) {
05330448 1332 *kvm_reg = *qemu_reg;
b9bec74b 1333 } else {
05330448 1334 *qemu_reg = *kvm_reg;
b9bec74b 1335 }
05330448
AL		 1336}
1337
1bc22652 1338static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1339{
1bc22652 1340 CPUX86State *env = &cpu->env;
05330448
AL		 1341 struct kvm_regs regs;
1342 int ret = 0;
1343
1344 if (!set) {
1bc22652 1345 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1346 if (ret < 0) {
05330448 1347 return ret;
b9bec74b 1348 }
05330448
AL		 1349 }
1350
1351 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1352 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1353 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1354 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1355 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1356 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1357 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1358 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1359#ifdef TARGET_X86_64
1360 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1361 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1362 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1363 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1364 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1365 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1366 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1367 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1368#endif
1369
1370 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1371 kvm_getput_reg(&regs.rip, &env->eip, set);
1372
b9bec74b 1373 if (set) {
1bc22652 1374 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1375 }
05330448
AL		 1376
1377 return ret;
1378}
1379
1bc22652 1380static int kvm_put_fpu(X86CPU *cpu)
05330448 1381{
1bc22652 1382 CPUX86State *env = &cpu->env;
05330448
AL		 1383 struct kvm_fpu fpu;
1384 int i;
1385
1386 memset(&fpu, 0, sizeof fpu);
1387 fpu.fsw = env->fpus & ~(7 << 11);
1388 fpu.fsw |= (env->fpstt & 7) << 11;
1389 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1390 fpu.last_opcode = env->fpop;
1391 fpu.last_ip = env->fpip;
1392 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1393 for (i = 0; i < 8; ++i) {
1394 fpu.ftwx |= (!env->fptags[i]) << i;
1395 }
05330448 1396 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1397 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1398 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1399 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1400 }
05330448
AL		 1401 fpu.mxcsr = env->mxcsr;
1402
1bc22652 1403 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1404}
1405
6b42494b
JK		 1406#define XSAVE_FCW_FSW 0
1407#define XSAVE_FTW_FOP 1
f1665b21
SY		 1408#define XSAVE_CWD_RIP 2
1409#define XSAVE_CWD_RDP 4
1410#define XSAVE_MXCSR 6
1411#define XSAVE_ST_SPACE 8
1412#define XSAVE_XMM_SPACE 40
1413#define XSAVE_XSTATE_BV 128
1414#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1415#define XSAVE_BNDREGS 240
1416#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1417#define XSAVE_OPMASK 272
1418#define XSAVE_ZMM_Hi256 288
1419#define XSAVE_Hi16_ZMM 416
f74eefe0 1420#define XSAVE_PKRU 672
f1665b21 1421
b503717d
EH		 1422#define XSAVE_BYTE_OFFSET(word_offset) \
1423 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1424
1425#define ASSERT_OFFSET(word_offset, field) \
1426 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1427 offsetof(X86XSaveArea, field))
1428
1429ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1430ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1431ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1432ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1433ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1434ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1435ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1436ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1437ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1438ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1439ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1440ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1441ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1442ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1443ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1444
1bc22652 1445static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1446{
1bc22652 1447 CPUX86State *env = &cpu->env;
86cd2ea0 1448 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1449
28143b40 1450 if (!has_xsave) {
1bc22652 1451 return kvm_put_fpu(cpu);
b9bec74b 1452 }
86a57621 1453 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1454
9be38598 1455 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1456}
1457
1bc22652 1458static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1459{
1bc22652 1460 CPUX86State *env = &cpu->env;
bdfc8480 1461 struct kvm_xcrs xcrs = {};
f1665b21 1462
28143b40 1463 if (!has_xcrs) {
f1665b21 1464 return 0;
b9bec74b 1465 }
f1665b21
SY		 1466
1467 xcrs.nr_xcrs = 1;
1468 xcrs.flags = 0;
1469 xcrs.xcrs[0].xcr = 0;
1470 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1471 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1472}
1473
1bc22652 1474static int kvm_put_sregs(X86CPU *cpu)
05330448 1475{
1bc22652 1476 CPUX86State *env = &cpu->env;
05330448
AL		 1477 struct kvm_sregs sregs;
1478
0e607a80
JK		 1479 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1480 if (env->interrupt_injected >= 0) {
1481 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1482 (uint64_t)1 << (env->interrupt_injected % 64);
1483 }
05330448
AL		 1484
1485 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1486 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1487 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1488 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1489 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1490 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1491 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1492 } else {
b9bec74b
JK		 1493 set_seg(&sregs.cs, &env->segs[R_CS]);
1494 set_seg(&sregs.ds, &env->segs[R_DS]);
1495 set_seg(&sregs.es, &env->segs[R_ES]);
1496 set_seg(&sregs.fs, &env->segs[R_FS]);
1497 set_seg(&sregs.gs, &env->segs[R_GS]);
1498 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1499 }
1500
1501 set_seg(&sregs.tr, &env->tr);
1502 set_seg(&sregs.ldt, &env->ldt);
1503
1504 sregs.idt.limit = env->idt.limit;
1505 sregs.idt.base = env->idt.base;
7e680753 1506 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1507 sregs.gdt.limit = env->gdt.limit;
1508 sregs.gdt.base = env->gdt.base;
7e680753 1509 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1510
1511 sregs.cr0 = env->cr[0];
1512 sregs.cr2 = env->cr[2];
1513 sregs.cr3 = env->cr[3];
1514 sregs.cr4 = env->cr[4];
1515
02e51483
CF		 1516 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1517 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1518
1519 sregs.efer = env->efer;
1520
1bc22652 1521 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1522}
1523
d71b62a1
EH		 1524static void kvm_msr_buf_reset(X86CPU *cpu)
1525{
1526 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1527}
1528
9c600a84
EH		 1529static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1530{
1531 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1532 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1533 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1534
1535 assert((void *)(entry + 1) <= limit);
1536
1abc2cae
EH		 1537 entry->index = index;
1538 entry->reserved = 0;
1539 entry->data = value;
9c600a84
EH		 1540 msrs->nmsrs++;
1541}
1542
73e1b8f2
PB		 1543static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1544{
1545 kvm_msr_buf_reset(cpu);
1546 kvm_msr_entry_add(cpu, index, value);
1547
1548 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1549}
1550
f8d9ccf8
DDAG		 1551void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1552{
1553 int ret;
1554
1555 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1556 assert(ret == 1);
1557}
1558
7477cd38
MT		 1559static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1560{
1561 CPUX86State *env = &cpu->env;
48e1a45c 1562 int ret;
7477cd38
MT		 1563
1564 if (!has_msr_tsc_deadline) {
1565 return 0;
1566 }
1567
73e1b8f2 1568 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1569 if (ret < 0) {
1570 return ret;
1571 }
1572
1573 assert(ret == 1);
1574 return 0;
7477cd38
MT		 1575}
1576
6bdf863d
JK		 1577/*
1578 * Provide a separate write service for the feature control MSR in order to
1579 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1580 * before writing any other state because forcibly leaving nested mode
1581 * invalidates the VCPU state.
1582 */
1583static int kvm_put_msr_feature_control(X86CPU *cpu)
1584{
48e1a45c
PB		 1585 int ret;
1586
1587 if (!has_msr_feature_control) {
1588 return 0;
1589 }
6bdf863d 1590
73e1b8f2
PB		 1591 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1592 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1593 if (ret < 0) {
1594 return ret;
1595 }
1596
1597 assert(ret == 1);
1598 return 0;
6bdf863d
JK		 1599}
1600
1bc22652 1601static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1602{
1bc22652 1603 CPUX86State *env = &cpu->env;
9c600a84 1604 int i;
48e1a45c 1605 int ret;
05330448 1606
d71b62a1
EH		 1607 kvm_msr_buf_reset(cpu);
1608
9c600a84
EH		 1609 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1610 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1611 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1612 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1613 if (has_msr_star) {
9c600a84 1614 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1615 }
c3a3a7d3 1616 if (has_msr_hsave_pa) {
9c600a84 1617 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1618 }
c9b8f6b6 1619 if (has_msr_tsc_aux) {
9c600a84 1620 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1621 }
f28558d3 1622 if (has_msr_tsc_adjust) {
9c600a84 1623 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1624 }
21e87c46 1625 if (has_msr_misc_enable) {
9c600a84 1626 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1627 env->msr_ia32_misc_enable);
1628 }
fc12d72e 1629 if (has_msr_smbase) {
9c600a84 1630 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1631 }
439d19f2 1632 if (has_msr_bndcfgs) {
9c600a84 1633 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1634 }
18cd2c17 1635 if (has_msr_xss) {
9c600a84 1636 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1637 }
05330448 1638#ifdef TARGET_X86_64
25d2e361 1639 if (lm_capable_kernel) {
9c600a84
EH		 1640 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1641 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1642 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1643 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1644 }
05330448 1645#endif
ff5c186b 1646 /*
0d894367
PB		 1647 * The following MSRs have side effects on the guest or are too heavy
1648 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1649 */
1650 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1651 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1652 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1653 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1654 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1655 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1656 }
55c911a5 1657 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1658 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1659 }
55c911a5 1660 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1661 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1662 }
0b368a10
JD		 1663 if (has_architectural_pmu_version > 0) {
1664 if (has_architectural_pmu_version > 1) {
1665 /* Stop the counter. */
1666 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1667 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1668 }
0d894367
PB		 1669
1670 /* Set the counter values. */
0b368a10 1671 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 1672 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1673 env->msr_fixed_counters[i]);
1674 }
0b368a10 1675 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 1676 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1677 env->msr_gp_counters[i]);
9c600a84 1678 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1679 env->msr_gp_evtsel[i]);
1680 }
0b368a10
JD		 1681 if (has_architectural_pmu_version > 1) {
1682 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1683 env->msr_global_status);
1684 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1685 env->msr_global_ovf_ctrl);
1686
1687 /* Now start the PMU. */
1688 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1689 env->msr_fixed_ctr_ctrl);
1690 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1691 env->msr_global_ctrl);
1692 }
0d894367 1693 }
da1cc323
EY		 1694 /*
1695 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1696 * only sync them to KVM on the first cpu
1697 */
1698 if (current_cpu == first_cpu) {
1699 if (has_msr_hv_hypercall) {
1700 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1701 env->msr_hv_guest_os_id);
1702 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1703 env->msr_hv_hypercall);
1704 }
1705 if (cpu->hyperv_time) {
1706 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1707 env->msr_hv_tsc);
1708 }
eab70139 1709 }
2d5aa872 1710 if (cpu->hyperv_vapic) {
9c600a84 1711 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1712 env->msr_hv_vapic);
eab70139 1713 }
f2a53c9e
AS		 1714 if (has_msr_hv_crash) {
1715 int j;
1716
5e953812 1717 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 1718 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1719 env->msr_hv_crash_params[j]);
1720
5e953812 1721 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 1722 }
46eb8f98 1723 if (has_msr_hv_runtime) {
9c600a84 1724 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1725 }
866eea9a
AS		 1726 if (cpu->hyperv_synic) {
1727 int j;
1728
09df29b6
RK		 1729 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1730
9c600a84 1731 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1732 env->msr_hv_synic_control);
9c600a84 1733 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1734 env->msr_hv_synic_evt_page);
9c600a84 1735 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1736 env->msr_hv_synic_msg_page);
1737
1738 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1739 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1740 env->msr_hv_synic_sint[j]);
1741 }
1742 }
ff99aa64
AS		 1743 if (has_msr_hv_stimer) {
1744 int j;
1745
1746 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1747 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1748 env->msr_hv_stimer_config[j]);
1749 }
1750
1751 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1752 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1753 env->msr_hv_stimer_count[j]);
1754 }
1755 }
1eabfce6 1756 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1757 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1758
9c600a84
EH		 1759 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1760 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1761 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1762 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1763 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1764 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1765 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1766 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1767 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1768 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1769 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1770 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1771 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1772 /* The CPU GPs if we write to a bit above the physical limit of
1773 * the host CPU (and KVM emulates that)
1774 */
1775 uint64_t mask = env->mtrr_var[i].mask;
1776 mask &= phys_mask;
1777
9c600a84
EH		 1778 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1779 env->mtrr_var[i].base);
112dad69 1780 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1781 }
1782 }
6bdf863d
JK		 1783
1784 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1785 * kvm_put_msr_feature_control. */
ea643051 1786 }
57780495 1787 if (env->mcg_cap) {
d8da8574 1788 int i;
b9bec74b 1789
9c600a84
EH		 1790 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1791 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1792 if (has_msr_mcg_ext_ctl) {
1793 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1794 }
c34d440a 1795 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1796 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1797 }
1798 }
1a03675d 1799
d71b62a1 1800 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1801 if (ret < 0) {
1802 return ret;
1803 }
05330448 1804
c70b11d1
EH		 1805 if (ret < cpu->kvm_msr_buf->nmsrs) {
1806 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1807 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1808 (uint32_t)e->index, (uint64_t)e->data);
1809 }
1810
9c600a84 1811 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1812 return 0;
05330448
AL		 1813}
1814
1815
1bc22652 1816static int kvm_get_fpu(X86CPU *cpu)
05330448 1817{
1bc22652 1818 CPUX86State *env = &cpu->env;
05330448
AL		 1819 struct kvm_fpu fpu;
1820 int i, ret;
1821
1bc22652 1822 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1823 if (ret < 0) {
05330448 1824 return ret;
b9bec74b 1825 }
05330448
AL		 1826
1827 env->fpstt = (fpu.fsw >> 11) & 7;
1828 env->fpus = fpu.fsw;
1829 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1830 env->fpop = fpu.last_opcode;
1831 env->fpip = fpu.last_ip;
1832 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1833 for (i = 0; i < 8; ++i) {
1834 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1835 }
05330448 1836 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1837 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1838 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1839 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1840 }
05330448
AL		 1841 env->mxcsr = fpu.mxcsr;
1842
1843 return 0;
1844}
1845
1bc22652 1846static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1847{
1bc22652 1848 CPUX86State *env = &cpu->env;
86cd2ea0 1849 X86XSaveArea *xsave = env->kvm_xsave_buf;
86a57621 1850 int ret;
f1665b21 1851
28143b40 1852 if (!has_xsave) {
1bc22652 1853 return kvm_get_fpu(cpu);
b9bec74b 1854 }
f1665b21 1855
1bc22652 1856 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1857 if (ret < 0) {
f1665b21 1858 return ret;
0f53994f 1859 }
86a57621 1860 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 1861
f1665b21 1862 return 0;
f1665b21
SY		 1863}
1864
1bc22652 1865static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1866{
1bc22652 1867 CPUX86State *env = &cpu->env;
f1665b21
SY		 1868 int i, ret;
1869 struct kvm_xcrs xcrs;
1870
28143b40 1871 if (!has_xcrs) {
f1665b21 1872 return 0;
b9bec74b 1873 }
f1665b21 1874
1bc22652 1875 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1876 if (ret < 0) {
f1665b21 1877 return ret;
b9bec74b 1878 }
f1665b21 1879
b9bec74b 1880 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1881 /* Only support xcr0 now */
0fd53fec
PB		 1882 if (xcrs.xcrs[i].xcr == 0) {
1883 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1884 break;
1885 }
b9bec74b 1886 }
f1665b21 1887 return 0;
f1665b21
SY		 1888}
1889
1bc22652 1890static int kvm_get_sregs(X86CPU *cpu)
05330448 1891{
1bc22652 1892 CPUX86State *env = &cpu->env;
05330448 1893 struct kvm_sregs sregs;
0e607a80 1894 int bit, i, ret;
05330448 1895
1bc22652 1896 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1897 if (ret < 0) {
05330448 1898 return ret;
b9bec74b 1899 }
05330448 1900
0e607a80
JK		 1901 /* There can only be one pending IRQ set in the bitmap at a time, so try
1902 to find it and save its number instead (-1 for none). */
1903 env->interrupt_injected = -1;
1904 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1905 if (sregs.interrupt_bitmap[i]) {
1906 bit = ctz64(sregs.interrupt_bitmap[i]);
1907 env->interrupt_injected = i * 64 + bit;
1908 break;
1909 }
1910 }
05330448
AL		 1911
1912 get_seg(&env->segs[R_CS], &sregs.cs);
1913 get_seg(&env->segs[R_DS], &sregs.ds);
1914 get_seg(&env->segs[R_ES], &sregs.es);
1915 get_seg(&env->segs[R_FS], &sregs.fs);
1916 get_seg(&env->segs[R_GS], &sregs.gs);
1917 get_seg(&env->segs[R_SS], &sregs.ss);
1918
1919 get_seg(&env->tr, &sregs.tr);
1920 get_seg(&env->ldt, &sregs.ldt);
1921
1922 env->idt.limit = sregs.idt.limit;
1923 env->idt.base = sregs.idt.base;
1924 env->gdt.limit = sregs.gdt.limit;
1925 env->gdt.base = sregs.gdt.base;
1926
1927 env->cr[0] = sregs.cr0;
1928 env->cr[2] = sregs.cr2;
1929 env->cr[3] = sregs.cr3;
1930 env->cr[4] = sregs.cr4;
1931
05330448 1932 env->efer = sregs.efer;
cce47516
JK		 1933
1934 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 1935 x86_update_hflags(env);
05330448
AL		 1936
1937 return 0;
1938}
1939
1bc22652 1940static int kvm_get_msrs(X86CPU *cpu)
05330448 1941{
1bc22652 1942 CPUX86State *env = &cpu->env;
d71b62a1 1943 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 1944 int ret, i;
fcc35e7c 1945 uint64_t mtrr_top_bits;
05330448 1946
d71b62a1
EH		 1947 kvm_msr_buf_reset(cpu);
1948
9c600a84
EH		 1949 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
1950 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
1951 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
1952 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 1953 if (has_msr_star) {
9c600a84 1954 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 1955 }
c3a3a7d3 1956 if (has_msr_hsave_pa) {
9c600a84 1957 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 1958 }
c9b8f6b6 1959 if (has_msr_tsc_aux) {
9c600a84 1960 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 1961 }
f28558d3 1962 if (has_msr_tsc_adjust) {
9c600a84 1963 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 1964 }
aa82ba54 1965 if (has_msr_tsc_deadline) {
9c600a84 1966 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 1967 }
21e87c46 1968 if (has_msr_misc_enable) {
9c600a84 1969 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 1970 }
fc12d72e 1971 if (has_msr_smbase) {
9c600a84 1972 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 1973 }
df67696e 1974 if (has_msr_feature_control) {
9c600a84 1975 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 1976 }
79e9ebeb 1977 if (has_msr_bndcfgs) {
9c600a84 1978 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 1979 }
18cd2c17 1980 if (has_msr_xss) {
9c600a84 1981 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17
WL		 1982 }
1983
b8cc45d6
GC		 1984
1985 if (!env->tsc_valid) {
9c600a84 1986 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 1987 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 1988 }
1989
05330448 1990#ifdef TARGET_X86_64
25d2e361 1991 if (lm_capable_kernel) {
9c600a84
EH		 1992 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
1993 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
1994 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
1995 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 1996 }
05330448 1997#endif
9c600a84
EH		 1998 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
1999 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2000 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2001 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2002 }
55c911a5 2003 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2004 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2005 }
55c911a5 2006 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2007 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2008 }
0b368a10
JD		 2009 if (has_architectural_pmu_version > 0) {
2010 if (has_architectural_pmu_version > 1) {
2011 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2012 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2013 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2014 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2015 }
2016 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2017 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2018 }
0b368a10 2019 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2020 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2021 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2022 }
2023 }
1a03675d 2024
57780495 2025 if (env->mcg_cap) {
9c600a84
EH		 2026 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2027 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2028 if (has_msr_mcg_ext_ctl) {
2029 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2030 }
b9bec74b 2031 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2032 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2033 }
57780495 2034 }
57780495 2035
1c90ef26 2036 if (has_msr_hv_hypercall) {
9c600a84
EH		 2037 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2038 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2039 }
2d5aa872 2040 if (cpu->hyperv_vapic) {
9c600a84 2041 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2042 }
3ddcd2ed 2043 if (cpu->hyperv_time) {
9c600a84 2044 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2045 }
f2a53c9e
AS		 2046 if (has_msr_hv_crash) {
2047 int j;
2048
5e953812 2049 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2050 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2051 }
2052 }
46eb8f98 2053 if (has_msr_hv_runtime) {
9c600a84 2054 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2055 }
866eea9a
AS		 2056 if (cpu->hyperv_synic) {
2057 uint32_t msr;
2058
9c600a84 2059 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2060 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2061 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2062 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2063 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2064 }
2065 }
ff99aa64
AS		 2066 if (has_msr_hv_stimer) {
2067 uint32_t msr;
2068
2069 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2070 msr++) {
9c600a84 2071 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2072 }
2073 }
1eabfce6 2074 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2075 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2076 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2077 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2078 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2079 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2080 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2081 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2082 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2083 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2084 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2085 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2086 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2087 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2088 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2089 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2090 }
2091 }
5ef68987 2092
d71b62a1 2093 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2094 if (ret < 0) {
05330448 2095 return ret;
b9bec74b 2096 }
05330448 2097
c70b11d1
EH		 2098 if (ret < cpu->kvm_msr_buf->nmsrs) {
2099 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2100 error_report("error: failed to get MSR 0x%" PRIx32,
2101 (uint32_t)e->index);
2102 }
2103
9c600a84 2104 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2105 /*
2106 * MTRR masks: Each mask consists of 5 parts
2107 * a 10..0: must be zero
2108 * b 11 : valid bit
2109 * c n-1.12: actual mask bits
2110 * d 51..n: reserved must be zero
2111 * e 63.52: reserved must be zero
2112 *
2113 * 'n' is the number of physical bits supported by the CPU and is
2114 * apparently always <= 52. We know our 'n' but don't know what
2115 * the destinations 'n' is; it might be smaller, in which case
2116 * it masks (c) on loading. It might be larger, in which case
2117 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2118 * we're migrating to.
2119 */
2120
2121 if (cpu->fill_mtrr_mask) {
2122 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2123 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2124 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2125 } else {
2126 mtrr_top_bits = 0;
2127 }
2128
05330448 2129 for (i = 0; i < ret; i++) {
0d894367
PB		 2130 uint32_t index = msrs[i].index;
2131 switch (index) {
05330448
AL		 2132 case MSR_IA32_SYSENTER_CS:
2133 env->sysenter_cs = msrs[i].data;
2134 break;
2135 case MSR_IA32_SYSENTER_ESP:
2136 env->sysenter_esp = msrs[i].data;
2137 break;
2138 case MSR_IA32_SYSENTER_EIP:
2139 env->sysenter_eip = msrs[i].data;
2140 break;
0c03266a
JK		 2141 case MSR_PAT:
2142 env->pat = msrs[i].data;
2143 break;
05330448
AL		 2144 case MSR_STAR:
2145 env->star = msrs[i].data;
2146 break;
2147#ifdef TARGET_X86_64
2148 case MSR_CSTAR:
2149 env->cstar = msrs[i].data;
2150 break;
2151 case MSR_KERNELGSBASE:
2152 env->kernelgsbase = msrs[i].data;
2153 break;
2154 case MSR_FMASK:
2155 env->fmask = msrs[i].data;
2156 break;
2157 case MSR_LSTAR:
2158 env->lstar = msrs[i].data;
2159 break;
2160#endif
2161 case MSR_IA32_TSC:
2162 env->tsc = msrs[i].data;
2163 break;
c9b8f6b6
AS		 2164 case MSR_TSC_AUX:
2165 env->tsc_aux = msrs[i].data;
2166 break;
f28558d3
WA		 2167 case MSR_TSC_ADJUST:
2168 env->tsc_adjust = msrs[i].data;
2169 break;
aa82ba54
LJ		 2170 case MSR_IA32_TSCDEADLINE:
2171 env->tsc_deadline = msrs[i].data;
2172 break;
aa851e36
MT		 2173 case MSR_VM_HSAVE_PA:
2174 env->vm_hsave = msrs[i].data;
2175 break;
1a03675d
GC		 2176 case MSR_KVM_SYSTEM_TIME:
2177 env->system_time_msr = msrs[i].data;
2178 break;
2179 case MSR_KVM_WALL_CLOCK:
2180 env->wall_clock_msr = msrs[i].data;
2181 break;
57780495
MT		 2182 case MSR_MCG_STATUS:
2183 env->mcg_status = msrs[i].data;
2184 break;
2185 case MSR_MCG_CTL:
2186 env->mcg_ctl = msrs[i].data;
2187 break;
87f8b626
AR		 2188 case MSR_MCG_EXT_CTL:
2189 env->mcg_ext_ctl = msrs[i].data;
2190 break;
21e87c46
AK		 2191 case MSR_IA32_MISC_ENABLE:
2192 env->msr_ia32_misc_enable = msrs[i].data;
2193 break;
fc12d72e
PB		 2194 case MSR_IA32_SMBASE:
2195 env->smbase = msrs[i].data;
2196 break;
0779caeb
ACL		 2197 case MSR_IA32_FEATURE_CONTROL:
2198 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2199 break;
79e9ebeb
LJ		 2200 case MSR_IA32_BNDCFGS:
2201 env->msr_bndcfgs = msrs[i].data;
2202 break;
18cd2c17
WL		 2203 case MSR_IA32_XSS:
2204 env->xss = msrs[i].data;
2205 break;
57780495 2206 default:
57780495
MT		 2207 if (msrs[i].index >= MSR_MC0_CTL &&
2208 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2209 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2210 }
d8da8574 2211 break;
f6584ee2
GN		 2212 case MSR_KVM_ASYNC_PF_EN:
2213 env->async_pf_en_msr = msrs[i].data;
2214 break;
bc9a839d
MT		 2215 case MSR_KVM_PV_EOI_EN:
2216 env->pv_eoi_en_msr = msrs[i].data;
2217 break;
917367aa
MT		 2218 case MSR_KVM_STEAL_TIME:
2219 env->steal_time_msr = msrs[i].data;
2220 break;
0d894367
PB		 2221 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2222 env->msr_fixed_ctr_ctrl = msrs[i].data;
2223 break;
2224 case MSR_CORE_PERF_GLOBAL_CTRL:
2225 env->msr_global_ctrl = msrs[i].data;
2226 break;
2227 case MSR_CORE_PERF_GLOBAL_STATUS:
2228 env->msr_global_status = msrs[i].data;
2229 break;
2230 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2231 env->msr_global_ovf_ctrl = msrs[i].data;
2232 break;
2233 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2234 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2235 break;
2236 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2237 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2238 break;
2239 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2240 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2241 break;
1c90ef26
VR		 2242 case HV_X64_MSR_HYPERCALL:
2243 env->msr_hv_hypercall = msrs[i].data;
2244 break;
2245 case HV_X64_MSR_GUEST_OS_ID:
2246 env->msr_hv_guest_os_id = msrs[i].data;
2247 break;
5ef68987
VR		 2248 case HV_X64_MSR_APIC_ASSIST_PAGE:
2249 env->msr_hv_vapic = msrs[i].data;
2250 break;
48a5f3bc
VR		 2251 case HV_X64_MSR_REFERENCE_TSC:
2252 env->msr_hv_tsc = msrs[i].data;
2253 break;
f2a53c9e
AS		 2254 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2255 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2256 break;
46eb8f98
AS		 2257 case HV_X64_MSR_VP_RUNTIME:
2258 env->msr_hv_runtime = msrs[i].data;
2259 break;
866eea9a
AS		 2260 case HV_X64_MSR_SCONTROL:
2261 env->msr_hv_synic_control = msrs[i].data;
2262 break;
866eea9a
AS		 2263 case HV_X64_MSR_SIEFP:
2264 env->msr_hv_synic_evt_page = msrs[i].data;
2265 break;
2266 case HV_X64_MSR_SIMP:
2267 env->msr_hv_synic_msg_page = msrs[i].data;
2268 break;
2269 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2270 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2271 break;
2272 case HV_X64_MSR_STIMER0_CONFIG:
2273 case HV_X64_MSR_STIMER1_CONFIG:
2274 case HV_X64_MSR_STIMER2_CONFIG:
2275 case HV_X64_MSR_STIMER3_CONFIG:
2276 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2277 msrs[i].data;
2278 break;
2279 case HV_X64_MSR_STIMER0_COUNT:
2280 case HV_X64_MSR_STIMER1_COUNT:
2281 case HV_X64_MSR_STIMER2_COUNT:
2282 case HV_X64_MSR_STIMER3_COUNT:
2283 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2284 msrs[i].data;
866eea9a 2285 break;
d1ae67f6
AW		 2286 case MSR_MTRRdefType:
2287 env->mtrr_deftype = msrs[i].data;
2288 break;
2289 case MSR_MTRRfix64K_00000:
2290 env->mtrr_fixed[0] = msrs[i].data;
2291 break;
2292 case MSR_MTRRfix16K_80000:
2293 env->mtrr_fixed[1] = msrs[i].data;
2294 break;
2295 case MSR_MTRRfix16K_A0000:
2296 env->mtrr_fixed[2] = msrs[i].data;
2297 break;
2298 case MSR_MTRRfix4K_C0000:
2299 env->mtrr_fixed[3] = msrs[i].data;
2300 break;
2301 case MSR_MTRRfix4K_C8000:
2302 env->mtrr_fixed[4] = msrs[i].data;
2303 break;
2304 case MSR_MTRRfix4K_D0000:
2305 env->mtrr_fixed[5] = msrs[i].data;
2306 break;
2307 case MSR_MTRRfix4K_D8000:
2308 env->mtrr_fixed[6] = msrs[i].data;
2309 break;
2310 case MSR_MTRRfix4K_E0000:
2311 env->mtrr_fixed[7] = msrs[i].data;
2312 break;
2313 case MSR_MTRRfix4K_E8000:
2314 env->mtrr_fixed[8] = msrs[i].data;
2315 break;
2316 case MSR_MTRRfix4K_F0000:
2317 env->mtrr_fixed[9] = msrs[i].data;
2318 break;
2319 case MSR_MTRRfix4K_F8000:
2320 env->mtrr_fixed[10] = msrs[i].data;
2321 break;
2322 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2323 if (index & 1) {
fcc35e7c
DDAG		 2324 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2325 mtrr_top_bits;
d1ae67f6
AW		 2326 } else {
2327 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2328 }
2329 break;
05330448
AL		 2330 }
2331 }
2332
2333 return 0;
2334}
2335
1bc22652 2336static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2337{
1bc22652 2338 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2339
1bc22652 2340 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2341}
2342
23d02d9b 2343static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2344{
259186a7 2345 CPUState *cs = CPU(cpu);
23d02d9b 2346 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2347 struct kvm_mp_state mp_state;
2348 int ret;
2349
259186a7 2350 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2351 if (ret < 0) {
2352 return ret;
2353 }
2354 env->mp_state = mp_state.mp_state;
c14750e8 2355 if (kvm_irqchip_in_kernel()) {
259186a7 2356 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2357 }
9bdbe550
HB		 2358 return 0;
2359}
2360
1bc22652 2361static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2362{
02e51483 2363 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2364 struct kvm_lapic_state kapic;
2365 int ret;
2366
3d4b2649 2367 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2368 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2369 if (ret < 0) {
2370 return ret;
2371 }
2372
2373 kvm_get_apic_state(apic, &kapic);
2374 }
2375 return 0;
2376}
2377
1bc22652 2378static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2379{
fc12d72e 2380 CPUState *cs = CPU(cpu);
1bc22652 2381 CPUX86State *env = &cpu->env;
076796f8 2382 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2383
2384 if (!kvm_has_vcpu_events()) {
2385 return 0;
2386 }
2387
31827373
JK		 2388 events.exception.injected = (env->exception_injected >= 0);
2389 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2390 events.exception.has_error_code = env->has_error_code;
2391 events.exception.error_code = env->error_code;
7e680753 2392 events.exception.pad = 0;
a0fb002c
JK		 2393
2394 events.interrupt.injected = (env->interrupt_injected >= 0);
2395 events.interrupt.nr = env->interrupt_injected;
2396 events.interrupt.soft = env->soft_interrupt;
2397
2398 events.nmi.injected = env->nmi_injected;
2399 events.nmi.pending = env->nmi_pending;
2400 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2401 events.nmi.pad = 0;
a0fb002c
JK		 2402
2403 events.sipi_vector = env->sipi_vector;
68c6efe0 2404 events.flags = 0;
a0fb002c 2405
fc12d72e
PB		 2406 if (has_msr_smbase) {
2407 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2408 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2409 if (kvm_irqchip_in_kernel()) {
2410 /* As soon as these are moved to the kernel, remove them
2411 * from cs->interrupt_request.
2412 */
2413 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2414 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2415 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2416 } else {
2417 /* Keep these in cs->interrupt_request. */
2418 events.smi.pending = 0;
2419 events.smi.latched_init = 0;
2420 }
fc3a1fd7
DDAG		 2421 /* Stop SMI delivery on old machine types to avoid a reboot
2422 * on an inward migration of an old VM.
2423 */
2424 if (!cpu->kvm_no_smi_migration) {
2425 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2426 }
fc12d72e
PB		 2427 }
2428
ea643051 2429 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2430 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2431 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2432 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2433 }
ea643051 2434 }
aee028b9 2435
1bc22652 2436 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2437}
2438
1bc22652 2439static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2440{
1bc22652 2441 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2442 struct kvm_vcpu_events events;
2443 int ret;
2444
2445 if (!kvm_has_vcpu_events()) {
2446 return 0;
2447 }
2448
fc12d72e 2449 memset(&events, 0, sizeof(events));
1bc22652 2450 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2451 if (ret < 0) {
2452 return ret;
2453 }
31827373 2454 env->exception_injected =
a0fb002c
JK		 2455 events.exception.injected ? events.exception.nr : -1;
2456 env->has_error_code = events.exception.has_error_code;
2457 env->error_code = events.exception.error_code;
2458
2459 env->interrupt_injected =
2460 events.interrupt.injected ? events.interrupt.nr : -1;
2461 env->soft_interrupt = events.interrupt.soft;
2462
2463 env->nmi_injected = events.nmi.injected;
2464 env->nmi_pending = events.nmi.pending;
2465 if (events.nmi.masked) {
2466 env->hflags2 |= HF2_NMI_MASK;
2467 } else {
2468 env->hflags2 &= ~HF2_NMI_MASK;
2469 }
2470
fc12d72e
PB		 2471 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2472 if (events.smi.smm) {
2473 env->hflags |= HF_SMM_MASK;
2474 } else {
2475 env->hflags &= ~HF_SMM_MASK;
2476 }
2477 if (events.smi.pending) {
2478 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2479 } else {
2480 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2481 }
2482 if (events.smi.smm_inside_nmi) {
2483 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2484 } else {
2485 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2486 }
2487 if (events.smi.latched_init) {
2488 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2489 } else {
2490 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2491 }
2492 }
2493
a0fb002c 2494 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2495
2496 return 0;
2497}
2498
1bc22652 2499static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2500{
ed2803da 2501 CPUState *cs = CPU(cpu);
1bc22652 2502 CPUX86State *env = &cpu->env;
b0b1d690 2503 int ret = 0;
b0b1d690
JK		 2504 unsigned long reinject_trap = 0;
2505
2506 if (!kvm_has_vcpu_events()) {
2507 if (env->exception_injected == 1) {
2508 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2509 } else if (env->exception_injected == 3) {
2510 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2511 }
2512 env->exception_injected = -1;
2513 }
2514
2515 /*
2516 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2517 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2518 * by updating the debug state once again if single-stepping is on.
2519 * Another reason to call kvm_update_guest_debug here is a pending debug
2520 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2521 * reinject them via SET_GUEST_DEBUG.
2522 */
2523 if (reinject_trap ||
ed2803da 2524 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2525 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2526 }
b0b1d690
JK		 2527 return ret;
2528}
2529
1bc22652 2530static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2531{
1bc22652 2532 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2533 struct kvm_debugregs dbgregs;
2534 int i;
2535
2536 if (!kvm_has_debugregs()) {
2537 return 0;
2538 }
2539
2540 for (i = 0; i < 4; i++) {
2541 dbgregs.db[i] = env->dr[i];
2542 }
2543 dbgregs.dr6 = env->dr[6];
2544 dbgregs.dr7 = env->dr[7];
2545 dbgregs.flags = 0;
2546
1bc22652 2547 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2548}
2549
1bc22652 2550static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2551{
1bc22652 2552 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2553 struct kvm_debugregs dbgregs;
2554 int i, ret;
2555
2556 if (!kvm_has_debugregs()) {
2557 return 0;
2558 }
2559
1bc22652 2560 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2561 if (ret < 0) {
b9bec74b 2562 return ret;
ff44f1a3
JK		 2563 }
2564 for (i = 0; i < 4; i++) {
2565 env->dr[i] = dbgregs.db[i];
2566 }
2567 env->dr[4] = env->dr[6] = dbgregs.dr6;
2568 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2569
2570 return 0;
2571}
2572
20d695a9 2573int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2574{
20d695a9 2575 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2576 int ret;
2577
2fa45344 2578 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2579
48e1a45c 2580 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2581 ret = kvm_put_msr_feature_control(x86_cpu);
2582 if (ret < 0) {
2583 return ret;
2584 }
2585 }
2586
36f96c4b
HZ		 2587 if (level == KVM_PUT_FULL_STATE) {
2588 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2589 * because TSC frequency mismatch shouldn't abort migration,
2590 * unless the user explicitly asked for a more strict TSC
2591 * setting (e.g. using an explicit "tsc-freq" option).
2592 */
2593 kvm_arch_set_tsc_khz(cpu);
2594 }
2595
1bc22652 2596 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2597 if (ret < 0) {
05330448 2598 return ret;
b9bec74b 2599 }
1bc22652 2600 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2601 if (ret < 0) {
f1665b21 2602 return ret;
b9bec74b 2603 }
1bc22652 2604 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2605 if (ret < 0) {
05330448 2606 return ret;
b9bec74b 2607 }
1bc22652 2608 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2609 if (ret < 0) {
05330448 2610 return ret;
b9bec74b 2611 }
ab443475 2612 /* must be before kvm_put_msrs */
1bc22652 2613 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2614 if (ret < 0) {
2615 return ret;
2616 }
1bc22652 2617 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2618 if (ret < 0) {
05330448 2619 return ret;
b9bec74b 2620 }
4fadfa00
PH		 2621 ret = kvm_put_vcpu_events(x86_cpu, level);
2622 if (ret < 0) {
2623 return ret;
2624 }
ea643051 2625 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2626 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2627 if (ret < 0) {
680c1c6f
JK		 2628 return ret;
2629 }
ea643051 2630 }
7477cd38
MT		 2631
2632 ret = kvm_put_tscdeadline_msr(x86_cpu);
2633 if (ret < 0) {
2634 return ret;
2635 }
1bc22652 2636 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2637 if (ret < 0) {
b0b1d690 2638 return ret;
b9bec74b 2639 }
b0b1d690 2640 /* must be last */
1bc22652 2641 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2642 if (ret < 0) {
ff44f1a3 2643 return ret;
b9bec74b 2644 }
05330448
AL		 2645 return 0;
2646}
2647
20d695a9 2648int kvm_arch_get_registers(CPUState *cs)
05330448 2649{
20d695a9 2650 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2651 int ret;
2652
20d695a9 2653 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2654
4fadfa00 2655 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2656 if (ret < 0) {
f4f1110e 2657 goto out;
b9bec74b 2658 }
4fadfa00
PH		 2659 /*
2660 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2661 * KVM_GET_REGS and KVM_GET_SREGS.
2662 */
2663 ret = kvm_get_mp_state(cpu);
b9bec74b 2664 if (ret < 0) {
f4f1110e 2665 goto out;
b9bec74b 2666 }
4fadfa00 2667 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2668 if (ret < 0) {
f4f1110e 2669 goto out;
b9bec74b 2670 }
4fadfa00 2671 ret = kvm_get_xsave(cpu);
b9bec74b 2672 if (ret < 0) {
f4f1110e 2673 goto out;
b9bec74b 2674 }
4fadfa00 2675 ret = kvm_get_xcrs(cpu);
b9bec74b 2676 if (ret < 0) {
f4f1110e 2677 goto out;
b9bec74b 2678 }
4fadfa00 2679 ret = kvm_get_sregs(cpu);
b9bec74b 2680 if (ret < 0) {
f4f1110e 2681 goto out;
b9bec74b 2682 }
4fadfa00 2683 ret = kvm_get_msrs(cpu);
680c1c6f 2684 if (ret < 0) {
f4f1110e 2685 goto out;
680c1c6f 2686 }
4fadfa00 2687 ret = kvm_get_apic(cpu);
b9bec74b 2688 if (ret < 0) {
f4f1110e 2689 goto out;
b9bec74b 2690 }
1bc22652 2691 ret = kvm_get_debugregs(cpu);
b9bec74b 2692 if (ret < 0) {
f4f1110e 2693 goto out;
b9bec74b 2694 }
f4f1110e
RH		 2695 ret = 0;
2696 out:
2697 cpu_sync_bndcs_hflags(&cpu->env);
2698 return ret;
05330448
AL		 2699}
2700
20d695a9 2701void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2702{
20d695a9
AF		 2703 X86CPU *x86_cpu = X86_CPU(cpu);
2704 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2705 int ret;
2706
276ce815 2707 /* Inject NMI */
fc12d72e
PB		 2708 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2709 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2710 qemu_mutex_lock_iothread();
2711 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2712 qemu_mutex_unlock_iothread();
2713 DPRINTF("injected NMI\n");
2714 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2715 if (ret < 0) {
2716 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2717 strerror(-ret));
2718 }
2719 }
2720 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2721 qemu_mutex_lock_iothread();
2722 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2723 qemu_mutex_unlock_iothread();
2724 DPRINTF("injected SMI\n");
2725 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2726 if (ret < 0) {
2727 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2728 strerror(-ret));
2729 }
ce377af3 2730 }
276ce815
LJ		 2731 }
2732
15eafc2e 2733 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2734 qemu_mutex_lock_iothread();
2735 }
2736
e0723c45
PB		 2737 /* Force the VCPU out of its inner loop to process any INIT requests
2738 * or (for userspace APIC, but it is cheap to combine the checks here)
2739 * pending TPR access reports.
2740 */
2741 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2742 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2743 !(env->hflags & HF_SMM_MASK)) {
2744 cpu->exit_request = 1;
2745 }
2746 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2747 cpu->exit_request = 1;
2748 }
e0723c45 2749 }
05330448 2750
15eafc2e 2751 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2752 /* Try to inject an interrupt if the guest can accept it */
2753 if (run->ready_for_interrupt_injection &&
259186a7 2754 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2755 (env->eflags & IF_MASK)) {
2756 int irq;
2757
259186a7 2758 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2759 irq = cpu_get_pic_interrupt(env);
2760 if (irq >= 0) {
2761 struct kvm_interrupt intr;
2762
2763 intr.irq = irq;
db1669bc 2764 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2765 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2766 if (ret < 0) {
2767 fprintf(stderr,
2768 "KVM: injection failed, interrupt lost (%s)\n",
2769 strerror(-ret));
2770 }
db1669bc
JK		 2771 }
2772 }
05330448 2773
db1669bc
JK		 2774 /* If we have an interrupt but the guest is not ready to receive an
2775 * interrupt, request an interrupt window exit. This will
2776 * cause a return to userspace as soon as the guest is ready to
2777 * receive interrupts. */
259186a7 2778 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2779 run->request_interrupt_window = 1;
2780 } else {
2781 run->request_interrupt_window = 0;
2782 }
2783
2784 DPRINTF("setting tpr\n");
02e51483 2785 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2786
2787 qemu_mutex_unlock_iothread();
db1669bc 2788 }
05330448
AL		 2789}
2790
4c663752 2791MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2792{
20d695a9
AF		 2793 X86CPU *x86_cpu = X86_CPU(cpu);
2794 CPUX86State *env = &x86_cpu->env;
2795
fc12d72e
PB		 2796 if (run->flags & KVM_RUN_X86_SMM) {
2797 env->hflags |= HF_SMM_MASK;
2798 } else {
f5c052b9 2799 env->hflags &= ~HF_SMM_MASK;
fc12d72e 2800 }
b9bec74b 2801 if (run->if_flag) {
05330448 2802 env->eflags |= IF_MASK;
b9bec74b 2803 } else {
05330448 2804 env->eflags &= ~IF_MASK;
b9bec74b 2805 }
4b8523ee
JK		 2806
2807 /* We need to protect the apic state against concurrent accesses from
2808 * different threads in case the userspace irqchip is used. */
2809 if (!kvm_irqchip_in_kernel()) {
2810 qemu_mutex_lock_iothread();
2811 }
02e51483
CF		 2812 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2813 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2814 if (!kvm_irqchip_in_kernel()) {
2815 qemu_mutex_unlock_iothread();
2816 }
f794aa4a 2817 return cpu_get_mem_attrs(env);
05330448
AL		 2818}
2819
20d695a9 2820int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2821{
20d695a9
AF		 2822 X86CPU *cpu = X86_CPU(cs);
2823 CPUX86State *env = &cpu->env;
232fc23b 2824
259186a7 2825 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2826 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2827 assert(env->mcg_cap);
2828
259186a7 2829 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2830
dd1750d7 2831 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2832
2833 if (env->exception_injected == EXCP08_DBLE) {
2834 /* this means triple fault */
cf83f140 2835 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 2836 cs->exit_request = 1;
ab443475
JK		 2837 return 0;
2838 }
2839 env->exception_injected = EXCP12_MCHK;
2840 env->has_error_code = 0;
2841
259186a7 2842 cs->halted = 0;
ab443475
JK		 2843 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2844 env->mp_state = KVM_MP_STATE_RUNNABLE;
2845 }
2846 }
2847
fc12d72e
PB		 2848 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2849 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2850 kvm_cpu_synchronize_state(cs);
2851 do_cpu_init(cpu);
2852 }
2853
db1669bc
JK		 2854 if (kvm_irqchip_in_kernel()) {
2855 return 0;
2856 }
2857
259186a7
AF		 2858 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2859 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2860 apic_poll_irq(cpu->apic_state);
5d62c43a 2861 }
259186a7 2862 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2863 (env->eflags & IF_MASK)) ||
259186a7
AF		 2864 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2865 cs->halted = 0;
6792a57b 2866 }
259186a7 2867 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2868 kvm_cpu_synchronize_state(cs);
232fc23b 2869 do_cpu_sipi(cpu);
0af691d7 2870 }
259186a7
AF		 2871 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2872 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2873 kvm_cpu_synchronize_state(cs);
02e51483 2874 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2875 env->tpr_access_type);
2876 }
0af691d7 2877
259186a7 2878 return cs->halted;
0af691d7
MT		 2879}
2880
839b5630 2881static int kvm_handle_halt(X86CPU *cpu)
05330448 2882{
259186a7 2883 CPUState *cs = CPU(cpu);
839b5630
AF		 2884 CPUX86State *env = &cpu->env;
2885
259186a7 2886 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2887 (env->eflags & IF_MASK)) &&
259186a7
AF		 2888 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2889 cs->halted = 1;
bb4ea393 2890 return EXCP_HLT;
05330448
AL		 2891 }
2892
bb4ea393 2893 return 0;
05330448
AL		 2894}
2895
f7575c96 2896static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 2897{
f7575c96
AF		 2898 CPUState *cs = CPU(cpu);
2899 struct kvm_run *run = cs->kvm_run;
d362e757 2900
02e51483 2901 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 2902 run->tpr_access.is_write ? TPR_ACCESS_WRITE
2903 : TPR_ACCESS_READ);
2904 return 1;
2905}
2906
f17ec444 2907int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 2908{
38972938 2909 static const uint8_t int3 = 0xcc;
64bf3f4e 2910
f17ec444
AF		 2911 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
2912 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 2913 return -EINVAL;
b9bec74b 2914 }
e22a25c9
AL		 2915 return 0;
2916}
2917
f17ec444 2918int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 2919{
2920 uint8_t int3;
2921
f17ec444
AF		 2922 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
2923 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 2924 return -EINVAL;
b9bec74b 2925 }
e22a25c9
AL		 2926 return 0;
2927}
2928
2929static struct {
2930 target_ulong addr;
2931 int len;
2932 int type;
2933} hw_breakpoint[4];
2934
2935static int nb_hw_breakpoint;
2936
2937static int find_hw_breakpoint(target_ulong addr, int len, int type)
2938{
2939 int n;
2940
b9bec74b 2941 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 2942 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 2943 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 2944 return n;
b9bec74b
JK		 2945 }
2946 }
e22a25c9
AL		 2947 return -1;
2948}
2949
2950int kvm_arch_insert_hw_breakpoint(target_ulong addr,
2951 target_ulong len, int type)
2952{
2953 switch (type) {
2954 case GDB_BREAKPOINT_HW:
2955 len = 1;
2956 break;
2957 case GDB_WATCHPOINT_WRITE:
2958 case GDB_WATCHPOINT_ACCESS:
2959 switch (len) {
2960 case 1:
2961 break;
2962 case 2:
2963 case 4:
2964 case 8:
b9bec74b 2965 if (addr & (len - 1)) {
e22a25c9 2966 return -EINVAL;
b9bec74b 2967 }
e22a25c9
AL		 2968 break;
2969 default:
2970 return -EINVAL;
2971 }
2972 break;
2973 default:
2974 return -ENOSYS;
2975 }
2976
b9bec74b 2977 if (nb_hw_breakpoint == 4) {
e22a25c9 2978 return -ENOBUFS;
b9bec74b
JK		 2979 }
2980 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 2981 return -EEXIST;
b9bec74b 2982 }
e22a25c9
AL		 2983 hw_breakpoint[nb_hw_breakpoint].addr = addr;
2984 hw_breakpoint[nb_hw_breakpoint].len = len;
2985 hw_breakpoint[nb_hw_breakpoint].type = type;
2986 nb_hw_breakpoint++;
2987
2988 return 0;
2989}
2990
2991int kvm_arch_remove_hw_breakpoint(target_ulong addr,
2992 target_ulong len, int type)
2993{
2994 int n;
2995
2996 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 2997 if (n < 0) {
e22a25c9 2998 return -ENOENT;
b9bec74b 2999 }
e22a25c9
AL		 3000 nb_hw_breakpoint--;
3001 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3002
3003 return 0;
3004}
3005
3006void kvm_arch_remove_all_hw_breakpoints(void)
3007{
3008 nb_hw_breakpoint = 0;
3009}
3010
3011static CPUWatchpoint hw_watchpoint;
3012
a60f24b5 3013static int kvm_handle_debug(X86CPU *cpu,
48405526 3014 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3015{
ed2803da 3016 CPUState *cs = CPU(cpu);
a60f24b5 3017 CPUX86State *env = &cpu->env;
f2574737 3018 int ret = 0;
e22a25c9
AL		 3019 int n;
3020
3021 if (arch_info->exception == 1) {
3022 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3023 if (cs->singlestep_enabled) {
f2574737 3024 ret = EXCP_DEBUG;
b9bec74b 3025 }
e22a25c9 3026 } else {
b9bec74b
JK		 3027 for (n = 0; n < 4; n++) {
3028 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3029 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3030 case 0x0:
f2574737 3031 ret = EXCP_DEBUG;
e22a25c9
AL		 3032 break;
3033 case 0x1:
f2574737 3034 ret = EXCP_DEBUG;
ff4700b0 3035 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3036 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3037 hw_watchpoint.flags = BP_MEM_WRITE;
3038 break;
3039 case 0x3:
f2574737 3040 ret = EXCP_DEBUG;
ff4700b0 3041 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3042 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3043 hw_watchpoint.flags = BP_MEM_ACCESS;
3044 break;
3045 }
b9bec74b
JK		 3046 }
3047 }
e22a25c9 3048 }
ff4700b0 3049 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3050 ret = EXCP_DEBUG;
b9bec74b 3051 }
f2574737 3052 if (ret == 0) {
ff4700b0 3053 cpu_synchronize_state(cs);
48405526 3054 assert(env->exception_injected == -1);
b0b1d690 3055
f2574737 3056 /* pass to guest */
48405526
BS		 3057 env->exception_injected = arch_info->exception;
3058 env->has_error_code = 0;
b0b1d690 3059 }
e22a25c9 3060
f2574737 3061 return ret;
e22a25c9
AL		 3062}
3063
20d695a9 3064void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3065{
3066 const uint8_t type_code[] = {
3067 [GDB_BREAKPOINT_HW] = 0x0,
3068 [GDB_WATCHPOINT_WRITE] = 0x1,
3069 [GDB_WATCHPOINT_ACCESS] = 0x3
3070 };
3071 const uint8_t len_code[] = {
3072 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3073 };
3074 int n;
3075
a60f24b5 3076 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3077 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3078 }
e22a25c9
AL		 3079 if (nb_hw_breakpoint > 0) {
3080 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3081 dbg->arch.debugreg[7] = 0x0600;
3082 for (n = 0; n < nb_hw_breakpoint; n++) {
3083 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3084 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3085 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3086 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3087 }
3088 }
3089}
4513d923 3090
2a4dac83
JK		 3091static bool host_supports_vmx(void)
3092{
3093 uint32_t ecx, unused;
3094
3095 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3096 return ecx & CPUID_EXT_VMX;
3097}
3098
3099#define VMX_INVALID_GUEST_STATE 0x80000021
3100
20d695a9 3101int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3102{
20d695a9 3103 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3104 uint64_t code;
3105 int ret;
3106
3107 switch (run->exit_reason) {
3108 case KVM_EXIT_HLT:
3109 DPRINTF("handle_hlt\n");
4b8523ee 3110 qemu_mutex_lock_iothread();
839b5630 3111 ret = kvm_handle_halt(cpu);
4b8523ee 3112 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3113 break;
3114 case KVM_EXIT_SET_TPR:
3115 ret = 0;
3116 break;
d362e757 3117 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3118 qemu_mutex_lock_iothread();
f7575c96 3119 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3120 qemu_mutex_unlock_iothread();
d362e757 3121 break;
2a4dac83
JK		 3122 case KVM_EXIT_FAIL_ENTRY:
3123 code = run->fail_entry.hardware_entry_failure_reason;
3124 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3125 code);
3126 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3127 fprintf(stderr,
12619721 3128 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3129 "unrestricted mode\n"
3130 "support, the failure can be most likely due to the guest "
3131 "entering an invalid\n"
3132 "state for Intel VT. For example, the guest maybe running "
3133 "in big real mode\n"
3134 "which is not supported on less recent Intel processors."
3135 "\n\n");
3136 }
3137 ret = -1;
3138 break;
3139 case KVM_EXIT_EXCEPTION:
3140 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3141 run->ex.exception, run->ex.error_code);
3142 ret = -1;
3143 break;
f2574737
JK		 3144 case KVM_EXIT_DEBUG:
3145 DPRINTF("kvm_exit_debug\n");
4b8523ee 3146 qemu_mutex_lock_iothread();
a60f24b5 3147 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3148 qemu_mutex_unlock_iothread();
f2574737 3149 break;
50efe82c
AS		 3150 case KVM_EXIT_HYPERV:
3151 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3152 break;
15eafc2e
PB		 3153 case KVM_EXIT_IOAPIC_EOI:
3154 ioapic_eoi_broadcast(run->eoi.vector);
3155 ret = 0;
3156 break;
2a4dac83
JK		 3157 default:
3158 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3159 ret = -1;
3160 break;
3161 }
3162
3163 return ret;
3164}
3165
20d695a9 3166bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3167{
20d695a9
AF		 3168 X86CPU *cpu = X86_CPU(cs);
3169 CPUX86State *env = &cpu->env;
3170
dd1750d7 3171 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3172 return !(env->cr[0] & CR0_PE_MASK) ||
3173 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3174}
84b058d7
JK		 3175
3176void kvm_arch_init_irq_routing(KVMState *s)
3177{
3178 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3179 /* If kernel can't do irq routing, interrupt source
3180 * override 0->2 cannot be set up as required by HPET.
3181 * So we have to disable it.
3182 */
3183 no_hpet = 1;
3184 }
cc7e0ddf 3185 /* We know at this point that we're using the in-kernel
614e41bc 3186 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3187 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3188 */
614e41bc 3189 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3190 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3191
3192 if (kvm_irqchip_is_split()) {
3193 int i;
3194
3195 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3196 MSI routes for signaling interrupts to the local apics. */
3197 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3198 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3199 error_report("Could not enable split IRQ mode.");
3200 exit(1);
3201 }
3202 }
3203 }
3204}
3205
3206int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3207{
3208 int ret;
3209 if (machine_kernel_irqchip_split(ms)) {
3210 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3211 if (ret) {
df3c286c 3212 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3213 strerror(-ret));
3214 exit(1);
3215 } else {
3216 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3217 kvm_split_irqchip = true;
3218 return 1;
3219 }
3220 } else {
3221 return 0;
3222 }
84b058d7 3223}
b139bd30
JK		 3224
3225/* Classic KVM device assignment interface. Will remain x86 only. */
3226int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3227 uint32_t flags, uint32_t *dev_id)
3228{
3229 struct kvm_assigned_pci_dev dev_data = {
3230 .segnr = dev_addr->domain,
3231 .busnr = dev_addr->bus,
3232 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3233 .flags = flags,
3234 };
3235 int ret;
3236
3237 dev_data.assigned_dev_id =
3238 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3239
3240 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3241 if (ret < 0) {
3242 return ret;
3243 }
3244
3245 *dev_id = dev_data.assigned_dev_id;
3246
3247 return 0;
3248}
3249
3250int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3251{
3252 struct kvm_assigned_pci_dev dev_data = {
3253 .assigned_dev_id = dev_id,
3254 };
3255
3256 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3257}
3258
3259static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3260 uint32_t irq_type, uint32_t guest_irq)
3261{
3262 struct kvm_assigned_irq assigned_irq = {
3263 .assigned_dev_id = dev_id,
3264 .guest_irq = guest_irq,
3265 .flags = irq_type,
3266 };
3267
3268 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3269 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3270 } else {
3271 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3272 }
3273}
3274
3275int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3276 uint32_t guest_irq)
3277{
3278 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3279 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3280
3281 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3282}
3283
3284int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3285{
3286 struct kvm_assigned_pci_dev dev_data = {
3287 .assigned_dev_id = dev_id,
3288 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3289 };
3290
3291 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3292}
3293
3294static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3295 uint32_t type)
3296{
3297 struct kvm_assigned_irq assigned_irq = {
3298 .assigned_dev_id = dev_id,
3299 .flags = type,
3300 };
3301
3302 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3303}
3304
3305int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3306{
3307 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3308 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3309}
3310
3311int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3312{
3313 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3314 KVM_DEV_IRQ_GUEST_MSI, virq);
3315}
3316
3317int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3318{
3319 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3320 KVM_DEV_IRQ_HOST_MSI);
3321}
3322
3323bool kvm_device_msix_supported(KVMState *s)
3324{
3325 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3326 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3327 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3328}
3329
3330int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3331 uint32_t nr_vectors)
3332{
3333 struct kvm_assigned_msix_nr msix_nr = {
3334 .assigned_dev_id = dev_id,
3335 .entry_nr = nr_vectors,
3336 };
3337
3338 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3339}
3340
3341int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3342 int virq)
3343{
3344 struct kvm_assigned_msix_entry msix_entry = {
3345 .assigned_dev_id = dev_id,
3346 .gsi = virq,
3347 .entry = vector,
3348 };
3349
3350 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3351}
3352
3353int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3354{
3355 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3356 KVM_DEV_IRQ_GUEST_MSIX, 0);
3357}
3358
3359int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3360{
3361 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3362 KVM_DEV_IRQ_HOST_MSIX);
3363}
9e03a040
FB		 3364
3365int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3366 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3367{
8b5ed7df
PX		 3368 X86IOMMUState *iommu = x86_iommu_get_default();
3369
3370 if (iommu) {
3371 int ret;
3372 MSIMessage src, dst;
3373 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3374
3375 src.address = route->u.msi.address_hi;
3376 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3377 src.address |= route->u.msi.address_lo;
3378 src.data = route->u.msi.data;
3379
3380 ret = class->int_remap(iommu, &src, &dst, dev ? \
3381 pci_requester_id(dev) : \
3382 X86_IOMMU_SID_INVALID);
3383 if (ret) {
3384 trace_kvm_x86_fixup_msi_error(route->gsi);
3385 return 1;
3386 }
3387
3388 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3389 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3390 route->u.msi.data = dst.data;
3391 }
3392
9e03a040
FB		 3393 return 0;
3394}
1850b6b7 3395
38d87493
PX		 3396typedef struct MSIRouteEntry MSIRouteEntry;
3397
3398struct MSIRouteEntry {
3399 PCIDevice *dev; /* Device pointer */
3400 int vector; /* MSI/MSIX vector index */
3401 int virq; /* Virtual IRQ index */
3402 QLIST_ENTRY(MSIRouteEntry) list;
3403};
3404
3405/* List of used GSI routes */
3406static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3407 QLIST_HEAD_INITIALIZER(msi_route_list);
3408
e1d4fb2d
PX		 3409static void kvm_update_msi_routes_all(void *private, bool global,
3410 uint32_t index, uint32_t mask)
3411{
3412 int cnt = 0;
3413 MSIRouteEntry *entry;
3414 MSIMessage msg;
fd563564
PX		 3415 PCIDevice *dev;
3416
e1d4fb2d
PX		 3417 /* TODO: explicit route update */
3418 QLIST_FOREACH(entry, &msi_route_list, list) {
3419 cnt++;
fd563564
PX		 3420 dev = entry->dev;
3421 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3422 continue;
3423 }
3424 msg = pci_get_msi_message(dev, entry->vector);
3425 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3426 }
3f1fea0f 3427 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3428 trace_kvm_x86_update_msi_routes(cnt);
3429}
3430
38d87493
PX		 3431int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3432 int vector, PCIDevice *dev)
3433{
e1d4fb2d 3434 static bool notify_list_inited = false;
38d87493
PX		 3435 MSIRouteEntry *entry;
3436
3437 if (!dev) {
3438 /* These are (possibly) IOAPIC routes only used for split
3439 * kernel irqchip mode, while what we are housekeeping are
3440 * PCI devices only. */
3441 return 0;
3442 }
3443
3444 entry = g_new0(MSIRouteEntry, 1);
3445 entry->dev = dev;
3446 entry->vector = vector;
3447 entry->virq = route->gsi;
3448 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3449
3450 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3451
3452 if (!notify_list_inited) {
3453 /* For the first time we do add route, add ourselves into
3454 * IOMMU's IEC notify list if needed. */
3455 X86IOMMUState *iommu = x86_iommu_get_default();
3456 if (iommu) {
3457 x86_iommu_iec_register_notifier(iommu,
3458 kvm_update_msi_routes_all,
3459 NULL);
3460 }
3461 notify_list_inited = true;
3462 }
38d87493
PX		 3463 return 0;
3464}
3465
3466int kvm_arch_release_virq_post(int virq)
3467{
3468 MSIRouteEntry *entry, *next;
3469 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3470 if (entry->virq == virq) {
3471 trace_kvm_x86_remove_msi_route(virq);
3472 QLIST_REMOVE(entry, list);
3473 break;
3474 }
3475 }
9e03a040
FB		 3476 return 0;
3477}
1850b6b7
EA		 3478
3479int kvm_arch_msi_data_to_gsi(uint32_t data)
3480{
3481 abort();
3482}
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