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KVM: VMX: support MSR_IA32_ARCH_CAPABILITIES as a feature MSR
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO
1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO
10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY
14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
474a5bb9 30#include "pmu.h"
e83d5887 31#include "hyperv.h"
313a3dc7 32
18068523 33#include <linux/clocksource.h>
4d5c5d0f 34#include <linux/interrupt.h>
313a3dc7
CO
35#include <linux/kvm.h>
36#include <linux/fs.h>
37#include <linux/vmalloc.h>
1767e931
PG
38#include <linux/export.h>
39#include <linux/moduleparam.h>
0de10343 40#include <linux/mman.h>
2bacc55c 41#include <linux/highmem.h>
19de40a8 42#include <linux/iommu.h>
62c476c7 43#include <linux/intel-iommu.h>
c8076604 44#include <linux/cpufreq.h>
18863bdd 45#include <linux/user-return-notifier.h>
a983fb23 46#include <linux/srcu.h>
5a0e3ad6 47#include <linux/slab.h>
ff9d07a0 48#include <linux/perf_event.h>
7bee342a 49#include <linux/uaccess.h>
af585b92 50#include <linux/hash.h>
a1b60c1c 51#include <linux/pci.h>
16e8d74d
MT
52#include <linux/timekeeper_internal.h>
53#include <linux/pvclock_gtod.h>
87276880
FW
54#include <linux/kvm_irqfd.h>
55#include <linux/irqbypass.h>
3905f9ad 56#include <linux/sched/stat.h>
d0ec49d4 57#include <linux/mem_encrypt.h>
3905f9ad 58
aec51dc4 59#include <trace/events/kvm.h>
2ed152af 60
24f1e32c 61#include <asm/debugreg.h>
d825ed0a 62#include <asm/msr.h>
a5f61300 63#include <asm/desc.h>
890ca9ae 64#include <asm/mce.h>
f89e32e0 65#include <linux/kernel_stat.h>
78f7f1e5 66#include <asm/fpu/internal.h> /* Ugh! */
1d5f066e 67#include <asm/pvclock.h>
217fc9cf 68#include <asm/div64.h>
efc64404 69#include <asm/irq_remapping.h>
043405e1 70
d1898b73
DH
71#define CREATE_TRACE_POINTS
72#include "trace.h"
73
313a3dc7 74#define MAX_IO_MSRS 256
890ca9ae 75#define KVM_MAX_MCE_BANKS 32
c45dcc71
AR
76u64 __read_mostly kvm_mce_cap_supported = MCG_CTL_P | MCG_SER_P;
77EXPORT_SYMBOL_GPL(kvm_mce_cap_supported);
890ca9ae 78
0f65dd70
AK
79#define emul_to_vcpu(ctxt) \
80 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
81
50a37eb4
JR
82/* EFER defaults:
83 * - enable syscall per default because its emulated by KVM
84 * - enable LME and LMA per default on 64 bit KVM
85 */
86#ifdef CONFIG_X86_64
1260edbe
LJ
87static
88u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 89#else
1260edbe 90static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 91#endif
313a3dc7 92
ba1389b7
AK
93#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
94#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 95
c519265f
RK
96#define KVM_X2APIC_API_VALID_FLAGS (KVM_X2APIC_API_USE_32BIT_IDS | \
97 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
37131313 98
cb142eb7 99static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 100static void process_nmi(struct kvm_vcpu *vcpu);
ee2cd4b7 101static void enter_smm(struct kvm_vcpu *vcpu);
6addfc42 102static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
674eea0f 103
893590c7 104struct kvm_x86_ops *kvm_x86_ops __read_mostly;
5fdbf976 105EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 106
893590c7 107static bool __read_mostly ignore_msrs = 0;
476bc001 108module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 109
fab0aa3b
EM
110static bool __read_mostly report_ignored_msrs = true;
111module_param(report_ignored_msrs, bool, S_IRUGO | S_IWUSR);
112
9ed96e87
MT
113unsigned int min_timer_period_us = 500;
114module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
115
630994b3
MT
116static bool __read_mostly kvmclock_periodic_sync = true;
117module_param(kvmclock_periodic_sync, bool, S_IRUGO);
118
893590c7 119bool __read_mostly kvm_has_tsc_control;
92a1f12d 120EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
893590c7 121u32 __read_mostly kvm_max_guest_tsc_khz;
92a1f12d 122EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
bc9b961b
HZ
123u8 __read_mostly kvm_tsc_scaling_ratio_frac_bits;
124EXPORT_SYMBOL_GPL(kvm_tsc_scaling_ratio_frac_bits);
125u64 __read_mostly kvm_max_tsc_scaling_ratio;
126EXPORT_SYMBOL_GPL(kvm_max_tsc_scaling_ratio);
64672c95
YJ
127u64 __read_mostly kvm_default_tsc_scaling_ratio;
128EXPORT_SYMBOL_GPL(kvm_default_tsc_scaling_ratio);
92a1f12d 129
cc578287 130/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
893590c7 131static u32 __read_mostly tsc_tolerance_ppm = 250;
cc578287
ZA
132module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
133
d0659d94 134/* lapic timer advance (tscdeadline mode only) in nanoseconds */
893590c7 135unsigned int __read_mostly lapic_timer_advance_ns = 0;
d0659d94
MT
136module_param(lapic_timer_advance_ns, uint, S_IRUGO | S_IWUSR);
137
52004014
FW
138static bool __read_mostly vector_hashing = true;
139module_param(vector_hashing, bool, S_IRUGO);
140
18863bdd
AK
141#define KVM_NR_SHARED_MSRS 16
142
143struct kvm_shared_msrs_global {
144 int nr;
2bf78fa7 145 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK
146};
147
148struct kvm_shared_msrs {
149 struct user_return_notifier urn;
150 bool registered;
2bf78fa7
SY
151 struct kvm_shared_msr_values {
152 u64 host;
153 u64 curr;
154 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK
155};
156
157static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 158static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 159
417bc304 160struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK
161 { "pf_fixed", VCPU_STAT(pf_fixed) },
162 { "pf_guest", VCPU_STAT(pf_guest) },
163 { "tlb_flush", VCPU_STAT(tlb_flush) },
164 { "invlpg", VCPU_STAT(invlpg) },
165 { "exits", VCPU_STAT(exits) },
166 { "io_exits", VCPU_STAT(io_exits) },
167 { "mmio_exits", VCPU_STAT(mmio_exits) },
168 { "signal_exits", VCPU_STAT(signal_exits) },
169 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 170 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7 171 { "halt_exits", VCPU_STAT(halt_exits) },
f7819512 172 { "halt_successful_poll", VCPU_STAT(halt_successful_poll) },
62bea5bf 173 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll) },
3491caf2 174 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid) },
ba1389b7 175 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 176 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK
177 { "request_irq", VCPU_STAT(request_irq_exits) },
178 { "irq_exits", VCPU_STAT(irq_exits) },
179 { "host_state_reload", VCPU_STAT(host_state_reload) },
180 { "efer_reload", VCPU_STAT(efer_reload) },
181 { "fpu_reload", VCPU_STAT(fpu_reload) },
182 { "insn_emulation", VCPU_STAT(insn_emulation) },
183 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 184 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 185 { "nmi_injections", VCPU_STAT(nmi_injections) },
0f1e261e 186 { "req_event", VCPU_STAT(req_event) },
f0ace387 187 { "l1d_flush", VCPU_STAT(l1d_flush) },
4cee5764
AK
188 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
189 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
190 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
191 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
192 { "mmu_flooded", VM_STAT(mmu_flooded) },
193 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 194 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 195 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 196 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 197 { "largepages", VM_STAT(lpages) },
f3414bc7
DM
198 { "max_mmu_page_hash_collisions",
199 VM_STAT(max_mmu_page_hash_collisions) },
417bc304
HB
200 { NULL }
201};
202
2acf923e
DC
203u64 __read_mostly host_xcr0;
204
b6785def 205static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 206
af585b92
GN
207static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
208{
209 int i;
210 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
211 vcpu->arch.apf.gfns[i] = ~0;
212}
213
18863bdd
AK
214static void kvm_on_user_return(struct user_return_notifier *urn)
215{
216 unsigned slot;
18863bdd
AK
217 struct kvm_shared_msrs *locals
218 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 219 struct kvm_shared_msr_values *values;
1650b4eb
IA
220 unsigned long flags;
221
222 /*
223 * Disabling irqs at this point since the following code could be
224 * interrupted and executed through kvm_arch_hardware_disable()
225 */
226 local_irq_save(flags);
227 if (locals->registered) {
228 locals->registered = false;
229 user_return_notifier_unregister(urn);
230 }
231 local_irq_restore(flags);
18863bdd 232 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY
233 values = &locals->values[slot];
234 if (values->host != values->curr) {
235 wrmsrl(shared_msrs_global.msrs[slot], values->host);
236 values->curr = values->host;
18863bdd
AK
237 }
238 }
18863bdd
AK
239}
240
2bf78fa7 241static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 242{
18863bdd 243 u64 value;
013f6a5d
MT
244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 246
2bf78fa7
SY
247 /* only read, and nobody should modify it at this time,
248 * so don't need lock */
249 if (slot >= shared_msrs_global.nr) {
250 printk(KERN_ERR "kvm: invalid MSR slot!");
251 return;
252 }
253 rdmsrl_safe(msr, &value);
254 smsr->values[slot].host = value;
255 smsr->values[slot].curr = value;
256}
257
258void kvm_define_shared_msr(unsigned slot, u32 msr)
259{
0123be42 260 BUG_ON(slot >= KVM_NR_SHARED_MSRS);
c847fe88 261 shared_msrs_global.msrs[slot] = msr;
18863bdd
AK
262 if (slot >= shared_msrs_global.nr)
263 shared_msrs_global.nr = slot + 1;
18863bdd
AK
264}
265EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
266
267static void kvm_shared_msr_cpu_online(void)
268{
269 unsigned i;
18863bdd
AK
270
271 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 272 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK
273}
274
8b3c3104 275int kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 276{
013f6a5d
MT
277 unsigned int cpu = smp_processor_id();
278 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
8b3c3104 279 int err;
18863bdd 280
2bf78fa7 281 if (((value ^ smsr->values[slot].curr) & mask) == 0)
8b3c3104 282 return 0;
2bf78fa7 283 smsr->values[slot].curr = value;
8b3c3104
AH
284 err = wrmsrl_safe(shared_msrs_global.msrs[slot], value);
285 if (err)
286 return 1;
287
18863bdd
AK
288 if (!smsr->registered) {
289 smsr->urn.on_user_return = kvm_on_user_return;
290 user_return_notifier_register(&smsr->urn);
291 smsr->registered = true;
292 }
8b3c3104 293 return 0;
18863bdd
AK
294}
295EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
296
13a34e06 297static void drop_user_return_notifiers(void)
3548bab5 298{
013f6a5d
MT
299 unsigned int cpu = smp_processor_id();
300 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK
301
302 if (smsr->registered)
303 kvm_on_user_return(&smsr->urn);
304}
305
6866b83e
CO
306u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
307{
8a5a87d9 308 return vcpu->arch.apic_base;
6866b83e
CO
309}
310EXPORT_SYMBOL_GPL(kvm_get_apic_base);
311
58cb628d
JK
312int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
313{
314 u64 old_state = vcpu->arch.apic_base &
315 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
316 u64 new_state = msr_info->data &
317 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
d6321d49
RK
318 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) | 0x2ff |
319 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
58cb628d 320
d3802286
JM
321 if ((msr_info->data & reserved_bits) || new_state == X2APIC_ENABLE)
322 return 1;
58cb628d 323 if (!msr_info->host_initiated &&
d3802286 324 ((new_state == MSR_IA32_APICBASE_ENABLE &&
58cb628d
JK
325 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
326 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
327 old_state == 0)))
328 return 1;
329
330 kvm_lapic_set_base(vcpu, msr_info->data);
331 return 0;
6866b83e
CO
332}
333EXPORT_SYMBOL_GPL(kvm_set_apic_base);
334
2605fc21 335asmlinkage __visible void kvm_spurious_fault(void)
e3ba45b8
GL
336{
337 /* Fault while not rebooting. We want the trace. */
338 BUG();
339}
340EXPORT_SYMBOL_GPL(kvm_spurious_fault);
341
3fd28fce
ED
342#define EXCPT_BENIGN 0
343#define EXCPT_CONTRIBUTORY 1
344#define EXCPT_PF 2
345
346static int exception_class(int vector)
347{
348 switch (vector) {
349 case PF_VECTOR:
350 return EXCPT_PF;
351 case DE_VECTOR:
352 case TS_VECTOR:
353 case NP_VECTOR:
354 case SS_VECTOR:
355 case GP_VECTOR:
356 return EXCPT_CONTRIBUTORY;
357 default:
358 break;
359 }
360 return EXCPT_BENIGN;
361}
362
d6e8c854
NA
363#define EXCPT_FAULT 0
364#define EXCPT_TRAP 1
365#define EXCPT_ABORT 2
366#define EXCPT_INTERRUPT 3
367
368static int exception_type(int vector)
369{
370 unsigned int mask;
371
372 if (WARN_ON(vector > 31 || vector == NMI_VECTOR))
373 return EXCPT_INTERRUPT;
374
375 mask = 1 << vector;
376
377 /* #DB is trap, as instruction watchpoints are handled elsewhere */
378 if (mask & ((1 << DB_VECTOR) | (1 << BP_VECTOR) | (1 << OF_VECTOR)))
379 return EXCPT_TRAP;
380
381 if (mask & ((1 << DF_VECTOR) | (1 << MC_VECTOR)))
382 return EXCPT_ABORT;
383
384 /* Reserved exceptions will result in fault */
385 return EXCPT_FAULT;
386}
387
3fd28fce 388static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR
389 unsigned nr, bool has_error, u32 error_code,
390 bool reinject)
3fd28fce
ED
391{
392 u32 prev_nr;
393 int class1, class2;
394
3842d135
AK
395 kvm_make_request(KVM_REQ_EVENT, vcpu);
396
664f8e26 397 if (!vcpu->arch.exception.pending && !vcpu->arch.exception.injected) {
3fd28fce 398 queue:
3ffb2468
NA
399 if (has_error && !is_protmode(vcpu))
400 has_error = false;
664f8e26
WL
401 if (reinject) {
402 /*
403 * On vmentry, vcpu->arch.exception.pending is only
404 * true if an event injection was blocked by
405 * nested_run_pending. In that case, however,
406 * vcpu_enter_guest requests an immediate exit,
407 * and the guest shouldn't proceed far enough to
408 * need reinjection.
409 */
410 WARN_ON_ONCE(vcpu->arch.exception.pending);
411 vcpu->arch.exception.injected = true;
412 } else {
413 vcpu->arch.exception.pending = true;
414 vcpu->arch.exception.injected = false;
415 }
3fd28fce
ED
416 vcpu->arch.exception.has_error_code = has_error;
417 vcpu->arch.exception.nr = nr;
418 vcpu->arch.exception.error_code = error_code;
419 return;
420 }
421
422 /* to check exception */
423 prev_nr = vcpu->arch.exception.nr;
424 if (prev_nr == DF_VECTOR) {
425 /* triple fault -> shutdown */
a8eeb04a 426 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED
427 return;
428 }
429 class1 = exception_class(prev_nr);
430 class2 = exception_class(nr);
431 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
432 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
664f8e26
WL
433 /*
434 * Generate double fault per SDM Table 5-5. Set
435 * exception.pending = true so that the double fault
436 * can trigger a nested vmexit.
437 */
3fd28fce 438 vcpu->arch.exception.pending = true;
664f8e26 439 vcpu->arch.exception.injected = false;
3fd28fce
ED
440 vcpu->arch.exception.has_error_code = true;
441 vcpu->arch.exception.nr = DF_VECTOR;
442 vcpu->arch.exception.error_code = 0;
443 } else
444 /* replace previous exception with a new one in a hope
445 that instruction re-execution will regenerate lost
446 exception */
447 goto queue;
448}
449
298101da
AK
450void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
451{
ce7ddec4 452 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK
453}
454EXPORT_SYMBOL_GPL(kvm_queue_exception);
455
ce7ddec4
JR
456void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
457{
458 kvm_multiple_exception(vcpu, nr, false, 0, true);
459}
460EXPORT_SYMBOL_GPL(kvm_requeue_exception);
461
6affcbed 462int kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 463{
db8fcefa
AP
464 if (err)
465 kvm_inject_gp(vcpu, 0);
466 else
6affcbed
KH
467 return kvm_skip_emulated_instruction(vcpu);
468
469 return 1;
db8fcefa
AP
470}
471EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 472
6389ee94 473void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK
474{
475 ++vcpu->stat.pf_guest;
adfe20fb
WL
476 vcpu->arch.exception.nested_apf =
477 is_guest_mode(vcpu) && fault->async_page_fault;
478 if (vcpu->arch.exception.nested_apf)
479 vcpu->arch.apf.nested_apf_token = fault->address;
480 else
481 vcpu->arch.cr2 = fault->address;
6389ee94 482 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 483}
27d6c865 484EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 485
ef54bcfe 486static bool kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 487{
6389ee94
AK
488 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
489 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 490 else
6389ee94 491 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
ef54bcfe
PB
492
493 return fault->nested_page_fault;
d4f8cf66
JR
494}
495
3419ffc8
SY
496void kvm_inject_nmi(struct kvm_vcpu *vcpu)
497{
7460fb4a
AK
498 atomic_inc(&vcpu->arch.nmi_queued);
499 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY
500}
501EXPORT_SYMBOL_GPL(kvm_inject_nmi);
502
298101da
AK
503void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
504{
ce7ddec4 505 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK
506}
507EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
508
ce7ddec4
JR
509void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
510{
511 kvm_multiple_exception(vcpu, nr, true, error_code, true);
512}
513EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
514
0a79b009
AK
515/*
516 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
517 * a #GP and return false.
518 */
519bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 520{
0a79b009
AK
521 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
522 return true;
523 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
524 return false;
298101da 525}
0a79b009 526EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 527
16f8a6f9
NA
528bool kvm_require_dr(struct kvm_vcpu *vcpu, int dr)
529{
530 if ((dr != 4 && dr != 5) || !kvm_read_cr4_bits(vcpu, X86_CR4_DE))
531 return true;
532
533 kvm_queue_exception(vcpu, UD_VECTOR);
534 return false;
535}
536EXPORT_SYMBOL_GPL(kvm_require_dr);
537
ec92fe44
JR
538/*
539 * This function will be used to read from the physical memory of the currently
54bf36aa 540 * running guest. The difference to kvm_vcpu_read_guest_page is that this function
ec92fe44
JR
541 * can read from guest physical or from the guest's guest physical memory.
542 */
543int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
544 gfn_t ngfn, void *data, int offset, int len,
545 u32 access)
546{
54987b7a 547 struct x86_exception exception;
ec92fe44
JR
548 gfn_t real_gfn;
549 gpa_t ngpa;
550
551 ngpa = gfn_to_gpa(ngfn);
54987b7a 552 real_gfn = mmu->translate_gpa(vcpu, ngpa, access, &exception);
ec92fe44
JR
553 if (real_gfn == UNMAPPED_GVA)
554 return -EFAULT;
555
556 real_gfn = gpa_to_gfn(real_gfn);
557
54bf36aa 558 return kvm_vcpu_read_guest_page(vcpu, real_gfn, data, offset, len);
ec92fe44
JR
559}
560EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
561
69b0049a 562static int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
3d06b8bf
JR
563 void *data, int offset, int len, u32 access)
564{
565 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
566 data, offset, len, access);
567}
568
a03490ed
CO
569/*
570 * Load the pae pdptrs. Return true is they are all valid.
571 */
ff03a073 572int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO
573{
574 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
575 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
576 int i;
577 int ret;
ff03a073 578 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 579
ff03a073
JR
580 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
581 offset * sizeof(u64), sizeof(pdpte),
582 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO
583 if (ret < 0) {
584 ret = 0;
585 goto out;
586 }
587 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
812f30b2 588 if ((pdpte[i] & PT_PRESENT_MASK) &&
a0a64f50
XG
589 (pdpte[i] &
590 vcpu->arch.mmu.guest_rsvd_check.rsvd_bits_mask[0][2])) {
a03490ed
CO
591 ret = 0;
592 goto out;
593 }
594 }
595 ret = 1;
596
ff03a073 597 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK
598 __set_bit(VCPU_EXREG_PDPTR,
599 (unsigned long *)&vcpu->arch.regs_avail);
600 __set_bit(VCPU_EXREG_PDPTR,
601 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 602out:
a03490ed
CO
603
604 return ret;
605}
cc4b6871 606EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 607
9ed38ffa 608bool pdptrs_changed(struct kvm_vcpu *vcpu)
d835dfec 609{
ff03a073 610 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 611 bool changed = true;
3d06b8bf
JR
612 int offset;
613 gfn_t gfn;
d835dfec
AK
614 int r;
615
616 if (is_long_mode(vcpu) || !is_pae(vcpu))
617 return false;
618
6de4f3ad
AK
619 if (!test_bit(VCPU_EXREG_PDPTR,
620 (unsigned long *)&vcpu->arch.regs_avail))
621 return true;
622
a512177e
PB
623 gfn = (kvm_read_cr3(vcpu) & 0xffffffe0ul) >> PAGE_SHIFT;
624 offset = (kvm_read_cr3(vcpu) & 0xffffffe0ul) & (PAGE_SIZE - 1);
3d06b8bf
JR
625 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
626 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK
627 if (r < 0)
628 goto out;
ff03a073 629 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 630out:
d835dfec
AK
631
632 return changed;
633}
9ed38ffa 634EXPORT_SYMBOL_GPL(pdptrs_changed);
d835dfec 635
49a9b07e 636int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 637{
aad82703 638 unsigned long old_cr0 = kvm_read_cr0(vcpu);
d81135a5 639 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP;
aad82703 640
f9a48e6a
AK
641 cr0 |= X86_CR0_ET;
642
ab344828 643#ifdef CONFIG_X86_64
0f12244f
GN
644 if (cr0 & 0xffffffff00000000UL)
645 return 1;
ab344828
GN
646#endif
647
648 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 649
0f12244f
GN
650 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
651 return 1;
a03490ed 652
0f12244f
GN
653 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
654 return 1;
a03490ed
CO
655
656 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
657#ifdef CONFIG_X86_64
f6801dff 658 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO
659 int cs_db, cs_l;
660
0f12244f
GN
661 if (!is_pae(vcpu))
662 return 1;
a03490ed 663 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN
664 if (cs_l)
665 return 1;
a03490ed
CO
666 } else
667#endif
ff03a073 668 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 669 kvm_read_cr3(vcpu)))
0f12244f 670 return 1;
a03490ed
CO
671 }
672
ad756a16
MJ
673 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
674 return 1;
675
a03490ed 676 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 677
d170c419 678 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 679 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ
680 kvm_async_pf_hash_reset(vcpu);
681 }
e5f3f027 682
aad82703
SY
683 if ((cr0 ^ old_cr0) & update_bits)
684 kvm_mmu_reset_context(vcpu);
b18d5431 685
879ae188
LE
686 if (((cr0 ^ old_cr0) & X86_CR0_CD) &&
687 kvm_arch_has_noncoherent_dma(vcpu->kvm) &&
688 !kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
b18d5431
XG
689 kvm_zap_gfn_range(vcpu->kvm, 0, ~0ULL);
690
0f12244f
GN
691 return 0;
692}
2d3ad1f4 693EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 694
2d3ad1f4 695void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 696{
49a9b07e 697 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 700
42bdf991
MT
701static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
702{
703 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
704 !vcpu->guest_xcr0_loaded) {
705 /* kvm_set_xcr() also depends on this */
706 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
707 vcpu->guest_xcr0_loaded = 1;
708 }
709}
710
711static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
712{
713 if (vcpu->guest_xcr0_loaded) {
714 if (vcpu->arch.xcr0 != host_xcr0)
715 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
716 vcpu->guest_xcr0_loaded = 0;
717 }
718}
719
69b0049a 720static int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
2acf923e 721{
56c103ec
LJ
722 u64 xcr0 = xcr;
723 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 724 u64 valid_bits;
2acf923e
DC
725
726 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
727 if (index != XCR_XFEATURE_ENABLED_MASK)
728 return 1;
d91cab78 729 if (!(xcr0 & XFEATURE_MASK_FP))
2acf923e 730 return 1;
d91cab78 731 if ((xcr0 & XFEATURE_MASK_YMM) && !(xcr0 & XFEATURE_MASK_SSE))
2acf923e 732 return 1;
46c34cb0
PB
733
734 /*
735 * Do not allow the guest to set bits that we do not support
736 * saving. However, xcr0 bit 0 is always set, even if the
737 * emulated CPU does not support XSAVE (see fx_init).
738 */
d91cab78 739 valid_bits = vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FP;
46c34cb0 740 if (xcr0 & ~valid_bits)
2acf923e 741 return 1;
46c34cb0 742
d91cab78
DH
743 if ((!(xcr0 & XFEATURE_MASK_BNDREGS)) !=
744 (!(xcr0 & XFEATURE_MASK_BNDCSR)))
390bd528
LJ
745 return 1;
746
d91cab78
DH
747 if (xcr0 & XFEATURE_MASK_AVX512) {
748 if (!(xcr0 & XFEATURE_MASK_YMM))
612263b3 749 return 1;
d91cab78 750 if ((xcr0 & XFEATURE_MASK_AVX512) != XFEATURE_MASK_AVX512)
612263b3
CP
751 return 1;
752 }
2acf923e 753 vcpu->arch.xcr0 = xcr0;
56c103ec 754
d91cab78 755 if ((xcr0 ^ old_xcr0) & XFEATURE_MASK_EXTEND)
56c103ec 756 kvm_update_cpuid(vcpu);
2acf923e
DC
757 return 0;
758}
759
760int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
761{
764bcbc5
Z
762 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
763 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC
764 kvm_inject_gp(vcpu, 0);
765 return 1;
766 }
767 return 0;
768}
769EXPORT_SYMBOL_GPL(kvm_set_xcr);
770
a83b29c6 771int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 772{
fc78f519 773 unsigned long old_cr4 = kvm_read_cr4(vcpu);
0be0226f 774 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE |
b9baba86 775 X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE;
0be0226f 776
0f12244f
GN
777 if (cr4 & CR4_RESERVED_BITS)
778 return 1;
a03490ed 779
d6321d49 780 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && (cr4 & X86_CR4_OSXSAVE))
2acf923e
DC
781 return 1;
782
d6321d49 783 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMEP) && (cr4 & X86_CR4_SMEP))
2acf923e
DC
784 return 1;
785
d6321d49 786 if (!guest_cpuid_has(vcpu, X86_FEATURE_SMAP) && (cr4 & X86_CR4_SMAP))
c68b734f
YW
787 return 1;
788
d6321d49 789 if (!guest_cpuid_has(vcpu, X86_FEATURE_FSGSBASE) && (cr4 & X86_CR4_FSGSBASE))
97ec8c06
FW
790 return 1;
791
d6321d49 792 if (!guest_cpuid_has(vcpu, X86_FEATURE_PKU) && (cr4 & X86_CR4_PKE))
74dc2b4f
YW
793 return 1;
794
fd8cb433 795 if (!guest_cpuid_has(vcpu, X86_FEATURE_LA57) && (cr4 & X86_CR4_LA57))
b9baba86
HH
796 return 1;
797
df9b1e03
PB
798 if (!guest_cpuid_has(vcpu, X86_FEATURE_UMIP) && (cr4 & X86_CR4_UMIP))
799 return 1;
800
a03490ed 801 if (is_long_mode(vcpu)) {
0f12244f
GN
802 if (!(cr4 & X86_CR4_PAE))
803 return 1;
a2edf57f
AK
804 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
805 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK
806 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
807 kvm_read_cr3(vcpu)))
0f12244f
GN
808 return 1;
809
ad756a16 810 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
d6321d49 811 if (!guest_cpuid_has(vcpu, X86_FEATURE_PCID))
ad756a16
MJ
812 return 1;
813
814 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
815 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
816 return 1;
817 }
818
5e1746d6 819 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 820 return 1;
a03490ed 821
ad756a16
MJ
822 if (((cr4 ^ old_cr4) & pdptr_bits) ||
823 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 824 kvm_mmu_reset_context(vcpu);
0f12244f 825
b9baba86 826 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 827 kvm_update_cpuid(vcpu);
2acf923e 828
0f12244f
GN
829 return 0;
830}
2d3ad1f4 831EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 832
2390218b 833int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 834{
ac146235 835#ifdef CONFIG_X86_64
9d88fca7 836 cr3 &= ~CR3_PCID_INVD;
ac146235 837#endif
9d88fca7 838
9f8fe504 839 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 840 kvm_mmu_sync_roots(vcpu);
77c3913b 841 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
0f12244f 842 return 0;
d835dfec
AK
843 }
844
d1cd3ce9
YZ
845 if (is_long_mode(vcpu) &&
846 (cr3 & rsvd_bits(cpuid_maxphyaddr(vcpu), 62)))
847 return 1;
848 else if (is_pae(vcpu) && is_paging(vcpu) &&
d9f89b88 849 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
346874c9 850 return 1;
a03490ed 851
0f12244f 852 vcpu->arch.cr3 = cr3;
aff48baa 853 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 854 kvm_mmu_new_cr3(vcpu);
0f12244f
GN
855 return 0;
856}
2d3ad1f4 857EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 858
eea1cff9 859int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 860{
0f12244f
GN
861 if (cr8 & CR8_RESERVED_BITS)
862 return 1;
35754c98 863 if (lapic_in_kernel(vcpu))
a03490ed
CO
864 kvm_lapic_set_tpr(vcpu, cr8);
865 else
ad312c7c 866 vcpu->arch.cr8 = cr8;
0f12244f
GN
867 return 0;
868}
2d3ad1f4 869EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 870
2d3ad1f4 871unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed 872{
35754c98 873 if (lapic_in_kernel(vcpu))
a03490ed
CO
874 return kvm_lapic_get_cr8(vcpu);
875 else
ad312c7c 876 return vcpu->arch.cr8;
a03490ed 877}
2d3ad1f4 878EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 879
ae561ede
NA
880static void kvm_update_dr0123(struct kvm_vcpu *vcpu)
881{
882 int i;
883
884 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
885 for (i = 0; i < KVM_NR_DB_REGS; i++)
886 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
887 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_RELOAD;
888 }
889}
890
73aaf249
JK
891static void kvm_update_dr6(struct kvm_vcpu *vcpu)
892{
893 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
894 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
895}
896
c8639010
JK
897static void kvm_update_dr7(struct kvm_vcpu *vcpu)
898{
899 unsigned long dr7;
900
901 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
902 dr7 = vcpu->arch.guest_debug_dr7;
903 else
904 dr7 = vcpu->arch.dr7;
905 kvm_x86_ops->set_dr7(vcpu, dr7);
360b948d
PB
906 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_BP_ENABLED;
907 if (dr7 & DR7_BP_EN_MASK)
908 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_BP_ENABLED;
c8639010
JK
909}
910
6f43ed01
NA
911static u64 kvm_dr6_fixed(struct kvm_vcpu *vcpu)
912{
913 u64 fixed = DR6_FIXED_1;
914
d6321d49 915 if (!guest_cpuid_has(vcpu, X86_FEATURE_RTM))
6f43ed01
NA
916 fixed |= DR6_RTM;
917 return fixed;
918}
919
338dbc97 920static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN
921{
922 switch (dr) {
923 case 0 ... 3:
924 vcpu->arch.db[dr] = val;
925 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
926 vcpu->arch.eff_db[dr] = val;
927 break;
928 case 4:
020df079
GN
929 /* fall through */
930 case 6:
338dbc97
GN
931 if (val & 0xffffffff00000000ULL)
932 return -1; /* #GP */
6f43ed01 933 vcpu->arch.dr6 = (val & DR6_VOLATILE) | kvm_dr6_fixed(vcpu);
73aaf249 934 kvm_update_dr6(vcpu);
020df079
GN
935 break;
936 case 5:
020df079
GN
937 /* fall through */
938 default: /* 7 */
338dbc97
GN
939 if (val & 0xffffffff00000000ULL)
940 return -1; /* #GP */
020df079 941 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 942 kvm_update_dr7(vcpu);
020df079
GN
943 break;
944 }
945
946 return 0;
947}
338dbc97
GN
948
949int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
950{
16f8a6f9 951 if (__kvm_set_dr(vcpu, dr, val)) {
338dbc97 952 kvm_inject_gp(vcpu, 0);
16f8a6f9
NA
953 return 1;
954 }
955 return 0;
338dbc97 956}
020df079
GN
957EXPORT_SYMBOL_GPL(kvm_set_dr);
958
16f8a6f9 959int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN
960{
961 switch (dr) {
962 case 0 ... 3:
963 *val = vcpu->arch.db[dr];
964 break;
965 case 4:
020df079
GN
966 /* fall through */
967 case 6:
73aaf249
JK
968 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
969 *val = vcpu->arch.dr6;
970 else
971 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN
972 break;
973 case 5:
020df079
GN
974 /* fall through */
975 default: /* 7 */
976 *val = vcpu->arch.dr7;
977 break;
978 }
338dbc97
GN
979 return 0;
980}
020df079
GN
981EXPORT_SYMBOL_GPL(kvm_get_dr);
982
022cd0e8
AK
983bool kvm_rdpmc(struct kvm_vcpu *vcpu)
984{
985 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
986 u64 data;
987 int err;
988
c6702c9d 989 err = kvm_pmu_rdpmc(vcpu, ecx, &data);
022cd0e8
AK
990 if (err)
991 return err;
992 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
993 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
994 return err;
995}
996EXPORT_SYMBOL_GPL(kvm_rdpmc);
997
043405e1
CO
998/*
999 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
1000 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
1001 *
1002 * This list is modified at module load time to reflect the
e3267cbb 1003 * capabilities of the host cpu. This capabilities test skips MSRs that are
62ef68bb
PB
1004 * kvm-specific. Those are put in emulated_msrs; filtering of emulated_msrs
1005 * may depend on host virtualization features rather than host cpu features.
043405e1 1006 */
e3267cbb 1007
043405e1
CO
1008static u32 msrs_to_save[] = {
1009 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 1010 MSR_STAR,
043405e1
CO
1011#ifdef CONFIG_X86_64
1012 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
1013#endif
b3897a49 1014 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
9dbe6cf9 1015 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS, MSR_TSC_AUX,
74469996 1016 MSR_IA32_SPEC_CTRL, MSR_IA32_ARCH_CAPABILITIES
043405e1
CO
1017};
1018
1019static unsigned num_msrs_to_save;
1020
62ef68bb
PB
1021static u32 emulated_msrs[] = {
1022 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
1023 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
1024 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
1025 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
72c139ba 1026 HV_X64_MSR_TSC_FREQUENCY, HV_X64_MSR_APIC_FREQUENCY,
e7d9513b
AS
1027 HV_X64_MSR_CRASH_P0, HV_X64_MSR_CRASH_P1, HV_X64_MSR_CRASH_P2,
1028 HV_X64_MSR_CRASH_P3, HV_X64_MSR_CRASH_P4, HV_X64_MSR_CRASH_CTL,
e516cebb 1029 HV_X64_MSR_RESET,
11c4b1ca 1030 HV_X64_MSR_VP_INDEX,
9eec50b8 1031 HV_X64_MSR_VP_RUNTIME,
5c919412 1032 HV_X64_MSR_SCONTROL,
1f4b34f8 1033 HV_X64_MSR_STIMER0_CONFIG,
62ef68bb
PB
1034 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
1035 MSR_KVM_PV_EOI_EN,
1036
ba904635 1037 MSR_IA32_TSC_ADJUST,
a3e06bbe 1038 MSR_IA32_TSCDEADLINE,
043405e1 1039 MSR_IA32_MISC_ENABLE,
908e75f3
AK
1040 MSR_IA32_MCG_STATUS,
1041 MSR_IA32_MCG_CTL,
c45dcc71 1042 MSR_IA32_MCG_EXT_CTL,
64d60670 1043 MSR_IA32_SMBASE,
db2336a8
KH
1044 MSR_PLATFORM_INFO,
1045 MSR_MISC_FEATURES_ENABLES,
4d5c8a07 1046 MSR_AMD64_VIRT_SPEC_CTRL,
043405e1
CO
1047};
1048
62ef68bb
PB
1049static unsigned num_emulated_msrs;
1050
ab1bebf8
TL
1051/*
1052 * List of msr numbers which are used to expose MSR-based features that
1053 * can be used by a hypervisor to validate requested CPU features.
1054 */
1055static u32 msr_based_features[] = {
47ae8501 1056 MSR_IA32_ARCH_CAPABILITIES,
ab1bebf8
TL
1057};
1058
1059static unsigned int num_msr_based_features;
1060
08215b9d
WL
1061static int kvm_get_msr_feature(struct kvm_msr_entry *msr)
1062{
1063 switch (msr->index) {
47ae8501
PB
1064 case MSR_IA32_ARCH_CAPABILITIES:
1065 rdmsrl_safe(msr->index, &msr->data);
1066 break;
08215b9d
WL
1067 default:
1068 if (kvm_x86_ops->get_msr_feature(msr))
1069 return 1;
1070 }
1071 return 0;
1072}
1073
ab1bebf8
TL
1074static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1075{
1076 struct kvm_msr_entry msr;
08215b9d 1077 int r;
ab1bebf8
TL
1078
1079 msr.index = index;
08215b9d
WL
1080 r = kvm_get_msr_feature(&msr);
1081 if (r)
1082 return r;
ab1bebf8
TL
1083
1084 *data = msr.data;
1085
1086 return 0;
1087}
1088
384bb783 1089bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 1090{
b69e8cae 1091 if (efer & efer_reserved_bits)
384bb783 1092 return false;
15c4a640 1093
1b4d56b8 1094 if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT))
384bb783 1095 return false;
1b2fd70c 1096
1b4d56b8 1097 if (efer & EFER_SVME && !guest_cpuid_has(vcpu, X86_FEATURE_SVM))
384bb783 1098 return false;
d8017474 1099
384bb783
JK
1100 return true;
1101}
1102EXPORT_SYMBOL_GPL(kvm_valid_efer);
1103
1104static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
1105{
1106 u64 old_efer = vcpu->arch.efer;
1107
1108 if (!kvm_valid_efer(vcpu, efer))
1109 return 1;
1110
1111 if (is_paging(vcpu)
1112 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
1113 return 1;
1114
15c4a640 1115 efer &= ~EFER_LMA;
f6801dff 1116 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 1117
a3d204e2
SY
1118 kvm_x86_ops->set_efer(vcpu, efer);
1119
aad82703
SY
1120 /* Update reserved bits */
1121 if ((efer ^ old_efer) & EFER_NX)
1122 kvm_mmu_reset_context(vcpu);
1123
b69e8cae 1124 return 0;
15c4a640
CO
1125}
1126
f2b4b7dd
JR
1127void kvm_enable_efer_bits(u64 mask)
1128{
1129 efer_reserved_bits &= ~mask;
1130}
1131EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
1132
15c4a640
CO
1133/*
1134 * Writes msr value into into the appropriate "register".
1135 * Returns 0 on success, non-0 otherwise.
1136 * Assumes vcpu_load() was already called.
1137 */
8fe8ab46 1138int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 1139{
854e8bb1
NA
1140 switch (msr->index) {
1141 case MSR_FS_BASE:
1142 case MSR_GS_BASE:
1143 case MSR_KERNEL_GS_BASE:
1144 case MSR_CSTAR:
1145 case MSR_LSTAR:
fd8cb433 1146 if (is_noncanonical_address(msr->data, vcpu))
854e8bb1
NA
1147 return 1;
1148 break;
1149 case MSR_IA32_SYSENTER_EIP:
1150 case MSR_IA32_SYSENTER_ESP:
1151 /*
1152 * IA32_SYSENTER_ESP and IA32_SYSENTER_EIP cause #GP if
1153 * non-canonical address is written on Intel but not on
1154 * AMD (which ignores the top 32-bits, because it does
1155 * not implement 64-bit SYSENTER).
1156 *
1157 * 64-bit code should hence be able to write a non-canonical
1158 * value on AMD. Making the address canonical ensures that
1159 * vmentry does not fail on Intel after writing a non-canonical
1160 * value, and that something deterministic happens if the guest
1161 * invokes 64-bit SYSENTER.
1162 */
fd8cb433 1163 msr->data = get_canonical(msr->data, vcpu_virt_addr_bits(vcpu));
854e8bb1 1164 }
8fe8ab46 1165 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640 1166}
854e8bb1 1167EXPORT_SYMBOL_GPL(kvm_set_msr);
15c4a640 1168
313a3dc7
CO
1169/*
1170 * Adapt set_msr() to msr_io()'s calling convention
1171 */
609e36d3
PB
1172static int do_get_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1173{
1174 struct msr_data msr;
1175 int r;
1176
1177 msr.index = index;
1178 msr.host_initiated = true;
1179 r = kvm_get_msr(vcpu, &msr);
1180 if (r)
1181 return r;
1182
1183 *data = msr.data;
1184 return 0;
1185}
1186
313a3dc7
CO
1187static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
1188{
8fe8ab46
WA
1189 struct msr_data msr;
1190
1191 msr.data = *data;
1192 msr.index = index;
1193 msr.host_initiated = true;
1194 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO
1195}
1196
16e8d74d
MT
1197#ifdef CONFIG_X86_64
1198struct pvclock_gtod_data {
1199 seqcount_t seq;
1200
1201 struct { /* extract of a clocksource struct */
1202 int vclock_mode;
a5a1d1c2
TG
1203 u64 cycle_last;
1204 u64 mask;
16e8d74d
MT
1205 u32 mult;
1206 u32 shift;
1207 } clock;
1208
cbcf2dd3
TG
1209 u64 boot_ns;
1210 u64 nsec_base;
55dd00a7 1211 u64 wall_time_sec;
16e8d74d
MT
1212};
1213
1214static struct pvclock_gtod_data pvclock_gtod_data;
1215
1216static void update_pvclock_gtod(struct timekeeper *tk)
1217{
1218 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
cbcf2dd3
TG
1219 u64 boot_ns;
1220
876e7881 1221 boot_ns = ktime_to_ns(ktime_add(tk->tkr_mono.base, tk->offs_boot));
16e8d74d
MT
1222
1223 write_seqcount_begin(&vdata->seq);
1224
1225 /* copy pvclock gtod data */
876e7881
PZ
1226 vdata->clock.vclock_mode = tk->tkr_mono.clock->archdata.vclock_mode;
1227 vdata->clock.cycle_last = tk->tkr_mono.cycle_last;
1228 vdata->clock.mask = tk->tkr_mono.mask;
1229 vdata->clock.mult = tk->tkr_mono.mult;
1230 vdata->clock.shift = tk->tkr_mono.shift;
16e8d74d 1231
cbcf2dd3 1232 vdata->boot_ns = boot_ns;
876e7881 1233 vdata->nsec_base = tk->tkr_mono.xtime_nsec;
16e8d74d 1234
55dd00a7
MT
1235 vdata->wall_time_sec = tk->xtime_sec;
1236
16e8d74d
MT
1237 write_seqcount_end(&vdata->seq);
1238}
1239#endif
1240
bab5bb39
NK
1241void kvm_set_pending_timer(struct kvm_vcpu *vcpu)
1242{
1243 /*
1244 * Note: KVM_REQ_PENDING_TIMER is implicitly checked in
1245 * vcpu_enter_guest. This function is only called from
1246 * the physical CPU that is running vcpu.
1247 */
1248 kvm_make_request(KVM_REQ_PENDING_TIMER, vcpu);
1249}
16e8d74d 1250
18068523
GOC
1251static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1252{
9ed3c444
AK
1253 int version;
1254 int r;
50d0a0f9 1255 struct pvclock_wall_clock wc;
87aeb54f 1256 struct timespec64 boot;
18068523
GOC
1257
1258 if (!wall_clock)
1259 return;
1260
9ed3c444
AK
1261 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1262 if (r)
1263 return;
1264
1265 if (version & 1)
1266 ++version; /* first time write, random junk */
1267
1268 ++version;
18068523 1269
1dab1345
NK
1270 if (kvm_write_guest(kvm, wall_clock, &version, sizeof(version)))
1271 return;
18068523 1272
50d0a0f9
GH
1273 /*
1274 * The guest calculates current wall clock time by adding
34c238a1 1275 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH
1276 * wall clock specified here. guest system time equals host
1277 * system time for us, thus we must fill in host boot time here.
1278 */
87aeb54f 1279 getboottime64(&boot);
50d0a0f9 1280
4b648665 1281 if (kvm->arch.kvmclock_offset) {
87aeb54f
AB
1282 struct timespec64 ts = ns_to_timespec64(kvm->arch.kvmclock_offset);
1283 boot = timespec64_sub(boot, ts);
4b648665 1284 }
87aeb54f 1285 wc.sec = (u32)boot.tv_sec; /* overflow in 2106 guest time */
50d0a0f9
GH
1286 wc.nsec = boot.tv_nsec;
1287 wc.version = version;
18068523
GOC
1288
1289 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1290
1291 version++;
1292 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC
1293}
1294
50d0a0f9
GH
1295static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1296{
b51012de
PB
1297 do_shl32_div32(dividend, divisor);
1298 return dividend;
50d0a0f9
GH
1299}
1300
3ae13faa 1301static void kvm_get_time_scale(uint64_t scaled_hz, uint64_t base_hz,
5f4e3f88 1302 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1303{
5f4e3f88 1304 uint64_t scaled64;
50d0a0f9
GH
1305 int32_t shift = 0;
1306 uint64_t tps64;
1307 uint32_t tps32;
1308
3ae13faa
PB
1309 tps64 = base_hz;
1310 scaled64 = scaled_hz;
50933623 1311 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH
1312 tps64 >>= 1;
1313 shift--;
1314 }
1315
1316 tps32 = (uint32_t)tps64;
50933623
JK
1317 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1318 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA
1319 scaled64 >>= 1;
1320 else
1321 tps32 <<= 1;
50d0a0f9
GH
1322 shift++;
1323 }
1324
5f4e3f88
ZA
1325 *pshift = shift;
1326 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1327
3ae13faa
PB
1328 pr_debug("%s: base_hz %llu => %llu, shift %d, mul %u\n",
1329 __func__, base_hz, scaled_hz, shift, *pmultiplier);
50d0a0f9
GH
1330}
1331
d828199e 1332#ifdef CONFIG_X86_64
16e8d74d 1333static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1334#endif
16e8d74d 1335
c8076604 1336static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
69b0049a 1337static unsigned long max_tsc_khz;
c8076604 1338
cc578287 1339static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1340{
cc578287
ZA
1341 u64 v = (u64)khz * (1000000 + ppm);
1342 do_div(v, 1000000);
1343 return v;
1e993611
JR
1344}
1345
381d585c
HZ
1346static int set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1347{
1348 u64 ratio;
1349
1350 /* Guest TSC same frequency as host TSC? */
1351 if (!scale) {
1352 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
1353 return 0;
1354 }
1355
1356 /* TSC scaling supported? */
1357 if (!kvm_has_tsc_control) {
1358 if (user_tsc_khz > tsc_khz) {
1359 vcpu->arch.tsc_catchup = 1;
1360 vcpu->arch.tsc_always_catchup = 1;
1361 return 0;
1362 } else {
1363 WARN(1, "user requested TSC rate below hardware speed\n");
1364 return -1;
1365 }
1366 }
1367
1368 /* TSC scaling required - calculate ratio */
1369 ratio = mul_u64_u32_div(1ULL << kvm_tsc_scaling_ratio_frac_bits,
1370 user_tsc_khz, tsc_khz);
1371
1372 if (ratio == 0 || ratio >= kvm_max_tsc_scaling_ratio) {
1373 WARN_ONCE(1, "Invalid TSC scaling ratio - virtual-tsc-khz=%u\n",
1374 user_tsc_khz);
1375 return -1;
1376 }
1377
1378 vcpu->arch.tsc_scaling_ratio = ratio;
1379 return 0;
1380}
1381
4941b8cb 1382static int kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
759379dd 1383{
cc578287
ZA
1384 u32 thresh_lo, thresh_hi;
1385 int use_scaling = 0;
217fc9cf 1386
03ba32ca 1387 /* tsc_khz can be zero if TSC calibration fails */
4941b8cb 1388 if (user_tsc_khz == 0) {
ad721883
HZ
1389 /* set tsc_scaling_ratio to a safe value */
1390 vcpu->arch.tsc_scaling_ratio = kvm_default_tsc_scaling_ratio;
381d585c 1391 return -1;
ad721883 1392 }
03ba32ca 1393
c285545f 1394 /* Compute a scale to convert nanoseconds in TSC cycles */
3ae13faa 1395 kvm_get_time_scale(user_tsc_khz * 1000LL, NSEC_PER_SEC,
cc578287
ZA
1396 &vcpu->arch.virtual_tsc_shift,
1397 &vcpu->arch.virtual_tsc_mult);
4941b8cb 1398 vcpu->arch.virtual_tsc_khz = user_tsc_khz;
cc578287
ZA
1399
1400 /*
1401 * Compute the variation in TSC rate which is acceptable
1402 * within the range of tolerance and decide if the
1403 * rate being applied is within that bounds of the hardware
1404 * rate. If so, no scaling or compensation need be done.
1405 */
1406 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1407 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
4941b8cb
PB
1408 if (user_tsc_khz < thresh_lo || user_tsc_khz > thresh_hi) {
1409 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", user_tsc_khz, thresh_lo, thresh_hi);
cc578287
ZA
1410 use_scaling = 1;
1411 }
4941b8cb 1412 return set_tsc_khz(vcpu, user_tsc_khz, use_scaling);
c285545f
ZA
1413}
1414
1415static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1416{
e26101b1 1417 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA
1418 vcpu->arch.virtual_tsc_mult,
1419 vcpu->arch.virtual_tsc_shift);
e26101b1 1420 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA
1421 return tsc;
1422}
1423
69b0049a 1424static void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
b48aa97e
MT
1425{
1426#ifdef CONFIG_X86_64
1427 bool vcpus_matched;
b48aa97e
MT
1428 struct kvm_arch *ka = &vcpu->kvm->arch;
1429 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1430
1431 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1432 atomic_read(&vcpu->kvm->online_vcpus));
1433
7f187922
MT
1434 /*
1435 * Once the masterclock is enabled, always perform request in
1436 * order to update it.
1437 *
1438 * In order to enable masterclock, the host clocksource must be TSC
1439 * and the vcpus need to have matched TSCs. When that happens,
1440 * perform request to enable masterclock.
1441 */
1442 if (ka->use_master_clock ||
1443 (gtod->clock.vclock_mode == VCLOCK_TSC && vcpus_matched))
b48aa97e
MT
1444 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1445
1446 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1447 atomic_read(&vcpu->kvm->online_vcpus),
1448 ka->use_master_clock, gtod->clock.vclock_mode);
1449#endif
1450}
1451
ba904635
WA
1452static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1453{
3e3f5026 1454 u64 curr_offset = vcpu->arch.tsc_offset;
ba904635
WA
1455 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1456}
1457
35181e86
HZ
1458/*
1459 * Multiply tsc by a fixed point number represented by ratio.
1460 *
1461 * The most significant 64-N bits (mult) of ratio represent the
1462 * integral part of the fixed point number; the remaining N bits
1463 * (frac) represent the fractional part, ie. ratio represents a fixed
1464 * point number (mult + frac * 2^(-N)).
1465 *
1466 * N equals to kvm_tsc_scaling_ratio_frac_bits.
1467 */
1468static inline u64 __scale_tsc(u64 ratio, u64 tsc)
1469{
1470 return mul_u64_u64_shr(tsc, ratio, kvm_tsc_scaling_ratio_frac_bits);
1471}
1472
1473u64 kvm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
1474{
1475 u64 _tsc = tsc;
1476 u64 ratio = vcpu->arch.tsc_scaling_ratio;
1477
1478 if (ratio != kvm_default_tsc_scaling_ratio)
1479 _tsc = __scale_tsc(ratio, tsc);
1480
1481 return _tsc;
1482}
1483EXPORT_SYMBOL_GPL(kvm_scale_tsc);
1484
07c1419a
HZ
1485static u64 kvm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1486{
1487 u64 tsc;
1488
1489 tsc = kvm_scale_tsc(vcpu, rdtsc());
1490
1491 return target_tsc - tsc;
1492}
1493
4ba76538
HZ
1494u64 kvm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1495{
ea26e4ec 1496 return vcpu->arch.tsc_offset + kvm_scale_tsc(vcpu, host_tsc);
4ba76538
HZ
1497}
1498EXPORT_SYMBOL_GPL(kvm_read_l1_tsc);
1499
a545ab6a
LC
1500static void kvm_vcpu_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1501{
1502 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1503 vcpu->arch.tsc_offset = offset;
1504}
1505
8fe8ab46 1506void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA
1507{
1508 struct kvm *kvm = vcpu->kvm;
f38e098f 1509 u64 offset, ns, elapsed;
99e3e30a 1510 unsigned long flags;
b48aa97e 1511 bool matched;
0d3da0d2 1512 bool already_matched;
8fe8ab46 1513 u64 data = msr->data;
c5e8ec8e 1514 bool synchronizing = false;
99e3e30a 1515
038f8c11 1516 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
07c1419a 1517 offset = kvm_compute_tsc_offset(vcpu, data);
108b249c 1518 ns = ktime_get_boot_ns();
f38e098f 1519 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1520
03ba32ca 1521 if (vcpu->arch.virtual_tsc_khz) {
bd8fab39
DP
1522 if (data == 0 && msr->host_initiated) {
1523 /*
1524 * detection of vcpu initialization -- need to sync
1525 * with other vCPUs. This particularly helps to keep
1526 * kvm_clock stable after CPU hotplug
1527 */
1528 synchronizing = true;
1529 } else {
1530 u64 tsc_exp = kvm->arch.last_tsc_write +
1531 nsec_to_cycles(vcpu, elapsed);
1532 u64 tsc_hz = vcpu->arch.virtual_tsc_khz * 1000LL;
1533 /*
1534 * Special case: TSC write with a small delta (1 second)
1535 * of virtual cycle time against real time is
1536 * interpreted as an attempt to synchronize the CPU.
1537 */
1538 synchronizing = data < tsc_exp + tsc_hz &&
1539 data + tsc_hz > tsc_exp;
1540 }
c5e8ec8e 1541 }
f38e098f
ZA
1542
1543 /*
5d3cb0f6
ZA
1544 * For a reliable TSC, we can match TSC offsets, and for an unstable
1545 * TSC, we add elapsed time in this computation. We could let the
1546 * compensation code attempt to catch up if we fall behind, but
1547 * it's better to try to match offsets from the beginning.
1548 */
c5e8ec8e 1549 if (synchronizing &&
5d3cb0f6 1550 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1551 if (!check_tsc_unstable()) {
e26101b1 1552 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA
1553 pr_debug("kvm: matched tsc offset for %llu\n", data);
1554 } else {
857e4099 1555 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6 1556 data += delta;
07c1419a 1557 offset = kvm_compute_tsc_offset(vcpu, data);
759379dd 1558 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1559 }
b48aa97e 1560 matched = true;
0d3da0d2 1561 already_matched = (vcpu->arch.this_tsc_generation == kvm->arch.cur_tsc_generation);
e26101b1
ZA
1562 } else {
1563 /*
1564 * We split periods of matched TSC writes into generations.
1565 * For each generation, we track the original measured
1566 * nanosecond time, offset, and write, so if TSCs are in
1567 * sync, we can match exact offset, and if not, we can match
4a969980 1568 * exact software computation in compute_guest_tsc()
e26101b1
ZA
1569 *
1570 * These values are tracked in kvm->arch.cur_xxx variables.
1571 */
1572 kvm->arch.cur_tsc_generation++;
1573 kvm->arch.cur_tsc_nsec = ns;
1574 kvm->arch.cur_tsc_write = data;
1575 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1576 matched = false;
0d3da0d2 1577 pr_debug("kvm: new tsc generation %llu, clock %llu\n",
e26101b1 1578 kvm->arch.cur_tsc_generation, data);
f38e098f 1579 }
e26101b1
ZA
1580
1581 /*
1582 * We also track th most recent recorded KHZ, write and time to
1583 * allow the matching interval to be extended at each write.
1584 */
f38e098f
ZA
1585 kvm->arch.last_tsc_nsec = ns;
1586 kvm->arch.last_tsc_write = data;
5d3cb0f6 1587 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1588
b183aa58 1589 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA
1590
1591 /* Keep track of which generation this VCPU has synchronized to */
1592 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1593 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1594 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1595
d6321d49 1596 if (!msr->host_initiated && guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST))
ba904635 1597 update_ia32_tsc_adjust_msr(vcpu, offset);
d6321d49 1598
a545ab6a 1599 kvm_vcpu_write_tsc_offset(vcpu, offset);
e26101b1 1600 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT
1601
1602 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
0d3da0d2 1603 if (!matched) {
b48aa97e 1604 kvm->arch.nr_vcpus_matched_tsc = 0;
0d3da0d2
TG
1605 } else if (!already_matched) {
1606 kvm->arch.nr_vcpus_matched_tsc++;
1607 }
b48aa97e
MT
1608
1609 kvm_track_tsc_matching(vcpu);
1610 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1611}
e26101b1 1612
99e3e30a
ZA
1613EXPORT_SYMBOL_GPL(kvm_write_tsc);
1614
58ea6767
HZ
1615static inline void adjust_tsc_offset_guest(struct kvm_vcpu *vcpu,
1616 s64 adjustment)
1617{
ea26e4ec 1618 kvm_vcpu_write_tsc_offset(vcpu, vcpu->arch.tsc_offset + adjustment);
58ea6767
HZ
1619}
1620
1621static inline void adjust_tsc_offset_host(struct kvm_vcpu *vcpu, s64 adjustment)
1622{
1623 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio)
1624 WARN_ON(adjustment < 0);
1625 adjustment = kvm_scale_tsc(vcpu, (u64) adjustment);
ea26e4ec 1626 adjust_tsc_offset_guest(vcpu, adjustment);
58ea6767
HZ
1627}
1628
d828199e
MT
1629#ifdef CONFIG_X86_64
1630
a5a1d1c2 1631static u64 read_tsc(void)
d828199e 1632{
a5a1d1c2 1633 u64 ret = (u64)rdtsc_ordered();
03b9730b 1634 u64 last = pvclock_gtod_data.clock.cycle_last;
d828199e
MT
1635
1636 if (likely(ret >= last))
1637 return ret;
1638
1639 /*
1640 * GCC likes to generate cmov here, but this branch is extremely
6a6256f9 1641 * predictable (it's just a function of time and the likely is
d828199e
MT
1642 * very likely) and there's a data dependence, so force GCC
1643 * to generate a branch instead. I don't barrier() because
1644 * we don't actually need a barrier, and if this function
1645 * ever gets inlined it will generate worse code.
1646 */
1647 asm volatile ("");
1648 return last;
1649}
1650
a5a1d1c2 1651static inline u64 vgettsc(u64 *cycle_now)
d828199e
MT
1652{
1653 long v;
1654 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1655
1656 *cycle_now = read_tsc();
1657
1658 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1659 return v * gtod->clock.mult;
1660}
1661
a5a1d1c2 1662static int do_monotonic_boot(s64 *t, u64 *cycle_now)
d828199e 1663{
cbcf2dd3 1664 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
d828199e 1665 unsigned long seq;
d828199e 1666 int mode;
cbcf2dd3 1667 u64 ns;
d828199e 1668
d828199e
MT
1669 do {
1670 seq = read_seqcount_begin(&gtod->seq);
1671 mode = gtod->clock.vclock_mode;
cbcf2dd3 1672 ns = gtod->nsec_base;
d828199e
MT
1673 ns += vgettsc(cycle_now);
1674 ns >>= gtod->clock.shift;
cbcf2dd3 1675 ns += gtod->boot_ns;
d828199e 1676 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
cbcf2dd3 1677 *t = ns;
d828199e
MT
1678
1679 return mode;
1680}
1681
55dd00a7
MT
1682static int do_realtime(struct timespec *ts, u64 *cycle_now)
1683{
1684 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1685 unsigned long seq;
1686 int mode;
1687 u64 ns;
1688
1689 do {
1690 seq = read_seqcount_begin(&gtod->seq);
1691 mode = gtod->clock.vclock_mode;
1692 ts->tv_sec = gtod->wall_time_sec;
1693 ns = gtod->nsec_base;
1694 ns += vgettsc(cycle_now);
1695 ns >>= gtod->clock.shift;
1696 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1697
1698 ts->tv_sec += __iter_div_u64_rem(ns, NSEC_PER_SEC, &ns);
1699 ts->tv_nsec = ns;
1700
1701 return mode;
1702}
1703
d828199e 1704/* returns true if host is using tsc clocksource */
a5a1d1c2 1705static bool kvm_get_time_and_clockread(s64 *kernel_ns, u64 *cycle_now)
d828199e 1706{
d828199e
MT
1707 /* checked again under seqlock below */
1708 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1709 return false;
1710
cbcf2dd3 1711 return do_monotonic_boot(kernel_ns, cycle_now) == VCLOCK_TSC;
d828199e 1712}
55dd00a7
MT
1713
1714/* returns true if host is using tsc clocksource */
1715static bool kvm_get_walltime_and_clockread(struct timespec *ts,
1716 u64 *cycle_now)
1717{
1718 /* checked again under seqlock below */
1719 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1720 return false;
1721
1722 return do_realtime(ts, cycle_now) == VCLOCK_TSC;
1723}
d828199e
MT
1724#endif
1725
1726/*
1727 *
b48aa97e
MT
1728 * Assuming a stable TSC across physical CPUS, and a stable TSC
1729 * across virtual CPUs, the following condition is possible.
1730 * Each numbered line represents an event visible to both
d828199e
MT
1731 * CPUs at the next numbered event.
1732 *
1733 * "timespecX" represents host monotonic time. "tscX" represents
1734 * RDTSC value.
1735 *
1736 * VCPU0 on CPU0 | VCPU1 on CPU1
1737 *
1738 * 1. read timespec0,tsc0
1739 * 2. | timespec1 = timespec0 + N
1740 * | tsc1 = tsc0 + M
1741 * 3. transition to guest | transition to guest
1742 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1743 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1744 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1745 *
1746 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1747 *
1748 * - ret0 < ret1
1749 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1750 * ...
1751 * - 0 < N - M => M < N
1752 *
1753 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1754 * always the case (the difference between two distinct xtime instances
1755 * might be smaller then the difference between corresponding TSC reads,
1756 * when updating guest vcpus pvclock areas).
1757 *
1758 * To avoid that problem, do not allow visibility of distinct
1759 * system_timestamp/tsc_timestamp values simultaneously: use a master
1760 * copy of host monotonic time values. Update that master copy
1761 * in lockstep.
1762 *
b48aa97e 1763 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT
1764 *
1765 */
1766
1767static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1768{
1769#ifdef CONFIG_X86_64
1770 struct kvm_arch *ka = &kvm->arch;
1771 int vclock_mode;
b48aa97e
MT
1772 bool host_tsc_clocksource, vcpus_matched;
1773
1774 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1775 atomic_read(&kvm->online_vcpus));
d828199e
MT
1776
1777 /*
1778 * If the host uses TSC clock, then passthrough TSC as stable
1779 * to the guest.
1780 */
b48aa97e 1781 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT
1782 &ka->master_kernel_ns,
1783 &ka->master_cycle_now);
1784
16a96021 1785 ka->use_master_clock = host_tsc_clocksource && vcpus_matched
a826faf1 1786 && !ka->backwards_tsc_observed
54750f2c 1787 && !ka->boot_vcpu_runs_old_kvmclock;
b48aa97e 1788
d828199e
MT
1789 if (ka->use_master_clock)
1790 atomic_set(&kvm_guest_has_master_clock, 1);
1791
1792 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT
1793 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1794 vcpus_matched);
d828199e
MT
1795#endif
1796}
1797
2860c4b1
PB
1798void kvm_make_mclock_inprogress_request(struct kvm *kvm)
1799{
1800 kvm_make_all_cpus_request(kvm, KVM_REQ_MCLOCK_INPROGRESS);
1801}
1802
2e762ff7
MT
1803static void kvm_gen_update_masterclock(struct kvm *kvm)
1804{
1805#ifdef CONFIG_X86_64
1806 int i;
1807 struct kvm_vcpu *vcpu;
1808 struct kvm_arch *ka = &kvm->arch;
1809
1810 spin_lock(&ka->pvclock_gtod_sync_lock);
1811 kvm_make_mclock_inprogress_request(kvm);
1812 /* no guest entries from this point */
1813 pvclock_update_vm_gtod_copy(kvm);
1814
1815 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 1816 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2e762ff7
MT
1817
1818 /* guest entries allowed */
1819 kvm_for_each_vcpu(i, vcpu, kvm)
72875d8a 1820 kvm_clear_request(KVM_REQ_MCLOCK_INPROGRESS, vcpu);
2e762ff7
MT
1821
1822 spin_unlock(&ka->pvclock_gtod_sync_lock);
1823#endif
1824}
1825
e891a32e 1826u64 get_kvmclock_ns(struct kvm *kvm)
108b249c 1827{
108b249c 1828 struct kvm_arch *ka = &kvm->arch;
8b953440 1829 struct pvclock_vcpu_time_info hv_clock;
e2c2206a 1830 u64 ret;
108b249c 1831
8b953440
PB
1832 spin_lock(&ka->pvclock_gtod_sync_lock);
1833 if (!ka->use_master_clock) {
1834 spin_unlock(&ka->pvclock_gtod_sync_lock);
1835 return ktime_get_boot_ns() + ka->kvmclock_offset;
108b249c
PB
1836 }
1837
8b953440
PB
1838 hv_clock.tsc_timestamp = ka->master_cycle_now;
1839 hv_clock.system_time = ka->master_kernel_ns + ka->kvmclock_offset;
1840 spin_unlock(&ka->pvclock_gtod_sync_lock);
1841
e2c2206a
WL
1842 /* both __this_cpu_read() and rdtsc() should be on the same cpu */
1843 get_cpu();
1844
e70b57a6
WL
1845 if (__this_cpu_read(cpu_tsc_khz)) {
1846 kvm_get_time_scale(NSEC_PER_SEC, __this_cpu_read(cpu_tsc_khz) * 1000LL,
1847 &hv_clock.tsc_shift,
1848 &hv_clock.tsc_to_system_mul);
1849 ret = __pvclock_read_cycles(&hv_clock, rdtsc());
1850 } else
1851 ret = ktime_get_boot_ns() + ka->kvmclock_offset;
e2c2206a
WL
1852
1853 put_cpu();
1854
1855 return ret;
108b249c
PB
1856}
1857
0d6dd2ff
PB
1858static void kvm_setup_pvclock_page(struct kvm_vcpu *v)
1859{
1860 struct kvm_vcpu_arch *vcpu = &v->arch;
1861 struct pvclock_vcpu_time_info guest_hv_clock;
1862
4e335d9e 1863 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
0d6dd2ff
PB
1864 &guest_hv_clock, sizeof(guest_hv_clock))))
1865 return;
1866
1867 /* This VCPU is paused, but it's legal for a guest to read another
1868 * VCPU's kvmclock, so we really have to follow the specification where
1869 * it says that version is odd if data is being modified, and even after
1870 * it is consistent.
1871 *
1872 * Version field updates must be kept separate. This is because
1873 * kvm_write_guest_cached might use a "rep movs" instruction, and
1874 * writes within a string instruction are weakly ordered. So there
1875 * are three writes overall.
1876 *
1877 * As a small optimization, only write the version field in the first
1878 * and third write. The vcpu->pv_time cache is still valid, because the
1879 * version field is the first in the struct.
1880 */
1881 BUILD_BUG_ON(offsetof(struct pvclock_vcpu_time_info, version) != 0);
1882
51c4b8bb
LA
1883 if (guest_hv_clock.version & 1)
1884 ++guest_hv_clock.version; /* first time write, random junk */
1885
0d6dd2ff 1886 vcpu->hv_clock.version = guest_hv_clock.version + 1;
4e335d9e
PB
1887 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1888 &vcpu->hv_clock,
1889 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB
1890
1891 smp_wmb();
1892
1893 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1894 vcpu->hv_clock.flags |= (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
1895
1896 if (vcpu->pvclock_set_guest_stopped_request) {
1897 vcpu->hv_clock.flags |= PVCLOCK_GUEST_STOPPED;
1898 vcpu->pvclock_set_guest_stopped_request = false;
1899 }
1900
1901 trace_kvm_pvclock_update(v->vcpu_id, &vcpu->hv_clock);
1902
4e335d9e
PB
1903 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1904 &vcpu->hv_clock,
1905 sizeof(vcpu->hv_clock));
0d6dd2ff
PB
1906
1907 smp_wmb();
1908
1909 vcpu->hv_clock.version++;
4e335d9e
PB
1910 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1911 &vcpu->hv_clock,
1912 sizeof(vcpu->hv_clock.version));
0d6dd2ff
PB
1913}
1914
34c238a1 1915static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1916{
78db6a50 1917 unsigned long flags, tgt_tsc_khz;
18068523 1918 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1919 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1920 s64 kernel_ns;
d828199e 1921 u64 tsc_timestamp, host_tsc;
51d59c6b 1922 u8 pvclock_flags;
d828199e
MT
1923 bool use_master_clock;
1924
1925 kernel_ns = 0;
1926 host_tsc = 0;
18068523 1927
d828199e
MT
1928 /*
1929 * If the host uses TSC clock, then passthrough TSC as stable
1930 * to the guest.
1931 */
1932 spin_lock(&ka->pvclock_gtod_sync_lock);
1933 use_master_clock = ka->use_master_clock;
1934 if (use_master_clock) {
1935 host_tsc = ka->master_cycle_now;
1936 kernel_ns = ka->master_kernel_ns;
1937 }
1938 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT
1939
1940 /* Keep irq disabled to prevent changes to the clock */
1941 local_irq_save(flags);
78db6a50
PB
1942 tgt_tsc_khz = __this_cpu_read(cpu_tsc_khz);
1943 if (unlikely(tgt_tsc_khz == 0)) {
c09664bb
MT
1944 local_irq_restore(flags);
1945 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1946 return 1;
1947 }
d828199e 1948 if (!use_master_clock) {
4ea1636b 1949 host_tsc = rdtsc();
108b249c 1950 kernel_ns = ktime_get_boot_ns();
d828199e
MT
1951 }
1952
4ba76538 1953 tsc_timestamp = kvm_read_l1_tsc(v, host_tsc);
d828199e 1954
c285545f
ZA
1955 /*
1956 * We may have to catch up the TSC to match elapsed wall clock
1957 * time for two reasons, even if kvmclock is used.
1958 * 1) CPU could have been running below the maximum TSC rate
1959 * 2) Broken TSC compensation resets the base at each VCPU
1960 * entry to avoid unknown leaps of TSC even when running
1961 * again on the same CPU. This may cause apparent elapsed
1962 * time to disappear, and the guest to stand still or run
1963 * very slowly.
1964 */
1965 if (vcpu->tsc_catchup) {
1966 u64 tsc = compute_guest_tsc(v, kernel_ns);
1967 if (tsc > tsc_timestamp) {
f1e2b260 1968 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA
1969 tsc_timestamp = tsc;
1970 }
50d0a0f9
GH
1971 }
1972
18068523
GOC
1973 local_irq_restore(flags);
1974
0d6dd2ff 1975 /* With all the info we got, fill in the values */
18068523 1976
78db6a50
PB
1977 if (kvm_has_tsc_control)
1978 tgt_tsc_khz = kvm_scale_tsc(v, tgt_tsc_khz);
1979
1980 if (unlikely(vcpu->hw_tsc_khz != tgt_tsc_khz)) {
3ae13faa 1981 kvm_get_time_scale(NSEC_PER_SEC, tgt_tsc_khz * 1000LL,
5f4e3f88
ZA
1982 &vcpu->hv_clock.tsc_shift,
1983 &vcpu->hv_clock.tsc_to_system_mul);
78db6a50 1984 vcpu->hw_tsc_khz = tgt_tsc_khz;
8cfdc000
ZA
1985 }
1986
1d5f066e 1987 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1988 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1989 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1990
d828199e 1991 /* If the host uses TSC clocksource, then it is stable */
0d6dd2ff 1992 pvclock_flags = 0;
d828199e
MT
1993 if (use_master_clock)
1994 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1995
78c0337a
MT
1996 vcpu->hv_clock.flags = pvclock_flags;
1997
095cf55d
PB
1998 if (vcpu->pv_time_enabled)
1999 kvm_setup_pvclock_page(v);
2000 if (v == kvm_get_vcpu(v->kvm, 0))
2001 kvm_hv_setup_tsc_page(v->kvm, &vcpu->hv_clock);
8cfdc000 2002 return 0;
c8076604
GH
2003}
2004
0061d53d
MT
2005/*
2006 * kvmclock updates which are isolated to a given vcpu, such as
2007 * vcpu->cpu migration, should not allow system_timestamp from
2008 * the rest of the vcpus to remain static. Otherwise ntp frequency
2009 * correction applies to one vcpu's system_timestamp but not
2010 * the others.
2011 *
2012 * So in those cases, request a kvmclock update for all vcpus.
7e44e449
AJ
2013 * We need to rate-limit these requests though, as they can
2014 * considerably slow guests that have a large number of vcpus.
2015 * The time for a remote vcpu to update its kvmclock is bound
2016 * by the delay we use to rate-limit the updates.
0061d53d
MT
2017 */
2018
7e44e449
AJ
2019#define KVMCLOCK_UPDATE_DELAY msecs_to_jiffies(100)
2020
2021static void kvmclock_update_fn(struct work_struct *work)
0061d53d
MT
2022{
2023 int i;
7e44e449
AJ
2024 struct delayed_work *dwork = to_delayed_work(work);
2025 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2026 kvmclock_update_work);
2027 struct kvm *kvm = container_of(ka, struct kvm, arch);
0061d53d
MT
2028 struct kvm_vcpu *vcpu;
2029
2030 kvm_for_each_vcpu(i, vcpu, kvm) {
105b21bb 2031 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0061d53d
MT
2032 kvm_vcpu_kick(vcpu);
2033 }
2034}
2035
7e44e449
AJ
2036static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
2037{
2038 struct kvm *kvm = v->kvm;
2039
105b21bb 2040 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
7e44e449
AJ
2041 schedule_delayed_work(&kvm->arch.kvmclock_update_work,
2042 KVMCLOCK_UPDATE_DELAY);
2043}
2044
332967a3
AJ
2045#define KVMCLOCK_SYNC_PERIOD (300 * HZ)
2046
2047static void kvmclock_sync_fn(struct work_struct *work)
2048{
2049 struct delayed_work *dwork = to_delayed_work(work);
2050 struct kvm_arch *ka = container_of(dwork, struct kvm_arch,
2051 kvmclock_sync_work);
2052 struct kvm *kvm = container_of(ka, struct kvm, arch);
2053
630994b3
MT
2054 if (!kvmclock_periodic_sync)
2055 return;
2056
332967a3
AJ
2057 schedule_delayed_work(&kvm->arch.kvmclock_update_work, 0);
2058 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
2059 KVMCLOCK_SYNC_PERIOD);
2060}
2061
9ffd986c 2062static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2063{
890ca9ae
HY
2064 u64 mcg_cap = vcpu->arch.mcg_cap;
2065 unsigned bank_num = mcg_cap & 0xff;
9ffd986c
WL
2066 u32 msr = msr_info->index;
2067 u64 data = msr_info->data;
890ca9ae 2068
15c4a640 2069 switch (msr) {
15c4a640 2070 case MSR_IA32_MCG_STATUS:
890ca9ae 2071 vcpu->arch.mcg_status = data;
15c4a640 2072 break;
c7ac679c 2073 case MSR_IA32_MCG_CTL:
890ca9ae
HY
2074 if (!(mcg_cap & MCG_CTL_P))
2075 return 1;
2076 if (data != 0 && data != ~(u64)0)
2077 return -1;
2078 vcpu->arch.mcg_ctl = data;
2079 break;
2080 default:
2081 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2082 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae 2083 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP
2084 /* only 0 or all 1s can be written to IA32_MCi_CTL
2085 * some Linux kernels though clear bit 10 in bank 4 to
2086 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
2087 * this to avoid an uncatched #GP in the guest
2088 */
890ca9ae 2089 if ((offset & 0x3) == 0 &&
114be429 2090 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae 2091 return -1;
9ffd986c
WL
2092 if (!msr_info->host_initiated &&
2093 (offset & 0x3) == 1 && data != 0)
2094 return -1;
890ca9ae
HY
2095 vcpu->arch.mce_banks[offset] = data;
2096 break;
2097 }
2098 return 1;
2099 }
2100 return 0;
2101}
2102
ffde22ac
ES
2103static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
2104{
2105 struct kvm *kvm = vcpu->kvm;
2106 int lm = is_long_mode(vcpu);
2107 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
2108 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
2109 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
2110 : kvm->arch.xen_hvm_config.blob_size_32;
2111 u32 page_num = data & ~PAGE_MASK;
2112 u64 page_addr = data & PAGE_MASK;
2113 u8 *page;
2114 int r;
2115
2116 r = -E2BIG;
2117 if (page_num >= blob_size)
2118 goto out;
2119 r = -ENOMEM;
ff5c2c03
SL
2120 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
2121 if (IS_ERR(page)) {
2122 r = PTR_ERR(page);
ffde22ac 2123 goto out;
ff5c2c03 2124 }
54bf36aa 2125 if (kvm_vcpu_write_guest(vcpu, page_addr, page, PAGE_SIZE))
ffde22ac
ES
2126 goto out_free;
2127 r = 0;
2128out_free:
2129 kfree(page);
2130out:
2131 return r;
2132}
2133
344d9588
GN
2134static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
2135{
2136 gpa_t gpa = data & ~0x3f;
2137
52a5c155
WL
2138 /* Bits 3:5 are reserved, Should be zero */
2139 if (data & 0x38)
344d9588
GN
2140 return 1;
2141
2142 vcpu->arch.apf.msr_val = data;
2143
2144 if (!(data & KVM_ASYNC_PF_ENABLED)) {
2145 kvm_clear_async_pf_completion_queue(vcpu);
2146 kvm_async_pf_hash_reset(vcpu);
2147 return 0;
2148 }
2149
4e335d9e 2150 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
8f964525 2151 sizeof(u32)))
344d9588
GN
2152 return 1;
2153
6adba527 2154 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
52a5c155 2155 vcpu->arch.apf.delivery_as_pf_vmexit = data & KVM_ASYNC_PF_DELIVERY_AS_PF_VMEXIT;
344d9588
GN
2156 kvm_async_pf_wakeup_all(vcpu);
2157 return 0;
2158}
2159
12f9a48f
GC
2160static void kvmclock_reset(struct kvm_vcpu *vcpu)
2161{
0b79459b 2162 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC
2163}
2164
c9aaa895
GC
2165static void record_steal_time(struct kvm_vcpu *vcpu)
2166{
2167 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2168 return;
2169
4e335d9e 2170 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC
2171 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
2172 return;
2173
0b9f6c46
PX
2174 vcpu->arch.st.steal.preempted = 0;
2175
35f3fae1
WL
2176 if (vcpu->arch.st.steal.version & 1)
2177 vcpu->arch.st.steal.version += 1; /* first time write, random junk */
2178
2179 vcpu->arch.st.steal.version += 1;
2180
4e335d9e 2181 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL
2182 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2183
2184 smp_wmb();
2185
c54cdf14
LC
2186 vcpu->arch.st.steal.steal += current->sched_info.run_delay -
2187 vcpu->arch.st.last_steal;
2188 vcpu->arch.st.last_steal = current->sched_info.run_delay;
35f3fae1 2189
4e335d9e 2190 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
35f3fae1
WL
2191 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2192
2193 smp_wmb();
2194
2195 vcpu->arch.st.steal.version += 1;
c9aaa895 2196
4e335d9e 2197 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
c9aaa895
GC
2198 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
2199}
2200
8fe8ab46 2201int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 2202{
5753785f 2203 bool pr = false;
8fe8ab46
WA
2204 u32 msr = msr_info->index;
2205 u64 data = msr_info->data;
5753785f 2206
15c4a640 2207 switch (msr) {
2e32b719
BP
2208 case MSR_AMD64_NB_CFG:
2209 case MSR_IA32_UCODE_REV:
2210 case MSR_IA32_UCODE_WRITE:
2211 case MSR_VM_HSAVE_PA:
2212 case MSR_AMD64_PATCH_LOADER:
2213 case MSR_AMD64_BU_CFG2:
405a353a 2214 case MSR_AMD64_DC_CFG:
2e32b719
BP
2215 break;
2216
15c4a640 2217 case MSR_EFER:
b69e8cae 2218 return set_efer(vcpu, data);
8f1589d9
AP
2219 case MSR_K7_HWCR:
2220 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2221 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2222 data &= ~(u64)0x8; /* ignore TLB cache disable */
22d48b2d 2223 data &= ~(u64)0x40000; /* ignore Mc status write enable */
8f1589d9 2224 if (data != 0) {
a737f256
CD
2225 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2226 data);
8f1589d9
AP
2227 return 1;
2228 }
15c4a640 2229 break;
f7c6d140
AP
2230 case MSR_FAM10H_MMIO_CONF_BASE:
2231 if (data != 0) {
a737f256
CD
2232 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2233 "0x%llx\n", data);
f7c6d140
AP
2234 return 1;
2235 }
15c4a640 2236 break;
b5e2fec0
AG
2237 case MSR_IA32_DEBUGCTLMSR:
2238 if (!data) {
2239 /* We support the non-activated case already */
2240 break;
2241 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2242 /* Values other than LBR and BTF are vendor-specific,
2243 thus reserved and should throw a #GP */
2244 return 1;
2245 }
a737f256
CD
2246 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2247 __func__, data);
b5e2fec0 2248 break;
9ba075a6 2249 case 0x200 ... 0x2ff:
ff53604b 2250 return kvm_mtrr_set_msr(vcpu, msr, data);
15c4a640 2251 case MSR_IA32_APICBASE:
58cb628d 2252 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN
2253 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2254 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ
2255 case MSR_IA32_TSCDEADLINE:
2256 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2257 break;
ba904635 2258 case MSR_IA32_TSC_ADJUST:
d6321d49 2259 if (guest_cpuid_has(vcpu, X86_FEATURE_TSC_ADJUST)) {
ba904635 2260 if (!msr_info->host_initiated) {
d913b904 2261 s64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
d7add054 2262 adjust_tsc_offset_guest(vcpu, adj);
ba904635
WA
2263 }
2264 vcpu->arch.ia32_tsc_adjust_msr = data;
2265 }
2266 break;
15c4a640 2267 case MSR_IA32_MISC_ENABLE:
ad312c7c 2268 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2269 break;
64d60670
PB
2270 case MSR_IA32_SMBASE:
2271 if (!msr_info->host_initiated)
2272 return 1;
2273 vcpu->arch.smbase = data;
2274 break;
11c6bffa 2275 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC
2276 case MSR_KVM_WALL_CLOCK:
2277 vcpu->kvm->arch.wall_clock = data;
2278 kvm_write_wall_clock(vcpu->kvm, data);
2279 break;
11c6bffa 2280 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2281 case MSR_KVM_SYSTEM_TIME: {
54750f2c
MT
2282 struct kvm_arch *ka = &vcpu->kvm->arch;
2283
12f9a48f 2284 kvmclock_reset(vcpu);
18068523 2285
54750f2c
MT
2286 if (vcpu->vcpu_id == 0 && !msr_info->host_initiated) {
2287 bool tmp = (msr == MSR_KVM_SYSTEM_TIME);
2288
2289 if (ka->boot_vcpu_runs_old_kvmclock != tmp)
1bd2009e 2290 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
54750f2c
MT
2291
2292 ka->boot_vcpu_runs_old_kvmclock = tmp;
2293 }
2294
18068523 2295 vcpu->arch.time = data;
0061d53d 2296 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC
2297
2298 /* we verify if the enable bit is set... */
2299 if (!(data & 1))
2300 break;
2301
4e335d9e 2302 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH
2303 &vcpu->arch.pv_time, data & ~1ULL,
2304 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH
2305 vcpu->arch.pv_time_enabled = false;
2306 else
2307 vcpu->arch.pv_time_enabled = true;
32cad84f 2308
18068523
GOC
2309 break;
2310 }
344d9588
GN
2311 case MSR_KVM_ASYNC_PF_EN:
2312 if (kvm_pv_enable_async_pf(vcpu, data))
2313 return 1;
2314 break;
c9aaa895
GC
2315 case MSR_KVM_STEAL_TIME:
2316
2317 if (unlikely(!sched_info_on()))
2318 return 1;
2319
2320 if (data & KVM_STEAL_RESERVED_MASK)
2321 return 1;
2322
4e335d9e 2323 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH
2324 data & KVM_STEAL_VALID_BITS,
2325 sizeof(struct kvm_steal_time)))
c9aaa895
GC
2326 return 1;
2327
2328 vcpu->arch.st.msr_val = data;
2329
2330 if (!(data & KVM_MSR_ENABLED))
2331 break;
2332
c9aaa895
GC
2333 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2334
2335 break;
ae7a2a3f
MT
2336 case MSR_KVM_PV_EOI_EN:
2337 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2338 return 1;
2339 break;
c9aaa895 2340
890ca9ae
HY
2341 case MSR_IA32_MCG_CTL:
2342 case MSR_IA32_MCG_STATUS:
81760dcc 2343 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
9ffd986c 2344 return set_msr_mce(vcpu, msr_info);
71db6023 2345
6912ac32
WH
2346 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2347 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2348 pr = true; /* fall through */
2349 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2350 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2351 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2352 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN
2353
2354 if (pr || data != 0)
a737f256
CD
2355 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2356 "0x%x data 0x%llx\n", msr, data);
5753785f 2357 break;
84e0cefa
JS
2358 case MSR_K7_CLK_CTL:
2359 /*
2360 * Ignore all writes to this no longer documented MSR.
2361 * Writes are only relevant for old K7 processors,
2362 * all pre-dating SVM, but a recommended workaround from
4a969980 2363 * AMD for these chips. It is possible to specify the
84e0cefa
JS
2364 * affected processor models on the command line, hence
2365 * the need to ignore the workaround.
2366 */
2367 break;
55cd8e5a 2368 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS
2369 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2370 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2371 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e7d9513b
AS
2372 return kvm_hv_set_msr_common(vcpu, msr, data,
2373 msr_info->host_initiated);
91c9c3ed 2374 case MSR_IA32_BBL_CR_CTL3:
2375 /* Drop writes to this legacy MSR -- see rdmsr
2376 * counterpart for further detail.
2377 */
fab0aa3b
EM
2378 if (report_ignored_msrs)
2379 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data 0x%llx\n",
2380 msr, data);
91c9c3ed 2381 break;
2b036c6b 2382 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2383 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO
2384 return 1;
2385 vcpu->arch.osvw.length = data;
2386 break;
2387 case MSR_AMD64_OSVW_STATUS:
d6321d49 2388 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b
BO
2389 return 1;
2390 vcpu->arch.osvw.status = data;
2391 break;
db2336a8
KH
2392 case MSR_PLATFORM_INFO:
2393 if (!msr_info->host_initiated ||
2394 data & ~MSR_PLATFORM_INFO_CPUID_FAULT ||
2395 (!(data & MSR_PLATFORM_INFO_CPUID_FAULT) &&
2396 cpuid_fault_enabled(vcpu)))
2397 return 1;
2398 vcpu->arch.msr_platform_info = data;
2399 break;
2400 case MSR_MISC_FEATURES_ENABLES:
2401 if (data & ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT ||
2402 (data & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
2403 !supports_cpuid_fault(vcpu)))
2404 return 1;
2405 vcpu->arch.msr_misc_features_enables = data;
2406 break;
15c4a640 2407 default:
ffde22ac
ES
2408 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2409 return xen_hvm_config(vcpu, data);
c6702c9d 2410 if (kvm_pmu_is_valid_msr(vcpu, msr))
afd80d85 2411 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2412 if (!ignore_msrs) {
ae0f5499 2413 vcpu_debug_ratelimited(vcpu, "unhandled wrmsr: 0x%x data 0x%llx\n",
a737f256 2414 msr, data);
ed85c068
AP
2415 return 1;
2416 } else {
fab0aa3b
EM
2417 if (report_ignored_msrs)
2418 vcpu_unimpl(vcpu,
2419 "ignored wrmsr: 0x%x data 0x%llx\n",
2420 msr, data);
ed85c068
AP
2421 break;
2422 }
15c4a640
CO
2423 }
2424 return 0;
2425}
2426EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2427
2428
2429/*
2430 * Reads an msr value (of 'msr_index') into 'pdata'.
2431 * Returns 0 on success, non-0 otherwise.
2432 * Assumes vcpu_load() was already called.
2433 */
609e36d3 2434int kvm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 2435{
609e36d3 2436 return kvm_x86_ops->get_msr(vcpu, msr);
15c4a640 2437}
ff651cb6 2438EXPORT_SYMBOL_GPL(kvm_get_msr);
15c4a640 2439
890ca9ae 2440static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO
2441{
2442 u64 data;
890ca9ae
HY
2443 u64 mcg_cap = vcpu->arch.mcg_cap;
2444 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO
2445
2446 switch (msr) {
15c4a640
CO
2447 case MSR_IA32_P5_MC_ADDR:
2448 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY
2449 data = 0;
2450 break;
15c4a640 2451 case MSR_IA32_MCG_CAP:
890ca9ae
HY
2452 data = vcpu->arch.mcg_cap;
2453 break;
c7ac679c 2454 case MSR_IA32_MCG_CTL:
890ca9ae
HY
2455 if (!(mcg_cap & MCG_CTL_P))
2456 return 1;
2457 data = vcpu->arch.mcg_ctl;
2458 break;
2459 case MSR_IA32_MCG_STATUS:
2460 data = vcpu->arch.mcg_status;
2461 break;
2462 default:
2463 if (msr >= MSR_IA32_MC0_CTL &&
81760dcc 2464 msr < MSR_IA32_MCx_CTL(bank_num)) {
890ca9ae
HY
2465 u32 offset = msr - MSR_IA32_MC0_CTL;
2466 data = vcpu->arch.mce_banks[offset];
2467 break;
2468 }
2469 return 1;
2470 }
2471 *pdata = data;
2472 return 0;
2473}
2474
609e36d3 2475int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
890ca9ae 2476{
609e36d3 2477 switch (msr_info->index) {
890ca9ae 2478 case MSR_IA32_PLATFORM_ID:
15c4a640 2479 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG
2480 case MSR_IA32_DEBUGCTLMSR:
2481 case MSR_IA32_LASTBRANCHFROMIP:
2482 case MSR_IA32_LASTBRANCHTOIP:
2483 case MSR_IA32_LASTINTFROMIP:
2484 case MSR_IA32_LASTINTTOIP:
60af2ecd 2485 case MSR_K8_SYSCFG:
3afb1121
PB
2486 case MSR_K8_TSEG_ADDR:
2487 case MSR_K8_TSEG_MASK:
60af2ecd 2488 case MSR_K7_HWCR:
61a6bd67 2489 case MSR_VM_HSAVE_PA:
1fdbd48c 2490 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2491 case MSR_AMD64_NB_CFG:
f7c6d140 2492 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2493 case MSR_AMD64_BU_CFG2:
0c2df2a1 2494 case MSR_IA32_PERF_CTL:
405a353a 2495 case MSR_AMD64_DC_CFG:
609e36d3 2496 msr_info->data = 0;
15c4a640 2497 break;
6912ac32
WH
2498 case MSR_K7_EVNTSEL0 ... MSR_K7_EVNTSEL3:
2499 case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
2500 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
2501 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL1:
c6702c9d 2502 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3
PB
2503 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
2504 msr_info->data = 0;
5753785f 2505 break;
742bc670 2506 case MSR_IA32_UCODE_REV:
609e36d3 2507 msr_info->data = 0x100000000ULL;
742bc670 2508 break;
9ba075a6 2509 case MSR_MTRRcap:
9ba075a6 2510 case 0x200 ... 0x2ff:
ff53604b 2511 return kvm_mtrr_get_msr(vcpu, msr_info->index, &msr_info->data);
15c4a640 2512 case 0xcd: /* fsb frequency */
609e36d3 2513 msr_info->data = 3;
15c4a640 2514 break;
7b914098
JS
2515 /*
2516 * MSR_EBC_FREQUENCY_ID
2517 * Conservative value valid for even the basic CPU models.
2518 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2519 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2520 * and 266MHz for model 3, or 4. Set Core Clock
2521 * Frequency to System Bus Frequency Ratio to 1 (bits
2522 * 31:24) even though these are only valid for CPU
2523 * models > 2, however guests may end up dividing or
2524 * multiplying by zero otherwise.
2525 */
2526 case MSR_EBC_FREQUENCY_ID:
609e36d3 2527 msr_info->data = 1 << 24;
7b914098 2528 break;
15c4a640 2529 case MSR_IA32_APICBASE:
609e36d3 2530 msr_info->data = kvm_get_apic_base(vcpu);
15c4a640 2531 break;
0105d1a5 2532 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
609e36d3 2533 return kvm_x2apic_msr_read(vcpu, msr_info->index, &msr_info->data);
0105d1a5 2534 break;
a3e06bbe 2535 case MSR_IA32_TSCDEADLINE:
609e36d3 2536 msr_info->data = kvm_get_lapic_tscdeadline_msr(vcpu);
a3e06bbe 2537 break;
ba904635 2538 case MSR_IA32_TSC_ADJUST:
609e36d3 2539 msr_info->data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
ba904635 2540 break;
15c4a640 2541 case MSR_IA32_MISC_ENABLE:
609e36d3 2542 msr_info->data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2543 break;
64d60670
PB
2544 case MSR_IA32_SMBASE:
2545 if (!msr_info->host_initiated)
2546 return 1;
2547 msr_info->data = vcpu->arch.smbase;
15c4a640 2548 break;
847f0ad8
AG
2549 case MSR_IA32_PERF_STATUS:
2550 /* TSC increment by tick */
609e36d3 2551 msr_info->data = 1000ULL;
847f0ad8 2552 /* CPU multiplier */
b0996ae4 2553 msr_info->data |= (((uint64_t)4ULL) << 40);
847f0ad8 2554 break;
15c4a640 2555 case MSR_EFER:
609e36d3 2556 msr_info->data = vcpu->arch.efer;
15c4a640 2557 break;
18068523 2558 case MSR_KVM_WALL_CLOCK:
11c6bffa 2559 case MSR_KVM_WALL_CLOCK_NEW:
609e36d3 2560 msr_info->data = vcpu->kvm->arch.wall_clock;
18068523
GOC
2561 break;
2562 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2563 case MSR_KVM_SYSTEM_TIME_NEW:
609e36d3 2564 msr_info->data = vcpu->arch.time;
18068523 2565 break;
344d9588 2566 case MSR_KVM_ASYNC_PF_EN:
609e36d3 2567 msr_info->data = vcpu->arch.apf.msr_val;
344d9588 2568 break;
c9aaa895 2569 case MSR_KVM_STEAL_TIME:
609e36d3 2570 msr_info->data = vcpu->arch.st.msr_val;
c9aaa895 2571 break;
1d92128f 2572 case MSR_KVM_PV_EOI_EN:
609e36d3 2573 msr_info->data = vcpu->arch.pv_eoi.msr_val;
1d92128f 2574 break;
890ca9ae
HY
2575 case MSR_IA32_P5_MC_ADDR:
2576 case MSR_IA32_P5_MC_TYPE:
2577 case MSR_IA32_MCG_CAP:
2578 case MSR_IA32_MCG_CTL:
2579 case MSR_IA32_MCG_STATUS:
81760dcc 2580 case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
609e36d3 2581 return get_msr_mce(vcpu, msr_info->index, &msr_info->data);
84e0cefa
JS
2582 case MSR_K7_CLK_CTL:
2583 /*
2584 * Provide expected ramp-up count for K7. All other
2585 * are set to zero, indicating minimum divisors for
2586 * every field.
2587 *
2588 * This prevents guest kernels on AMD host with CPU
2589 * type 6, model 8 and higher from exploding due to
2590 * the rdmsr failing.
2591 */
609e36d3 2592 msr_info->data = 0x20000000;
84e0cefa 2593 break;
55cd8e5a 2594 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
e7d9513b
AS
2595 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2596 case HV_X64_MSR_CRASH_CTL:
1f4b34f8 2597 case HV_X64_MSR_STIMER0_CONFIG ... HV_X64_MSR_STIMER3_COUNT:
e83d5887
AS
2598 return kvm_hv_get_msr_common(vcpu,
2599 msr_info->index, &msr_info->data);
55cd8e5a 2600 break;
91c9c3ed 2601 case MSR_IA32_BBL_CR_CTL3:
2602 /* This legacy MSR exists but isn't fully documented in current
2603 * silicon. It is however accessed by winxp in very narrow
2604 * scenarios where it sets bit #19, itself documented as
2605 * a "reserved" bit. Best effort attempt to source coherent
2606 * read data here should the balance of the register be
2607 * interpreted by the guest:
2608 *
2609 * L2 cache control register 3: 64GB range, 256KB size,
2610 * enabled, latency 0x1, configured
2611 */
609e36d3 2612 msr_info->data = 0xbe702111;
91c9c3ed 2613 break;
2b036c6b 2614 case MSR_AMD64_OSVW_ID_LENGTH:
d6321d49 2615 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2616 return 1;
609e36d3 2617 msr_info->data = vcpu->arch.osvw.length;
2b036c6b
BO
2618 break;
2619 case MSR_AMD64_OSVW_STATUS:
d6321d49 2620 if (!guest_cpuid_has(vcpu, X86_FEATURE_OSVW))
2b036c6b 2621 return 1;
609e36d3 2622 msr_info->data = vcpu->arch.osvw.status;
2b036c6b 2623 break;
db2336a8
KH
2624 case MSR_PLATFORM_INFO:
2625 msr_info->data = vcpu->arch.msr_platform_info;
2626 break;
2627 case MSR_MISC_FEATURES_ENABLES:
2628 msr_info->data = vcpu->arch.msr_misc_features_enables;
2629 break;
15c4a640 2630 default:
c6702c9d 2631 if (kvm_pmu_is_valid_msr(vcpu, msr_info->index))
609e36d3 2632 return kvm_pmu_get_msr(vcpu, msr_info->index, &msr_info->data);
ed85c068 2633 if (!ignore_msrs) {
ae0f5499
BD
2634 vcpu_debug_ratelimited(vcpu, "unhandled rdmsr: 0x%x\n",
2635 msr_info->index);
ed85c068
AP
2636 return 1;
2637 } else {
fab0aa3b
EM
2638 if (report_ignored_msrs)
2639 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n",
2640 msr_info->index);
609e36d3 2641 msr_info->data = 0;
ed85c068
AP
2642 }
2643 break;
15c4a640 2644 }
15c4a640
CO
2645 return 0;
2646}
2647EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2648
313a3dc7
CO
2649/*
2650 * Read or write a bunch of msrs. All parameters are kernel addresses.
2651 *
2652 * @return number of msrs set successfully.
2653 */
2654static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2655 struct kvm_msr_entry *entries,
2656 int (*do_msr)(struct kvm_vcpu *vcpu,
2657 unsigned index, u64 *data))
2658{
ab1bebf8 2659 int i;
313a3dc7 2660
313a3dc7
CO
2661 for (i = 0; i < msrs->nmsrs; ++i)
2662 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2663 break;
2664
313a3dc7
CO
2665 return i;
2666}
2667
2668/*
2669 * Read or write a bunch of msrs. Parameters are user addresses.
2670 *
2671 * @return number of msrs set successfully.
2672 */
2673static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2674 int (*do_msr)(struct kvm_vcpu *vcpu,
2675 unsigned index, u64 *data),
2676 int writeback)
2677{
2678 struct kvm_msrs msrs;
2679 struct kvm_msr_entry *entries;
2680 int r, n;
2681 unsigned size;
2682
2683 r = -EFAULT;
2684 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2685 goto out;
2686
2687 r = -E2BIG;
2688 if (msrs.nmsrs >= MAX_IO_MSRS)
2689 goto out;
2690
313a3dc7 2691 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL
2692 entries = memdup_user(user_msrs->entries, size);
2693 if (IS_ERR(entries)) {
2694 r = PTR_ERR(entries);
313a3dc7 2695 goto out;
ff5c2c03 2696 }
313a3dc7
CO
2697
2698 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2699 if (r < 0)
2700 goto out_free;
2701
2702 r = -EFAULT;
2703 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2704 goto out_free;
2705
2706 r = n;
2707
2708out_free:
7a73c028 2709 kfree(entries);
313a3dc7
CO
2710out:
2711 return r;
2712}
2713
784aa3d7 2714int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
018d00d2
ZX
2715{
2716 int r;
2717
2718 switch (ext) {
2719 case KVM_CAP_IRQCHIP:
2720 case KVM_CAP_HLT:
2721 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2722 case KVM_CAP_SET_TSS_ADDR:
07716717 2723 case KVM_CAP_EXT_CPUID:
9c15bb1d 2724 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2725 case KVM_CAP_CLOCKSOURCE:
7837699f 2726 case KVM_CAP_PIT:
a28e4f5a 2727 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2728 case KVM_CAP_MP_STATE:
ed848624 2729 case KVM_CAP_SYNC_MMU:
a355c85c 2730 case KVM_CAP_USER_NMI:
52d939a0 2731 case KVM_CAP_REINJECT_CONTROL:
4925663a 2732 case KVM_CAP_IRQ_INJECT_STATUS:
d34e6b17 2733 case KVM_CAP_IOEVENTFD:
f848a5a8 2734 case KVM_CAP_IOEVENTFD_NO_LENGTH:
c5ff41ce 2735 case KVM_CAP_PIT2:
e9f42757 2736 case KVM_CAP_PIT_STATE2:
b927a3ce 2737 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2738 case KVM_CAP_XEN_HVM:
3cfc3092 2739 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2740 case KVM_CAP_HYPERV:
10388a07 2741 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2742 case KVM_CAP_HYPERV_SPIN:
5c919412 2743 case KVM_CAP_HYPERV_SYNIC:
efc479e6 2744 case KVM_CAP_HYPERV_SYNIC2:
d3457c87 2745 case KVM_CAP_HYPERV_VP_INDEX:
ab9f4ecb 2746 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2747 case KVM_CAP_DEBUGREGS:
d2be1651 2748 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2749 case KVM_CAP_XSAVE:
344d9588 2750 case KVM_CAP_ASYNC_PF:
92a1f12d 2751 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2752 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2753 case KVM_CAP_READONLY_MEM:
5f66b620 2754 case KVM_CAP_HYPERV_TIME:
100943c5 2755 case KVM_CAP_IOAPIC_POLARITY_IGNORED:
defcf51f 2756 case KVM_CAP_TSC_DEADLINE_TIMER:
90de4a18
NA
2757 case KVM_CAP_ENABLE_CAP_VM:
2758 case KVM_CAP_DISABLE_QUIRKS:
d71ba788 2759 case KVM_CAP_SET_BOOT_CPU_ID:
49df6397 2760 case KVM_CAP_SPLIT_IRQCHIP:
460df4c1 2761 case KVM_CAP_IMMEDIATE_EXIT:
ab1bebf8 2762 case KVM_CAP_GET_MSR_FEATURES:
018d00d2
ZX
2763 r = 1;
2764 break;
e3fd9a93
PB
2765 case KVM_CAP_ADJUST_CLOCK:
2766 r = KVM_CLOCK_TSC_STABLE;
2767 break;
668fffa3
MT
2768 case KVM_CAP_X86_GUEST_MWAIT:
2769 r = kvm_mwait_in_guest();
2770 break;
6d396b55
PB
2771 case KVM_CAP_X86_SMM:
2772 /* SMBASE is usually relocated above 1M on modern chipsets,
2773 * and SMM handlers might indeed rely on 4G segment limits,
2774 * so do not report SMM to be available if real mode is
2775 * emulated via vm86 mode. Still, do not go to great lengths
2776 * to avoid userspace's usage of the feature, because it is a
2777 * fringe case that is not enabled except via specific settings
2778 * of the module parameters.
2779 */
4d5c8a07 2780 r = kvm_x86_ops->has_emulated_msr(MSR_IA32_SMBASE);
6d396b55 2781 break;
774ead3a
AK
2782 case KVM_CAP_VAPIC:
2783 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2784 break;
f725230a 2785 case KVM_CAP_NR_VCPUS:
8c3ba334
SL
2786 r = KVM_SOFT_MAX_VCPUS;
2787 break;
2788 case KVM_CAP_MAX_VCPUS:
f725230a
AK
2789 r = KVM_MAX_VCPUS;
2790 break;
a988b910 2791 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2792 r = KVM_USER_MEM_SLOTS;
a988b910 2793 break;
a68a6a72
MT
2794 case KVM_CAP_PV_MMU: /* obsolete */
2795 r = 0;
2f333bcb 2796 break;
890ca9ae
HY
2797 case KVM_CAP_MCE:
2798 r = KVM_MAX_MCE_BANKS;
2799 break;
2d5b5a66 2800 case KVM_CAP_XCRS:
d366bf7e 2801 r = boot_cpu_has(X86_FEATURE_XSAVE);
2d5b5a66 2802 break;
92a1f12d
JR
2803 case KVM_CAP_TSC_CONTROL:
2804 r = kvm_has_tsc_control;
2805 break;
37131313
RK
2806 case KVM_CAP_X2APIC_API:
2807 r = KVM_X2APIC_API_VALID_FLAGS;
2808 break;
018d00d2
ZX
2809 default:
2810 r = 0;
2811 break;
2812 }
2813 return r;
2814
2815}
2816
043405e1
CO
2817long kvm_arch_dev_ioctl(struct file *filp,
2818 unsigned int ioctl, unsigned long arg)
2819{
2820 void __user *argp = (void __user *)arg;
2821 long r;
2822
2823 switch (ioctl) {
2824 case KVM_GET_MSR_INDEX_LIST: {
2825 struct kvm_msr_list __user *user_msr_list = argp;
2826 struct kvm_msr_list msr_list;
2827 unsigned n;
2828
2829 r = -EFAULT;
2830 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2831 goto out;
2832 n = msr_list.nmsrs;
62ef68bb 2833 msr_list.nmsrs = num_msrs_to_save + num_emulated_msrs;
043405e1
CO
2834 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2835 goto out;
2836 r = -E2BIG;
e125e7b6 2837 if (n < msr_list.nmsrs)
043405e1
CO
2838 goto out;
2839 r = -EFAULT;
2840 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2841 num_msrs_to_save * sizeof(u32)))
2842 goto out;
e125e7b6 2843 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1 2844 &emulated_msrs,
62ef68bb 2845 num_emulated_msrs * sizeof(u32)))
043405e1
CO
2846 goto out;
2847 r = 0;
2848 break;
2849 }
9c15bb1d
BP
2850 case KVM_GET_SUPPORTED_CPUID:
2851 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK
2852 struct kvm_cpuid2 __user *cpuid_arg = argp;
2853 struct kvm_cpuid2 cpuid;
2854
2855 r = -EFAULT;
2856 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2857 goto out;
9c15bb1d
BP
2858
2859 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2860 ioctl);
674eea0f
AK
2861 if (r)
2862 goto out;
2863
2864 r = -EFAULT;
2865 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2866 goto out;
2867 r = 0;
2868 break;
2869 }
890ca9ae 2870 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
890ca9ae 2871 r = -EFAULT;
c45dcc71
AR
2872 if (copy_to_user(argp, &kvm_mce_cap_supported,
2873 sizeof(kvm_mce_cap_supported)))
890ca9ae
HY
2874 goto out;
2875 r = 0;
2876 break;
ab1bebf8
TL
2877 case KVM_GET_MSR_FEATURE_INDEX_LIST: {
2878 struct kvm_msr_list __user *user_msr_list = argp;
2879 struct kvm_msr_list msr_list;
2880 unsigned int n;
2881
2882 r = -EFAULT;
2883 if (copy_from_user(&msr_list, user_msr_list, sizeof(msr_list)))
2884 goto out;
2885 n = msr_list.nmsrs;
2886 msr_list.nmsrs = num_msr_based_features;
2887 if (copy_to_user(user_msr_list, &msr_list, sizeof(msr_list)))
2888 goto out;
2889 r = -E2BIG;
2890 if (n < msr_list.nmsrs)
2891 goto out;
2892 r = -EFAULT;
2893 if (copy_to_user(user_msr_list->indices, &msr_based_features,
2894 num_msr_based_features * sizeof(u32)))
2895 goto out;
2896 r = 0;
2897 break;
2898 }
2899 case KVM_GET_MSRS:
2900 r = msr_io(NULL, argp, do_get_msr_feature, 1);
2901 break;
890ca9ae 2902 }
043405e1
CO
2903 default:
2904 r = -EINVAL;
2905 }
2906out:
2907 return r;
2908}
2909
f5f48ee1
SY
2910static void wbinvd_ipi(void *garbage)
2911{
2912 wbinvd();
2913}
2914
2915static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2916{
e0f0bbc5 2917 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY
2918}
2919
313a3dc7
CO
2920void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2921{
f5f48ee1
SY
2922 /* Address WBINVD may be executed by guest */
2923 if (need_emulate_wbinvd(vcpu)) {
2924 if (kvm_x86_ops->has_wbinvd_exit())
2925 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2926 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2927 smp_call_function_single(vcpu->cpu,
2928 wbinvd_ipi, NULL, 1);
2929 }
2930
313a3dc7 2931 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2932
0dd6a6ed
ZA
2933 /* Apply any externally detected TSC adjustments (due to suspend) */
2934 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2935 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2936 vcpu->arch.tsc_offset_adjustment = 0;
105b21bb 2937 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed 2938 }
8f6055cb 2939
48434c20 2940 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5 2941 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
4ea1636b 2942 rdtsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA
2943 if (tsc_delta < 0)
2944 mark_tsc_unstable("KVM discovered backwards TSC");
ce7a058a 2945
c285545f 2946 if (check_tsc_unstable()) {
07c1419a 2947 u64 offset = kvm_compute_tsc_offset(vcpu,
b183aa58 2948 vcpu->arch.last_guest_tsc);
a545ab6a 2949 kvm_vcpu_write_tsc_offset(vcpu, offset);
c285545f 2950 vcpu->arch.tsc_catchup = 1;
c285545f 2951 }
a749e247
PB
2952
2953 if (kvm_lapic_hv_timer_in_use(vcpu))
2954 kvm_lapic_restart_hv_timer(vcpu);
2955
d98d07ca
MT
2956 /*
2957 * On a host with synchronized TSC, there is no need to update
2958 * kvmclock on vcpu->cpu migration
2959 */
2960 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2961 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f 2962 if (vcpu->cpu != cpu)
1bd2009e 2963 kvm_make_request(KVM_REQ_MIGRATE_TIMER, vcpu);
e48672fa 2964 vcpu->cpu = cpu;
6b7d7e76 2965 }
c9aaa895 2966
c9aaa895 2967 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO
2968}
2969
0b9f6c46
PX
2970static void kvm_steal_time_set_preempted(struct kvm_vcpu *vcpu)
2971{
2972 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
2973 return;
2974
2975 vcpu->arch.st.steal.preempted = 1;
2976
4e335d9e 2977 kvm_write_guest_offset_cached(vcpu->kvm, &vcpu->arch.st.stime,
0b9f6c46
PX
2978 &vcpu->arch.st.steal.preempted,
2979 offsetof(struct kvm_steal_time, preempted),
2980 sizeof(vcpu->arch.st.steal.preempted));
2981}
2982
313a3dc7
CO
2983void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2984{
cc0d907c 2985 int idx;
de63ad4c
LM
2986
2987 if (vcpu->preempted)
2988 vcpu->arch.preempted_in_kernel = !kvm_x86_ops->get_cpl(vcpu);
2989
931f261b
AA
2990 /*
2991 * Disable page faults because we're in atomic context here.
2992 * kvm_write_guest_offset_cached() would call might_fault()
2993 * that relies on pagefault_disable() to tell if there's a
2994 * bug. NOTE: the write to guest memory may not go through if
2995 * during postcopy live migration or if there's heavy guest
2996 * paging.
2997 */
2998 pagefault_disable();
cc0d907c
AA
2999 /*
3000 * kvm_memslots() will be called by
3001 * kvm_write_guest_offset_cached() so take the srcu lock.
3002 */
3003 idx = srcu_read_lock(&vcpu->kvm->srcu);
0b9f6c46 3004 kvm_steal_time_set_preempted(vcpu);
cc0d907c 3005 srcu_read_unlock(&vcpu->kvm->srcu, idx);
931f261b 3006 pagefault_enable();
02daab21 3007 kvm_x86_ops->vcpu_put(vcpu);
4ea1636b 3008 vcpu->arch.last_host_tsc = rdtsc();
7046f30e
WL
3009 /*
3010 * If userspace has set any breakpoints or watchpoints, dr6 is restored
3011 * on every vmexit, but if not, we might have a stale dr6 from the
3012 * guest. do_debug expects dr6 to be cleared after it runs, do the same.
3013 */
3014 set_debugreg(0, 6);
313a3dc7
CO
3015}
3016
313a3dc7
CO
3017static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
3018 struct kvm_lapic_state *s)
3019{
76dfafd5 3020 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb
AS
3021 kvm_x86_ops->sync_pir_to_irr(vcpu);
3022
a92e2543 3023 return kvm_apic_get_state(vcpu, s);
313a3dc7
CO
3024}
3025
3026static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
3027 struct kvm_lapic_state *s)
3028{
a92e2543
RK
3029 int r;
3030
3031 r = kvm_apic_set_state(vcpu, s);
3032 if (r)
3033 return r;
cb142eb7 3034 update_cr8_intercept(vcpu);
313a3dc7
CO
3035
3036 return 0;
3037}
3038
127a457a
MG
3039static int kvm_cpu_accept_dm_intr(struct kvm_vcpu *vcpu)
3040{
3041 return (!lapic_in_kernel(vcpu) ||
3042 kvm_apic_accept_pic_intr(vcpu));
3043}
3044
782d422b
MG
3045/*
3046 * if userspace requested an interrupt window, check that the
3047 * interrupt window is open.
3048 *
3049 * No need to exit to userspace if we already have an interrupt queued.
3050 */
3051static int kvm_vcpu_ready_for_interrupt_injection(struct kvm_vcpu *vcpu)
3052{
3053 return kvm_arch_interrupt_allowed(vcpu) &&
3054 !kvm_cpu_has_interrupt(vcpu) &&
3055 !kvm_event_needs_reinjection(vcpu) &&
3056 kvm_cpu_accept_dm_intr(vcpu);
3057}
3058
f77bc6a4
ZX
3059static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
3060 struct kvm_interrupt *irq)
3061{
02cdb50f 3062 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4 3063 return -EINVAL;
1c1a9ce9
SR
3064
3065 if (!irqchip_in_kernel(vcpu->kvm)) {
3066 kvm_queue_interrupt(vcpu, irq->irq, false);
3067 kvm_make_request(KVM_REQ_EVENT, vcpu);
3068 return 0;
3069 }
3070
3071 /*
3072 * With in-kernel LAPIC, we only use this to inject EXTINT, so
3073 * fail for in-kernel 8259.
3074 */
3075 if (pic_in_kernel(vcpu->kvm))
f77bc6a4 3076 return -ENXIO;
f77bc6a4 3077
1c1a9ce9
SR
3078 if (vcpu->arch.pending_external_vector != -1)
3079 return -EEXIST;
f77bc6a4 3080
1c1a9ce9 3081 vcpu->arch.pending_external_vector = irq->irq;
934bf653 3082 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4
ZX
3083 return 0;
3084}
3085
c4abb7c9
JK
3086static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
3087{
c4abb7c9 3088 kvm_inject_nmi(vcpu);
c4abb7c9
JK
3089
3090 return 0;
3091}
3092
f077825a
PB
3093static int kvm_vcpu_ioctl_smi(struct kvm_vcpu *vcpu)
3094{
64d60670
PB
3095 kvm_make_request(KVM_REQ_SMI, vcpu);
3096
f077825a
PB
3097 return 0;
3098}
3099
b209749f
AK
3100static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
3101 struct kvm_tpr_access_ctl *tac)
3102{
3103 if (tac->flags)
3104 return -EINVAL;
3105 vcpu->arch.tpr_access_reporting = !!tac->enabled;
3106 return 0;
3107}
3108
890ca9ae
HY
3109static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
3110 u64 mcg_cap)
3111{
3112 int r;
3113 unsigned bank_num = mcg_cap & 0xff, bank;
3114
3115 r = -EINVAL;
a9e38c3e 3116 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae 3117 goto out;
c45dcc71 3118 if (mcg_cap & ~(kvm_mce_cap_supported | 0xff | 0xff0000))
890ca9ae
HY
3119 goto out;
3120 r = 0;
3121 vcpu->arch.mcg_cap = mcg_cap;
3122 /* Init IA32_MCG_CTL to all 1s */
3123 if (mcg_cap & MCG_CTL_P)
3124 vcpu->arch.mcg_ctl = ~(u64)0;
3125 /* Init IA32_MCi_CTL to all 1s */
3126 for (bank = 0; bank < bank_num; bank++)
3127 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
c45dcc71
AR
3128
3129 if (kvm_x86_ops->setup_mce)
3130 kvm_x86_ops->setup_mce(vcpu);
890ca9ae
HY
3131out:
3132 return r;
3133}
3134
3135static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
3136 struct kvm_x86_mce *mce)
3137{
3138 u64 mcg_cap = vcpu->arch.mcg_cap;
3139 unsigned bank_num = mcg_cap & 0xff;
3140 u64 *banks = vcpu->arch.mce_banks;
3141
3142 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
3143 return -EINVAL;
3144 /*
3145 * if IA32_MCG_CTL is not all 1s, the uncorrected error
3146 * reporting is disabled
3147 */
3148 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
3149 vcpu->arch.mcg_ctl != ~(u64)0)
3150 return 0;
3151 banks += 4 * mce->bank;
3152 /*
3153 * if IA32_MCi_CTL is not all 1s, the uncorrected error
3154 * reporting is disabled for the bank
3155 */
3156 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
3157 return 0;
3158 if (mce->status & MCI_STATUS_UC) {
3159 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 3160 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 3161 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY
3162 return 0;
3163 }
3164 if (banks[1] & MCI_STATUS_VAL)
3165 mce->status |= MCI_STATUS_OVER;
3166 banks[2] = mce->addr;
3167 banks[3] = mce->misc;
3168 vcpu->arch.mcg_status = mce->mcg_status;
3169 banks[1] = mce->status;
3170 kvm_queue_exception(vcpu, MC_VECTOR);
3171 } else if (!(banks[1] & MCI_STATUS_VAL)
3172 || !(banks[1] & MCI_STATUS_UC)) {
3173 if (banks[1] & MCI_STATUS_VAL)
3174 mce->status |= MCI_STATUS_OVER;
3175 banks[2] = mce->addr;
3176 banks[3] = mce->misc;
3177 banks[1] = mce->status;
3178 } else
3179 banks[1] |= MCI_STATUS_OVER;
3180 return 0;
3181}
3182
3cfc3092
JK
3183static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
3184 struct kvm_vcpu_events *events)
3185{
7460fb4a 3186 process_nmi(vcpu);
664f8e26
WL
3187 /*
3188 * FIXME: pass injected and pending separately. This is only
3189 * needed for nested virtualization, whose state cannot be
3190 * migrated yet. For now we can combine them.
3191 */
03b82a30 3192 events->exception.injected =
664f8e26
WL
3193 (vcpu->arch.exception.pending ||
3194 vcpu->arch.exception.injected) &&
03b82a30 3195 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK
3196 events->exception.nr = vcpu->arch.exception.nr;
3197 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 3198 events->exception.pad = 0;
3cfc3092
JK
3199 events->exception.error_code = vcpu->arch.exception.error_code;
3200
03b82a30
JK
3201 events->interrupt.injected =
3202 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 3203 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 3204 events->interrupt.soft = 0;
37ccdcbe 3205 events->interrupt.shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
3cfc3092
JK
3206
3207 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 3208 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 3209 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 3210 events->nmi.pad = 0;
3cfc3092 3211
66450a21 3212 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 3213
f077825a
PB
3214 events->smi.smm = is_smm(vcpu);
3215 events->smi.pending = vcpu->arch.smi_pending;
3216 events->smi.smm_inside_nmi =
3217 !!(vcpu->arch.hflags & HF_SMM_INSIDE_NMI_MASK);
3218 events->smi.latched_init = kvm_lapic_latched_init(vcpu);
3219
dab4b911 3220 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
f077825a
PB
3221 | KVM_VCPUEVENT_VALID_SHADOW
3222 | KVM_VCPUEVENT_VALID_SMM);
97e69aa6 3223 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK
3224}
3225
6ef4e07e
XG
3226static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags);
3227
3cfc3092
JK
3228static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
3229 struct kvm_vcpu_events *events)
3230{
dab4b911 3231 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 3232 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
f077825a
PB
3233 | KVM_VCPUEVENT_VALID_SHADOW
3234 | KVM_VCPUEVENT_VALID_SMM))
3cfc3092
JK
3235 return -EINVAL;
3236
78e546c8 3237 if (events->exception.injected &&
28d06353
JM
3238 (events->exception.nr > 31 || events->exception.nr == NMI_VECTOR ||
3239 is_guest_mode(vcpu)))
78e546c8
PB
3240 return -EINVAL;
3241
28bf2888
DH
3242 /* INITs are latched while in SMM */
3243 if (events->flags & KVM_VCPUEVENT_VALID_SMM &&
3244 (events->smi.smm || events->smi.pending) &&
3245 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED)
3246 return -EINVAL;
3247
7460fb4a 3248 process_nmi(vcpu);
664f8e26 3249 vcpu->arch.exception.injected = false;
3cfc3092
JK
3250 vcpu->arch.exception.pending = events->exception.injected;
3251 vcpu->arch.exception.nr = events->exception.nr;
3252 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
3253 vcpu->arch.exception.error_code = events->exception.error_code;
3254
3255 vcpu->arch.interrupt.pending = events->interrupt.injected;
3256 vcpu->arch.interrupt.nr = events->interrupt.nr;
3257 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK
3258 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
3259 kvm_x86_ops->set_interrupt_shadow(vcpu,
3260 events->interrupt.shadow);
3cfc3092
JK
3261
3262 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK
3263 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
3264 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK
3265 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
3266
66450a21 3267 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
bce87cce 3268 lapic_in_kernel(vcpu))
66450a21 3269 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 3270
f077825a 3271 if (events->flags & KVM_VCPUEVENT_VALID_SMM) {
6ef4e07e 3272 u32 hflags = vcpu->arch.hflags;
f077825a 3273 if (events->smi.smm)
6ef4e07e 3274 hflags |= HF_SMM_MASK;
f077825a 3275 else
6ef4e07e
XG
3276 hflags &= ~HF_SMM_MASK;
3277 kvm_set_hflags(vcpu, hflags);
3278
f077825a 3279 vcpu->arch.smi_pending = events->smi.pending;
f4ef1910
WL
3280
3281 if (events->smi.smm) {
3282 if (events->smi.smm_inside_nmi)
3283 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
f077825a 3284 else
f4ef1910
WL
3285 vcpu->arch.hflags &= ~HF_SMM_INSIDE_NMI_MASK;
3286 if (lapic_in_kernel(vcpu)) {
3287 if (events->smi.latched_init)
3288 set_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3289 else
3290 clear_bit(KVM_APIC_INIT, &vcpu->arch.apic->pending_events);
3291 }
f077825a
PB
3292 }
3293 }
3294
3842d135
AK
3295 kvm_make_request(KVM_REQ_EVENT, vcpu);
3296
3cfc3092
JK
3297 return 0;
3298}
3299
a1efbe77
JK
3300static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
3301 struct kvm_debugregs *dbgregs)
3302{
73aaf249
JK
3303 unsigned long val;
3304
a1efbe77 3305 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
16f8a6f9 3306 kvm_get_dr(vcpu, 6, &val);
73aaf249 3307 dbgregs->dr6 = val;
a1efbe77
JK
3308 dbgregs->dr7 = vcpu->arch.dr7;
3309 dbgregs->flags = 0;
97e69aa6 3310 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK
3311}
3312
3313static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3314 struct kvm_debugregs *dbgregs)
3315{
3316 if (dbgregs->flags)
3317 return -EINVAL;
3318
d14bdb55
PB
3319 if (dbgregs->dr6 & ~0xffffffffull)
3320 return -EINVAL;
3321 if (dbgregs->dr7 & ~0xffffffffull)
3322 return -EINVAL;
3323
a1efbe77 3324 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
ae561ede 3325 kvm_update_dr0123(vcpu);
a1efbe77 3326 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3327 kvm_update_dr6(vcpu);
a1efbe77 3328 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3329 kvm_update_dr7(vcpu);
a1efbe77 3330
a1efbe77
JK
3331 return 0;
3332}
3333
df1daba7
PB
3334#define XSTATE_COMPACTION_ENABLED (1ULL << 63)
3335
3336static void fill_xsave(u8 *dest, struct kvm_vcpu *vcpu)
3337{
c47ada30 3338 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
400e4b20 3339 u64 xstate_bv = xsave->header.xfeatures;
df1daba7
PB
3340 u64 valid;
3341
3342 /*
3343 * Copy legacy XSAVE area, to avoid complications with CPUID
3344 * leaves 0 and 1 in the loop below.
3345 */
3346 memcpy(dest, xsave, XSAVE_HDR_OFFSET);
3347
3348 /* Set XSTATE_BV */
00c87e9a 3349 xstate_bv &= vcpu->arch.guest_supported_xcr0 | XFEATURE_MASK_FPSSE;
df1daba7
PB
3350 *(u64 *)(dest + XSAVE_HDR_OFFSET) = xstate_bv;
3351
3352 /*
3353 * Copy each region from the possibly compacted offset to the
3354 * non-compacted offset.
3355 */
d91cab78 3356 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB
3357 while (valid) {
3358 u64 feature = valid & -valid;
3359 int index = fls64(feature) - 1;
3360 void *src = get_xsave_addr(xsave, feature);
3361
3362 if (src) {
3363 u32 size, offset, ecx, edx;
3364 cpuid_count(XSTATE_CPUID, index,
3365 &size, &offset, &ecx, &edx);
38cfd5e3
PB
3366 if (feature == XFEATURE_MASK_PKRU)
3367 memcpy(dest + offset, &vcpu->arch.pkru,
3368 sizeof(vcpu->arch.pkru));
3369 else
3370 memcpy(dest + offset, src, size);
3371
df1daba7
PB
3372 }
3373
3374 valid -= feature;
3375 }
3376}
3377
3378static void load_xsave(struct kvm_vcpu *vcpu, u8 *src)
3379{
c47ada30 3380 struct xregs_state *xsave = &vcpu->arch.guest_fpu.state.xsave;
df1daba7
PB
3381 u64 xstate_bv = *(u64 *)(src + XSAVE_HDR_OFFSET);
3382 u64 valid;
3383
3384 /*
3385 * Copy legacy XSAVE area, to avoid complications with CPUID
3386 * leaves 0 and 1 in the loop below.
3387 */
3388 memcpy(xsave, src, XSAVE_HDR_OFFSET);
3389
3390 /* Set XSTATE_BV and possibly XCOMP_BV. */
400e4b20 3391 xsave->header.xfeatures = xstate_bv;
782511b0 3392 if (boot_cpu_has(X86_FEATURE_XSAVES))
3a54450b 3393 xsave->header.xcomp_bv = host_xcr0 | XSTATE_COMPACTION_ENABLED;
df1daba7
PB
3394
3395 /*
3396 * Copy each region from the non-compacted offset to the
3397 * possibly compacted offset.
3398 */
d91cab78 3399 valid = xstate_bv & ~XFEATURE_MASK_FPSSE;
df1daba7
PB
3400 while (valid) {
3401 u64 feature = valid & -valid;
3402 int index = fls64(feature) - 1;
3403 void *dest = get_xsave_addr(xsave, feature);
3404
3405 if (dest) {
3406 u32 size, offset, ecx, edx;
3407 cpuid_count(XSTATE_CPUID, index,
3408 &size, &offset, &ecx, &edx);
38cfd5e3
PB
3409 if (feature == XFEATURE_MASK_PKRU)
3410 memcpy(&vcpu->arch.pkru, src + offset,
3411 sizeof(vcpu->arch.pkru));
3412 else
3413 memcpy(dest, src + offset, size);
ee4100da 3414 }
df1daba7
PB
3415
3416 valid -= feature;
3417 }
3418}
3419
2d5b5a66
SY
3420static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3421 struct kvm_xsave *guest_xsave)
3422{
d366bf7e 3423 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
df1daba7
PB
3424 memset(guest_xsave, 0, sizeof(struct kvm_xsave));
3425 fill_xsave((u8 *) guest_xsave->region, vcpu);
4344ee98 3426 } else {
2d5b5a66 3427 memcpy(guest_xsave->region,
7366ed77 3428 &vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3429 sizeof(struct fxregs_state));
2d5b5a66 3430 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
d91cab78 3431 XFEATURE_MASK_FPSSE;
2d5b5a66
SY
3432 }
3433}
3434
a575813b
WL
3435#define XSAVE_MXCSR_OFFSET 24
3436
2d5b5a66
SY
3437static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3438 struct kvm_xsave *guest_xsave)
3439{
3440 u64 xstate_bv =
3441 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
a575813b 3442 u32 mxcsr = *(u32 *)&guest_xsave->region[XSAVE_MXCSR_OFFSET / sizeof(u32)];
2d5b5a66 3443
d366bf7e 3444 if (boot_cpu_has(X86_FEATURE_XSAVE)) {
d7876f1b
PB
3445 /*
3446 * Here we allow setting states that are not present in
3447 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3448 * with old userspace.
3449 */
a575813b
WL
3450 if (xstate_bv & ~kvm_supported_xcr0() ||
3451 mxcsr & ~mxcsr_feature_mask)
d7876f1b 3452 return -EINVAL;
df1daba7 3453 load_xsave(vcpu, (u8 *)guest_xsave->region);
d7876f1b 3454 } else {
a575813b
WL
3455 if (xstate_bv & ~XFEATURE_MASK_FPSSE ||
3456 mxcsr & ~mxcsr_feature_mask)
2d5b5a66 3457 return -EINVAL;
7366ed77 3458 memcpy(&vcpu->arch.guest_fpu.state.fxsave,
c47ada30 3459 guest_xsave->region, sizeof(struct fxregs_state));
2d5b5a66
SY
3460 }
3461 return 0;
3462}
3463
3464static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3465 struct kvm_xcrs *guest_xcrs)
3466{
d366bf7e 3467 if (!boot_cpu_has(X86_FEATURE_XSAVE)) {
2d5b5a66
SY
3468 guest_xcrs->nr_xcrs = 0;
3469 return;
3470 }
3471
3472 guest_xcrs->nr_xcrs = 1;
3473 guest_xcrs->flags = 0;
3474 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3475 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3476}
3477
3478static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3479 struct kvm_xcrs *guest_xcrs)
3480{
3481 int i, r = 0;
3482
d366bf7e 3483 if (!boot_cpu_has(X86_FEATURE_XSAVE))
2d5b5a66
SY
3484 return -EINVAL;
3485
3486 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3487 return -EINVAL;
3488
3489 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3490 /* Only support XCR0 currently */
c67a04cb 3491 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3492 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3493 guest_xcrs->xcrs[i].value);
2d5b5a66
SY
3494 break;
3495 }
3496 if (r)
3497 r = -EINVAL;
3498 return r;
3499}
3500
1c0b28c2
EM
3501/*
3502 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3503 * stopped by the hypervisor. This function will be called from the host only.
3504 * EINVAL is returned when the host attempts to set the flag for a guest that
3505 * does not support pv clocks.
3506 */
3507static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3508{
0b79459b 3509 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3510 return -EINVAL;
51d59c6b 3511 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM
3512 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3513 return 0;
3514}
3515
5c919412
AS
3516static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
3517 struct kvm_enable_cap *cap)
3518{
3519 if (cap->flags)
3520 return -EINVAL;
3521
3522 switch (cap->cap) {
efc479e6
RK
3523 case KVM_CAP_HYPERV_SYNIC2:
3524 if (cap->args[0])
3525 return -EINVAL;
5c919412 3526 case KVM_CAP_HYPERV_SYNIC:
546d87e5
WL
3527 if (!irqchip_in_kernel(vcpu->kvm))
3528 return -EINVAL;
efc479e6
RK
3529 return kvm_hv_activate_synic(vcpu, cap->cap ==
3530 KVM_CAP_HYPERV_SYNIC2);
5c919412
AS
3531 default:
3532 return -EINVAL;
3533 }
3534}
3535
313a3dc7
CO
3536long kvm_arch_vcpu_ioctl(struct file *filp,
3537 unsigned int ioctl, unsigned long arg)
3538{
3539 struct kvm_vcpu *vcpu = filp->private_data;
3540 void __user *argp = (void __user *)arg;
3541 int r;
d1ac91d8
AK
3542 union {
3543 struct kvm_lapic_state *lapic;
3544 struct kvm_xsave *xsave;
3545 struct kvm_xcrs *xcrs;
3546 void *buffer;
3547 } u;
3548
3549 u.buffer = NULL;
313a3dc7
CO
3550 switch (ioctl) {
3551 case KVM_GET_LAPIC: {
2204ae3c 3552 r = -EINVAL;
bce87cce 3553 if (!lapic_in_kernel(vcpu))
2204ae3c 3554 goto out;
d1ac91d8 3555 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3556
b772ff36 3557 r = -ENOMEM;
d1ac91d8 3558 if (!u.lapic)
b772ff36 3559 goto out;
d1ac91d8 3560 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO
3561 if (r)
3562 goto out;
3563 r = -EFAULT;
d1ac91d8 3564 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO
3565 goto out;
3566 r = 0;
3567 break;
3568 }
3569 case KVM_SET_LAPIC: {
2204ae3c 3570 r = -EINVAL;
bce87cce 3571 if (!lapic_in_kernel(vcpu))
2204ae3c 3572 goto out;
ff5c2c03 3573 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC
3574 if (IS_ERR(u.lapic))
3575 return PTR_ERR(u.lapic);
ff5c2c03 3576
d1ac91d8 3577 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO
3578 break;
3579 }
f77bc6a4
ZX
3580 case KVM_INTERRUPT: {
3581 struct kvm_interrupt irq;
3582
3583 r = -EFAULT;
3584 if (copy_from_user(&irq, argp, sizeof irq))
3585 goto out;
3586 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX
3587 break;
3588 }
c4abb7c9
JK
3589 case KVM_NMI: {
3590 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK
3591 break;
3592 }
f077825a
PB
3593 case KVM_SMI: {
3594 r = kvm_vcpu_ioctl_smi(vcpu);
3595 break;
3596 }
313a3dc7
CO
3597 case KVM_SET_CPUID: {
3598 struct kvm_cpuid __user *cpuid_arg = argp;
3599 struct kvm_cpuid cpuid;
3600
3601 r = -EFAULT;
3602 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3603 goto out;
3604 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO
3605 break;
3606 }
07716717
DK
3607 case KVM_SET_CPUID2: {
3608 struct kvm_cpuid2 __user *cpuid_arg = argp;
3609 struct kvm_cpuid2 cpuid;
3610
3611 r = -EFAULT;
3612 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3613 goto out;
3614 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3615 cpuid_arg->entries);
07716717
DK
3616 break;
3617 }
3618 case KVM_GET_CPUID2: {
3619 struct kvm_cpuid2 __user *cpuid_arg = argp;
3620 struct kvm_cpuid2 cpuid;
3621
3622 r = -EFAULT;
3623 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3624 goto out;
3625 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3626 cpuid_arg->entries);
07716717
DK
3627 if (r)
3628 goto out;
3629 r = -EFAULT;
3630 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3631 goto out;
3632 r = 0;
3633 break;
3634 }
ab1bebf8
TL
3635 case KVM_GET_MSRS: {
3636 int idx = srcu_read_lock(&vcpu->kvm->srcu);
609e36d3 3637 r = msr_io(vcpu, argp, do_get_msr, 1);
ab1bebf8 3638 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3639 break;
ab1bebf8
TL
3640 }
3641 case KVM_SET_MSRS: {
3642 int idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7 3643 r = msr_io(vcpu, argp, do_set_msr, 0);
ab1bebf8 3644 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 3645 break;
ab1bebf8 3646 }
b209749f
AK
3647 case KVM_TPR_ACCESS_REPORTING: {
3648 struct kvm_tpr_access_ctl tac;
3649
3650 r = -EFAULT;
3651 if (copy_from_user(&tac, argp, sizeof tac))
3652 goto out;
3653 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3654 if (r)
3655 goto out;
3656 r = -EFAULT;
3657 if (copy_to_user(argp, &tac, sizeof tac))
3658 goto out;
3659 r = 0;
3660 break;
3661 };
b93463aa
AK
3662 case KVM_SET_VAPIC_ADDR: {
3663 struct kvm_vapic_addr va;
7301d6ab 3664 int idx;
b93463aa
AK
3665
3666 r = -EINVAL;
35754c98 3667 if (!lapic_in_kernel(vcpu))
b93463aa
AK
3668 goto out;
3669 r = -EFAULT;
3670 if (copy_from_user(&va, argp, sizeof va))
3671 goto out;
7301d6ab 3672 idx = srcu_read_lock(&vcpu->kvm->srcu);
fda4e2e8 3673 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
7301d6ab 3674 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK
3675 break;
3676 }
890ca9ae
HY
3677 case KVM_X86_SETUP_MCE: {
3678 u64 mcg_cap;
3679
3680 r = -EFAULT;
3681 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3682 goto out;
3683 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3684 break;
3685 }
3686 case KVM_X86_SET_MCE: {
3687 struct kvm_x86_mce mce;
3688
3689 r = -EFAULT;
3690 if (copy_from_user(&mce, argp, sizeof mce))
3691 goto out;
3692 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3693 break;
3694 }
3cfc3092
JK
3695 case KVM_GET_VCPU_EVENTS: {
3696 struct kvm_vcpu_events events;
3697
3698 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3699
3700 r = -EFAULT;
3701 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3702 break;
3703 r = 0;
3704 break;
3705 }
3706 case KVM_SET_VCPU_EVENTS: {
3707 struct kvm_vcpu_events events;
3708
3709 r = -EFAULT;
3710 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3711 break;
3712
3713 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3714 break;
3715 }
a1efbe77
JK
3716 case KVM_GET_DEBUGREGS: {
3717 struct kvm_debugregs dbgregs;
3718
3719 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3720
3721 r = -EFAULT;
3722 if (copy_to_user(argp, &dbgregs,
3723 sizeof(struct kvm_debugregs)))
3724 break;
3725 r = 0;
3726 break;
3727 }
3728 case KVM_SET_DEBUGREGS: {
3729 struct kvm_debugregs dbgregs;
3730
3731 r = -EFAULT;
3732 if (copy_from_user(&dbgregs, argp,
3733 sizeof(struct kvm_debugregs)))
3734 break;
3735
3736 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3737 break;
3738 }
2d5b5a66 3739 case KVM_GET_XSAVE: {
d1ac91d8 3740 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3741 r = -ENOMEM;
d1ac91d8 3742 if (!u.xsave)
2d5b5a66
SY
3743 break;
3744
d1ac91d8 3745 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY
3746
3747 r = -EFAULT;
d1ac91d8 3748 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY
3749 break;
3750 r = 0;
3751 break;
3752 }
3753 case KVM_SET_XSAVE: {
ff5c2c03 3754 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC
3755 if (IS_ERR(u.xsave))
3756 return PTR_ERR(u.xsave);
2d5b5a66 3757
d1ac91d8 3758 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY
3759 break;
3760 }
3761 case KVM_GET_XCRS: {
d1ac91d8 3762 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3763 r = -ENOMEM;
d1ac91d8 3764 if (!u.xcrs)
2d5b5a66
SY
3765 break;
3766
d1ac91d8 3767 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY
3768
3769 r = -EFAULT;
d1ac91d8 3770 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY
3771 sizeof(struct kvm_xcrs)))
3772 break;
3773 r = 0;
3774 break;
3775 }
3776 case KVM_SET_XCRS: {
ff5c2c03 3777 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC
3778 if (IS_ERR(u.xcrs))
3779 return PTR_ERR(u.xcrs);
2d5b5a66 3780
d1ac91d8 3781 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY
3782 break;
3783 }
92a1f12d
JR
3784 case KVM_SET_TSC_KHZ: {
3785 u32 user_tsc_khz;
3786
3787 r = -EINVAL;
92a1f12d
JR
3788 user_tsc_khz = (u32)arg;
3789
3790 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3791 goto out;
3792
cc578287
ZA
3793 if (user_tsc_khz == 0)
3794 user_tsc_khz = tsc_khz;
3795
381d585c
HZ
3796 if (!kvm_set_tsc_khz(vcpu, user_tsc_khz))
3797 r = 0;
92a1f12d 3798
92a1f12d
JR
3799 goto out;
3800 }
3801 case KVM_GET_TSC_KHZ: {
cc578287 3802 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR
3803 goto out;
3804 }
1c0b28c2
EM
3805 case KVM_KVMCLOCK_CTRL: {
3806 r = kvm_set_guest_paused(vcpu);
3807 goto out;
3808 }
5c919412
AS
3809 case KVM_ENABLE_CAP: {
3810 struct kvm_enable_cap cap;
3811
3812 r = -EFAULT;
3813 if (copy_from_user(&cap, argp, sizeof(cap)))
3814 goto out;
3815 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
3816 break;
3817 }
313a3dc7
CO
3818 default:
3819 r = -EINVAL;
3820 }
3821out:
d1ac91d8 3822 kfree(u.buffer);
313a3dc7
CO
3823 return r;
3824}
3825
5b1c1493
CO
3826int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3827{
3828 return VM_FAULT_SIGBUS;
3829}
3830
1fe779f8
CO
3831static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3832{
3833 int ret;
3834
3835 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3836 return -EINVAL;
1fe779f8
CO
3837 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3838 return ret;
3839}
3840
b927a3ce
SY
3841static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3842 u64 ident_addr)
3843{
3844 kvm->arch.ept_identity_map_addr = ident_addr;
3845 return 0;
3846}
3847
1fe779f8
CO
3848static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3849 u32 kvm_nr_mmu_pages)
3850{
3851 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3852 return -EINVAL;
3853
79fac95e 3854 mutex_lock(&kvm->slots_lock);
1fe779f8
CO
3855
3856 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3857 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3858
79fac95e 3859 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO
3860 return 0;
3861}
3862
3863static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3864{
39de71ec 3865 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO
3866}
3867
1fe779f8
CO
3868static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3869{
90bca052 3870 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO
3871 int r;
3872
3873 r = 0;
3874 switch (chip->chip_id) {
3875 case KVM_IRQCHIP_PIC_MASTER:
90bca052 3876 memcpy(&chip->chip.pic, &pic->pics[0],
1fe779f8
CO
3877 sizeof(struct kvm_pic_state));
3878 break;
3879 case KVM_IRQCHIP_PIC_SLAVE:
90bca052 3880 memcpy(&chip->chip.pic, &pic->pics[1],
1fe779f8
CO
3881 sizeof(struct kvm_pic_state));
3882 break;
3883 case KVM_IRQCHIP_IOAPIC:
33392b49 3884 kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO
3885 break;
3886 default:
3887 r = -EINVAL;
3888 break;
3889 }
3890 return r;
3891}
3892
3893static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3894{
90bca052 3895 struct kvm_pic *pic = kvm->arch.vpic;
1fe779f8
CO
3896 int r;
3897
3898 r = 0;
3899 switch (chip->chip_id) {
3900 case KVM_IRQCHIP_PIC_MASTER:
90bca052
DH
3901 spin_lock(&pic->lock);
3902 memcpy(&pic->pics[0], &chip->chip.pic,
1fe779f8 3903 sizeof(struct kvm_pic_state));
90bca052 3904 spin_unlock(&pic->lock);
1fe779f8
CO
3905 break;
3906 case KVM_IRQCHIP_PIC_SLAVE:
90bca052
DH
3907 spin_lock(&pic->lock);
3908 memcpy(&pic->pics[1], &chip->chip.pic,
1fe779f8 3909 sizeof(struct kvm_pic_state));
90bca052 3910 spin_unlock(&pic->lock);
1fe779f8
CO
3911 break;
3912 case KVM_IRQCHIP_IOAPIC:
33392b49 3913 kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO
3914 break;
3915 default:
3916 r = -EINVAL;
3917 break;
3918 }
90bca052 3919 kvm_pic_update_irq(pic);
1fe779f8
CO
3920 return r;
3921}
3922
e0f63cb9
SY
3923static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3924{
34f3941c
RK
3925 struct kvm_kpit_state *kps = &kvm->arch.vpit->pit_state;
3926
3927 BUILD_BUG_ON(sizeof(*ps) != sizeof(kps->channels));
3928
3929 mutex_lock(&kps->lock);
3930 memcpy(ps, &kps->channels, sizeof(*ps));
3931 mutex_unlock(&kps->lock);
2da29bcc 3932 return 0;
e0f63cb9
SY
3933}
3934
3935static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3936{
0185604c 3937 int i;
09edea72
RK
3938 struct kvm_pit *pit = kvm->arch.vpit;
3939
3940 mutex_lock(&pit->pit_state.lock);
34f3941c 3941 memcpy(&pit->pit_state.channels, ps, sizeof(*ps));
0185604c 3942 for (i = 0; i < 3; i++)
09edea72
RK
3943 kvm_pit_load_count(pit, i, ps->channels[i].count, 0);
3944 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3945 return 0;
e9f42757
BK
3946}
3947
3948static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3949{
e9f42757
BK
3950 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3951 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3952 sizeof(ps->channels));
3953 ps->flags = kvm->arch.vpit->pit_state.flags;
3954 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3955 memset(&ps->reserved, 0, sizeof(ps->reserved));
2da29bcc 3956 return 0;
e9f42757
BK
3957}
3958
3959static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3960{
2da29bcc 3961 int start = 0;
0185604c 3962 int i;
e9f42757 3963 u32 prev_legacy, cur_legacy;
09edea72
RK
3964 struct kvm_pit *pit = kvm->arch.vpit;
3965
3966 mutex_lock(&pit->pit_state.lock);
3967 prev_legacy = pit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
e9f42757
BK
3968 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3969 if (!prev_legacy && cur_legacy)
3970 start = 1;
09edea72
RK
3971 memcpy(&pit->pit_state.channels, &ps->channels,
3972 sizeof(pit->pit_state.channels));
3973 pit->pit_state.flags = ps->flags;
0185604c 3974 for (i = 0; i < 3; i++)
09edea72 3975 kvm_pit_load_count(pit, i, pit->pit_state.channels[i].count,
e5e57e7a 3976 start && i == 0);
09edea72 3977 mutex_unlock(&pit->pit_state.lock);
2da29bcc 3978 return 0;
e0f63cb9
SY
3979}
3980
52d939a0
MT
3981static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3982 struct kvm_reinject_control *control)
3983{
71474e2f
RK
3984 struct kvm_pit *pit = kvm->arch.vpit;
3985
3986 if (!pit)
52d939a0 3987 return -ENXIO;
b39c90b6 3988
71474e2f
RK
3989 /* pit->pit_state.lock was overloaded to prevent userspace from getting
3990 * an inconsistent state after running multiple KVM_REINJECT_CONTROL
3991 * ioctls in parallel. Use a separate lock if that ioctl isn't rare.
3992 */
3993 mutex_lock(&pit->pit_state.lock);
3994 kvm_pit_set_reinject(pit, control->pit_reinject);
3995 mutex_unlock(&pit->pit_state.lock);
b39c90b6 3996
52d939a0
MT
3997 return 0;
3998}
3999
95d4c16c 4000/**
60c34612
TY
4001 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
4002 * @kvm: kvm instance
4003 * @log: slot id and address to which we copy the log
95d4c16c 4004 *
e108ff2f
PB
4005 * Steps 1-4 below provide general overview of dirty page logging. See
4006 * kvm_get_dirty_log_protect() function description for additional details.
4007 *
4008 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
4009 * always flush the TLB (step 4) even if previous step failed and the dirty
4010 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
4011 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
4012 * writes will be marked dirty for next log read.
95d4c16c 4013 *
60c34612
TY
4014 * 1. Take a snapshot of the bit and clear it if needed.
4015 * 2. Write protect the corresponding page.
e108ff2f
PB
4016 * 3. Copy the snapshot to the userspace.
4017 * 4. Flush TLB's if needed.
5bb064dc 4018 */
60c34612 4019int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 4020{
60c34612 4021 bool is_dirty = false;
e108ff2f 4022 int r;
5bb064dc 4023
79fac95e 4024 mutex_lock(&kvm->slots_lock);
5bb064dc 4025
88178fd4
KH
4026 /*
4027 * Flush potentially hardware-cached dirty pages to dirty_bitmap.
4028 */
4029 if (kvm_x86_ops->flush_log_dirty)
4030 kvm_x86_ops->flush_log_dirty(kvm);
4031
e108ff2f 4032 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
198c74f4
XG
4033
4034 /*
4035 * All the TLBs can be flushed out of mmu lock, see the comments in
4036 * kvm_mmu_slot_remove_write_access().
4037 */
e108ff2f 4038 lockdep_assert_held(&kvm->slots_lock);
198c74f4
XG
4039 if (is_dirty)
4040 kvm_flush_remote_tlbs(kvm);
4041
79fac95e 4042 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX
4043 return r;
4044}
4045
aa2fbe6d
YZ
4046int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
4047 bool line_status)
23d43cf9
CD
4048{
4049 if (!irqchip_in_kernel(kvm))
4050 return -ENXIO;
4051
4052 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ
4053 irq_event->irq, irq_event->level,
4054 line_status);
23d43cf9
CD
4055 return 0;
4056}
4057
90de4a18
NA
4058static int kvm_vm_ioctl_enable_cap(struct kvm *kvm,
4059 struct kvm_enable_cap *cap)
4060{
4061 int r;
4062
4063 if (cap->flags)
4064 return -EINVAL;
4065
4066 switch (cap->cap) {
4067 case KVM_CAP_DISABLE_QUIRKS:
4068 kvm->arch.disabled_quirks = cap->args[0];
4069 r = 0;
4070 break;
49df6397
SR
4071 case KVM_CAP_SPLIT_IRQCHIP: {
4072 mutex_lock(&kvm->lock);
b053b2ae
SR
4073 r = -EINVAL;
4074 if (cap->args[0] > MAX_NR_RESERVED_IOAPIC_PINS)
4075 goto split_irqchip_unlock;
49df6397
SR
4076 r = -EEXIST;
4077 if (irqchip_in_kernel(kvm))
4078 goto split_irqchip_unlock;
557abc40 4079 if (kvm->created_vcpus)
49df6397
SR
4080 goto split_irqchip_unlock;
4081 r = kvm_setup_empty_irq_routing(kvm);
5c0aea0e 4082 if (r)
49df6397
SR
4083 goto split_irqchip_unlock;
4084 /* Pairs with irqchip_in_kernel. */
4085 smp_wmb();
49776faf 4086 kvm->arch.irqchip_mode = KVM_IRQCHIP_SPLIT;
b053b2ae 4087 kvm->arch.nr_reserved_ioapic_pins = cap->args[0];
49df6397
SR
4088 r = 0;
4089split_irqchip_unlock:
4090 mutex_unlock(&kvm->lock);
4091 break;
4092 }
37131313
RK
4093 case KVM_CAP_X2APIC_API:
4094 r = -EINVAL;
4095 if (cap->args[0] & ~KVM_X2APIC_API_VALID_FLAGS)
4096 break;
4097
4098 if (cap->args[0] & KVM_X2APIC_API_USE_32BIT_IDS)
4099 kvm->arch.x2apic_format = true;
c519265f
RK
4100 if (cap->args[0] & KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK)
4101 kvm->arch.x2apic_broadcast_quirk_disabled = true;
37131313
RK
4102
4103 r = 0;
4104 break;
90de4a18
NA
4105 default:
4106 r = -EINVAL;
4107 break;
4108 }
4109 return r;
4110}
4111
1fe779f8
CO
4112long kvm_arch_vm_ioctl(struct file *filp,
4113 unsigned int ioctl, unsigned long arg)
4114{
4115 struct kvm *kvm = filp->private_data;
4116 void __user *argp = (void __user *)arg;
367e1319 4117 int r = -ENOTTY;
f0d66275
DH
4118 /*
4119 * This union makes it completely explicit to gcc-3.x
4120 * that these two variables' stack usage should be
4121 * combined, not added together.
4122 */
4123 union {
4124 struct kvm_pit_state ps;
e9f42757 4125 struct kvm_pit_state2 ps2;
c5ff41ce 4126 struct kvm_pit_config pit_config;
f0d66275 4127 } u;
1fe779f8
CO
4128
4129 switch (ioctl) {
4130 case KVM_SET_TSS_ADDR:
4131 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 4132 break;
b927a3ce
SY
4133 case KVM_SET_IDENTITY_MAP_ADDR: {
4134 u64 ident_addr;
4135
1af1ac91
DH
4136 mutex_lock(&kvm->lock);
4137 r = -EINVAL;
4138 if (kvm->created_vcpus)
4139 goto set_identity_unlock;
b927a3ce
SY
4140 r = -EFAULT;
4141 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
1af1ac91 4142 goto set_identity_unlock;
b927a3ce 4143 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
1af1ac91
DH
4144set_identity_unlock:
4145 mutex_unlock(&kvm->lock);
b927a3ce
SY
4146 break;
4147 }
1fe779f8
CO
4148 case KVM_SET_NR_MMU_PAGES:
4149 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO
4150 break;
4151 case KVM_GET_NR_MMU_PAGES:
4152 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
4153 break;
3ddea128 4154 case KVM_CREATE_IRQCHIP: {
3ddea128 4155 mutex_lock(&kvm->lock);
09941366 4156
3ddea128 4157 r = -EEXIST;
35e6eaa3 4158 if (irqchip_in_kernel(kvm))
3ddea128 4159 goto create_irqchip_unlock;
09941366 4160
3e515705 4161 r = -EINVAL;
557abc40 4162 if (kvm->created_vcpus)
3e515705 4163 goto create_irqchip_unlock;
09941366
RK
4164
4165 r = kvm_pic_init(kvm);
4166 if (r)
3ddea128 4167 goto create_irqchip_unlock;
09941366
RK
4168
4169 r = kvm_ioapic_init(kvm);
4170 if (r) {
09941366 4171 kvm_pic_destroy(kvm);
3ddea128 4172 goto create_irqchip_unlock;
09941366
RK
4173 }
4174
399ec807
AK
4175 r = kvm_setup_default_irq_routing(kvm);
4176 if (r) {
72bb2fcd 4177 kvm_ioapic_destroy(kvm);
09941366 4178 kvm_pic_destroy(kvm);
71ba994c 4179 goto create_irqchip_unlock;
399ec807 4180 }
49776faf 4181 /* Write kvm->irq_routing before enabling irqchip_in_kernel. */
71ba994c 4182 smp_wmb();
49776faf 4183 kvm->arch.irqchip_mode = KVM_IRQCHIP_KERNEL;
3ddea128
MT
4184 create_irqchip_unlock:
4185 mutex_unlock(&kvm->lock);
1fe779f8 4186 break;
3ddea128 4187 }
7837699f 4188 case KVM_CREATE_PIT:
c5ff41ce
JK
4189 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
4190 goto create_pit;
4191 case KVM_CREATE_PIT2:
4192 r = -EFAULT;
4193 if (copy_from_user(&u.pit_config, argp,
4194 sizeof(struct kvm_pit_config)))
4195 goto out;
4196 create_pit:
250715a6 4197 mutex_lock(&kvm->lock);
269e05e4
AK
4198 r = -EEXIST;
4199 if (kvm->arch.vpit)
4200 goto create_pit_unlock;
7837699f 4201 r = -ENOMEM;
c5ff41ce 4202 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY
4203 if (kvm->arch.vpit)
4204 r = 0;
269e05e4 4205 create_pit_unlock:
250715a6 4206 mutex_unlock(&kvm->lock);
7837699f 4207 break;
1fe779f8
CO
4208 case KVM_GET_IRQCHIP: {
4209 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4210 struct kvm_irqchip *chip;
1fe779f8 4211
ff5c2c03
SL
4212 chip = memdup_user(argp, sizeof(*chip));
4213 if (IS_ERR(chip)) {
4214 r = PTR_ERR(chip);
1fe779f8 4215 goto out;
ff5c2c03
SL
4216 }
4217
1fe779f8 4218 r = -ENXIO;
826da321 4219 if (!irqchip_kernel(kvm))
f0d66275
DH
4220 goto get_irqchip_out;
4221 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 4222 if (r)
f0d66275 4223 goto get_irqchip_out;
1fe779f8 4224 r = -EFAULT;
f0d66275
DH
4225 if (copy_to_user(argp, chip, sizeof *chip))
4226 goto get_irqchip_out;
1fe779f8 4227 r = 0;
f0d66275
DH
4228 get_irqchip_out:
4229 kfree(chip);
1fe779f8
CO
4230 break;
4231 }
4232 case KVM_SET_IRQCHIP: {
4233 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 4234 struct kvm_irqchip *chip;
1fe779f8 4235
ff5c2c03
SL
4236 chip = memdup_user(argp, sizeof(*chip));
4237 if (IS_ERR(chip)) {
4238 r = PTR_ERR(chip);
1fe779f8 4239 goto out;
ff5c2c03
SL
4240 }
4241
1fe779f8 4242 r = -ENXIO;
826da321 4243 if (!irqchip_kernel(kvm))
f0d66275
DH
4244 goto set_irqchip_out;
4245 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 4246 if (r)
f0d66275 4247 goto set_irqchip_out;
1fe779f8 4248 r = 0;
f0d66275
DH
4249 set_irqchip_out:
4250 kfree(chip);
1fe779f8
CO
4251 break;
4252 }
e0f63cb9 4253 case KVM_GET_PIT: {
e0f63cb9 4254 r = -EFAULT;
f0d66275 4255 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY
4256 goto out;
4257 r = -ENXIO;
4258 if (!kvm->arch.vpit)
4259 goto out;
f0d66275 4260 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY
4261 if (r)
4262 goto out;
4263 r = -EFAULT;
f0d66275 4264 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY
4265 goto out;
4266 r = 0;
4267 break;
4268 }
4269 case KVM_SET_PIT: {
e0f63cb9 4270 r = -EFAULT;
f0d66275 4271 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY
4272 goto out;
4273 r = -ENXIO;
4274 if (!kvm->arch.vpit)
4275 goto out;
f0d66275 4276 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY
4277 break;
4278 }
e9f42757
BK
4279 case KVM_GET_PIT2: {
4280 r = -ENXIO;
4281 if (!kvm->arch.vpit)
4282 goto out;
4283 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
4284 if (r)
4285 goto out;
4286 r = -EFAULT;
4287 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
4288 goto out;
4289 r = 0;
4290 break;
4291 }
4292 case KVM_SET_PIT2: {
4293 r = -EFAULT;
4294 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
4295 goto out;
4296 r = -ENXIO;
4297 if (!kvm->arch.vpit)
4298 goto out;
4299 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK
4300 break;
4301 }
52d939a0
MT
4302 case KVM_REINJECT_CONTROL: {
4303 struct kvm_reinject_control control;
4304 r = -EFAULT;
4305 if (copy_from_user(&control, argp, sizeof(control)))
4306 goto out;
4307 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT
4308 break;
4309 }
d71ba788
PB
4310 case KVM_SET_BOOT_CPU_ID:
4311 r = 0;
4312 mutex_lock(&kvm->lock);
557abc40 4313 if (kvm->created_vcpus)
d71ba788
PB
4314 r = -EBUSY;
4315 else
4316 kvm->arch.bsp_vcpu_id = arg;
4317 mutex_unlock(&kvm->lock);
4318 break;
ffde22ac 4319 case KVM_XEN_HVM_CONFIG: {
df92b316 4320 struct kvm_xen_hvm_config xhc;
ffde22ac 4321 r = -EFAULT;
df92b316 4322 if (copy_from_user(&xhc, argp, sizeof(xhc)))
ffde22ac
ES
4323 goto out;
4324 r = -EINVAL;
df92b316 4325 if (xhc.flags)
ffde22ac 4326 goto out;
df92b316 4327 memcpy(&kvm->arch.xen_hvm_config, &xhc, sizeof(xhc));
ffde22ac
ES
4328 r = 0;
4329 break;
4330 }
afbcf7ab 4331 case KVM_SET_CLOCK: {
afbcf7ab
GC
4332 struct kvm_clock_data user_ns;
4333 u64 now_ns;
afbcf7ab
GC
4334
4335 r = -EFAULT;
4336 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
4337 goto out;
4338
4339 r = -EINVAL;
4340 if (user_ns.flags)
4341 goto out;
4342
4343 r = 0;
0bc48bea
RK
4344 /*
4345 * TODO: userspace has to take care of races with VCPU_RUN, so
4346 * kvm_gen_update_masterclock() can be cut down to locked
4347 * pvclock_update_vm_gtod_copy().
4348 */
4349 kvm_gen_update_masterclock(kvm);
e891a32e 4350 now_ns = get_kvmclock_ns(kvm);
108b249c 4351 kvm->arch.kvmclock_offset += user_ns.clock - now_ns;
0bc48bea 4352 kvm_make_all_cpus_request(kvm, KVM_REQ_CLOCK_UPDATE);
afbcf7ab
GC
4353 break;
4354 }
4355 case KVM_GET_CLOCK: {
afbcf7ab
GC
4356 struct kvm_clock_data user_ns;
4357 u64 now_ns;
4358
e891a32e 4359 now_ns = get_kvmclock_ns(kvm);
108b249c 4360 user_ns.clock = now_ns;
e3fd9a93 4361 user_ns.flags = kvm->arch.use_master_clock ? KVM_CLOCK_TSC_STABLE : 0;
97e69aa6 4362 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC
4363
4364 r = -EFAULT;
4365 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
4366 goto out;
4367 r = 0;
4368 break;
4369 }
90de4a18
NA
4370 case KVM_ENABLE_CAP: {
4371 struct kvm_enable_cap cap;
afbcf7ab 4372
90de4a18
NA
4373 r = -EFAULT;
4374 if (copy_from_user(&cap, argp, sizeof(cap)))
4375 goto out;
4376 r = kvm_vm_ioctl_enable_cap(kvm, &cap);
4377 break;
4378 }
1fe779f8 4379 default:
ad6260da 4380 r = -ENOTTY;
1fe779f8
CO
4381 }
4382out:
4383 return r;
4384}
4385
a16b043c 4386static void kvm_init_msr_list(void)
043405e1
CO
4387{
4388 u32 dummy[2];
4389 unsigned i, j;
4390
62ef68bb 4391 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO
4392 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
4393 continue;
93c4adc7
PB
4394
4395 /*
4396 * Even MSRs that are valid in the host may not be exposed
9dbe6cf9 4397 * to the guests in some cases.
93c4adc7
PB
4398 */
4399 switch (msrs_to_save[i]) {
4400 case MSR_IA32_BNDCFGS:
4401 if (!kvm_x86_ops->mpx_supported())
4402 continue;
4403 break;
9dbe6cf9
PB
4404 case MSR_TSC_AUX:
4405 if (!kvm_x86_ops->rdtscp_supported())
4406 continue;
4407 break;
93c4adc7
PB
4408 default:
4409 break;
4410 }
4411
043405e1
CO
4412 if (j < i)
4413 msrs_to_save[j] = msrs_to_save[i];
4414 j++;
4415 }
4416 num_msrs_to_save = j;
62ef68bb
PB
4417
4418 for (i = j = 0; i < ARRAY_SIZE(emulated_msrs); i++) {
4d5c8a07
TL
4419 if (!kvm_x86_ops->has_emulated_msr(emulated_msrs[i]))
4420 continue;
62ef68bb
PB
4421
4422 if (j < i)
4423 emulated_msrs[j] = emulated_msrs[i];
4424 j++;
4425 }
4426 num_emulated_msrs = j;
ab1bebf8
TL
4427
4428 for (i = j = 0; i < ARRAY_SIZE(msr_based_features); i++) {
4429 struct kvm_msr_entry msr;
4430
4431 msr.index = msr_based_features[i];
08215b9d 4432 if (kvm_get_msr_feature(&msr))
ab1bebf8
TL
4433 continue;
4434
4435 if (j < i)
4436 msr_based_features[j] = msr_based_features[i];
4437 j++;
4438 }
4439 num_msr_based_features = j;
043405e1
CO
4440}
4441
bda9020e
MT
4442static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
4443 const void *v)
bbd9b64e 4444{
70252a10
AK
4445 int handled = 0;
4446 int n;
4447
4448 do {
4449 n = min(len, 8);
bce87cce 4450 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN
4451 !kvm_iodevice_write(vcpu, &vcpu->arch.apic->dev, addr, n, v))
4452 && kvm_io_bus_write(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10
AK
4453 break;
4454 handled += n;
4455 addr += n;
4456 len -= n;
4457 v += n;
4458 } while (len);
bbd9b64e 4459
70252a10 4460 return handled;
bbd9b64e
CO
4461}
4462
bda9020e 4463static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 4464{
70252a10
AK
4465 int handled = 0;
4466 int n;
4467
4468 do {
4469 n = min(len, 8);
bce87cce 4470 if (!(lapic_in_kernel(vcpu) &&
e32edf4f
NN
4471 !kvm_iodevice_read(vcpu, &vcpu->arch.apic->dev,
4472 addr, n, v))
4473 && kvm_io_bus_read(vcpu, KVM_MMIO_BUS, addr, n, v))
70252a10 4474 break;
e39d200f 4475 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, v);
70252a10
AK
4476 handled += n;
4477 addr += n;
4478 len -= n;
4479 v += n;
4480 } while (len);
bbd9b64e 4481
70252a10 4482 return handled;
bbd9b64e
CO
4483}
4484
2dafc6c2
GN
4485static void kvm_set_segment(struct kvm_vcpu *vcpu,
4486 struct kvm_segment *var, int seg)
4487{
4488 kvm_x86_ops->set_segment(vcpu, var, seg);
4489}
4490
4491void kvm_get_segment(struct kvm_vcpu *vcpu,
4492 struct kvm_segment *var, int seg)
4493{
4494 kvm_x86_ops->get_segment(vcpu, var, seg);
4495}
4496
54987b7a
PB
4497gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
4498 struct x86_exception *exception)
02f59dc9
JR
4499{
4500 gpa_t t_gpa;
02f59dc9
JR
4501
4502 BUG_ON(!mmu_is_nested(vcpu));
4503
4504 /* NPT walks are always user-walks */
4505 access |= PFERR_USER_MASK;
54987b7a 4506 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, exception);
02f59dc9
JR
4507
4508 return t_gpa;
4509}
4510
ab9ae313
AK
4511gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
4512 struct x86_exception *exception)
1871c602
GN
4513{
4514 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 4515 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN
4516}
4517
ab9ae313
AK
4518 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
4519 struct x86_exception *exception)
1871c602
GN
4520{
4521 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4522 access |= PFERR_FETCH_MASK;
ab9ae313 4523 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN
4524}
4525
ab9ae313
AK
4526gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
4527 struct x86_exception *exception)
1871c602
GN
4528{
4529 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4530 access |= PFERR_WRITE_MASK;
ab9ae313 4531 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN
4532}
4533
4534/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK
4535gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4536 struct x86_exception *exception)
1871c602 4537{
ab9ae313 4538 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN
4539}
4540
4541static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4542 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4543 struct x86_exception *exception)
bbd9b64e
CO
4544{
4545 void *data = val;
10589a46 4546 int r = X86EMUL_CONTINUE;
bbd9b64e
CO
4547
4548 while (bytes) {
14dfe855 4549 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4550 exception);
bbd9b64e 4551 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4552 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO
4553 int ret;
4554
bcc55cba 4555 if (gpa == UNMAPPED_GVA)
ab9ae313 4556 return X86EMUL_PROPAGATE_FAULT;
54bf36aa
PB
4557 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, data,
4558 offset, toread);
10589a46 4559 if (ret < 0) {
c3cd7ffa 4560 r = X86EMUL_IO_NEEDED;
10589a46
MT
4561 goto out;
4562 }
bbd9b64e 4563
77c2002e
IE
4564 bytes -= toread;
4565 data += toread;
4566 addr += toread;
bbd9b64e 4567 }
10589a46 4568out:
10589a46 4569 return r;
bbd9b64e 4570}
77c2002e 4571
1871c602 4572/* used for instruction fetching */
0f65dd70
AK
4573static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4574 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4575 struct x86_exception *exception)
1871c602 4576{
0f65dd70 4577 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4578 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
44583cba
PB
4579 unsigned offset;
4580 int ret;
0f65dd70 4581
44583cba
PB
4582 /* Inline kvm_read_guest_virt_helper for speed. */
4583 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access|PFERR_FETCH_MASK,
4584 exception);
4585 if (unlikely(gpa == UNMAPPED_GVA))
4586 return X86EMUL_PROPAGATE_FAULT;
4587
4588 offset = addr & (PAGE_SIZE-1);
4589 if (WARN_ON(offset + bytes > PAGE_SIZE))
4590 bytes = (unsigned)PAGE_SIZE - offset;
54bf36aa
PB
4591 ret = kvm_vcpu_read_guest_page(vcpu, gpa >> PAGE_SHIFT, val,
4592 offset, bytes);
44583cba
PB
4593 if (unlikely(ret < 0))
4594 return X86EMUL_IO_NEEDED;
4595
4596 return X86EMUL_CONTINUE;
1871c602
GN
4597}
4598
064aea77 4599int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4600 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4601 struct x86_exception *exception)
1871c602 4602{
0f65dd70 4603 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4604 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4605
1871c602 4606 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4607 exception);
1871c602 4608}
064aea77 4609EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4610
0f65dd70
AK
4611static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4612 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4613 struct x86_exception *exception)
1871c602 4614{
0f65dd70 4615 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4616 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN
4617}
4618
7a036a6f
RK
4619static int kvm_read_guest_phys_system(struct x86_emulate_ctxt *ctxt,
4620 unsigned long addr, void *val, unsigned int bytes)
4621{
4622 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4623 int r = kvm_vcpu_read_guest(vcpu, addr, val, bytes);
4624
4625 return r < 0 ? X86EMUL_IO_NEEDED : X86EMUL_CONTINUE;
4626}
4627
6a4d7550 4628int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4629 gva_t addr, void *val,
2dafc6c2 4630 unsigned int bytes,
bcc55cba 4631 struct x86_exception *exception)
77c2002e 4632{
0f65dd70 4633 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE
4634 void *data = val;
4635 int r = X86EMUL_CONTINUE;
4636
f0ace387
PB
4637 /* kvm_write_guest_virt_system can pull in tons of pages. */
4638 vcpu->arch.l1tf_flush_l1d = true;
4639
77c2002e 4640 while (bytes) {
14dfe855
JR
4641 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4642 PFERR_WRITE_MASK,
ab9ae313 4643 exception);
77c2002e
IE
4644 unsigned offset = addr & (PAGE_SIZE-1);
4645 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4646 int ret;
4647
bcc55cba 4648 if (gpa == UNMAPPED_GVA)
ab9ae313 4649 return X86EMUL_PROPAGATE_FAULT;
54bf36aa 4650 ret = kvm_vcpu_write_guest(vcpu, gpa, data, towrite);
77c2002e 4651 if (ret < 0) {
c3cd7ffa 4652 r = X86EMUL_IO_NEEDED;
77c2002e
IE
4653 goto out;
4654 }
4655
4656 bytes -= towrite;
4657 data += towrite;
4658 addr += towrite;
4659 }
4660out:
4661 return r;
4662}
6a4d7550 4663EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4664
0f89b207
TL
4665static int vcpu_is_mmio_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4666 gpa_t gpa, bool write)
4667{
4668 /* For APIC access vmexit */
4669 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4670 return 1;
4671
4672 if (vcpu_match_mmio_gpa(vcpu, gpa)) {
4673 trace_vcpu_match_mmio(gva, gpa, write, true);
4674 return 1;
4675 }
4676
4677 return 0;
4678}
4679
af7cc7d1
XG
4680static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4681 gpa_t *gpa, struct x86_exception *exception,
4682 bool write)
4683{
97d64b78
AK
4684 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4685 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4686
be94f6b7
HH
4687 /*
4688 * currently PKRU is only applied to ept enabled guest so
4689 * there is no pkey in EPT page table for L1 guest or EPT
4690 * shadow page table for L2 guest.
4691 */
97d64b78 4692 if (vcpu_match_mmio_gva(vcpu, gva)
97ec8c06 4693 && !permission_fault(vcpu, vcpu->arch.walk_mmu,
be94f6b7 4694 vcpu->arch.access, 0, access)) {
bebb106a
XG
4695 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4696 (gva & (PAGE_SIZE - 1));
4f022648 4697 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG
4698 return 1;
4699 }
4700
af7cc7d1
XG
4701 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4702
4703 if (*gpa == UNMAPPED_GVA)
4704 return -1;
4705
0f89b207 4706 return vcpu_is_mmio_gpa(vcpu, gva, *gpa, write);
af7cc7d1
XG
4707}
4708
3200f405 4709int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4710 const void *val, int bytes)
bbd9b64e
CO
4711{
4712 int ret;
4713
54bf36aa 4714 ret = kvm_vcpu_write_guest(vcpu, gpa, val, bytes);
9f811285 4715 if (ret < 0)
bbd9b64e 4716 return 0;
0eb05bf2 4717 kvm_page_track_write(vcpu, gpa, val, bytes);
bbd9b64e
CO
4718 return 1;
4719}
4720
77d197b2
XG
4721struct read_write_emulator_ops {
4722 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4723 int bytes);
4724 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4725 void *val, int bytes);
4726 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4727 int bytes, void *val);
4728 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4729 void *val, int bytes);
4730 bool write;
4731};
4732
4733static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4734{
4735 if (vcpu->mmio_read_completed) {
77d197b2 4736 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
e39d200f 4737 vcpu->mmio_fragments[0].gpa, val);
77d197b2
XG
4738 vcpu->mmio_read_completed = 0;
4739 return 1;
4740 }
4741
4742 return 0;
4743}
4744
4745static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4746 void *val, int bytes)
4747{
54bf36aa 4748 return !kvm_vcpu_read_guest(vcpu, gpa, val, bytes);
77d197b2
XG
4749}
4750
4751static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4752 void *val, int bytes)
4753{
4754 return emulator_write_phys(vcpu, gpa, val, bytes);
4755}
4756
4757static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4758{
e39d200f 4759 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, val);
77d197b2
XG
4760 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4761}
4762
4763static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4764 void *val, int bytes)
4765{
e39d200f 4766 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, NULL);
77d197b2
XG
4767 return X86EMUL_IO_NEEDED;
4768}
4769
4770static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4771 void *val, int bytes)
4772{
f78146b0
AK
4773 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4774
87da7e66 4775 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG
4776 return X86EMUL_CONTINUE;
4777}
4778
0fbe9b0b 4779static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG
4780 .read_write_prepare = read_prepare,
4781 .read_write_emulate = read_emulate,
4782 .read_write_mmio = vcpu_mmio_read,
4783 .read_write_exit_mmio = read_exit_mmio,
4784};
4785
0fbe9b0b 4786static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG
4787 .read_write_emulate = write_emulate,
4788 .read_write_mmio = write_mmio,
4789 .read_write_exit_mmio = write_exit_mmio,
4790 .write = true,
4791};
4792
22388a3c
XG
4793static int emulator_read_write_onepage(unsigned long addr, void *val,
4794 unsigned int bytes,
4795 struct x86_exception *exception,
4796 struct kvm_vcpu *vcpu,
0fbe9b0b 4797 const struct read_write_emulator_ops *ops)
bbd9b64e 4798{
af7cc7d1
XG
4799 gpa_t gpa;
4800 int handled, ret;
22388a3c 4801 bool write = ops->write;
f78146b0 4802 struct kvm_mmio_fragment *frag;
0f89b207
TL
4803 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
4804
4805 /*
4806 * If the exit was due to a NPF we may already have a GPA.
4807 * If the GPA is present, use it to avoid the GVA to GPA table walk.
4808 * Note, this cannot be used on string operations since string
4809 * operation using rep will only have the initial GPA from the NPF
4810 * occurred.
4811 */
4812 if (vcpu->arch.gpa_available &&
4813 emulator_can_use_gpa(ctxt) &&
618232e2
BS
4814 (addr & ~PAGE_MASK) == (vcpu->arch.gpa_val & ~PAGE_MASK)) {
4815 gpa = vcpu->arch.gpa_val;
4816 ret = vcpu_is_mmio_gpa(vcpu, addr, gpa, write);
4817 } else {
4818 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
4819 if (ret < 0)
4820 return X86EMUL_PROPAGATE_FAULT;
0f89b207 4821 }
10589a46 4822
618232e2 4823 if (!ret && ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO
4824 return X86EMUL_CONTINUE;
4825
bbd9b64e
CO
4826 /*
4827 * Is this MMIO handled locally?
4828 */
22388a3c 4829 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4830 if (handled == bytes)
bbd9b64e 4831 return X86EMUL_CONTINUE;
bbd9b64e 4832
70252a10
AK
4833 gpa += handled;
4834 bytes -= handled;
4835 val += handled;
4836
87da7e66
XG
4837 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4838 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4839 frag->gpa = gpa;
4840 frag->data = val;
4841 frag->len = bytes;
f78146b0 4842 return X86EMUL_CONTINUE;
bbd9b64e
CO
4843}
4844
52eb5a6d
XL
4845static int emulator_read_write(struct x86_emulate_ctxt *ctxt,
4846 unsigned long addr,
22388a3c
XG
4847 void *val, unsigned int bytes,
4848 struct x86_exception *exception,
0fbe9b0b 4849 const struct read_write_emulator_ops *ops)
bbd9b64e 4850{
0f65dd70 4851 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK
4852 gpa_t gpa;
4853 int rc;
4854
4855 if (ops->read_write_prepare &&
4856 ops->read_write_prepare(vcpu, val, bytes))
4857 return X86EMUL_CONTINUE;
4858
4859 vcpu->mmio_nr_fragments = 0;
0f65dd70 4860
bbd9b64e
CO
4861 /* Crossing a page boundary? */
4862 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4863 int now;
bbd9b64e
CO
4864
4865 now = -addr & ~PAGE_MASK;
22388a3c
XG
4866 rc = emulator_read_write_onepage(addr, val, now, exception,
4867 vcpu, ops);
4868
bbd9b64e
CO
4869 if (rc != X86EMUL_CONTINUE)
4870 return rc;
4871 addr += now;
bac15531
NA
4872 if (ctxt->mode != X86EMUL_MODE_PROT64)
4873 addr = (u32)addr;
bbd9b64e
CO
4874 val += now;
4875 bytes -= now;
4876 }
22388a3c 4877
f78146b0
AK
4878 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4879 vcpu, ops);
4880 if (rc != X86EMUL_CONTINUE)
4881 return rc;
4882
4883 if (!vcpu->mmio_nr_fragments)
4884 return rc;
4885
4886 gpa = vcpu->mmio_fragments[0].gpa;
4887
4888 vcpu->mmio_needed = 1;
4889 vcpu->mmio_cur_fragment = 0;
4890
87da7e66 4891 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK
4892 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4893 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4894 vcpu->run->mmio.phys_addr = gpa;
4895
4896 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG
4897}
4898
4899static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4900 unsigned long addr,
4901 void *val,
4902 unsigned int bytes,
4903 struct x86_exception *exception)
4904{
4905 return emulator_read_write(ctxt, addr, val, bytes,
4906 exception, &read_emultor);
4907}
4908
52eb5a6d 4909static int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
22388a3c
XG
4910 unsigned long addr,
4911 const void *val,
4912 unsigned int bytes,
4913 struct x86_exception *exception)
4914{
4915 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4916 exception, &write_emultor);
bbd9b64e 4917}
bbd9b64e 4918
daea3e73
AK
4919#define CMPXCHG_TYPE(t, ptr, old, new) \
4920 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4921
4922#ifdef CONFIG_X86_64
4923# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4924#else
4925# define CMPXCHG64(ptr, old, new) \
9749a6c0 4926 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK
4927#endif
4928
0f65dd70
AK
4929static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4930 unsigned long addr,
bbd9b64e
CO
4931 const void *old,
4932 const void *new,
4933 unsigned int bytes,
0f65dd70 4934 struct x86_exception *exception)
bbd9b64e 4935{
0f65dd70 4936 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK
4937 gpa_t gpa;
4938 struct page *page;
4939 char *kaddr;
4940 bool exchanged;
2bacc55c 4941
daea3e73
AK
4942 /* guests cmpxchg8b have to be emulated atomically */
4943 if (bytes > 8 || (bytes & (bytes - 1)))
4944 goto emul_write;
10589a46 4945
daea3e73 4946 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4947
daea3e73
AK
4948 if (gpa == UNMAPPED_GVA ||
4949 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4950 goto emul_write;
2bacc55c 4951
daea3e73
AK
4952 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4953 goto emul_write;
72dc67a6 4954
54bf36aa 4955 page = kvm_vcpu_gfn_to_page(vcpu, gpa >> PAGE_SHIFT);
32cad84f 4956 if (is_error_page(page))
c19b8bd6 4957 goto emul_write;
72dc67a6 4958
8fd75e12 4959 kaddr = kmap_atomic(page);
daea3e73
AK
4960 kaddr += offset_in_page(gpa);
4961 switch (bytes) {
4962 case 1:
4963 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4964 break;
4965 case 2:
4966 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4967 break;
4968 case 4:
4969 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4970 break;
4971 case 8:
4972 exchanged = CMPXCHG64(kaddr, old, new);
4973 break;
4974 default:
4975 BUG();
2bacc55c 4976 }
8fd75e12 4977 kunmap_atomic(kaddr);
daea3e73
AK
4978 kvm_release_page_dirty(page);
4979
4980 if (!exchanged)
4981 return X86EMUL_CMPXCHG_FAILED;
4982
54bf36aa 4983 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
0eb05bf2 4984 kvm_page_track_write(vcpu, gpa, new, bytes);
8f6abd06
GN
4985
4986 return X86EMUL_CONTINUE;
4a5f48f6 4987
3200f405 4988emul_write:
daea3e73 4989 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4990
0f65dd70 4991 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO
4992}
4993
cf8f70bf
GN
4994static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4995{
cbfc6c91 4996 int r = 0, i;
cf8f70bf 4997
cbfc6c91
WL
4998 for (i = 0; i < vcpu->arch.pio.count; i++) {
4999 if (vcpu->arch.pio.in)
5000 r = kvm_io_bus_read(vcpu, KVM_PIO_BUS, vcpu->arch.pio.port,
5001 vcpu->arch.pio.size, pd);
5002 else
5003 r = kvm_io_bus_write(vcpu, KVM_PIO_BUS,
5004 vcpu->arch.pio.port, vcpu->arch.pio.size,
5005 pd);
5006 if (r)
5007 break;
5008 pd += vcpu->arch.pio.size;
5009 }
cf8f70bf
GN
5010 return r;
5011}
5012
6f6fbe98
XG
5013static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
5014 unsigned short port, void *val,
5015 unsigned int count, bool in)
cf8f70bf 5016{
cf8f70bf 5017 vcpu->arch.pio.port = port;
6f6fbe98 5018 vcpu->arch.pio.in = in;
7972995b 5019 vcpu->arch.pio.count = count;
cf8f70bf
GN
5020 vcpu->arch.pio.size = size;
5021
5022 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 5023 vcpu->arch.pio.count = 0;
cf8f70bf
GN
5024 return 1;
5025 }
5026
5027 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 5028 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN
5029 vcpu->run->io.size = size;
5030 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
5031 vcpu->run->io.count = count;
5032 vcpu->run->io.port = port;
5033
5034 return 0;
5035}
5036
6f6fbe98
XG
5037static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
5038 int size, unsigned short port, void *val,
5039 unsigned int count)
cf8f70bf 5040{
ca1d4a9e 5041 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 5042 int ret;
ca1d4a9e 5043
6f6fbe98
XG
5044 if (vcpu->arch.pio.count)
5045 goto data_avail;
cf8f70bf 5046
cbfc6c91
WL
5047 memset(vcpu->arch.pio_data, 0, size * count);
5048
6f6fbe98
XG
5049 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
5050 if (ret) {
5051data_avail:
5052 memcpy(val, vcpu->arch.pio_data, size * count);
1171903d 5053 trace_kvm_pio(KVM_PIO_IN, port, size, count, vcpu->arch.pio_data);
7972995b 5054 vcpu->arch.pio.count = 0;
cf8f70bf
GN
5055 return 1;
5056 }
5057
cf8f70bf
GN
5058 return 0;
5059}
5060
6f6fbe98
XG
5061static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
5062 int size, unsigned short port,
5063 const void *val, unsigned int count)
5064{
5065 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5066
5067 memcpy(vcpu->arch.pio_data, val, size * count);
1171903d 5068 trace_kvm_pio(KVM_PIO_OUT, port, size, count, vcpu->arch.pio_data);
6f6fbe98
XG
5069 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
5070}
5071
bbd9b64e
CO
5072static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
5073{
5074 return kvm_x86_ops->get_segment_base(vcpu, seg);
5075}
5076
3cb16fe7 5077static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 5078{
3cb16fe7 5079 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO
5080}
5081
ae6a2375 5082static int kvm_emulate_wbinvd_noskip(struct kvm_vcpu *vcpu)
f5f48ee1
SY
5083{
5084 if (!need_emulate_wbinvd(vcpu))
5085 return X86EMUL_CONTINUE;
5086
5087 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK
5088 int cpu = get_cpu();
5089
5090 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY
5091 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
5092 wbinvd_ipi, NULL, 1);
2eec7343 5093 put_cpu();
f5f48ee1 5094 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK
5095 } else
5096 wbinvd();
f5f48ee1
SY
5097 return X86EMUL_CONTINUE;
5098}
5cb56059
JS
5099
5100int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
5101{
6affcbed
KH
5102 kvm_emulate_wbinvd_noskip(vcpu);
5103 return kvm_skip_emulated_instruction(vcpu);
5cb56059 5104}
f5f48ee1
SY
5105EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
5106
5cb56059
JS
5107
5108
bcaf5cc5
AK
5109static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
5110{
5cb56059 5111 kvm_emulate_wbinvd_noskip(emul_to_vcpu(ctxt));
bcaf5cc5
AK
5112}
5113
52eb5a6d
XL
5114static int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr,
5115 unsigned long *dest)
bbd9b64e 5116{
16f8a6f9 5117 return kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO
5118}
5119
52eb5a6d
XL
5120static int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr,
5121 unsigned long value)
bbd9b64e 5122{
338dbc97 5123
717746e3 5124 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO
5125}
5126
52a46617 5127static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 5128{
52a46617 5129 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT
5130}
5131
717746e3 5132static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 5133{
717746e3 5134 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN
5135 unsigned long value;
5136
5137 switch (cr) {
5138 case 0:
5139 value = kvm_read_cr0(vcpu);
5140 break;
5141 case 2:
5142 value = vcpu->arch.cr2;
5143 break;
5144 case 3:
9f8fe504 5145 value = kvm_read_cr3(vcpu);
52a46617
GN
5146 break;
5147 case 4:
5148 value = kvm_read_cr4(vcpu);
5149 break;
5150 case 8:
5151 value = kvm_get_cr8(vcpu);
5152 break;
5153 default:
a737f256 5154 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN
5155 return 0;
5156 }
5157
5158 return value;
5159}
5160
717746e3 5161static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 5162{
717746e3 5163 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN
5164 int res = 0;
5165
52a46617
GN
5166 switch (cr) {
5167 case 0:
49a9b07e 5168 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN
5169 break;
5170 case 2:
5171 vcpu->arch.cr2 = val;
5172 break;
5173 case 3:
2390218b 5174 res = kvm_set_cr3(vcpu, val);
52a46617
GN
5175 break;
5176 case 4:
a83b29c6 5177 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN
5178 break;
5179 case 8:
eea1cff9 5180 res = kvm_set_cr8(vcpu, val);
52a46617
GN
5181 break;
5182 default:
a737f256 5183 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 5184 res = -1;
52a46617 5185 }
0f12244f
GN
5186
5187 return res;
52a46617
GN
5188}
5189
717746e3 5190static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 5191{
717746e3 5192 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN
5193}
5194
4bff1e86 5195static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 5196{
4bff1e86 5197 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN
5198}
5199
4bff1e86 5200static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 5201{
4bff1e86 5202 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG
5203}
5204
1ac9d0cf
AK
5205static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5206{
5207 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
5208}
5209
5210static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
5211{
5212 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
5213}
5214
4bff1e86
AK
5215static unsigned long emulator_get_cached_segment_base(
5216 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 5217{
4bff1e86 5218 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN
5219}
5220
1aa36616
AK
5221static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
5222 struct desc_struct *desc, u32 *base3,
5223 int seg)
2dafc6c2
GN
5224{
5225 struct kvm_segment var;
5226
4bff1e86 5227 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 5228 *selector = var.selector;
2dafc6c2 5229
378a8b09
GN
5230 if (var.unusable) {
5231 memset(desc, 0, sizeof(*desc));
f0367ee1
RK
5232 if (base3)
5233 *base3 = 0;
2dafc6c2 5234 return false;
378a8b09 5235 }
2dafc6c2
GN
5236
5237 if (var.g)
5238 var.limit >>= 12;
5239 set_desc_limit(desc, var.limit);
5240 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN
5241#ifdef CONFIG_X86_64
5242 if (base3)
5243 *base3 = var.base >> 32;
5244#endif
2dafc6c2
GN
5245 desc->type = var.type;
5246 desc->s = var.s;
5247 desc->dpl = var.dpl;
5248 desc->p = var.present;
5249 desc->avl = var.avl;
5250 desc->l = var.l;
5251 desc->d = var.db;
5252 desc->g = var.g;
5253
5254 return true;
5255}
5256
1aa36616
AK
5257static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
5258 struct desc_struct *desc, u32 base3,
5259 int seg)
2dafc6c2 5260{
4bff1e86 5261 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN
5262 struct kvm_segment var;
5263
1aa36616 5264 var.selector = selector;
2dafc6c2 5265 var.base = get_desc_base(desc);
5601d05b
GN
5266#ifdef CONFIG_X86_64
5267 var.base |= ((u64)base3) << 32;
5268#endif
2dafc6c2
GN
5269 var.limit = get_desc_limit(desc);
5270 if (desc->g)
5271 var.limit = (var.limit << 12) | 0xfff;
5272 var.type = desc->type;
2dafc6c2
GN
5273 var.dpl = desc->dpl;
5274 var.db = desc->d;
5275 var.s = desc->s;
5276 var.l = desc->l;
5277 var.g = desc->g;
5278 var.avl = desc->avl;
5279 var.present = desc->p;
5280 var.unusable = !var.present;
5281 var.padding = 0;
5282
5283 kvm_set_segment(vcpu, &var, seg);
5284 return;
5285}
5286
717746e3
AK
5287static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
5288 u32 msr_index, u64 *pdata)
5289{
609e36d3
PB
5290 struct msr_data msr;
5291 int r;
5292
5293 msr.index = msr_index;
5294 msr.host_initiated = false;
5295 r = kvm_get_msr(emul_to_vcpu(ctxt), &msr);
5296 if (r)
5297 return r;
5298
5299 *pdata = msr.data;
5300 return 0;
717746e3
AK
5301}
5302
5303static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
5304 u32 msr_index, u64 data)
5305{
8fe8ab46
WA
5306 struct msr_data msr;
5307
5308 msr.data = data;
5309 msr.index = msr_index;
5310 msr.host_initiated = false;
5311 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK
5312}
5313
64d60670
PB
5314static u64 emulator_get_smbase(struct x86_emulate_ctxt *ctxt)
5315{
5316 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5317
5318 return vcpu->arch.smbase;
5319}
5320
5321static void emulator_set_smbase(struct x86_emulate_ctxt *ctxt, u64 smbase)
5322{
5323 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5324
5325 vcpu->arch.smbase = smbase;
5326}
5327
67f4d428
NA
5328static int emulator_check_pmc(struct x86_emulate_ctxt *ctxt,
5329 u32 pmc)
5330{
c6702c9d 5331 return kvm_pmu_is_valid_msr_idx(emul_to_vcpu(ctxt), pmc);
67f4d428
NA
5332}
5333
222d21aa
AK
5334static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
5335 u32 pmc, u64 *pdata)
5336{
c6702c9d 5337 return kvm_pmu_rdpmc(emul_to_vcpu(ctxt), pmc, pdata);
222d21aa
AK
5338}
5339
6c3287f7
AK
5340static void emulator_halt(struct x86_emulate_ctxt *ctxt)
5341{
5342 emul_to_vcpu(ctxt)->arch.halt_request = 1;
5343}
5344
2953538e 5345static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 5346 struct x86_instruction_info *info,
c4f035c6
AK
5347 enum x86_intercept_stage stage)
5348{
2953538e 5349 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK
5350}
5351
e911eb3b
YZ
5352static bool emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
5353 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx, bool check_limit)
bdb42f5a 5354{
e911eb3b 5355 return kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx, check_limit);
bdb42f5a
SB
5356}
5357
dd856efa
AK
5358static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
5359{
5360 return kvm_register_read(emul_to_vcpu(ctxt), reg);
5361}
5362
5363static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
5364{
5365 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
5366}
5367
801806d9
NA
5368static void emulator_set_nmi_mask(struct x86_emulate_ctxt *ctxt, bool masked)
5369{
5370 kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
5371}
5372
6ed071f0
LP
5373static unsigned emulator_get_hflags(struct x86_emulate_ctxt *ctxt)
5374{
5375 return emul_to_vcpu(ctxt)->arch.hflags;
5376}
5377
5378static void emulator_set_hflags(struct x86_emulate_ctxt *ctxt, unsigned emul_flags)
5379{
5380 kvm_set_hflags(emul_to_vcpu(ctxt), emul_flags);
5381}
5382
0234bf88
LP
5383static int emulator_pre_leave_smm(struct x86_emulate_ctxt *ctxt, u64 smbase)
5384{
5385 return kvm_x86_ops->pre_leave_smm(emul_to_vcpu(ctxt), smbase);
5386}
5387
0225fb50 5388static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK
5389 .read_gpr = emulator_read_gpr,
5390 .write_gpr = emulator_write_gpr,
1871c602 5391 .read_std = kvm_read_guest_virt_system,
2dafc6c2 5392 .write_std = kvm_write_guest_virt_system,
7a036a6f 5393 .read_phys = kvm_read_guest_phys_system,
1871c602 5394 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO
5395 .read_emulated = emulator_read_emulated,
5396 .write_emulated = emulator_write_emulated,
5397 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 5398 .invlpg = emulator_invlpg,
cf8f70bf
GN
5399 .pio_in_emulated = emulator_pio_in_emulated,
5400 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK
5401 .get_segment = emulator_get_segment,
5402 .set_segment = emulator_set_segment,
5951c442 5403 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 5404 .get_gdt = emulator_get_gdt,
160ce1f1 5405 .get_idt = emulator_get_idt,
1ac9d0cf
AK
5406 .set_gdt = emulator_set_gdt,
5407 .set_idt = emulator_set_idt,
52a46617
GN
5408 .get_cr = emulator_get_cr,
5409 .set_cr = emulator_set_cr,
9c537244 5410 .cpl = emulator_get_cpl,
35aa5375
GN
5411 .get_dr = emulator_get_dr,
5412 .set_dr = emulator_set_dr,
64d60670
PB
5413 .get_smbase = emulator_get_smbase,
5414 .set_smbase = emulator_set_smbase,
717746e3
AK
5415 .set_msr = emulator_set_msr,
5416 .get_msr = emulator_get_msr,
67f4d428 5417 .check_pmc = emulator_check_pmc,
222d21aa 5418 .read_pmc = emulator_read_pmc,
6c3287f7 5419 .halt = emulator_halt,
bcaf5cc5 5420 .wbinvd = emulator_wbinvd,
d6aa1000 5421 .fix_hypercall = emulator_fix_hypercall,
c4f035c6 5422 .intercept = emulator_intercept,
bdb42f5a 5423 .get_cpuid = emulator_get_cpuid,
801806d9 5424 .set_nmi_mask = emulator_set_nmi_mask,
6ed071f0
LP
5425 .get_hflags = emulator_get_hflags,
5426 .set_hflags = emulator_set_hflags,
0234bf88 5427 .pre_leave_smm = emulator_pre_leave_smm,
bbd9b64e
CO
5428};
5429
95cb2295
GN
5430static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
5431{
37ccdcbe 5432 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu);
95cb2295
GN
5433 /*
5434 * an sti; sti; sequence only disable interrupts for the first
5435 * instruction. So, if the last instruction, be it emulated or
5436 * not, left the system with the INT_STI flag enabled, it
5437 * means that the last instruction is an sti. We should not
5438 * leave the flag on in this case. The same goes for mov ss
5439 */
37ccdcbe
PB
5440 if (int_shadow & mask)
5441 mask = 0;
6addfc42 5442 if (unlikely(int_shadow || mask)) {
95cb2295 5443 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
6addfc42
PB
5444 if (!mask)
5445 kvm_make_request(KVM_REQ_EVENT, vcpu);
5446 }
95cb2295
GN
5447}
5448
ef54bcfe 5449static bool inject_emulated_exception(struct kvm_vcpu *vcpu)
54b8486f
GN
5450{
5451 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 5452 if (ctxt->exception.vector == PF_VECTOR)
ef54bcfe
PB
5453 return kvm_propagate_fault(vcpu, &ctxt->exception);
5454
5455 if (ctxt->exception.error_code_valid)
da9cb575
AK
5456 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
5457 ctxt->exception.error_code);
54b8486f 5458 else
da9cb575 5459 kvm_queue_exception(vcpu, ctxt->exception.vector);
ef54bcfe 5460 return false;
54b8486f
GN
5461}
5462
8ec4722d
MG
5463static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
5464{
adf52235 5465 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG
5466 int cs_db, cs_l;
5467
8ec4722d
MG
5468 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5469
adf52235 5470 ctxt->eflags = kvm_get_rflags(vcpu);
c8401dda
PB
5471 ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
5472
adf52235
TY
5473 ctxt->eip = kvm_rip_read(vcpu);
5474 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
5475 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
42bf549f 5476 (cs_l && is_long_mode(vcpu)) ? X86EMUL_MODE_PROT64 :
adf52235
TY
5477 cs_db ? X86EMUL_MODE_PROT32 :
5478 X86EMUL_MODE_PROT16;
a584539b 5479 BUILD_BUG_ON(HF_GUEST_MASK != X86EMUL_GUEST_MASK);
64d60670
PB
5480 BUILD_BUG_ON(HF_SMM_MASK != X86EMUL_SMM_MASK);
5481 BUILD_BUG_ON(HF_SMM_INSIDE_NMI_MASK != X86EMUL_SMM_INSIDE_NMI_MASK);
adf52235 5482
dd856efa 5483 init_decode_cache(ctxt);
7ae441ea 5484 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG
5485}
5486
71f9833b 5487int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 5488{
9d74191a 5489 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG
5490 int ret;
5491
5492 init_emulate_ctxt(vcpu);
5493
9dac77fa
AK
5494 ctxt->op_bytes = 2;
5495 ctxt->ad_bytes = 2;
5496 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 5497 ret = emulate_int_real(ctxt, irq);
63995653
MG
5498
5499 if (ret != X86EMUL_CONTINUE)
5500 return EMULATE_FAIL;
5501
9dac77fa 5502 ctxt->eip = ctxt->_eip;
9d74191a
TY
5503 kvm_rip_write(vcpu, ctxt->eip);
5504 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG
5505
5506 if (irq == NMI_VECTOR)
7460fb4a 5507 vcpu->arch.nmi_pending = 0;
63995653
MG
5508 else
5509 vcpu->arch.interrupt.pending = false;
5510
5511 return EMULATE_DONE;
5512}
5513EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
5514
6d77dbfc
GN
5515static int handle_emulation_failure(struct kvm_vcpu *vcpu)
5516{
fc3a9157
JR
5517 int r = EMULATE_DONE;
5518
6d77dbfc
GN
5519 ++vcpu->stat.insn_emulation_fail;
5520 trace_kvm_emulate_insn_failed(vcpu);
a2b9e6c1 5521 if (!is_guest_mode(vcpu) && kvm_x86_ops->get_cpl(vcpu) == 0) {
fc3a9157
JR
5522 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5523 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5524 vcpu->run->internal.ndata = 0;
1f4dcb3b 5525 r = EMULATE_USER_EXIT;
fc3a9157 5526 }
6d77dbfc 5527 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR
5528
5529 return r;
6d77dbfc
GN
5530}
5531
93c05d3e 5532static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN
5533 bool write_fault_to_shadow_pgtable,
5534 int emulation_type)
a6f177ef 5535{
95b3cf69 5536 gpa_t gpa = cr2;
ba049e93 5537 kvm_pfn_t pfn;
a6f177ef 5538
991eebf9
GN
5539 if (emulation_type & EMULTYPE_NO_REEXECUTE)
5540 return false;
5541
95b3cf69
XG
5542 if (!vcpu->arch.mmu.direct_map) {
5543 /*
5544 * Write permission should be allowed since only
5545 * write access need to be emulated.
5546 */
5547 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 5548
95b3cf69
XG
5549 /*
5550 * If the mapping is invalid in guest, let cpu retry
5551 * it to generate fault.
5552 */
5553 if (gpa == UNMAPPED_GVA)
5554 return true;
5555 }
a6f177ef 5556
8e3d9d06
XG
5557 /*
5558 * Do not retry the unhandleable instruction if it faults on the
5559 * readonly host memory, otherwise it will goto a infinite loop:
5560 * retry instruction -> write #PF -> emulation fail -> retry
5561 * instruction -> ...
5562 */
5563 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG
5564
5565 /*
5566 * If the instruction failed on the error pfn, it can not be fixed,
5567 * report the error to userspace.
5568 */
5569 if (is_error_noslot_pfn(pfn))
5570 return false;
5571
5572 kvm_release_pfn_clean(pfn);
5573
5574 /* The instructions are well-emulated on direct mmu. */
5575 if (vcpu->arch.mmu.direct_map) {
5576 unsigned int indirect_shadow_pages;
5577
5578 spin_lock(&vcpu->kvm->mmu_lock);
5579 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
5580 spin_unlock(&vcpu->kvm->mmu_lock);
5581
5582 if (indirect_shadow_pages)
5583 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
5584
a6f177ef 5585 return true;
8e3d9d06 5586 }
a6f177ef 5587
95b3cf69
XG
5588 /*
5589 * if emulation was due to access to shadowed page table
5590 * and it failed try to unshadow page and re-enter the
5591 * guest to let CPU execute the instruction.
5592 */
5593 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG
5594
5595 /*
5596 * If the access faults on its page table, it can not
5597 * be fixed by unprotecting shadow page and it should
5598 * be reported to userspace.
5599 */
5600 return !write_fault_to_shadow_pgtable;
a6f177ef
GN
5601}
5602
1cb3f3ae
XG
5603static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
5604 unsigned long cr2, int emulation_type)
5605{
5606 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
5607 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
5608
5609 last_retry_eip = vcpu->arch.last_retry_eip;
5610 last_retry_addr = vcpu->arch.last_retry_addr;
5611
5612 /*
5613 * If the emulation is caused by #PF and it is non-page_table
5614 * writing instruction, it means the VM-EXIT is caused by shadow
5615 * page protected, we can zap the shadow page and retry this
5616 * instruction directly.
5617 *
5618 * Note: if the guest uses a non-page-table modifying instruction
5619 * on the PDE that points to the instruction, then we will unmap
5620 * the instruction and go to an infinite loop. So, we cache the
5621 * last retried eip and the last fault address, if we meet the eip
5622 * and the address again, we can break out of the potential infinite
5623 * loop.
5624 */
5625 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
5626
5627 if (!(emulation_type & EMULTYPE_RETRY))
5628 return false;
5629
5630 if (x86_page_table_writing_insn(ctxt))
5631 return false;
5632
5633 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5634 return false;
5635
5636 vcpu->arch.last_retry_eip = ctxt->eip;
5637 vcpu->arch.last_retry_addr = cr2;
5638
5639 if (!vcpu->arch.mmu.direct_map)
5640 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5641
22368028 5642 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG
5643
5644 return true;
5645}
5646
716d51ab
GN
5647static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5648static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5649
64d60670 5650static void kvm_smm_changed(struct kvm_vcpu *vcpu)
a584539b 5651{
64d60670 5652 if (!(vcpu->arch.hflags & HF_SMM_MASK)) {
660a5d51
PB
5653 /* This is a good place to trace that we are exiting SMM. */
5654 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, false);
5655
c43203ca
PB
5656 /* Process a latched INIT or SMI, if any. */
5657 kvm_make_request(KVM_REQ_EVENT, vcpu);
64d60670 5658 }
699023e2
PB
5659
5660 kvm_mmu_reset_context(vcpu);
64d60670
PB
5661}
5662
5663static void kvm_set_hflags(struct kvm_vcpu *vcpu, unsigned emul_flags)
5664{
5665 unsigned changed = vcpu->arch.hflags ^ emul_flags;
5666
a584539b 5667 vcpu->arch.hflags = emul_flags;
64d60670
PB
5668
5669 if (changed & HF_SMM_MASK)
5670 kvm_smm_changed(vcpu);
a584539b
PB
5671}
5672
4a1e10d5
PB
5673static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5674 unsigned long *db)
5675{
5676 u32 dr6 = 0;
5677 int i;
5678 u32 enable, rwlen;
5679
5680 enable = dr7;
5681 rwlen = dr7 >> 16;
5682 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5683 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5684 dr6 |= (1 << i);
5685 return dr6;
5686}
5687
c8401dda 5688static void kvm_vcpu_do_singlestep(struct kvm_vcpu *vcpu, int *r)
663f4c61
PB
5689{
5690 struct kvm_run *kvm_run = vcpu->run;
5691
c8401dda
PB
5692 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5693 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1 | DR6_RTM;
5694 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5695 kvm_run->debug.arch.exception = DB_VECTOR;
5696 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5697 *r = EMULATE_USER_EXIT;
5698 } else {
5699 /*
5700 * "Certain debug exceptions may clear bit 0-3. The
5701 * remaining contents of the DR6 register are never
5702 * cleared by the processor".
5703 */
5704 vcpu->arch.dr6 &= ~15;
5705 vcpu->arch.dr6 |= DR6_BS | DR6_RTM;
5706 kvm_queue_exception(vcpu, DB_VECTOR);
663f4c61
PB
5707 }
5708}
5709
6affcbed
KH
5710int kvm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
5711{
5712 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5713 int r = EMULATE_DONE;
5714
5715 kvm_x86_ops->skip_emulated_instruction(vcpu);
c8401dda
PB
5716
5717 /*
5718 * rflags is the old, "raw" value of the flags. The new value has
5719 * not been saved yet.
5720 *
5721 * This is correct even for TF set by the guest, because "the
5722 * processor will not generate this exception after the instruction
5723 * that sets the TF flag".
5724 */
5725 if (unlikely(rflags & X86_EFLAGS_TF))
5726 kvm_vcpu_do_singlestep(vcpu, &r);
6affcbed
KH
5727 return r == EMULATE_DONE;
5728}
5729EXPORT_SYMBOL_GPL(kvm_skip_emulated_instruction);
5730
4a1e10d5
PB
5731static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5732{
4a1e10d5
PB
5733 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5734 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
82b32774
NA
5735 struct kvm_run *kvm_run = vcpu->run;
5736 unsigned long eip = kvm_get_linear_rip(vcpu);
5737 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB
5738 vcpu->arch.guest_debug_dr7,
5739 vcpu->arch.eff_db);
5740
5741 if (dr6 != 0) {
6f43ed01 5742 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1 | DR6_RTM;
82b32774 5743 kvm_run->debug.arch.pc = eip;
4a1e10d5
PB
5744 kvm_run->debug.arch.exception = DB_VECTOR;
5745 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5746 *r = EMULATE_USER_EXIT;
5747 return true;
5748 }
5749 }
5750
4161a569
NA
5751 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK) &&
5752 !(kvm_get_rflags(vcpu) & X86_EFLAGS_RF)) {
82b32774
NA
5753 unsigned long eip = kvm_get_linear_rip(vcpu);
5754 u32 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
4a1e10d5
PB
5755 vcpu->arch.dr7,
5756 vcpu->arch.db);
5757
5758 if (dr6 != 0) {
5759 vcpu->arch.dr6 &= ~15;
6f43ed01 5760 vcpu->arch.dr6 |= dr6 | DR6_RTM;
4a1e10d5
PB
5761 kvm_queue_exception(vcpu, DB_VECTOR);
5762 *r = EMULATE_DONE;
5763 return true;
5764 }
5765 }
5766
5767 return false;
5768}
5769
51d8b661
AP
5770int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5771 unsigned long cr2,
dc25e89e
AP
5772 int emulation_type,
5773 void *insn,
5774 int insn_len)
bbd9b64e 5775{
95cb2295 5776 int r;
9d74191a 5777 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5778 bool writeback = true;
93c05d3e 5779 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5780
f0ace387
PB
5781 vcpu->arch.l1tf_flush_l1d = true;
5782
93c05d3e
XG
5783 /*
5784 * Clear write_fault_to_shadow_pgtable here to ensure it is
5785 * never reused.
5786 */
5787 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5788 kvm_clear_exception_queue(vcpu);
8d7d8102 5789
571008da 5790 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5791 init_emulate_ctxt(vcpu);
4a1e10d5
PB
5792
5793 /*
5794 * We will reenter on the same instruction since
5795 * we do not set complete_userspace_io. This does not
5796 * handle watchpoints yet, those would be handled in
5797 * the emulate_ops.
5798 */
60165b0a
VK
5799 if (!(emulation_type & EMULTYPE_SKIP) &&
5800 kvm_vcpu_check_breakpoint(vcpu, &r))
4a1e10d5
PB
5801 return r;
5802
9d74191a
TY
5803 ctxt->interruptibility = 0;
5804 ctxt->have_exception = false;
e0ad0b47 5805 ctxt->exception.vector = -1;
9d74191a 5806 ctxt->perm_ok = false;
bbd9b64e 5807
b51e974f 5808 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5809
9d74191a 5810 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5811
e46479f8 5812 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5813 ++vcpu->stat.insn_emulation;
1d2887e2 5814 if (r != EMULATION_OK) {
4005996e
AK
5815 if (emulation_type & EMULTYPE_TRAP_UD)
5816 return EMULATE_FAIL;
991eebf9
GN
5817 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5818 emulation_type))
bbd9b64e 5819 return EMULATE_DONE;
6ea6e843
PB
5820 if (ctxt->have_exception && inject_emulated_exception(vcpu))
5821 return EMULATE_DONE;
6d77dbfc
GN
5822 if (emulation_type & EMULTYPE_SKIP)
5823 return EMULATE_FAIL;
5824 return handle_emulation_failure(vcpu);
bbd9b64e
CO
5825 }
5826 }
5827
ba8afb6b 5828 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5829 kvm_rip_write(vcpu, ctxt->_eip);
bb663c7a
NA
5830 if (ctxt->eflags & X86_EFLAGS_RF)
5831 kvm_set_rflags(vcpu, ctxt->eflags & ~X86_EFLAGS_RF);
ba8afb6b
GN
5832 return EMULATE_DONE;
5833 }
5834
1cb3f3ae
XG
5835 if (retry_instruction(ctxt, cr2, emulation_type))
5836 return EMULATE_DONE;
5837
7ae441ea 5838 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5839 changes registers values during IO operation */
7ae441ea
GN
5840 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5841 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5842 emulator_invalidate_register_cache(ctxt);
7ae441ea 5843 }
4d2179e1 5844
5cd21917 5845restart:
0f89b207
TL
5846 /* Save the faulting GPA (cr2) in the address field */
5847 ctxt->exception.address = cr2;
5848
9d74191a 5849 r = x86_emulate_insn(ctxt);
bbd9b64e 5850
775fde86
JR
5851 if (r == EMULATION_INTERCEPTED)
5852 return EMULATE_DONE;
5853
d2ddd1c4 5854 if (r == EMULATION_FAILED) {
991eebf9
GN
5855 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5856 emulation_type))
c3cd7ffa
GN
5857 return EMULATE_DONE;
5858
6d77dbfc 5859 return handle_emulation_failure(vcpu);
bbd9b64e
CO
5860 }
5861
9d74191a 5862 if (ctxt->have_exception) {
d2ddd1c4 5863 r = EMULATE_DONE;
ef54bcfe
PB
5864 if (inject_emulated_exception(vcpu))
5865 return r;
d2ddd1c4 5866 } else if (vcpu->arch.pio.count) {
0912c977
PB
5867 if (!vcpu->arch.pio.in) {
5868 /* FIXME: return into emulator if single-stepping. */
3457e419 5869 vcpu->arch.pio.count = 0;
0912c977 5870 } else {
7ae441ea 5871 writeback = false;
716d51ab
GN
5872 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5873 }
ac0a48c3 5874 r = EMULATE_USER_EXIT;
7ae441ea
GN
5875 } else if (vcpu->mmio_needed) {
5876 if (!vcpu->mmio_is_write)
5877 writeback = false;
ac0a48c3 5878 r = EMULATE_USER_EXIT;
716d51ab 5879 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5880 } else if (r == EMULATION_RESTART)
5cd21917 5881 goto restart;
d2ddd1c4
GN
5882 else
5883 r = EMULATE_DONE;
f850e2e6 5884
7ae441ea 5885 if (writeback) {
6addfc42 5886 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
9d74191a 5887 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5888 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5889 kvm_rip_write(vcpu, ctxt->eip);
c8401dda
PB
5890 if (r == EMULATE_DONE &&
5891 (ctxt->tf || (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)))
5892 kvm_vcpu_do_singlestep(vcpu, &r);
38827dbd
NA
5893 if (!ctxt->have_exception ||
5894 exception_type(ctxt->exception.vector) == EXCPT_TRAP)
5895 __kvm_set_rflags(vcpu, ctxt->eflags);
6addfc42
PB
5896
5897 /*
5898 * For STI, interrupts are shadowed; so KVM_REQ_EVENT will
5899 * do nothing, and it will be requested again as soon as
5900 * the shadow expires. But we still need to check here,
5901 * because POPF has no interrupt shadow.
5902 */
5903 if (unlikely((ctxt->eflags & ~rflags) & X86_EFLAGS_IF))
5904 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea
GN
5905 } else
5906 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN
5907
5908 return r;
de7d789a 5909}
51d8b661 5910EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5911
cf8f70bf 5912int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5913{
cf8f70bf 5914 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK
5915 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5916 size, port, &val, 1);
cf8f70bf 5917 /* do not return to emulator after return from userspace */
7972995b 5918 vcpu->arch.pio.count = 0;
de7d789a
CO
5919 return ret;
5920}
cf8f70bf 5921EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5922
8370c3d0
TL
5923static int complete_fast_pio_in(struct kvm_vcpu *vcpu)
5924{
5925 unsigned long val;
5926
5927 /* We should only ever be called with arch.pio.count equal to 1 */
5928 BUG_ON(vcpu->arch.pio.count != 1);
5929
5930 /* For size less than 4 we merge, else we zero extend */
5931 val = (vcpu->arch.pio.size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX)
5932 : 0;
5933
5934 /*
5935 * Since vcpu->arch.pio.count == 1 let emulator_pio_in_emulated perform
5936 * the copy and tracing
5937 */
5938 emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, vcpu->arch.pio.size,
5939 vcpu->arch.pio.port, &val, 1);
5940 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5941
5942 return 1;
5943}
5944
5945int kvm_fast_pio_in(struct kvm_vcpu *vcpu, int size, unsigned short port)
5946{
5947 unsigned long val;
5948 int ret;
5949
5950 /* For size less than 4 we merge, else we zero extend */
5951 val = (size < 4) ? kvm_register_read(vcpu, VCPU_REGS_RAX) : 0;
5952
5953 ret = emulator_pio_in_emulated(&vcpu->arch.emulate_ctxt, size, port,
5954 &val, 1);
5955 if (ret) {
5956 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
5957 return ret;
5958 }
5959
5960 vcpu->arch.complete_userspace_io = complete_fast_pio_in;
5961
5962 return 0;
5963}
5964EXPORT_SYMBOL_GPL(kvm_fast_pio_in);
5965
251a5fd6 5966static int kvmclock_cpu_down_prep(unsigned int cpu)
8cfdc000 5967{
0a3aee0d 5968 __this_cpu_write(cpu_tsc_khz, 0);
251a5fd6 5969 return 0;
8cfdc000
ZA
5970}
5971
5972static void tsc_khz_changed(void *data)
c8076604 5973{
8cfdc000
ZA
5974 struct cpufreq_freqs *freq = data;
5975 unsigned long khz = 0;
5976
5977 if (data)
5978 khz = freq->new;
5979 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5980 khz = cpufreq_quick_get(raw_smp_processor_id());
5981 if (!khz)
5982 khz = tsc_khz;
0a3aee0d 5983 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH
5984}
5985
c8076604
GH
5986static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5987 void *data)
5988{
5989 struct cpufreq_freqs *freq = data;
5990 struct kvm *kvm;
5991 struct kvm_vcpu *vcpu;
5992 int i, send_ipi = 0;
5993
8cfdc000
ZA
5994 /*
5995 * We allow guests to temporarily run on slowing clocks,
5996 * provided we notify them after, or to run on accelerating
5997 * clocks, provided we notify them before. Thus time never
5998 * goes backwards.
5999 *
6000 * However, we have a problem. We can't atomically update
6001 * the frequency of a given CPU from this function; it is
6002 * merely a notifier, which can be called from any CPU.
6003 * Changing the TSC frequency at arbitrary points in time
6004 * requires a recomputation of local variables related to
6005 * the TSC for each VCPU. We must flag these local variables
6006 * to be updated and be sure the update takes place with the
6007 * new frequency before any guests proceed.
6008 *
6009 * Unfortunately, the combination of hotplug CPU and frequency
6010 * change creates an intractable locking scenario; the order
6011 * of when these callouts happen is undefined with respect to
6012 * CPU hotplug, and they can race with each other. As such,
6013 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
6014 * undefined; you can actually have a CPU frequency change take
6015 * place in between the computation of X and the setting of the
6016 * variable. To protect against this problem, all updates of
6017 * the per_cpu tsc_khz variable are done in an interrupt
6018 * protected IPI, and all callers wishing to update the value
6019 * must wait for a synchronous IPI to complete (which is trivial
6020 * if the caller is on the CPU already). This establishes the
6021 * necessary total order on variable updates.
6022 *
6023 * Note that because a guest time update may take place
6024 * anytime after the setting of the VCPU's request bit, the
6025 * correct TSC value must be set before the request. However,
6026 * to ensure the update actually makes it to any guest which
6027 * starts running in hardware virtualization between the set
6028 * and the acquisition of the spinlock, we must also ping the
6029 * CPU after setting the request bit.
6030 *
6031 */
6032
c8076604
GH
6033 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
6034 return 0;
6035 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
6036 return 0;
8cfdc000
ZA
6037
6038 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 6039
2f303b74 6040 spin_lock(&kvm_lock);
c8076604 6041 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 6042 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH
6043 if (vcpu->cpu != freq->cpu)
6044 continue;
c285545f 6045 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 6046 if (vcpu->cpu != smp_processor_id())
8cfdc000 6047 send_ipi = 1;
c8076604
GH
6048 }
6049 }
2f303b74 6050 spin_unlock(&kvm_lock);
c8076604
GH
6051
6052 if (freq->old < freq->new && send_ipi) {
6053 /*
6054 * We upscale the frequency. Must make the guest
6055 * doesn't see old kvmclock values while running with
6056 * the new frequency, otherwise we risk the guest sees
6057 * time go backwards.
6058 *
6059 * In case we update the frequency for another cpu
6060 * (which might be in guest context) send an interrupt
6061 * to kick the cpu out of guest context. Next time
6062 * guest context is entered kvmclock will be updated,
6063 * so the guest will not see stale values.
6064 */
8cfdc000 6065 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH
6066 }
6067 return 0;
6068}
6069
6070static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA
6071 .notifier_call = kvmclock_cpufreq_notifier
6072};
6073
251a5fd6 6074static int kvmclock_cpu_online(unsigned int cpu)
8cfdc000 6075{
251a5fd6
SAS
6076 tsc_khz_changed(NULL);
6077 return 0;
8cfdc000
ZA
6078}
6079
b820cc0c
ZA
6080static void kvm_timer_init(void)
6081{
c285545f 6082 max_tsc_khz = tsc_khz;
460dd42e 6083
b820cc0c 6084 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA
6085#ifdef CONFIG_CPU_FREQ
6086 struct cpufreq_policy policy;
758f588d
BP
6087 int cpu;
6088
c285545f 6089 memset(&policy, 0, sizeof(policy));
3e26f230
AK
6090 cpu = get_cpu();
6091 cpufreq_get_policy(&policy, cpu);
c285545f
ZA
6092 if (policy.cpuinfo.max_freq)
6093 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 6094 put_cpu();
c285545f 6095#endif
b820cc0c
ZA
6096 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
6097 CPUFREQ_TRANSITION_NOTIFIER);
6098 }
c285545f 6099 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
460dd42e 6100
73c1b41e 6101 cpuhp_setup_state(CPUHP_AP_X86_KVM_CLK_ONLINE, "x86/kvm/clk:online",
251a5fd6 6102 kvmclock_cpu_online, kvmclock_cpu_down_prep);
b820cc0c
ZA
6103}
6104
ff9d07a0
ZY
6105static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
6106
f5132b01 6107int kvm_is_in_guest(void)
ff9d07a0 6108{
086c9855 6109 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY
6110}
6111
6112static int kvm_is_user_mode(void)
6113{
6114 int user_mode = 3;
dcf46b94 6115
086c9855
AS
6116 if (__this_cpu_read(current_vcpu))
6117 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 6118
ff9d07a0
ZY
6119 return user_mode != 0;
6120}
6121
6122static unsigned long kvm_get_guest_ip(void)
6123{
6124 unsigned long ip = 0;
dcf46b94 6125
086c9855
AS
6126 if (__this_cpu_read(current_vcpu))
6127 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 6128
ff9d07a0
ZY
6129 return ip;
6130}
6131
6132static struct perf_guest_info_callbacks kvm_guest_cbs = {
6133 .is_in_guest = kvm_is_in_guest,
6134 .is_user_mode = kvm_is_user_mode,
6135 .get_guest_ip = kvm_get_guest_ip,
6136};
6137
6138void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
6139{
086c9855 6140 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY
6141}
6142EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
6143
6144void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
6145{
086c9855 6146 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY
6147}
6148EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
6149
ce88decf
XG
6150static void kvm_set_mmio_spte_mask(void)
6151{
6152 u64 mask;
6153 int maxphyaddr = boot_cpu_data.x86_phys_bits;
6154
6155 /*
6156 * Set the reserved bits and the present bit of an paging-structure
6157 * entry to generate page fault with PFER.RSV = 1.
6158 */
885032b9 6159 /* Mask the reserved physical address bits. */
d1431483 6160 mask = rsvd_bits(maxphyaddr, 51);
885032b9 6161
885032b9 6162 /* Set the present bit. */
ce88decf
XG
6163 mask |= 1ull;
6164
6165#ifdef CONFIG_X86_64
6166 /*
6167 * If reserved bit is not supported, clear the present bit to disable
6168 * mmio page fault.
6169 */
6170 if (maxphyaddr == 52)
6171 mask &= ~1ull;
6172#endif
6173
dcdca5fe 6174 kvm_mmu_set_mmio_spte_mask(mask, mask);
ce88decf
XG
6175}
6176
16e8d74d
MT
6177#ifdef CONFIG_X86_64
6178static void pvclock_gtod_update_fn(struct work_struct *work)
6179{
d828199e
MT
6180 struct kvm *kvm;
6181
6182 struct kvm_vcpu *vcpu;
6183 int i;
6184
2f303b74 6185 spin_lock(&kvm_lock);
d828199e
MT
6186 list_for_each_entry(kvm, &vm_list, vm_list)
6187 kvm_for_each_vcpu(i, vcpu, kvm)
105b21bb 6188 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
d828199e 6189 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 6190 spin_unlock(&kvm_lock);
16e8d74d
MT
6191}
6192
6193static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
6194
6195/*
6196 * Notification about pvclock gtod data update.
6197 */
6198static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
6199 void *priv)
6200{
6201 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
6202 struct timekeeper *tk = priv;
6203
6204 update_pvclock_gtod(tk);
6205
6206 /* disable master clock if host does not trust, or does not
6207 * use, TSC clocksource
6208 */
6209 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
6210 atomic_read(&kvm_guest_has_master_clock) != 0)
6211 queue_work(system_long_wq, &pvclock_gtod_work);
6212
6213 return 0;
6214}
6215
6216static struct notifier_block pvclock_gtod_notifier = {
6217 .notifier_call = pvclock_gtod_notify,
6218};
6219#endif
6220
f8c16bba 6221int kvm_arch_init(void *opaque)
043405e1 6222{
b820cc0c 6223 int r;
6b61edf7 6224 struct kvm_x86_ops *ops = opaque;
f8c16bba 6225
f8c16bba
ZX
6226 if (kvm_x86_ops) {
6227 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX
6228 r = -EEXIST;
6229 goto out;
f8c16bba
ZX
6230 }
6231
6232 if (!ops->cpu_has_kvm_support()) {
6233 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX
6234 r = -EOPNOTSUPP;
6235 goto out;
f8c16bba
ZX
6236 }
6237 if (ops->disabled_by_bios()) {
1cdfde02 6238 printk(KERN_WARNING "kvm: disabled by bios\n");
56c6d28a
ZX
6239 r = -EOPNOTSUPP;
6240 goto out;
f8c16bba
ZX
6241 }
6242
013f6a5d
MT
6243 r = -ENOMEM;
6244 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
6245 if (!shared_msrs) {
6246 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
6247 goto out;
6248 }
6249
97db56ce
AK
6250 r = kvm_mmu_module_init();
6251 if (r)
013f6a5d 6252 goto out_free_percpu;
97db56ce 6253
ce88decf 6254 kvm_set_mmio_spte_mask();
97db56ce 6255
f8c16bba 6256 kvm_x86_ops = ops;
920c8377 6257
7b52345e 6258 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
ffb128c8 6259 PT_DIRTY_MASK, PT64_NX_MASK, 0,
d0ec49d4 6260 PT_PRESENT_MASK, 0, sme_me_mask);
b820cc0c 6261 kvm_timer_init();
c8076604 6262
ff9d07a0
ZY
6263 perf_register_guest_info_callbacks(&kvm_guest_cbs);
6264
d366bf7e 6265 if (boot_cpu_has(X86_FEATURE_XSAVE))
2acf923e
DC
6266 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
6267
c5cc421b 6268 kvm_lapic_init();
16e8d74d
MT
6269#ifdef CONFIG_X86_64
6270 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
6271#endif
6272
f8c16bba 6273 return 0;
56c6d28a 6274
013f6a5d
MT
6275out_free_percpu:
6276 free_percpu(shared_msrs);
56c6d28a 6277out:
56c6d28a 6278 return r;
043405e1 6279}
8776e519 6280
f8c16bba
ZX
6281void kvm_arch_exit(void)
6282{
cef84c30 6283 kvm_lapic_exit();
ff9d07a0
ZY
6284 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
6285
888d256e
JK
6286 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
6287 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
6288 CPUFREQ_TRANSITION_NOTIFIER);
251a5fd6 6289 cpuhp_remove_state_nocalls(CPUHP_AP_X86_KVM_CLK_ONLINE);
16e8d74d
MT
6290#ifdef CONFIG_X86_64
6291 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
6292#endif
f8c16bba 6293 kvm_x86_ops = NULL;
56c6d28a 6294 kvm_mmu_module_exit();
013f6a5d 6295 free_percpu(shared_msrs);
56c6d28a 6296}
f8c16bba 6297
5cb56059 6298int kvm_vcpu_halt(struct kvm_vcpu *vcpu)
8776e519
HB
6299{
6300 ++vcpu->stat.halt_exits;
35754c98 6301 if (lapic_in_kernel(vcpu)) {
a4535290 6302 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB
6303 return 1;
6304 } else {
6305 vcpu->run->exit_reason = KVM_EXIT_HLT;
6306 return 0;
6307 }
6308}
5cb56059
JS
6309EXPORT_SYMBOL_GPL(kvm_vcpu_halt);
6310
6311int kvm_emulate_halt(struct kvm_vcpu *vcpu)
6312{
6affcbed
KH
6313 int ret = kvm_skip_emulated_instruction(vcpu);
6314 /*
6315 * TODO: we might be squashing a GUESTDBG_SINGLESTEP-triggered
6316 * KVM_EXIT_DEBUG here.
6317 */
6318 return kvm_vcpu_halt(vcpu) && ret;
5cb56059 6319}
8776e519
HB
6320EXPORT_SYMBOL_GPL(kvm_emulate_halt);
6321
8ef81a9a 6322#ifdef CONFIG_X86_64
55dd00a7
MT
6323static int kvm_pv_clock_pairing(struct kvm_vcpu *vcpu, gpa_t paddr,
6324 unsigned long clock_type)
6325{
6326 struct kvm_clock_pairing clock_pairing;
6327 struct timespec ts;
80fbd89c 6328 u64 cycle;
55dd00a7
MT
6329 int ret;
6330
6331 if (clock_type != KVM_CLOCK_PAIRING_WALLCLOCK)
6332 return -KVM_EOPNOTSUPP;
6333
6334 if (kvm_get_walltime_and_clockread(&ts, &cycle) == false)
6335 return -KVM_EOPNOTSUPP;
6336
6337 clock_pairing.sec = ts.tv_sec;
6338 clock_pairing.nsec = ts.tv_nsec;
6339 clock_pairing.tsc = kvm_read_l1_tsc(vcpu, cycle);
6340 clock_pairing.flags = 0;
6341
6342 ret = 0;
6343 if (kvm_write_guest(vcpu->kvm, paddr, &clock_pairing,
6344 sizeof(struct kvm_clock_pairing)))
6345 ret = -KVM_EFAULT;
6346
6347 return ret;
6348}
8ef81a9a 6349#endif
55dd00a7 6350
6aef266c
SV
6351/*
6352 * kvm_pv_kick_cpu_op: Kick a vcpu.
6353 *
6354 * @apicid - apicid of vcpu to be kicked.
6355 */
6356static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
6357{
24d2166b 6358 struct kvm_lapic_irq lapic_irq;
6aef266c 6359
24d2166b
R
6360 lapic_irq.shorthand = 0;
6361 lapic_irq.dest_mode = 0;
ebd28fcb 6362 lapic_irq.level = 0;
24d2166b 6363 lapic_irq.dest_id = apicid;
93bbf0b8 6364 lapic_irq.msi_redir_hint = false;
6aef266c 6365
24d2166b 6366 lapic_irq.delivery_mode = APIC_DM_REMRD;
795a149e 6367 kvm_irq_delivery_to_apic(kvm, NULL, &lapic_irq, NULL);
6aef266c
SV
6368}
6369
d62caabb
AS
6370void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu)
6371{
6372 vcpu->arch.apicv_active = false;
6373 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu);
6374}
6375
8776e519
HB
6376int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
6377{
6378 unsigned long nr, a0, a1, a2, a3, ret;
6affcbed 6379 int op_64_bit, r;
8776e519 6380
6affcbed 6381 r = kvm_skip_emulated_instruction(vcpu);
5cb56059 6382
55cd8e5a
GN
6383 if (kvm_hv_hypercall_enabled(vcpu->kvm))
6384 return kvm_hv_hypercall(vcpu);
6385
5fdbf976
MT
6386 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
6387 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
6388 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
6389 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
6390 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 6391
229456fc 6392 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 6393
a449c7aa
NA
6394 op_64_bit = is_64_bit_mode(vcpu);
6395 if (!op_64_bit) {
8776e519
HB
6396 nr &= 0xFFFFFFFF;
6397 a0 &= 0xFFFFFFFF;
6398 a1 &= 0xFFFFFFFF;
6399 a2 &= 0xFFFFFFFF;
6400 a3 &= 0xFFFFFFFF;
6401 }
6402
07708c4a
JK
6403 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
6404 ret = -KVM_EPERM;
6405 goto out;
6406 }
6407
8776e519 6408 switch (nr) {
b93463aa
AK
6409 case KVM_HC_VAPIC_POLL_IRQ:
6410 ret = 0;
6411 break;
6aef266c
SV
6412 case KVM_HC_KICK_CPU:
6413 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
6414 ret = 0;
6415 break;
8ef81a9a 6416#ifdef CONFIG_X86_64
55dd00a7
MT
6417 case KVM_HC_CLOCK_PAIRING:
6418 ret = kvm_pv_clock_pairing(vcpu, a0, a1);
6419 break;
8ef81a9a 6420#endif
8776e519
HB
6421 default:
6422 ret = -KVM_ENOSYS;
6423 break;
6424 }
07708c4a 6425out:
a449c7aa
NA
6426 if (!op_64_bit)
6427 ret = (u32)ret;
5fdbf976 6428 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 6429 ++vcpu->stat.hypercalls;
2f333bcb 6430 return r;
8776e519
HB
6431}
6432EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
6433
b6785def 6434static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 6435{
d6aa1000 6436 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 6437 char instruction[3];
5fdbf976 6438 unsigned long rip = kvm_rip_read(vcpu);
8776e519 6439
8776e519 6440 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 6441
ce2e852e
DV
6442 return emulator_write_emulated(ctxt, rip, instruction, 3,
6443 &ctxt->exception);
8776e519
HB
6444}
6445
851ba692 6446static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 6447{
782d422b
MG
6448 return vcpu->run->request_interrupt_window &&
6449 likely(!pic_in_kernel(vcpu->kvm));
b6c7a5dc
HB
6450}
6451
851ba692 6452static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 6453{
851ba692
AK
6454 struct kvm_run *kvm_run = vcpu->run;
6455
91586a3b 6456 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
f077825a 6457 kvm_run->flags = is_smm(vcpu) ? KVM_RUN_X86_SMM : 0;
2d3ad1f4 6458 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 6459 kvm_run->apic_base = kvm_get_apic_base(vcpu);
127a457a
MG
6460 kvm_run->ready_for_interrupt_injection =
6461 pic_in_kernel(vcpu->kvm) ||
782d422b 6462 kvm_vcpu_ready_for_interrupt_injection(vcpu);
b6c7a5dc
HB
6463}
6464
95ba8273
GN
6465static void update_cr8_intercept(struct kvm_vcpu *vcpu)
6466{
6467 int max_irr, tpr;
6468
6469 if (!kvm_x86_ops->update_cr8_intercept)
6470 return;
6471
bce87cce 6472 if (!lapic_in_kernel(vcpu))
88c808fd
AK
6473 return;
6474
d62caabb
AS
6475 if (vcpu->arch.apicv_active)
6476 return;
6477
8db3baa2
GN
6478 if (!vcpu->arch.apic->vapic_addr)
6479 max_irr = kvm_lapic_find_highest_irr(vcpu);
6480 else
6481 max_irr = -1;
95ba8273
GN
6482
6483 if (max_irr != -1)
6484 max_irr >>= 4;
6485
6486 tpr = kvm_lapic_get_cr8(vcpu);
6487
6488 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
6489}
6490
b6b8a145 6491static int inject_pending_event(struct kvm_vcpu *vcpu, bool req_int_win)
95ba8273 6492{
b6b8a145
JK
6493 int r;
6494
95ba8273 6495 /* try to reinject previous events if any */
664f8e26
WL
6496 if (vcpu->arch.exception.injected) {
6497 kvm_x86_ops->queue_exception(vcpu);
6498 return 0;
6499 }
6500
6501 /*
6502 * Exceptions must be injected immediately, or the exception
6503 * frame will have the address of the NMI or interrupt handler.
6504 */
6505 if (!vcpu->arch.exception.pending) {
6506 if (vcpu->arch.nmi_injected) {
6507 kvm_x86_ops->set_nmi(vcpu);
6508 return 0;
6509 }
6510
6511 if (vcpu->arch.interrupt.pending) {
6512 kvm_x86_ops->set_irq(vcpu);
6513 return 0;
6514 }
6515 }
6516
6517 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6518 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6519 if (r != 0)
6520 return r;
6521 }
6522
6523 /* try to inject new event if pending */
b59bb7bd 6524 if (vcpu->arch.exception.pending) {
5c1c85d0
AK
6525 trace_kvm_inj_exception(vcpu->arch.exception.nr,
6526 vcpu->arch.exception.has_error_code,
6527 vcpu->arch.exception.error_code);
d6e8c854 6528
664f8e26
WL
6529 vcpu->arch.exception.pending = false;
6530 vcpu->arch.exception.injected = true;
6531
d6e8c854
NA
6532 if (exception_type(vcpu->arch.exception.nr) == EXCPT_FAULT)
6533 __kvm_set_rflags(vcpu, kvm_get_rflags(vcpu) |
6534 X86_EFLAGS_RF);
6535
6bdf0662
NA
6536 if (vcpu->arch.exception.nr == DB_VECTOR &&
6537 (vcpu->arch.dr7 & DR7_GD)) {
6538 vcpu->arch.dr7 &= ~DR7_GD;
6539 kvm_update_dr7(vcpu);
6540 }
6541
cfcd20e5 6542 kvm_x86_ops->queue_exception(vcpu);
72d7b374 6543 } else if (vcpu->arch.smi_pending && !is_smm(vcpu) && kvm_x86_ops->smi_allowed(vcpu)) {
c43203ca 6544 vcpu->arch.smi_pending = false;
ee2cd4b7 6545 enter_smm(vcpu);
c43203ca 6546 } else if (vcpu->arch.nmi_pending && kvm_x86_ops->nmi_allowed(vcpu)) {
321c5658
YS
6547 --vcpu->arch.nmi_pending;
6548 vcpu->arch.nmi_injected = true;
6549 kvm_x86_ops->set_nmi(vcpu);
c7c9c56c 6550 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
9242b5b6
BD
6551 /*
6552 * Because interrupts can be injected asynchronously, we are
6553 * calling check_nested_events again here to avoid a race condition.
6554 * See https://lkml.org/lkml/2014/7/2/60 for discussion about this
6555 * proposal and current concerns. Perhaps we should be setting
6556 * KVM_REQ_EVENT only on certain events and not unconditionally?
6557 */
6558 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events) {
6559 r = kvm_x86_ops->check_nested_events(vcpu, req_int_win);
6560 if (r != 0)
6561 return r;
6562 }
95ba8273 6563 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN
6564 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
6565 false);
6566 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN
6567 }
6568 }
ee2cd4b7 6569
b6b8a145 6570 return 0;
95ba8273
GN
6571}
6572
7460fb4a
AK
6573static void process_nmi(struct kvm_vcpu *vcpu)
6574{
6575 unsigned limit = 2;
6576
6577 /*
6578 * x86 is limited to one NMI running, and one NMI pending after it.
6579 * If an NMI is already in progress, limit further NMIs to just one.
6580 * Otherwise, allow two (and we'll inject the first one immediately).
6581 */
6582 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
6583 limit = 1;
6584
6585 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
6586 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
6587 kvm_make_request(KVM_REQ_EVENT, vcpu);
6588}
6589
ee2cd4b7 6590static u32 enter_smm_get_segment_flags(struct kvm_segment *seg)
660a5d51
PB
6591{
6592 u32 flags = 0;
6593 flags |= seg->g << 23;
6594 flags |= seg->db << 22;
6595 flags |= seg->l << 21;
6596 flags |= seg->avl << 20;
6597 flags |= seg->present << 15;
6598 flags |= seg->dpl << 13;
6599 flags |= seg->s << 12;
6600 flags |= seg->type << 8;
6601 return flags;
6602}
6603
ee2cd4b7 6604static void enter_smm_save_seg_32(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB
6605{
6606 struct kvm_segment seg;
6607 int offset;
6608
6609 kvm_get_segment(vcpu, &seg, n);
6610 put_smstate(u32, buf, 0x7fa8 + n * 4, seg.selector);
6611
6612 if (n < 3)
6613 offset = 0x7f84 + n * 12;
6614 else
6615 offset = 0x7f2c + (n - 3) * 12;
6616
6617 put_smstate(u32, buf, offset + 8, seg.base);
6618 put_smstate(u32, buf, offset + 4, seg.limit);
ee2cd4b7 6619 put_smstate(u32, buf, offset, enter_smm_get_segment_flags(&seg));
660a5d51
PB
6620}
6621
efbb288a 6622#ifdef CONFIG_X86_64
ee2cd4b7 6623static void enter_smm_save_seg_64(struct kvm_vcpu *vcpu, char *buf, int n)
660a5d51
PB
6624{
6625 struct kvm_segment seg;
6626 int offset;
6627 u16 flags;
6628
6629 kvm_get_segment(vcpu, &seg, n);
6630 offset = 0x7e00 + n * 16;
6631
ee2cd4b7 6632 flags = enter_smm_get_segment_flags(&seg) >> 8;
660a5d51
PB
6633 put_smstate(u16, buf, offset, seg.selector);
6634 put_smstate(u16, buf, offset + 2, flags);
6635 put_smstate(u32, buf, offset + 4, seg.limit);
6636 put_smstate(u64, buf, offset + 8, seg.base);
6637}
efbb288a 6638#endif
660a5d51 6639
ee2cd4b7 6640static void enter_smm_save_state_32(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB
6641{
6642 struct desc_ptr dt;
6643 struct kvm_segment seg;
6644 unsigned long val;
6645 int i;
6646
6647 put_smstate(u32, buf, 0x7ffc, kvm_read_cr0(vcpu));
6648 put_smstate(u32, buf, 0x7ff8, kvm_read_cr3(vcpu));
6649 put_smstate(u32, buf, 0x7ff4, kvm_get_rflags(vcpu));
6650 put_smstate(u32, buf, 0x7ff0, kvm_rip_read(vcpu));
6651
6652 for (i = 0; i < 8; i++)
6653 put_smstate(u32, buf, 0x7fd0 + i * 4, kvm_register_read(vcpu, i));
6654
6655 kvm_get_dr(vcpu, 6, &val);
6656 put_smstate(u32, buf, 0x7fcc, (u32)val);
6657 kvm_get_dr(vcpu, 7, &val);
6658 put_smstate(u32, buf, 0x7fc8, (u32)val);
6659
6660 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6661 put_smstate(u32, buf, 0x7fc4, seg.selector);
6662 put_smstate(u32, buf, 0x7f64, seg.base);
6663 put_smstate(u32, buf, 0x7f60, seg.limit);
ee2cd4b7 6664 put_smstate(u32, buf, 0x7f5c, enter_smm_get_segment_flags(&seg));
660a5d51
PB
6665
6666 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6667 put_smstate(u32, buf, 0x7fc0, seg.selector);
6668 put_smstate(u32, buf, 0x7f80, seg.base);
6669 put_smstate(u32, buf, 0x7f7c, seg.limit);
ee2cd4b7 6670 put_smstate(u32, buf, 0x7f78, enter_smm_get_segment_flags(&seg));
660a5d51
PB
6671
6672 kvm_x86_ops->get_gdt(vcpu, &dt);
6673 put_smstate(u32, buf, 0x7f74, dt.address);
6674 put_smstate(u32, buf, 0x7f70, dt.size);
6675
6676 kvm_x86_ops->get_idt(vcpu, &dt);
6677 put_smstate(u32, buf, 0x7f58, dt.address);
6678 put_smstate(u32, buf, 0x7f54, dt.size);
6679
6680 for (i = 0; i < 6; i++)
ee2cd4b7 6681 enter_smm_save_seg_32(vcpu, buf, i);
660a5d51
PB
6682
6683 put_smstate(u32, buf, 0x7f14, kvm_read_cr4(vcpu));
6684
6685 /* revision id */
6686 put_smstate(u32, buf, 0x7efc, 0x00020000);
6687 put_smstate(u32, buf, 0x7ef8, vcpu->arch.smbase);
6688}
6689
ee2cd4b7 6690static void enter_smm_save_state_64(struct kvm_vcpu *vcpu, char *buf)
660a5d51
PB
6691{
6692#ifdef CONFIG_X86_64
6693 struct desc_ptr dt;
6694 struct kvm_segment seg;
6695 unsigned long val;
6696 int i;
6697
6698 for (i = 0; i < 16; i++)
6699 put_smstate(u64, buf, 0x7ff8 - i * 8, kvm_register_read(vcpu, i));
6700
6701 put_smstate(u64, buf, 0x7f78, kvm_rip_read(vcpu));
6702 put_smstate(u32, buf, 0x7f70, kvm_get_rflags(vcpu));
6703
6704 kvm_get_dr(vcpu, 6, &val);
6705 put_smstate(u64, buf, 0x7f68, val);
6706 kvm_get_dr(vcpu, 7, &val);
6707 put_smstate(u64, buf, 0x7f60, val);
6708
6709 put_smstate(u64, buf, 0x7f58, kvm_read_cr0(vcpu));
6710 put_smstate(u64, buf, 0x7f50, kvm_read_cr3(vcpu));
6711 put_smstate(u64, buf, 0x7f48, kvm_read_cr4(vcpu));
6712
6713 put_smstate(u32, buf, 0x7f00, vcpu->arch.smbase);
6714
6715 /* revision id */
6716 put_smstate(u32, buf, 0x7efc, 0x00020064);
6717
6718 put_smstate(u64, buf, 0x7ed0, vcpu->arch.efer);
6719
6720 kvm_get_segment(vcpu, &seg, VCPU_SREG_TR);
6721 put_smstate(u16, buf, 0x7e90, seg.selector);
ee2cd4b7 6722 put_smstate(u16, buf, 0x7e92, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB
6723 put_smstate(u32, buf, 0x7e94, seg.limit);
6724 put_smstate(u64, buf, 0x7e98, seg.base);
6725
6726 kvm_x86_ops->get_idt(vcpu, &dt);
6727 put_smstate(u32, buf, 0x7e84, dt.size);
6728 put_smstate(u64, buf, 0x7e88, dt.address);
6729
6730 kvm_get_segment(vcpu, &seg, VCPU_SREG_LDTR);
6731 put_smstate(u16, buf, 0x7e70, seg.selector);
ee2cd4b7 6732 put_smstate(u16, buf, 0x7e72, enter_smm_get_segment_flags(&seg) >> 8);
660a5d51
PB
6733 put_smstate(u32, buf, 0x7e74, seg.limit);
6734 put_smstate(u64, buf, 0x7e78, seg.base);
6735
6736 kvm_x86_ops->get_gdt(vcpu, &dt);
6737 put_smstate(u32, buf, 0x7e64, dt.size);
6738 put_smstate(u64, buf, 0x7e68, dt.address);
6739
6740 for (i = 0; i < 6; i++)
ee2cd4b7 6741 enter_smm_save_seg_64(vcpu, buf, i);
660a5d51
PB
6742#else
6743 WARN_ON_ONCE(1);
6744#endif
6745}
6746
ee2cd4b7 6747static void enter_smm(struct kvm_vcpu *vcpu)
64d60670 6748{
660a5d51 6749 struct kvm_segment cs, ds;
18c3626e 6750 struct desc_ptr dt;
660a5d51
PB
6751 char buf[512];
6752 u32 cr0;
6753
660a5d51 6754 trace_kvm_enter_smm(vcpu->vcpu_id, vcpu->arch.smbase, true);
660a5d51 6755 memset(buf, 0, 512);
d6321d49 6756 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
ee2cd4b7 6757 enter_smm_save_state_64(vcpu, buf);
660a5d51 6758 else
ee2cd4b7 6759 enter_smm_save_state_32(vcpu, buf);
660a5d51 6760
0234bf88
LP
6761 /*
6762 * Give pre_enter_smm() a chance to make ISA-specific changes to the
6763 * vCPU state (e.g. leave guest mode) after we've saved the state into
6764 * the SMM state-save area.
6765 */
6766 kvm_x86_ops->pre_enter_smm(vcpu, buf);
6767
6768 vcpu->arch.hflags |= HF_SMM_MASK;
54bf36aa 6769 kvm_vcpu_write_guest(vcpu, vcpu->arch.smbase + 0xfe00, buf, sizeof(buf));
660a5d51
PB
6770
6771 if (kvm_x86_ops->get_nmi_mask(vcpu))
6772 vcpu->arch.hflags |= HF_SMM_INSIDE_NMI_MASK;
6773 else
6774 kvm_x86_ops->set_nmi_mask(vcpu, true);
6775
6776 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
6777 kvm_rip_write(vcpu, 0x8000);
6778
6779 cr0 = vcpu->arch.cr0 & ~(X86_CR0_PE | X86_CR0_EM | X86_CR0_TS | X86_CR0_PG);
6780 kvm_x86_ops->set_cr0(vcpu, cr0);
6781 vcpu->arch.cr0 = cr0;
6782
6783 kvm_x86_ops->set_cr4(vcpu, 0);
6784
18c3626e
PB
6785 /* Undocumented: IDT limit is set to zero on entry to SMM. */
6786 dt.address = dt.size = 0;
6787 kvm_x86_ops->set_idt(vcpu, &dt);
6788
660a5d51
PB
6789 __kvm_set_dr(vcpu, 7, DR7_FIXED_1);
6790
6791 cs.selector = (vcpu->arch.smbase >> 4) & 0xffff;
6792 cs.base = vcpu->arch.smbase;
6793
6794 ds.selector = 0;
6795 ds.base = 0;
6796
6797 cs.limit = ds.limit = 0xffffffff;
6798 cs.type = ds.type = 0x3;
6799 cs.dpl = ds.dpl = 0;
6800 cs.db = ds.db = 0;
6801 cs.s = ds.s = 1;
6802 cs.l = ds.l = 0;
6803 cs.g = ds.g = 1;
6804 cs.avl = ds.avl = 0;
6805 cs.present = ds.present = 1;
6806 cs.unusable = ds.unusable = 0;
6807 cs.padding = ds.padding = 0;
6808
6809 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6810 kvm_set_segment(vcpu, &ds, VCPU_SREG_DS);
6811 kvm_set_segment(vcpu, &ds, VCPU_SREG_ES);
6812 kvm_set_segment(vcpu, &ds, VCPU_SREG_FS);
6813 kvm_set_segment(vcpu, &ds, VCPU_SREG_GS);
6814 kvm_set_segment(vcpu, &ds, VCPU_SREG_SS);
6815
d6321d49 6816 if (guest_cpuid_has(vcpu, X86_FEATURE_LM))
660a5d51
PB
6817 kvm_x86_ops->set_efer(vcpu, 0);
6818
6819 kvm_update_cpuid(vcpu);
6820 kvm_mmu_reset_context(vcpu);
64d60670
PB
6821}
6822
ee2cd4b7 6823static void process_smi(struct kvm_vcpu *vcpu)
c43203ca
PB
6824{
6825 vcpu->arch.smi_pending = true;
6826 kvm_make_request(KVM_REQ_EVENT, vcpu);
6827}
6828
2860c4b1
PB
6829void kvm_make_scan_ioapic_request(struct kvm *kvm)
6830{
6831 kvm_make_all_cpus_request(kvm, KVM_REQ_SCAN_IOAPIC);
6832}
6833
3d81bc7e 6834static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c 6835{
5c919412
AS
6836 u64 eoi_exit_bitmap[4];
6837
3d81bc7e
YZ
6838 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
6839 return;
c7c9c56c 6840
6308630b 6841 bitmap_zero(vcpu->arch.ioapic_handled_vectors, 256);
c7c9c56c 6842
b053b2ae 6843 if (irqchip_split(vcpu->kvm))
6308630b 6844 kvm_scan_ioapic_routes(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6845 else {
76dfafd5 6846 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
d62caabb 6847 kvm_x86_ops->sync_pir_to_irr(vcpu);
6308630b 6848 kvm_ioapic_scan_entry(vcpu, vcpu->arch.ioapic_handled_vectors);
db2bdcbb 6849 }
5c919412
AS
6850 bitmap_or((ulong *)eoi_exit_bitmap, vcpu->arch.ioapic_handled_vectors,
6851 vcpu_to_synic(vcpu)->vec_bitmap, 256);
6852 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
c7c9c56c
YZ
6853}
6854
a70656b6
RK
6855static void kvm_vcpu_flush_tlb(struct kvm_vcpu *vcpu)
6856{
6857 ++vcpu->stat.tlb_flush;
6858 kvm_x86_ops->tlb_flush(vcpu);
6859}
6860
b1394e74
RK
6861void kvm_arch_mmu_notifier_invalidate_range(struct kvm *kvm,
6862 unsigned long start, unsigned long end)
6863{
6864 unsigned long apic_address;
6865
6866 /*
6867 * The physical address of apic access page is stored in the VMCS.
6868 * Update it when it becomes invalid.
6869 */
6870 apic_address = gfn_to_hva(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
6871 if (start <= apic_address && apic_address < end)
6872 kvm_make_all_cpus_request(kvm, KVM_REQ_APIC_PAGE_RELOAD);
6873}
6874
4256f43f
TC
6875void kvm_vcpu_reload_apic_access_page(struct kvm_vcpu *vcpu)
6876{
c24ae0dc
TC
6877 struct page *page = NULL;
6878
35754c98 6879 if (!lapic_in_kernel(vcpu))
f439ed27
PB
6880 return;
6881
4256f43f
TC
6882 if (!kvm_x86_ops->set_apic_access_page_addr)
6883 return;
6884
c24ae0dc 6885 page = gfn_to_page(vcpu->kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
e8fd5e9e
AA
6886 if (is_error_page(page))
6887 return;
c24ae0dc
TC
6888 kvm_x86_ops->set_apic_access_page_addr(vcpu, page_to_phys(page));
6889
6890 /*
6891 * Do not pin apic access page in memory, the MMU notifier
6892 * will call us again if it is migrated or swapped out.
6893 */
6894 put_page(page);
4256f43f
TC
6895}
6896EXPORT_SYMBOL_GPL(kvm_vcpu_reload_apic_access_page);
6897
9357d939 6898/*
362c698f 6899 * Returns 1 to let vcpu_run() continue the guest execution loop without
9357d939
TY
6900 * exiting to the userspace. Otherwise, the value will be returned to the
6901 * userspace.
6902 */
851ba692 6903static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB
6904{
6905 int r;
62a193ed
MG
6906 bool req_int_win =
6907 dm_request_for_irq_injection(vcpu) &&
6908 kvm_cpu_accept_dm_intr(vcpu);
6909
730dca42 6910 bool req_immediate_exit = false;
b6c7a5dc 6911
2fa6e1e1 6912 if (kvm_request_pending(vcpu)) {
a8eeb04a 6913 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 6914 kvm_mmu_unload(vcpu);
a8eeb04a 6915 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 6916 __kvm_migrate_timers(vcpu);
d828199e
MT
6917 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
6918 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT
6919 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
6920 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA
6921 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
6922 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA
6923 if (unlikely(r))
6924 goto out;
6925 }
a8eeb04a 6926 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 6927 kvm_mmu_sync_roots(vcpu);
a8eeb04a 6928 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
a70656b6 6929 kvm_vcpu_flush_tlb(vcpu);
a8eeb04a 6930 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 6931 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK
6932 r = 0;
6933 goto out;
6934 }
a8eeb04a 6935 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 6936 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 6937 vcpu->mmio_needed = 0;
71c4dfaf
JR
6938 r = 0;
6939 goto out;
6940 }
af585b92
GN
6941 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
6942 /* Page is swapped out. Do synthetic halt */
6943 vcpu->arch.apf.halted = true;
6944 r = 1;
6945 goto out;
6946 }
c9aaa895
GC
6947 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
6948 record_steal_time(vcpu);
64d60670
PB
6949 if (kvm_check_request(KVM_REQ_SMI, vcpu))
6950 process_smi(vcpu);
7460fb4a
AK
6951 if (kvm_check_request(KVM_REQ_NMI, vcpu))
6952 process_nmi(vcpu);
f5132b01 6953 if (kvm_check_request(KVM_REQ_PMU, vcpu))
c6702c9d 6954 kvm_pmu_handle_event(vcpu);
f5132b01 6955 if (kvm_check_request(KVM_REQ_PMI, vcpu))
c6702c9d 6956 kvm_pmu_deliver_pmi(vcpu);
7543a635
SR
6957 if (kvm_check_request(KVM_REQ_IOAPIC_EOI_EXIT, vcpu)) {
6958 BUG_ON(vcpu->arch.pending_ioapic_eoi > 255);
6959 if (test_bit(vcpu->arch.pending_ioapic_eoi,
6308630b 6960 vcpu->arch.ioapic_handled_vectors)) {
7543a635
SR
6961 vcpu->run->exit_reason = KVM_EXIT_IOAPIC_EOI;
6962 vcpu->run->eoi.vector =
6963 vcpu->arch.pending_ioapic_eoi;
6964 r = 0;
6965 goto out;
6966 }
6967 }
3d81bc7e
YZ
6968 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
6969 vcpu_scan_ioapic(vcpu);
4256f43f
TC
6970 if (kvm_check_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu))
6971 kvm_vcpu_reload_apic_access_page(vcpu);
2ce79189
AS
6972 if (kvm_check_request(KVM_REQ_HV_CRASH, vcpu)) {
6973 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6974 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_CRASH;
6975 r = 0;
6976 goto out;
6977 }
e516cebb
AS
6978 if (kvm_check_request(KVM_REQ_HV_RESET, vcpu)) {
6979 vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
6980 vcpu->run->system_event.type = KVM_SYSTEM_EVENT_RESET;
6981 r = 0;
6982 goto out;
6983 }
db397571
AS
6984 if (kvm_check_request(KVM_REQ_HV_EXIT, vcpu)) {
6985 vcpu->run->exit_reason = KVM_EXIT_HYPERV;
6986 vcpu->run->hyperv = vcpu->arch.hyperv.exit;
6987 r = 0;
6988 goto out;
6989 }
f3b138c5
AS
6990
6991 /*
6992 * KVM_REQ_HV_STIMER has to be processed after
6993 * KVM_REQ_CLOCK_UPDATE, because Hyper-V SynIC timers
6994 * depend on the guest clock being up-to-date
6995 */
1f4b34f8
AS
6996 if (kvm_check_request(KVM_REQ_HV_STIMER, vcpu))
6997 kvm_hv_process_stimers(vcpu);
2f52d58c 6998 }
b93463aa 6999
b463a6f7 7000 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
0f1e261e 7001 ++vcpu->stat.req_event;
66450a21
JK
7002 kvm_apic_accept_events(vcpu);
7003 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
7004 r = 1;
7005 goto out;
7006 }
7007
b6b8a145
JK
7008 if (inject_pending_event(vcpu, req_int_win) != 0)
7009 req_immediate_exit = true;
321c5658 7010 else {
cc3d967f 7011 /* Enable SMI/NMI/IRQ window open exits if needed.
c43203ca 7012 *
cc3d967f
LP
7013 * SMIs have three cases:
7014 * 1) They can be nested, and then there is nothing to
7015 * do here because RSM will cause a vmexit anyway.
7016 * 2) There is an ISA-specific reason why SMI cannot be
7017 * injected, and the moment when this changes can be
7018 * intercepted.
7019 * 3) Or the SMI can be pending because
7020 * inject_pending_event has completed the injection
7021 * of an IRQ or NMI from the previous vmexit, and
7022 * then we request an immediate exit to inject the
7023 * SMI.
c43203ca
PB
7024 */
7025 if (vcpu->arch.smi_pending && !is_smm(vcpu))
cc3d967f
LP
7026 if (!kvm_x86_ops->enable_smi_window(vcpu))
7027 req_immediate_exit = true;
321c5658
YS
7028 if (vcpu->arch.nmi_pending)
7029 kvm_x86_ops->enable_nmi_window(vcpu);
7030 if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
7031 kvm_x86_ops->enable_irq_window(vcpu);
664f8e26 7032 WARN_ON(vcpu->arch.exception.pending);
321c5658 7033 }
b463a6f7
AK
7034
7035 if (kvm_lapic_enabled(vcpu)) {
7036 update_cr8_intercept(vcpu);
7037 kvm_lapic_sync_to_vapic(vcpu);
7038 }
7039 }
7040
d8368af8
AK
7041 r = kvm_mmu_reload(vcpu);
7042 if (unlikely(r)) {
d905c069 7043 goto cancel_injection;
d8368af8
AK
7044 }
7045
b6c7a5dc
HB
7046 preempt_disable();
7047
7048 kvm_x86_ops->prepare_guest_switch(vcpu);
b95234c8
PB
7049
7050 /*
7051 * Disable IRQs before setting IN_GUEST_MODE. Posted interrupt
7052 * IPI are then delayed after guest entry, which ensures that they
7053 * result in virtual interrupt delivery.
7054 */
7055 local_irq_disable();
6b7e2d09
XG
7056 vcpu->mode = IN_GUEST_MODE;
7057
01b71917
MT
7058 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7059
0f127d12 7060 /*
b95234c8 7061 * 1) We should set ->mode before checking ->requests. Please see
cde9af6e 7062 * the comment in kvm_vcpu_exiting_guest_mode().
b95234c8
PB
7063 *
7064 * 2) For APICv, we should set ->mode before checking PIR.ON. This
7065 * pairs with the memory barrier implicit in pi_test_and_set_on
7066 * (see vmx_deliver_posted_interrupt).
7067 *
7068 * 3) This also orders the write to mode from any reads to the page
7069 * tables done while the VCPU is running. Please see the comment
7070 * in kvm_flush_remote_tlbs.
6b7e2d09 7071 */
01b71917 7072 smp_mb__after_srcu_read_unlock();
b6c7a5dc 7073
b95234c8
PB
7074 /*
7075 * This handles the case where a posted interrupt was
7076 * notified with kvm_vcpu_kick.
7077 */
7078 if (kvm_lapic_enabled(vcpu)) {
7079 if (kvm_x86_ops->sync_pir_to_irr && vcpu->arch.apicv_active)
7080 kvm_x86_ops->sync_pir_to_irr(vcpu);
7081 }
32f88400 7082
2fa6e1e1 7083 if (vcpu->mode == EXITING_GUEST_MODE || kvm_request_pending(vcpu)
d94e1dc9 7084 || need_resched() || signal_pending(current)) {
6b7e2d09 7085 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7086 smp_wmb();
6c142801
AK
7087 local_irq_enable();
7088 preempt_enable();
01b71917 7089 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 7090 r = 1;
d905c069 7091 goto cancel_injection;
6c142801
AK
7092 }
7093
fc5b7f3b
DM
7094 kvm_load_guest_xcr0(vcpu);
7095
c43203ca
PB
7096 if (req_immediate_exit) {
7097 kvm_make_request(KVM_REQ_EVENT, vcpu);
d6185f20 7098 smp_send_reschedule(vcpu->cpu);
c43203ca 7099 }
d6185f20 7100
8b89fe1f
PB
7101 trace_kvm_entry(vcpu->vcpu_id);
7102 wait_lapic_expire(vcpu);
6edaa530 7103 guest_enter_irqoff();
b6c7a5dc 7104
42dbaa5a 7105 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK
7106 set_debugreg(0, 7);
7107 set_debugreg(vcpu->arch.eff_db[0], 0);
7108 set_debugreg(vcpu->arch.eff_db[1], 1);
7109 set_debugreg(vcpu->arch.eff_db[2], 2);
7110 set_debugreg(vcpu->arch.eff_db[3], 3);
c77fb5fe 7111 set_debugreg(vcpu->arch.dr6, 6);
ae561ede 7112 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
42dbaa5a 7113 }
b6c7a5dc 7114
851ba692 7115 kvm_x86_ops->run(vcpu);
b6c7a5dc 7116
c77fb5fe
PB
7117 /*
7118 * Do this here before restoring debug registers on the host. And
7119 * since we do this before handling the vmexit, a DR access vmexit
7120 * can (a) read the correct value of the debug registers, (b) set
7121 * KVM_DEBUGREG_WONT_EXIT again.
7122 */
7123 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)) {
c77fb5fe
PB
7124 WARN_ON(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP);
7125 kvm_x86_ops->sync_dirty_debug_regs(vcpu);
70e4da7a
PB
7126 kvm_update_dr0123(vcpu);
7127 kvm_update_dr6(vcpu);
7128 kvm_update_dr7(vcpu);
7129 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_RELOAD;
c77fb5fe
PB
7130 }
7131
24f1e32c
FW
7132 /*
7133 * If the guest has used debug registers, at least dr7
7134 * will be disabled while returning to the host.
7135 * If we don't have active breakpoints in the host, we don't
7136 * care about the messed up debug address registers. But if
7137 * we have some of them active, restore the old state.
7138 */
59d8eb53 7139 if (hw_breakpoint_active())
24f1e32c 7140 hw_breakpoint_restore();
42dbaa5a 7141
4ba76538 7142 vcpu->arch.last_guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1d5f066e 7143
6b7e2d09 7144 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 7145 smp_wmb();
a547c6db 7146
fc5b7f3b
DM
7147 kvm_put_guest_xcr0(vcpu);
7148
a547c6db 7149 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB
7150
7151 ++vcpu->stat.exits;
7152
f2485b3e 7153 guest_exit_irqoff();
b6c7a5dc 7154
f2485b3e 7155 local_irq_enable();
b6c7a5dc
HB
7156 preempt_enable();
7157
f656ce01 7158 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 7159
b6c7a5dc
HB
7160 /*
7161 * Profile KVM exit RIPs:
7162 */
7163 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT
7164 unsigned long rip = kvm_rip_read(vcpu);
7165 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB
7166 }
7167
cc578287
ZA
7168 if (unlikely(vcpu->arch.tsc_always_catchup))
7169 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 7170
5cfb1d5a
MT
7171 if (vcpu->arch.apic_attention)
7172 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 7173
618232e2 7174 vcpu->arch.gpa_available = false;
851ba692 7175 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT
7176 return r;
7177
7178cancel_injection:
7179 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT
7180 if (unlikely(vcpu->arch.apic_attention))
7181 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT
7182out:
7183 return r;
7184}
b6c7a5dc 7185
362c698f
PB
7186static inline int vcpu_block(struct kvm *kvm, struct kvm_vcpu *vcpu)
7187{
bf9f6ac8
FW
7188 if (!kvm_arch_vcpu_runnable(vcpu) &&
7189 (!kvm_x86_ops->pre_block || kvm_x86_ops->pre_block(vcpu) == 0)) {
9c8fd1ba
PB
7190 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
7191 kvm_vcpu_block(vcpu);
7192 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
bf9f6ac8
FW
7193
7194 if (kvm_x86_ops->post_block)
7195 kvm_x86_ops->post_block(vcpu);
7196
9c8fd1ba
PB
7197 if (!kvm_check_request(KVM_REQ_UNHALT, vcpu))
7198 return 1;
7199 }
362c698f
PB
7200
7201 kvm_apic_accept_events(vcpu);
7202 switch(vcpu->arch.mp_state) {
7203 case KVM_MP_STATE_HALTED:
7204 vcpu->arch.pv.pv_unhalted = false;
7205 vcpu->arch.mp_state =
7206 KVM_MP_STATE_RUNNABLE;
7207 case KVM_MP_STATE_RUNNABLE:
7208 vcpu->arch.apf.halted = false;
7209 break;
7210 case KVM_MP_STATE_INIT_RECEIVED:
7211 break;
7212 default:
7213 return -EINTR;
7214 break;
7215 }
7216 return 1;
7217}
09cec754 7218
5d9bc648
PB
7219static inline bool kvm_vcpu_running(struct kvm_vcpu *vcpu)
7220{
0ad3bed6
PB
7221 if (is_guest_mode(vcpu) && kvm_x86_ops->check_nested_events)
7222 kvm_x86_ops->check_nested_events(vcpu, false);
7223
5d9bc648
PB
7224 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7225 !vcpu->arch.apf.halted);
7226}
7227
362c698f 7228static int vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT
7229{
7230 int r;
f656ce01 7231 struct kvm *kvm = vcpu->kvm;
d7690175 7232
f656ce01 7233 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
f0ace387 7234 vcpu->arch.l1tf_flush_l1d = true;
d7690175 7235
362c698f 7236 for (;;) {
58f800d5 7237 if (kvm_vcpu_running(vcpu)) {
851ba692 7238 r = vcpu_enter_guest(vcpu);
bf9f6ac8 7239 } else {
362c698f 7240 r = vcpu_block(kvm, vcpu);
bf9f6ac8
FW
7241 }
7242
09cec754
GN
7243 if (r <= 0)
7244 break;
7245
72875d8a 7246 kvm_clear_request(KVM_REQ_PENDING_TIMER, vcpu);
09cec754
GN
7247 if (kvm_cpu_has_pending_timer(vcpu))
7248 kvm_inject_pending_timer_irqs(vcpu);
7249
782d422b
MG
7250 if (dm_request_for_irq_injection(vcpu) &&
7251 kvm_vcpu_ready_for_interrupt_injection(vcpu)) {
4ca7dd8c
PB
7252 r = 0;
7253 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
09cec754 7254 ++vcpu->stat.request_irq_exits;
362c698f 7255 break;
09cec754 7256 }
af585b92
GN
7257
7258 kvm_check_async_pf_completion(vcpu);
7259
09cec754
GN
7260 if (signal_pending(current)) {
7261 r = -EINTR;
851ba692 7262 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754 7263 ++vcpu->stat.signal_exits;
362c698f 7264 break;
09cec754
GN
7265 }
7266 if (need_resched()) {
f656ce01 7267 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 7268 cond_resched();
f656ce01 7269 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 7270 }
b6c7a5dc
HB
7271 }
7272
f656ce01 7273 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB
7274
7275 return r;
7276}
7277
716d51ab
GN
7278static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
7279{
7280 int r;
7281 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
7282 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
7283 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
7284 if (r != EMULATE_DONE)
7285 return 0;
7286 return 1;
7287}
7288
7289static int complete_emulated_pio(struct kvm_vcpu *vcpu)
7290{
7291 BUG_ON(!vcpu->arch.pio.count);
7292
7293 return complete_emulated_io(vcpu);
7294}
7295
f78146b0
AK
7296/*
7297 * Implements the following, as a state machine:
7298 *
7299 * read:
7300 * for each fragment
87da7e66
XG
7301 * for each mmio piece in the fragment
7302 * write gpa, len
7303 * exit
7304 * copy data
f78146b0
AK
7305 * execute insn
7306 *
7307 * write:
7308 * for each fragment
87da7e66
XG
7309 * for each mmio piece in the fragment
7310 * write gpa, len
7311 * copy data
7312 * exit
f78146b0 7313 */
716d51ab 7314static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK
7315{
7316 struct kvm_run *run = vcpu->run;
f78146b0 7317 struct kvm_mmio_fragment *frag;
87da7e66 7318 unsigned len;
5287f194 7319
716d51ab 7320 BUG_ON(!vcpu->mmio_needed);
5287f194 7321
716d51ab 7322 /* Complete previous fragment */
87da7e66
XG
7323 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
7324 len = min(8u, frag->len);
716d51ab 7325 if (!vcpu->mmio_is_write)
87da7e66
XG
7326 memcpy(frag->data, run->mmio.data, len);
7327
7328 if (frag->len <= 8) {
7329 /* Switch to the next fragment. */
7330 frag++;
7331 vcpu->mmio_cur_fragment++;
7332 } else {
7333 /* Go forward to the next mmio piece. */
7334 frag->data += len;
7335 frag->gpa += len;
7336 frag->len -= len;
7337 }
7338
a08d3b3b 7339 if (vcpu->mmio_cur_fragment >= vcpu->mmio_nr_fragments) {
716d51ab 7340 vcpu->mmio_needed = 0;
0912c977
PB
7341
7342 /* FIXME: return into emulator if single-stepping. */
cef4dea0 7343 if (vcpu->mmio_is_write)
716d51ab
GN
7344 return 1;
7345 vcpu->mmio_read_completed = 1;
7346 return complete_emulated_io(vcpu);
7347 }
87da7e66 7348
716d51ab
GN
7349 run->exit_reason = KVM_EXIT_MMIO;
7350 run->mmio.phys_addr = frag->gpa;
7351 if (vcpu->mmio_is_write)
87da7e66
XG
7352 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
7353 run->mmio.len = min(8u, frag->len);
716d51ab
GN
7354 run->mmio.is_write = vcpu->mmio_is_write;
7355 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7356 return 0;
5287f194
AK
7357}
7358
716d51ab 7359
b6c7a5dc
HB
7360int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
7361{
7362 int r;
b6c7a5dc 7363
20b7035c 7364 kvm_sigset_activate(vcpu);
ac9f6dc0 7365
5663d8f9
PX
7366 kvm_load_guest_fpu(vcpu);
7367
a4535290 7368 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
2f173d26
JS
7369 if (kvm_run->immediate_exit) {
7370 r = -EINTR;
7371 goto out;
7372 }
b6c7a5dc 7373 kvm_vcpu_block(vcpu);
66450a21 7374 kvm_apic_accept_events(vcpu);
72875d8a 7375 kvm_clear_request(KVM_REQ_UNHALT, vcpu);
ac9f6dc0 7376 r = -EAGAIN;
a0595000
JS
7377 if (signal_pending(current)) {
7378 r = -EINTR;
7379 vcpu->run->exit_reason = KVM_EXIT_INTR;
7380 ++vcpu->stat.signal_exits;
7381 }
ac9f6dc0 7382 goto out;
b6c7a5dc
HB
7383 }
7384
b6c7a5dc 7385 /* re-sync apic's tpr */
35754c98 7386 if (!lapic_in_kernel(vcpu)) {
eea1cff9
AP
7387 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
7388 r = -EINVAL;
7389 goto out;
7390 }
7391 }
b6c7a5dc 7392
716d51ab
GN
7393 if (unlikely(vcpu->arch.complete_userspace_io)) {
7394 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
7395 vcpu->arch.complete_userspace_io = NULL;
7396 r = cui(vcpu);
7397 if (r <= 0)
5663d8f9 7398 goto out;
716d51ab
GN
7399 } else
7400 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 7401
460df4c1
PB
7402 if (kvm_run->immediate_exit)
7403 r = -EINTR;
7404 else
7405 r = vcpu_run(vcpu);
b6c7a5dc
HB
7406
7407out:
5663d8f9 7408 kvm_put_guest_fpu(vcpu);
f1d86e46 7409 post_kvm_run_save(vcpu);
20b7035c 7410 kvm_sigset_deactivate(vcpu);
b6c7a5dc 7411
b6c7a5dc
HB
7412 return r;
7413}
7414
7415int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7416{
7ae441ea
GN
7417 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
7418 /*
7419 * We are here if userspace calls get_regs() in the middle of
7420 * instruction emulation. Registers state needs to be copied
4a969980 7421 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN
7422 * that usually, but some bad designed PV devices (vmware
7423 * backdoor interface) need this to work
7424 */
dd856efa 7425 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN
7426 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7427 }
5fdbf976
MT
7428 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
7429 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
7430 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
7431 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
7432 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
7433 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
7434 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7435 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 7436#ifdef CONFIG_X86_64
5fdbf976
MT
7437 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
7438 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
7439 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
7440 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
7441 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
7442 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
7443 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
7444 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB
7445#endif
7446
5fdbf976 7447 regs->rip = kvm_rip_read(vcpu);
91586a3b 7448 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 7449
b6c7a5dc
HB
7450 return 0;
7451}
7452
7453int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
7454{
7ae441ea
GN
7455 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
7456 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
7457
5fdbf976
MT
7458 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
7459 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
7460 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
7461 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
7462 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
7463 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
7464 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
7465 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 7466#ifdef CONFIG_X86_64
5fdbf976
MT
7467 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
7468 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
7469 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
7470 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
7471 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
7472 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
7473 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
7474 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB
7475#endif
7476
5fdbf976 7477 kvm_rip_write(vcpu, regs->rip);
d73235d1 7478 kvm_set_rflags(vcpu, regs->rflags | X86_EFLAGS_FIXED);
b6c7a5dc 7479
b4f14abd
JK
7480 vcpu->arch.exception.pending = false;
7481
3842d135
AK
7482 kvm_make_request(KVM_REQ_EVENT, vcpu);
7483
b6c7a5dc
HB
7484 return 0;
7485}
7486
b6c7a5dc
HB
7487void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
7488{
7489 struct kvm_segment cs;
7490
3e6e0aab 7491 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB
7492 *db = cs.db;
7493 *l = cs.l;
7494}
7495EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
7496
7497int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
7498 struct kvm_sregs *sregs)
7499{
89a27f4d 7500 struct desc_ptr dt;
b6c7a5dc 7501
3e6e0aab
GT
7502 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7503 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7504 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7505 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7506 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7507 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7508
3e6e0aab
GT
7509 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7510 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB
7511
7512 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN
7513 sregs->idt.limit = dt.size;
7514 sregs->idt.base = dt.address;
b6c7a5dc 7515 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN
7516 sregs->gdt.limit = dt.size;
7517 sregs->gdt.base = dt.address;
b6c7a5dc 7518
4d4ec087 7519 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 7520 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 7521 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 7522 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 7523 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 7524 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB
7525 sregs->apic_base = kvm_get_apic_base(vcpu);
7526
923c61bb 7527 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 7528
36752c9b 7529 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN
7530 set_bit(vcpu->arch.interrupt.nr,
7531 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 7532
b6c7a5dc
HB
7533 return 0;
7534}
7535
62d9f0db
MT
7536int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
7537 struct kvm_mp_state *mp_state)
7538{
66450a21 7539 kvm_apic_accept_events(vcpu);
6aef266c
SV
7540 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
7541 vcpu->arch.pv.pv_unhalted)
7542 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
7543 else
7544 mp_state->mp_state = vcpu->arch.mp_state;
7545
62d9f0db
MT
7546 return 0;
7547}
7548
7549int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
7550 struct kvm_mp_state *mp_state)
7551{
bce87cce 7552 if (!lapic_in_kernel(vcpu) &&
66450a21
JK
7553 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
7554 return -EINVAL;
7555
28bf2888
DH
7556 /* INITs are latched while in SMM */
7557 if ((is_smm(vcpu) || vcpu->arch.smi_pending) &&
7558 (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED ||
7559 mp_state->mp_state == KVM_MP_STATE_INIT_RECEIVED))
7560 return -EINVAL;
7561
66450a21
JK
7562 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
7563 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
7564 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
7565 } else
7566 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 7567 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT
7568 return 0;
7569}
7570
7f3d35fd
KW
7571int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
7572 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 7573{
9d74191a 7574 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 7575 int ret;
e01c2426 7576
8ec4722d 7577 init_emulate_ctxt(vcpu);
c697518a 7578
7f3d35fd 7579 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 7580 has_error_code, error_code);
c697518a 7581
c697518a 7582 if (ret)
19d04437 7583 return EMULATE_FAIL;
37817f29 7584
9d74191a
TY
7585 kvm_rip_write(vcpu, ctxt->eip);
7586 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 7587 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 7588 return EMULATE_DONE;
37817f29
IE
7589}
7590EXPORT_SYMBOL_GPL(kvm_task_switch);
7591
f2981033
LT
7592int kvm_valid_sregs(struct kvm_vcpu *vcpu, struct kvm_sregs *sregs)
7593{
37b95951 7594 if ((sregs->efer & EFER_LME) && (sregs->cr0 & X86_CR0_PG)) {
f2981033
LT
7595 /*
7596 * When EFER.LME and CR0.PG are set, the processor is in
7597 * 64-bit mode (though maybe in a 32-bit code segment).
7598 * CR4.PAE and EFER.LMA must be set.
7599 */
37b95951 7600 if (!(sregs->cr4 & X86_CR4_PAE)
f2981033
LT
7601 || !(sregs->efer & EFER_LMA))
7602 return -EINVAL;
7603 } else {
7604 /*
7605 * Not in 64-bit mode: EFER.LMA is clear and the code
7606 * segment cannot be 64-bit.
7607 */
7608 if (sregs->efer & EFER_LMA || sregs->cs.l)
7609 return -EINVAL;
7610 }
7611
7612 return 0;
7613}
7614
b6c7a5dc
HB
7615int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
7616 struct kvm_sregs *sregs)
7617{
58cb628d 7618 struct msr_data apic_base_msr;
b6c7a5dc 7619 int mmu_reset_needed = 0;
63f42e02 7620 int pending_vec, max_bits, idx;
89a27f4d 7621 struct desc_ptr dt;
b6c7a5dc 7622
d6321d49
RK
7623 if (!guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
7624 (sregs->cr4 & X86_CR4_OSXSAVE))
6d1068b3
PM
7625 return -EINVAL;
7626
f2981033
LT
7627 if (kvm_valid_sregs(vcpu, sregs))
7628 return -EINVAL;
7629
d3802286
JM
7630 apic_base_msr.data = sregs->apic_base;
7631 apic_base_msr.host_initiated = true;
7632 if (kvm_set_apic_base(vcpu, &apic_base_msr))
6d1068b3
PM
7633 return -EINVAL;
7634
89a27f4d
GN
7635 dt.size = sregs->idt.limit;
7636 dt.address = sregs->idt.base;
b6c7a5dc 7637 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN
7638 dt.size = sregs->gdt.limit;
7639 dt.address = sregs->gdt.base;
b6c7a5dc
HB
7640 kvm_x86_ops->set_gdt(vcpu, &dt);
7641
ad312c7c 7642 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 7643 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 7644 vcpu->arch.cr3 = sregs->cr3;
aff48baa 7645 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 7646
2d3ad1f4 7647 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 7648
f6801dff 7649 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 7650 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc 7651
4d4ec087 7652 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 7653 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 7654 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 7655
fc78f519 7656 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 7657 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
b9baba86 7658 if (sregs->cr4 & (X86_CR4_OSXSAVE | X86_CR4_PKE))
00b27a3e 7659 kvm_update_cpuid(vcpu);
63f42e02
XG
7660
7661 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 7662 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 7663 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT
7664 mmu_reset_needed = 1;
7665 }
63f42e02 7666 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB
7667
7668 if (mmu_reset_needed)
7669 kvm_mmu_reset_context(vcpu);
7670
a50abc3b 7671 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN
7672 pending_vec = find_first_bit(
7673 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
7674 if (pending_vec < max_bits) {
66fd3f7f 7675 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 7676 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB
7677 }
7678
3e6e0aab
GT
7679 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
7680 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
7681 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
7682 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
7683 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
7684 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 7685
3e6e0aab
GT
7686 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
7687 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 7688
5f0269f5
ME
7689 update_cr8_intercept(vcpu);
7690
9c3e4aab 7691 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 7692 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 7693 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 7694 !is_protmode(vcpu))
9c3e4aab
MT
7695 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7696
3842d135
AK
7697 kvm_make_request(KVM_REQ_EVENT, vcpu);
7698
b6c7a5dc
HB
7699 return 0;
7700}
7701
d0bfb940
JK
7702int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
7703 struct kvm_guest_debug *dbg)
b6c7a5dc 7704{
355be0b9 7705 unsigned long rflags;
ae675ef0 7706 int i, r;
b6c7a5dc 7707
4f926bf2
JK
7708 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
7709 r = -EBUSY;
7710 if (vcpu->arch.exception.pending)
2122ff5e 7711 goto out;
4f926bf2
JK
7712 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
7713 kvm_queue_exception(vcpu, DB_VECTOR);
7714 else
7715 kvm_queue_exception(vcpu, BP_VECTOR);
7716 }
7717
91586a3b
JK
7718 /*
7719 * Read rflags as long as potentially injected trace flags are still
7720 * filtered out.
7721 */
7722 rflags = kvm_get_rflags(vcpu);
355be0b9
JK
7723
7724 vcpu->guest_debug = dbg->control;
7725 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
7726 vcpu->guest_debug = 0;
7727
7728 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK
7729 for (i = 0; i < KVM_NR_DB_REGS; ++i)
7730 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 7731 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK
7732 } else {
7733 for (i = 0; i < KVM_NR_DB_REGS; i++)
7734 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 7735 }
c8639010 7736 kvm_update_dr7(vcpu);
ae675ef0 7737
f92653ee
JK
7738 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7739 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
7740 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 7741
91586a3b
JK
7742 /*
7743 * Trigger an rflags update that will inject or remove the trace
7744 * flags.
7745 */
7746 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 7747
a96036b8 7748 kvm_x86_ops->update_bp_intercept(vcpu);
b6c7a5dc 7749
4f926bf2 7750 r = 0;
d0bfb940 7751
2122ff5e 7752out:
b6c7a5dc
HB
7753
7754 return r;
7755}
7756
8b006791
ZX
7757/*
7758 * Translate a guest virtual address to a guest physical address.
7759 */
7760int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
7761 struct kvm_translation *tr)
7762{
7763 unsigned long vaddr = tr->linear_address;
7764 gpa_t gpa;
f656ce01 7765 int idx;
8b006791 7766
f656ce01 7767 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 7768 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 7769 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX
7770 tr->physical_address = gpa;
7771 tr->valid = gpa != UNMAPPED_GVA;
7772 tr->writeable = 1;
7773 tr->usermode = 0;
8b006791
ZX
7774
7775 return 0;
7776}
7777
d0752060
HB
7778int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7779{
c47ada30 7780 struct fxregs_state *fxsave =
7366ed77 7781 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7782
d0752060
HB
7783 memcpy(fpu->fpr, fxsave->st_space, 128);
7784 fpu->fcw = fxsave->cwd;
7785 fpu->fsw = fxsave->swd;
7786 fpu->ftwx = fxsave->twd;
7787 fpu->last_opcode = fxsave->fop;
7788 fpu->last_ip = fxsave->rip;
7789 fpu->last_dp = fxsave->rdp;
7790 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
7791
d0752060
HB
7792 return 0;
7793}
7794
7795int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
7796{
c47ada30 7797 struct fxregs_state *fxsave =
7366ed77 7798 &vcpu->arch.guest_fpu.state.fxsave;
d0752060 7799
d0752060
HB
7800 memcpy(fxsave->st_space, fpu->fpr, 128);
7801 fxsave->cwd = fpu->fcw;
7802 fxsave->swd = fpu->fsw;
7803 fxsave->twd = fpu->ftwx;
7804 fxsave->fop = fpu->last_opcode;
7805 fxsave->rip = fpu->last_ip;
7806 fxsave->rdp = fpu->last_dp;
7807 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
7808
d0752060
HB
7809 return 0;
7810}
7811
0ee6a517 7812static void fx_init(struct kvm_vcpu *vcpu)
d0752060 7813{
bf935b0b 7814 fpstate_init(&vcpu->arch.guest_fpu.state);
782511b0 7815 if (boot_cpu_has(X86_FEATURE_XSAVES))
7366ed77 7816 vcpu->arch.guest_fpu.state.xsave.header.xcomp_bv =
df1daba7 7817 host_xcr0 | XSTATE_COMPACTION_ENABLED;
d0752060 7818
2acf923e
DC
7819 /*
7820 * Ensure guest xcr0 is valid for loading
7821 */
d91cab78 7822 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
2acf923e 7823
ad312c7c 7824 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 7825}
d0752060 7826
f775b13e 7827/* Swap (qemu) user FPU context for the guest FPU context. */
d0752060
HB
7828void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
7829{
f775b13e
RR
7830 preempt_disable();
7831 copy_fpregs_to_fpstate(&vcpu->arch.user_fpu);
38cfd5e3
PB
7832 /* PKRU is separately restored in kvm_x86_ops->run. */
7833 __copy_kernel_to_fpregs(&vcpu->arch.guest_fpu.state,
7834 ~XFEATURE_MASK_PKRU);
f775b13e 7835 preempt_enable();
0c04851c 7836 trace_kvm_fpu(1);
d0752060 7837}
d0752060 7838
f775b13e 7839/* When vcpu_run ends, restore user space FPU context. */
d0752060
HB
7840void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
7841{
f775b13e 7842 preempt_disable();
4f836347 7843 copy_fpregs_to_fpstate(&vcpu->arch.guest_fpu);
f775b13e
RR
7844 copy_kernel_to_fpregs(&vcpu->arch.user_fpu.state);
7845 preempt_enable();
f096ed85 7846 ++vcpu->stat.fpu_reload;
0c04851c 7847 trace_kvm_fpu(0);
d0752060 7848}
e9b11c17
ZX
7849
7850void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
7851{
bd768e14
IY
7852 void *wbinvd_dirty_mask = vcpu->arch.wbinvd_dirty_mask;
7853
12f9a48f 7854 kvmclock_reset(vcpu);
7f1ea208 7855
e9b11c17 7856 kvm_x86_ops->vcpu_free(vcpu);
bd768e14 7857 free_cpumask_var(wbinvd_dirty_mask);
e9b11c17
ZX
7858}
7859
7860struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
7861 unsigned int id)
7862{
c447e76b
LL
7863 struct kvm_vcpu *vcpu;
7864
6755bae8
ZA
7865 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
7866 printk_once(KERN_WARNING
7867 "kvm: SMP vm created on host with unstable TSC; "
7868 "guest TSC will not be reliable\n");
c447e76b
LL
7869
7870 vcpu = kvm_x86_ops->vcpu_create(kvm, id);
7871
c447e76b 7872 return vcpu;
26e5215f 7873}
e9b11c17 7874
26e5215f
AK
7875int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
7876{
7877 int r;
e9b11c17 7878
19efffa2 7879 kvm_vcpu_mtrr_init(vcpu);
9fc77441
MT
7880 r = vcpu_load(vcpu);
7881 if (r)
7882 return r;
d28bc9dd 7883 kvm_vcpu_reset(vcpu, false);
8a3c1a33 7884 kvm_mmu_setup(vcpu);
e9b11c17 7885 vcpu_put(vcpu);
26e5215f 7886 return r;
e9b11c17
ZX
7887}
7888
31928aa5 7889void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
42897d86 7890{
8fe8ab46 7891 struct msr_data msr;
332967a3 7892 struct kvm *kvm = vcpu->kvm;
42897d86 7893
d3457c87
RK
7894 kvm_hv_vcpu_postcreate(vcpu);
7895
31928aa5
DD
7896 if (vcpu_load(vcpu))
7897 return;
8fe8ab46
WA
7898 msr.data = 0x0;
7899 msr.index = MSR_IA32_TSC;
7900 msr.host_initiated = true;
7901 kvm_write_tsc(vcpu, &msr);
42897d86
MT
7902 vcpu_put(vcpu);
7903
630994b3
MT
7904 if (!kvmclock_periodic_sync)
7905 return;
7906
332967a3
AJ
7907 schedule_delayed_work(&kvm->arch.kvmclock_sync_work,
7908 KVMCLOCK_SYNC_PERIOD);
42897d86
MT
7909}
7910
d40ccc62 7911void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 7912{
9fc77441 7913 int r;
344d9588
GN
7914 vcpu->arch.apf.msr_val = 0;
7915
9fc77441
MT
7916 r = vcpu_load(vcpu);
7917 BUG_ON(r);
e9b11c17
ZX
7918 kvm_mmu_unload(vcpu);
7919 vcpu_put(vcpu);
7920
7921 kvm_x86_ops->vcpu_free(vcpu);
7922}
7923
d28bc9dd 7924void kvm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e9b11c17 7925{
a04c389c
RK
7926 kvm_lapic_reset(vcpu, init_event);
7927
e69fab5d
PB
7928 vcpu->arch.hflags = 0;
7929
c43203ca 7930 vcpu->arch.smi_pending = 0;
7460fb4a
AK
7931 atomic_set(&vcpu->arch.nmi_queued, 0);
7932 vcpu->arch.nmi_pending = 0;
448fa4a9 7933 vcpu->arch.nmi_injected = false;
5f7552d4
NA
7934 kvm_clear_interrupt_queue(vcpu);
7935 kvm_clear_exception_queue(vcpu);
664f8e26 7936 vcpu->arch.exception.pending = false;
448fa4a9 7937
42dbaa5a 7938 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
ae561ede 7939 kvm_update_dr0123(vcpu);
6f43ed01 7940 vcpu->arch.dr6 = DR6_INIT;
73aaf249 7941 kvm_update_dr6(vcpu);
42dbaa5a 7942 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 7943 kvm_update_dr7(vcpu);
42dbaa5a 7944
1119022c
NA
7945 vcpu->arch.cr2 = 0;
7946
3842d135 7947 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 7948 vcpu->arch.apf.msr_val = 0;
c9aaa895 7949 vcpu->arch.st.msr_val = 0;
3842d135 7950
12f9a48f
GC
7951 kvmclock_reset(vcpu);
7952
af585b92
GN
7953 kvm_clear_async_pf_completion_queue(vcpu);
7954 kvm_async_pf_hash_reset(vcpu);
7955 vcpu->arch.apf.halted = false;
3842d135 7956
a554d207
WL
7957 if (kvm_mpx_supported()) {
7958 void *mpx_state_buffer;
7959
7960 /*
7961 * To avoid have the INIT path from kvm_apic_has_events() that be
7962 * called with loaded FPU and does not let userspace fix the state.
7963 */
f775b13e
RR
7964 if (init_event)
7965 kvm_put_guest_fpu(vcpu);
a554d207
WL
7966 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7967 XFEATURE_MASK_BNDREGS);
7968 if (mpx_state_buffer)
7969 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndreg_state));
7970 mpx_state_buffer = get_xsave_addr(&vcpu->arch.guest_fpu.state.xsave,
7971 XFEATURE_MASK_BNDCSR);
7972 if (mpx_state_buffer)
7973 memset(mpx_state_buffer, 0, sizeof(struct mpx_bndcsr));
f775b13e
RR
7974 if (init_event)
7975 kvm_load_guest_fpu(vcpu);
a554d207
WL
7976 }
7977
64d60670 7978 if (!init_event) {
d28bc9dd 7979 kvm_pmu_reset(vcpu);
64d60670 7980 vcpu->arch.smbase = 0x30000;
db2336a8
KH
7981
7982 vcpu->arch.msr_platform_info = MSR_PLATFORM_INFO_CPUID_FAULT;
7983 vcpu->arch.msr_misc_features_enables = 0;
a554d207
WL
7984
7985 vcpu->arch.xcr0 = XFEATURE_MASK_FP;
64d60670 7986 }
f5132b01 7987
66f7b72e
JS
7988 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
7989 vcpu->arch.regs_avail = ~0;
7990 vcpu->arch.regs_dirty = ~0;
7991
a554d207
WL
7992 vcpu->arch.ia32_xss = 0;
7993
d28bc9dd 7994 kvm_x86_ops->vcpu_reset(vcpu, init_event);
e9b11c17
ZX
7995}
7996
2b4a273b 7997void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
66450a21
JK
7998{
7999 struct kvm_segment cs;
8000
8001 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
8002 cs.selector = vector << 8;
8003 cs.base = vector << 12;
8004 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
8005 kvm_rip_write(vcpu, 0);
e9b11c17
ZX
8006}
8007
13a34e06 8008int kvm_arch_hardware_enable(void)
e9b11c17 8009{
ca84d1a2
ZA
8010 struct kvm *kvm;
8011 struct kvm_vcpu *vcpu;
8012 int i;
0dd6a6ed
ZA
8013 int ret;
8014 u64 local_tsc;
8015 u64 max_tsc = 0;
8016 bool stable, backwards_tsc = false;
18863bdd
AK
8017
8018 kvm_shared_msr_cpu_online();
13a34e06 8019 ret = kvm_x86_ops->hardware_enable();
0dd6a6ed
ZA
8020 if (ret != 0)
8021 return ret;
8022
4ea1636b 8023 local_tsc = rdtsc();
0dd6a6ed
ZA
8024 stable = !check_tsc_unstable();
8025 list_for_each_entry(kvm, &vm_list, vm_list) {
8026 kvm_for_each_vcpu(i, vcpu, kvm) {
8027 if (!stable && vcpu->cpu == smp_processor_id())
105b21bb 8028 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
0dd6a6ed
ZA
8029 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
8030 backwards_tsc = true;
8031 if (vcpu->arch.last_host_tsc > max_tsc)
8032 max_tsc = vcpu->arch.last_host_tsc;
8033 }
8034 }
8035 }
8036
8037 /*
8038 * Sometimes, even reliable TSCs go backwards. This happens on
8039 * platforms that reset TSC during suspend or hibernate actions, but
8040 * maintain synchronization. We must compensate. Fortunately, we can
8041 * detect that condition here, which happens early in CPU bringup,
8042 * before any KVM threads can be running. Unfortunately, we can't
8043 * bring the TSCs fully up to date with real time, as we aren't yet far
8044 * enough into CPU bringup that we know how much real time has actually
108b249c 8045 * elapsed; our helper function, ktime_get_boot_ns() will be using boot
0dd6a6ed
ZA
8046 * variables that haven't been updated yet.
8047 *
8048 * So we simply find the maximum observed TSC above, then record the
8049 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
8050 * the adjustment will be applied. Note that we accumulate
8051 * adjustments, in case multiple suspend cycles happen before some VCPU
8052 * gets a chance to run again. In the event that no KVM threads get a
8053 * chance to run, we will miss the entire elapsed period, as we'll have
8054 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
8055 * loose cycle time. This isn't too big a deal, since the loss will be
8056 * uniform across all VCPUs (not to mention the scenario is extremely
8057 * unlikely). It is possible that a second hibernate recovery happens
8058 * much faster than a first, causing the observed TSC here to be
8059 * smaller; this would require additional padding adjustment, which is
8060 * why we set last_host_tsc to the local tsc observed here.
8061 *
8062 * N.B. - this code below runs only on platforms with reliable TSC,
8063 * as that is the only way backwards_tsc is set above. Also note
8064 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
8065 * have the same delta_cyc adjustment applied if backwards_tsc
8066 * is detected. Note further, this adjustment is only done once,
8067 * as we reset last_host_tsc on all VCPUs to stop this from being
8068 * called multiple times (one for each physical CPU bringup).
8069 *
4a969980 8070 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA
8071 * will be compensated by the logic in vcpu_load, which sets the TSC to
8072 * catchup mode. This will catchup all VCPUs to real time, but cannot
8073 * guarantee that they stay in perfect synchronization.
8074 */
8075 if (backwards_tsc) {
8076 u64 delta_cyc = max_tsc - local_tsc;
8077 list_for_each_entry(kvm, &vm_list, vm_list) {
a826faf1 8078 kvm->arch.backwards_tsc_observed = true;
0dd6a6ed
ZA
8079 kvm_for_each_vcpu(i, vcpu, kvm) {
8080 vcpu->arch.tsc_offset_adjustment += delta_cyc;
8081 vcpu->arch.last_host_tsc = local_tsc;
105b21bb 8082 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
0dd6a6ed
ZA
8083 }
8084
8085 /*
8086 * We have to disable TSC offset matching.. if you were
8087 * booting a VM while issuing an S4 host suspend....
8088 * you may have some problem. Solving this issue is
8089 * left as an exercise to the reader.
8090 */
8091 kvm->arch.last_tsc_nsec = 0;
8092 kvm->arch.last_tsc_write = 0;
8093 }
8094
8095 }
8096 return 0;
e9b11c17
ZX
8097}
8098
13a34e06 8099void kvm_arch_hardware_disable(void)
e9b11c17 8100{
13a34e06
RK
8101 kvm_x86_ops->hardware_disable();
8102 drop_user_return_notifiers();
e9b11c17
ZX
8103}
8104
8105int kvm_arch_hardware_setup(void)
8106{
9e9c3fe4
NA
8107 int r;
8108
8109 r = kvm_x86_ops->hardware_setup();
8110 if (r != 0)
8111 return r;
8112
35181e86
HZ
8113 if (kvm_has_tsc_control) {
8114 /*
8115 * Make sure the user can only configure tsc_khz values that
8116 * fit into a signed integer.
8117 * A min value is not calculated needed because it will always
8118 * be 1 on all machines.
8119 */
8120 u64 max = min(0x7fffffffULL,
8121 __scale_tsc(kvm_max_tsc_scaling_ratio, tsc_khz));
8122 kvm_max_guest_tsc_khz = max;
8123
ad721883 8124 kvm_default_tsc_scaling_ratio = 1ULL << kvm_tsc_scaling_ratio_frac_bits;
35181e86 8125 }
ad721883 8126
9e9c3fe4
NA
8127 kvm_init_msr_list();
8128 return 0;
e9b11c17
ZX
8129}
8130
8131void kvm_arch_hardware_unsetup(void)
8132{
8133 kvm_x86_ops->hardware_unsetup();
8134}
8135
8136void kvm_arch_check_processor_compat(void *rtn)
8137{
8138 kvm_x86_ops->check_processor_compatibility(rtn);
d71ba788
PB
8139}
8140
8141bool kvm_vcpu_is_reset_bsp(struct kvm_vcpu *vcpu)
8142{
8143 return vcpu->kvm->arch.bsp_vcpu_id == vcpu->vcpu_id;
8144}
8145EXPORT_SYMBOL_GPL(kvm_vcpu_is_reset_bsp);
8146
8147bool kvm_vcpu_is_bsp(struct kvm_vcpu *vcpu)
8148{
8149 return (vcpu->arch.apic_base & MSR_IA32_APICBASE_BSP) != 0;
e9b11c17
ZX
8150}
8151
54e9818f 8152struct static_key kvm_no_apic_vcpu __read_mostly;
bce87cce 8153EXPORT_SYMBOL_GPL(kvm_no_apic_vcpu);
54e9818f 8154
e9b11c17
ZX
8155int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
8156{
8157 struct page *page;
e9b11c17
ZX
8158 int r;
8159
b2a05fef 8160 vcpu->arch.apicv_active = kvm_x86_ops->get_enable_apicv(vcpu);
9aabc88f 8161 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
26de7988 8162 if (!irqchip_in_kernel(vcpu->kvm) || kvm_vcpu_is_reset_bsp(vcpu))
a4535290 8163 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 8164 else
a4535290 8165 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX
8166
8167 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
8168 if (!page) {
8169 r = -ENOMEM;
8170 goto fail;
8171 }
ad312c7c 8172 vcpu->arch.pio_data = page_address(page);
e9b11c17 8173
cc578287 8174 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 8175
e9b11c17
ZX
8176 r = kvm_mmu_create(vcpu);
8177 if (r < 0)
8178 goto fail_free_pio_data;
8179
26de7988 8180 if (irqchip_in_kernel(vcpu->kvm)) {
e9b11c17
ZX
8181 r = kvm_create_lapic(vcpu);
8182 if (r < 0)
8183 goto fail_mmu_destroy;
54e9818f
GN
8184 } else
8185 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 8186
890ca9ae
HY
8187 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
8188 GFP_KERNEL);
8189 if (!vcpu->arch.mce_banks) {
8190 r = -ENOMEM;
443c39bc 8191 goto fail_free_lapic;
890ca9ae
HY
8192 }
8193 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
8194
f1797359
WY
8195 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
8196 r = -ENOMEM;
f5f48ee1 8197 goto fail_free_mce_banks;
f1797359 8198 }
f5f48ee1 8199
0ee6a517 8200 fx_init(vcpu);
66f7b72e 8201
4344ee98 8202 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 8203
5a4f55cd
EK
8204 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu);
8205
74545705
RK
8206 vcpu->arch.pat = MSR_IA32_CR_PAT_DEFAULT;
8207
af585b92 8208 kvm_async_pf_hash_reset(vcpu);
f5132b01 8209 kvm_pmu_init(vcpu);
af585b92 8210
1c1a9ce9 8211 vcpu->arch.pending_external_vector = -1;
de63ad4c 8212 vcpu->arch.preempted_in_kernel = false;
1c1a9ce9 8213
5c919412
AS
8214 kvm_hv_vcpu_init(vcpu);
8215
e9b11c17 8216 return 0;
0ee6a517 8217
f5f48ee1
SY
8218fail_free_mce_banks:
8219 kfree(vcpu->arch.mce_banks);
443c39bc
WY
8220fail_free_lapic:
8221 kvm_free_lapic(vcpu);
e9b11c17
ZX
8222fail_mmu_destroy:
8223 kvm_mmu_destroy(vcpu);
8224fail_free_pio_data:
ad312c7c 8225 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX
8226fail:
8227 return r;
8228}
8229
8230void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
8231{
f656ce01
MT
8232 int idx;
8233
1f4b34f8 8234 kvm_hv_vcpu_uninit(vcpu);
f5132b01 8235 kvm_pmu_destroy(vcpu);
36cb93fd 8236 kfree(vcpu->arch.mce_banks);
e9b11c17 8237 kvm_free_lapic(vcpu);
f656ce01 8238 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 8239 kvm_mmu_destroy(vcpu);
f656ce01 8240 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 8241 free_page((unsigned long)vcpu->arch.pio_data);
35754c98 8242 if (!lapic_in_kernel(vcpu))
54e9818f 8243 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 8244}
d19a9cd2 8245
e790d9ef
RK
8246void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu)
8247{
f0ace387 8248 vcpu->arch.l1tf_flush_l1d = true;
ae97a3b8 8249 kvm_x86_ops->sched_in(vcpu, cpu);
e790d9ef
RK
8250}
8251
e08b9637 8252int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 8253{
e08b9637
CO
8254 if (type)
8255 return -EINVAL;
8256
6ef768fa 8257 INIT_HLIST_HEAD(&kvm->arch.mask_notifier_list);
f05e70ac 8258 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 8259 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 8260 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 8261 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 8262
5550af4d
SY
8263 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
8264 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW
8265 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
8266 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
8267 &kvm->arch.irq_sources_bitmap);
5550af4d 8268
038f8c11 8269 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 8270 mutex_init(&kvm->arch.apic_map_lock);
3f5ad8be 8271 mutex_init(&kvm->arch.hyperv.hv_lock);
d828199e
MT
8272 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
8273
108b249c 8274 kvm->arch.kvmclock_offset = -ktime_get_boot_ns();
d828199e 8275 pvclock_update_vm_gtod_copy(kvm);
53f658b3 8276
7e44e449 8277 INIT_DELAYED_WORK(&kvm->arch.kvmclock_update_work, kvmclock_update_fn);
332967a3 8278 INIT_DELAYED_WORK(&kvm->arch.kvmclock_sync_work, kvmclock_sync_fn);
7e44e449 8279
0eb05bf2 8280 kvm_page_track_init(kvm);
13d268ca 8281 kvm_mmu_init_vm(kvm);
0eb05bf2 8282
03543133
SS
8283 if (kvm_x86_ops->vm_init)
8284 return kvm_x86_ops->vm_init(kvm);
8285
d89f5eff 8286 return 0;
d19a9cd2
ZX
8287}
8288
8289static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
8290{
9fc77441
MT
8291 int r;
8292 r = vcpu_load(vcpu);
8293 BUG_ON(r);
d19a9cd2
ZX
8294 kvm_mmu_unload(vcpu);
8295 vcpu_put(vcpu);
8296}
8297
8298static void kvm_free_vcpus(struct kvm *kvm)
8299{
8300 unsigned int i;
988a2cae 8301 struct kvm_vcpu *vcpu;
d19a9cd2
ZX
8302
8303 /*
8304 * Unpin any mmu pages first.
8305 */
af585b92
GN
8306 kvm_for_each_vcpu(i, vcpu, kvm) {
8307 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 8308 kvm_unload_vcpu_mmu(vcpu);
af585b92 8309 }
988a2cae
GN
8310 kvm_for_each_vcpu(i, vcpu, kvm)
8311 kvm_arch_vcpu_free(vcpu);
8312
8313 mutex_lock(&kvm->lock);
8314 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
8315 kvm->vcpus[i] = NULL;
d19a9cd2 8316
988a2cae
GN
8317 atomic_set(&kvm->online_vcpus, 0);
8318 mutex_unlock(&kvm->lock);
d19a9cd2
ZX
8319}
8320
ad8ba2cd
SY
8321void kvm_arch_sync_events(struct kvm *kvm)
8322{
332967a3 8323 cancel_delayed_work_sync(&kvm->arch.kvmclock_sync_work);
7e44e449 8324 cancel_delayed_work_sync(&kvm->arch.kvmclock_update_work);
aea924f6 8325 kvm_free_pit(kvm);
ad8ba2cd
SY
8326}
8327
1d8007bd 8328int __x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB
8329{
8330 int i, r;
25188b99 8331 unsigned long hva;
f0d648bd
PB
8332 struct kvm_memslots *slots = kvm_memslots(kvm);
8333 struct kvm_memory_slot *slot, old;
9da0e4d5
PB
8334
8335 /* Called with kvm->slots_lock held. */
1d8007bd
PB
8336 if (WARN_ON(id >= KVM_MEM_SLOTS_NUM))
8337 return -EINVAL;
9da0e4d5 8338
f0d648bd
PB
8339 slot = id_to_memslot(slots, id);
8340 if (size) {
b21629da 8341 if (slot->npages)
f0d648bd
PB
8342 return -EEXIST;
8343
8344 /*
8345 * MAP_SHARED to prevent internal slot pages from being moved
8346 * by fork()/COW.
8347 */
8348 hva = vm_mmap(NULL, 0, size, PROT_READ | PROT_WRITE,
8349 MAP_SHARED | MAP_ANONYMOUS, 0);
8350 if (IS_ERR((void *)hva))
8351 return PTR_ERR((void *)hva);
8352 } else {
8353 if (!slot->npages)
8354 return 0;
8355
8356 hva = 0;
8357 }
8358
8359 old = *slot;
9da0e4d5 8360 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
1d8007bd 8361 struct kvm_userspace_memory_region m;
9da0e4d5 8362
1d8007bd
PB
8363 m.slot = id | (i << 16);
8364 m.flags = 0;
8365 m.guest_phys_addr = gpa;
f0d648bd 8366 m.userspace_addr = hva;
1d8007bd 8367 m.memory_size = size;
9da0e4d5
PB
8368 r = __kvm_set_memory_region(kvm, &m);
8369 if (r < 0)
8370 return r;
8371 }
8372
55a4a47b
EB
8373 if (!size)
8374 vm_munmap(old.userspace_addr, old.npages * PAGE_SIZE);
f0d648bd 8375
9da0e4d5
PB
8376 return 0;
8377}
8378EXPORT_SYMBOL_GPL(__x86_set_memory_region);
8379
1d8007bd 8380int x86_set_memory_region(struct kvm *kvm, int id, gpa_t gpa, u32 size)
9da0e4d5
PB
8381{
8382 int r;
8383
8384 mutex_lock(&kvm->slots_lock);
1d8007bd 8385 r = __x86_set_memory_region(kvm, id, gpa, size);
9da0e4d5
PB
8386 mutex_unlock(&kvm->slots_lock);
8387
8388 return r;
8389}
8390EXPORT_SYMBOL_GPL(x86_set_memory_region);
8391
d19a9cd2
ZX
8392void kvm_arch_destroy_vm(struct kvm *kvm)
8393{
27469d29
AH
8394 if (current->mm == kvm->mm) {
8395 /*
8396 * Free memory regions allocated on behalf of userspace,
8397 * unless the the memory map has changed due to process exit
8398 * or fd copying.
8399 */
1d8007bd
PB
8400 x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
8401 x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 0, 0);
8402 x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, 0, 0);
27469d29 8403 }
03543133
SS
8404 if (kvm_x86_ops->vm_destroy)
8405 kvm_x86_ops->vm_destroy(kvm);
c761159c
PX
8406 kvm_pic_destroy(kvm);
8407 kvm_ioapic_destroy(kvm);
d19a9cd2 8408 kvm_free_vcpus(kvm);
af1bae54 8409 kvfree(rcu_dereference_check(kvm->arch.apic_map, 1));
13d268ca 8410 kvm_mmu_uninit_vm(kvm);
2beb6dad 8411 kvm_page_track_cleanup(kvm);
d19a9cd2 8412}
0de10343 8413
5587027c 8414void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY
8415 struct kvm_memory_slot *dont)
8416{
8417 int i;
8418
d89cc617
TY
8419 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
8420 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
548ef284 8421 kvfree(free->arch.rmap[i]);
d89cc617 8422 free->arch.rmap[i] = NULL;
77d11309 8423 }
d89cc617
TY
8424 if (i == 0)
8425 continue;
8426
8427 if (!dont || free->arch.lpage_info[i - 1] !=
8428 dont->arch.lpage_info[i - 1]) {
548ef284 8429 kvfree(free->arch.lpage_info[i - 1]);
d89cc617 8430 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY
8431 }
8432 }
21ebbeda
XG
8433
8434 kvm_page_track_free_memslot(free, dont);
db3fe4eb
TY
8435}
8436
5587027c
AK
8437int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
8438 unsigned long npages)
db3fe4eb
TY
8439{
8440 int i;
8441
d89cc617 8442 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
92f94f1e 8443 struct kvm_lpage_info *linfo;
db3fe4eb
TY
8444 unsigned long ugfn;
8445 int lpages;
d89cc617 8446 int level = i + 1;
db3fe4eb
TY
8447
8448 lpages = gfn_to_index(slot->base_gfn + npages - 1,
8449 slot->base_gfn, level) + 1;
8450
d89cc617 8451 slot->arch.rmap[i] =
a7c3e901 8452 kvzalloc(lpages * sizeof(*slot->arch.rmap[i]), GFP_KERNEL);
d89cc617 8453 if (!slot->arch.rmap[i])
77d11309 8454 goto out_free;
d89cc617
TY
8455 if (i == 0)
8456 continue;
77d11309 8457
a7c3e901 8458 linfo = kvzalloc(lpages * sizeof(*linfo), GFP_KERNEL);
92f94f1e 8459 if (!linfo)
db3fe4eb
TY
8460 goto out_free;
8461
92f94f1e
XG
8462 slot->arch.lpage_info[i - 1] = linfo;
8463
db3fe4eb 8464 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8465 linfo[0].disallow_lpage = 1;
db3fe4eb 8466 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
92f94f1e 8467 linfo[lpages - 1].disallow_lpage = 1;
db3fe4eb
TY
8468 ugfn = slot->userspace_addr >> PAGE_SHIFT;
8469 /*
8470 * If the gfn and userspace address are not aligned wrt each
8471 * other, or if explicitly asked to, disable large page
8472 * support for this slot
8473 */
8474 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
8475 !kvm_largepages_enabled()) {
8476 unsigned long j;
8477
8478 for (j = 0; j < lpages; ++j)
92f94f1e 8479 linfo[j].disallow_lpage = 1;
db3fe4eb
TY
8480 }
8481 }
8482
21ebbeda
XG
8483 if (kvm_page_track_create_memslot(slot, npages))
8484 goto out_free;
8485
db3fe4eb
TY
8486 return 0;
8487
8488out_free:
d89cc617 8489 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
548ef284 8490 kvfree(slot->arch.rmap[i]);
d89cc617
TY
8491 slot->arch.rmap[i] = NULL;
8492 if (i == 0)
8493 continue;
8494
548ef284 8495 kvfree(slot->arch.lpage_info[i - 1]);
d89cc617 8496 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY
8497 }
8498 return -ENOMEM;
8499}
8500
15f46015 8501void kvm_arch_memslots_updated(struct kvm *kvm, struct kvm_memslots *slots)
e59dbe09 8502{
e6dff7d1
TY
8503 /*
8504 * memslots->generation has been incremented.
8505 * mmio generation may have reached its maximum value.
8506 */
54bf36aa 8507 kvm_mmu_invalidate_mmio_sptes(kvm, slots);
e59dbe09
TY
8508}
8509
f7784b8e
MT
8510int kvm_arch_prepare_memory_region(struct kvm *kvm,
8511 struct kvm_memory_slot *memslot,
09170a49 8512 const struct kvm_userspace_memory_region *mem,
7b6195a9 8513 enum kvm_mr_change change)
0de10343 8514{
f7784b8e
MT
8515 return 0;
8516}
8517
88178fd4
KH
8518static void kvm_mmu_slot_apply_flags(struct kvm *kvm,
8519 struct kvm_memory_slot *new)
8520{
8521 /* Still write protect RO slot */
8522 if (new->flags & KVM_MEM_READONLY) {
8523 kvm_mmu_slot_remove_write_access(kvm, new);
8524 return;
8525 }
8526
8527 /*
8528 * Call kvm_x86_ops dirty logging hooks when they are valid.
8529 *
8530 * kvm_x86_ops->slot_disable_log_dirty is called when:
8531 *
8532 * - KVM_MR_CREATE with dirty logging is disabled
8533 * - KVM_MR_FLAGS_ONLY with dirty logging is disabled in new flag
8534 *
8535 * The reason is, in case of PML, we need to set D-bit for any slots
8536 * with dirty logging disabled in order to eliminate unnecessary GPA
8537 * logging in PML buffer (and potential PML buffer full VMEXT). This
8538 * guarantees leaving PML enabled during guest's lifetime won't have
8539 * any additonal overhead from PML when guest is running with dirty
8540 * logging disabled for memory slots.
8541 *
8542 * kvm_x86_ops->slot_enable_log_dirty is called when switching new slot
8543 * to dirty logging mode.
8544 *
8545 * If kvm_x86_ops dirty logging hooks are invalid, use write protect.
8546 *
8547 * In case of write protect:
8548 *
8549 * Write protect all pages for dirty logging.
8550 *
8551 * All the sptes including the large sptes which point to this
8552 * slot are set to readonly. We can not create any new large
8553 * spte on this slot until the end of the logging.
8554 *
8555 * See the comments in fast_page_fault().
8556 */
8557 if (new->flags & KVM_MEM_LOG_DIRTY_PAGES) {
8558 if (kvm_x86_ops->slot_enable_log_dirty)
8559 kvm_x86_ops->slot_enable_log_dirty(kvm, new);
8560 else
8561 kvm_mmu_slot_remove_write_access(kvm, new);
8562 } else {
8563 if (kvm_x86_ops->slot_disable_log_dirty)
8564 kvm_x86_ops->slot_disable_log_dirty(kvm, new);
8565 }
8566}
8567
f7784b8e 8568void kvm_arch_commit_memory_region(struct kvm *kvm,
09170a49 8569 const struct kvm_userspace_memory_region *mem,
8482644a 8570 const struct kvm_memory_slot *old,
f36f3f28 8571 const struct kvm_memory_slot *new,
8482644a 8572 enum kvm_mr_change change)
f7784b8e 8573{
8482644a 8574 int nr_mmu_pages = 0;
f7784b8e 8575
48c0e4e9
XG
8576 if (!kvm->arch.n_requested_mmu_pages)
8577 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
8578
48c0e4e9 8579 if (nr_mmu_pages)
0de10343 8580 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
1c91cad4 8581
3ea3b7fa
WL
8582 /*
8583 * Dirty logging tracks sptes in 4k granularity, meaning that large
8584 * sptes have to be split. If live migration is successful, the guest
8585 * in the source machine will be destroyed and large sptes will be
8586 * created in the destination. However, if the guest continues to run
8587 * in the source machine (for example if live migration fails), small
8588 * sptes will remain around and cause bad performance.
8589 *
8590 * Scan sptes if dirty logging has been stopped, dropping those
8591 * which can be collapsed into a single large-page spte. Later
8592 * page faults will create the large-page sptes.
8593 */
8594 if ((change != KVM_MR_DELETE) &&
8595 (old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
8596 !(new->flags & KVM_MEM_LOG_DIRTY_PAGES))
8597 kvm_mmu_zap_collapsible_sptes(kvm, new);
8598
c972f3b1 8599 /*
88178fd4 8600 * Set up write protection and/or dirty logging for the new slot.
c126d94f 8601 *
88178fd4
KH
8602 * For KVM_MR_DELETE and KVM_MR_MOVE, the shadow pages of old slot have
8603 * been zapped so no dirty logging staff is needed for old slot. For
8604 * KVM_MR_FLAGS_ONLY, the old slot is essentially the same one as the
8605 * new and it's also covered when dealing with the new slot.
f36f3f28
PB
8606 *
8607 * FIXME: const-ify all uses of struct kvm_memory_slot.
c972f3b1 8608 */
88178fd4 8609 if (change != KVM_MR_DELETE)
f36f3f28 8610 kvm_mmu_slot_apply_flags(kvm, (struct kvm_memory_slot *) new);
0de10343 8611}
1d737c8a 8612
2df72e9b 8613void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 8614{
6ca18b69 8615 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT
8616}
8617
2df72e9b
MT
8618void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
8619 struct kvm_memory_slot *slot)
8620{
ae7cd873 8621 kvm_page_track_flush_slot(kvm, slot);
2df72e9b
MT
8622}
8623
5d9bc648
PB
8624static inline bool kvm_vcpu_has_events(struct kvm_vcpu *vcpu)
8625{
8626 if (!list_empty_careful(&vcpu->async_pf.done))
8627 return true;
8628
8629 if (kvm_apic_has_events(vcpu))
8630 return true;
8631
8632 if (vcpu->arch.pv.pv_unhalted)
8633 return true;
8634
a5f01f8e
WL
8635 if (vcpu->arch.exception.pending)
8636 return true;
8637
47a66eed
Z
8638 if (kvm_test_request(KVM_REQ_NMI, vcpu) ||
8639 (vcpu->arch.nmi_pending &&
8640 kvm_x86_ops->nmi_allowed(vcpu)))
5d9bc648
PB
8641 return true;
8642
47a66eed
Z
8643 if (kvm_test_request(KVM_REQ_SMI, vcpu) ||
8644 (vcpu->arch.smi_pending && !is_smm(vcpu)))
73917739
PB
8645 return true;
8646
5d9bc648
PB
8647 if (kvm_arch_interrupt_allowed(vcpu) &&
8648 kvm_cpu_has_interrupt(vcpu))
8649 return true;
8650
1f4b34f8
AS
8651 if (kvm_hv_has_stimer_pending(vcpu))
8652 return true;
8653
5d9bc648
PB
8654 return false;
8655}
8656
1d737c8a
ZX
8657int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
8658{
5d9bc648 8659 return kvm_vcpu_running(vcpu) || kvm_vcpu_has_events(vcpu);
1d737c8a 8660}
5736199a 8661
199b5763
LM
8662bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
8663{
de63ad4c 8664 return vcpu->arch.preempted_in_kernel;
199b5763
LM
8665}
8666
b6d33834 8667int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 8668{
b6d33834 8669 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 8670}
78646121
GN
8671
8672int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
8673{
8674 return kvm_x86_ops->interrupt_allowed(vcpu);
8675}
229456fc 8676
82b32774 8677unsigned long kvm_get_linear_rip(struct kvm_vcpu *vcpu)
f92653ee 8678{
82b32774
NA
8679 if (is_64_bit_mode(vcpu))
8680 return kvm_rip_read(vcpu);
8681 return (u32)(get_segment_base(vcpu, VCPU_SREG_CS) +
8682 kvm_rip_read(vcpu));
8683}
8684EXPORT_SYMBOL_GPL(kvm_get_linear_rip);
f92653ee 8685
82b32774
NA
8686bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
8687{
8688 return kvm_get_linear_rip(vcpu) == linear_rip;
f92653ee
JK
8689}
8690EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
8691
94fe45da
JK
8692unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
8693{
8694 unsigned long rflags;
8695
8696 rflags = kvm_x86_ops->get_rflags(vcpu);
8697 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 8698 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK
8699 return rflags;
8700}
8701EXPORT_SYMBOL_GPL(kvm_get_rflags);
8702
6addfc42 8703static void __kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
94fe45da
JK
8704{
8705 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 8706 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 8707 rflags |= X86_EFLAGS_TF;
94fe45da 8708 kvm_x86_ops->set_rflags(vcpu, rflags);
6addfc42
PB
8709}
8710
8711void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
8712{
8713 __kvm_set_rflags(vcpu, rflags);
3842d135 8714 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK
8715}
8716EXPORT_SYMBOL_GPL(kvm_set_rflags);
8717
56028d08
GN
8718void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
8719{
8720 int r;
8721
fb67e14f 8722 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 8723 work->wakeup_all)
56028d08
GN
8724 return;
8725
8726 r = kvm_mmu_reload(vcpu);
8727 if (unlikely(r))
8728 return;
8729
fb67e14f
XG
8730 if (!vcpu->arch.mmu.direct_map &&
8731 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
8732 return;
8733
56028d08
GN
8734 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
8735}
8736
af585b92
GN
8737static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
8738{
8739 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
8740}
8741
8742static inline u32 kvm_async_pf_next_probe(u32 key)
8743{
8744 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
8745}
8746
8747static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8748{
8749 u32 key = kvm_async_pf_hash_fn(gfn);
8750
8751 while (vcpu->arch.apf.gfns[key] != ~0)
8752 key = kvm_async_pf_next_probe(key);
8753
8754 vcpu->arch.apf.gfns[key] = gfn;
8755}
8756
8757static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
8758{
8759 int i;
8760 u32 key = kvm_async_pf_hash_fn(gfn);
8761
8762 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG
8763 (vcpu->arch.apf.gfns[key] != gfn &&
8764 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN
8765 key = kvm_async_pf_next_probe(key);
8766
8767 return key;
8768}
8769
8770bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8771{
8772 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
8773}
8774
8775static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
8776{
8777 u32 i, j, k;
8778
8779 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
8780 while (true) {
8781 vcpu->arch.apf.gfns[i] = ~0;
8782 do {
8783 j = kvm_async_pf_next_probe(j);
8784 if (vcpu->arch.apf.gfns[j] == ~0)
8785 return;
8786 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
8787 /*
8788 * k lies cyclically in ]i,j]
8789 * | i.k.j |
8790 * |....j i.k.| or |.k..j i...|
8791 */
8792 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
8793 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
8794 i = j;
8795 }
8796}
8797
7c90705b
GN
8798static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
8799{
4e335d9e
PB
8800
8801 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
8802 sizeof(val));
7c90705b
GN
8803}
8804
9a6e7c39
WL
8805static int apf_get_user(struct kvm_vcpu *vcpu, u32 *val)
8806{
8807
8808 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, val,
8809 sizeof(u32));
8810}
8811
af585b92
GN
8812void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
8813 struct kvm_async_pf *work)
8814{
6389ee94
AK
8815 struct x86_exception fault;
8816
7c90705b 8817 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 8818 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN
8819
8820 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN
8821 (vcpu->arch.apf.send_user_only &&
8822 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN
8823 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
8824 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK
8825 fault.vector = PF_VECTOR;
8826 fault.error_code_valid = true;
8827 fault.error_code = 0;
8828 fault.nested_page_fault = false;
8829 fault.address = work->arch.token;
adfe20fb 8830 fault.async_page_fault = true;
6389ee94 8831 kvm_inject_page_fault(vcpu, &fault);
7c90705b 8832 }
af585b92
GN
8833}
8834
8835void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
8836 struct kvm_async_pf *work)
8837{
6389ee94 8838 struct x86_exception fault;
9a6e7c39 8839 u32 val;
6389ee94 8840
f2e10669 8841 if (work->wakeup_all)
7c90705b
GN
8842 work->arch.token = ~0; /* broadcast wakeup */
8843 else
8844 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
24dccf83 8845 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7c90705b 8846
9a6e7c39
WL
8847 if (vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED &&
8848 !apf_get_user(vcpu, &val)) {
8849 if (val == KVM_PV_REASON_PAGE_NOT_PRESENT &&
8850 vcpu->arch.exception.pending &&
8851 vcpu->arch.exception.nr == PF_VECTOR &&
8852 !apf_put_user(vcpu, 0)) {
8853 vcpu->arch.exception.injected = false;
8854 vcpu->arch.exception.pending = false;
8855 vcpu->arch.exception.nr = 0;
8856 vcpu->arch.exception.has_error_code = false;
8857 vcpu->arch.exception.error_code = 0;
8858 } else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
8859 fault.vector = PF_VECTOR;
8860 fault.error_code_valid = true;
8861 fault.error_code = 0;
8862 fault.nested_page_fault = false;
8863 fault.address = work->arch.token;
8864 fault.async_page_fault = true;
8865 kvm_inject_page_fault(vcpu, &fault);
8866 }
7c90705b 8867 }
e6d53e3b 8868 vcpu->arch.apf.halted = false;
a4fa1635 8869 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN
8870}
8871
8872bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
8873{
8874 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
8875 return true;
8876 else
9bc1f09f 8877 return kvm_can_do_async_pf(vcpu);
af585b92
GN
8878}
8879
5544eb9b
PB
8880void kvm_arch_start_assignment(struct kvm *kvm)
8881{
8882 atomic_inc(&kvm->arch.assigned_device_count);
8883}
8884EXPORT_SYMBOL_GPL(kvm_arch_start_assignment);
8885
8886void kvm_arch_end_assignment(struct kvm *kvm)
8887{
8888 atomic_dec(&kvm->arch.assigned_device_count);
8889}
8890EXPORT_SYMBOL_GPL(kvm_arch_end_assignment);
8891
8892bool kvm_arch_has_assigned_device(struct kvm *kvm)
8893{
8894 return atomic_read(&kvm->arch.assigned_device_count);
8895}
8896EXPORT_SYMBOL_GPL(kvm_arch_has_assigned_device);
8897
e0f0bbc5
AW
8898void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
8899{
8900 atomic_inc(&kvm->arch.noncoherent_dma_count);
8901}
8902EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
8903
8904void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
8905{
8906 atomic_dec(&kvm->arch.noncoherent_dma_count);
8907}
8908EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
8909
8910bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
8911{
8912 return atomic_read(&kvm->arch.noncoherent_dma_count);
8913}
8914EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
8915
14717e20
AW
8916bool kvm_arch_has_irq_bypass(void)
8917{
8918 return kvm_x86_ops->update_pi_irte != NULL;
8919}
8920
87276880
FW
8921int kvm_arch_irq_bypass_add_producer(struct irq_bypass_consumer *cons,
8922 struct irq_bypass_producer *prod)
8923{
8924 struct kvm_kernel_irqfd *irqfd =
8925 container_of(cons, struct kvm_kernel_irqfd, consumer);
8926
14717e20 8927 irqfd->producer = prod;
87276880 8928
14717e20
AW
8929 return kvm_x86_ops->update_pi_irte(irqfd->kvm,
8930 prod->irq, irqfd->gsi, 1);
87276880
FW
8931}
8932
8933void kvm_arch_irq_bypass_del_producer(struct irq_bypass_consumer *cons,
8934 struct irq_bypass_producer *prod)
8935{
8936 int ret;
8937 struct kvm_kernel_irqfd *irqfd =
8938 container_of(cons, struct kvm_kernel_irqfd, consumer);
8939
87276880
FW
8940 WARN_ON(irqfd->producer != prod);
8941 irqfd->producer = NULL;
8942
8943 /*
8944 * When producer of consumer is unregistered, we change back to
8945 * remapped mode, so we can re-use the current implementation
bb3541f1 8946 * when the irq is masked/disabled or the consumer side (KVM
87276880
FW
8947 * int this case doesn't want to receive the interrupts.
8948 */
8949 ret = kvm_x86_ops->update_pi_irte(irqfd->kvm, prod->irq, irqfd->gsi, 0);
8950 if (ret)
8951 printk(KERN_INFO "irq bypass consumer (token %p) unregistration"
8952 " fails: %d\n", irqfd->consumer.token, ret);
8953}
8954
8955int kvm_arch_update_irqfd_routing(struct kvm *kvm, unsigned int host_irq,
8956 uint32_t guest_irq, bool set)
8957{
8958 if (!kvm_x86_ops->update_pi_irte)
8959 return -EINVAL;
8960
8961 return kvm_x86_ops->update_pi_irte(kvm, host_irq, guest_irq, set);
8962}
8963
52004014
FW
8964bool kvm_vector_hashing_enabled(void)
8965{
8966 return vector_hashing;
8967}
8968EXPORT_SYMBOL_GPL(kvm_vector_hashing_enabled);
8969
229456fc 8970EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
931c33b1 8971EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_fast_mmio);
229456fc
MT
8972EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
8973EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
8974EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
8975EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 8976EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 8977EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 8978EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 8979EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 8980EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 8981EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 8982EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 8983EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
7b46268d 8984EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_ple_window);
843e4330 8985EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pml_full);
efc64404 8986EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_pi_irte_update);
18f40c53
SS
8987EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_unaccelerated_access);
8988EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_avic_incomplete_ipi);