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b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
8de05535 16#include <linux/bitops.h>
b60503ba 17#include <linux/blkdev.h>
a4aea562 18#include <linux/blk-mq.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
be7b6275 36#include <linux/poison.h>
c3bfe717 37#include <linux/ptrace.h>
b60503ba
MW		 38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/types.h>
5d0f6131 41#include <scsi/sg.h>
797a796a
HM		 42#include <asm-generic/io-64-nonatomic-lo-hi.h>
43
9d43cf64 44#define NVME_Q_DEPTH 1024
a4aea562 45#define NVME_AQ_DEPTH 64
b60503ba
MW		 46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
9d43cf64 48#define ADMIN_TIMEOUT (admin_timeout * HZ)
2484f407 49#define SHUTDOWN_TIMEOUT (shutdown_timeout * HZ)
9d43cf64
KB		 50#define IOD_TIMEOUT (retry_time * HZ)
51
52static unsigned char admin_timeout = 60;
53module_param(admin_timeout, byte, 0644);
54MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 55
bd67608a
MW		 56unsigned char nvme_io_timeout = 30;
57module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 58MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 59
61e4ce08
KB		 60static unsigned char retry_time = 30;
61module_param(retry_time, byte, 0644);
62MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
63
2484f407
DM		 64static unsigned char shutdown_timeout = 5;
65module_param(shutdown_timeout, byte, 0644);
66MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown");
67
b60503ba
MW		 68static int nvme_major;
69module_param(nvme_major, int, 0);
70
58ffacb5
MW		 71static int use_threaded_interrupts;
72module_param(use_threaded_interrupts, int, 0);
73
1fa6aead
MW		 74static DEFINE_SPINLOCK(dev_list_lock);
75static LIST_HEAD(dev_list);
76static struct task_struct *nvme_thread;
9a6b9458 77static struct workqueue_struct *nvme_workq;
b9afca3e 78static wait_queue_head_t nvme_kthread_wait;
f3db22fe 79static struct notifier_block nvme_nb;
1fa6aead 80
d4b4ff8e 81static void nvme_reset_failed_dev(struct work_struct *ws);
a4aea562 82static int nvme_process_cq(struct nvme_queue *nvmeq);
d4b4ff8e 83
4d115420
KB		 84struct async_cmd_info {
85 struct kthread_work work;
86 struct kthread_worker *worker;
a4aea562 87 struct request *req;
4d115420
KB		 88 u32 result;
89 int status;
90 void *ctx;
91};
1fa6aead 92
b60503ba
MW		 93/*
94 * An NVM Express queue. Each device has at least two (one for admin
95 * commands and one for I/O commands).
96 */
97struct nvme_queue {
f435c282 98 struct llist_node node;
b60503ba 99 struct device *q_dmadev;
091b6092 100 struct nvme_dev *dev;
3193f07b 101 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 102 spinlock_t q_lock;
103 struct nvme_command *sq_cmds;
104 volatile struct nvme_completion *cqes;
105 dma_addr_t sq_dma_addr;
106 dma_addr_t cq_dma_addr;
b60503ba
MW		 107 u32 __iomem *q_db;
108 u16 q_depth;
109 u16 cq_vector;
110 u16 sq_head;
111 u16 sq_tail;
112 u16 cq_head;
c30341dc 113 u16 qid;
e9539f47
MW		 114 u8 cq_phase;
115 u8 cqe_seen;
4d115420 116 struct async_cmd_info cmdinfo;
a4aea562 117 struct blk_mq_hw_ctx *hctx;
b60503ba
MW		 118};
119
120/*
121 * Check we didin't inadvertently grow the command struct
122 */
123static inline void _nvme_check_size(void)
124{
125 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
126 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 130 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 131 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 132 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
133 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 136 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 137}
138
edd10d33 139typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 140 struct nvme_completion *);
141
e85248e5 142struct nvme_cmd_info {
c2f5b650
MW		 143 nvme_completion_fn fn;
144 void *ctx;
c30341dc 145 int aborted;
a4aea562 146 struct nvme_queue *nvmeq;
e85248e5
MW		 147};
148
a4aea562
MB		 149static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
150 unsigned int hctx_idx)
e85248e5 151{
a4aea562
MB		 152 struct nvme_dev *dev = data;
153 struct nvme_queue *nvmeq = dev->queues[0];
154
155 WARN_ON(nvmeq->hctx);
156 nvmeq->hctx = hctx;
157 hctx->driver_data = nvmeq;
158 return 0;
e85248e5
MW		 159}
160
a4aea562
MB		 161static int nvme_admin_init_request(void *data, struct request *req,
162 unsigned int hctx_idx, unsigned int rq_idx,
163 unsigned int numa_node)
22404274 164{
a4aea562
MB		 165 struct nvme_dev *dev = data;
166 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
167 struct nvme_queue *nvmeq = dev->queues[0];
168
169 BUG_ON(!nvmeq);
170 cmd->nvmeq = nvmeq;
171 return 0;
22404274
KB		 172}
173
2c30540b
JA		 174static void nvme_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
175{
176 struct nvme_queue *nvmeq = hctx->driver_data;
177
178 nvmeq->hctx = NULL;
179}
180
a4aea562
MB		 181static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
182 unsigned int hctx_idx)
b60503ba 183{
a4aea562
MB		 184 struct nvme_dev *dev = data;
185 struct nvme_queue *nvmeq = dev->queues[
186 (hctx_idx % dev->queue_count) + 1];
b60503ba 187
a4aea562
MB		 188 if (!nvmeq->hctx)
189 nvmeq->hctx = hctx;
190
191 /* nvmeq queues are shared between namespaces. We assume here that
192 * blk-mq map the tags so they match up with the nvme queue tags. */
193 WARN_ON(nvmeq->hctx->tags != hctx->tags);
b60503ba 194
a4aea562
MB		 195 hctx->driver_data = nvmeq;
196 return 0;
b60503ba
MW		 197}
198
a4aea562
MB		 199static int nvme_init_request(void *data, struct request *req,
200 unsigned int hctx_idx, unsigned int rq_idx,
201 unsigned int numa_node)
b60503ba 202{
a4aea562
MB		 203 struct nvme_dev *dev = data;
204 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
205 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
206
207 BUG_ON(!nvmeq);
208 cmd->nvmeq = nvmeq;
209 return 0;
210}
211
212static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx,
213 nvme_completion_fn handler)
214{
215 cmd->fn = handler;
216 cmd->ctx = ctx;
217 cmd->aborted = 0;
c917dfe5 218 blk_mq_start_request(blk_mq_rq_from_pdu(cmd));
b60503ba
MW		 219}
220
c2f5b650
MW		 221/* Special values must be less than 0x1000 */
222#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 223#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
224#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
225#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
be7b6275 226
edd10d33 227static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 228 struct nvme_completion *cqe)
229{
230 if (ctx == CMD_CTX_CANCELLED)
231 return;
c2f5b650 232 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 233 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 234 "completed id %d twice on queue %d\n",
235 cqe->command_id, le16_to_cpup(&cqe->sq_id));
236 return;
237 }
238 if (ctx == CMD_CTX_INVALID) {
edd10d33 239 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 240 "invalid id %d completed on queue %d\n",
241 cqe->command_id, le16_to_cpup(&cqe->sq_id));
242 return;
243 }
edd10d33 244 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 245}
246
a4aea562 247static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn)
b60503ba 248{
c2f5b650 249 void *ctx;
b60503ba 250
859361a2 251 if (fn)
a4aea562
MB		 252 *fn = cmd->fn;
253 ctx = cmd->ctx;
254 cmd->fn = special_completion;
255 cmd->ctx = CMD_CTX_CANCELLED;
c2f5b650 256 return ctx;
b60503ba
MW		 257}
258
a4aea562
MB		 259static void async_req_completion(struct nvme_queue *nvmeq, void *ctx,
260 struct nvme_completion *cqe)
3c0cf138 261{
a4aea562 262 struct request *req = ctx;
3c0cf138 263
a4aea562
MB		 264 u32 result = le32_to_cpup(&cqe->result);
265 u16 status = le16_to_cpup(&cqe->status) >> 1;
266
267 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
268 ++nvmeq->dev->event_limit;
269 if (status == NVME_SC_SUCCESS)
270 dev_warn(nvmeq->q_dmadev,
271 "async event result %08x\n", result);
272
9d135bb8 273 blk_mq_free_hctx_request(nvmeq->hctx, req);
b60503ba
MW		 274}
275
a4aea562
MB		 276static void abort_completion(struct nvme_queue *nvmeq, void *ctx,
277 struct nvme_completion *cqe)
5a92e700 278{
a4aea562
MB		 279 struct request *req = ctx;
280
281 u16 status = le16_to_cpup(&cqe->status) >> 1;
282 u32 result = le32_to_cpup(&cqe->result);
a51afb54 283
9d135bb8 284 blk_mq_free_hctx_request(nvmeq->hctx, req);
a51afb54 285
a4aea562
MB		 286 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result);
287 ++nvmeq->dev->abort_limit;
5a92e700
KB		 288}
289
a4aea562
MB		 290static void async_completion(struct nvme_queue *nvmeq, void *ctx,
291 struct nvme_completion *cqe)
b60503ba 292{
a4aea562
MB		 293 struct async_cmd_info *cmdinfo = ctx;
294 cmdinfo->result = le32_to_cpup(&cqe->result);
295 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
296 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
9d135bb8 297 blk_mq_free_hctx_request(nvmeq->hctx, cmdinfo->req);
b60503ba
MW		 298}
299
a4aea562
MB		 300static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq,
301 unsigned int tag)
b60503ba 302{
a4aea562
MB		 303 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
304 struct request *req = blk_mq_tag_to_rq(hctx->tags, tag);
a51afb54 305
a4aea562 306 return blk_mq_rq_to_pdu(req);
4f5099af
KB		 307}
308
a4aea562
MB		 309/*
310 * Called with local interrupts disabled and the q_lock held. May not sleep.
311 */
312static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag,
313 nvme_completion_fn *fn)
4f5099af 314{
a4aea562
MB		 315 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag);
316 void *ctx;
317 if (tag >= nvmeq->q_depth) {
318 *fn = special_completion;
319 return CMD_CTX_INVALID;
320 }
321 if (fn)
322 *fn = cmd->fn;
323 ctx = cmd->ctx;
324 cmd->fn = special_completion;
325 cmd->ctx = CMD_CTX_COMPLETED;
326 return ctx;
b60503ba
MW		 327}
328
329/**
714a7a22 330 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 331 * @nvmeq: The queue to use
332 * @cmd: The command to send
333 *
334 * Safe to use from interrupt context
335 */
a4aea562 336static int __nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
b60503ba 337{
a4aea562
MB		 338 u16 tail = nvmeq->sq_tail;
339
b60503ba 340 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 341 if (++tail == nvmeq->q_depth)
342 tail = 0;
7547881d 343 writel(tail, nvmeq->q_db);
b60503ba 344 nvmeq->sq_tail = tail;
b60503ba
MW		 345
346 return 0;
347}
348
a4aea562
MB		 349static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
350{
351 unsigned long flags;
352 int ret;
353 spin_lock_irqsave(&nvmeq->q_lock, flags);
354 ret = __nvme_submit_cmd(nvmeq, cmd);
355 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
356 return ret;
357}
358
eca18b23 359static __le64 **iod_list(struct nvme_iod *iod)
e025344c 360{
eca18b23 361 return ((void *)iod) + iod->offset;
e025344c
SMM		 362}
363
eca18b23
MW		 364/*
365 * Will slightly overestimate the number of pages needed. This is OK
366 * as it only leads to a small amount of wasted memory for the lifetime of
367 * the I/O.
368 */
1d090624 369static int nvme_npages(unsigned size, struct nvme_dev *dev)
eca18b23 370{
1d090624
KB		 371 unsigned nprps = DIV_ROUND_UP(size + dev->page_size, dev->page_size);
372 return DIV_ROUND_UP(8 * nprps, dev->page_size - 8);
eca18b23 373}
b60503ba 374
eca18b23 375static struct nvme_iod *
1d090624 376nvme_alloc_iod(unsigned nseg, unsigned nbytes, struct nvme_dev *dev, gfp_t gfp)
b60503ba 377{
eca18b23 378 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
1d090624 379 sizeof(__le64 *) * nvme_npages(nbytes, dev) +
eca18b23
MW		 380 sizeof(struct scatterlist) * nseg, gfp);
381
382 if (iod) {
383 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
384 iod->npages = -1;
385 iod->length = nbytes;
2b196034 386 iod->nents = 0;
edd10d33 387 iod->first_dma = 0ULL;
eca18b23
MW		 388 }
389
390 return iod;
b60503ba
MW		 391}
392
5d0f6131 393void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 394{
1d090624 395 const int last_prp = dev->page_size / 8 - 1;
eca18b23
MW		 396 int i;
397 __le64 **list = iod_list(iod);
398 dma_addr_t prp_dma = iod->first_dma;
399
400 if (iod->npages == 0)
401 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
402 for (i = 0; i < iod->npages; i++) {
403 __le64 *prp_list = list[i];
404 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
405 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
406 prp_dma = next_prp_dma;
407 }
408 kfree(iod);
b60503ba
MW		 409}
410
b4ff9c8d
KB		 411static int nvme_error_status(u16 status)
412{
413 switch (status & 0x7ff) {
414 case NVME_SC_SUCCESS:
415 return 0;
416 case NVME_SC_CAP_EXCEEDED:
417 return -ENOSPC;
418 default:
419 return -EIO;
420 }
421}
422
a4aea562 423static void req_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 424 struct nvme_completion *cqe)
425{
eca18b23 426 struct nvme_iod *iod = ctx;
a4aea562
MB		 427 struct request *req = iod->private;
428 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
429
b60503ba
MW		 430 u16 status = le16_to_cpup(&cqe->status) >> 1;
431
edd10d33 432 if (unlikely(status)) {
a4aea562
MB		 433 if (!(status & NVME_SC_DNR || blk_noretry_request(req))
434 && (jiffies - req->start_time) < req->timeout) {
435 blk_mq_requeue_request(req);
436 blk_mq_kick_requeue_list(req->q);
edd10d33
KB		 437 return;
438 }
a4aea562
MB		 439 req->errors = nvme_error_status(status);
440 } else
441 req->errors = 0;
442
443 if (cmd_rq->aborted)
444 dev_warn(&nvmeq->dev->pci_dev->dev,
445 "completing aborted command with status:%04x\n",
446 status);
447
448 if (iod->nents)
449 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg, iod->nents,
450 rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
edd10d33 451 nvme_free_iod(nvmeq->dev, iod);
3291fa57 452
a4aea562 453 blk_mq_complete_request(req);
b60503ba
MW		 454}
455
184d2944 456/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 457int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
458 gfp_t gfp)
ff22b54f 459{
99802a7a 460 struct dma_pool *pool;
eca18b23
MW		 461 int length = total_len;
462 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 463 int dma_len = sg_dma_len(sg);
464 u64 dma_addr = sg_dma_address(sg);
465 int offset = offset_in_page(dma_addr);
e025344c 466 __le64 *prp_list;
eca18b23 467 __le64 **list = iod_list(iod);
e025344c 468 dma_addr_t prp_dma;
eca18b23 469 int nprps, i;
1d090624 470 u32 page_size = dev->page_size;
ff22b54f 471
1d090624 472 length -= (page_size - offset);
ff22b54f 473 if (length <= 0)
eca18b23 474 return total_len;
ff22b54f 475
1d090624 476 dma_len -= (page_size - offset);
ff22b54f 477 if (dma_len) {
1d090624 478 dma_addr += (page_size - offset);
ff22b54f
MW		 479 } else {
480 sg = sg_next(sg);
481 dma_addr = sg_dma_address(sg);
482 dma_len = sg_dma_len(sg);
483 }
484
1d090624 485 if (length <= page_size) {
edd10d33 486 iod->first_dma = dma_addr;
eca18b23 487 return total_len;
e025344c
SMM		 488 }
489
1d090624 490 nprps = DIV_ROUND_UP(length, page_size);
99802a7a
MW		 491 if (nprps <= (256 / 8)) {
492 pool = dev->prp_small_pool;
eca18b23 493 iod->npages = 0;
99802a7a
MW		 494 } else {
495 pool = dev->prp_page_pool;
eca18b23 496 iod->npages = 1;
99802a7a
MW		 497 }
498
b77954cb
MW		 499 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
500 if (!prp_list) {
edd10d33 501 iod->first_dma = dma_addr;
eca18b23 502 iod->npages = -1;
1d090624 503 return (total_len - length) + page_size;
b77954cb 504 }
eca18b23
MW		 505 list[0] = prp_list;
506 iod->first_dma = prp_dma;
e025344c
SMM		 507 i = 0;
508 for (;;) {
1d090624 509 if (i == page_size >> 3) {
e025344c 510 __le64 *old_prp_list = prp_list;
b77954cb 511 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 512 if (!prp_list)
513 return total_len - length;
514 list[iod->npages++] = prp_list;
7523d834
MW		 515 prp_list[0] = old_prp_list[i - 1];
516 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
517 i = 1;
e025344c
SMM		 518 }
519 prp_list[i++] = cpu_to_le64(dma_addr);
1d090624
KB		 520 dma_len -= page_size;
521 dma_addr += page_size;
522 length -= page_size;
e025344c
SMM		 523 if (length <= 0)
524 break;
525 if (dma_len > 0)
526 continue;
527 BUG_ON(dma_len < 0);
528 sg = sg_next(sg);
529 dma_addr = sg_dma_address(sg);
530 dma_len = sg_dma_len(sg);
ff22b54f
MW		 531 }
532
eca18b23 533 return total_len;
ff22b54f
MW		 534}
535
a4aea562
MB		 536/*
537 * We reuse the small pool to allocate the 16-byte range here as it is not
538 * worth having a special pool for these or additional cases to handle freeing
539 * the iod.
540 */
541static void nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
542 struct request *req, struct nvme_iod *iod)
0e5e4f0e 543{
edd10d33
KB		 544 struct nvme_dsm_range *range =
545 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 546 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
547
0e5e4f0e 548 range->cattr = cpu_to_le32(0);
a4aea562
MB		 549 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift);
550 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
0e5e4f0e
KB		 551
552 memset(cmnd, 0, sizeof(*cmnd));
553 cmnd->dsm.opcode = nvme_cmd_dsm;
a4aea562 554 cmnd->dsm.command_id = req->tag;
0e5e4f0e
KB		 555 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
556 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
557 cmnd->dsm.nr = 0;
558 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
559
560 if (++nvmeq->sq_tail == nvmeq->q_depth)
561 nvmeq->sq_tail = 0;
562 writel(nvmeq->sq_tail, nvmeq->q_db);
0e5e4f0e
KB		 563}
564
a4aea562 565static void nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
00df5cb4
MW		 566 int cmdid)
567{
568 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
569
570 memset(cmnd, 0, sizeof(*cmnd));
571 cmnd->common.opcode = nvme_cmd_flush;
572 cmnd->common.command_id = cmdid;
573 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
574
575 if (++nvmeq->sq_tail == nvmeq->q_depth)
576 nvmeq->sq_tail = 0;
577 writel(nvmeq->sq_tail, nvmeq->q_db);
00df5cb4
MW		 578}
579
a4aea562
MB		 580static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod,
581 struct nvme_ns *ns)
b60503ba 582{
a4aea562 583 struct request *req = iod->private;
ff22b54f 584 struct nvme_command *cmnd;
a4aea562
MB		 585 u16 control = 0;
586 u32 dsmgmt = 0;
00df5cb4 587
a4aea562 588 if (req->cmd_flags & REQ_FUA)
b60503ba 589 control |= NVME_RW_FUA;
a4aea562 590 if (req->cmd_flags & (REQ_FAILFAST_DEV | REQ_RAHEAD))
b60503ba
MW		 591 control |= NVME_RW_LR;
592
a4aea562 593 if (req->cmd_flags & REQ_RAHEAD)
b60503ba
MW		 594 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
595
ff22b54f 596 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 597 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 598
a4aea562
MB		 599 cmnd->rw.opcode = (rq_data_dir(req) ? nvme_cmd_write : nvme_cmd_read);
600 cmnd->rw.command_id = req->tag;
ff22b54f 601 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 602 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
603 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
a4aea562
MB		 604 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req)));
605 cmnd->rw.length = cpu_to_le16((blk_rq_bytes(req) >> ns->lba_shift) - 1);
ff22b54f
MW		 606 cmnd->rw.control = cpu_to_le16(control);
607 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 608
b60503ba
MW		 609 if (++nvmeq->sq_tail == nvmeq->q_depth)
610 nvmeq->sq_tail = 0;
7547881d 611 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 612
1974b1ae 613 return 0;
edd10d33
KB		 614}
615
a4aea562
MB		 616static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
617 const struct blk_mq_queue_data *bd)
edd10d33 618{
a4aea562
MB		 619 struct nvme_ns *ns = hctx->queue->queuedata;
620 struct nvme_queue *nvmeq = hctx->driver_data;
621 struct request *req = bd->rq;
622 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
edd10d33 623 struct nvme_iod *iod;
a4aea562 624 int psegs = req->nr_phys_segments;
a4aea562
MB		 625 enum dma_data_direction dma_dir;
626 unsigned size = !(req->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(req) :
9dbbfab7 627 sizeof(struct nvme_dsm_range);
edd10d33 628
9dbbfab7 629 iod = nvme_alloc_iod(psegs, size, ns->dev, GFP_ATOMIC);
edd10d33 630 if (!iod)
fe54303e 631 return BLK_MQ_RQ_QUEUE_BUSY;
a4aea562
MB		 632
633 iod->private = req;
edd10d33 634
a4aea562 635 if (req->cmd_flags & REQ_DISCARD) {
edd10d33
KB		 636 void *range;
637 /*
638 * We reuse the small pool to allocate the 16-byte range here
639 * as it is not worth having a special pool for these or
640 * additional cases to handle freeing the iod.
641 */
642 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
643 GFP_ATOMIC,
644 &iod->first_dma);
a4aea562 645 if (!range)
fe54303e 646 goto retry_cmd;
edd10d33
KB		 647 iod_list(iod)[0] = (__le64 *)range;
648 iod->npages = 0;
649 } else if (psegs) {
a4aea562
MB		 650 dma_dir = rq_data_dir(req) ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
651
652 sg_init_table(iod->sg, psegs);
653 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
fe54303e
JA		 654 if (!iod->nents)
655 goto error_cmd;
a4aea562
MB		 656
657 if (!dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir))
fe54303e 658 goto retry_cmd;
a4aea562 659
fe54303e
JA		 660 if (blk_rq_bytes(req) !=
661 nvme_setup_prps(nvmeq->dev, iod, blk_rq_bytes(req), GFP_ATOMIC)) {
662 dma_unmap_sg(&nvmeq->dev->pci_dev->dev, iod->sg,
663 iod->nents, dma_dir);
664 goto retry_cmd;
665 }
edd10d33 666 }
1974b1ae 667
9af8785a 668 nvme_set_info(cmd, iod, req_completion);
a4aea562
MB		 669 spin_lock_irq(&nvmeq->q_lock);
670 if (req->cmd_flags & REQ_DISCARD)
671 nvme_submit_discard(nvmeq, ns, req, iod);
672 else if (req->cmd_flags & REQ_FLUSH)
673 nvme_submit_flush(nvmeq, ns, req->tag);
674 else
675 nvme_submit_iod(nvmeq, iod, ns);
676
677 nvme_process_cq(nvmeq);
678 spin_unlock_irq(&nvmeq->q_lock);
679 return BLK_MQ_RQ_QUEUE_OK;
680
fe54303e
JA		 681 error_cmd:
682 nvme_free_iod(nvmeq->dev, iod);
683 return BLK_MQ_RQ_QUEUE_ERROR;
684 retry_cmd:
eca18b23 685 nvme_free_iod(nvmeq->dev, iod);
fe54303e 686 return BLK_MQ_RQ_QUEUE_BUSY;
b60503ba
MW		 687}
688
e9539f47 689static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 690{
82123460 691 u16 head, phase;
b60503ba 692
b60503ba 693 head = nvmeq->cq_head;
82123460 694 phase = nvmeq->cq_phase;
b60503ba
MW		 695
696 for (;;) {
c2f5b650
MW		 697 void *ctx;
698 nvme_completion_fn fn;
b60503ba 699 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 700 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 701 break;
702 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
703 if (++head == nvmeq->q_depth) {
704 head = 0;
82123460 705 phase = !phase;
b60503ba 706 }
a4aea562 707 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn);
edd10d33 708 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 709 }
710
711 /* If the controller ignores the cq head doorbell and continuously
712 * writes to the queue, it is theoretically possible to wrap around
713 * the queue twice and mistakenly return IRQ_NONE. Linux only
714 * requires that 0.1% of your interrupts are handled, so this isn't
715 * a big problem.
716 */
82123460 717 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 718 return 0;
b60503ba 719
b80d5ccc 720 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 721 nvmeq->cq_head = head;
82123460 722 nvmeq->cq_phase = phase;
b60503ba 723
e9539f47
MW		 724 nvmeq->cqe_seen = 1;
725 return 1;
b60503ba
MW		 726}
727
a4aea562
MB		 728/* Admin queue isn't initialized as a request queue. If at some point this
729 * happens anyway, make sure to notify the user */
730static int nvme_admin_queue_rq(struct blk_mq_hw_ctx *hctx,
731 const struct blk_mq_queue_data *bd)
7d822457 732{
a4aea562
MB		 733 WARN_ON_ONCE(1);
734 return BLK_MQ_RQ_QUEUE_ERROR;
7d822457
MW		 735}
736
b60503ba 737static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 738{
739 irqreturn_t result;
740 struct nvme_queue *nvmeq = data;
741 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 742 nvme_process_cq(nvmeq);
743 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
744 nvmeq->cqe_seen = 0;
58ffacb5
MW		 745 spin_unlock(&nvmeq->q_lock);
746 return result;
747}
748
749static irqreturn_t nvme_irq_check(int irq, void *data)
750{
751 struct nvme_queue *nvmeq = data;
752 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
753 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
754 return IRQ_NONE;
755 return IRQ_WAKE_THREAD;
756}
757
a4aea562
MB		 758static void nvme_abort_cmd_info(struct nvme_queue *nvmeq, struct nvme_cmd_info *
759 cmd_info)
3c0cf138
MW		 760{
761 spin_lock_irq(&nvmeq->q_lock);
a4aea562 762 cancel_cmd_info(cmd_info, NULL);
3c0cf138
MW		 763 spin_unlock_irq(&nvmeq->q_lock);
764}
765
c2f5b650
MW		 766struct sync_cmd_info {
767 struct task_struct *task;
768 u32 result;
769 int status;
770};
771
edd10d33 772static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 773 struct nvme_completion *cqe)
774{
775 struct sync_cmd_info *cmdinfo = ctx;
776 cmdinfo->result = le32_to_cpup(&cqe->result);
777 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
778 wake_up_process(cmdinfo->task);
779}
780
b60503ba
MW		 781/*
782 * Returns 0 on success. If the result is negative, it's a Linux error code;
783 * if the result is positive, it's an NVM Express status code
784 */
a4aea562 785static int nvme_submit_sync_cmd(struct request *req, struct nvme_command *cmd,
5d0f6131 786 u32 *result, unsigned timeout)
b60503ba 787{
a4aea562 788 int ret;
b60503ba 789 struct sync_cmd_info cmdinfo;
a4aea562
MB		 790 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
791 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
b60503ba
MW		 792
793 cmdinfo.task = current;
794 cmdinfo.status = -EINTR;
795
a4aea562
MB		 796 cmd->common.command_id = req->tag;
797
798 nvme_set_info(cmd_rq, &cmdinfo, sync_completion);
b60503ba 799
3c0cf138 800 set_current_state(TASK_KILLABLE);
4f5099af
KB		 801 ret = nvme_submit_cmd(nvmeq, cmd);
802 if (ret) {
a4aea562 803 nvme_finish_cmd(nvmeq, req->tag, NULL);
4f5099af 804 set_current_state(TASK_RUNNING);
4f5099af 805 }
849c6e77 806 ret = schedule_timeout(timeout);
b60503ba 807
849c6e77
JA		 808 /*
809 * Ensure that sync_completion has either run, or that it will
810 * never run.
811 */
812 nvme_abort_cmd_info(nvmeq, blk_mq_rq_to_pdu(req));
813
814 /*
815 * We never got the completion
816 */
817 if (cmdinfo.status == -EINTR)
3c0cf138 818 return -EINTR;
3c0cf138 819
b60503ba
MW		 820 if (result)
821 *result = cmdinfo.result;
822
823 return cmdinfo.status;
824}
825
a4aea562
MB		 826static int nvme_submit_async_admin_req(struct nvme_dev *dev)
827{
828 struct nvme_queue *nvmeq = dev->queues[0];
829 struct nvme_command c;
830 struct nvme_cmd_info *cmd_info;
831 struct request *req;
832
6dcc0cf6 833 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC, false);
9f173b33
DC		 834 if (IS_ERR(req))
835 return PTR_ERR(req);
a4aea562 836
c917dfe5 837 req->cmd_flags |= REQ_NO_TIMEOUT;
a4aea562
MB		 838 cmd_info = blk_mq_rq_to_pdu(req);
839 nvme_set_info(cmd_info, req, async_req_completion);
840
841 memset(&c, 0, sizeof(c));
842 c.common.opcode = nvme_admin_async_event;
843 c.common.command_id = req->tag;
844
845 return __nvme_submit_cmd(nvmeq, &c);
846}
847
848static int nvme_submit_admin_async_cmd(struct nvme_dev *dev,
4d115420
KB		 849 struct nvme_command *cmd,
850 struct async_cmd_info *cmdinfo, unsigned timeout)
851{
a4aea562
MB		 852 struct nvme_queue *nvmeq = dev->queues[0];
853 struct request *req;
854 struct nvme_cmd_info *cmd_rq;
4d115420 855
a4aea562 856 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
9f173b33
DC		 857 if (IS_ERR(req))
858 return PTR_ERR(req);
a4aea562
MB		 859
860 req->timeout = timeout;
861 cmd_rq = blk_mq_rq_to_pdu(req);
862 cmdinfo->req = req;
863 nvme_set_info(cmd_rq, cmdinfo, async_completion);
4d115420 864 cmdinfo->status = -EINTR;
a4aea562
MB		 865
866 cmd->common.command_id = req->tag;
867
4f5099af 868 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 869}
870
a64e6bb4 871static int __nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
a4aea562 872 u32 *result, unsigned timeout)
b60503ba 873{
a4aea562
MB		 874 int res;
875 struct request *req;
876
877 req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_KERNEL, false);
97fe3832
JA		 878 if (IS_ERR(req))
879 return PTR_ERR(req);
a4aea562 880 res = nvme_submit_sync_cmd(req, cmd, result, timeout);
9d135bb8 881 blk_mq_free_request(req);
a4aea562 882 return res;
4f5099af
KB		 883}
884
a4aea562 885int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
4f5099af
KB		 886 u32 *result)
887{
a4aea562 888 return __nvme_submit_admin_cmd(dev, cmd, result, ADMIN_TIMEOUT);
b60503ba
MW		 889}
890
a4aea562
MB		 891int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
892 struct nvme_command *cmd, u32 *result)
4d115420 893{
a4aea562
MB		 894 int res;
895 struct request *req;
896
897 req = blk_mq_alloc_request(ns->queue, WRITE, (GFP_KERNEL|__GFP_WAIT),
898 false);
97fe3832
JA		 899 if (IS_ERR(req))
900 return PTR_ERR(req);
a4aea562 901 res = nvme_submit_sync_cmd(req, cmd, result, NVME_IO_TIMEOUT);
9d135bb8 902 blk_mq_free_request(req);
a4aea562 903 return res;
4d115420
KB		 904}
905
b60503ba
MW		 906static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
907{
b60503ba
MW		 908 struct nvme_command c;
909
910 memset(&c, 0, sizeof(c));
911 c.delete_queue.opcode = opcode;
912 c.delete_queue.qid = cpu_to_le16(id);
913
a4aea562 914 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 915}
916
917static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
918 struct nvme_queue *nvmeq)
919{
b60503ba
MW		 920 struct nvme_command c;
921 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
922
923 memset(&c, 0, sizeof(c));
924 c.create_cq.opcode = nvme_admin_create_cq;
925 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
926 c.create_cq.cqid = cpu_to_le16(qid);
927 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
928 c.create_cq.cq_flags = cpu_to_le16(flags);
929 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
930
a4aea562 931 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 932}
933
934static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
935 struct nvme_queue *nvmeq)
936{
b60503ba
MW		 937 struct nvme_command c;
938 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
939
940 memset(&c, 0, sizeof(c));
941 c.create_sq.opcode = nvme_admin_create_sq;
942 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
943 c.create_sq.sqid = cpu_to_le16(qid);
944 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
945 c.create_sq.sq_flags = cpu_to_le16(flags);
946 c.create_sq.cqid = cpu_to_le16(qid);
947
a4aea562 948 return nvme_submit_admin_cmd(dev, &c, NULL);
b60503ba
MW		 949}
950
951static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
952{
953 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
954}
955
956static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
957{
958 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
959}
960
5d0f6131 961int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 962 dma_addr_t dma_addr)
963{
964 struct nvme_command c;
965
966 memset(&c, 0, sizeof(c));
967 c.identify.opcode = nvme_admin_identify;
968 c.identify.nsid = cpu_to_le32(nsid);
969 c.identify.prp1 = cpu_to_le64(dma_addr);
970 c.identify.cns = cpu_to_le32(cns);
971
972 return nvme_submit_admin_cmd(dev, &c, NULL);
973}
974
5d0f6131 975int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 976 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 977{
978 struct nvme_command c;
979
980 memset(&c, 0, sizeof(c));
981 c.features.opcode = nvme_admin_get_features;
a42cecce 982 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 983 c.features.prp1 = cpu_to_le64(dma_addr);
984 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 985
08df1e05 986 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 987}
988
5d0f6131
VV		 989int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
990 dma_addr_t dma_addr, u32 *result)
df348139
MW		 991{
992 struct nvme_command c;
993
994 memset(&c, 0, sizeof(c));
995 c.features.opcode = nvme_admin_set_features;
996 c.features.prp1 = cpu_to_le64(dma_addr);
997 c.features.fid = cpu_to_le32(fid);
998 c.features.dword11 = cpu_to_le32(dword11);
999
bc5fc7e4
MW		 1000 return nvme_submit_admin_cmd(dev, &c, result);
1001}
1002
c30341dc 1003/**
a4aea562 1004 * nvme_abort_req - Attempt aborting a request
c30341dc
KB		 1005 *
1006 * Schedule controller reset if the command was already aborted once before and
1007 * still hasn't been returned to the driver, or if this is the admin queue.
1008 */
a4aea562 1009static void nvme_abort_req(struct request *req)
c30341dc 1010{
a4aea562
MB		 1011 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req);
1012 struct nvme_queue *nvmeq = cmd_rq->nvmeq;
c30341dc 1013 struct nvme_dev *dev = nvmeq->dev;
a4aea562
MB		 1014 struct request *abort_req;
1015 struct nvme_cmd_info *abort_cmd;
1016 struct nvme_command cmd;
c30341dc 1017
a4aea562 1018 if (!nvmeq->qid || cmd_rq->aborted) {
c30341dc
KB		 1019 if (work_busy(&dev->reset_work))
1020 return;
1021 list_del_init(&dev->node);
1022 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1023 "I/O %d QID %d timeout, reset controller\n",
1024 req->tag, nvmeq->qid);
9ca97374 1025 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1026 queue_work(nvme_workq, &dev->reset_work);
1027 return;
1028 }
1029
1030 if (!dev->abort_limit)
1031 return;
1032
a4aea562
MB		 1033 abort_req = blk_mq_alloc_request(dev->admin_q, WRITE, GFP_ATOMIC,
1034 false);
9f173b33 1035 if (IS_ERR(abort_req))
c30341dc
KB		 1036 return;
1037
a4aea562
MB		 1038 abort_cmd = blk_mq_rq_to_pdu(abort_req);
1039 nvme_set_info(abort_cmd, abort_req, abort_completion);
1040
c30341dc
KB		 1041 memset(&cmd, 0, sizeof(cmd));
1042 cmd.abort.opcode = nvme_admin_abort_cmd;
a4aea562 1043 cmd.abort.cid = req->tag;
c30341dc 1044 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
a4aea562 1045 cmd.abort.command_id = abort_req->tag;
c30341dc
KB		 1046
1047 --dev->abort_limit;
a4aea562 1048 cmd_rq->aborted = 1;
c30341dc 1049
a4aea562 1050 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag,
c30341dc 1051 nvmeq->qid);
a4aea562
MB		 1052 if (nvme_submit_cmd(dev->queues[0], &cmd) < 0) {
1053 dev_warn(nvmeq->q_dmadev,
1054 "Could not abort I/O %d QID %d",
1055 req->tag, nvmeq->qid);
c87fd540 1056 blk_mq_free_request(abort_req);
a4aea562 1057 }
c30341dc
KB		 1058}
1059
a4aea562
MB		 1060static void nvme_cancel_queue_ios(struct blk_mq_hw_ctx *hctx,
1061 struct request *req, void *data, bool reserved)
a09115b2 1062{
a4aea562
MB		 1063 struct nvme_queue *nvmeq = data;
1064 void *ctx;
1065 nvme_completion_fn fn;
1066 struct nvme_cmd_info *cmd;
1067 static struct nvme_completion cqe = {
1068 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
1069 };
a09115b2 1070
a4aea562 1071 cmd = blk_mq_rq_to_pdu(req);
a09115b2 1072
a4aea562
MB		 1073 if (cmd->ctx == CMD_CTX_CANCELLED)
1074 return;
1075
1076 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n",
1077 req->tag, nvmeq->qid);
1078 ctx = cancel_cmd_info(cmd, &fn);
1079 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1080}
1081
a4aea562 1082static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
9e866774 1083{
a4aea562
MB		 1084 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req);
1085 struct nvme_queue *nvmeq = cmd->nvmeq;
1086
1087 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag,
1088 nvmeq->qid);
c917dfe5
KB		 1089
1090 if (!nvmeq->dev->initialized) {
1091 /*
1092 * Force cancelled command frees the request, which requires we
1093 * return BLK_EH_NOT_HANDLED.
1094 */
1095 nvme_cancel_queue_ios(nvmeq->hctx, req, nvmeq, reserved);
1096 return BLK_EH_NOT_HANDLED;
1097 }
1098 nvme_abort_req(req);
a4aea562
MB		 1099
1100 /*
1101 * The aborted req will be completed on receiving the abort req.
1102 * We enable the timer again. If hit twice, it'll cause a device reset,
1103 * as the device then is in a faulty state.
1104 */
1105 return BLK_EH_RESET_TIMER;
1106}
22404274 1107
a4aea562
MB		 1108static void nvme_free_queue(struct nvme_queue *nvmeq)
1109{
9e866774
MW		 1110 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1111 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1112 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1113 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1114 kfree(nvmeq);
1115}
1116
a1a5ef99 1117static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274 1118{
f435c282
KB		 1119 LLIST_HEAD(q_list);
1120 struct nvme_queue *nvmeq, *next;
1121 struct llist_node *entry;
22404274
KB		 1122 int i;
1123
a1a5ef99 1124 for (i = dev->queue_count - 1; i >= lowest; i--) {
a4aea562 1125 struct nvme_queue *nvmeq = dev->queues[i];
f435c282 1126 llist_add(&nvmeq->node, &q_list);
22404274 1127 dev->queue_count--;
a4aea562 1128 dev->queues[i] = NULL;
22404274 1129 }
f435c282
KB		 1130 synchronize_rcu();
1131 entry = llist_del_all(&q_list);
1132 llist_for_each_entry_safe(nvmeq, next, entry, node)
1133 nvme_free_queue(nvmeq);
22404274
KB		 1134}
1135
4d115420
KB		 1136/**
1137 * nvme_suspend_queue - put queue into suspended state
1138 * @nvmeq - queue to suspend
4d115420
KB		 1139 */
1140static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1141{
2b25d981 1142 int vector;
b60503ba 1143
a09115b2 1144 spin_lock_irq(&nvmeq->q_lock);
2b25d981
KB		 1145 if (nvmeq->cq_vector == -1) {
1146 spin_unlock_irq(&nvmeq->q_lock);
1147 return 1;
1148 }
1149 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
42f61420 1150 nvmeq->dev->online_queues--;
2b25d981 1151 nvmeq->cq_vector = -1;
a09115b2
MW		 1152 spin_unlock_irq(&nvmeq->q_lock);
1153
aba2080f
MW		 1154 irq_set_affinity_hint(vector, NULL);
1155 free_irq(vector, nvmeq);
b60503ba 1156
4d115420
KB		 1157 return 0;
1158}
b60503ba 1159
4d115420
KB		 1160static void nvme_clear_queue(struct nvme_queue *nvmeq)
1161{
a4aea562
MB		 1162 struct blk_mq_hw_ctx *hctx = nvmeq->hctx;
1163
22404274
KB		 1164 spin_lock_irq(&nvmeq->q_lock);
1165 nvme_process_cq(nvmeq);
a4aea562
MB		 1166 if (hctx && hctx->tags)
1167 blk_mq_tag_busy_iter(hctx, nvme_cancel_queue_ios, nvmeq);
22404274 1168 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1169}
1170
4d115420
KB		 1171static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1172{
a4aea562 1173 struct nvme_queue *nvmeq = dev->queues[qid];
4d115420
KB		 1174
1175 if (!nvmeq)
1176 return;
1177 if (nvme_suspend_queue(nvmeq))
1178 return;
1179
0e53d180
KB		 1180 /* Don't tell the adapter to delete the admin queue.
1181 * Don't tell a removed adapter to delete IO queues. */
1182 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1183 adapter_delete_sq(dev, qid);
1184 adapter_delete_cq(dev, qid);
1185 }
4d115420 1186 nvme_clear_queue(nvmeq);
b60503ba
MW		 1187}
1188
1189static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
2b25d981 1190 int depth)
b60503ba
MW		 1191{
1192 struct device *dmadev = &dev->pci_dev->dev;
a4aea562 1193 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
b60503ba
MW		 1194 if (!nvmeq)
1195 return NULL;
1196
4d51abf9
JP		 1197 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1198 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW		 1199 if (!nvmeq->cqes)
1200 goto free_nvmeq;
b60503ba
MW		 1201
1202 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1203 &nvmeq->sq_dma_addr, GFP_KERNEL);
1204 if (!nvmeq->sq_cmds)
1205 goto free_cqdma;
1206
1207 nvmeq->q_dmadev = dmadev;
091b6092 1208 nvmeq->dev = dev;
3193f07b
MW		 1209 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1210 dev->instance, qid);
b60503ba
MW		 1211 spin_lock_init(&nvmeq->q_lock);
1212 nvmeq->cq_head = 0;
82123460 1213 nvmeq->cq_phase = 1;
b80d5ccc 1214 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba 1215 nvmeq->q_depth = depth;
c30341dc 1216 nvmeq->qid = qid;
22404274 1217 dev->queue_count++;
a4aea562 1218 dev->queues[qid] = nvmeq;
b60503ba
MW		 1219
1220 return nvmeq;
1221
1222 free_cqdma:
68b8eca5 1223 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1224 nvmeq->cq_dma_addr);
1225 free_nvmeq:
1226 kfree(nvmeq);
1227 return NULL;
1228}
1229
3001082c
MW		 1230static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1231 const char *name)
1232{
58ffacb5
MW		 1233 if (use_threaded_interrupts)
1234 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1235 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1236 name, nvmeq);
3001082c 1237 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1238 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1239}
1240
22404274 1241static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1242{
22404274 1243 struct nvme_dev *dev = nvmeq->dev;
b60503ba 1244
7be50e93 1245 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1246 nvmeq->sq_tail = 0;
1247 nvmeq->cq_head = 0;
1248 nvmeq->cq_phase = 1;
b80d5ccc 1249 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274 1250 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
42f61420 1251 dev->online_queues++;
7be50e93 1252 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1253}
1254
1255static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1256{
1257 struct nvme_dev *dev = nvmeq->dev;
1258 int result;
3f85d50b 1259
2b25d981 1260 nvmeq->cq_vector = qid - 1;
b60503ba
MW		 1261 result = adapter_alloc_cq(dev, qid, nvmeq);
1262 if (result < 0)
22404274 1263 return result;
b60503ba
MW		 1264
1265 result = adapter_alloc_sq(dev, qid, nvmeq);
1266 if (result < 0)
1267 goto release_cq;
1268
3193f07b 1269 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1270 if (result < 0)
1271 goto release_sq;
1272
22404274 1273 nvme_init_queue(nvmeq, qid);
22404274 1274 return result;
b60503ba
MW		 1275
1276 release_sq:
1277 adapter_delete_sq(dev, qid);
1278 release_cq:
1279 adapter_delete_cq(dev, qid);
22404274 1280 return result;
b60503ba
MW		 1281}
1282
ba47e386
MW		 1283static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1284{
1285 unsigned long timeout;
1286 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1287
1288 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1289
1290 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1291 msleep(100);
1292 if (fatal_signal_pending(current))
1293 return -EINTR;
1294 if (time_after(jiffies, timeout)) {
1295 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1296 "Device not ready; aborting %s\n", enabled ?
1297 "initialisation" : "reset");
ba47e386
MW		 1298 return -ENODEV;
1299 }
1300 }
1301
1302 return 0;
1303}
1304
1305/*
1306 * If the device has been passed off to us in an enabled state, just clear
1307 * the enabled bit. The spec says we should set the 'shutdown notification
1308 * bits', but doing so may cause the device to complete commands to the
1309 * admin queue ... and we don't know what memory that might be pointing at!
1310 */
1311static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1312{
01079522
DM		 1313 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1314 dev->ctrl_config &= ~NVME_CC_ENABLE;
1315 writel(dev->ctrl_config, &dev->bar->cc);
44af146a 1316
ba47e386
MW		 1317 return nvme_wait_ready(dev, cap, false);
1318}
1319
1320static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1321{
01079522
DM		 1322 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1323 dev->ctrl_config |= NVME_CC_ENABLE;
1324 writel(dev->ctrl_config, &dev->bar->cc);
1325
ba47e386
MW		 1326 return nvme_wait_ready(dev, cap, true);
1327}
1328
1894d8f1
KB		 1329static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1330{
1331 unsigned long timeout;
1894d8f1 1332
01079522
DM		 1333 dev->ctrl_config &= ~NVME_CC_SHN_MASK;
1334 dev->ctrl_config |= NVME_CC_SHN_NORMAL;
1335
1336 writel(dev->ctrl_config, &dev->bar->cc);
1894d8f1 1337
2484f407 1338 timeout = SHUTDOWN_TIMEOUT + jiffies;
1894d8f1
KB		 1339 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1340 NVME_CSTS_SHST_CMPLT) {
1341 msleep(100);
1342 if (fatal_signal_pending(current))
1343 return -EINTR;
1344 if (time_after(jiffies, timeout)) {
1345 dev_err(&dev->pci_dev->dev,
1346 "Device shutdown incomplete; abort shutdown\n");
1347 return -ENODEV;
1348 }
1349 }
1350
1351 return 0;
1352}
1353
a4aea562
MB		 1354static struct blk_mq_ops nvme_mq_admin_ops = {
1355 .queue_rq = nvme_admin_queue_rq,
1356 .map_queue = blk_mq_map_queue,
1357 .init_hctx = nvme_admin_init_hctx,
2c30540b 1358 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1359 .init_request = nvme_admin_init_request,
1360 .timeout = nvme_timeout,
1361};
1362
1363static struct blk_mq_ops nvme_mq_ops = {
1364 .queue_rq = nvme_queue_rq,
1365 .map_queue = blk_mq_map_queue,
1366 .init_hctx = nvme_init_hctx,
2c30540b 1367 .exit_hctx = nvme_exit_hctx,
a4aea562
MB		 1368 .init_request = nvme_init_request,
1369 .timeout = nvme_timeout,
1370};
1371
1372static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1373{
1374 if (!dev->admin_q) {
1375 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1376 dev->admin_tagset.nr_hw_queues = 1;
1377 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1;
1378 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1379 dev->admin_tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
1380 dev->admin_tagset.cmd_size = sizeof(struct nvme_cmd_info);
1381 dev->admin_tagset.driver_data = dev;
1382
1383 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1384 return -ENOMEM;
1385
1386 dev->admin_q = blk_mq_init_queue(&dev->admin_tagset);
35b489d3 1387 if (IS_ERR(dev->admin_q)) {
a4aea562
MB		 1388 blk_mq_free_tag_set(&dev->admin_tagset);
1389 return -ENOMEM;
1390 }
1391 }
1392
1393 return 0;
1394}
1395
1396static void nvme_free_admin_tags(struct nvme_dev *dev)
1397{
1398 if (dev->admin_q)
1399 blk_mq_free_tag_set(&dev->admin_tagset);
1400}
1401
8d85fce7 1402static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1403{
ba47e386 1404 int result;
b60503ba 1405 u32 aqa;
ba47e386 1406 u64 cap = readq(&dev->bar->cap);
b60503ba 1407 struct nvme_queue *nvmeq;
1d090624
KB		 1408 unsigned page_shift = PAGE_SHIFT;
1409 unsigned dev_page_min = NVME_CAP_MPSMIN(cap) + 12;
1410 unsigned dev_page_max = NVME_CAP_MPSMAX(cap) + 12;
1411
1412 if (page_shift < dev_page_min) {
1413 dev_err(&dev->pci_dev->dev,
1414 "Minimum device page size (%u) too large for "
1415 "host (%u)\n", 1 << dev_page_min,
1416 1 << page_shift);
1417 return -ENODEV;
1418 }
1419 if (page_shift > dev_page_max) {
1420 dev_info(&dev->pci_dev->dev,
1421 "Device maximum page size (%u) smaller than "
1422 "host (%u); enabling work-around\n",
1423 1 << dev_page_max, 1 << page_shift);
1424 page_shift = dev_page_max;
1425 }
b60503ba 1426
ba47e386
MW		 1427 result = nvme_disable_ctrl(dev, cap);
1428 if (result < 0)
1429 return result;
b60503ba 1430
a4aea562 1431 nvmeq = dev->queues[0];
cd638946 1432 if (!nvmeq) {
2b25d981 1433 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
cd638946
KB		 1434 if (!nvmeq)
1435 return -ENOMEM;
cd638946 1436 }
b60503ba
MW		 1437
1438 aqa = nvmeq->q_depth - 1;
1439 aqa |= aqa << 16;
1440
1d090624
KB		 1441 dev->page_size = 1 << page_shift;
1442
01079522 1443 dev->ctrl_config = NVME_CC_CSS_NVM;
1d090624 1444 dev->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
b60503ba 1445 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1446 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1447
1448 writel(aqa, &dev->bar->aqa);
1449 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1450 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
b60503ba 1451
ba47e386 1452 result = nvme_enable_ctrl(dev, cap);
025c557a 1453 if (result)
a4aea562
MB		 1454 goto free_nvmeq;
1455
1456 result = nvme_alloc_admin_tags(dev);
1457 if (result)
1458 goto free_nvmeq;
9e866774 1459
2b25d981 1460 nvmeq->cq_vector = 0;
3193f07b 1461 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1462 if (result)
a4aea562 1463 goto free_tags;
025c557a 1464
b60503ba 1465 return result;
a4aea562
MB		 1466
1467 free_tags:
1468 nvme_free_admin_tags(dev);
1469 free_nvmeq:
1470 nvme_free_queues(dev, 0);
1471 return result;
b60503ba
MW		 1472}
1473
5d0f6131 1474struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1475 unsigned long addr, unsigned length)
b60503ba 1476{
36c14ed9 1477 int i, err, count, nents, offset;
7fc3cdab
MW		 1478 struct scatterlist *sg;
1479 struct page **pages;
eca18b23 1480 struct nvme_iod *iod;
36c14ed9
MW		 1481
1482 if (addr & 3)
eca18b23 1483 return ERR_PTR(-EINVAL);
5460fc03 1484 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1485 return ERR_PTR(-EINVAL);
7fc3cdab 1486
36c14ed9 1487 offset = offset_in_page(addr);
7fc3cdab
MW		 1488 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1489 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1490 if (!pages)
1491 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1492
1493 err = get_user_pages_fast(addr, count, 1, pages);
1494 if (err < count) {
1495 count = err;
1496 err = -EFAULT;
1497 goto put_pages;
1498 }
7fc3cdab 1499
6808c5fb 1500 err = -ENOMEM;
1d090624 1501 iod = nvme_alloc_iod(count, length, dev, GFP_KERNEL);
6808c5fb
S		 1502 if (!iod)
1503 goto put_pages;
1504
eca18b23 1505 sg = iod->sg;
36c14ed9 1506 sg_init_table(sg, count);
d0ba1e49
MW		 1507 for (i = 0; i < count; i++) {
1508 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1509 min_t(unsigned, length, PAGE_SIZE - offset),
1510 offset);
d0ba1e49
MW		 1511 length -= (PAGE_SIZE - offset);
1512 offset = 0;
7fc3cdab 1513 }
fe304c43 1514 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1515 iod->nents = count;
7fc3cdab 1516
7fc3cdab
MW		 1517 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1518 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1519 if (!nents)
eca18b23 1520 goto free_iod;
b60503ba 1521
7fc3cdab 1522 kfree(pages);
eca18b23 1523 return iod;
b60503ba 1524
eca18b23
MW		 1525 free_iod:
1526 kfree(iod);
7fc3cdab
MW		 1527 put_pages:
1528 for (i = 0; i < count; i++)
1529 put_page(pages[i]);
1530 kfree(pages);
eca18b23 1531 return ERR_PTR(err);
7fc3cdab 1532}
b60503ba 1533
5d0f6131 1534void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1535 struct nvme_iod *iod)
7fc3cdab 1536{
1c2ad9fa 1537 int i;
b60503ba 1538
1c2ad9fa
MW		 1539 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1540 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1541
1c2ad9fa
MW		 1542 for (i = 0; i < iod->nents; i++)
1543 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1544}
b60503ba 1545
a53295b6
MW		 1546static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1547{
1548 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1549 struct nvme_user_io io;
1550 struct nvme_command c;
f410c680
KB		 1551 unsigned length, meta_len;
1552 int status, i;
1553 struct nvme_iod *iod, *meta_iod = NULL;
1554 dma_addr_t meta_dma_addr;
1555 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1556
1557 if (copy_from_user(&io, uio, sizeof(io)))
1558 return -EFAULT;
6c7d4945 1559 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1560 meta_len = (io.nblocks + 1) * ns->ms;
1561
1562 if (meta_len && ((io.metadata & 3) || !io.metadata))
1563 return -EINVAL;
6c7d4945
MW		 1564
1565 switch (io.opcode) {
1566 case nvme_cmd_write:
1567 case nvme_cmd_read:
6bbf1acd 1568 case nvme_cmd_compare:
eca18b23 1569 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1570 break;
6c7d4945 1571 default:
6bbf1acd 1572 return -EINVAL;
6c7d4945
MW		 1573 }
1574
eca18b23
MW		 1575 if (IS_ERR(iod))
1576 return PTR_ERR(iod);
a53295b6
MW		 1577
1578 memset(&c, 0, sizeof(c));
1579 c.rw.opcode = io.opcode;
1580 c.rw.flags = io.flags;
6c7d4945 1581 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1582 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1583 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1584 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1585 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1586 c.rw.reftag = cpu_to_le32(io.reftag);
1587 c.rw.apptag = cpu_to_le16(io.apptag);
1588 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1589
1590 if (meta_len) {
1b56749e
KB		 1591 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1592 meta_len);
f410c680
KB		 1593 if (IS_ERR(meta_iod)) {
1594 status = PTR_ERR(meta_iod);
1595 meta_iod = NULL;
1596 goto unmap;
1597 }
1598
1599 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1600 &meta_dma_addr, GFP_KERNEL);
1601 if (!meta_mem) {
1602 status = -ENOMEM;
1603 goto unmap;
1604 }
1605
1606 if (io.opcode & 1) {
1607 int meta_offset = 0;
1608
1609 for (i = 0; i < meta_iod->nents; i++) {
1610 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1611 meta_iod->sg[i].offset;
1612 memcpy(meta_mem + meta_offset, meta,
1613 meta_iod->sg[i].length);
1614 kunmap_atomic(meta);
1615 meta_offset += meta_iod->sg[i].length;
1616 }
1617 }
1618
1619 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1620 }
1621
edd10d33
KB		 1622 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1623 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1624 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1625
b77954cb
MW		 1626 if (length != (io.nblocks + 1) << ns->lba_shift)
1627 status = -ENOMEM;
1628 else
a4aea562 1629 status = nvme_submit_io_cmd(dev, ns, &c, NULL);
a53295b6 1630
f410c680
KB		 1631 if (meta_len) {
1632 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1633 int meta_offset = 0;
1634
1635 for (i = 0; i < meta_iod->nents; i++) {
1636 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1637 meta_iod->sg[i].offset;
1638 memcpy(meta, meta_mem + meta_offset,
1639 meta_iod->sg[i].length);
1640 kunmap_atomic(meta);
1641 meta_offset += meta_iod->sg[i].length;
1642 }
1643 }
1644
1645 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1646 meta_dma_addr);
1647 }
1648
1649 unmap:
1c2ad9fa 1650 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1651 nvme_free_iod(dev, iod);
f410c680
KB		 1652
1653 if (meta_iod) {
1654 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1655 nvme_free_iod(dev, meta_iod);
1656 }
1657
a53295b6
MW		 1658 return status;
1659}
1660
a4aea562
MB		 1661static int nvme_user_cmd(struct nvme_dev *dev, struct nvme_ns *ns,
1662 struct nvme_passthru_cmd __user *ucmd)
6ee44cdc 1663{
7963e521 1664 struct nvme_passthru_cmd cmd;
6ee44cdc 1665 struct nvme_command c;
eca18b23 1666 int status, length;
c7d36ab8 1667 struct nvme_iod *uninitialized_var(iod);
94f370ca 1668 unsigned timeout;
6ee44cdc 1669
6bbf1acd
MW		 1670 if (!capable(CAP_SYS_ADMIN))
1671 return -EACCES;
1672 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1673 return -EFAULT;
6ee44cdc
MW		 1674
1675 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1676 c.common.opcode = cmd.opcode;
1677 c.common.flags = cmd.flags;
1678 c.common.nsid = cpu_to_le32(cmd.nsid);
1679 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1680 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1681 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1682 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1683 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1684 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1685 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1686 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1687
1688 length = cmd.data_len;
1689 if (cmd.data_len) {
49742188
MW		 1690 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1691 length);
eca18b23
MW		 1692 if (IS_ERR(iod))
1693 return PTR_ERR(iod);
edd10d33
KB		 1694 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1695 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1696 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1697 }
1698
94f370ca
KB		 1699 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1700 ADMIN_TIMEOUT;
a4aea562 1701
6bbf1acd 1702 if (length != cmd.data_len)
b77954cb 1703 status = -ENOMEM;
a4aea562
MB		 1704 else if (ns) {
1705 struct request *req;
1706
1707 req = blk_mq_alloc_request(ns->queue, WRITE,
1708 (GFP_KERNEL|__GFP_WAIT), false);
97fe3832
JA		 1709 if (IS_ERR(req))
1710 status = PTR_ERR(req);
a4aea562
MB		 1711 else {
1712 status = nvme_submit_sync_cmd(req, &c, &cmd.result,
1713 timeout);
9d135bb8 1714 blk_mq_free_request(req);
a4aea562
MB		 1715 }
1716 } else
1717 status = __nvme_submit_admin_cmd(dev, &c, &cmd.result, timeout);
eca18b23 1718
6bbf1acd 1719 if (cmd.data_len) {
1c2ad9fa 1720 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1721 nvme_free_iod(dev, iod);
6bbf1acd 1722 }
f4f117f6 1723
cf90bc48 1724 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1725 sizeof(cmd.result)))
1726 status = -EFAULT;
1727
6ee44cdc
MW		 1728 return status;
1729}
1730
b60503ba
MW		 1731static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1732 unsigned long arg)
1733{
1734 struct nvme_ns *ns = bdev->bd_disk->private_data;
1735
1736 switch (cmd) {
6bbf1acd 1737 case NVME_IOCTL_ID:
c3bfe717 1738 force_successful_syscall_return();
6bbf1acd
MW		 1739 return ns->ns_id;
1740 case NVME_IOCTL_ADMIN_CMD:
a4aea562 1741 return nvme_user_cmd(ns->dev, NULL, (void __user *)arg);
7963e521 1742 case NVME_IOCTL_IO_CMD:
a4aea562 1743 return nvme_user_cmd(ns->dev, ns, (void __user *)arg);
a53295b6
MW		 1744 case NVME_IOCTL_SUBMIT_IO:
1745 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1746 case SG_GET_VERSION_NUM:
1747 return nvme_sg_get_version_num((void __user *)arg);
1748 case SG_IO:
1749 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1750 default:
1751 return -ENOTTY;
1752 }
1753}
1754
320a3827
KB		 1755#ifdef CONFIG_COMPAT
1756static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1757 unsigned int cmd, unsigned long arg)
1758{
320a3827
KB		 1759 switch (cmd) {
1760 case SG_IO:
e179729a 1761 return -ENOIOCTLCMD;
320a3827
KB		 1762 }
1763 return nvme_ioctl(bdev, mode, cmd, arg);
1764}
1765#else
1766#define nvme_compat_ioctl NULL
1767#endif
1768
9ac27090
KB		 1769static int nvme_open(struct block_device *bdev, fmode_t mode)
1770{
9e60352c
KB		 1771 int ret = 0;
1772 struct nvme_ns *ns;
9ac27090 1773
9e60352c
KB		 1774 spin_lock(&dev_list_lock);
1775 ns = bdev->bd_disk->private_data;
1776 if (!ns)
1777 ret = -ENXIO;
1778 else if (!kref_get_unless_zero(&ns->dev->kref))
1779 ret = -ENXIO;
1780 spin_unlock(&dev_list_lock);
1781
1782 return ret;
9ac27090
KB		 1783}
1784
1785static void nvme_free_dev(struct kref *kref);
1786
1787static void nvme_release(struct gendisk *disk, fmode_t mode)
1788{
1789 struct nvme_ns *ns = disk->private_data;
1790 struct nvme_dev *dev = ns->dev;
1791
1792 kref_put(&dev->kref, nvme_free_dev);
1793}
1794
4cc09e2d
KB		 1795static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1796{
1797 /* some standard values */
1798 geo->heads = 1 << 6;
1799 geo->sectors = 1 << 5;
1800 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1801 return 0;
1802}
1803
1b9dbf7f
KB		 1804static int nvme_revalidate_disk(struct gendisk *disk)
1805{
1806 struct nvme_ns *ns = disk->private_data;
1807 struct nvme_dev *dev = ns->dev;
1808 struct nvme_id_ns *id;
1809 dma_addr_t dma_addr;
1810 int lbaf;
1811
1812 id = dma_alloc_coherent(&dev->pci_dev->dev, 4096, &dma_addr,
1813 GFP_KERNEL);
1814 if (!id) {
1815 dev_warn(&dev->pci_dev->dev, "%s: Memory alocation failure\n",
1816 __func__);
1817 return 0;
1818 }
1819
1820 if (nvme_identify(dev, ns->ns_id, 0, dma_addr))
1821 goto free;
1822
1823 lbaf = id->flbas & 0xf;
1824 ns->lba_shift = id->lbaf[lbaf].ds;
1825
1826 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
1827 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1828 free:
1829 dma_free_coherent(&dev->pci_dev->dev, 4096, id, dma_addr);
1830 return 0;
1831}
1832
b60503ba
MW		 1833static const struct block_device_operations nvme_fops = {
1834 .owner = THIS_MODULE,
1835 .ioctl = nvme_ioctl,
320a3827 1836 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1837 .open = nvme_open,
1838 .release = nvme_release,
4cc09e2d 1839 .getgeo = nvme_getgeo,
1b9dbf7f 1840 .revalidate_disk= nvme_revalidate_disk,
b60503ba
MW		 1841};
1842
1fa6aead
MW		 1843static int nvme_kthread(void *data)
1844{
d4b4ff8e 1845 struct nvme_dev *dev, *next;
1fa6aead
MW		 1846
1847 while (!kthread_should_stop()) {
564a232c 1848 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1849 spin_lock(&dev_list_lock);
d4b4ff8e 1850 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1851 int i;
d4b4ff8e
KB		 1852 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1853 dev->initialized) {
1854 if (work_busy(&dev->reset_work))
1855 continue;
1856 list_del_init(&dev->node);
1857 dev_warn(&dev->pci_dev->dev,
a4aea562
MB		 1858 "Failed status: %x, reset controller\n",
1859 readl(&dev->bar->csts));
9ca97374 1860 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1861 queue_work(nvme_workq, &dev->reset_work);
1862 continue;
1863 }
1fa6aead 1864 for (i = 0; i < dev->queue_count; i++) {
a4aea562 1865 struct nvme_queue *nvmeq = dev->queues[i];
740216fc
MW		 1866 if (!nvmeq)
1867 continue;
1fa6aead 1868 spin_lock_irq(&nvmeq->q_lock);
bc57a0f7 1869 nvme_process_cq(nvmeq);
6fccf938
KB		 1870
1871 while ((i == 0) && (dev->event_limit > 0)) {
a4aea562 1872 if (nvme_submit_async_admin_req(dev))
6fccf938
KB		 1873 break;
1874 dev->event_limit--;
1875 }
1fa6aead
MW		 1876 spin_unlock_irq(&nvmeq->q_lock);
1877 }
1878 }
1879 spin_unlock(&dev_list_lock);
acb7aa0d 1880 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1881 }
1882 return 0;
1883}
1884
0e5e4f0e
KB		 1885static void nvme_config_discard(struct nvme_ns *ns)
1886{
1887 u32 logical_block_size = queue_logical_block_size(ns->queue);
1888 ns->queue->limits.discard_zeroes_data = 0;
1889 ns->queue->limits.discard_alignment = logical_block_size;
1890 ns->queue->limits.discard_granularity = logical_block_size;
1891 ns->queue->limits.max_discard_sectors = 0xffffffff;
1892 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1893}
1894
c3bfe717 1895static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1896 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1897{
1898 struct nvme_ns *ns;
1899 struct gendisk *disk;
a4aea562 1900 int node = dev_to_node(&dev->pci_dev->dev);
b60503ba
MW		 1901 int lbaf;
1902
1903 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1904 return NULL;
1905
a4aea562 1906 ns = kzalloc_node(sizeof(*ns), GFP_KERNEL, node);
b60503ba
MW		 1907 if (!ns)
1908 return NULL;
a4aea562 1909 ns->queue = blk_mq_init_queue(&dev->tagset);
9f173b33 1910 if (IS_ERR(ns->queue))
b60503ba 1911 goto out_free_ns;
4eeb9215
MW		 1912 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1913 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
a4aea562 1914 queue_flag_set_unlocked(QUEUE_FLAG_SG_GAPS, ns->queue);
b60503ba
MW		 1915 ns->dev = dev;
1916 ns->queue->queuedata = ns;
1917
a4aea562 1918 disk = alloc_disk_node(0, node);
b60503ba
MW		 1919 if (!disk)
1920 goto out_free_queue;
a4aea562 1921
5aff9382 1922 ns->ns_id = nsid;
b60503ba
MW		 1923 ns->disk = disk;
1924 lbaf = id->flbas & 0xf;
1925 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1926 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1927 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1928 if (dev->max_hw_sectors)
1929 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a4aea562
MB		 1930 if (dev->stripe_size)
1931 blk_queue_chunk_sectors(ns->queue, dev->stripe_size >> 9);
a7d2ce28
KB		 1932 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1933 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW		 1934
1935 disk->major = nvme_major;
469071a3 1936 disk->first_minor = 0;
b60503ba
MW		 1937 disk->fops = &nvme_fops;
1938 disk->private_data = ns;
1939 disk->queue = ns->queue;
388f037f 1940 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1941 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1942 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1943 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1944
0e5e4f0e
KB		 1945 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1946 nvme_config_discard(ns);
1947
b60503ba
MW		 1948 return ns;
1949
1950 out_free_queue:
1951 blk_cleanup_queue(ns->queue);
1952 out_free_ns:
1953 kfree(ns);
1954 return NULL;
1955}
1956
42f61420
KB		 1957static void nvme_create_io_queues(struct nvme_dev *dev)
1958{
a4aea562 1959 unsigned i;
42f61420 1960
a4aea562 1961 for (i = dev->queue_count; i <= dev->max_qid; i++)
2b25d981 1962 if (!nvme_alloc_queue(dev, i, dev->q_depth))
42f61420
KB		 1963 break;
1964
a4aea562
MB		 1965 for (i = dev->online_queues; i <= dev->queue_count - 1; i++)
1966 if (nvme_create_queue(dev->queues[i], i))
42f61420
KB		 1967 break;
1968}
1969
b3b06812 1970static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 1971{
1972 int status;
1973 u32 result;
b3b06812 1974 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 1975
df348139 1976 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 1977 &result);
27e8166c
MW		 1978 if (status < 0)
1979 return status;
1980 if (status > 0) {
1981 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
1982 status);
badc34d4 1983 return 0;
27e8166c 1984 }
b60503ba
MW		 1985 return min(result & 0xffff, result >> 16) + 1;
1986}
1987
9d713c2b
KB		 1988static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1989{
b80d5ccc 1990 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 1991}
1992
8d85fce7 1993static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 1994{
a4aea562 1995 struct nvme_queue *adminq = dev->queues[0];
fa08a396 1996 struct pci_dev *pdev = dev->pci_dev;
42f61420 1997 int result, i, vecs, nr_io_queues, size;
b60503ba 1998
42f61420 1999 nr_io_queues = num_possible_cpus();
b348b7d5 2000 result = set_queue_count(dev, nr_io_queues);
badc34d4 2001 if (result <= 0)
1b23484b 2002 return result;
b348b7d5
MW		 2003 if (result < nr_io_queues)
2004 nr_io_queues = result;
b60503ba 2005
9d713c2b
KB		 2006 size = db_bar_size(dev, nr_io_queues);
2007 if (size > 8192) {
f1938f6e 2008 iounmap(dev->bar);
9d713c2b
KB		 2009 do {
2010 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2011 if (dev->bar)
2012 break;
2013 if (!--nr_io_queues)
2014 return -ENOMEM;
2015 size = db_bar_size(dev, nr_io_queues);
2016 } while (1);
f1938f6e 2017 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2018 adminq->q_db = dev->dbs;
f1938f6e
MW		 2019 }
2020
9d713c2b 2021 /* Deregister the admin queue's interrupt */
3193f07b 2022 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2023
e32efbfc
JA		 2024 /*
2025 * If we enable msix early due to not intx, disable it again before
2026 * setting up the full range we need.
2027 */
2028 if (!pdev->irq)
2029 pci_disable_msix(pdev);
2030
be577fab 2031 for (i = 0; i < nr_io_queues; i++)
1b23484b 2032 dev->entry[i].entry = i;
be577fab
AG		 2033 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2034 if (vecs < 0) {
2035 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2036 if (vecs < 0) {
2037 vecs = 1;
2038 } else {
2039 for (i = 0; i < vecs; i++)
2040 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2041 }
2042 }
2043
063a8096
MW		 2044 /*
2045 * Should investigate if there's a performance win from allocating
2046 * more queues than interrupt vectors; it might allow the submission
2047 * path to scale better, even if the receive path is limited by the
2048 * number of interrupts.
2049 */
2050 nr_io_queues = vecs;
42f61420 2051 dev->max_qid = nr_io_queues;
063a8096 2052
3193f07b 2053 result = queue_request_irq(dev, adminq, adminq->irqname);
a4aea562 2054 if (result)
22404274 2055 goto free_queues;
1b23484b 2056
cd638946 2057 /* Free previously allocated queues that are no longer usable */
42f61420 2058 nvme_free_queues(dev, nr_io_queues + 1);
a4aea562 2059 nvme_create_io_queues(dev);
9ecdc946 2060
22404274 2061 return 0;
b60503ba 2062
22404274 2063 free_queues:
a1a5ef99 2064 nvme_free_queues(dev, 1);
22404274 2065 return result;
b60503ba
MW		 2066}
2067
422ef0c7
MW		 2068/*
2069 * Return: error value if an error occurred setting up the queues or calling
2070 * Identify Device. 0 if these succeeded, even if adding some of the
2071 * namespaces failed. At the moment, these failures are silent. TBD which
2072 * failures should be reported.
2073 */
8d85fce7 2074static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2075{
68608c26 2076 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2077 int res;
2078 unsigned nn, i;
cbb6218f 2079 struct nvme_ns *ns;
51814232 2080 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2081 struct nvme_id_ns *id_ns;
2082 void *mem;
b60503ba 2083 dma_addr_t dma_addr;
159b67d7 2084 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2085
68608c26 2086 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2087 if (!mem)
2088 return -ENOMEM;
b60503ba 2089
bc5fc7e4 2090 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2091 if (res) {
27e8166c 2092 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2093 res = -EIO;
cbb6218f 2094 goto out;
b60503ba
MW		 2095 }
2096
bc5fc7e4 2097 ctrl = mem;
51814232 2098 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2099 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2100 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2101 dev->vwc = ctrl->vwc;
6fccf938 2102 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW		 2103 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2104 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2105 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2106 if (ctrl->mdts)
8fc23e03 2107 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26 2108 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
a4aea562
MB		 2109 (pdev->device == 0x0953) && ctrl->vs[3]) {
2110 unsigned int max_hw_sectors;
2111
159b67d7 2112 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
a4aea562
MB		 2113 max_hw_sectors = dev->stripe_size >> (shift - 9);
2114 if (dev->max_hw_sectors) {
2115 dev->max_hw_sectors = min(max_hw_sectors,
2116 dev->max_hw_sectors);
2117 } else
2118 dev->max_hw_sectors = max_hw_sectors;
2119 }
2120
2121 dev->tagset.ops = &nvme_mq_ops;
2122 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2123 dev->tagset.timeout = NVME_IO_TIMEOUT;
2124 dev->tagset.numa_node = dev_to_node(&dev->pci_dev->dev);
2125 dev->tagset.queue_depth =
2126 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2127 dev->tagset.cmd_size = sizeof(struct nvme_cmd_info);
2128 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2129 dev->tagset.driver_data = dev;
2130
2131 if (blk_mq_alloc_tag_set(&dev->tagset))
2132 goto out;
b60503ba 2133
bc5fc7e4 2134 id_ns = mem;
2b2c1896 2135 for (i = 1; i <= nn; i++) {
bc5fc7e4 2136 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2137 if (res)
2138 continue;
2139
bc5fc7e4 2140 if (id_ns->ncap == 0)
b60503ba
MW		 2141 continue;
2142
bc5fc7e4 2143 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2144 dma_addr + 4096, NULL);
b60503ba 2145 if (res)
12209036 2146 memset(mem + 4096, 0, 4096);
b60503ba 2147
bc5fc7e4 2148 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2149 if (ns)
2150 list_add_tail(&ns->list, &dev->namespaces);
2151 }
2152 list_for_each_entry(ns, &dev->namespaces, list)
2153 add_disk(ns->disk);
422ef0c7 2154 res = 0;
b60503ba 2155
bc5fc7e4 2156 out:
684f5c20 2157 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2158 return res;
2159}
2160
0877cb0d
KB		 2161static int nvme_dev_map(struct nvme_dev *dev)
2162{
42f61420 2163 u64 cap;
0877cb0d
KB		 2164 int bars, result = -ENOMEM;
2165 struct pci_dev *pdev = dev->pci_dev;
2166
2167 if (pci_enable_device_mem(pdev))
2168 return result;
2169
2170 dev->entry[0].vector = pdev->irq;
2171 pci_set_master(pdev);
2172 bars = pci_select_bars(pdev, IORESOURCE_MEM);
be7837e8
JA		 2173 if (!bars)
2174 goto disable_pci;
2175
0877cb0d
KB		 2176 if (pci_request_selected_regions(pdev, bars, "nvme"))
2177 goto disable_pci;
2178
052d0efa
RK		 2179 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2180 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2181 goto disable;
0877cb0d 2182
0877cb0d
KB		 2183 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2184 if (!dev->bar)
2185 goto disable;
e32efbfc 2186
0e53d180
KB		 2187 if (readl(&dev->bar->csts) == -1) {
2188 result = -ENODEV;
2189 goto unmap;
2190 }
e32efbfc
JA		 2191
2192 /*
2193 * Some devices don't advertse INTx interrupts, pre-enable a single
2194 * MSIX vec for setup. We'll adjust this later.
2195 */
2196 if (!pdev->irq) {
2197 result = pci_enable_msix(pdev, dev->entry, 1);
2198 if (result < 0)
2199 goto unmap;
2200 }
2201
42f61420
KB		 2202 cap = readq(&dev->bar->cap);
2203 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2204 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2205 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2206
2207 return 0;
2208
0e53d180
KB		 2209 unmap:
2210 iounmap(dev->bar);
2211 dev->bar = NULL;
0877cb0d
KB		 2212 disable:
2213 pci_release_regions(pdev);
2214 disable_pci:
2215 pci_disable_device(pdev);
2216 return result;
2217}
2218
2219static void nvme_dev_unmap(struct nvme_dev *dev)
2220{
2221 if (dev->pci_dev->msi_enabled)
2222 pci_disable_msi(dev->pci_dev);
2223 else if (dev->pci_dev->msix_enabled)
2224 pci_disable_msix(dev->pci_dev);
2225
2226 if (dev->bar) {
2227 iounmap(dev->bar);
2228 dev->bar = NULL;
9a6b9458 2229 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2230 }
2231
0877cb0d
KB		 2232 if (pci_is_enabled(dev->pci_dev))
2233 pci_disable_device(dev->pci_dev);
2234}
2235
4d115420
KB		 2236struct nvme_delq_ctx {
2237 struct task_struct *waiter;
2238 struct kthread_worker *worker;
2239 atomic_t refcount;
2240};
2241
2242static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2243{
2244 dq->waiter = current;
2245 mb();
2246
2247 for (;;) {
2248 set_current_state(TASK_KILLABLE);
2249 if (!atomic_read(&dq->refcount))
2250 break;
2251 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2252 fatal_signal_pending(current)) {
2253 set_current_state(TASK_RUNNING);
2254
2255 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2256 nvme_disable_queue(dev, 0);
2257
2258 send_sig(SIGKILL, dq->worker->task, 1);
2259 flush_kthread_worker(dq->worker);
2260 return;
2261 }
2262 }
2263 set_current_state(TASK_RUNNING);
2264}
2265
2266static void nvme_put_dq(struct nvme_delq_ctx *dq)
2267{
2268 atomic_dec(&dq->refcount);
2269 if (dq->waiter)
2270 wake_up_process(dq->waiter);
2271}
2272
2273static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2274{
2275 atomic_inc(&dq->refcount);
2276 return dq;
2277}
2278
2279static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2280{
2281 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2282
2283 nvme_clear_queue(nvmeq);
2284 nvme_put_dq(dq);
2285}
2286
2287static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2288 kthread_work_func_t fn)
2289{
2290 struct nvme_command c;
2291
2292 memset(&c, 0, sizeof(c));
2293 c.delete_queue.opcode = opcode;
2294 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2295
2296 init_kthread_work(&nvmeq->cmdinfo.work, fn);
a4aea562
MB		 2297 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo,
2298 ADMIN_TIMEOUT);
4d115420
KB		 2299}
2300
2301static void nvme_del_cq_work_handler(struct kthread_work *work)
2302{
2303 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2304 cmdinfo.work);
2305 nvme_del_queue_end(nvmeq);
2306}
2307
2308static int nvme_delete_cq(struct nvme_queue *nvmeq)
2309{
2310 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2311 nvme_del_cq_work_handler);
2312}
2313
2314static void nvme_del_sq_work_handler(struct kthread_work *work)
2315{
2316 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2317 cmdinfo.work);
2318 int status = nvmeq->cmdinfo.status;
2319
2320 if (!status)
2321 status = nvme_delete_cq(nvmeq);
2322 if (status)
2323 nvme_del_queue_end(nvmeq);
2324}
2325
2326static int nvme_delete_sq(struct nvme_queue *nvmeq)
2327{
2328 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2329 nvme_del_sq_work_handler);
2330}
2331
2332static void nvme_del_queue_start(struct kthread_work *work)
2333{
2334 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2335 cmdinfo.work);
2336 allow_signal(SIGKILL);
2337 if (nvme_delete_sq(nvmeq))
2338 nvme_del_queue_end(nvmeq);
2339}
2340
2341static void nvme_disable_io_queues(struct nvme_dev *dev)
2342{
2343 int i;
2344 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2345 struct nvme_delq_ctx dq;
2346 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2347 &worker, "nvme%d", dev->instance);
2348
2349 if (IS_ERR(kworker_task)) {
2350 dev_err(&dev->pci_dev->dev,
2351 "Failed to create queue del task\n");
2352 for (i = dev->queue_count - 1; i > 0; i--)
2353 nvme_disable_queue(dev, i);
2354 return;
2355 }
2356
2357 dq.waiter = NULL;
2358 atomic_set(&dq.refcount, 0);
2359 dq.worker = &worker;
2360 for (i = dev->queue_count - 1; i > 0; i--) {
a4aea562 2361 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2362
2363 if (nvme_suspend_queue(nvmeq))
2364 continue;
2365 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2366 nvmeq->cmdinfo.worker = dq.worker;
2367 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2368 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2369 }
2370 nvme_wait_dq(&dq, dev);
2371 kthread_stop(kworker_task);
2372}
2373
b9afca3e
DM		 2374/*
2375* Remove the node from the device list and check
2376* for whether or not we need to stop the nvme_thread.
2377*/
2378static void nvme_dev_list_remove(struct nvme_dev *dev)
2379{
2380 struct task_struct *tmp = NULL;
2381
2382 spin_lock(&dev_list_lock);
2383 list_del_init(&dev->node);
2384 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2385 tmp = nvme_thread;
2386 nvme_thread = NULL;
2387 }
2388 spin_unlock(&dev_list_lock);
2389
2390 if (tmp)
2391 kthread_stop(tmp);
2392}
2393
f0b50732 2394static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2395{
22404274 2396 int i;
7c1b2450 2397 u32 csts = -1;
22404274 2398
d4b4ff8e 2399 dev->initialized = 0;
b9afca3e 2400 nvme_dev_list_remove(dev);
1fa6aead 2401
7c1b2450
KB		 2402 if (dev->bar)
2403 csts = readl(&dev->bar->csts);
2404 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
4d115420 2405 for (i = dev->queue_count - 1; i >= 0; i--) {
a4aea562 2406 struct nvme_queue *nvmeq = dev->queues[i];
4d115420
KB		 2407 nvme_suspend_queue(nvmeq);
2408 nvme_clear_queue(nvmeq);
2409 }
2410 } else {
2411 nvme_disable_io_queues(dev);
1894d8f1 2412 nvme_shutdown_ctrl(dev);
4d115420
KB		 2413 nvme_disable_queue(dev, 0);
2414 }
f0b50732
KB		 2415 nvme_dev_unmap(dev);
2416}
2417
a4aea562
MB		 2418static void nvme_dev_remove_admin(struct nvme_dev *dev)
2419{
2420 if (dev->admin_q && !blk_queue_dying(dev->admin_q))
2421 blk_cleanup_queue(dev->admin_q);
2422}
2423
f0b50732
KB		 2424static void nvme_dev_remove(struct nvme_dev *dev)
2425{
9ac27090 2426 struct nvme_ns *ns;
f0b50732 2427
9ac27090
KB		 2428 list_for_each_entry(ns, &dev->namespaces, list) {
2429 if (ns->disk->flags & GENHD_FL_UP)
2430 del_gendisk(ns->disk);
2431 if (!blk_queue_dying(ns->queue))
2432 blk_cleanup_queue(ns->queue);
b60503ba 2433 }
b60503ba
MW		 2434}
2435
091b6092
MW		 2436static int nvme_setup_prp_pools(struct nvme_dev *dev)
2437{
2438 struct device *dmadev = &dev->pci_dev->dev;
2439 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2440 PAGE_SIZE, PAGE_SIZE, 0);
2441 if (!dev->prp_page_pool)
2442 return -ENOMEM;
2443
99802a7a
MW		 2444 /* Optimisation for I/Os between 4k and 128k */
2445 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2446 256, 256, 0);
2447 if (!dev->prp_small_pool) {
2448 dma_pool_destroy(dev->prp_page_pool);
2449 return -ENOMEM;
2450 }
091b6092
MW		 2451 return 0;
2452}
2453
2454static void nvme_release_prp_pools(struct nvme_dev *dev)
2455{
2456 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2457 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2458}
2459
cd58ad7d
QSA		 2460static DEFINE_IDA(nvme_instance_ida);
2461
2462static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2463{
cd58ad7d
QSA		 2464 int instance, error;
2465
2466 do {
2467 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2468 return -ENODEV;
2469
2470 spin_lock(&dev_list_lock);
2471 error = ida_get_new(&nvme_instance_ida, &instance);
2472 spin_unlock(&dev_list_lock);
2473 } while (error == -EAGAIN);
2474
2475 if (error)
2476 return -ENODEV;
2477
2478 dev->instance = instance;
2479 return 0;
b60503ba
MW		 2480}
2481
2482static void nvme_release_instance(struct nvme_dev *dev)
2483{
cd58ad7d
QSA		 2484 spin_lock(&dev_list_lock);
2485 ida_remove(&nvme_instance_ida, dev->instance);
2486 spin_unlock(&dev_list_lock);
b60503ba
MW		 2487}
2488
9ac27090
KB		 2489static void nvme_free_namespaces(struct nvme_dev *dev)
2490{
2491 struct nvme_ns *ns, *next;
2492
2493 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2494 list_del(&ns->list);
9e60352c
KB		 2495
2496 spin_lock(&dev_list_lock);
2497 ns->disk->private_data = NULL;
2498 spin_unlock(&dev_list_lock);
2499
9ac27090
KB		 2500 put_disk(ns->disk);
2501 kfree(ns);
2502 }
2503}
2504
5e82e952
KB		 2505static void nvme_free_dev(struct kref *kref)
2506{
2507 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090 2508
a96d4f5c 2509 pci_dev_put(dev->pci_dev);
9ac27090 2510 nvme_free_namespaces(dev);
285dffc9 2511 nvme_release_instance(dev);
a4aea562 2512 blk_mq_free_tag_set(&dev->tagset);
5e82e952
KB		 2513 kfree(dev->queues);
2514 kfree(dev->entry);
2515 kfree(dev);
2516}
2517
2518static int nvme_dev_open(struct inode *inode, struct file *f)
2519{
2520 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2521 miscdev);
2522 kref_get(&dev->kref);
2523 f->private_data = dev;
2524 return 0;
2525}
2526
2527static int nvme_dev_release(struct inode *inode, struct file *f)
2528{
2529 struct nvme_dev *dev = f->private_data;
2530 kref_put(&dev->kref, nvme_free_dev);
2531 return 0;
2532}
2533
2534static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2535{
2536 struct nvme_dev *dev = f->private_data;
a4aea562
MB		 2537 struct nvme_ns *ns;
2538
5e82e952
KB		 2539 switch (cmd) {
2540 case NVME_IOCTL_ADMIN_CMD:
a4aea562 2541 return nvme_user_cmd(dev, NULL, (void __user *)arg);
7963e521 2542 case NVME_IOCTL_IO_CMD:
a4aea562
MB		 2543 if (list_empty(&dev->namespaces))
2544 return -ENOTTY;
2545 ns = list_first_entry(&dev->namespaces, struct nvme_ns, list);
2546 return nvme_user_cmd(dev, ns, (void __user *)arg);
5e82e952
KB		 2547 default:
2548 return -ENOTTY;
2549 }
2550}
2551
2552static const struct file_operations nvme_dev_fops = {
2553 .owner = THIS_MODULE,
2554 .open = nvme_dev_open,
2555 .release = nvme_dev_release,
2556 .unlocked_ioctl = nvme_dev_ioctl,
2557 .compat_ioctl = nvme_dev_ioctl,
2558};
2559
a4aea562
MB		 2560static void nvme_set_irq_hints(struct nvme_dev *dev)
2561{
2562 struct nvme_queue *nvmeq;
2563 int i;
2564
2565 for (i = 0; i < dev->online_queues; i++) {
2566 nvmeq = dev->queues[i];
2567
2568 if (!nvmeq->hctx)
2569 continue;
2570
2571 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2572 nvmeq->hctx->cpumask);
2573 }
2574}
2575
f0b50732
KB		 2576static int nvme_dev_start(struct nvme_dev *dev)
2577{
2578 int result;
b9afca3e 2579 bool start_thread = false;
f0b50732
KB		 2580
2581 result = nvme_dev_map(dev);
2582 if (result)
2583 return result;
2584
2585 result = nvme_configure_admin_queue(dev);
2586 if (result)
2587 goto unmap;
2588
2589 spin_lock(&dev_list_lock);
b9afca3e
DM		 2590 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2591 start_thread = true;
2592 nvme_thread = NULL;
2593 }
f0b50732
KB		 2594 list_add(&dev->node, &dev_list);
2595 spin_unlock(&dev_list_lock);
2596
b9afca3e
DM		 2597 if (start_thread) {
2598 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
387caa5a 2599 wake_up_all(&nvme_kthread_wait);
b9afca3e
DM		 2600 } else
2601 wait_event_killable(nvme_kthread_wait, nvme_thread);
2602
2603 if (IS_ERR_OR_NULL(nvme_thread)) {
2604 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2605 goto disable;
2606 }
a4aea562
MB		 2607
2608 nvme_init_queue(dev->queues[0], 0);
b9afca3e 2609
f0b50732 2610 result = nvme_setup_io_queues(dev);
badc34d4 2611 if (result)
f0b50732
KB		 2612 goto disable;
2613
a4aea562
MB		 2614 nvme_set_irq_hints(dev);
2615
d82e8bfd 2616 return result;
f0b50732
KB		 2617
2618 disable:
a1a5ef99 2619 nvme_disable_queue(dev, 0);
b9afca3e 2620 nvme_dev_list_remove(dev);
f0b50732
KB		 2621 unmap:
2622 nvme_dev_unmap(dev);
2623 return result;
2624}
2625
9a6b9458
KB		 2626static int nvme_remove_dead_ctrl(void *arg)
2627{
2628 struct nvme_dev *dev = (struct nvme_dev *)arg;
2629 struct pci_dev *pdev = dev->pci_dev;
2630
2631 if (pci_get_drvdata(pdev))
c81f4975 2632 pci_stop_and_remove_bus_device_locked(pdev);
9a6b9458
KB		 2633 kref_put(&dev->kref, nvme_free_dev);
2634 return 0;
2635}
2636
2637static void nvme_remove_disks(struct work_struct *ws)
2638{
9a6b9458
KB		 2639 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2640
5a92e700 2641 nvme_free_queues(dev, 1);
302c6727 2642 nvme_dev_remove(dev);
9a6b9458
KB		 2643}
2644
2645static int nvme_dev_resume(struct nvme_dev *dev)
2646{
2647 int ret;
2648
2649 ret = nvme_dev_start(dev);
badc34d4 2650 if (ret)
9a6b9458 2651 return ret;
badc34d4 2652 if (dev->online_queues < 2) {
9a6b9458 2653 spin_lock(&dev_list_lock);
9ca97374 2654 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2655 queue_work(nvme_workq, &dev->reset_work);
2656 spin_unlock(&dev_list_lock);
2657 }
d4b4ff8e 2658 dev->initialized = 1;
9a6b9458
KB		 2659 return 0;
2660}
2661
2662static void nvme_dev_reset(struct nvme_dev *dev)
2663{
2664 nvme_dev_shutdown(dev);
2665 if (nvme_dev_resume(dev)) {
a4aea562 2666 dev_warn(&dev->pci_dev->dev, "Device failed to resume\n");
9a6b9458
KB		 2667 kref_get(&dev->kref);
2668 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2669 dev->instance))) {
2670 dev_err(&dev->pci_dev->dev,
2671 "Failed to start controller remove task\n");
2672 kref_put(&dev->kref, nvme_free_dev);
2673 }
2674 }
2675}
2676
2677static void nvme_reset_failed_dev(struct work_struct *ws)
2678{
2679 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2680 nvme_dev_reset(dev);
2681}
2682
9ca97374
TH		 2683static void nvme_reset_workfn(struct work_struct *work)
2684{
2685 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2686 dev->reset_workfn(work);
2687}
2688
8d85fce7 2689static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2690{
a4aea562 2691 int node, result = -ENOMEM;
b60503ba
MW		 2692 struct nvme_dev *dev;
2693
a4aea562
MB		 2694 node = dev_to_node(&pdev->dev);
2695 if (node == NUMA_NO_NODE)
2696 set_dev_node(&pdev->dev, 0);
2697
2698 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
b60503ba
MW		 2699 if (!dev)
2700 return -ENOMEM;
a4aea562
MB		 2701 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry),
2702 GFP_KERNEL, node);
b60503ba
MW		 2703 if (!dev->entry)
2704 goto free;
a4aea562
MB		 2705 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2706 GFP_KERNEL, node);
b60503ba
MW		 2707 if (!dev->queues)
2708 goto free;
2709
2710 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2711 dev->reset_workfn = nvme_reset_failed_dev;
2712 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
a96d4f5c 2713 dev->pci_dev = pci_dev_get(pdev);
9a6b9458 2714 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2715 result = nvme_set_instance(dev);
2716 if (result)
a96d4f5c 2717 goto put_pci;
b60503ba 2718
091b6092
MW		 2719 result = nvme_setup_prp_pools(dev);
2720 if (result)
0877cb0d 2721 goto release;
091b6092 2722
fb35e914 2723 kref_init(&dev->kref);
f0b50732 2724 result = nvme_dev_start(dev);
badc34d4 2725 if (result)
0877cb0d 2726 goto release_pools;
b60503ba 2727
badc34d4
KB		 2728 if (dev->online_queues > 1)
2729 result = nvme_dev_add(dev);
d82e8bfd 2730 if (result)
f0b50732 2731 goto shutdown;
740216fc 2732
5e82e952
KB		 2733 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2734 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2735 dev->miscdev.parent = &pdev->dev;
2736 dev->miscdev.name = dev->name;
2737 dev->miscdev.fops = &nvme_dev_fops;
2738 result = misc_register(&dev->miscdev);
2739 if (result)
2740 goto remove;
2741
a4aea562
MB		 2742 nvme_set_irq_hints(dev);
2743
d4b4ff8e 2744 dev->initialized = 1;
b60503ba
MW		 2745 return 0;
2746
5e82e952
KB		 2747 remove:
2748 nvme_dev_remove(dev);
a4aea562 2749 nvme_dev_remove_admin(dev);
9ac27090 2750 nvme_free_namespaces(dev);
f0b50732
KB		 2751 shutdown:
2752 nvme_dev_shutdown(dev);
0877cb0d 2753 release_pools:
a1a5ef99 2754 nvme_free_queues(dev, 0);
091b6092 2755 nvme_release_prp_pools(dev);
0877cb0d
KB		 2756 release:
2757 nvme_release_instance(dev);
a96d4f5c
KB		 2758 put_pci:
2759 pci_dev_put(dev->pci_dev);
b60503ba
MW		 2760 free:
2761 kfree(dev->queues);
2762 kfree(dev->entry);
2763 kfree(dev);
2764 return result;
2765}
2766
f0d54a54
KB		 2767static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2768{
a6739479 2769 struct nvme_dev *dev = pci_get_drvdata(pdev);
f0d54a54 2770
a6739479
KB		 2771 if (prepare)
2772 nvme_dev_shutdown(dev);
2773 else
2774 nvme_dev_resume(dev);
f0d54a54
KB		 2775}
2776
09ece142
KB		 2777static void nvme_shutdown(struct pci_dev *pdev)
2778{
2779 struct nvme_dev *dev = pci_get_drvdata(pdev);
2780 nvme_dev_shutdown(dev);
2781}
2782
8d85fce7 2783static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2784{
2785 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2786
2787 spin_lock(&dev_list_lock);
2788 list_del_init(&dev->node);
2789 spin_unlock(&dev_list_lock);
2790
2791 pci_set_drvdata(pdev, NULL);
2792 flush_work(&dev->reset_work);
5e82e952 2793 misc_deregister(&dev->miscdev);
a4aea562 2794 nvme_dev_remove(dev);
9a6b9458 2795 nvme_dev_shutdown(dev);
a4aea562 2796 nvme_dev_remove_admin(dev);
a1a5ef99 2797 nvme_free_queues(dev, 0);
a4aea562 2798 nvme_free_admin_tags(dev);
9a6b9458 2799 nvme_release_prp_pools(dev);
5e82e952 2800 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2801}
2802
2803/* These functions are yet to be implemented */
2804#define nvme_error_detected NULL
2805#define nvme_dump_registers NULL
2806#define nvme_link_reset NULL
2807#define nvme_slot_reset NULL
2808#define nvme_error_resume NULL
cd638946 2809
671a6018 2810#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2811static int nvme_suspend(struct device *dev)
2812{
2813 struct pci_dev *pdev = to_pci_dev(dev);
2814 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2815
2816 nvme_dev_shutdown(ndev);
2817 return 0;
2818}
2819
2820static int nvme_resume(struct device *dev)
2821{
2822 struct pci_dev *pdev = to_pci_dev(dev);
2823 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2824
9a6b9458 2825 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2826 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2827 queue_work(nvme_workq, &ndev->reset_work);
2828 }
2829 return 0;
cd638946 2830}
671a6018 2831#endif
cd638946
KB		 2832
2833static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2834
1d352035 2835static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2836 .error_detected = nvme_error_detected,
2837 .mmio_enabled = nvme_dump_registers,
2838 .link_reset = nvme_link_reset,
2839 .slot_reset = nvme_slot_reset,
2840 .resume = nvme_error_resume,
f0d54a54 2841 .reset_notify = nvme_reset_notify,
b60503ba
MW		 2842};
2843
2844/* Move to pci_ids.h later */
2845#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2846
6eb0d698 2847static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2848 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2849 { 0, }
2850};
2851MODULE_DEVICE_TABLE(pci, nvme_id_table);
2852
2853static struct pci_driver nvme_driver = {
2854 .name = "nvme",
2855 .id_table = nvme_id_table,
2856 .probe = nvme_probe,
8d85fce7 2857 .remove = nvme_remove,
09ece142 2858 .shutdown = nvme_shutdown,
cd638946
KB		 2859 .driver = {
2860 .pm = &nvme_dev_pm_ops,
2861 },
b60503ba
MW		 2862 .err_handler = &nvme_err_handler,
2863};
2864
2865static int __init nvme_init(void)
2866{
0ac13140 2867 int result;
1fa6aead 2868
b9afca3e 2869 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2870
9a6b9458
KB		 2871 nvme_workq = create_singlethread_workqueue("nvme");
2872 if (!nvme_workq)
b9afca3e 2873 return -ENOMEM;
9a6b9458 2874
5c42ea16
KB		 2875 result = register_blkdev(nvme_major, "nvme");
2876 if (result < 0)
9a6b9458 2877 goto kill_workq;
5c42ea16 2878 else if (result > 0)
0ac13140 2879 nvme_major = result;
b60503ba 2880
f3db22fe
KB		 2881 result = pci_register_driver(&nvme_driver);
2882 if (result)
a4aea562 2883 goto unregister_blkdev;
1fa6aead 2884 return 0;
b60503ba 2885
1fa6aead 2886 unregister_blkdev:
b60503ba 2887 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2888 kill_workq:
2889 destroy_workqueue(nvme_workq);
b60503ba
MW		 2890 return result;
2891}
2892
2893static void __exit nvme_exit(void)
2894{
2895 pci_unregister_driver(&nvme_driver);
f3db22fe 2896 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 2897 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2898 destroy_workqueue(nvme_workq);
b9afca3e 2899 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 2900 _nvme_check_size();
b60503ba
MW		 2901}
2902
2903MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2904MODULE_LICENSE("GPL");
c78b4713 2905MODULE_VERSION("1.0");
b60503ba
MW		 2906module_init(nvme_init);
2907module_exit(nvme_exit);
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