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Commit | Line | Data |
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0ebc4cda BH |
1 | /* |
2 | * This file contains the 64-bit "server" PowerPC variant | |
3 | * of the low level exception handling including exception | |
4 | * vectors, exception return, part of the slb and stab | |
5 | * handling and other fixed offset specific things. | |
6 | * | |
7 | * This file is meant to be #included from head_64.S due to | |
25985edc | 8 | * position dependent assembly. |
0ebc4cda BH |
9 | * |
10 | * Most of this originates from head_64.S and thus has the same | |
11 | * copyright history. | |
12 | * | |
13 | */ | |
14 | ||
7230c564 | 15 | #include <asm/hw_irq.h> |
8aa34ab8 | 16 | #include <asm/exception-64s.h> |
46f52210 | 17 | #include <asm/ptrace.h> |
7cba160a | 18 | #include <asm/cpuidle.h> |
da2bc464 | 19 | #include <asm/head-64.h> |
8aa34ab8 | 20 | |
0ebc4cda | 21 | /* |
57f26649 NP |
22 | * There are a few constraints to be concerned with. |
23 | * - Real mode exceptions code/data must be located at their physical location. | |
24 | * - Virtual mode exceptions must be mapped at their 0xc000... location. | |
25 | * - Fixed location code must not call directly beyond the __end_interrupts | |
26 | * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence | |
27 | * must be used. | |
28 | * - LOAD_HANDLER targets must be within first 64K of physical 0 / | |
29 | * virtual 0xc00... | |
30 | * - Conditional branch targets must be within +/-32K of caller. | |
31 | * | |
32 | * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and | |
33 | * therefore don't have to run in physically located code or rfid to | |
34 | * virtual mode kernel code. However on relocatable kernels they do have | |
35 | * to branch to KERNELBASE offset because the rest of the kernel (outside | |
36 | * the exception vectors) may be located elsewhere. | |
37 | * | |
38 | * Virtual exceptions correspond with physical, except their entry points | |
39 | * are offset by 0xc000000000000000 and also tend to get an added 0x4000 | |
40 | * offset applied. Virtual exceptions are enabled with the Alternate | |
41 | * Interrupt Location (AIL) bit set in the LPCR. However this does not | |
42 | * guarantee they will be delivered virtually. Some conditions (see the ISA) | |
43 | * cause exceptions to be delivered in real mode. | |
44 | * | |
45 | * It's impossible to receive interrupts below 0x300 via AIL. | |
46 | * | |
47 | * KVM: None of the virtual exceptions are from the guest. Anything that | |
48 | * escalated to HV=1 from HV=0 is delivered via real mode handlers. | |
49 | * | |
50 | * | |
0ebc4cda BH |
51 | * We layout physical memory as follows: |
52 | * 0x0000 - 0x00ff : Secondary processor spin code | |
57f26649 NP |
53 | * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors |
54 | * 0x1900 - 0x3fff : Real mode trampolines | |
55 | * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors | |
56 | * 0x5900 - 0x6fff : Relon mode trampolines | |
0ebc4cda | 57 | * 0x7000 - 0x7fff : FWNMI data area |
57f26649 NP |
58 | * 0x8000 - .... : Common interrupt handlers, remaining early |
59 | * setup code, rest of kernel. | |
60 | */ | |
61 | OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900) | |
62 | OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000) | |
63 | OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900) | |
64 | OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000) | |
65 | #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV) | |
66 | /* | |
67 | * Data area reserved for FWNMI option. | |
68 | * This address (0x7000) is fixed by the RPA. | |
69 | * pseries and powernv need to keep the whole page from | |
70 | * 0x7000 to 0x8000 free for use by the firmware | |
0ebc4cda | 71 | */ |
57f26649 NP |
72 | ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000) |
73 | OPEN_TEXT_SECTION(0x8000) | |
74 | #else | |
75 | OPEN_TEXT_SECTION(0x7000) | |
76 | #endif | |
77 | ||
78 | USE_FIXED_SECTION(real_vectors) | |
79 | ||
80 | #define LOAD_SYSCALL_HANDLER(reg) \ | |
81 | ld reg,PACAKBASE(r13); \ | |
82 | ori reg,reg,(ABS_ADDR(system_call_common))@l; | |
83 | ||
742415d6 MN |
84 | /* Syscall routine is used twice, in reloc-off and reloc-on paths */ |
85 | #define SYSCALL_PSERIES_1 \ | |
86 | BEGIN_FTR_SECTION \ | |
87 | cmpdi r0,0x1ebe ; \ | |
88 | beq- 1f ; \ | |
89 | END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \ | |
90 | mr r9,r13 ; \ | |
91 | GET_PACA(r13) ; \ | |
92 | mfspr r11,SPRN_SRR0 ; \ | |
93 | 0: | |
94 | ||
95 | #define SYSCALL_PSERIES_2_RFID \ | |
96 | mfspr r12,SPRN_SRR1 ; \ | |
57f26649 | 97 | LOAD_SYSCALL_HANDLER(r10) ; \ |
742415d6 MN |
98 | mtspr SPRN_SRR0,r10 ; \ |
99 | ld r10,PACAKMSR(r13) ; \ | |
100 | mtspr SPRN_SRR1,r10 ; \ | |
101 | rfid ; \ | |
102 | b . ; /* prevent speculative execution */ | |
103 | ||
104 | #define SYSCALL_PSERIES_3 \ | |
105 | /* Fast LE/BE switch system call */ \ | |
106 | 1: mfspr r12,SPRN_SRR1 ; \ | |
107 | xori r12,r12,MSR_LE ; \ | |
108 | mtspr SPRN_SRR1,r12 ; \ | |
109 | rfid ; /* return to userspace */ \ | |
742415d6 MN |
110 | b . ; /* prevent speculative execution */ |
111 | ||
4700dfaf MN |
112 | #if defined(CONFIG_RELOCATABLE) |
113 | /* | |
05b05f28 AB |
114 | * We can't branch directly so we do it via the CTR which |
115 | * is volatile across system calls. | |
4700dfaf MN |
116 | */ |
117 | #define SYSCALL_PSERIES_2_DIRECT \ | |
57f26649 | 118 | LOAD_SYSCALL_HANDLER(r12) ; \ |
6a404806 | 119 | mtctr r12 ; \ |
4700dfaf | 120 | mfspr r12,SPRN_SRR1 ; \ |
18e3f56b NP |
121 | li r10,MSR_RI ; \ |
122 | mtmsrd r10,1 ; \ | |
6a404806 | 123 | bctr ; |
4700dfaf MN |
124 | #else |
125 | /* We can branch directly */ | |
126 | #define SYSCALL_PSERIES_2_DIRECT \ | |
127 | mfspr r12,SPRN_SRR1 ; \ | |
128 | li r10,MSR_RI ; \ | |
129 | mtmsrd r10,1 ; /* Set RI (EE=0) */ \ | |
d20be433 | 130 | b system_call_common ; |
4700dfaf | 131 | #endif |
0ebc4cda | 132 | |
0ebc4cda BH |
133 | /* |
134 | * This is the start of the interrupt handlers for pSeries | |
135 | * This code runs with relocation off. | |
136 | * Code from here to __end_interrupts gets copied down to real | |
137 | * address 0x100 when we are running a relocatable kernel. | |
138 | * Therefore any relative branches in this section must only | |
139 | * branch to labels in this section. | |
140 | */ | |
0ebc4cda BH |
141 | .globl __start_interrupts |
142 | __start_interrupts: | |
143 | ||
da2bc464 | 144 | EXC_REAL_BEGIN(system_reset, 0x100, 0x200) |
948cf67c BH |
145 | SET_SCRATCH0(r13) |
146 | #ifdef CONFIG_PPC_P7_NAP | |
147 | BEGIN_FTR_SECTION | |
148 | /* Running native on arch 2.06 or later, check if we are | |
77b54e9f | 149 | * waking up from nap/sleep/winkle. |
948cf67c BH |
150 | */ |
151 | mfspr r13,SPRN_SRR1 | |
371fefd6 PM |
152 | rlwinm. r13,r13,47-31,30,31 |
153 | beq 9f | |
154 | ||
7cba160a | 155 | cmpwi cr3,r13,2 |
371fefd6 | 156 | GET_PACA(r13) |
5fa6b6bd | 157 | bl pnv_restore_hyp_resource |
77b54e9f | 158 | |
7cba160a SP |
159 | li r0,PNV_THREAD_RUNNING |
160 | stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */ | |
371fefd6 | 161 | |
3a167bea | 162 | #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE |
f0888f70 PM |
163 | li r0,KVM_HWTHREAD_IN_KERNEL |
164 | stb r0,HSTATE_HWTHREAD_STATE(r13) | |
165 | /* Order setting hwthread_state vs. testing hwthread_req */ | |
166 | sync | |
167 | lbz r0,HSTATE_HWTHREAD_REQ(r13) | |
168 | cmpwi r0,0 | |
169 | beq 1f | |
371fefd6 PM |
170 | b kvm_start_guest |
171 | 1: | |
172 | #endif | |
173 | ||
56548fc0 PM |
174 | /* Return SRR1 from power7_nap() */ |
175 | mfspr r3,SPRN_SRR1 | |
17065671 | 176 | blt cr3,2f |
5fa6b6bd SP |
177 | b pnv_wakeup_loss |
178 | 2: b pnv_wakeup_noloss | |
aca79d2b | 179 | |
371fefd6 | 180 | 9: |
969391c5 | 181 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
948cf67c | 182 | #endif /* CONFIG_PPC_P7_NAP */ |
b01c8b54 PM |
183 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, |
184 | NOTEST, 0x100) | |
da2bc464 | 185 | EXC_REAL_END(system_reset, 0x100, 0x200) |
582baf44 NP |
186 | EXC_VIRT_NONE(0x4100, 0x4200) |
187 | EXC_COMMON(system_reset_common, 0x100, system_reset_exception) | |
188 | ||
189 | #ifdef CONFIG_PPC_PSERIES | |
190 | /* | |
191 | * Vectors for the FWNMI option. Share common code. | |
192 | */ | |
193 | TRAMP_REAL_BEGIN(system_reset_fwnmi) | |
194 | SET_SCRATCH0(r13) /* save r13 */ | |
195 | EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD, | |
196 | NOTEST, 0x100) | |
197 | #endif /* CONFIG_PPC_PSERIES */ | |
198 | ||
0ebc4cda | 199 | |
da2bc464 | 200 | EXC_REAL_BEGIN(machine_check, 0x200, 0x300) |
b01c8b54 PM |
201 | /* This is moved out of line as it can be patched by FW, but |
202 | * some code path might still want to branch into the original | |
203 | * vector | |
204 | */ | |
1707dd16 | 205 | SET_SCRATCH0(r13) /* save r13 */ |
bc14c491 MS |
206 | /* |
207 | * Running native on arch 2.06 or later, we may wakeup from winkle | |
208 | * inside machine check. If yes, then last bit of HSPGR0 would be set | |
209 | * to 1. Hence clear it unconditionally. | |
1c51089f | 210 | */ |
bc14c491 MS |
211 | GET_PACA(r13) |
212 | clrrdi r13,r13,1 | |
213 | SET_PACA(r13) | |
1707dd16 | 214 | EXCEPTION_PROLOG_0(PACA_EXMC) |
1e9b4507 | 215 | BEGIN_FTR_SECTION |
2513767d | 216 | b machine_check_powernv_early |
1e9b4507 | 217 | FTR_SECTION_ELSE |
1707dd16 | 218 | b machine_check_pSeries_0 |
1e9b4507 | 219 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
da2bc464 | 220 | EXC_REAL_END(machine_check, 0x200, 0x300) |
0ebc4cda | 221 | |
da2bc464 | 222 | EXC_REAL(data_access, 0x300, 0x380) |
0ebc4cda | 223 | |
da2bc464 | 224 | EXC_REAL_BEGIN(data_access_slb, 0x380, 0x400) |
673b189a | 225 | SET_SCRATCH0(r13) |
1707dd16 | 226 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 227 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380) |
0ebc4cda BH |
228 | std r3,PACA_EXSLB+EX_R3(r13) |
229 | mfspr r3,SPRN_DAR | |
b01c8b54 | 230 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 231 | crset 4*cr6+eq |
0ebc4cda | 232 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 233 | b slb_miss_realmode |
0ebc4cda BH |
234 | #else |
235 | /* | |
ad0289e4 | 236 | * We can't just use a direct branch to slb_miss_realmode |
0ebc4cda BH |
237 | * because the distance from here to there depends on where |
238 | * the kernel ends up being put. | |
239 | */ | |
240 | mfctr r11 | |
ad0289e4 | 241 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
242 | mtctr r10 |
243 | bctr | |
244 | #endif | |
da2bc464 | 245 | EXC_REAL_END(data_access_slb, 0x380, 0x400) |
0ebc4cda | 246 | |
da2bc464 | 247 | EXC_REAL(instruction_access, 0x400, 0x480) |
0ebc4cda | 248 | |
da2bc464 | 249 | EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x500) |
673b189a | 250 | SET_SCRATCH0(r13) |
1707dd16 | 251 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
da2bc464 | 252 | EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480) |
0ebc4cda BH |
253 | std r3,PACA_EXSLB+EX_R3(r13) |
254 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
b01c8b54 | 255 | mfspr r12,SPRN_SRR1 |
f0f558b1 | 256 | crclr 4*cr6+eq |
0ebc4cda | 257 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 258 | b slb_miss_realmode |
0ebc4cda BH |
259 | #else |
260 | mfctr r11 | |
ad0289e4 | 261 | LOAD_HANDLER(r10, slb_miss_realmode) |
0ebc4cda BH |
262 | mtctr r10 |
263 | bctr | |
264 | #endif | |
da2bc464 | 265 | EXC_REAL_END(instruction_access_slb, 0x480, 0x500) |
0ebc4cda | 266 | |
da2bc464 | 267 | EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x600) |
b3e6b5df | 268 | .globl hardware_interrupt_hv; |
b3e6b5df | 269 | hardware_interrupt_hv: |
a5d4f3ad | 270 | BEGIN_FTR_SECTION |
da2bc464 | 271 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
b01c8b54 | 272 | EXC_HV, SOFTEN_TEST_HV) |
da2bc464 | 273 | do_kvm_H0x500: |
b01c8b54 | 274 | KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x502) |
de56a948 | 275 | FTR_SECTION_ELSE |
da2bc464 | 276 | _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, |
31a40e2b | 277 | EXC_STD, SOFTEN_TEST_PR) |
da2bc464 | 278 | do_kvm_0x500: |
de56a948 | 279 | KVM_HANDLER(PACA_EXGEN, EXC_STD, 0x500) |
969391c5 | 280 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206) |
da2bc464 ME |
281 | EXC_REAL_END(hardware_interrupt, 0x500, 0x600) |
282 | ||
283 | EXC_REAL(alignment, 0x600, 0x700) | |
284 | ||
285 | TRAMP_KVM(PACA_EXGEN, 0x600) | |
286 | ||
287 | EXC_REAL(program_check, 0x700, 0x800) | |
a5d4f3ad | 288 | |
da2bc464 | 289 | TRAMP_KVM(PACA_EXGEN, 0x700) |
b01c8b54 | 290 | |
da2bc464 | 291 | EXC_REAL(fp_unavailable, 0x800, 0x900) |
b01c8b54 | 292 | |
da2bc464 | 293 | TRAMP_KVM(PACA_EXGEN, 0x800) |
a5d4f3ad | 294 | |
da2bc464 | 295 | EXC_REAL_MASKABLE(decrementer, 0x900, 0x980) |
a485c709 | 296 | |
da2bc464 | 297 | EXC_REAL_HV(hdecrementer, 0x980, 0xa00) |
a5d4f3ad | 298 | |
da2bc464 | 299 | EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0xb00) |
b01c8b54 | 300 | |
da2bc464 | 301 | TRAMP_KVM(PACA_EXGEN, 0xa00) |
0ebc4cda | 302 | |
da2bc464 ME |
303 | EXC_REAL(trap_0b, 0xb00, 0xc00) |
304 | ||
305 | TRAMP_KVM(PACA_EXGEN, 0xb00) | |
306 | ||
307 | EXC_REAL_BEGIN(system_call, 0xc00, 0xd00) | |
8b91a255 SW |
308 | /* |
309 | * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems | |
310 | * that support it) before changing to HMT_MEDIUM. That allows the KVM | |
311 | * code to save that value into the guest state (it is the guest's PPR | |
312 | * value). Otherwise just change to HMT_MEDIUM as userspace has | |
313 | * already saved the PPR. | |
314 | */ | |
b01c8b54 PM |
315 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
316 | SET_SCRATCH0(r13) | |
317 | GET_PACA(r13) | |
318 | std r9,PACA_EXGEN+EX_R9(r13) | |
8b91a255 SW |
319 | OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); |
320 | HMT_MEDIUM; | |
b01c8b54 | 321 | std r10,PACA_EXGEN+EX_R10(r13) |
8b91a255 | 322 | OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); |
b01c8b54 | 323 | mfcr r9 |
da2bc464 | 324 | KVMTEST_PR(0xc00) |
b01c8b54 | 325 | GET_SCRATCH0(r13) |
8b91a255 SW |
326 | #else |
327 | HMT_MEDIUM; | |
b01c8b54 | 328 | #endif |
742415d6 MN |
329 | SYSCALL_PSERIES_1 |
330 | SYSCALL_PSERIES_2_RFID | |
331 | SYSCALL_PSERIES_3 | |
da2bc464 ME |
332 | EXC_REAL_END(system_call, 0xc00, 0xd00) |
333 | ||
334 | TRAMP_KVM(PACA_EXGEN, 0xc00) | |
335 | ||
336 | EXC_REAL(single_step, 0xd00, 0xe00) | |
337 | ||
338 | TRAMP_KVM(PACA_EXGEN, 0xd00) | |
b01c8b54 | 339 | |
b3e6b5df BH |
340 | |
341 | /* At 0xe??? we have a bunch of hypervisor exceptions, we branch | |
342 | * out of line to handle them | |
343 | */ | |
da2bc464 | 344 | __EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0xe20) |
1707dd16 | 345 | |
da2bc464 | 346 | __EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0xe40) |
1707dd16 | 347 | |
da2bc464 | 348 | __EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0xe60) |
1707dd16 | 349 | |
da2bc464 | 350 | __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0xe80, hmi_exception_early) |
1707dd16 | 351 | |
da2bc464 | 352 | __EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0xea0) |
0ebc4cda | 353 | |
da2bc464 | 354 | __EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0xec0) |
9baaef0a | 355 | |
da2bc464 | 356 | EXC_REAL_NONE(0xec0, 0xf00) |
0ebc4cda | 357 | |
da2bc464 | 358 | __EXC_REAL_OOL(performance_monitor, 0xf00, 0xf20) |
0ebc4cda | 359 | |
da2bc464 | 360 | __EXC_REAL_OOL(altivec_unavailable, 0xf20, 0xf40) |
0ebc4cda | 361 | |
da2bc464 ME |
362 | __EXC_REAL_OOL(vsx_unavailable, 0xf40, 0xf60) |
363 | ||
364 | __EXC_REAL_OOL(facility_unavailable, 0xf60, 0xf80) | |
365 | ||
366 | __EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0xfa0) | |
367 | ||
368 | EXC_REAL_NONE(0xfa0, 0x1200) | |
d0c0c9a1 | 369 | |
0ebc4cda | 370 | #ifdef CONFIG_CBE_RAS |
da2bc464 ME |
371 | EXC_REAL_HV(cbe_system_error, 0x1200, 0x1300) |
372 | ||
373 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200) | |
374 | ||
375 | #else /* CONFIG_CBE_RAS */ | |
376 | EXC_REAL_NONE(0x1200, 0x1300) | |
377 | #endif | |
b01c8b54 | 378 | |
da2bc464 | 379 | EXC_REAL(instruction_breakpoint, 0x1300, 0x1400) |
b01c8b54 | 380 | |
da2bc464 ME |
381 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300) |
382 | ||
383 | EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x1600) | |
b92a66a6 | 384 | mtspr SPRN_SPRG_HSCRATCH0,r13 |
1707dd16 | 385 | EXCEPTION_PROLOG_0(PACA_EXGEN) |
630573c1 | 386 | EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500) |
b92a66a6 MN |
387 | |
388 | #ifdef CONFIG_PPC_DENORMALISATION | |
389 | mfspr r10,SPRN_HSRR1 | |
390 | mfspr r11,SPRN_HSRR0 /* save HSRR0 */ | |
391 | andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */ | |
392 | addi r11,r11,-4 /* HSRR0 is next instruction */ | |
393 | bne+ denorm_assist | |
394 | #endif | |
395 | ||
da2bc464 | 396 | KVMTEST_PR(0x1500) |
b92a66a6 | 397 | EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV) |
da2bc464 ME |
398 | EXC_REAL_END(denorm_exception_hv, 0x1500, 0x1600) |
399 | ||
400 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500) | |
b92a66a6 | 401 | |
0ebc4cda | 402 | #ifdef CONFIG_CBE_RAS |
da2bc464 | 403 | EXC_REAL_HV(cbe_maintenance, 0x1600, 0x1700) |
b01c8b54 | 404 | |
da2bc464 ME |
405 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600) |
406 | ||
407 | #else /* CONFIG_CBE_RAS */ | |
408 | EXC_REAL_NONE(0x1600, 0x1700) | |
409 | #endif | |
410 | ||
411 | EXC_REAL(altivec_assist, 0x1700, 0x1800) | |
412 | ||
413 | TRAMP_KVM(PACA_EXGEN, 0x1700) | |
b01c8b54 | 414 | |
0ebc4cda | 415 | #ifdef CONFIG_CBE_RAS |
da2bc464 ME |
416 | EXC_REAL_HV(cbe_thermal, 0x1800, 0x1900) |
417 | ||
418 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800) | |
419 | ||
420 | #else /* CONFIG_CBE_RAS */ | |
421 | EXC_REAL_NONE(0x1800, 0x1900) | |
da2bc464 | 422 | #endif |
0ebc4cda | 423 | |
0ebc4cda | 424 | |
b3e6b5df BH |
425 | /*** Out of line interrupts support ***/ |
426 | ||
b01c8b54 | 427 | /* moved from 0x200 */ |
da2bc464 | 428 | TRAMP_REAL_BEGIN(machine_check_powernv_early) |
1e9b4507 MS |
429 | BEGIN_FTR_SECTION |
430 | EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200) | |
431 | /* | |
432 | * Register contents: | |
433 | * R13 = PACA | |
434 | * R9 = CR | |
435 | * Original R9 to R13 is saved on PACA_EXMC | |
436 | * | |
e75ad93a MS |
437 | * Switch to mc_emergency stack and handle re-entrancy (we limit |
438 | * the nested MCE upto level 4 to avoid stack overflow). | |
439 | * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1 | |
1e9b4507 MS |
440 | * |
441 | * We use paca->in_mce to check whether this is the first entry or | |
442 | * nested machine check. We increment paca->in_mce to track nested | |
443 | * machine checks. | |
444 | * | |
445 | * If this is the first entry then set stack pointer to | |
446 | * paca->mc_emergency_sp, otherwise r1 is already pointing to | |
447 | * stack frame on mc_emergency stack. | |
448 | * | |
449 | * NOTE: We are here with MSR_ME=0 (off), which means we risk a | |
450 | * checkstop if we get another machine check exception before we do | |
451 | * rfid with MSR_ME=1. | |
452 | */ | |
453 | mr r11,r1 /* Save r1 */ | |
454 | lhz r10,PACA_IN_MCE(r13) | |
455 | cmpwi r10,0 /* Are we in nested machine check */ | |
456 | bne 0f /* Yes, we are. */ | |
457 | /* First machine check entry */ | |
458 | ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */ | |
459 | 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
460 | addi r10,r10,1 /* increment paca->in_mce */ | |
461 | sth r10,PACA_IN_MCE(r13) | |
e75ad93a MS |
462 | /* Limit nested MCE to level 4 to avoid stack overflow */ |
463 | cmpwi r10,4 | |
464 | bgt 2f /* Check if we hit limit of 4 */ | |
1e9b4507 MS |
465 | std r11,GPR1(r1) /* Save r1 on the stack. */ |
466 | std r11,0(r1) /* make stack chain pointer */ | |
467 | mfspr r11,SPRN_SRR0 /* Save SRR0 */ | |
468 | std r11,_NIP(r1) | |
469 | mfspr r11,SPRN_SRR1 /* Save SRR1 */ | |
470 | std r11,_MSR(r1) | |
471 | mfspr r11,SPRN_DAR /* Save DAR */ | |
472 | std r11,_DAR(r1) | |
473 | mfspr r11,SPRN_DSISR /* Save DSISR */ | |
474 | std r11,_DSISR(r1) | |
475 | std r9,_CCR(r1) /* Save CR in stackframe */ | |
476 | /* Save r9 through r13 from EXMC save area to stack frame. */ | |
477 | EXCEPTION_PROLOG_COMMON_2(PACA_EXMC) | |
478 | mfmsr r11 /* get MSR value */ | |
479 | ori r11,r11,MSR_ME /* turn on ME bit */ | |
480 | ori r11,r11,MSR_RI /* turn on RI bit */ | |
1e9b4507 | 481 | LOAD_HANDLER(r12, machine_check_handle_early) |
e75ad93a | 482 | 1: mtspr SPRN_SRR0,r12 |
1e9b4507 MS |
483 | mtspr SPRN_SRR1,r11 |
484 | rfid | |
485 | b . /* prevent speculative execution */ | |
e75ad93a MS |
486 | 2: |
487 | /* Stack overflow. Stay on emergency stack and panic. | |
488 | * Keep the ME bit off while panic-ing, so that if we hit | |
489 | * another machine check we checkstop. | |
490 | */ | |
491 | addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */ | |
492 | ld r11,PACAKMSR(r13) | |
e75ad93a MS |
493 | LOAD_HANDLER(r12, unrecover_mce) |
494 | li r10,MSR_ME | |
495 | andc r11,r11,r10 /* Turn off MSR_ME */ | |
496 | b 1b | |
497 | b . /* prevent speculative execution */ | |
1e9b4507 MS |
498 | END_FTR_SECTION_IFSET(CPU_FTR_HVMODE) |
499 | ||
da2bc464 | 500 | TRAMP_REAL_BEGIN(machine_check_pSeries) |
b01c8b54 PM |
501 | .globl machine_check_fwnmi |
502 | machine_check_fwnmi: | |
b01c8b54 | 503 | SET_SCRATCH0(r13) /* save r13 */ |
1707dd16 PM |
504 | EXCEPTION_PROLOG_0(PACA_EXMC) |
505 | machine_check_pSeries_0: | |
da2bc464 | 506 | EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200) |
a74599a5 NP |
507 | /* |
508 | * The following is essentially EXCEPTION_PROLOG_PSERIES_1 with the | |
509 | * difference that MSR_RI is not enabled, because PACA_EXMC is being | |
510 | * used, so nested machine check corrupts it. machine_check_common | |
511 | * enables MSR_RI. | |
512 | */ | |
a74599a5 NP |
513 | ld r10,PACAKMSR(r13) |
514 | xori r10,r10,MSR_RI | |
515 | mfspr r11,SPRN_SRR0 | |
516 | LOAD_HANDLER(r12, machine_check_common) | |
517 | mtspr SPRN_SRR0,r12 | |
518 | mfspr r12,SPRN_SRR1 | |
519 | mtspr SPRN_SRR1,r10 | |
520 | rfid | |
521 | b . /* prevent speculative execution */ | |
522 | ||
da2bc464 ME |
523 | |
524 | TRAMP_KVM_SKIP(PACA_EXMC, 0x200) | |
525 | TRAMP_KVM_SKIP(PACA_EXGEN, 0x300) | |
526 | TRAMP_KVM_SKIP(PACA_EXSLB, 0x380) | |
527 | TRAMP_KVM(PACA_EXGEN, 0x400) | |
528 | TRAMP_KVM(PACA_EXSLB, 0x480) | |
529 | TRAMP_KVM(PACA_EXGEN, 0x900) | |
530 | TRAMP_KVM_HV(PACA_EXGEN, 0x980) | |
b01c8b54 | 531 | |
b92a66a6 | 532 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 | 533 | TRAMP_REAL_BEGIN(denorm_assist) |
b92a66a6 MN |
534 | BEGIN_FTR_SECTION |
535 | /* | |
536 | * To denormalise we need to move a copy of the register to itself. | |
537 | * For POWER6 do that here for all FP regs. | |
538 | */ | |
539 | mfmsr r10 | |
540 | ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1) | |
541 | xori r10,r10,(MSR_FE0|MSR_FE1) | |
542 | mtmsrd r10 | |
543 | sync | |
d7c67fb1 MN |
544 | |
545 | #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1 | |
546 | #define FMR4(n) FMR2(n) ; FMR2(n+2) | |
547 | #define FMR8(n) FMR4(n) ; FMR4(n+4) | |
548 | #define FMR16(n) FMR8(n) ; FMR8(n+8) | |
549 | #define FMR32(n) FMR16(n) ; FMR16(n+16) | |
550 | FMR32(0) | |
551 | ||
b92a66a6 MN |
552 | FTR_SECTION_ELSE |
553 | /* | |
554 | * To denormalise we need to move a copy of the register to itself. | |
555 | * For POWER7 do that here for the first 32 VSX registers only. | |
556 | */ | |
557 | mfmsr r10 | |
558 | oris r10,r10,MSR_VSX@h | |
559 | mtmsrd r10 | |
560 | sync | |
d7c67fb1 MN |
561 | |
562 | #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1) | |
563 | #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2) | |
564 | #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4) | |
565 | #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8) | |
566 | #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16) | |
567 | XVCPSGNDP32(0) | |
568 | ||
b92a66a6 | 569 | ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206) |
fb0fce3e MN |
570 | |
571 | BEGIN_FTR_SECTION | |
572 | b denorm_done | |
573 | END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S) | |
574 | /* | |
575 | * To denormalise we need to move a copy of the register to itself. | |
576 | * For POWER8 we need to do that for all 64 VSX registers | |
577 | */ | |
578 | XVCPSGNDP32(32) | |
579 | denorm_done: | |
b92a66a6 MN |
580 | mtspr SPRN_HSRR0,r11 |
581 | mtcrf 0x80,r9 | |
582 | ld r9,PACA_EXGEN+EX_R9(r13) | |
44e9309f | 583 | RESTORE_PPR_PACA(PACA_EXGEN, r10) |
630573c1 PM |
584 | BEGIN_FTR_SECTION |
585 | ld r10,PACA_EXGEN+EX_CFAR(r13) | |
586 | mtspr SPRN_CFAR,r10 | |
587 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
b92a66a6 MN |
588 | ld r10,PACA_EXGEN+EX_R10(r13) |
589 | ld r11,PACA_EXGEN+EX_R11(r13) | |
590 | ld r12,PACA_EXGEN+EX_R12(r13) | |
591 | ld r13,PACA_EXGEN+EX_R13(r13) | |
592 | HRFID | |
593 | b . | |
594 | #endif | |
595 | ||
b3e6b5df | 596 | /* moved from 0xe00 */ |
da2bc464 ME |
597 | __TRAMP_REAL_REAL_OOL_HV(h_data_storage, 0xe00) |
598 | TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00) | |
599 | ||
600 | __TRAMP_REAL_REAL_OOL_HV(h_instr_storage, 0xe20) | |
601 | TRAMP_KVM_HV(PACA_EXGEN, 0xe20) | |
602 | ||
603 | __TRAMP_REAL_REAL_OOL_HV(emulation_assist, 0xe40) | |
604 | TRAMP_KVM_HV(PACA_EXGEN, 0xe40) | |
0869b6fd | 605 | |
da2bc464 ME |
606 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60) |
607 | TRAMP_KVM_HV(PACA_EXGEN, 0xe60) | |
0ebc4cda | 608 | |
da2bc464 ME |
609 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80) |
610 | TRAMP_KVM_HV(PACA_EXGEN, 0xe80) | |
611 | ||
612 | __TRAMP_REAL_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0) | |
613 | TRAMP_KVM_HV(PACA_EXGEN, 0xea0) | |
9baaef0a | 614 | |
0ebc4cda | 615 | /* moved from 0xf00 */ |
da2bc464 ME |
616 | __TRAMP_REAL_REAL_OOL(performance_monitor, 0xf00) |
617 | TRAMP_KVM(PACA_EXGEN, 0xf00) | |
618 | ||
619 | __TRAMP_REAL_REAL_OOL(altivec_unavailable, 0xf20) | |
620 | TRAMP_KVM(PACA_EXGEN, 0xf20) | |
621 | ||
622 | __TRAMP_REAL_REAL_OOL(vsx_unavailable, 0xf40) | |
623 | TRAMP_KVM(PACA_EXGEN, 0xf40) | |
624 | ||
625 | __TRAMP_REAL_REAL_OOL(facility_unavailable, 0xf60) | |
626 | TRAMP_KVM(PACA_EXGEN, 0xf60) | |
627 | ||
628 | __TRAMP_REAL_REAL_OOL_HV(h_facility_unavailable, 0xf80) | |
629 | TRAMP_KVM_HV(PACA_EXGEN, 0xf80) | |
0ebc4cda BH |
630 | |
631 | /* | |
fe9e1d54 IM |
632 | * An interrupt came in while soft-disabled. We set paca->irq_happened, then: |
633 | * - If it was a decrementer interrupt, we bump the dec to max and and return. | |
634 | * - If it was a doorbell we return immediately since doorbells are edge | |
635 | * triggered and won't automatically refire. | |
0869b6fd MS |
636 | * - If it was a HMI we return immediately since we handled it in realmode |
637 | * and it won't refire. | |
fe9e1d54 IM |
638 | * - else we hard disable and return. |
639 | * This is called with r10 containing the value to OR to the paca field. | |
0ebc4cda | 640 | */ |
7230c564 BH |
641 | #define MASKED_INTERRUPT(_H) \ |
642 | masked_##_H##interrupt: \ | |
643 | std r11,PACA_EXGEN+EX_R11(r13); \ | |
644 | lbz r11,PACAIRQHAPPENED(r13); \ | |
645 | or r11,r11,r10; \ | |
646 | stb r11,PACAIRQHAPPENED(r13); \ | |
fe9e1d54 IM |
647 | cmpwi r10,PACA_IRQ_DEC; \ |
648 | bne 1f; \ | |
7230c564 BH |
649 | lis r10,0x7fff; \ |
650 | ori r10,r10,0xffff; \ | |
651 | mtspr SPRN_DEC,r10; \ | |
652 | b 2f; \ | |
fe9e1d54 | 653 | 1: cmpwi r10,PACA_IRQ_DBELL; \ |
0869b6fd MS |
654 | beq 2f; \ |
655 | cmpwi r10,PACA_IRQ_HMI; \ | |
fe9e1d54 IM |
656 | beq 2f; \ |
657 | mfspr r10,SPRN_##_H##SRR1; \ | |
7230c564 BH |
658 | rldicl r10,r10,48,1; /* clear MSR_EE */ \ |
659 | rotldi r10,r10,16; \ | |
660 | mtspr SPRN_##_H##SRR1,r10; \ | |
661 | 2: mtcrf 0x80,r9; \ | |
662 | ld r9,PACA_EXGEN+EX_R9(r13); \ | |
663 | ld r10,PACA_EXGEN+EX_R10(r13); \ | |
664 | ld r11,PACA_EXGEN+EX_R11(r13); \ | |
665 | GET_SCRATCH0(r13); \ | |
666 | ##_H##rfid; \ | |
0ebc4cda | 667 | b . |
57f26649 NP |
668 | |
669 | /* | |
670 | * Real mode exceptions actually use this too, but alternate | |
671 | * instruction code patches (which end up in the common .text area) | |
672 | * cannot reach these if they are put there. | |
673 | */ | |
674 | USE_FIXED_SECTION(virt_trampolines) | |
7230c564 BH |
675 | MASKED_INTERRUPT() |
676 | MASKED_INTERRUPT(H) | |
0ebc4cda | 677 | |
7230c564 BH |
678 | /* |
679 | * Called from arch_local_irq_enable when an interrupt needs | |
fe9e1d54 IM |
680 | * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate |
681 | * which kind of interrupt. MSR:EE is already off. We generate a | |
7230c564 BH |
682 | * stackframe like if a real interrupt had happened. |
683 | * | |
684 | * Note: While MSR:EE is off, we need to make sure that _MSR | |
685 | * in the generated frame has EE set to 1 or the exception | |
686 | * handler will not properly re-enable them. | |
687 | */ | |
57f26649 | 688 | USE_TEXT_SECTION() |
7230c564 BH |
689 | _GLOBAL(__replay_interrupt) |
690 | /* We are going to jump to the exception common code which | |
691 | * will retrieve various register values from the PACA which | |
692 | * we don't give a damn about, so we don't bother storing them. | |
693 | */ | |
694 | mfmsr r12 | |
695 | mflr r11 | |
696 | mfcr r9 | |
697 | ori r12,r12,MSR_EE | |
fe9e1d54 IM |
698 | cmpwi r3,0x900 |
699 | beq decrementer_common | |
700 | cmpwi r3,0x500 | |
701 | beq hardware_interrupt_common | |
702 | BEGIN_FTR_SECTION | |
703 | cmpwi r3,0xe80 | |
704 | beq h_doorbell_common | |
9baaef0a BH |
705 | cmpwi r3,0xea0 |
706 | beq h_virt_irq_common | |
fd7bacbc MS |
707 | cmpwi r3,0xe60 |
708 | beq hmi_exception_common | |
fe9e1d54 IM |
709 | FTR_SECTION_ELSE |
710 | cmpwi r3,0xa00 | |
711 | beq doorbell_super_common | |
712 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) | |
713 | blr | |
a5d4f3ad | 714 | |
4f6c11db | 715 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
da2bc464 | 716 | TRAMP_REAL_BEGIN(kvmppc_skip_interrupt) |
4f6c11db PM |
717 | /* |
718 | * Here all GPRs are unchanged from when the interrupt happened | |
719 | * except for r13, which is saved in SPRG_SCRATCH0. | |
720 | */ | |
721 | mfspr r13, SPRN_SRR0 | |
722 | addi r13, r13, 4 | |
723 | mtspr SPRN_SRR0, r13 | |
724 | GET_SCRATCH0(r13) | |
725 | rfid | |
726 | b . | |
727 | ||
da2bc464 | 728 | TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt) |
4f6c11db PM |
729 | /* |
730 | * Here all GPRs are unchanged from when the interrupt happened | |
731 | * except for r13, which is saved in SPRG_SCRATCH0. | |
732 | */ | |
733 | mfspr r13, SPRN_HSRR0 | |
734 | addi r13, r13, 4 | |
735 | mtspr SPRN_HSRR0, r13 | |
736 | GET_SCRATCH0(r13) | |
737 | hrfid | |
738 | b . | |
739 | #endif | |
740 | ||
0ebc4cda | 741 | /* |
057b6d7e HB |
742 | * Ensure that any handlers that get invoked from the exception prologs |
743 | * above are below the first 64KB (0x10000) of the kernel image because | |
744 | * the prologs assemble the addresses of these handlers using the | |
745 | * LOAD_HANDLER macro, which uses an ori instruction. | |
0ebc4cda BH |
746 | */ |
747 | ||
748 | /*** Common interrupt handlers ***/ | |
749 | ||
da2bc464 | 750 | EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ) |
da2bc464 | 751 | EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt) |
da2bc464 | 752 | EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt) |
0ebc4cda | 753 | |
1dbdafec | 754 | #ifdef CONFIG_PPC_DOORBELL |
da2bc464 | 755 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception) |
1dbdafec | 756 | #else |
da2bc464 | 757 | EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception) |
1dbdafec | 758 | #endif |
da2bc464 | 759 | EXC_COMMON(trap_0b_common, 0xb00, unknown_exception) |
da2bc464 | 760 | EXC_COMMON(single_step_common, 0xd00, single_step_exception) |
da2bc464 | 761 | EXC_COMMON(trap_0e_common, 0xe00, unknown_exception) |
da2bc464 | 762 | EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt) |
da2bc464 | 763 | EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception) |
655bb3f4 | 764 | #ifdef CONFIG_PPC_DOORBELL |
da2bc464 | 765 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception) |
655bb3f4 | 766 | #else |
da2bc464 | 767 | EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception) |
655bb3f4 | 768 | #endif |
da2bc464 | 769 | EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ) |
da2bc464 | 770 | EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception) |
da2bc464 | 771 | EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception) |
da2bc464 | 772 | EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception) |
0ebc4cda | 773 | #ifdef CONFIG_ALTIVEC |
da2bc464 | 774 | EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception) |
0ebc4cda | 775 | #else |
da2bc464 | 776 | EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception) |
0ebc4cda | 777 | #endif |
0ebc4cda | 778 | |
c1fb6816 MN |
779 | /* |
780 | * Relocation-on interrupts: A subset of the interrupts can be delivered | |
781 | * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering | |
782 | * it. Addresses are the same as the original interrupt addresses, but | |
783 | * offset by 0xc000000000004000. | |
784 | * It's impossible to receive interrupts below 0x300 via this mechanism. | |
785 | * KVM: None of these traps are from the guest ; anything that escalated | |
786 | * to HV=1 from HV=0 is delivered via real mode handlers. | |
787 | */ | |
788 | ||
789 | /* | |
790 | * This uses the standard macro, since the original 0x300 vector | |
791 | * only has extra guff for STAB-based processors -- which never | |
792 | * come here. | |
793 | */ | |
da2bc464 ME |
794 | EXC_VIRT_NONE(0x4200, 0x4300) |
795 | ||
796 | EXC_VIRT(data_access, 0x4300, 0x4380, 0x300) | |
797 | ||
798 | EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x4400) | |
c1fb6816 | 799 | SET_SCRATCH0(r13) |
1707dd16 | 800 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
801 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380) |
802 | std r3,PACA_EXSLB+EX_R3(r13) | |
803 | mfspr r3,SPRN_DAR | |
804 | mfspr r12,SPRN_SRR1 | |
f0f558b1 | 805 | crset 4*cr6+eq |
c1fb6816 | 806 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 807 | b slb_miss_realmode |
c1fb6816 MN |
808 | #else |
809 | /* | |
ad0289e4 | 810 | * We can't just use a direct branch to slb_miss_realmode |
c1fb6816 MN |
811 | * because the distance from here to there depends on where |
812 | * the kernel ends up being put. | |
813 | */ | |
814 | mfctr r11 | |
ad0289e4 | 815 | LOAD_HANDLER(r10, slb_miss_realmode) |
c1fb6816 MN |
816 | mtctr r10 |
817 | bctr | |
818 | #endif | |
da2bc464 | 819 | EXC_VIRT_END(data_access_slb, 0x4380, 0x4400) |
c1fb6816 | 820 | |
da2bc464 ME |
821 | EXC_VIRT(instruction_access, 0x4400, 0x4480, 0x400) |
822 | ||
823 | EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x4500) | |
c1fb6816 | 824 | SET_SCRATCH0(r13) |
1707dd16 | 825 | EXCEPTION_PROLOG_0(PACA_EXSLB) |
c1fb6816 MN |
826 | EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480) |
827 | std r3,PACA_EXSLB+EX_R3(r13) | |
828 | mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */ | |
829 | mfspr r12,SPRN_SRR1 | |
f0f558b1 | 830 | crclr 4*cr6+eq |
c1fb6816 | 831 | #ifndef CONFIG_RELOCATABLE |
b1576fec | 832 | b slb_miss_realmode |
c1fb6816 MN |
833 | #else |
834 | mfctr r11 | |
ad0289e4 | 835 | LOAD_HANDLER(r10, slb_miss_realmode) |
c1fb6816 MN |
836 | mtctr r10 |
837 | bctr | |
838 | #endif | |
da2bc464 | 839 | EXC_VIRT_END(instruction_access_slb, 0x4480, 0x4500) |
c1fb6816 | 840 | |
da2bc464 | 841 | EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x4600) |
c1fb6816 | 842 | .globl hardware_interrupt_relon_hv; |
c1fb6816 MN |
843 | hardware_interrupt_relon_hv: |
844 | BEGIN_FTR_SECTION | |
da2bc464 | 845 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV) |
c1fb6816 | 846 | FTR_SECTION_ELSE |
da2bc464 | 847 | _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR) |
3e96ca7f | 848 | ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE) |
da2bc464 ME |
849 | EXC_VIRT_END(hardware_interrupt, 0x4500, 0x4600) |
850 | ||
851 | EXC_VIRT(alignment, 0x4600, 0x4700, 0x600) | |
852 | EXC_VIRT(program_check, 0x4700, 0x4800, 0x700) | |
853 | EXC_VIRT(fp_unavailable, 0x4800, 0x4900, 0x800) | |
854 | EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x4980, 0x900) | |
855 | EXC_VIRT_HV(hdecrementer, 0x4980, 0x4a00, 0x980) | |
856 | EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x4b00, 0xa00) | |
857 | EXC_VIRT(trap_0b, 0x4b00, 0x4c00, 0xb00) | |
858 | ||
859 | EXC_VIRT_BEGIN(system_call, 0x4c00, 0x4d00) | |
c1fb6816 MN |
860 | HMT_MEDIUM |
861 | SYSCALL_PSERIES_1 | |
862 | SYSCALL_PSERIES_2_DIRECT | |
863 | SYSCALL_PSERIES_3 | |
da2bc464 | 864 | EXC_VIRT_END(system_call, 0x4c00, 0x4d00) |
c1fb6816 | 865 | |
da2bc464 | 866 | EXC_VIRT(single_step, 0x4d00, 0x4e00, 0xd00) |
c1fb6816 | 867 | |
da2bc464 ME |
868 | EXC_VIRT_BEGIN(unused, 0x4e00, 0x4e20) |
869 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ | |
870 | EXC_VIRT_END(unused, 0x4e00, 0x4e20) | |
c1fb6816 | 871 | |
da2bc464 ME |
872 | EXC_VIRT_BEGIN(unused, 0x4e20, 0x4e40) |
873 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ | |
874 | EXC_VIRT_END(unused, 0x4e20, 0x4e40) | |
c1fb6816 | 875 | |
da2bc464 | 876 | __EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x4e60) |
c1fb6816 | 877 | |
da2bc464 ME |
878 | EXC_VIRT_BEGIN(unused, 0x4e60, 0x4e80) |
879 | b . /* Can't happen, see v2.07 Book III-S section 6.5 */ | |
880 | EXC_VIRT_END(unused, 0x4e60, 0x4e80) | |
c1fb6816 | 881 | |
da2bc464 | 882 | __EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x4ea0) |
c1fb6816 | 883 | |
da2bc464 | 884 | __EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x4ec0) |
9baaef0a | 885 | |
da2bc464 | 886 | EXC_VIRT_NONE(0x4ec0, 0x4f00) |
c1fb6816 | 887 | |
da2bc464 | 888 | __EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x4f20) |
c1fb6816 | 889 | |
da2bc464 | 890 | __EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x4f40) |
c1fb6816 | 891 | |
da2bc464 | 892 | __EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x4f60) |
d0c0c9a1 | 893 | |
da2bc464 ME |
894 | __EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x4f80) |
895 | ||
896 | __EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x4fa0) | |
897 | ||
898 | EXC_VIRT_NONE(0x4fa0, 0x5200) | |
899 | ||
900 | EXC_VIRT_NONE(0x5200, 0x5300) | |
901 | ||
902 | EXC_VIRT(instruction_breakpoint, 0x5300, 0x5400, 0x1300) | |
b14b6260 | 903 | |
c1fb6816 | 904 | #ifdef CONFIG_PPC_DENORMALISATION |
da2bc464 ME |
905 | EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x5600) |
906 | b exc_real_0x1500_denorm_exception_hv | |
907 | EXC_VIRT_END(denorm_exception, 0x5500, 0x5600) | |
908 | #else | |
909 | EXC_VIRT_NONE(0x5500, 0x5600) | |
c1fb6816 | 910 | #endif |
c1fb6816 | 911 | |
da2bc464 ME |
912 | EXC_VIRT_NONE(0x5600, 0x5700) |
913 | ||
914 | EXC_VIRT(altivec_assist, 0x5700, 0x5800, 0x1700) | |
915 | ||
916 | EXC_VIRT_NONE(0x5800, 0x5900) | |
917 | ||
57f26649 | 918 | EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline) |
b1576fec | 919 | b __ppc64_runlatch_on |
fe1952fc | 920 | |
0ebc4cda BH |
921 | /* |
922 | * Here r13 points to the paca, r9 contains the saved CR, | |
923 | * SRR0 and SRR1 are saved in r11 and r12, | |
924 | * r9 - r13 are saved in paca->exgen. | |
925 | */ | |
da2bc464 | 926 | EXC_COMMON_BEGIN(data_access_common) |
0ebc4cda BH |
927 | mfspr r10,SPRN_DAR |
928 | std r10,PACA_EXGEN+EX_DAR(r13) | |
929 | mfspr r10,SPRN_DSISR | |
930 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
931 | EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN) | |
9daf112b | 932 | RECONCILE_IRQ_STATE(r10, r11) |
a546498f | 933 | ld r12,_MSR(r1) |
0ebc4cda BH |
934 | ld r3,PACA_EXGEN+EX_DAR(r13) |
935 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
936 | li r5,0x300 | |
caca285e AK |
937 | std r3,_DAR(r1) |
938 | std r4,_DSISR(r1) | |
939 | BEGIN_MMU_FTR_SECTION | |
b1576fec | 940 | b do_hash_page /* Try to handle as hpte fault */ |
caca285e AK |
941 | MMU_FTR_SECTION_ELSE |
942 | b handle_page_fault | |
5a25b6f5 | 943 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) |
0ebc4cda | 944 | |
da2bc464 | 945 | EXC_COMMON_BEGIN(h_data_storage_common) |
278a6cdc MN |
946 | mfspr r10,SPRN_HDAR |
947 | std r10,PACA_EXGEN+EX_DAR(r13) | |
948 | mfspr r10,SPRN_HDSISR | |
949 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
950 | EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN) | |
b1576fec | 951 | bl save_nvgprs |
9daf112b | 952 | RECONCILE_IRQ_STATE(r10, r11) |
278a6cdc | 953 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
954 | bl unknown_exception |
955 | b ret_from_except | |
b3e6b5df | 956 | |
da2bc464 | 957 | EXC_COMMON_BEGIN(instruction_access_common) |
0ebc4cda | 958 | EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN) |
9daf112b | 959 | RECONCILE_IRQ_STATE(r10, r11) |
a546498f | 960 | ld r12,_MSR(r1) |
0ebc4cda BH |
961 | ld r3,_NIP(r1) |
962 | andis. r4,r12,0x5820 | |
963 | li r5,0x400 | |
caca285e AK |
964 | std r3,_DAR(r1) |
965 | std r4,_DSISR(r1) | |
966 | BEGIN_MMU_FTR_SECTION | |
b1576fec | 967 | b do_hash_page /* Try to handle as hpte fault */ |
caca285e AK |
968 | MMU_FTR_SECTION_ELSE |
969 | b handle_page_fault | |
5a25b6f5 | 970 | ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX) |
0ebc4cda | 971 | |
da2bc464 | 972 | EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception) |
b3e6b5df | 973 | |
4e243b79 MS |
974 | /* |
975 | * Machine check is different because we use a different | |
976 | * save area: PACA_EXMC instead of PACA_EXGEN. | |
977 | */ | |
da2bc464 | 978 | EXC_COMMON_BEGIN(machine_check_common) |
4e243b79 | 979 | mfspr r10,SPRN_DAR |
3f3b5dc1 | 980 | std r10,PACA_EXMC+EX_DAR(r13) |
4e243b79 | 981 | mfspr r10,SPRN_DSISR |
3f3b5dc1 | 982 | stw r10,PACA_EXMC+EX_DSISR(r13) |
4e243b79 MS |
983 | EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC) |
984 | FINISH_NAP | |
9daf112b | 985 | RECONCILE_IRQ_STATE(r10, r11) |
3f3b5dc1 NP |
986 | ld r3,PACA_EXMC+EX_DAR(r13) |
987 | lwz r4,PACA_EXMC+EX_DSISR(r13) | |
a74599a5 NP |
988 | /* Enable MSR_RI when finished with PACA_EXMC */ |
989 | li r10,MSR_RI | |
990 | mtmsrd r10,1 | |
4e243b79 MS |
991 | std r3,_DAR(r1) |
992 | std r4,_DSISR(r1) | |
b1576fec | 993 | bl save_nvgprs |
4e243b79 | 994 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
995 | bl machine_check_exception |
996 | b ret_from_except | |
4e243b79 | 997 | |
da2bc464 | 998 | EXC_COMMON_BEGIN(alignment_common) |
0ebc4cda BH |
999 | mfspr r10,SPRN_DAR |
1000 | std r10,PACA_EXGEN+EX_DAR(r13) | |
1001 | mfspr r10,SPRN_DSISR | |
1002 | stw r10,PACA_EXGEN+EX_DSISR(r13) | |
1003 | EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN) | |
1004 | ld r3,PACA_EXGEN+EX_DAR(r13) | |
1005 | lwz r4,PACA_EXGEN+EX_DSISR(r13) | |
1006 | std r3,_DAR(r1) | |
1007 | std r4,_DSISR(r1) | |
b1576fec | 1008 | bl save_nvgprs |
9daf112b | 1009 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 1010 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1011 | bl alignment_exception |
1012 | b ret_from_except | |
0ebc4cda | 1013 | |
da2bc464 | 1014 | EXC_COMMON_BEGIN(program_check_common) |
0ebc4cda | 1015 | EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN) |
b1576fec | 1016 | bl save_nvgprs |
9daf112b | 1017 | RECONCILE_IRQ_STATE(r10, r11) |
922b9f86 | 1018 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1019 | bl program_check_exception |
1020 | b ret_from_except | |
0ebc4cda | 1021 | |
da2bc464 | 1022 | EXC_COMMON_BEGIN(fp_unavailable_common) |
0ebc4cda BH |
1023 | EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN) |
1024 | bne 1f /* if from user, just load it up */ | |
b1576fec | 1025 | bl save_nvgprs |
9daf112b | 1026 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 1027 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 1028 | bl kernel_fp_unavailable_exception |
0ebc4cda | 1029 | BUG_OPCODE |
bc2a9408 MN |
1030 | 1: |
1031 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM | |
1032 | BEGIN_FTR_SECTION | |
1033 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1034 | * transaction), go do TM stuff | |
1035 | */ | |
1036 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1037 | bne- 2f | |
1038 | END_FTR_SECTION_IFSET(CPU_FTR_TM) | |
1039 | #endif | |
b1576fec | 1040 | bl load_up_fpu |
0ebc4cda | 1041 | b fast_exception_return |
bc2a9408 MN |
1042 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1043 | 2: /* User process was in a transaction */ | |
b1576fec | 1044 | bl save_nvgprs |
9daf112b | 1045 | RECONCILE_IRQ_STATE(r10, r11) |
bc2a9408 | 1046 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1047 | bl fp_unavailable_tm |
1048 | b ret_from_except | |
bc2a9408 | 1049 | #endif |
da2bc464 | 1050 | |
da2bc464 | 1051 | EXC_COMMON_BEGIN(altivec_unavailable_common) |
0ebc4cda BH |
1052 | EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN) |
1053 | #ifdef CONFIG_ALTIVEC | |
1054 | BEGIN_FTR_SECTION | |
1055 | beq 1f | |
bc2a9408 MN |
1056 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1057 | BEGIN_FTR_SECTION_NESTED(69) | |
1058 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1059 | * transaction), go do TM stuff | |
1060 | */ | |
1061 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1062 | bne- 2f | |
1063 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1064 | #endif | |
b1576fec | 1065 | bl load_up_altivec |
0ebc4cda | 1066 | b fast_exception_return |
bc2a9408 MN |
1067 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1068 | 2: /* User process was in a transaction */ | |
b1576fec | 1069 | bl save_nvgprs |
9daf112b | 1070 | RECONCILE_IRQ_STATE(r10, r11) |
bc2a9408 | 1071 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1072 | bl altivec_unavailable_tm |
1073 | b ret_from_except | |
bc2a9408 | 1074 | #endif |
0ebc4cda BH |
1075 | 1: |
1076 | END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |
1077 | #endif | |
b1576fec | 1078 | bl save_nvgprs |
9daf112b | 1079 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 1080 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1081 | bl altivec_unavailable_exception |
1082 | b ret_from_except | |
0ebc4cda | 1083 | |
da2bc464 | 1084 | EXC_COMMON_BEGIN(vsx_unavailable_common) |
0ebc4cda BH |
1085 | EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN) |
1086 | #ifdef CONFIG_VSX | |
1087 | BEGIN_FTR_SECTION | |
7230c564 | 1088 | beq 1f |
bc2a9408 MN |
1089 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1090 | BEGIN_FTR_SECTION_NESTED(69) | |
1091 | /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in | |
1092 | * transaction), go do TM stuff | |
1093 | */ | |
1094 | rldicl. r0, r12, (64-MSR_TS_LG), (64-2) | |
1095 | bne- 2f | |
1096 | END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69) | |
1097 | #endif | |
b1576fec | 1098 | b load_up_vsx |
bc2a9408 MN |
1099 | #ifdef CONFIG_PPC_TRANSACTIONAL_MEM |
1100 | 2: /* User process was in a transaction */ | |
b1576fec | 1101 | bl save_nvgprs |
9daf112b | 1102 | RECONCILE_IRQ_STATE(r10, r11) |
bc2a9408 | 1103 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1104 | bl vsx_unavailable_tm |
1105 | b ret_from_except | |
bc2a9408 | 1106 | #endif |
0ebc4cda BH |
1107 | 1: |
1108 | END_FTR_SECTION_IFSET(CPU_FTR_VSX) | |
1109 | #endif | |
b1576fec | 1110 | bl save_nvgprs |
9daf112b | 1111 | RECONCILE_IRQ_STATE(r10, r11) |
0ebc4cda | 1112 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec AB |
1113 | bl vsx_unavailable_exception |
1114 | b ret_from_except | |
0ebc4cda | 1115 | |
61383407 | 1116 | /* Equivalents to the above handlers for relocation-on interrupt vectors */ |
da2bc464 ME |
1117 | __TRAMP_REAL_VIRT_OOL_HV(emulation_assist, 0xe40) |
1118 | __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_doorbell, 0xe80) | |
1119 | __TRAMP_REAL_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0xea0) | |
1120 | __TRAMP_REAL_VIRT_OOL(performance_monitor, 0xf00) | |
1121 | __TRAMP_REAL_VIRT_OOL(altivec_unavailable, 0xf20) | |
1122 | __TRAMP_REAL_VIRT_OOL(vsx_unavailable, 0xf40) | |
1123 | __TRAMP_REAL_VIRT_OOL(facility_unavailable, 0xf60) | |
1124 | __TRAMP_REAL_VIRT_OOL_HV(h_facility_unavailable, 0xf80) | |
61383407 | 1125 | |
57f26649 | 1126 | USE_FIXED_SECTION(virt_trampolines) |
8ed8ab40 HB |
1127 | /* |
1128 | * The __end_interrupts marker must be past the out-of-line (OOL) | |
1129 | * handlers, so that they are copied to real address 0x100 when running | |
1130 | * a relocatable kernel. This ensures they can be reached from the short | |
1131 | * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch | |
1132 | * directly, without using LOAD_HANDLER(). | |
1133 | */ | |
1134 | .align 7 | |
1135 | .globl __end_interrupts | |
1136 | __end_interrupts: | |
57f26649 | 1137 | DEFINE_FIXED_SYMBOL(__end_interrupts) |
61383407 | 1138 | |
da2bc464 | 1139 | EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception) |
da2bc464 | 1140 | EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception) |
b88d4bce BH |
1141 | |
1142 | #ifdef CONFIG_CBE_RAS | |
da2bc464 | 1143 | EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception) |
da2bc464 | 1144 | EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception) |
da2bc464 | 1145 | EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception) |
b88d4bce BH |
1146 | #endif /* CONFIG_CBE_RAS */ |
1147 | ||
da2bc464 | 1148 | |
57f26649 | 1149 | TRAMP_REAL_BEGIN(hmi_exception_early) |
da2bc464 | 1150 | EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60) |
11d54904 GR |
1151 | mr r10,r1 /* Save r1 */ |
1152 | ld r1,PACAEMERGSP(r13) /* Use emergency stack */ | |
1153 | subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */ | |
1154 | std r9,_CCR(r1) /* save CR in stackframe */ | |
1155 | mfspr r11,SPRN_HSRR0 /* Save HSRR0 */ | |
1156 | std r11,_NIP(r1) /* save HSRR0 in stackframe */ | |
1157 | mfspr r12,SPRN_HSRR1 /* Save SRR1 */ | |
1158 | std r12,_MSR(r1) /* save SRR1 in stackframe */ | |
1159 | std r10,0(r1) /* make stack chain pointer */ | |
1160 | std r0,GPR0(r1) /* save r0 in stackframe */ | |
1161 | std r10,GPR1(r1) /* save r1 in stackframe */ | |
1162 | EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN) | |
1163 | EXCEPTION_PROLOG_COMMON_3(0xe60) | |
1164 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1165 | bl hmi_exception_realmode | |
1166 | /* Windup the stack. */ | |
11d54904 GR |
1167 | /* Move original HSRR0 and HSRR1 into the respective regs */ |
1168 | ld r9,_MSR(r1) | |
1169 | mtspr SPRN_HSRR1,r9 | |
1170 | ld r3,_NIP(r1) | |
1171 | mtspr SPRN_HSRR0,r3 | |
1172 | ld r9,_CTR(r1) | |
1173 | mtctr r9 | |
1174 | ld r9,_XER(r1) | |
1175 | mtxer r9 | |
1176 | ld r9,_LINK(r1) | |
1177 | mtlr r9 | |
1178 | REST_GPR(0, r1) | |
1179 | REST_8GPRS(2, r1) | |
1180 | REST_GPR(10, r1) | |
1181 | ld r11,_CCR(r1) | |
1182 | mtcr r11 | |
1183 | REST_GPR(11, r1) | |
1184 | REST_2GPRS(12, r1) | |
1185 | /* restore original r1. */ | |
1186 | ld r1,GPR1(r1) | |
1187 | ||
1188 | /* | |
1189 | * Go to virtual mode and pull the HMI event information from | |
1190 | * firmware. | |
1191 | */ | |
1192 | .globl hmi_exception_after_realmode | |
1193 | hmi_exception_after_realmode: | |
1194 | SET_SCRATCH0(r13) | |
1195 | EXCEPTION_PROLOG_0(PACA_EXGEN) | |
da2bc464 | 1196 | b tramp_real_hmi_exception |
11d54904 | 1197 | |
61383407 | 1198 | |
4e243b79 MS |
1199 | #define MACHINE_CHECK_HANDLER_WINDUP \ |
1200 | /* Clear MSR_RI before setting SRR0 and SRR1. */\ | |
1201 | li r0,MSR_RI; \ | |
1202 | mfmsr r9; /* get MSR value */ \ | |
1203 | andc r9,r9,r0; \ | |
1204 | mtmsrd r9,1; /* Clear MSR_RI */ \ | |
1205 | /* Move original SRR0 and SRR1 into the respective regs */ \ | |
1206 | ld r9,_MSR(r1); \ | |
1207 | mtspr SPRN_SRR1,r9; \ | |
1208 | ld r3,_NIP(r1); \ | |
1209 | mtspr SPRN_SRR0,r3; \ | |
1210 | ld r9,_CTR(r1); \ | |
1211 | mtctr r9; \ | |
1212 | ld r9,_XER(r1); \ | |
1213 | mtxer r9; \ | |
1214 | ld r9,_LINK(r1); \ | |
1215 | mtlr r9; \ | |
1216 | REST_GPR(0, r1); \ | |
1217 | REST_8GPRS(2, r1); \ | |
1218 | REST_GPR(10, r1); \ | |
1219 | ld r11,_CCR(r1); \ | |
1220 | mtcr r11; \ | |
1221 | /* Decrement paca->in_mce. */ \ | |
1222 | lhz r12,PACA_IN_MCE(r13); \ | |
1223 | subi r12,r12,1; \ | |
1224 | sth r12,PACA_IN_MCE(r13); \ | |
1225 | REST_GPR(11, r1); \ | |
1226 | REST_2GPRS(12, r1); \ | |
1227 | /* restore original r1. */ \ | |
1228 | ld r1,GPR1(r1) | |
1229 | ||
1230 | /* | |
1231 | * Handle machine check early in real mode. We come here with | |
1232 | * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack. | |
1233 | */ | |
da2bc464 | 1234 | EXC_COMMON_BEGIN(machine_check_handle_early) |
4e243b79 MS |
1235 | std r0,GPR0(r1) /* Save r0 */ |
1236 | EXCEPTION_PROLOG_COMMON_3(0x200) | |
b1576fec | 1237 | bl save_nvgprs |
4e243b79 | 1238 | addi r3,r1,STACK_FRAME_OVERHEAD |
b1576fec | 1239 | bl machine_check_early |
2749a2f2 | 1240 | std r3,RESULT(r1) /* Save result */ |
4e243b79 MS |
1241 | ld r12,_MSR(r1) |
1242 | #ifdef CONFIG_PPC_P7_NAP | |
1243 | /* | |
1244 | * Check if thread was in power saving mode. We come here when any | |
1245 | * of the following is true: | |
1246 | * a. thread wasn't in power saving mode | |
bc14c491 MS |
1247 | * b. thread was in power saving mode with no state loss, |
1248 | * supervisor state loss or hypervisor state loss. | |
4e243b79 | 1249 | * |
bc14c491 | 1250 | * Go back to nap/sleep/winkle mode again if (b) is true. |
4e243b79 MS |
1251 | */ |
1252 | rlwinm. r11,r12,47-31,30,31 /* Was it in power saving mode? */ | |
1253 | beq 4f /* No, it wasn;t */ | |
1254 | /* Thread was in power saving mode. Go back to nap again. */ | |
1255 | cmpwi r11,2 | |
bc14c491 MS |
1256 | blt 3f |
1257 | /* Supervisor/Hypervisor state loss */ | |
4e243b79 MS |
1258 | li r0,1 |
1259 | stb r0,PACA_NAPSTATELOST(r13) | |
b1576fec | 1260 | 3: bl machine_check_queue_event |
4e243b79 MS |
1261 | MACHINE_CHECK_HANDLER_WINDUP |
1262 | GET_PACA(r13) | |
1263 | ld r1,PACAR1(r13) | |
bc14c491 MS |
1264 | /* |
1265 | * Check what idle state this CPU was in and go back to same mode | |
1266 | * again. | |
1267 | */ | |
1268 | lbz r3,PACA_THREAD_IDLE_STATE(r13) | |
1269 | cmpwi r3,PNV_THREAD_NAP | |
1270 | bgt 10f | |
1271 | IDLE_STATE_ENTER_SEQ(PPC_NAP) | |
1272 | /* No return */ | |
1273 | 10: | |
1274 | cmpwi r3,PNV_THREAD_SLEEP | |
1275 | bgt 2f | |
1276 | IDLE_STATE_ENTER_SEQ(PPC_SLEEP) | |
1277 | /* No return */ | |
1278 | ||
1279 | 2: | |
1280 | /* | |
1281 | * Go back to winkle. Please note that this thread was woken up in | |
1282 | * machine check from winkle and have not restored the per-subcore | |
1283 | * state. Hence before going back to winkle, set last bit of HSPGR0 | |
1284 | * to 1. This will make sure that if this thread gets woken up | |
1285 | * again at reset vector 0x100 then it will get chance to restore | |
1286 | * the subcore state. | |
1287 | */ | |
1288 | ori r13,r13,1 | |
1289 | SET_PACA(r13) | |
1290 | IDLE_STATE_ENTER_SEQ(PPC_WINKLE) | |
1291 | /* No return */ | |
4e243b79 MS |
1292 | 4: |
1293 | #endif | |
1294 | /* | |
1295 | * Check if we are coming from hypervisor userspace. If yes then we | |
1296 | * continue in host kernel in V mode to deliver the MC event. | |
1297 | */ | |
1298 | rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */ | |
1299 | beq 5f | |
1300 | andi. r11,r12,MSR_PR /* See if coming from user. */ | |
1301 | bne 9f /* continue in V mode if we are. */ | |
1302 | ||
1303 | 5: | |
44d5f6f5 | 1304 | #ifdef CONFIG_KVM_BOOK3S_64_HANDLER |
4e243b79 MS |
1305 | /* |
1306 | * We are coming from kernel context. Check if we are coming from | |
1307 | * guest. if yes, then we can continue. We will fall through | |
1308 | * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest. | |
1309 | */ | |
1310 | lbz r11,HSTATE_IN_GUEST(r13) | |
1311 | cmpwi r11,0 /* Check if coming from guest */ | |
1312 | bne 9f /* continue if we are. */ | |
1313 | #endif | |
1314 | /* | |
1315 | * At this point we are not sure about what context we come from. | |
1316 | * Queue up the MCE event and return from the interrupt. | |
1317 | * But before that, check if this is an un-recoverable exception. | |
1318 | * If yes, then stay on emergency stack and panic. | |
1319 | */ | |
1320 | andi. r11,r12,MSR_RI | |
1321 | bne 2f | |
2749a2f2 | 1322 | 1: mfspr r11,SPRN_SRR0 |
2749a2f2 MS |
1323 | LOAD_HANDLER(r10,unrecover_mce) |
1324 | mtspr SPRN_SRR0,r10 | |
1325 | ld r10,PACAKMSR(r13) | |
1326 | /* | |
1327 | * We are going down. But there are chances that we might get hit by | |
1328 | * another MCE during panic path and we may run into unstable state | |
1329 | * with no way out. Hence, turn ME bit off while going down, so that | |
1330 | * when another MCE is hit during panic path, system will checkstop | |
1331 | * and hypervisor will get restarted cleanly by SP. | |
1332 | */ | |
1333 | li r3,MSR_ME | |
1334 | andc r10,r10,r3 /* Turn off MSR_ME */ | |
1335 | mtspr SPRN_SRR1,r10 | |
1336 | rfid | |
1337 | b . | |
4e243b79 | 1338 | 2: |
2749a2f2 MS |
1339 | /* |
1340 | * Check if we have successfully handled/recovered from error, if not | |
1341 | * then stay on emergency stack and panic. | |
1342 | */ | |
1343 | ld r3,RESULT(r1) /* Load result */ | |
1344 | cmpdi r3,0 /* see if we handled MCE successfully */ | |
1345 | ||
1346 | beq 1b /* if !handled then panic */ | |
4e243b79 MS |
1347 | /* |
1348 | * Return from MC interrupt. | |
1349 | * Queue up the MCE event so that we can log it later, while | |
1350 | * returning from kernel or opal call. | |
1351 | */ | |
b1576fec | 1352 | bl machine_check_queue_event |
4e243b79 MS |
1353 | MACHINE_CHECK_HANDLER_WINDUP |
1354 | rfid | |
1355 | 9: | |
1356 | /* Deliver the machine check to host kernel in V mode. */ | |
1357 | MACHINE_CHECK_HANDLER_WINDUP | |
1358 | b machine_check_pSeries | |
1359 | ||
da2bc464 | 1360 | EXC_COMMON_BEGIN(unrecover_mce) |
2749a2f2 MS |
1361 | /* Invoke machine_check_exception to print MCE event and panic. */ |
1362 | addi r3,r1,STACK_FRAME_OVERHEAD | |
ad718622 | 1363 | bl machine_check_exception |
2749a2f2 MS |
1364 | /* |
1365 | * We will not reach here. Even if we did, there is no way out. Call | |
1366 | * unrecoverable_exception and die. | |
1367 | */ | |
1368 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
ad718622 | 1369 | bl unrecoverable_exception |
2749a2f2 | 1370 | b 1b |
da2bc464 | 1371 | |
087aa036 CG |
1372 | /* |
1373 | * r13 points to the PACA, r9 contains the saved CR, | |
1374 | * r12 contain the saved SRR1, SRR0 is still ready for return | |
1375 | * r3 has the faulting address | |
1376 | * r9 - r13 are saved in paca->exslb. | |
1377 | * r3 is saved in paca->slb_r3 | |
f0f558b1 | 1378 | * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss |
087aa036 CG |
1379 | * We assume we aren't going to take any exceptions during this procedure. |
1380 | */ | |
da2bc464 | 1381 | EXC_COMMON_BEGIN(slb_miss_realmode) |
087aa036 CG |
1382 | mflr r10 |
1383 | #ifdef CONFIG_RELOCATABLE | |
1384 | mtctr r11 | |
1385 | #endif | |
1386 | ||
1387 | stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */ | |
1388 | std r10,PACA_EXSLB+EX_LR(r13) /* save LR */ | |
f0f558b1 | 1389 | std r3,PACA_EXSLB+EX_DAR(r13) |
087aa036 | 1390 | |
f0f558b1 | 1391 | crset 4*cr0+eq |
caca285e AK |
1392 | #ifdef CONFIG_PPC_STD_MMU_64 |
1393 | BEGIN_MMU_FTR_SECTION | |
b1576fec | 1394 | bl slb_allocate_realmode |
5a25b6f5 | 1395 | END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX) |
caca285e | 1396 | #endif |
087aa036 CG |
1397 | |
1398 | ld r10,PACA_EXSLB+EX_LR(r13) | |
1399 | ld r3,PACA_EXSLB+EX_R3(r13) | |
1400 | lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */ | |
087aa036 | 1401 | mtlr r10 |
f0f558b1 PM |
1402 | |
1403 | beq 8f /* if bad address, make full stack frame */ | |
1404 | ||
087aa036 CG |
1405 | andi. r10,r12,MSR_RI /* check for unrecoverable exception */ |
1406 | beq- 2f | |
f0f558b1 PM |
1407 | |
1408 | /* All done -- return from exception. */ | |
087aa036 CG |
1409 | |
1410 | .machine push | |
1411 | .machine "power4" | |
1412 | mtcrf 0x80,r9 | |
f0f558b1 | 1413 | mtcrf 0x02,r9 /* I/D indication is in cr6 */ |
087aa036 CG |
1414 | mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */ |
1415 | .machine pop | |
1416 | ||
1417 | RESTORE_PPR_PACA(PACA_EXSLB, r9) | |
1418 | ld r9,PACA_EXSLB+EX_R9(r13) | |
1419 | ld r10,PACA_EXSLB+EX_R10(r13) | |
1420 | ld r11,PACA_EXSLB+EX_R11(r13) | |
1421 | ld r12,PACA_EXSLB+EX_R12(r13) | |
1422 | ld r13,PACA_EXSLB+EX_R13(r13) | |
1423 | rfid | |
1424 | b . /* prevent speculative execution */ | |
1425 | ||
1426 | 2: mfspr r11,SPRN_SRR0 | |
087aa036 CG |
1427 | LOAD_HANDLER(r10,unrecov_slb) |
1428 | mtspr SPRN_SRR0,r10 | |
1429 | ld r10,PACAKMSR(r13) | |
1430 | mtspr SPRN_SRR1,r10 | |
1431 | rfid | |
1432 | b . | |
1433 | ||
f0f558b1 | 1434 | 8: mfspr r11,SPRN_SRR0 |
f0f558b1 PM |
1435 | LOAD_HANDLER(r10,bad_addr_slb) |
1436 | mtspr SPRN_SRR0,r10 | |
1437 | ld r10,PACAKMSR(r13) | |
1438 | mtspr SPRN_SRR1,r10 | |
1439 | rfid | |
1440 | b . | |
1441 | ||
da2bc464 ME |
1442 | EXC_COMMON_BEGIN(unrecov_slb) |
1443 | EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB) | |
1444 | RECONCILE_IRQ_STATE(r10, r11) | |
1445 | bl save_nvgprs | |
1446 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1447 | bl unrecoverable_exception | |
1448 | b 1b | |
1449 | ||
1450 | ||
1451 | EXC_COMMON_BEGIN(bad_addr_slb) | |
f0f558b1 PM |
1452 | EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB) |
1453 | RECONCILE_IRQ_STATE(r10, r11) | |
1454 | ld r3, PACA_EXSLB+EX_DAR(r13) | |
1455 | std r3, _DAR(r1) | |
1456 | beq cr6, 2f | |
1457 | li r10, 0x480 /* fix trap number for I-SLB miss */ | |
1458 | std r10, _TRAP(r1) | |
1459 | 2: bl save_nvgprs | |
1460 | addi r3, r1, STACK_FRAME_OVERHEAD | |
1461 | bl slb_miss_bad_addr | |
1462 | b ret_from_except | |
087aa036 CG |
1463 | |
1464 | #ifdef CONFIG_PPC_970_NAP | |
da2bc464 | 1465 | TRAMP_REAL_BEGIN(power4_fixup_nap) |
087aa036 CG |
1466 | andc r9,r9,r10 |
1467 | std r9,TI_LOCAL_FLAGS(r11) | |
1468 | ld r10,_LINK(r1) /* make idle task do the */ | |
1469 | std r10,_NIP(r1) /* equivalent of a blr */ | |
1470 | blr | |
1471 | #endif | |
1472 | ||
57f26649 NP |
1473 | CLOSE_FIXED_SECTION(real_vectors); |
1474 | CLOSE_FIXED_SECTION(real_trampolines); | |
1475 | CLOSE_FIXED_SECTION(virt_vectors); | |
1476 | CLOSE_FIXED_SECTION(virt_trampolines); | |
1477 | ||
1478 | USE_TEXT_SECTION() | |
1479 | ||
0ebc4cda BH |
1480 | /* |
1481 | * Hash table stuff | |
1482 | */ | |
1483 | .align 7 | |
6a3bab90 | 1484 | do_hash_page: |
caca285e | 1485 | #ifdef CONFIG_PPC_STD_MMU_64 |
9c7cc234 | 1486 | andis. r0,r4,0xa410 /* weird error? */ |
0ebc4cda | 1487 | bne- handle_page_fault /* if not, try to insert a HPTE */ |
9c7cc234 P |
1488 | andis. r0,r4,DSISR_DABRMATCH@h |
1489 | bne- handle_dabr_fault | |
9778b696 | 1490 | CURRENT_THREAD_INFO(r11, r1) |
9c1e1052 PM |
1491 | lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */ |
1492 | andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */ | |
1493 | bne 77f /* then don't call hash_page now */ | |
0ebc4cda BH |
1494 | |
1495 | /* | |
1496 | * r3 contains the faulting address | |
106713a1 | 1497 | * r4 msr |
0ebc4cda | 1498 | * r5 contains the trap number |
aefa5688 | 1499 | * r6 contains dsisr |
0ebc4cda | 1500 | * |
7230c564 | 1501 | * at return r3 = 0 for success, 1 for page fault, negative for error |
0ebc4cda | 1502 | */ |
106713a1 | 1503 | mr r4,r12 |
aefa5688 | 1504 | ld r6,_DSISR(r1) |
106713a1 AK |
1505 | bl __hash_page /* build HPTE if possible */ |
1506 | cmpdi r3,0 /* see if __hash_page succeeded */ | |
0ebc4cda | 1507 | |
7230c564 | 1508 | /* Success */ |
0ebc4cda | 1509 | beq fast_exc_return_irq /* Return from exception on success */ |
0ebc4cda | 1510 | |
7230c564 BH |
1511 | /* Error */ |
1512 | blt- 13f | |
caca285e | 1513 | #endif /* CONFIG_PPC_STD_MMU_64 */ |
9c7cc234 | 1514 | |
0ebc4cda BH |
1515 | /* Here we have a page fault that hash_page can't handle. */ |
1516 | handle_page_fault: | |
0ebc4cda BH |
1517 | 11: ld r4,_DAR(r1) |
1518 | ld r5,_DSISR(r1) | |
1519 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec | 1520 | bl do_page_fault |
0ebc4cda | 1521 | cmpdi r3,0 |
a546498f | 1522 | beq+ 12f |
b1576fec | 1523 | bl save_nvgprs |
0ebc4cda BH |
1524 | mr r5,r3 |
1525 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1526 | lwz r4,_DAR(r1) | |
b1576fec AB |
1527 | bl bad_page_fault |
1528 | b ret_from_except | |
0ebc4cda | 1529 | |
a546498f BH |
1530 | /* We have a data breakpoint exception - handle it */ |
1531 | handle_dabr_fault: | |
b1576fec | 1532 | bl save_nvgprs |
a546498f BH |
1533 | ld r4,_DAR(r1) |
1534 | ld r5,_DSISR(r1) | |
1535 | addi r3,r1,STACK_FRAME_OVERHEAD | |
b1576fec AB |
1536 | bl do_break |
1537 | 12: b ret_from_except_lite | |
a546498f | 1538 | |
0ebc4cda | 1539 | |
caca285e | 1540 | #ifdef CONFIG_PPC_STD_MMU_64 |
0ebc4cda BH |
1541 | /* We have a page fault that hash_page could handle but HV refused |
1542 | * the PTE insertion | |
1543 | */ | |
b1576fec | 1544 | 13: bl save_nvgprs |
0ebc4cda BH |
1545 | mr r5,r3 |
1546 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1547 | ld r4,_DAR(r1) | |
b1576fec AB |
1548 | bl low_hash_fault |
1549 | b ret_from_except | |
caca285e | 1550 | #endif |
0ebc4cda | 1551 | |
9c1e1052 PM |
1552 | /* |
1553 | * We come here as a result of a DSI at a point where we don't want | |
1554 | * to call hash_page, such as when we are accessing memory (possibly | |
1555 | * user memory) inside a PMU interrupt that occurred while interrupts | |
1556 | * were soft-disabled. We want to invoke the exception handler for | |
1557 | * the access, or panic if there isn't a handler. | |
1558 | */ | |
b1576fec | 1559 | 77: bl save_nvgprs |
9c1e1052 PM |
1560 | mr r4,r3 |
1561 | addi r3,r1,STACK_FRAME_OVERHEAD | |
1562 | li r5,SIGSEGV | |
b1576fec AB |
1563 | bl bad_page_fault |
1564 | b ret_from_except | |
4e2bf01b ME |
1565 | |
1566 | /* | |
1567 | * Here we have detected that the kernel stack pointer is bad. | |
1568 | * R9 contains the saved CR, r13 points to the paca, | |
1569 | * r10 contains the (bad) kernel stack pointer, | |
1570 | * r11 and r12 contain the saved SRR0 and SRR1. | |
1571 | * We switch to using an emergency stack, save the registers there, | |
1572 | * and call kernel_bad_stack(), which panics. | |
1573 | */ | |
1574 | bad_stack: | |
1575 | ld r1,PACAEMERGSP(r13) | |
1576 | subi r1,r1,64+INT_FRAME_SIZE | |
1577 | std r9,_CCR(r1) | |
1578 | std r10,GPR1(r1) | |
1579 | std r11,_NIP(r1) | |
1580 | std r12,_MSR(r1) | |
1581 | mfspr r11,SPRN_DAR | |
1582 | mfspr r12,SPRN_DSISR | |
1583 | std r11,_DAR(r1) | |
1584 | std r12,_DSISR(r1) | |
1585 | mflr r10 | |
1586 | mfctr r11 | |
1587 | mfxer r12 | |
1588 | std r10,_LINK(r1) | |
1589 | std r11,_CTR(r1) | |
1590 | std r12,_XER(r1) | |
1591 | SAVE_GPR(0,r1) | |
1592 | SAVE_GPR(2,r1) | |
1593 | ld r10,EX_R3(r3) | |
1594 | std r10,GPR3(r1) | |
1595 | SAVE_GPR(4,r1) | |
1596 | SAVE_4GPRS(5,r1) | |
1597 | ld r9,EX_R9(r3) | |
1598 | ld r10,EX_R10(r3) | |
1599 | SAVE_2GPRS(9,r1) | |
1600 | ld r9,EX_R11(r3) | |
1601 | ld r10,EX_R12(r3) | |
1602 | ld r11,EX_R13(r3) | |
1603 | std r9,GPR11(r1) | |
1604 | std r10,GPR12(r1) | |
1605 | std r11,GPR13(r1) | |
1606 | BEGIN_FTR_SECTION | |
1607 | ld r10,EX_CFAR(r3) | |
1608 | std r10,ORIG_GPR3(r1) | |
1609 | END_FTR_SECTION_IFSET(CPU_FTR_CFAR) | |
1610 | SAVE_8GPRS(14,r1) | |
1611 | SAVE_10GPRS(22,r1) | |
1612 | lhz r12,PACA_TRAP_SAVE(r13) | |
1613 | std r12,_TRAP(r1) | |
1614 | addi r11,r1,INT_FRAME_SIZE | |
1615 | std r11,0(r1) | |
1616 | li r12,0 | |
1617 | std r12,0(r11) | |
1618 | ld r2,PACATOC(r13) | |
1619 | ld r11,exception_marker@toc(r2) | |
1620 | std r12,RESULT(r1) | |
1621 | std r11,STACK_FRAME_OVERHEAD-16(r1) | |
1622 | 1: addi r3,r1,STACK_FRAME_OVERHEAD | |
1623 | bl kernel_bad_stack | |
1624 | b 1b |