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target-arm: Convert cp15 crn=13 registers
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
9ee6e8bb 2#include "gdbstub.h"
7b59220e 3#include "helper.h"
7bbcb0af 4#include "host-utils.h"
0b03bdfc
PM		 5#include "sysemu.h"
6
0ecb72a5 7static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 8{
9 int nregs;
10
11 /* VFP data registers are always little-endian. */
12 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
13 if (reg < nregs) {
14 stfq_le_p(buf, env->vfp.regs[reg]);
15 return 8;
16 }
17 if (arm_feature(env, ARM_FEATURE_NEON)) {
18 /* Aliases for Q regs. */
19 nregs += 16;
20 if (reg < nregs) {
21 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
22 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
23 return 16;
24 }
25 }
26 switch (reg - nregs) {
27 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
28 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
29 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
30 }
31 return 0;
32}
33
0ecb72a5 34static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 35{
36 int nregs;
37
38 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
39 if (reg < nregs) {
40 env->vfp.regs[reg] = ldfq_le_p(buf);
41 return 8;
42 }
43 if (arm_feature(env, ARM_FEATURE_NEON)) {
44 nregs += 16;
45 if (reg < nregs) {
46 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
47 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
48 return 16;
49 }
50 }
51 switch (reg - nregs) {
52 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
53 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 54 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 55 }
56 return 0;
57}
58
c983fe6c
PM		 59static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
60{
61 env->cp15.c3 = value;
62 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
63 return 0;
64}
65
08de207b
PM		 66static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
67{
68 if (env->cp15.c13_fcse != value) {
69 /* Unlike real hardware the qemu TLB uses virtual addresses,
70 * not modified virtual addresses, so this causes a TLB flush.
71 */
72 tlb_flush(env, 1);
73 env->cp15.c13_fcse = value;
74 }
75 return 0;
76}
77static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
78 uint64_t value)
79{
80 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
81 /* For VMSA (when not using the LPAE long descriptor page table
82 * format) this register includes the ASID, so do a TLB flush.
83 * For PMSA it is purely a process ID and no action is needed.
84 */
85 tlb_flush(env, 1);
86 }
87 env->cp15.c13_context = value;
88 return 0;
89}
90
e9aa6c21
PM		 91static const ARMCPRegInfo cp_reginfo[] = {
92 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
93 * version" bits will read as a reserved value, which should cause
94 * Linux to not try to use the debug hardware.
95 */
96 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
97 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 98 /* MMU Domain access control / MPU write buffer control */
99 { .name = "DACR", .cp = 15,
100 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
101 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
102 .resetvalue = 0, .writefn = dacr_write },
08de207b
PM		 103 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
104 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
105 .resetvalue = 0, .writefn = fcse_write },
106 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
107 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
108 .resetvalue = 0, .writefn = contextidr_write },
e9aa6c21
PM		 109 REGINFO_SENTINEL
110};
111
7d57f408
PM		 112static const ARMCPRegInfo not_v6_cp_reginfo[] = {
113 /* Not all pre-v6 cores implemented this WFI, so this is slightly
114 * over-broad.
115 */
116 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
117 .access = PL1_W, .type = ARM_CP_WFI },
118 REGINFO_SENTINEL
119};
120
121static const ARMCPRegInfo not_v7_cp_reginfo[] = {
122 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
123 * is UNPREDICTABLE; we choose to NOP as most implementations do).
124 */
125 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
126 .access = PL1_W, .type = ARM_CP_WFI },
127 REGINFO_SENTINEL
128};
129
130static const ARMCPRegInfo v6_cp_reginfo[] = {
131 /* prefetch by MVA in v6, NOP in v7 */
132 { .name = "MVA_prefetch",
133 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
134 .access = PL1_W, .type = ARM_CP_NOP },
135 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
136 .access = PL0_W, .type = ARM_CP_NOP },
137 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
138 .access = PL0_W, .type = ARM_CP_NOP },
139 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
140 .access = PL0_W, .type = ARM_CP_NOP },
141 REGINFO_SENTINEL
142};
143
200ac0ef
PM		 144static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
145 uint64_t *value)
146{
147 /* Generic performance monitor register read function for where
148 * user access may be allowed by PMUSERENR.
149 */
150 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
151 return EXCP_UDEF;
152 }
153 *value = CPREG_FIELD32(env, ri);
154 return 0;
155}
156
157static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
158 uint64_t value)
159{
160 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
161 return EXCP_UDEF;
162 }
163 /* only the DP, X, D and E bits are writable */
164 env->cp15.c9_pmcr &= ~0x39;
165 env->cp15.c9_pmcr |= (value & 0x39);
166 return 0;
167}
168
169static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
170 uint64_t value)
171{
172 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
173 return EXCP_UDEF;
174 }
175 value &= (1 << 31);
176 env->cp15.c9_pmcnten |= value;
177 return 0;
178}
179
180static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
181 uint64_t value)
182{
183 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
184 return EXCP_UDEF;
185 }
186 value &= (1 << 31);
187 env->cp15.c9_pmcnten &= ~value;
188 return 0;
189}
190
191static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
192 uint64_t value)
193{
194 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
195 return EXCP_UDEF;
196 }
197 env->cp15.c9_pmovsr &= ~value;
198 return 0;
199}
200
201static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
202 uint64_t value)
203{
204 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
205 return EXCP_UDEF;
206 }
207 env->cp15.c9_pmxevtyper = value & 0xff;
208 return 0;
209}
210
211static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
212 uint64_t value)
213{
214 env->cp15.c9_pmuserenr = value & 1;
215 return 0;
216}
217
218static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
219 uint64_t value)
220{
221 /* We have no event counters so only the C bit can be changed */
222 value &= (1 << 31);
223 env->cp15.c9_pminten |= value;
224 return 0;
225}
226
227static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
228 uint64_t value)
229{
230 value &= (1 << 31);
231 env->cp15.c9_pminten &= ~value;
232 return 0;
233}
234
e9aa6c21
PM		 235static const ARMCPRegInfo v7_cp_reginfo[] = {
236 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
237 * debug components
238 */
239 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
240 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
241 { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
242 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 243 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
244 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
245 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 246 /* Performance monitors are implementation defined in v7,
247 * but with an ARM recommended set of registers, which we
248 * follow (although we don't actually implement any counters)
249 *
250 * Performance registers fall into three categories:
251 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
252 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
253 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
254 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
255 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
256 */
257 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
258 .access = PL0_RW, .resetvalue = 0,
259 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
260 .readfn = pmreg_read, .writefn = pmcntenset_write },
261 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
262 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
263 .readfn = pmreg_read, .writefn = pmcntenclr_write },
264 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
265 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
266 .readfn = pmreg_read, .writefn = pmovsr_write },
267 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
268 * respect PMUSERENR.
269 */
270 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
271 .access = PL0_W, .type = ARM_CP_NOP },
272 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
273 * We choose to RAZ/WI. XXX should respect PMUSERENR.
274 */
275 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
276 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
277 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
278 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
279 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
280 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
281 .access = PL0_RW,
282 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
283 .readfn = pmreg_read, .writefn = pmxevtyper_write },
284 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
285 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
286 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
287 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
288 .access = PL0_R | PL1_RW,
289 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
290 .resetvalue = 0,
291 .writefn = pmuserenr_write },
292 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
293 .access = PL1_RW,
294 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
295 .resetvalue = 0,
296 .writefn = pmintenset_write },
297 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
298 .access = PL1_RW,
299 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
300 .resetvalue = 0,
301 .writefn = pmintenclr_write },
e9aa6c21
PM		 302 REGINFO_SENTINEL
303};
304
c326b979
PM		 305static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
306{
307 value &= 1;
308 env->teecr = value;
309 return 0;
310}
311
312static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
313 uint64_t *value)
314{
315 /* This is a helper function because the user access rights
316 * depend on the value of the TEECR.
317 */
318 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
319 return EXCP_UDEF;
320 }
321 *value = env->teehbr;
322 return 0;
323}
324
325static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
326 uint64_t value)
327{
328 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
329 return EXCP_UDEF;
330 }
331 env->teehbr = value;
332 return 0;
333}
334
335static const ARMCPRegInfo t2ee_cp_reginfo[] = {
336 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
337 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
338 .resetvalue = 0,
339 .writefn = teecr_write },
340 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
341 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
342 .resetvalue = 0,
343 .readfn = teehbr_read, .writefn = teehbr_write },
344 REGINFO_SENTINEL
345};
346
4d31c596
PM		 347static const ARMCPRegInfo v6k_cp_reginfo[] = {
348 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
349 .access = PL0_RW,
350 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
351 .resetvalue = 0 },
352 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
353 .access = PL0_R|PL1_W,
354 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
355 .resetvalue = 0 },
356 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
357 .access = PL1_RW,
358 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
359 .resetvalue = 0 },
360 REGINFO_SENTINEL
361};
362
6cc7a3ae
PM		 363static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
364 /* Dummy implementation: RAZ/WI the whole crn=14 space */
365 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
366 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
367 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
368 REGINFO_SENTINEL
369};
370
18032bec
PM		 371/* Return basic MPU access permission bits. */
372static uint32_t simple_mpu_ap_bits(uint32_t val)
373{
374 uint32_t ret;
375 uint32_t mask;
376 int i;
377 ret = 0;
378 mask = 3;
379 for (i = 0; i < 16; i += 2) {
380 ret |= (val >> i) & mask;
381 mask <<= 2;
382 }
383 return ret;
384}
385
386/* Pad basic MPU access permission bits to extended format. */
387static uint32_t extended_mpu_ap_bits(uint32_t val)
388{
389 uint32_t ret;
390 uint32_t mask;
391 int i;
392 ret = 0;
393 mask = 3;
394 for (i = 0; i < 16; i += 2) {
395 ret |= (val & mask) << i;
396 mask <<= 2;
397 }
398 return ret;
399}
400
401static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
402 uint64_t value)
403{
404 env->cp15.c5_data = extended_mpu_ap_bits(value);
405 return 0;
406}
407
408static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
409 uint64_t *value)
410{
411 *value = simple_mpu_ap_bits(env->cp15.c5_data);
412 return 0;
413}
414
415static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
416 uint64_t value)
417{
418 env->cp15.c5_insn = extended_mpu_ap_bits(value);
419 return 0;
420}
421
422static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
423 uint64_t *value)
424{
425 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
426 return 0;
427}
428
429static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
430 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
431 .access = PL1_RW,
432 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
433 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
434 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
435 .access = PL1_RW,
436 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
437 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
438 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
439 .access = PL1_RW,
440 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
441 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
442 .access = PL1_RW,
443 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 444 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
445 .access = PL1_RW,
446 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
447 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
448 .access = PL1_RW,
449 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
18032bec
PM		 450 REGINFO_SENTINEL
451};
452
ecce5c3c
PM		 453static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
454 uint64_t value)
455{
456 value &= 7;
457 env->cp15.c2_control = value;
458 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
459 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
460 return 0;
461}
462
463static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
464{
465 env->cp15.c2_base_mask = 0xffffc000u;
466 env->cp15.c2_control = 0;
467 env->cp15.c2_mask = 0;
468}
469
18032bec
PM		 470static const ARMCPRegInfo vmsa_cp_reginfo[] = {
471 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
472 .access = PL1_RW,
473 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
474 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
475 .access = PL1_RW,
476 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 477 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
478 .access = PL1_RW,
479 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
480 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
481 .access = PL1_RW,
482 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
483 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
484 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
485 .resetfn = vmsa_ttbcr_reset,
486 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
18032bec
PM		 487 REGINFO_SENTINEL
488};
489
490static const ARMCPRegInfo omap_cp_reginfo[] = {
491 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
492 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
493 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
494 REGINFO_SENTINEL
495};
496
2ceb98c0
PM		 497void register_cp_regs_for_features(ARMCPU *cpu)
498{
499 /* Register all the coprocessor registers based on feature bits */
500 CPUARMState *env = &cpu->env;
501 if (arm_feature(env, ARM_FEATURE_M)) {
502 /* M profile has no coprocessor registers */
503 return;
504 }
505
e9aa6c21 506 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408
PM		 507 if (arm_feature(env, ARM_FEATURE_V6)) {
508 define_arm_cp_regs(cpu, v6_cp_reginfo);
509 } else {
510 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
511 }
4d31c596
PM		 512 if (arm_feature(env, ARM_FEATURE_V6K)) {
513 define_arm_cp_regs(cpu, v6k_cp_reginfo);
514 }
e9aa6c21 515 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 516 /* v7 performance monitor control register: same implementor
517 * field as main ID register, and we implement no event counters.
518 */
519 ARMCPRegInfo pmcr = {
520 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
521 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
522 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
523 .readfn = pmreg_read, .writefn = pmcr_write
524 };
525 define_one_arm_cp_reg(cpu, &pmcr);
e9aa6c21 526 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 527 } else {
528 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 529 }
18032bec
PM		 530 if (arm_feature(env, ARM_FEATURE_MPU)) {
531 /* These are the MPU registers prior to PMSAv6. Any new
532 * PMSA core later than the ARM946 will require that we
533 * implement the PMSAv6 or PMSAv7 registers, which are
534 * completely different.
535 */
536 assert(!arm_feature(env, ARM_FEATURE_V6));
537 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
538 } else {
539 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
540 }
c326b979
PM		 541 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
542 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
543 }
6cc7a3ae
PM		 544 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
545 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
546 }
18032bec
PM		 547 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
548 define_arm_cp_regs(cpu, omap_cp_reginfo);
549 }
2ceb98c0
PM		 550}
551
778c3a06 552ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 553{
dec9c2d4 554 ARMCPU *cpu;
40f137e1 555 CPUARMState *env;
b26eefb6 556 static int inited = 0;
40f137e1 557
777dc784 558 if (!object_class_by_name(cpu_model)) {
aaed909a 559 return NULL;
777dc784
PM		 560 }
561 cpu = ARM_CPU(object_new(cpu_model));
dec9c2d4 562 env = &cpu->env;
777dc784 563 env->cpu_model_str = cpu_model;
581be094 564 arm_cpu_realize(cpu);
777dc784 565
f4fc247b 566 if (tcg_enabled() && !inited) {
b26eefb6
PB		 567 inited = 1;
568 arm_translate_init();
569 }
570
df90dadb 571 cpu_reset(CPU(cpu));
56aebc89
PB		 572 if (arm_feature(env, ARM_FEATURE_NEON)) {
573 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
574 51, "arm-neon.xml", 0);
575 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
576 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
577 35, "arm-vfp3.xml", 0);
578 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
579 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
580 19, "arm-vfp.xml", 0);
581 }
0bf46a40 582 qemu_init_vcpu(env);
778c3a06 583 return cpu;
40f137e1
PB		 584}
585
777dc784
PM		 586typedef struct ARMCPUListState {
587 fprintf_function cpu_fprintf;
588 FILE *file;
589} ARMCPUListState;
3371d272 590
777dc784
PM		 591/* Sort alphabetically by type name, except for "any". */
592static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 593{
777dc784
PM		 594 ObjectClass *class_a = (ObjectClass *)a;
595 ObjectClass *class_b = (ObjectClass *)b;
596 const char *name_a, *name_b;
5adb4839 597
777dc784
PM		 598 name_a = object_class_get_name(class_a);
599 name_b = object_class_get_name(class_b);
600 if (strcmp(name_a, "any") == 0) {
601 return 1;
602 } else if (strcmp(name_b, "any") == 0) {
603 return -1;
604 } else {
605 return strcmp(name_a, name_b);
5adb4839
PB		 606 }
607}
608
777dc784 609static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 610{
777dc784
PM		 611 ObjectClass *oc = data;
612 ARMCPUListState *s = user_data;
3371d272 613
777dc784
PM		 614 (*s->cpu_fprintf)(s->file, " %s\n",
615 object_class_get_name(oc));
616}
617
618void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
619{
620 ARMCPUListState s = {
621 .file = f,
622 .cpu_fprintf = cpu_fprintf,
623 };
624 GSList *list;
625
626 list = object_class_get_list(TYPE_ARM_CPU, false);
627 list = g_slist_sort(list, arm_cpu_list_compare);
628 (*cpu_fprintf)(f, "Available CPUs:\n");
629 g_slist_foreach(list, arm_cpu_list_entry, &s);
630 g_slist_free(list);
40f137e1
PB		 631}
632
4b6a83fb
PM		 633void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
634 const ARMCPRegInfo *r, void *opaque)
635{
636 /* Define implementations of coprocessor registers.
637 * We store these in a hashtable because typically
638 * there are less than 150 registers in a space which
639 * is 16*16*16*8*8 = 262144 in size.
640 * Wildcarding is supported for the crm, opc1 and opc2 fields.
641 * If a register is defined twice then the second definition is
642 * used, so this can be used to define some generic registers and
643 * then override them with implementation specific variations.
644 * At least one of the original and the second definition should
645 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
646 * against accidental use.
647 */
648 int crm, opc1, opc2;
649 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
650 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
651 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
652 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
653 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
654 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
655 /* 64 bit registers have only CRm and Opc1 fields */
656 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
657 /* Check that the register definition has enough info to handle
658 * reads and writes if they are permitted.
659 */
660 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
661 if (r->access & PL3_R) {
662 assert(r->fieldoffset || r->readfn);
663 }
664 if (r->access & PL3_W) {
665 assert(r->fieldoffset || r->writefn);
666 }
667 }
668 /* Bad type field probably means missing sentinel at end of reg list */
669 assert(cptype_valid(r->type));
670 for (crm = crmmin; crm <= crmmax; crm++) {
671 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
672 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
673 uint32_t *key = g_new(uint32_t, 1);
674 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
675 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
676 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
677 r2->opaque = opaque;
678 /* Make sure reginfo passed to helpers for wildcarded regs
679 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
680 */
681 r2->crm = crm;
682 r2->opc1 = opc1;
683 r2->opc2 = opc2;
684 /* Overriding of an existing definition must be explicitly
685 * requested.
686 */
687 if (!(r->type & ARM_CP_OVERRIDE)) {
688 ARMCPRegInfo *oldreg;
689 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
690 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
691 fprintf(stderr, "Register redefined: cp=%d %d bit "
692 "crn=%d crm=%d opc1=%d opc2=%d, "
693 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
694 r2->crn, r2->crm, r2->opc1, r2->opc2,
695 oldreg->name, r2->name);
696 assert(0);
697 }
698 }
699 g_hash_table_insert(cpu->cp_regs, key, r2);
700 }
701 }
702 }
703}
704
705void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
706 const ARMCPRegInfo *regs, void *opaque)
707{
708 /* Define a whole list of registers */
709 const ARMCPRegInfo *r;
710 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
711 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
712 }
713}
714
715const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
716{
717 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
718}
719
720int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
721 uint64_t value)
722{
723 /* Helper coprocessor write function for write-ignore registers */
724 return 0;
725}
726
727int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
728{
729 /* Helper coprocessor write function for read-as-zero registers */
730 *value = 0;
731 return 0;
732}
733
0ecb72a5 734static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 735{
736 /* Return true if it is not valid for us to switch to
737 * this CPU mode (ie all the UNPREDICTABLE cases in
738 * the ARM ARM CPSRWriteByInstr pseudocode).
739 */
740 switch (mode) {
741 case ARM_CPU_MODE_USR:
742 case ARM_CPU_MODE_SYS:
743 case ARM_CPU_MODE_SVC:
744 case ARM_CPU_MODE_ABT:
745 case ARM_CPU_MODE_UND:
746 case ARM_CPU_MODE_IRQ:
747 case ARM_CPU_MODE_FIQ:
748 return 0;
749 default:
750 return 1;
751 }
752}
753
2f4a40e5
AZ		 754uint32_t cpsr_read(CPUARMState *env)
755{
756 int ZF;
6fbe23d5
PB		 757 ZF = (env->ZF == 0);
758 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 759 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
760 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
761 | ((env->condexec_bits & 0xfc) << 8)
762 | (env->GE << 16);
763}
764
765void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
766{
2f4a40e5 767 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 768 env->ZF = (~val) & CPSR_Z;
769 env->NF = val;
2f4a40e5
AZ		 770 env->CF = (val >> 29) & 1;
771 env->VF = (val << 3) & 0x80000000;
772 }
773 if (mask & CPSR_Q)
774 env->QF = ((val & CPSR_Q) != 0);
775 if (mask & CPSR_T)
776 env->thumb = ((val & CPSR_T) != 0);
777 if (mask & CPSR_IT_0_1) {
778 env->condexec_bits &= ~3;
779 env->condexec_bits |= (val >> 25) & 3;
780 }
781 if (mask & CPSR_IT_2_7) {
782 env->condexec_bits &= 3;
783 env->condexec_bits |= (val >> 8) & 0xfc;
784 }
785 if (mask & CPSR_GE) {
786 env->GE = (val >> 16) & 0xf;
787 }
788
789 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 790 if (bad_mode_switch(env, val & CPSR_M)) {
791 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
792 * We choose to ignore the attempt and leave the CPSR M field
793 * untouched.
794 */
795 mask &= ~CPSR_M;
796 } else {
797 switch_mode(env, val & CPSR_M);
798 }
2f4a40e5
AZ		 799 }
800 mask &= ~CACHED_CPSR_BITS;
801 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
802}
803
b26eefb6
PB		 804/* Sign/zero extend */
805uint32_t HELPER(sxtb16)(uint32_t x)
806{
807 uint32_t res;
808 res = (uint16_t)(int8_t)x;
809 res |= (uint32_t)(int8_t)(x >> 16) << 16;
810 return res;
811}
812
813uint32_t HELPER(uxtb16)(uint32_t x)
814{
815 uint32_t res;
816 res = (uint16_t)(uint8_t)x;
817 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
818 return res;
819}
820
f51bbbfe
PB		 821uint32_t HELPER(clz)(uint32_t x)
822{
7bbcb0af 823 return clz32(x);
f51bbbfe
PB		 824}
825
3670669c
PB		 826int32_t HELPER(sdiv)(int32_t num, int32_t den)
827{
828 if (den == 0)
829 return 0;
686eeb93
AJ		 830 if (num == INT_MIN && den == -1)
831 return INT_MIN;
3670669c
PB		 832 return num / den;
833}
834
835uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
836{
837 if (den == 0)
838 return 0;
839 return num / den;
840}
841
842uint32_t HELPER(rbit)(uint32_t x)
843{
844 x = ((x & 0xff000000) >> 24)
845 | ((x & 0x00ff0000) >> 8)
846 | ((x & 0x0000ff00) << 8)
847 | ((x & 0x000000ff) << 24);
848 x = ((x & 0xf0f0f0f0) >> 4)
849 | ((x & 0x0f0f0f0f) << 4);
850 x = ((x & 0x88888888) >> 3)
851 | ((x & 0x44444444) >> 1)
852 | ((x & 0x22222222) << 1)
853 | ((x & 0x11111111) << 3);
854 return x;
855}
856
ad69471c
PB		 857uint32_t HELPER(abs)(uint32_t x)
858{
859 return ((int32_t)x < 0) ? -x : x;
860}
861
5fafdf24 862#if defined(CONFIG_USER_ONLY)
b5ff1b31 863
0ecb72a5 864void do_interrupt (CPUARMState *env)
b5ff1b31
FB		 865{
866 env->exception_index = -1;
867}
868
0ecb72a5 869int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 870 int mmu_idx)
b5ff1b31
FB		 871{
872 if (rw == 2) {
873 env->exception_index = EXCP_PREFETCH_ABORT;
874 env->cp15.c6_insn = address;
875 } else {
876 env->exception_index = EXCP_DATA_ABORT;
877 env->cp15.c6_data = address;
878 }
879 return 1;
880}
881
0ecb72a5 882void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 883{
884 cpu_abort(env, "cp15 insn %08x\n", insn);
885}
886
0ecb72a5 887uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31
FB		 888{
889 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 890}
891
9ee6e8bb 892/* These should probably raise undefined insn exceptions. */
0ecb72a5 893void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 894{
895 cpu_abort(env, "v7m_mrs %d\n", reg);
896}
897
0ecb72a5 898uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 899{
900 cpu_abort(env, "v7m_mrs %d\n", reg);
901 return 0;
902}
903
0ecb72a5 904void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 905{
906 if (mode != ARM_CPU_MODE_USR)
907 cpu_abort(env, "Tried to switch out of user mode\n");
908}
909
0ecb72a5 910void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 911{
912 cpu_abort(env, "banked r13 write\n");
913}
914
0ecb72a5 915uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 916{
917 cpu_abort(env, "banked r13 read\n");
918 return 0;
919}
920
b5ff1b31
FB		 921#else
922
923/* Map CPU modes onto saved register banks. */
0ecb72a5 924static inline int bank_number(CPUARMState *env, int mode)
b5ff1b31
FB		 925{
926 switch (mode) {
927 case ARM_CPU_MODE_USR:
928 case ARM_CPU_MODE_SYS:
929 return 0;
930 case ARM_CPU_MODE_SVC:
931 return 1;
932 case ARM_CPU_MODE_ABT:
933 return 2;
934 case ARM_CPU_MODE_UND:
935 return 3;
936 case ARM_CPU_MODE_IRQ:
937 return 4;
938 case ARM_CPU_MODE_FIQ:
939 return 5;
940 }
1b9e01c1 941 cpu_abort(env, "Bad mode %x\n", mode);
b5ff1b31
FB		 942 return -1;
943}
944
0ecb72a5 945void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 946{
947 int old_mode;
948 int i;
949
950 old_mode = env->uncached_cpsr & CPSR_M;
951 if (mode == old_mode)
952 return;
953
954 if (old_mode == ARM_CPU_MODE_FIQ) {
955 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 956 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 957 } else if (mode == ARM_CPU_MODE_FIQ) {
958 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 959 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 960 }
961
1b9e01c1 962 i = bank_number(env, old_mode);
b5ff1b31
FB		 963 env->banked_r13[i] = env->regs[13];
964 env->banked_r14[i] = env->regs[14];
965 env->banked_spsr[i] = env->spsr;
966
1b9e01c1 967 i = bank_number(env, mode);
b5ff1b31
FB		 968 env->regs[13] = env->banked_r13[i];
969 env->regs[14] = env->banked_r14[i];
970 env->spsr = env->banked_spsr[i];
971}
972
9ee6e8bb
PB		 973static void v7m_push(CPUARMState *env, uint32_t val)
974{
975 env->regs[13] -= 4;
976 stl_phys(env->regs[13], val);
977}
978
979static uint32_t v7m_pop(CPUARMState *env)
980{
981 uint32_t val;
982 val = ldl_phys(env->regs[13]);
983 env->regs[13] += 4;
984 return val;
985}
986
987/* Switch to V7M main or process stack pointer. */
988static void switch_v7m_sp(CPUARMState *env, int process)
989{
990 uint32_t tmp;
991 if (env->v7m.current_sp != process) {
992 tmp = env->v7m.other_sp;
993 env->v7m.other_sp = env->regs[13];
994 env->regs[13] = tmp;
995 env->v7m.current_sp = process;
996 }
997}
998
999static void do_v7m_exception_exit(CPUARMState *env)
1000{
1001 uint32_t type;
1002 uint32_t xpsr;
1003
1004 type = env->regs[15];
1005 if (env->v7m.exception != 0)
983fe826 1006 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1007
1008 /* Switch to the target stack. */
1009 switch_v7m_sp(env, (type & 4) != 0);
1010 /* Pop registers. */
1011 env->regs[0] = v7m_pop(env);
1012 env->regs[1] = v7m_pop(env);
1013 env->regs[2] = v7m_pop(env);
1014 env->regs[3] = v7m_pop(env);
1015 env->regs[12] = v7m_pop(env);
1016 env->regs[14] = v7m_pop(env);
1017 env->regs[15] = v7m_pop(env);
1018 xpsr = v7m_pop(env);
1019 xpsr_write(env, xpsr, 0xfffffdff);
1020 /* Undo stack alignment. */
1021 if (xpsr & 0x200)
1022 env->regs[13] |= 4;
1023 /* ??? The exception return type specifies Thread/Handler mode. However
1024 this is also implied by the xPSR value. Not sure what to do
1025 if there is a mismatch. */
1026 /* ??? Likewise for mismatches between the CONTROL register and the stack
1027 pointer. */
1028}
1029
2b3ea315 1030static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 1031{
1032 uint32_t xpsr = xpsr_read(env);
1033 uint32_t lr;
1034 uint32_t addr;
1035
1036 lr = 0xfffffff1;
1037 if (env->v7m.current_sp)
1038 lr |= 4;
1039 if (env->v7m.exception == 0)
1040 lr |= 8;
1041
1042 /* For exceptions we just mark as pending on the NVIC, and let that
1043 handle it. */
1044 /* TODO: Need to escalate if the current priority is higher than the
1045 one we're raising. */
1046 switch (env->exception_index) {
1047 case EXCP_UDEF:
983fe826 1048 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1049 return;
1050 case EXCP_SWI:
1051 env->regs[15] += 2;
983fe826 1052 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1053 return;
1054 case EXCP_PREFETCH_ABORT:
1055 case EXCP_DATA_ABORT:
983fe826 1056 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1057 return;
1058 case EXCP_BKPT:
2ad207d4
PB		 1059 if (semihosting_enabled) {
1060 int nr;
d8fd2954 1061 nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1062 if (nr == 0xab) {
1063 env->regs[15] += 2;
1064 env->regs[0] = do_arm_semihosting(env);
1065 return;
1066 }
1067 }
983fe826 1068 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 1069 return;
1070 case EXCP_IRQ:
983fe826 1071 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 1072 break;
1073 case EXCP_EXCEPTION_EXIT:
1074 do_v7m_exception_exit(env);
1075 return;
1076 default:
1077 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1078 return; /* Never happens. Keep compiler happy. */
1079 }
1080
1081 /* Align stack pointer. */
1082 /* ??? Should only do this if Configuration Control Register
1083 STACKALIGN bit is set. */
1084 if (env->regs[13] & 4) {
ab19b0ec 1085 env->regs[13] -= 4;
9ee6e8bb
PB		 1086 xpsr |= 0x200;
1087 }
6c95676b 1088 /* Switch to the handler mode. */
9ee6e8bb
PB		 1089 v7m_push(env, xpsr);
1090 v7m_push(env, env->regs[15]);
1091 v7m_push(env, env->regs[14]);
1092 v7m_push(env, env->regs[12]);
1093 v7m_push(env, env->regs[3]);
1094 v7m_push(env, env->regs[2]);
1095 v7m_push(env, env->regs[1]);
1096 v7m_push(env, env->regs[0]);
1097 switch_v7m_sp(env, 0);
c98d174c
PM		 1098 /* Clear IT bits */
1099 env->condexec_bits = 0;
9ee6e8bb
PB		 1100 env->regs[14] = lr;
1101 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1102 env->regs[15] = addr & 0xfffffffe;
1103 env->thumb = addr & 1;
1104}
1105
b5ff1b31
FB		 1106/* Handle a CPU exception. */
1107void do_interrupt(CPUARMState *env)
1108{
1109 uint32_t addr;
1110 uint32_t mask;
1111 int new_mode;
1112 uint32_t offset;
1113
9ee6e8bb
PB		 1114 if (IS_M(env)) {
1115 do_interrupt_v7m(env);
1116 return;
1117 }
b5ff1b31
FB		 1118 /* TODO: Vectored interrupt controller. */
1119 switch (env->exception_index) {
1120 case EXCP_UDEF:
1121 new_mode = ARM_CPU_MODE_UND;
1122 addr = 0x04;
1123 mask = CPSR_I;
1124 if (env->thumb)
1125 offset = 2;
1126 else
1127 offset = 4;
1128 break;
1129 case EXCP_SWI:
8e71621f
PB		 1130 if (semihosting_enabled) {
1131 /* Check for semihosting interrupt. */
1132 if (env->thumb) {
d8fd2954 1133 mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
8e71621f 1134 } else {
d8fd2954
PB		 1135 mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
1136 & 0xffffff;
8e71621f
PB		 1137 }
1138 /* Only intercept calls from privileged modes, to provide some
1139 semblance of security. */
1140 if (((mask == 0x123456 && !env->thumb)
1141 || (mask == 0xab && env->thumb))
1142 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1143 env->regs[0] = do_arm_semihosting(env);
1144 return;
1145 }
1146 }
b5ff1b31
FB		 1147 new_mode = ARM_CPU_MODE_SVC;
1148 addr = 0x08;
1149 mask = CPSR_I;
601d70b9 1150 /* The PC already points to the next instruction. */
b5ff1b31
FB		 1151 offset = 0;
1152 break;
06c949e6 1153 case EXCP_BKPT:
9ee6e8bb 1154 /* See if this is a semihosting syscall. */
2ad207d4 1155 if (env->thumb && semihosting_enabled) {
d8fd2954 1156 mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 1157 if (mask == 0xab
1158 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1159 env->regs[15] += 2;
1160 env->regs[0] = do_arm_semihosting(env);
1161 return;
1162 }
1163 }
81c05daf 1164 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 1165 /* Fall through to prefetch abort. */
1166 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 1167 new_mode = ARM_CPU_MODE_ABT;
1168 addr = 0x0c;
1169 mask = CPSR_A | CPSR_I;
1170 offset = 4;
1171 break;
1172 case EXCP_DATA_ABORT:
1173 new_mode = ARM_CPU_MODE_ABT;
1174 addr = 0x10;
1175 mask = CPSR_A | CPSR_I;
1176 offset = 8;
1177 break;
1178 case EXCP_IRQ:
1179 new_mode = ARM_CPU_MODE_IRQ;
1180 addr = 0x18;
1181 /* Disable IRQ and imprecise data aborts. */
1182 mask = CPSR_A | CPSR_I;
1183 offset = 4;
1184 break;
1185 case EXCP_FIQ:
1186 new_mode = ARM_CPU_MODE_FIQ;
1187 addr = 0x1c;
1188 /* Disable FIQ, IRQ and imprecise data aborts. */
1189 mask = CPSR_A | CPSR_I | CPSR_F;
1190 offset = 4;
1191 break;
1192 default:
1193 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1194 return; /* Never happens. Keep compiler happy. */
1195 }
1196 /* High vectors. */
1197 if (env->cp15.c1_sys & (1 << 13)) {
1198 addr += 0xffff0000;
1199 }
1200 switch_mode (env, new_mode);
1201 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1202 /* Clear IT bits. */
1203 env->condexec_bits = 0;
30a8cac1 1204 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1205 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1206 env->uncached_cpsr |= mask;
be5e7a76
DES		 1207 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1208 * and we should just guard the thumb mode on V4 */
1209 if (arm_feature(env, ARM_FEATURE_V4T)) {
1210 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1211 }
b5ff1b31
FB		 1212 env->regs[14] = env->regs[15] + offset;
1213 env->regs[15] = addr;
1214 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1215}
1216
1217/* Check section/page access permissions.
1218 Returns the page protection flags, or zero if the access is not
1219 permitted. */
0ecb72a5 1220static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1221 int access_type, int is_user)
b5ff1b31 1222{
9ee6e8bb
PB		 1223 int prot_ro;
1224
dd4ebc2e 1225 if (domain_prot == 3) {
b5ff1b31 1226 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1227 }
b5ff1b31 1228
9ee6e8bb
PB		 1229 if (access_type == 1)
1230 prot_ro = 0;
1231 else
1232 prot_ro = PAGE_READ;
1233
b5ff1b31
FB		 1234 switch (ap) {
1235 case 0:
78600320 1236 if (access_type == 1)
b5ff1b31
FB		 1237 return 0;
1238 switch ((env->cp15.c1_sys >> 8) & 3) {
1239 case 1:
1240 return is_user ? 0 : PAGE_READ;
1241 case 2:
1242 return PAGE_READ;
1243 default:
1244 return 0;
1245 }
1246 case 1:
1247 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1248 case 2:
1249 if (is_user)
9ee6e8bb 1250 return prot_ro;
b5ff1b31
FB		 1251 else
1252 return PAGE_READ | PAGE_WRITE;
1253 case 3:
1254 return PAGE_READ | PAGE_WRITE;
d4934d18 1255 case 4: /* Reserved. */
9ee6e8bb
PB		 1256 return 0;
1257 case 5:
1258 return is_user ? 0 : prot_ro;
1259 case 6:
1260 return prot_ro;
d4934d18 1261 case 7:
0ab06d83 1262 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1263 return 0;
1264 return prot_ro;
b5ff1b31
FB		 1265 default:
1266 abort();
1267 }
1268}
1269
0ecb72a5 1270static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1271{
1272 uint32_t table;
1273
1274 if (address & env->cp15.c2_mask)
1275 table = env->cp15.c2_base1 & 0xffffc000;
1276 else
1277 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1278
1279 table |= (address >> 18) & 0x3ffc;
1280 return table;
1281}
1282
0ecb72a5 1283static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1284 int is_user, uint32_t *phys_ptr, int *prot,
1285 target_ulong *page_size)
b5ff1b31
FB		 1286{
1287 int code;
1288 uint32_t table;
1289 uint32_t desc;
1290 int type;
1291 int ap;
1292 int domain;
dd4ebc2e 1293 int domain_prot;
b5ff1b31
FB		 1294 uint32_t phys_addr;
1295
9ee6e8bb
PB		 1296 /* Pagetable walk. */
1297 /* Lookup l1 descriptor. */
b2fa1797 1298 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1299 desc = ldl_phys(table);
1300 type = (desc & 3);
dd4ebc2e
JCD		 1301 domain = (desc >> 5) & 0x0f;
1302 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1303 if (type == 0) {
601d70b9 1304 /* Section translation fault. */
9ee6e8bb
PB		 1305 code = 5;
1306 goto do_fault;
1307 }
dd4ebc2e 1308 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1309 if (type == 2)
1310 code = 9; /* Section domain fault. */
1311 else
1312 code = 11; /* Page domain fault. */
1313 goto do_fault;
1314 }
1315 if (type == 2) {
1316 /* 1Mb section. */
1317 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1318 ap = (desc >> 10) & 3;
1319 code = 13;
d4c430a8 1320 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1321 } else {
1322 /* Lookup l2 entry. */
1323 if (type == 1) {
1324 /* Coarse pagetable. */
1325 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1326 } else {
1327 /* Fine pagetable. */
1328 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1329 }
1330 desc = ldl_phys(table);
1331 switch (desc & 3) {
1332 case 0: /* Page translation fault. */
1333 code = 7;
1334 goto do_fault;
1335 case 1: /* 64k page. */
1336 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1337 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1338 *page_size = 0x10000;
ce819861 1339 break;
9ee6e8bb
PB		 1340 case 2: /* 4k page. */
1341 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1342 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1343 *page_size = 0x1000;
ce819861 1344 break;
9ee6e8bb
PB		 1345 case 3: /* 1k page. */
1346 if (type == 1) {
1347 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1348 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1349 } else {
1350 /* Page translation fault. */
1351 code = 7;
1352 goto do_fault;
1353 }
1354 } else {
1355 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1356 }
1357 ap = (desc >> 4) & 3;
d4c430a8 1358 *page_size = 0x400;
ce819861
PB		 1359 break;
1360 default:
9ee6e8bb
PB		 1361 /* Never happens, but compiler isn't smart enough to tell. */
1362 abort();
ce819861 1363 }
9ee6e8bb
PB		 1364 code = 15;
1365 }
dd4ebc2e 1366 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 1367 if (!*prot) {
1368 /* Access permission fault. */
1369 goto do_fault;
1370 }
3ad493fc 1371 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1372 *phys_ptr = phys_addr;
1373 return 0;
1374do_fault:
1375 return code | (domain << 4);
1376}
1377
0ecb72a5 1378static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1379 int is_user, uint32_t *phys_ptr, int *prot,
1380 target_ulong *page_size)
9ee6e8bb
PB		 1381{
1382 int code;
1383 uint32_t table;
1384 uint32_t desc;
1385 uint32_t xn;
1386 int type;
1387 int ap;
1388 int domain;
dd4ebc2e 1389 int domain_prot;
9ee6e8bb
PB		 1390 uint32_t phys_addr;
1391
1392 /* Pagetable walk. */
1393 /* Lookup l1 descriptor. */
b2fa1797 1394 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1395 desc = ldl_phys(table);
1396 type = (desc & 3);
1397 if (type == 0) {
601d70b9 1398 /* Section translation fault. */
9ee6e8bb
PB		 1399 code = 5;
1400 domain = 0;
1401 goto do_fault;
1402 } else if (type == 2 && (desc & (1 << 18))) {
1403 /* Supersection. */
1404 domain = 0;
b5ff1b31 1405 } else {
9ee6e8bb 1406 /* Section or page. */
dd4ebc2e 1407 domain = (desc >> 5) & 0x0f;
9ee6e8bb 1408 }
dd4ebc2e
JCD		 1409 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1410 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1411 if (type == 2)
1412 code = 9; /* Section domain fault. */
1413 else
1414 code = 11; /* Page domain fault. */
1415 goto do_fault;
1416 }
1417 if (type == 2) {
1418 if (desc & (1 << 18)) {
1419 /* Supersection. */
1420 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1421 *page_size = 0x1000000;
b5ff1b31 1422 } else {
9ee6e8bb
PB		 1423 /* Section. */
1424 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1425 *page_size = 0x100000;
b5ff1b31 1426 }
9ee6e8bb
PB		 1427 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1428 xn = desc & (1 << 4);
1429 code = 13;
1430 } else {
1431 /* Lookup l2 entry. */
1432 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1433 desc = ldl_phys(table);
1434 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1435 switch (desc & 3) {
1436 case 0: /* Page translation fault. */
1437 code = 7;
b5ff1b31 1438 goto do_fault;
9ee6e8bb
PB		 1439 case 1: /* 64k page. */
1440 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1441 xn = desc & (1 << 15);
d4c430a8 1442 *page_size = 0x10000;
9ee6e8bb
PB		 1443 break;
1444 case 2: case 3: /* 4k page. */
1445 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1446 xn = desc & 1;
d4c430a8 1447 *page_size = 0x1000;
9ee6e8bb
PB		 1448 break;
1449 default:
1450 /* Never happens, but compiler isn't smart enough to tell. */
1451 abort();
b5ff1b31 1452 }
9ee6e8bb
PB		 1453 code = 15;
1454 }
dd4ebc2e 1455 if (domain_prot == 3) {
c0034328
JR		 1456 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1457 } else {
1458 if (xn && access_type == 2)
1459 goto do_fault;
9ee6e8bb 1460
c0034328
JR		 1461 /* The simplified model uses AP[0] as an access control bit. */
1462 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1463 /* Access flag fault. */
1464 code = (code == 15) ? 6 : 3;
1465 goto do_fault;
1466 }
dd4ebc2e 1467 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 1468 if (!*prot) {
1469 /* Access permission fault. */
1470 goto do_fault;
1471 }
1472 if (!xn) {
1473 *prot |= PAGE_EXEC;
1474 }
3ad493fc 1475 }
9ee6e8bb 1476 *phys_ptr = phys_addr;
b5ff1b31
FB		 1477 return 0;
1478do_fault:
1479 return code | (domain << 4);
1480}
1481
0ecb72a5 1482static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type,
9ee6e8bb
PB		 1483 int is_user, uint32_t *phys_ptr, int *prot)
1484{
1485 int n;
1486 uint32_t mask;
1487 uint32_t base;
1488
1489 *phys_ptr = address;
1490 for (n = 7; n >= 0; n--) {
1491 base = env->cp15.c6_region[n];
1492 if ((base & 1) == 0)
1493 continue;
1494 mask = 1 << ((base >> 1) & 0x1f);
1495 /* Keep this shift separate from the above to avoid an
1496 (undefined) << 32. */
1497 mask = (mask << 1) - 1;
1498 if (((base ^ address) & ~mask) == 0)
1499 break;
1500 }
1501 if (n < 0)
1502 return 2;
1503
1504 if (access_type == 2) {
1505 mask = env->cp15.c5_insn;
1506 } else {
1507 mask = env->cp15.c5_data;
1508 }
1509 mask = (mask >> (n * 4)) & 0xf;
1510 switch (mask) {
1511 case 0:
1512 return 1;
1513 case 1:
1514 if (is_user)
1515 return 1;
1516 *prot = PAGE_READ | PAGE_WRITE;
1517 break;
1518 case 2:
1519 *prot = PAGE_READ;
1520 if (!is_user)
1521 *prot |= PAGE_WRITE;
1522 break;
1523 case 3:
1524 *prot = PAGE_READ | PAGE_WRITE;
1525 break;
1526 case 5:
1527 if (is_user)
1528 return 1;
1529 *prot = PAGE_READ;
1530 break;
1531 case 6:
1532 *prot = PAGE_READ;
1533 break;
1534 default:
1535 /* Bad permission. */
1536 return 1;
1537 }
3ad493fc 1538 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1539 return 0;
1540}
1541
0ecb72a5 1542static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 1543 int access_type, int is_user,
d4c430a8
PB		 1544 uint32_t *phys_ptr, int *prot,
1545 target_ulong *page_size)
9ee6e8bb
PB		 1546{
1547 /* Fast Context Switch Extension. */
1548 if (address < 0x02000000)
1549 address += env->cp15.c13_fcse;
1550
1551 if ((env->cp15.c1_sys & 1) == 0) {
1552 /* MMU/MPU disabled. */
1553 *phys_ptr = address;
3ad493fc 1554 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 1555 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1556 return 0;
1557 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 1558 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 1559 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1560 prot);
1561 } else if (env->cp15.c1_sys & (1 << 23)) {
1562 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 1563 prot, page_size);
9ee6e8bb
PB		 1564 } else {
1565 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 1566 prot, page_size);
9ee6e8bb
PB		 1567 }
1568}
1569
0ecb72a5 1570int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 1571 int access_type, int mmu_idx)
b5ff1b31
FB		 1572{
1573 uint32_t phys_addr;
d4c430a8 1574 target_ulong page_size;
b5ff1b31 1575 int prot;
6ebbf390 1576 int ret, is_user;
b5ff1b31 1577
6ebbf390 1578 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 1579 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
1580 &page_size);
b5ff1b31
FB		 1581 if (ret == 0) {
1582 /* Map a single [sub]page. */
1583 phys_addr &= ~(uint32_t)0x3ff;
1584 address &= ~(uint32_t)0x3ff;
3ad493fc 1585 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 1586 return 0;
b5ff1b31
FB		 1587 }
1588
1589 if (access_type == 2) {
1590 env->cp15.c5_insn = ret;
1591 env->cp15.c6_insn = address;
1592 env->exception_index = EXCP_PREFETCH_ABORT;
1593 } else {
1594 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1595 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1596 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1597 env->cp15.c6_data = address;
1598 env->exception_index = EXCP_DATA_ABORT;
1599 }
1600 return 1;
1601}
1602
0ecb72a5 1603target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31
FB		 1604{
1605 uint32_t phys_addr;
d4c430a8 1606 target_ulong page_size;
b5ff1b31
FB		 1607 int prot;
1608 int ret;
1609
d4c430a8 1610 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 1611
1612 if (ret != 0)
1613 return -1;
1614
1615 return phys_addr;
1616}
1617
0ecb72a5 1618void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31 1619{
9ee6e8bb
PB		 1620 int op1;
1621 int op2;
1622 int crm;
b5ff1b31 1623
9ee6e8bb 1624 op1 = (insn >> 21) & 7;
b5ff1b31 1625 op2 = (insn >> 5) & 7;
ce819861 1626 crm = insn & 0xf;
b5ff1b31 1627 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1628 case 0:
9ee6e8bb 1629 /* ID codes. */
610c3c8a
AZ		 1630 if (arm_feature(env, ARM_FEATURE_XSCALE))
1631 break;
c3d2689d
AZ		 1632 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1633 break;
a49ea279
PB		 1634 if (arm_feature(env, ARM_FEATURE_V7)
1635 && op1 == 2 && crm == 0 && op2 == 0) {
1636 env->cp15.c0_cssel = val & 0xf;
1637 break;
1638 }
b5ff1b31
FB		 1639 goto bad_reg;
1640 case 1: /* System configuration. */
2be27624
RH		 1641 if (arm_feature(env, ARM_FEATURE_V7)
1642 && op1 == 0 && crm == 1 && op2 == 0) {
1643 env->cp15.c1_scr = val;
1644 break;
1645 }
c3d2689d
AZ		 1646 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1647 op2 = 0;
b5ff1b31
FB		 1648 switch (op2) {
1649 case 0:
ce819861 1650 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1651 env->cp15.c1_sys = val;
b5ff1b31
FB		 1652 /* ??? Lots of these bits are not implemented. */
1653 /* This may enable/disable the MMU, so do a TLB flush. */
1654 tlb_flush(env, 1);
1655 break;
61cc8701 1656 case 1: /* Auxiliary control register. */
610c3c8a
AZ		 1657 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1658 env->cp15.c1_xscaleauxcr = val;
c1713132 1659 break;
610c3c8a 1660 }
9ee6e8bb
PB		 1661 /* Not implemented. */
1662 break;
b5ff1b31 1663 case 2:
610c3c8a
AZ		 1664 if (arm_feature(env, ARM_FEATURE_XSCALE))
1665 goto bad_reg;
4be27dbb
PB		 1666 if (env->cp15.c1_coproc != val) {
1667 env->cp15.c1_coproc = val;
1668 /* ??? Is this safe when called from within a TB? */
1669 tb_flush(env);
1670 }
c1713132 1671 break;
b5ff1b31
FB		 1672 default:
1673 goto bad_reg;
1674 }
1675 break;
b5ff1b31
FB		 1676 case 4: /* Reserved. */
1677 goto bad_reg;
ce819861
PB		 1678 case 6: /* MMU Fault address / MPU base/size. */
1679 if (arm_feature(env, ARM_FEATURE_MPU)) {
1680 if (crm >= 8)
1681 goto bad_reg;
1682 env->cp15.c6_region[crm] = val;
1683 } else {
c3d2689d
AZ		 1684 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1685 op2 = 0;
ce819861
PB		 1686 switch (op2) {
1687 case 0:
1688 env->cp15.c6_data = val;
1689 break;
9ee6e8bb
PB		 1690 case 1: /* ??? This is WFAR on armv6 */
1691 case 2:
ce819861
PB		 1692 env->cp15.c6_insn = val;
1693 break;
1694 default:
1695 goto bad_reg;
1696 }
1697 }
1698 break;
b5ff1b31 1699 case 7: /* Cache control. */
c3d2689d
AZ		 1700 env->cp15.c15_i_max = 0x000;
1701 env->cp15.c15_i_min = 0xff0;
f8bf8606
AL		 1702 if (op1 != 0) {
1703 goto bad_reg;
1704 }
1705 /* No cache, so nothing to do except VA->PA translations. */
906879a9 1706 if (arm_feature(env, ARM_FEATURE_VAPA)) {
f8bf8606
AL		 1707 switch (crm) {
1708 case 4:
1709 if (arm_feature(env, ARM_FEATURE_V7)) {
1710 env->cp15.c7_par = val & 0xfffff6ff;
1711 } else {
1712 env->cp15.c7_par = val & 0xfffff1ff;
1713 }
1714 break;
1715 case 8: {
1716 uint32_t phys_addr;
1717 target_ulong page_size;
1718 int prot;
1719 int ret, is_user = op2 & 2;
1720 int access_type = op2 & 1;
1721
1722 if (op2 & 4) {
1723 /* Other states are only available with TrustZone */
1724 goto bad_reg;
1725 }
1726 ret = get_phys_addr(env, val, access_type, is_user,
1727 &phys_addr, &prot, &page_size);
1728 if (ret == 0) {
1729 /* We do not set any attribute bits in the PAR */
1730 if (page_size == (1 << 24)
1731 && arm_feature(env, ARM_FEATURE_V7)) {
1732 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
1733 } else {
1734 env->cp15.c7_par = phys_addr & 0xfffff000;
1735 }
1736 } else {
1737 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
1738 ((ret & (12 << 1)) >> 6) |
1739 ((ret & 0xf) << 1) | 1;
1740 }
1741 break;
1742 }
1743 }
1744 }
b5ff1b31
FB		 1745 break;
1746 case 8: /* MMU TLB control. */
1747 switch (op2) {
dc8714ca
PM		 1748 case 0: /* Invalidate all (TLBIALL) */
1749 tlb_flush(env, 1);
b5ff1b31 1750 break;
dc8714ca 1751 case 1: /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
d4c430a8 1752 tlb_flush_page(env, val & TARGET_PAGE_MASK);
b5ff1b31 1753 break;
dc8714ca 1754 case 2: /* Invalidate by ASID (TLBIASID) */
9ee6e8bb
PB		 1755 tlb_flush(env, val == 0);
1756 break;
dc8714ca
PM		 1757 case 3: /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
1758 tlb_flush_page(env, val & TARGET_PAGE_MASK);
9ee6e8bb 1759 break;
b5ff1b31
FB		 1760 default:
1761 goto bad_reg;
1762 }
1763 break;
ce819861 1764 case 9:
c3d2689d
AZ		 1765 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1766 break;
5bc95aa2
DES		 1767 if (arm_feature(env, ARM_FEATURE_STRONGARM))
1768 break; /* Ignore ReadBuffer access */
ce819861
PB		 1769 switch (crm) {
1770 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1771 switch (op1) {
1772 case 0: /* L1 cache. */
1773 switch (op2) {
1774 case 0:
1775 env->cp15.c9_data = val;
1776 break;
1777 case 1:
1778 env->cp15.c9_insn = val;
1779 break;
1780 default:
1781 goto bad_reg;
1782 }
1783 break;
1784 case 1: /* L2 cache. */
1785 /* Ignore writes to L2 lockdown/auxiliary registers. */
1786 break;
1787 default:
1788 goto bad_reg;
1789 }
1790 break;
ce819861
PB		 1791 case 1: /* TCM memory region registers. */
1792 /* Not implemented. */
1793 goto bad_reg;
b5ff1b31
FB		 1794 default:
1795 goto bad_reg;
1796 }
1797 break;
1798 case 10: /* MMU TLB lockdown. */
1799 /* ??? TLB lockdown not implemented. */
1800 break;
b5ff1b31
FB		 1801 case 12: /* Reserved. */
1802 goto bad_reg;
b5ff1b31 1803 case 15: /* Implementation specific. */
c1713132 1804 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1805 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1806 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1807 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1808 tb_flush(env);
1809 env->cp15.c15_cpar = val & 0x3fff;
1810 }
c1713132
AZ		 1811 break;
1812 }
1813 goto bad_reg;
1814 }
c3d2689d
AZ		 1815 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1816 switch (crm) {
1817 case 0:
1818 break;
1819 case 1: /* Set TI925T configuration. */
1820 env->cp15.c15_ticonfig = val & 0xe7;
1821 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1822 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1823 break;
1824 case 2: /* Set I_max. */
1825 env->cp15.c15_i_max = val;
1826 break;
1827 case 3: /* Set I_min. */
1828 env->cp15.c15_i_min = val;
1829 break;
1830 case 4: /* Set thread-ID. */
1831 env->cp15.c15_threadid = val & 0xffff;
1832 break;
1833 case 8: /* Wait-for-interrupt (deprecated). */
1834 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1835 break;
1836 default:
1837 goto bad_reg;
1838 }
1839 }
7da362d0
ML		 1840 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
1841 switch (crm) {
1842 case 0:
1843 if ((op1 == 0) && (op2 == 0)) {
1844 env->cp15.c15_power_control = val;
1845 } else if ((op1 == 0) && (op2 == 1)) {
1846 env->cp15.c15_diagnostic = val;
1847 } else if ((op1 == 0) && (op2 == 2)) {
1848 env->cp15.c15_power_diagnostic = val;
1849 }
1850 default:
1851 break;
1852 }
1853 }
b5ff1b31
FB		 1854 break;
1855 }
1856 return;
1857bad_reg:
1858 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1859 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1860 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1861}
1862
0ecb72a5 1863uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31 1864{
9ee6e8bb
PB		 1865 int op1;
1866 int op2;
1867 int crm;
b5ff1b31 1868
9ee6e8bb 1869 op1 = (insn >> 21) & 7;
b5ff1b31 1870 op2 = (insn >> 5) & 7;
c3d2689d 1871 crm = insn & 0xf;
b5ff1b31
FB		 1872 switch ((insn >> 16) & 0xf) {
1873 case 0: /* ID codes. */
9ee6e8bb
PB		 1874 switch (op1) {
1875 case 0:
1876 switch (crm) {
1877 case 0:
1878 switch (op2) {
1879 case 0: /* Device ID. */
1880 return env->cp15.c0_cpuid;
1881 case 1: /* Cache Type. */
1882 return env->cp15.c0_cachetype;
1883 case 2: /* TCM status. */
1884 return 0;
1885 case 3: /* TLB type register. */
1886 return 0; /* No lockable TLB entries. */
607b4b08
PM		 1887 case 5: /* MPIDR */
1888 /* The MPIDR was standardised in v7; prior to
1889 * this it was implemented only in the 11MPCore.
1890 * For all other pre-v7 cores it does not exist.
1891 */
1892 if (arm_feature(env, ARM_FEATURE_V7) ||
1893 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
1894 int mpidr = env->cpu_index;
1895 /* We don't support setting cluster ID ([8..11])
1896 * so these bits always RAZ.
1897 */
1898 if (arm_feature(env, ARM_FEATURE_V7MP)) {
1899 mpidr |= (1 << 31);
1900 /* Cores which are uniprocessor (non-coherent)
1901 * but still implement the MP extensions set
1902 * bit 30. (For instance, A9UP.) However we do
1903 * not currently model any of those cores.
1904 */
1905 }
1906 return mpidr;
10055562 1907 }
607b4b08 1908 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 1909 default:
1910 goto bad_reg;
1911 }
1912 case 1:
1913 if (!arm_feature(env, ARM_FEATURE_V6))
1914 goto bad_reg;
1915 return env->cp15.c0_c1[op2];
1916 case 2:
1917 if (!arm_feature(env, ARM_FEATURE_V6))
1918 goto bad_reg;
1919 return env->cp15.c0_c2[op2];
1920 case 3: case 4: case 5: case 6: case 7:
1921 return 0;
1922 default:
1923 goto bad_reg;
1924 }
1925 case 1:
1926 /* These registers aren't documented on arm11 cores. However
1927 Linux looks at them anyway. */
1928 if (!arm_feature(env, ARM_FEATURE_V6))
1929 goto bad_reg;
1930 if (crm != 0)
1931 goto bad_reg;
a49ea279
PB		 1932 if (!arm_feature(env, ARM_FEATURE_V7))
1933 return 0;
1934
1935 switch (op2) {
1936 case 0:
1937 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1938 case 1:
1939 return env->cp15.c0_clid;
1940 case 7:
1941 return 0;
1942 }
1943 goto bad_reg;
1944 case 2:
1945 if (op2 != 0 || crm != 0)
610c3c8a 1946 goto bad_reg;
a49ea279 1947 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1948 default:
1949 goto bad_reg;
b5ff1b31
FB		 1950 }
1951 case 1: /* System configuration. */
2be27624
RH		 1952 if (arm_feature(env, ARM_FEATURE_V7)
1953 && op1 == 0 && crm == 1 && op2 == 0) {
1954 return env->cp15.c1_scr;
1955 }
c3d2689d
AZ		 1956 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1957 op2 = 0;
b5ff1b31
FB		 1958 switch (op2) {
1959 case 0: /* Control register. */
1960 return env->cp15.c1_sys;
1961 case 1: /* Auxiliary control register. */
c1713132 1962 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1963 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1964 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1965 goto bad_reg;
1966 switch (ARM_CPUID(env)) {
1967 case ARM_CPUID_ARM1026:
1968 return 1;
1969 case ARM_CPUID_ARM1136:
827df9f3 1970 case ARM_CPUID_ARM1136_R2:
7807eed9 1971 case ARM_CPUID_ARM1176:
9ee6e8bb
PB		 1972 return 7;
1973 case ARM_CPUID_ARM11MPCORE:
1974 return 1;
1975 case ARM_CPUID_CORTEXA8:
533d177a 1976 return 2;
10055562 1977 case ARM_CPUID_CORTEXA9:
0b03bdfc 1978 case ARM_CPUID_CORTEXA15:
10055562 1979 return 0;
9ee6e8bb
PB		 1980 default:
1981 goto bad_reg;
1982 }
b5ff1b31 1983 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1984 if (arm_feature(env, ARM_FEATURE_XSCALE))
1985 goto bad_reg;
b5ff1b31
FB		 1986 return env->cp15.c1_coproc;
1987 default:
1988 goto bad_reg;
1989 }
b5ff1b31
FB		 1990 case 4: /* Reserved. */
1991 goto bad_reg;
9ee6e8bb 1992 case 6: /* MMU Fault address. */
ce819861 1993 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1994 if (crm >= 8)
ce819861 1995 goto bad_reg;
9ee6e8bb 1996 return env->cp15.c6_region[crm];
ce819861 1997 } else {
c3d2689d
AZ		 1998 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1999 op2 = 0;
9ee6e8bb
PB		 2000 switch (op2) {
2001 case 0:
2002 return env->cp15.c6_data;
2003 case 1:
2004 if (arm_feature(env, ARM_FEATURE_V6)) {
2005 /* Watchpoint Fault Adrress. */
2006 return 0; /* Not implemented. */
2007 } else {
2008 /* Instruction Fault Adrress. */
2009 /* Arm9 doesn't have an IFAR, but implementing it anyway
2010 shouldn't do any harm. */
2011 return env->cp15.c6_insn;
2012 }
2013 case 2:
2014 if (arm_feature(env, ARM_FEATURE_V6)) {
2015 /* Instruction Fault Adrress. */
2016 return env->cp15.c6_insn;
2017 } else {
2018 goto bad_reg;
2019 }
2020 default:
2021 goto bad_reg;
2022 }
b5ff1b31
FB		 2023 }
2024 case 7: /* Cache control. */
f8bf8606
AL		 2025 if (crm == 4 && op1 == 0 && op2 == 0) {
2026 return env->cp15.c7_par;
2027 }
6fbe23d5
PB		 2028 /* FIXME: Should only clear Z flag if destination is r15. */
2029 env->ZF = 0;
b5ff1b31
FB		 2030 return 0;
2031 case 8: /* MMU TLB control. */
2032 goto bad_reg;
74594c9d
PM		 2033 case 9:
2034 switch (crm) {
2035 case 0: /* Cache lockdown */
2036 switch (op1) {
2037 case 0: /* L1 cache. */
2038 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2039 return 0;
2040 }
2041 switch (op2) {
2042 case 0:
2043 return env->cp15.c9_data;
2044 case 1:
2045 return env->cp15.c9_insn;
2046 default:
2047 goto bad_reg;
2048 }
2049 case 1: /* L2 cache */
0b03bdfc
PM		 2050 /* L2 Lockdown and Auxiliary control. */
2051 switch (op2) {
2052 case 0:
2053 /* L2 cache lockdown (A8 only) */
2054 return 0;
2055 case 2:
2056 /* L2 cache auxiliary control (A8) or control (A15) */
2057 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA15) {
2058 /* Linux wants the number of processors from here.
2059 * Might as well set the interrupt-controller bit too.
2060 */
2061 return ((smp_cpus - 1) << 24) | (1 << 23);
2062 }
2063 return 0;
2064 case 3:
2065 /* L2 cache extended control (A15) */
2066 return 0;
2067 default:
74594c9d
PM		 2068 goto bad_reg;
2069 }
74594c9d
PM		 2070 default:
2071 goto bad_reg;
2072 }
2073 break;
b5ff1b31
FB		 2074 default:
2075 goto bad_reg;
2076 }
74594c9d 2077 break;
b5ff1b31
FB		 2078 case 10: /* MMU TLB lockdown. */
2079 /* ??? TLB lockdown not implemented. */
2080 return 0;
2081 case 11: /* TCM DMA control. */
2082 case 12: /* Reserved. */
2083 goto bad_reg;
b5ff1b31 2084 case 15: /* Implementation specific. */
c1713132 2085 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 2086 if (op2 == 0 && crm == 1)
c1713132
AZ		 2087 return env->cp15.c15_cpar;
2088
2089 goto bad_reg;
2090 }
c3d2689d
AZ		 2091 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2092 switch (crm) {
2093 case 0:
2094 return 0;
2095 case 1: /* Read TI925T configuration. */
2096 return env->cp15.c15_ticonfig;
2097 case 2: /* Read I_max. */
2098 return env->cp15.c15_i_max;
2099 case 3: /* Read I_min. */
2100 return env->cp15.c15_i_min;
2101 case 4: /* Read thread-ID. */
2102 return env->cp15.c15_threadid;
2103 case 8: /* TI925T_status */
2104 return 0;
2105 }
827df9f3
AZ		 2106 /* TODO: Peripheral port remap register:
2107 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
2108 * controller base address at $rn & ~0xfff and map size of
2109 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 2110 goto bad_reg;
2111 }
7da362d0
ML		 2112 if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
2113 switch (crm) {
2114 case 0:
2115 if ((op1 == 4) && (op2 == 0)) {
2116 /* The config_base_address should hold the value of
2117 * the peripheral base. ARM should get this from a CPU
2118 * object property, but that support isn't available in
2119 * December 2011. Default to 0 for now and board models
2120 * that care can set it by a private hook */
2121 return env->cp15.c15_config_base_address;
2122 } else if ((op1 == 0) && (op2 == 0)) {
2123 /* power_control should be set to maximum latency. Again,
2124 default to 0 and set by private hook */
2125 return env->cp15.c15_power_control;
2126 } else if ((op1 == 0) && (op2 == 1)) {
2127 return env->cp15.c15_diagnostic;
2128 } else if ((op1 == 0) && (op2 == 2)) {
2129 return env->cp15.c15_power_diagnostic;
2130 }
2131 break;
2132 case 1: /* NEON Busy */
2133 return 0;
2134 case 5: /* tlb lockdown */
2135 case 6:
2136 case 7:
2137 if ((op1 == 5) && (op2 == 2)) {
2138 return 0;
2139 }
2140 break;
2141 default:
2142 break;
2143 }
2144 goto bad_reg;
2145 }
b5ff1b31
FB		 2146 return 0;
2147 }
2148bad_reg:
2149 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2150 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2151 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2152 return 0;
2153}
2154
0ecb72a5 2155void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2156{
39ea3d4e
PM		 2157 if ((env->uncached_cpsr & CPSR_M) == mode) {
2158 env->regs[13] = val;
2159 } else {
1b9e01c1 2160 env->banked_r13[bank_number(env, mode)] = val;
39ea3d4e 2161 }
9ee6e8bb
PB		 2162}
2163
0ecb72a5 2164uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2165{
39ea3d4e
PM		 2166 if ((env->uncached_cpsr & CPSR_M) == mode) {
2167 return env->regs[13];
2168 } else {
1b9e01c1 2169 return env->banked_r13[bank_number(env, mode)];
39ea3d4e 2170 }
9ee6e8bb
PB		 2171}
2172
0ecb72a5 2173uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2174{
2175 switch (reg) {
2176 case 0: /* APSR */
2177 return xpsr_read(env) & 0xf8000000;
2178 case 1: /* IAPSR */
2179 return xpsr_read(env) & 0xf80001ff;
2180 case 2: /* EAPSR */
2181 return xpsr_read(env) & 0xff00fc00;
2182 case 3: /* xPSR */
2183 return xpsr_read(env) & 0xff00fdff;
2184 case 5: /* IPSR */
2185 return xpsr_read(env) & 0x000001ff;
2186 case 6: /* EPSR */
2187 return xpsr_read(env) & 0x0700fc00;
2188 case 7: /* IEPSR */
2189 return xpsr_read(env) & 0x0700edff;
2190 case 8: /* MSP */
2191 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2192 case 9: /* PSP */
2193 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2194 case 16: /* PRIMASK */
2195 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2196 case 17: /* BASEPRI */
2197 case 18: /* BASEPRI_MAX */
9ee6e8bb 2198 return env->v7m.basepri;
82845826
SH		 2199 case 19: /* FAULTMASK */
2200 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2201 case 20: /* CONTROL */
2202 return env->v7m.control;
2203 default:
2204 /* ??? For debugging only. */
2205 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2206 return 0;
2207 }
2208}
2209
0ecb72a5 2210void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2211{
2212 switch (reg) {
2213 case 0: /* APSR */
2214 xpsr_write(env, val, 0xf8000000);
2215 break;
2216 case 1: /* IAPSR */
2217 xpsr_write(env, val, 0xf8000000);
2218 break;
2219 case 2: /* EAPSR */
2220 xpsr_write(env, val, 0xfe00fc00);
2221 break;
2222 case 3: /* xPSR */
2223 xpsr_write(env, val, 0xfe00fc00);
2224 break;
2225 case 5: /* IPSR */
2226 /* IPSR bits are readonly. */
2227 break;
2228 case 6: /* EPSR */
2229 xpsr_write(env, val, 0x0600fc00);
2230 break;
2231 case 7: /* IEPSR */
2232 xpsr_write(env, val, 0x0600fc00);
2233 break;
2234 case 8: /* MSP */
2235 if (env->v7m.current_sp)
2236 env->v7m.other_sp = val;
2237 else
2238 env->regs[13] = val;
2239 break;
2240 case 9: /* PSP */
2241 if (env->v7m.current_sp)
2242 env->regs[13] = val;
2243 else
2244 env->v7m.other_sp = val;
2245 break;
2246 case 16: /* PRIMASK */
2247 if (val & 1)
2248 env->uncached_cpsr |= CPSR_I;
2249 else
2250 env->uncached_cpsr &= ~CPSR_I;
2251 break;
82845826 2252 case 17: /* BASEPRI */
9ee6e8bb
PB		 2253 env->v7m.basepri = val & 0xff;
2254 break;
82845826 2255 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2256 val &= 0xff;
2257 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2258 env->v7m.basepri = val;
2259 break;
82845826
SH		 2260 case 19: /* FAULTMASK */
2261 if (val & 1)
2262 env->uncached_cpsr |= CPSR_F;
2263 else
2264 env->uncached_cpsr &= ~CPSR_F;
2265 break;
9ee6e8bb
PB		 2266 case 20: /* CONTROL */
2267 env->v7m.control = val & 3;
2268 switch_v7m_sp(env, (val & 2) != 0);
2269 break;
2270 default:
2271 /* ??? For debugging only. */
2272 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2273 return;
2274 }
2275}
2276
b5ff1b31 2277#endif
6ddbc6e4
PB		 2278
2279/* Note that signed overflow is undefined in C. The following routines are
2280 careful to use unsigned types where modulo arithmetic is required.
2281 Failure to do so _will_ break on newer gcc. */
2282
2283/* Signed saturating arithmetic. */
2284
1654b2d6 2285/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2286static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2287{
2288 uint16_t res;
2289
2290 res = a + b;
2291 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2292 if (a & 0x8000)
2293 res = 0x8000;
2294 else
2295 res = 0x7fff;
2296 }
2297 return res;
2298}
2299
1654b2d6 2300/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2301static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2302{
2303 uint8_t res;
2304
2305 res = a + b;
2306 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2307 if (a & 0x80)
2308 res = 0x80;
2309 else
2310 res = 0x7f;
2311 }
2312 return res;
2313}
2314
1654b2d6 2315/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2316static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2317{
2318 uint16_t res;
2319
2320 res = a - b;
2321 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2322 if (a & 0x8000)
2323 res = 0x8000;
2324 else
2325 res = 0x7fff;
2326 }
2327 return res;
2328}
2329
1654b2d6 2330/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2331static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2332{
2333 uint8_t res;
2334
2335 res = a - b;
2336 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2337 if (a & 0x80)
2338 res = 0x80;
2339 else
2340 res = 0x7f;
2341 }
2342 return res;
2343}
2344
2345#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2346#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2347#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2348#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2349#define PFX q
2350
2351#include "op_addsub.h"
2352
2353/* Unsigned saturating arithmetic. */
460a09c1 2354static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2355{
2356 uint16_t res;
2357 res = a + b;
2358 if (res < a)
2359 res = 0xffff;
2360 return res;
2361}
2362
460a09c1 2363static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2364{
4c4fd3f8 2365 if (a > b)
6ddbc6e4
PB		 2366 return a - b;
2367 else
2368 return 0;
2369}
2370
2371static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2372{
2373 uint8_t res;
2374 res = a + b;
2375 if (res < a)
2376 res = 0xff;
2377 return res;
2378}
2379
2380static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2381{
4c4fd3f8 2382 if (a > b)
6ddbc6e4
PB		 2383 return a - b;
2384 else
2385 return 0;
2386}
2387
2388#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2389#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2390#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2391#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2392#define PFX uq
2393
2394#include "op_addsub.h"
2395
2396/* Signed modulo arithmetic. */
2397#define SARITH16(a, b, n, op) do { \
2398 int32_t sum; \
db6e2e65 2399 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2400 RESULT(sum, n, 16); \
2401 if (sum >= 0) \
2402 ge |= 3 << (n * 2); \
2403 } while(0)
2404
2405#define SARITH8(a, b, n, op) do { \
2406 int32_t sum; \
db6e2e65 2407 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2408 RESULT(sum, n, 8); \
2409 if (sum >= 0) \
2410 ge |= 1 << n; \
2411 } while(0)
2412
2413
2414#define ADD16(a, b, n) SARITH16(a, b, n, +)
2415#define SUB16(a, b, n) SARITH16(a, b, n, -)
2416#define ADD8(a, b, n) SARITH8(a, b, n, +)
2417#define SUB8(a, b, n) SARITH8(a, b, n, -)
2418#define PFX s
2419#define ARITH_GE
2420
2421#include "op_addsub.h"
2422
2423/* Unsigned modulo arithmetic. */
2424#define ADD16(a, b, n) do { \
2425 uint32_t sum; \
2426 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2427 RESULT(sum, n, 16); \
a87aa10b 2428 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2429 ge |= 3 << (n * 2); \
2430 } while(0)
2431
2432#define ADD8(a, b, n) do { \
2433 uint32_t sum; \
2434 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2435 RESULT(sum, n, 8); \
a87aa10b
AZ		 2436 if ((sum >> 8) == 1) \
2437 ge |= 1 << n; \
6ddbc6e4
PB		 2438 } while(0)
2439
2440#define SUB16(a, b, n) do { \
2441 uint32_t sum; \
2442 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2443 RESULT(sum, n, 16); \
2444 if ((sum >> 16) == 0) \
2445 ge |= 3 << (n * 2); \
2446 } while(0)
2447
2448#define SUB8(a, b, n) do { \
2449 uint32_t sum; \
2450 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2451 RESULT(sum, n, 8); \
2452 if ((sum >> 8) == 0) \
a87aa10b 2453 ge |= 1 << n; \
6ddbc6e4
PB		 2454 } while(0)
2455
2456#define PFX u
2457#define ARITH_GE
2458
2459#include "op_addsub.h"
2460
2461/* Halved signed arithmetic. */
2462#define ADD16(a, b, n) \
2463 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2464#define SUB16(a, b, n) \
2465 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2466#define ADD8(a, b, n) \
2467 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2468#define SUB8(a, b, n) \
2469 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2470#define PFX sh
2471
2472#include "op_addsub.h"
2473
2474/* Halved unsigned arithmetic. */
2475#define ADD16(a, b, n) \
2476 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2477#define SUB16(a, b, n) \
2478 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2479#define ADD8(a, b, n) \
2480 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2481#define SUB8(a, b, n) \
2482 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2483#define PFX uh
2484
2485#include "op_addsub.h"
2486
2487static inline uint8_t do_usad(uint8_t a, uint8_t b)
2488{
2489 if (a > b)
2490 return a - b;
2491 else
2492 return b - a;
2493}
2494
2495/* Unsigned sum of absolute byte differences. */
2496uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2497{
2498 uint32_t sum;
2499 sum = do_usad(a, b);
2500 sum += do_usad(a >> 8, b >> 8);
2501 sum += do_usad(a >> 16, b >>16);
2502 sum += do_usad(a >> 24, b >> 24);
2503 return sum;
2504}
2505
2506/* For ARMv6 SEL instruction. */
2507uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2508{
2509 uint32_t mask;
2510
2511 mask = 0;
2512 if (flags & 1)
2513 mask |= 0xff;
2514 if (flags & 2)
2515 mask |= 0xff00;
2516 if (flags & 4)
2517 mask |= 0xff0000;
2518 if (flags & 8)
2519 mask |= 0xff000000;
2520 return (a & mask) | (b & ~mask);
2521}
2522
5e3f878a
PB		 2523uint32_t HELPER(logicq_cc)(uint64_t val)
2524{
2525 return (val >> 32) | (val != 0);
2526}
4373f3ce
PB		 2527
2528/* VFP support. We follow the convention used for VFP instrunctions:
2529 Single precition routines have a "s" suffix, double precision a
2530 "d" suffix. */
2531
2532/* Convert host exception flags to vfp form. */
2533static inline int vfp_exceptbits_from_host(int host_bits)
2534{
2535 int target_bits = 0;
2536
2537 if (host_bits & float_flag_invalid)
2538 target_bits |= 1;
2539 if (host_bits & float_flag_divbyzero)
2540 target_bits |= 2;
2541 if (host_bits & float_flag_overflow)
2542 target_bits |= 4;
36802b6b 2543 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2544 target_bits |= 8;
2545 if (host_bits & float_flag_inexact)
2546 target_bits |= 0x10;
cecd8504
PM		 2547 if (host_bits & float_flag_input_denormal)
2548 target_bits |= 0x80;
4373f3ce
PB		 2549 return target_bits;
2550}
2551
0ecb72a5 2552uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2553{
2554 int i;
2555 uint32_t fpscr;
2556
2557 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2558 | (env->vfp.vec_len << 16)
2559 | (env->vfp.vec_stride << 20);
2560 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2561 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2562 fpscr |= vfp_exceptbits_from_host(i);
2563 return fpscr;
2564}
2565
0ecb72a5 2566uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2567{
2568 return HELPER(vfp_get_fpscr)(env);
2569}
2570
4373f3ce
PB		 2571/* Convert vfp exception flags to target form. */
2572static inline int vfp_exceptbits_to_host(int target_bits)
2573{
2574 int host_bits = 0;
2575
2576 if (target_bits & 1)
2577 host_bits |= float_flag_invalid;
2578 if (target_bits & 2)
2579 host_bits |= float_flag_divbyzero;
2580 if (target_bits & 4)
2581 host_bits |= float_flag_overflow;
2582 if (target_bits & 8)
2583 host_bits |= float_flag_underflow;
2584 if (target_bits & 0x10)
2585 host_bits |= float_flag_inexact;
cecd8504
PM		 2586 if (target_bits & 0x80)
2587 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2588 return host_bits;
2589}
2590
0ecb72a5 2591void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2592{
2593 int i;
2594 uint32_t changed;
2595
2596 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2597 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2598 env->vfp.vec_len = (val >> 16) & 7;
2599 env->vfp.vec_stride = (val >> 20) & 3;
2600
2601 changed ^= val;
2602 if (changed & (3 << 22)) {
2603 i = (val >> 22) & 3;
2604 switch (i) {
2605 case 0:
2606 i = float_round_nearest_even;
2607 break;
2608 case 1:
2609 i = float_round_up;
2610 break;
2611 case 2:
2612 i = float_round_down;
2613 break;
2614 case 3:
2615 i = float_round_to_zero;
2616 break;
2617 }
2618 set_float_rounding_mode(i, &env->vfp.fp_status);
2619 }
cecd8504 2620 if (changed & (1 << 24)) {
fe76d976 2621 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2622 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2623 }
5c7908ed
PB		 2624 if (changed & (1 << 25))
2625 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2626
b12c390b 2627 i = vfp_exceptbits_to_host(val);
4373f3ce 2628 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2629 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2630}
2631
0ecb72a5 2632void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 2633{
2634 HELPER(vfp_set_fpscr)(env, val);
2635}
2636
4373f3ce
PB		 2637#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2638
2639#define VFP_BINOP(name) \
ae1857ec 2640float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2641{ \
ae1857ec
PM		 2642 float_status *fpst = fpstp; \
2643 return float32_ ## name(a, b, fpst); \
4373f3ce 2644} \
ae1857ec 2645float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2646{ \
ae1857ec
PM		 2647 float_status *fpst = fpstp; \
2648 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2649}
2650VFP_BINOP(add)
2651VFP_BINOP(sub)
2652VFP_BINOP(mul)
2653VFP_BINOP(div)
2654#undef VFP_BINOP
2655
2656float32 VFP_HELPER(neg, s)(float32 a)
2657{
2658 return float32_chs(a);
2659}
2660
2661float64 VFP_HELPER(neg, d)(float64 a)
2662{
66230e0d 2663 return float64_chs(a);
4373f3ce
PB		 2664}
2665
2666float32 VFP_HELPER(abs, s)(float32 a)
2667{
2668 return float32_abs(a);
2669}
2670
2671float64 VFP_HELPER(abs, d)(float64 a)
2672{
66230e0d 2673 return float64_abs(a);
4373f3ce
PB		 2674}
2675
0ecb72a5 2676float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 2677{
2678 return float32_sqrt(a, &env->vfp.fp_status);
2679}
2680
0ecb72a5 2681float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 2682{
2683 return float64_sqrt(a, &env->vfp.fp_status);
2684}
2685
2686/* XXX: check quiet/signaling case */
2687#define DO_VFP_cmp(p, type) \
0ecb72a5 2688void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2689{ \
2690 uint32_t flags; \
2691 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2692 case 0: flags = 0x6; break; \
2693 case -1: flags = 0x8; break; \
2694 case 1: flags = 0x2; break; \
2695 default: case 2: flags = 0x3; break; \
2696 } \
2697 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2698 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2699} \
0ecb72a5 2700void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2701{ \
2702 uint32_t flags; \
2703 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2704 case 0: flags = 0x6; break; \
2705 case -1: flags = 0x8; break; \
2706 case 1: flags = 0x2; break; \
2707 default: case 2: flags = 0x3; break; \
2708 } \
2709 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2710 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2711}
2712DO_VFP_cmp(s, float32)
2713DO_VFP_cmp(d, float64)
2714#undef DO_VFP_cmp
2715
5500b06c 2716/* Integer to float and float to integer conversions */
4373f3ce 2717
5500b06c
PM		 2718#define CONV_ITOF(name, fsz, sign) \
2719 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2720{ \
2721 float_status *fpst = fpstp; \
85836979 2722 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 2723}
2724
5500b06c
PM		 2725#define CONV_FTOI(name, fsz, sign, round) \
2726uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2727{ \
2728 float_status *fpst = fpstp; \
2729 if (float##fsz##_is_any_nan(x)) { \
2730 float_raise(float_flag_invalid, fpst); \
2731 return 0; \
2732 } \
2733 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2734}
2735
5500b06c
PM		 2736#define FLOAT_CONVS(name, p, fsz, sign) \
2737CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2738CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2739CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2740
5500b06c
PM		 2741FLOAT_CONVS(si, s, 32, )
2742FLOAT_CONVS(si, d, 64, )
2743FLOAT_CONVS(ui, s, 32, u)
2744FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2745
5500b06c
PM		 2746#undef CONV_ITOF
2747#undef CONV_FTOI
2748#undef FLOAT_CONVS
4373f3ce
PB		 2749
2750/* floating point conversion */
0ecb72a5 2751float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 2752{
2d627737
PM		 2753 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2754 /* ARM requires that S<->D conversion of any kind of NaN generates
2755 * a quiet NaN by forcing the most significant frac bit to 1.
2756 */
2757 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2758}
2759
0ecb72a5 2760float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 2761{
2d627737
PM		 2762 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2763 /* ARM requires that S<->D conversion of any kind of NaN generates
2764 * a quiet NaN by forcing the most significant frac bit to 1.
2765 */
2766 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2767}
2768
2769/* VFP3 fixed point conversion. */
622465e1 2770#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2771float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2772 void *fpstp) \
4373f3ce 2773{ \
5500b06c 2774 float_status *fpst = fpstp; \
622465e1 2775 float##fsz tmp; \
5500b06c
PM		 2776 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2777 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2778} \
5500b06c
PM		 2779uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2780 void *fpstp) \
4373f3ce 2781{ \
5500b06c 2782 float_status *fpst = fpstp; \
622465e1
PM		 2783 float##fsz tmp; \
2784 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2785 float_raise(float_flag_invalid, fpst); \
622465e1 2786 return 0; \
09d9487f 2787 } \
5500b06c
PM		 2788 tmp = float##fsz##_scalbn(x, shift, fpst); \
2789 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2790}
2791
2792VFP_CONV_FIX(sh, d, 64, int16, )
2793VFP_CONV_FIX(sl, d, 64, int32, )
2794VFP_CONV_FIX(uh, d, 64, uint16, u)
2795VFP_CONV_FIX(ul, d, 64, uint32, u)
2796VFP_CONV_FIX(sh, s, 32, int16, )
2797VFP_CONV_FIX(sl, s, 32, int32, )
2798VFP_CONV_FIX(uh, s, 32, uint16, u)
2799VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2800#undef VFP_CONV_FIX
2801
60011498 2802/* Half precision conversions. */
0ecb72a5 2803static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 2804{
60011498 2805 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2806 float32 r = float16_to_float32(make_float16(a), ieee, s);
2807 if (ieee) {
2808 return float32_maybe_silence_nan(r);
2809 }
2810 return r;
60011498
PB		 2811}
2812
0ecb72a5 2813static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 2814{
60011498 2815 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2816 float16 r = float32_to_float16(a, ieee, s);
2817 if (ieee) {
2818 r = float16_maybe_silence_nan(r);
2819 }
2820 return float16_val(r);
60011498
PB		 2821}
2822
0ecb72a5 2823float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2824{
2825 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2826}
2827
0ecb72a5 2828uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2829{
2830 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2831}
2832
0ecb72a5 2833float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2834{
2835 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2836}
2837
0ecb72a5 2838uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2839{
2840 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2841}
2842
dda3ec49 2843#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2844#define float32_three make_float32(0x40400000)
2845#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2846
0ecb72a5 2847float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2848{
dda3ec49
PM		 2849 float_status *s = &env->vfp.standard_fp_status;
2850 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2851 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2852 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2853 float_raise(float_flag_input_denormal, s);
2854 }
dda3ec49
PM		 2855 return float32_two;
2856 }
2857 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2858}
2859
0ecb72a5 2860float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2861{
71826966 2862 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2863 float32 product;
2864 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2865 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2866 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2867 float_raise(float_flag_input_denormal, s);
2868 }
6aae3df1 2869 return float32_one_point_five;
9ea62f57 2870 }
6aae3df1
PM		 2871 product = float32_mul(a, b, s);
2872 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2873}
2874
8f8e3aa4
PB		 2875/* NEON helpers. */
2876
56bf4fe2
CL		 2877/* Constants 256 and 512 are used in some helpers; we avoid relying on
2878 * int->float conversions at run-time. */
2879#define float64_256 make_float64(0x4070000000000000LL)
2880#define float64_512 make_float64(0x4080000000000000LL)
2881
fe0e4872
CL		 2882/* The algorithm that must be used to calculate the estimate
2883 * is specified by the ARM ARM.
2884 */
0ecb72a5 2885static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 2886{
1146a817
PM		 2887 /* These calculations mustn't set any fp exception flags,
2888 * so we use a local copy of the fp_status.
2889 */
2890 float_status dummy_status = env->vfp.standard_fp_status;
2891 float_status *s = &dummy_status;
fe0e4872
CL		 2892 /* q = (int)(a * 512.0) */
2893 float64 q = float64_mul(float64_512, a, s);
2894 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2895
2896 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2897 q = int64_to_float64(q_int, s);
2898 q = float64_add(q, float64_half, s);
2899 q = float64_div(q, float64_512, s);
2900 q = float64_div(float64_one, q, s);
2901
2902 /* s = (int)(256.0 * r + 0.5) */
2903 q = float64_mul(q, float64_256, s);
2904 q = float64_add(q, float64_half, s);
2905 q_int = float64_to_int64_round_to_zero(q, s);
2906
2907 /* return (double)s / 256.0 */
2908 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2909}
2910
0ecb72a5 2911float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 2912{
fe0e4872
CL		 2913 float_status *s = &env->vfp.standard_fp_status;
2914 float64 f64;
2915 uint32_t val32 = float32_val(a);
2916
2917 int result_exp;
2918 int a_exp = (val32 & 0x7f800000) >> 23;
2919 int sign = val32 & 0x80000000;
2920
2921 if (float32_is_any_nan(a)) {
2922 if (float32_is_signaling_nan(a)) {
2923 float_raise(float_flag_invalid, s);
2924 }
2925 return float32_default_nan;
2926 } else if (float32_is_infinity(a)) {
2927 return float32_set_sign(float32_zero, float32_is_neg(a));
2928 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2929 if (!float32_is_zero(a)) {
2930 float_raise(float_flag_input_denormal, s);
2931 }
fe0e4872
CL		 2932 float_raise(float_flag_divbyzero, s);
2933 return float32_set_sign(float32_infinity, float32_is_neg(a));
2934 } else if (a_exp >= 253) {
2935 float_raise(float_flag_underflow, s);
2936 return float32_set_sign(float32_zero, float32_is_neg(a));
2937 }
2938
2939 f64 = make_float64((0x3feULL << 52)
2940 | ((int64_t)(val32 & 0x7fffff) << 29));
2941
2942 result_exp = 253 - a_exp;
2943
2944 f64 = recip_estimate(f64, env);
2945
2946 val32 = sign
2947 | ((result_exp & 0xff) << 23)
2948 | ((float64_val(f64) >> 29) & 0x7fffff);
2949 return make_float32(val32);
4373f3ce
PB		 2950}
2951
e07be5d2
CL		 2952/* The algorithm that must be used to calculate the estimate
2953 * is specified by the ARM ARM.
2954 */
0ecb72a5 2955static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 2956{
1146a817
PM		 2957 /* These calculations mustn't set any fp exception flags,
2958 * so we use a local copy of the fp_status.
2959 */
2960 float_status dummy_status = env->vfp.standard_fp_status;
2961 float_status *s = &dummy_status;
e07be5d2
CL		 2962 float64 q;
2963 int64_t q_int;
2964
2965 if (float64_lt(a, float64_half, s)) {
2966 /* range 0.25 <= a < 0.5 */
2967
2968 /* a in units of 1/512 rounded down */
2969 /* q0 = (int)(a * 512.0); */
2970 q = float64_mul(float64_512, a, s);
2971 q_int = float64_to_int64_round_to_zero(q, s);
2972
2973 /* reciprocal root r */
2974 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2975 q = int64_to_float64(q_int, s);
2976 q = float64_add(q, float64_half, s);
2977 q = float64_div(q, float64_512, s);
2978 q = float64_sqrt(q, s);
2979 q = float64_div(float64_one, q, s);
2980 } else {
2981 /* range 0.5 <= a < 1.0 */
2982
2983 /* a in units of 1/256 rounded down */
2984 /* q1 = (int)(a * 256.0); */
2985 q = float64_mul(float64_256, a, s);
2986 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2987
2988 /* reciprocal root r */
2989 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
2990 q = int64_to_float64(q_int, s);
2991 q = float64_add(q, float64_half, s);
2992 q = float64_div(q, float64_256, s);
2993 q = float64_sqrt(q, s);
2994 q = float64_div(float64_one, q, s);
2995 }
2996 /* r in units of 1/256 rounded to nearest */
2997 /* s = (int)(256.0 * r + 0.5); */
2998
2999 q = float64_mul(q, float64_256,s );
3000 q = float64_add(q, float64_half, s);
3001 q_int = float64_to_int64_round_to_zero(q, s);
3002
3003 /* return (double)s / 256.0;*/
3004 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3005}
3006
0ecb72a5 3007float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3008{
e07be5d2
CL		 3009 float_status *s = &env->vfp.standard_fp_status;
3010 int result_exp;
3011 float64 f64;
3012 uint32_t val;
3013 uint64_t val64;
3014
3015 val = float32_val(a);
3016
3017 if (float32_is_any_nan(a)) {
3018 if (float32_is_signaling_nan(a)) {
3019 float_raise(float_flag_invalid, s);
3020 }
3021 return float32_default_nan;
3022 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3023 if (!float32_is_zero(a)) {
3024 float_raise(float_flag_input_denormal, s);
3025 }
e07be5d2
CL		 3026 float_raise(float_flag_divbyzero, s);
3027 return float32_set_sign(float32_infinity, float32_is_neg(a));
3028 } else if (float32_is_neg(a)) {
3029 float_raise(float_flag_invalid, s);
3030 return float32_default_nan;
3031 } else if (float32_is_infinity(a)) {
3032 return float32_zero;
3033 }
3034
3035 /* Normalize to a double-precision value between 0.25 and 1.0,
3036 * preserving the parity of the exponent. */
3037 if ((val & 0x800000) == 0) {
3038 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3039 | (0x3feULL << 52)
3040 | ((uint64_t)(val & 0x7fffff) << 29));
3041 } else {
3042 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3043 | (0x3fdULL << 52)
3044 | ((uint64_t)(val & 0x7fffff) << 29));
3045 }
3046
3047 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3048
3049 f64 = recip_sqrt_estimate(f64, env);
3050
3051 val64 = float64_val(f64);
3052
26cc6abf 3053 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3054 | ((val64 >> 29) & 0x7fffff);
3055 return make_float32(val);
4373f3ce
PB		 3056}
3057
0ecb72a5 3058uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3059{
fe0e4872
CL		 3060 float64 f64;
3061
3062 if ((a & 0x80000000) == 0) {
3063 return 0xffffffff;
3064 }
3065
3066 f64 = make_float64((0x3feULL << 52)
3067 | ((int64_t)(a & 0x7fffffff) << 21));
3068
3069 f64 = recip_estimate (f64, env);
3070
3071 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3072}
3073
0ecb72a5 3074uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3075{
e07be5d2
CL		 3076 float64 f64;
3077
3078 if ((a & 0xc0000000) == 0) {
3079 return 0xffffffff;
3080 }
3081
3082 if (a & 0x80000000) {
3083 f64 = make_float64((0x3feULL << 52)
3084 | ((uint64_t)(a & 0x7fffffff) << 21));
3085 } else { /* bits 31-30 == '01' */
3086 f64 = make_float64((0x3fdULL << 52)
3087 | ((uint64_t)(a & 0x3fffffff) << 22));
3088 }
3089
3090 f64 = recip_sqrt_estimate(f64, env);
3091
3092 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3093}
fe1479c3 3094
da97f52c
PM		 3095/* VFPv4 fused multiply-accumulate */
3096float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3097{
3098 float_status *fpst = fpstp;
3099 return float32_muladd(a, b, c, 0, fpst);
3100}
3101
3102float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3103{
3104 float_status *fpst = fpstp;
3105 return float64_muladd(a, b, c, 0, fpst);
3106}
Qemu copy for testing