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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1122cc78 | 33 | #include <asm/hypervisor.h> |
1353ebb4 | 34 | |
1592edce | 35 | static void __init spectre_v1_select_mitigation(void); |
da285121 | 36 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 37 | static void __init ssb_select_mitigation(void); |
05516ad8 | 38 | static void __init l1tf_select_mitigation(void); |
fc5ee888 | 39 | static void __init mds_select_mitigation(void); |
da285121 | 40 | |
7011f443 JK |
41 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
42 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 43 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 44 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 45 | |
d0c3bedd KRW |
46 | /* |
47 | * The vendor and possibly platform specific bits which can be modified in | |
48 | * x86_spec_ctrl_base. | |
49 | */ | |
e5f984ed | 50 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 51 | |
c37b94dd KRW |
52 | /* |
53 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 54 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
55 | */ |
56 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 57 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 58 | |
8edb388f | 59 | /* Control conditional STIBP in switch_to() */ |
6cd930f0 | 60 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
58b2d4c8 TG |
61 | /* Control conditional IBPB in switch_mm() */ |
62 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
63 | /* Control unconditional IBPB in switch_mm() */ | |
64 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
6cd930f0 | 65 | |
5ab15133 TG |
66 | /* Control MDS CPU buffer clear before returning to user space */ |
67 | DEFINE_STATIC_KEY_FALSE(mds_user_clear); | |
abf9852b | 68 | EXPORT_SYMBOL_GPL(mds_user_clear); |
f3eb8f09 TG |
69 | /* Control MDS CPU buffer clear before idling (halt, mwait) */ |
70 | DEFINE_STATIC_KEY_FALSE(mds_idle_clear); | |
71 | EXPORT_SYMBOL_GPL(mds_idle_clear); | |
5ab15133 | 72 | |
1353ebb4 JF |
73 | void __init check_bugs(void) |
74 | { | |
75 | identify_boot_cpu(); | |
55a36b65 | 76 | |
483ec3c6 TG |
77 | /* |
78 | * identify_boot_cpu() initialized SMT support information, let the | |
79 | * core code know. | |
80 | */ | |
ade31b9e | 81 | cpu_smt_check_topology_early(); |
483ec3c6 | 82 | |
62a67e12 BP |
83 | if (!IS_ENABLED(CONFIG_SMP)) { |
84 | pr_info("CPU: "); | |
85 | print_cpu_info(&boot_cpu_data); | |
86 | } | |
87 | ||
296b454a KRW |
88 | /* |
89 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
90 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
91 | * init code as it is not enumerated and depends on the family. | |
296b454a | 92 | */ |
50f9b919 | 93 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
94 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
95 | ||
e5f984ed TG |
96 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
97 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
98 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
99 | ||
1592edce JP |
100 | /* Select the proper CPU mitigations before patching alternatives: */ |
101 | spectre_v1_select_mitigation(); | |
da285121 | 102 | spectre_v2_select_mitigation(); |
e63490c8 | 103 | ssb_select_mitigation(); |
05516ad8 | 104 | l1tf_select_mitigation(); |
fc5ee888 TG |
105 | mds_select_mitigation(); |
106 | ||
15ff73d9 JP |
107 | arch_smt_update(); |
108 | ||
62a67e12 | 109 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
110 | /* |
111 | * Check whether we are able to run this kernel safely on SMP. | |
112 | * | |
113 | * - i386 is no longer supported. | |
114 | * - In order to run on anything without a TSC, we need to be | |
115 | * compiled for a i486. | |
116 | */ | |
117 | if (boot_cpu_data.x86 < 4) | |
118 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
119 | ||
bfe4bb15 MV |
120 | init_utsname()->machine[1] = |
121 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 122 | alternative_instructions(); |
304bceda | 123 | |
4d164092 | 124 | fpu__init_check_bugs(); |
62a67e12 BP |
125 | #else /* CONFIG_X86_64 */ |
126 | alternative_instructions(); | |
127 | ||
128 | /* | |
129 | * Make sure the first 2MB area is not mapped by huge pages | |
130 | * There are typically fixed size MTRRs in there and overlapping | |
131 | * MTRRs into large pages causes slow downs. | |
132 | * | |
133 | * Right now we don't do that with gbpages because there seems | |
134 | * very little benefit for that case. | |
135 | */ | |
136 | if (!direct_gbpages) | |
137 | set_memory_4k((unsigned long)__va(0), 1); | |
138 | #endif | |
1353ebb4 | 139 | } |
61dc0f55 | 140 | |
12376b62 BP |
141 | void |
142 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 143 | { |
e5f984ed | 144 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 145 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 146 | |
50f9b919 | 147 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 148 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
149 | /* |
150 | * Restrict guest_spec_ctrl to supported values. Clear the | |
151 | * modifiable bits in the host base value and or the | |
152 | * modifiable bits from the guest value. | |
153 | */ | |
154 | guestval = hostval & ~x86_spec_ctrl_mask; | |
155 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
156 | ||
12376b62 | 157 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
158 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
159 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 160 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 161 | |
e0b04783 TC |
162 | /* Conditional STIBP enabled? */ |
163 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
164 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
165 | ||
e5f984ed TG |
166 | if (hostval != guestval) { |
167 | msrval = setguest ? guestval : hostval; | |
168 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
169 | } |
170 | } | |
1238ed31 TG |
171 | |
172 | /* | |
173 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
174 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
175 | */ | |
176 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
177 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
178 | return; | |
179 | ||
180 | /* | |
181 | * If the host has SSBD mitigation enabled, force it in the host's | |
182 | * virtual MSR value. If its not permanently enabled, evaluate | |
183 | * current's TIF_SSBD thread flag. | |
184 | */ | |
185 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
186 | hostval = SPEC_CTRL_SSBD; | |
187 | else | |
188 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
189 | ||
190 | /* Sanitize the guest value */ | |
191 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
192 | ||
193 | if (hostval != guestval) { | |
194 | unsigned long tif; | |
195 | ||
196 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
197 | ssbd_spec_ctrl_to_tif(hostval); | |
198 | ||
8fce7184 | 199 | speculation_ctrl_update(tif); |
1238ed31 | 200 | } |
19fff03f | 201 | } |
12376b62 | 202 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 203 | |
8fe36c9d | 204 | static void x86_amd_ssb_disable(void) |
c37b94dd | 205 | { |
8fe36c9d | 206 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 207 | |
65e02bbd TL |
208 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
209 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
210 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
211 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
212 | } | |
213 | ||
fc5ee888 TG |
214 | #undef pr_fmt |
215 | #define pr_fmt(fmt) "MDS: " fmt | |
216 | ||
64adee4f | 217 | /* Default mitigation for MDS-affected CPUs */ |
fc5ee888 | 218 | static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL; |
e2f3c337 | 219 | static bool mds_nosmt __ro_after_init = false; |
fc5ee888 TG |
220 | |
221 | static const char * const mds_strings[] = { | |
222 | [MDS_MITIGATION_OFF] = "Vulnerable", | |
ebf1e8cb TG |
223 | [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", |
224 | [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", | |
fc5ee888 TG |
225 | }; |
226 | ||
c7ed1048 | 227 | static void __init mds_select_mitigation(void) |
fc5ee888 | 228 | { |
7781f6db | 229 | if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { |
fc5ee888 TG |
230 | mds_mitigation = MDS_MITIGATION_OFF; |
231 | return; | |
232 | } | |
233 | ||
234 | if (mds_mitigation == MDS_MITIGATION_FULL) { | |
ebf1e8cb TG |
235 | if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) |
236 | mds_mitigation = MDS_MITIGATION_VMWERV; | |
e2f3c337 | 237 | |
ebf1e8cb | 238 | static_branch_enable(&mds_user_clear); |
e2f3c337 | 239 | |
7781f6db JP |
240 | if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && |
241 | (mds_nosmt || cpu_mitigations_auto_nosmt())) | |
e2f3c337 | 242 | cpu_smt_disable(false); |
fc5ee888 | 243 | } |
e2f3c337 | 244 | |
fc5ee888 TG |
245 | pr_info("%s\n", mds_strings[mds_mitigation]); |
246 | } | |
247 | ||
248 | static int __init mds_cmdline(char *str) | |
249 | { | |
250 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
251 | return 0; | |
252 | ||
253 | if (!str) | |
254 | return -EINVAL; | |
255 | ||
256 | if (!strcmp(str, "off")) | |
257 | mds_mitigation = MDS_MITIGATION_OFF; | |
258 | else if (!strcmp(str, "full")) | |
259 | mds_mitigation = MDS_MITIGATION_FULL; | |
e2f3c337 JP |
260 | else if (!strcmp(str, "full,nosmt")) { |
261 | mds_mitigation = MDS_MITIGATION_FULL; | |
262 | mds_nosmt = true; | |
263 | } | |
fc5ee888 TG |
264 | |
265 | return 0; | |
266 | } | |
267 | early_param("mds", mds_cmdline); | |
268 | ||
1592edce JP |
269 | #undef pr_fmt |
270 | #define pr_fmt(fmt) "Spectre V1 : " fmt | |
271 | ||
272 | enum spectre_v1_mitigation { | |
273 | SPECTRE_V1_MITIGATION_NONE, | |
274 | SPECTRE_V1_MITIGATION_AUTO, | |
275 | }; | |
276 | ||
277 | static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = | |
278 | SPECTRE_V1_MITIGATION_AUTO; | |
279 | ||
280 | static const char * const spectre_v1_strings[] = { | |
281 | [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", | |
282 | [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", | |
283 | }; | |
284 | ||
1592edce JP |
285 | /* |
286 | * Does SMAP provide full mitigation against speculative kernel access to | |
287 | * userspace? | |
288 | */ | |
289 | static bool smap_works_speculatively(void) | |
290 | { | |
291 | if (!boot_cpu_has(X86_FEATURE_SMAP)) | |
292 | return false; | |
293 | ||
294 | /* | |
295 | * On CPUs which are vulnerable to Meltdown, SMAP does not | |
296 | * prevent speculative access to user data in the L1 cache. | |
297 | * Consider SMAP to be non-functional as a mitigation on these | |
298 | * CPUs. | |
299 | */ | |
300 | if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) | |
301 | return false; | |
302 | ||
303 | return true; | |
304 | } | |
305 | ||
306 | static void __init spectre_v1_select_mitigation(void) | |
307 | { | |
308 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { | |
309 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | |
310 | return; | |
311 | } | |
312 | ||
313 | if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { | |
314 | /* | |
315 | * With Spectre v1, a user can speculatively control either | |
316 | * path of a conditional swapgs with a user-controlled GS | |
317 | * value. The mitigation is to add lfences to both code paths. | |
318 | * | |
319 | * If FSGSBASE is enabled, the user can put a kernel address in | |
320 | * GS, in which case SMAP provides no protection. | |
321 | * | |
322 | * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the | |
323 | * FSGSBASE enablement patches have been merged. ] | |
324 | * | |
325 | * If FSGSBASE is disabled, the user can only put a user space | |
326 | * address in GS. That makes an attack harder, but still | |
327 | * possible if there's no SMAP protection. | |
328 | */ | |
329 | if (!smap_works_speculatively()) { | |
330 | /* | |
331 | * Mitigation can be provided from SWAPGS itself or | |
332 | * PTI as the CR3 write in the Meltdown mitigation | |
333 | * is serializing. | |
334 | * | |
3536b6c0 TG |
335 | * If neither is there, mitigate with an LFENCE to |
336 | * stop speculation through swapgs. | |
1592edce | 337 | */ |
3536b6c0 TG |
338 | if (boot_cpu_has_bug(X86_BUG_SWAPGS) && |
339 | !boot_cpu_has(X86_FEATURE_PTI)) | |
1592edce JP |
340 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); |
341 | ||
342 | /* | |
343 | * Enable lfences in the kernel entry (non-swapgs) | |
344 | * paths, to prevent user entry from speculatively | |
345 | * skipping swapgs. | |
346 | */ | |
347 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); | |
348 | } | |
349 | } | |
350 | ||
351 | pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); | |
352 | } | |
353 | ||
354 | static int __init nospectre_v1_cmdline(char *str) | |
355 | { | |
356 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | |
357 | return 0; | |
358 | } | |
359 | early_param("nospectre_v1", nospectre_v1_cmdline); | |
360 | ||
aef0bebc TG |
361 | #undef pr_fmt |
362 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
363 | ||
364 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
365 | SPECTRE_V2_NONE; | |
366 | ||
6cd930f0 TG |
367 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
368 | SPECTRE_V2_USER_NONE; | |
369 | ||
e9a556ad | 370 | #ifdef CONFIG_RETPOLINE |
bb3c2578 TG |
371 | static bool spectre_v2_bad_module; |
372 | ||
d280282b AK |
373 | bool retpoline_module_ok(bool has_retpoline) |
374 | { | |
375 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
376 | return true; | |
377 | ||
c8b8e109 | 378 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
379 | spectre_v2_bad_module = true; |
380 | return false; | |
381 | } | |
bb3c2578 TG |
382 | |
383 | static inline const char *spectre_v2_module_string(void) | |
384 | { | |
385 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
386 | } | |
387 | #else | |
388 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 389 | #endif |
da285121 | 390 | |
da285121 DW |
391 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
392 | { | |
393 | int len = strlen(opt); | |
394 | ||
395 | return len == arglen && !strncmp(arg, opt, len); | |
396 | } | |
397 | ||
aef0bebc TG |
398 | /* The kernel command line selection for spectre v2 */ |
399 | enum spectre_v2_mitigation_cmd { | |
400 | SPECTRE_V2_CMD_NONE, | |
401 | SPECTRE_V2_CMD_AUTO, | |
402 | SPECTRE_V2_CMD_FORCE, | |
403 | SPECTRE_V2_CMD_RETPOLINE, | |
404 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
405 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
406 | }; | |
407 | ||
6cd930f0 TG |
408 | enum spectre_v2_user_cmd { |
409 | SPECTRE_V2_USER_CMD_NONE, | |
410 | SPECTRE_V2_USER_CMD_AUTO, | |
411 | SPECTRE_V2_USER_CMD_FORCE, | |
2cdf6a58 | 412 | SPECTRE_V2_USER_CMD_PRCTL, |
fd1b7023 | 413 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
1c3cf627 | 414 | SPECTRE_V2_USER_CMD_SECCOMP, |
fd1b7023 | 415 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
6cd930f0 TG |
416 | }; |
417 | ||
418 | static const char * const spectre_v2_user_strings[] = { | |
fbed8eca TL |
419 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", |
420 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
421 | [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", | |
422 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", | |
423 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", | |
6cd930f0 TG |
424 | }; |
425 | ||
426 | static const struct { | |
427 | const char *option; | |
428 | enum spectre_v2_user_cmd cmd; | |
429 | bool secure; | |
430 | } v2_user_options[] __initdata = { | |
fd1b7023 TG |
431 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
432 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
433 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
434 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
435 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
436 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
437 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
6cd930f0 TG |
438 | }; |
439 | ||
440 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
441 | { | |
442 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
443 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
444 | } | |
445 | ||
446 | static enum spectre_v2_user_cmd __init | |
447 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
448 | { | |
449 | char arg[20]; | |
450 | int ret, i; | |
451 | ||
452 | switch (v2_cmd) { | |
453 | case SPECTRE_V2_CMD_NONE: | |
454 | return SPECTRE_V2_USER_CMD_NONE; | |
455 | case SPECTRE_V2_CMD_FORCE: | |
456 | return SPECTRE_V2_USER_CMD_FORCE; | |
457 | default: | |
458 | break; | |
459 | } | |
460 | ||
461 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
462 | arg, sizeof(arg)); | |
463 | if (ret < 0) | |
464 | return SPECTRE_V2_USER_CMD_AUTO; | |
465 | ||
466 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
467 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
468 | spec_v2_user_print_cond(v2_user_options[i].option, | |
469 | v2_user_options[i].secure); | |
470 | return v2_user_options[i].cmd; | |
471 | } | |
472 | } | |
473 | ||
474 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
475 | return SPECTRE_V2_USER_CMD_AUTO; | |
476 | } | |
477 | ||
478 | static void __init | |
479 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
480 | { | |
481 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
482 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
fd1b7023 | 483 | enum spectre_v2_user_cmd cmd; |
6cd930f0 TG |
484 | |
485 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
486 | return; | |
487 | ||
488 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
489 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
490 | smt_possible = false; | |
491 | ||
fd1b7023 TG |
492 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
493 | switch (cmd) { | |
6cd930f0 TG |
494 | case SPECTRE_V2_USER_CMD_NONE: |
495 | goto set_mode; | |
496 | case SPECTRE_V2_USER_CMD_FORCE: | |
497 | mode = SPECTRE_V2_USER_STRICT; | |
498 | break; | |
2cdf6a58 | 499 | case SPECTRE_V2_USER_CMD_PRCTL: |
fd1b7023 | 500 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
2cdf6a58 TG |
501 | mode = SPECTRE_V2_USER_PRCTL; |
502 | break; | |
1c3cf627 TG |
503 | case SPECTRE_V2_USER_CMD_AUTO: |
504 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
fd1b7023 | 505 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
1c3cf627 TG |
506 | if (IS_ENABLED(CONFIG_SECCOMP)) |
507 | mode = SPECTRE_V2_USER_SECCOMP; | |
508 | else | |
509 | mode = SPECTRE_V2_USER_PRCTL; | |
510 | break; | |
6cd930f0 TG |
511 | } |
512 | ||
fbed8eca TL |
513 | /* |
514 | * At this point, an STIBP mode other than "off" has been set. | |
515 | * If STIBP support is not being forced, check if STIBP always-on | |
516 | * is preferred. | |
517 | */ | |
518 | if (mode != SPECTRE_V2_USER_STRICT && | |
519 | boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) | |
520 | mode = SPECTRE_V2_USER_STRICT_PREFERRED; | |
521 | ||
6cd930f0 TG |
522 | /* Initialize Indirect Branch Prediction Barrier */ |
523 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
524 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
58b2d4c8 | 525 | |
fd1b7023 TG |
526 | switch (cmd) { |
527 | case SPECTRE_V2_USER_CMD_FORCE: | |
528 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
529 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
58b2d4c8 TG |
530 | static_branch_enable(&switch_mm_always_ibpb); |
531 | break; | |
fd1b7023 TG |
532 | case SPECTRE_V2_USER_CMD_PRCTL: |
533 | case SPECTRE_V2_USER_CMD_AUTO: | |
534 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
2cdf6a58 TG |
535 | static_branch_enable(&switch_mm_cond_ibpb); |
536 | break; | |
58b2d4c8 TG |
537 | default: |
538 | break; | |
539 | } | |
540 | ||
541 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
fd1b7023 TG |
542 | static_key_enabled(&switch_mm_always_ibpb) ? |
543 | "always-on" : "conditional"); | |
6cd930f0 TG |
544 | } |
545 | ||
8edb388f | 546 | /* If enhanced IBRS is enabled no STIBP required */ |
6cd930f0 TG |
547 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
548 | return; | |
549 | ||
2cdf6a58 | 550 | /* |
8edb388f | 551 | * If SMT is not possible or STIBP is not available clear the STIBP |
2cdf6a58 TG |
552 | * mode. |
553 | */ | |
554 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
555 | mode = SPECTRE_V2_USER_NONE; | |
6cd930f0 TG |
556 | set_mode: |
557 | spectre_v2_user = mode; | |
558 | /* Only print the STIBP mode when SMT possible */ | |
559 | if (smt_possible) | |
560 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
561 | } | |
562 | ||
0eb5928b | 563 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
564 | [SPECTRE_V2_NONE] = "Vulnerable", |
565 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
566 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
567 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
568 | }; | |
569 | ||
17c33e7c KA |
570 | static const struct { |
571 | const char *option; | |
572 | enum spectre_v2_mitigation_cmd cmd; | |
573 | bool secure; | |
5a76cb46 | 574 | } mitigation_options[] __initdata = { |
aef0bebc TG |
575 | { "off", SPECTRE_V2_CMD_NONE, false }, |
576 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
577 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
578 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
579 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
580 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
581 | }; |
582 | ||
10640103 | 583 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 584 | { |
10640103 | 585 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
586 | pr_info("%s selected on command line.\n", reason); |
587 | } | |
588 | ||
da285121 DW |
589 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
590 | { | |
aef0bebc | 591 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 592 | char arg[20]; |
17c33e7c | 593 | int ret, i; |
17c33e7c | 594 | |
2a56e210 JP |
595 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || |
596 | cpu_mitigations_off()) | |
17c33e7c | 597 | return SPECTRE_V2_CMD_NONE; |
17c33e7c | 598 | |
4e8e955a TC |
599 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
600 | if (ret < 0) | |
601 | return SPECTRE_V2_CMD_AUTO; | |
602 | ||
603 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
604 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
605 | continue; | |
606 | cmd = mitigation_options[i].cmd; | |
607 | break; | |
608 | } | |
609 | ||
610 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
611 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
612 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
613 | } |
614 | ||
17c33e7c KA |
615 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
616 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
617 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
618 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 619 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 620 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
621 | } |
622 | ||
623 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
624 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
625 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
626 | return SPECTRE_V2_CMD_AUTO; | |
627 | } | |
628 | ||
10640103 TG |
629 | spec_v2_print_cond(mitigation_options[i].option, |
630 | mitigation_options[i].secure); | |
17c33e7c | 631 | return cmd; |
da285121 DW |
632 | } |
633 | ||
634 | static void __init spectre_v2_select_mitigation(void) | |
635 | { | |
636 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
637 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
638 | ||
639 | /* | |
640 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
641 | * then nothing to do. | |
642 | */ | |
643 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
644 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
645 | return; | |
646 | ||
647 | switch (cmd) { | |
648 | case SPECTRE_V2_CMD_NONE: | |
649 | return; | |
650 | ||
651 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 652 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
653 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
654 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
655 | /* Force it so VMEXIT will restore correctly */ | |
656 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
657 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
658 | goto specv2_set_mode; | |
659 | } | |
d0f293e0 DL |
660 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
661 | goto retpoline_auto; | |
662 | break; | |
da285121 DW |
663 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
664 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
665 | goto retpoline_amd; | |
666 | break; | |
667 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
668 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
669 | goto retpoline_generic; | |
670 | break; | |
671 | case SPECTRE_V2_CMD_RETPOLINE: | |
672 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
673 | goto retpoline_auto; | |
674 | break; | |
675 | } | |
713f1b95 | 676 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
677 | return; |
678 | ||
679 | retpoline_auto: | |
680 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
681 | retpoline_amd: | |
682 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 683 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
684 | goto retpoline_generic; |
685 | } | |
51dd01b5 | 686 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
687 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
688 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
689 | } else { | |
690 | retpoline_generic: | |
51dd01b5 | 691 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
692 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
693 | } | |
694 | ||
1044fde9 | 695 | specv2_set_mode: |
da285121 DW |
696 | spectre_v2_enabled = mode; |
697 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
698 | |
699 | /* | |
14623a43 JK |
700 | * If spectre v2 protection has been enabled, unconditionally fill |
701 | * RSB during a context switch; this protects against two independent | |
702 | * issues: | |
c995efd5 | 703 | * |
14623a43 JK |
704 | * - RSB underflow (and switch to BTB) on Skylake+ |
705 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 706 | */ |
14623a43 JK |
707 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
708 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 709 | |
390b99c3 DW |
710 | /* |
711 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
712 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
713 | * speculation around firmware calls only when Enhanced IBRS isn't | |
714 | * supported. | |
715 | * | |
716 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
717 | * the user might select retpoline on the kernel command line and if | |
718 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
719 | * enable IBRS around firmware calls. | |
390b99c3 | 720 | */ |
1044fde9 | 721 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
722 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
723 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
724 | } | |
7011f443 | 725 | |
6cd930f0 TG |
726 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
727 | spectre_v2_user_select_mitigation(cmd); | |
da285121 DW |
728 | } |
729 | ||
984d266f | 730 | static void update_stibp_msr(void * __unused) |
aef0bebc | 731 | { |
984d266f | 732 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
aef0bebc TG |
733 | } |
734 | ||
984d266f TG |
735 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
736 | static void update_stibp_strict(void) | |
aef0bebc | 737 | { |
984d266f TG |
738 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
739 | ||
740 | if (sched_smt_active()) | |
741 | mask |= SPEC_CTRL_STIBP; | |
742 | ||
743 | if (mask == x86_spec_ctrl_base) | |
744 | return; | |
745 | ||
746 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
747 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
748 | x86_spec_ctrl_base = mask; | |
749 | on_each_cpu(update_stibp_msr, NULL, 1); | |
aef0bebc TG |
750 | } |
751 | ||
2cdf6a58 TG |
752 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
753 | static void update_indir_branch_cond(void) | |
754 | { | |
755 | if (sched_smt_active()) | |
756 | static_branch_enable(&switch_to_cond_stibp); | |
757 | else | |
758 | static_branch_disable(&switch_to_cond_stibp); | |
759 | } | |
760 | ||
0923e77e JP |
761 | #undef pr_fmt |
762 | #define pr_fmt(fmt) fmt | |
763 | ||
fc5ee888 TG |
764 | /* Update the static key controlling the MDS CPU buffer clear in idle */ |
765 | static void update_mds_branch_idle(void) | |
766 | { | |
767 | /* | |
c7ed1048 TH |
768 | * Enable the idle clearing if SMT is active on CPUs which are |
769 | * affected only by MSBDS and not any other MDS variant. | |
770 | * | |
771 | * The other variants cannot be mitigated when SMT is enabled, so | |
772 | * clearing the buffers on idle just to prevent the Store Buffer | |
773 | * repartitioning leak would be a window dressing exercise. | |
fc5ee888 | 774 | */ |
c7ed1048 | 775 | if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) |
fc5ee888 TG |
776 | return; |
777 | ||
778 | if (sched_smt_active()) | |
779 | static_branch_enable(&mds_idle_clear); | |
780 | else | |
781 | static_branch_disable(&mds_idle_clear); | |
782 | } | |
783 | ||
0923e77e JP |
784 | #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" |
785 | ||
aef0bebc TG |
786 | void arch_smt_update(void) |
787 | { | |
984d266f TG |
788 | /* Enhanced IBRS implies STIBP. No update required. */ |
789 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
aef0bebc TG |
790 | return; |
791 | ||
792 | mutex_lock(&spec_ctrl_mutex); | |
793 | ||
984d266f TG |
794 | switch (spectre_v2_user) { |
795 | case SPECTRE_V2_USER_NONE: | |
796 | break; | |
797 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 798 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
984d266f TG |
799 | update_stibp_strict(); |
800 | break; | |
ac40ad3b | 801 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 802 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 | 803 | update_indir_branch_cond(); |
ac40ad3b | 804 | break; |
aef0bebc | 805 | } |
984d266f | 806 | |
c7ed1048 | 807 | switch (mds_mitigation) { |
ebf1e8cb TG |
808 | case MDS_MITIGATION_FULL: |
809 | case MDS_MITIGATION_VMWERV: | |
0923e77e JP |
810 | if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) |
811 | pr_warn_once(MDS_MSG_SMT); | |
fc5ee888 | 812 | update_mds_branch_idle(); |
ebf1e8cb TG |
813 | break; |
814 | case MDS_MITIGATION_OFF: | |
815 | break; | |
816 | } | |
fc5ee888 | 817 | |
aef0bebc TG |
818 | mutex_unlock(&spec_ctrl_mutex); |
819 | } | |
820 | ||
e63490c8 KRW |
821 | #undef pr_fmt |
822 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
823 | ||
b5e6d77d | 824 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
825 | |
826 | /* The kernel command line selection */ | |
827 | enum ssb_mitigation_cmd { | |
828 | SPEC_STORE_BYPASS_CMD_NONE, | |
829 | SPEC_STORE_BYPASS_CMD_AUTO, | |
830 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 831 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 832 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
833 | }; |
834 | ||
0eb5928b | 835 | static const char * const ssb_strings[] = { |
e63490c8 | 836 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 837 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
838 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
839 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
840 | }; |
841 | ||
842 | static const struct { | |
843 | const char *option; | |
844 | enum ssb_mitigation_cmd cmd; | |
5a76cb46 | 845 | } ssb_mitigation_options[] __initdata = { |
c7416003 KC |
846 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
847 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
848 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
849 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
850 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
851 | }; |
852 | ||
853 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
854 | { | |
855 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
856 | char arg[20]; | |
857 | int ret, i; | |
858 | ||
2a56e210 JP |
859 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || |
860 | cpu_mitigations_off()) { | |
e63490c8 KRW |
861 | return SPEC_STORE_BYPASS_CMD_NONE; |
862 | } else { | |
863 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
864 | arg, sizeof(arg)); | |
865 | if (ret < 0) | |
866 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
867 | ||
868 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
869 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
870 | continue; | |
871 | ||
872 | cmd = ssb_mitigation_options[i].cmd; | |
873 | break; | |
874 | } | |
875 | ||
876 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
877 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
878 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
879 | } | |
880 | } | |
881 | ||
882 | return cmd; | |
883 | } | |
884 | ||
dbe3009d | 885 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
886 | { |
887 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
888 | enum ssb_mitigation_cmd cmd; | |
889 | ||
8fe36c9d | 890 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
891 | return mode; |
892 | ||
893 | cmd = ssb_parse_cmdline(); | |
894 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
895 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
896 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
897 | return mode; | |
898 | ||
899 | switch (cmd) { | |
900 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
901 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
902 | /* | |
903 | * Choose prctl+seccomp as the default mode if seccomp is | |
904 | * enabled. | |
905 | */ | |
906 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
907 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
908 | else | |
909 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 910 | break; |
e63490c8 KRW |
911 | case SPEC_STORE_BYPASS_CMD_ON: |
912 | mode = SPEC_STORE_BYPASS_DISABLE; | |
913 | break; | |
574dcf89 TG |
914 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
915 | mode = SPEC_STORE_BYPASS_PRCTL; | |
916 | break; | |
e63490c8 KRW |
917 | case SPEC_STORE_BYPASS_CMD_NONE: |
918 | break; | |
919 | } | |
920 | ||
23b9eab9 KRW |
921 | /* |
922 | * We have three CPU feature flags that are in play here: | |
923 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 924 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
925 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
926 | */ | |
574dcf89 | 927 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 928 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 929 | /* |
3b881627 KRW |
930 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
931 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 932 | */ |
5005c716 TL |
933 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
934 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 935 | x86_amd_ssb_disable(); |
5005c716 | 936 | } else { |
8fe36c9d | 937 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 938 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 939 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
940 | } |
941 | } | |
942 | ||
e63490c8 KRW |
943 | return mode; |
944 | } | |
945 | ||
043d480e | 946 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
947 | { |
948 | ssb_mode = __ssb_select_mitigation(); | |
949 | ||
950 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
951 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
952 | } | |
953 | ||
da285121 | 954 | #undef pr_fmt |
c7416003 | 955 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 956 | |
801d6893 | 957 | static void task_update_spec_tif(struct task_struct *tsk) |
574dcf89 | 958 | { |
801d6893 TG |
959 | /* Force the update of the real TIF bits */ |
960 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
d4595948 TG |
961 | |
962 | /* | |
963 | * Immediately update the speculation control MSRs for the current | |
964 | * task, but for a non-current task delay setting the CPU | |
965 | * mitigation until it is scheduled next. | |
966 | * | |
967 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
968 | * always the current task. | |
969 | */ | |
801d6893 | 970 | if (tsk == current) |
d4595948 TG |
971 | speculation_ctrl_update_current(); |
972 | } | |
973 | ||
974 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
975 | { | |
c7416003 KC |
976 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
977 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
978 | return -ENXIO; |
979 | ||
733f4234 TG |
980 | switch (ctrl) { |
981 | case PR_SPEC_ENABLE: | |
982 | /* If speculation is force disabled, enable is not allowed */ | |
983 | if (task_spec_ssb_force_disable(task)) | |
984 | return -EPERM; | |
985 | task_clear_spec_ssb_disable(task); | |
801d6893 | 986 | task_update_spec_tif(task); |
733f4234 TG |
987 | break; |
988 | case PR_SPEC_DISABLE: | |
989 | task_set_spec_ssb_disable(task); | |
801d6893 | 990 | task_update_spec_tif(task); |
733f4234 TG |
991 | break; |
992 | case PR_SPEC_FORCE_DISABLE: | |
993 | task_set_spec_ssb_disable(task); | |
994 | task_set_spec_ssb_force_disable(task); | |
801d6893 | 995 | task_update_spec_tif(task); |
733f4234 TG |
996 | break; |
997 | default: | |
998 | return -ERANGE; | |
999 | } | |
574dcf89 TG |
1000 | return 0; |
1001 | } | |
1002 | ||
ac40ad3b TG |
1003 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
1004 | { | |
1005 | switch (ctrl) { | |
1006 | case PR_SPEC_ENABLE: | |
1007 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
1008 | return 0; | |
1009 | /* | |
1010 | * Indirect branch speculation is always disabled in strict | |
1011 | * mode. | |
1012 | */ | |
fbed8eca TL |
1013 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
1014 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
1015 | return -EPERM; |
1016 | task_clear_spec_ib_disable(task); | |
1017 | task_update_spec_tif(task); | |
1018 | break; | |
1019 | case PR_SPEC_DISABLE: | |
1020 | case PR_SPEC_FORCE_DISABLE: | |
1021 | /* | |
1022 | * Indirect branch speculation is always allowed when | |
1023 | * mitigation is force disabled. | |
1024 | */ | |
1025 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
1026 | return -EPERM; | |
fbed8eca TL |
1027 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
1028 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
1029 | return 0; |
1030 | task_set_spec_ib_disable(task); | |
1031 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
1032 | task_set_spec_ib_force_disable(task); | |
1033 | task_update_spec_tif(task); | |
1034 | break; | |
1035 | default: | |
1036 | return -ERANGE; | |
1037 | } | |
1038 | return 0; | |
1039 | } | |
1040 | ||
5b38e244 TG |
1041 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
1042 | unsigned long ctrl) | |
1043 | { | |
1044 | switch (which) { | |
1045 | case PR_SPEC_STORE_BYPASS: | |
1046 | return ssb_prctl_set(task, ctrl); | |
ac40ad3b TG |
1047 | case PR_SPEC_INDIRECT_BRANCH: |
1048 | return ib_prctl_set(task, ctrl); | |
5b38e244 TG |
1049 | default: |
1050 | return -ENODEV; | |
1051 | } | |
1052 | } | |
1053 | ||
1054 | #ifdef CONFIG_SECCOMP | |
1055 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
1056 | { | |
c7416003 KC |
1057 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
1058 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
1c3cf627 TG |
1059 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
1060 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
1061 | } |
1062 | #endif | |
1063 | ||
199bfed2 | 1064 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
1065 | { |
1066 | switch (ssb_mode) { | |
1067 | case SPEC_STORE_BYPASS_DISABLE: | |
1068 | return PR_SPEC_DISABLE; | |
c7416003 | 1069 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 1070 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
1071 | if (task_spec_ssb_force_disable(task)) |
1072 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
1073 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
1074 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
1075 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1076 | default: | |
1077 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1078 | return PR_SPEC_ENABLE; | |
1079 | return PR_SPEC_NOT_AFFECTED; | |
1080 | } | |
1081 | } | |
1082 | ||
ac40ad3b TG |
1083 | static int ib_prctl_get(struct task_struct *task) |
1084 | { | |
1085 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
1086 | return PR_SPEC_NOT_AFFECTED; | |
1087 | ||
1088 | switch (spectre_v2_user) { | |
1089 | case SPECTRE_V2_USER_NONE: | |
1090 | return PR_SPEC_ENABLE; | |
1091 | case SPECTRE_V2_USER_PRCTL: | |
1c3cf627 | 1092 | case SPECTRE_V2_USER_SECCOMP: |
ac40ad3b TG |
1093 | if (task_spec_ib_force_disable(task)) |
1094 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
1095 | if (task_spec_ib_disable(task)) | |
1096 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
1097 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1098 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 1099 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
ac40ad3b TG |
1100 | return PR_SPEC_DISABLE; |
1101 | default: | |
1102 | return PR_SPEC_NOT_AFFECTED; | |
1103 | } | |
1104 | } | |
1105 | ||
199bfed2 | 1106 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
1107 | { |
1108 | switch (which) { | |
1109 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 1110 | return ssb_prctl_get(task); |
ac40ad3b TG |
1111 | case PR_SPEC_INDIRECT_BRANCH: |
1112 | return ib_prctl_get(task); | |
574dcf89 TG |
1113 | default: |
1114 | return -ENODEV; | |
1115 | } | |
1116 | } | |
1117 | ||
23b9eab9 KRW |
1118 | void x86_spec_ctrl_setup_ap(void) |
1119 | { | |
50f9b919 | 1120 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 1121 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
1122 | |
1123 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 1124 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
1125 | } |
1126 | ||
73ca9f47 KRW |
1127 | #undef pr_fmt |
1128 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 1129 | |
24fcb53c JK |
1130 | /* Default mitigation for L1TF-affected CPUs */ |
1131 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 1132 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c | 1133 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
47bb1124 | 1134 | #endif |
522c7bed | 1135 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd | 1136 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
b9cfedcd | 1137 | |
f1f016ed AK |
1138 | /* |
1139 | * These CPUs all support 44bits physical address space internally in the | |
1140 | * cache but CPUID can report a smaller number of physical address bits. | |
1141 | * | |
1142 | * The L1TF mitigation uses the top most address bit for the inversion of | |
1143 | * non present PTEs. When the installed memory reaches into the top most | |
1144 | * address bit due to memory holes, which has been observed on machines | |
1145 | * which report 36bits physical address bits and have 32G RAM installed, | |
1146 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
1147 | * This is a false positive because the mitigation is still possible due to | |
1148 | * the fact that the cache uses 44bit internally. Use the cache bits | |
1149 | * instead of the reported physical bits and adjust them on the affected | |
1150 | * machines to 44bit if the reported bits are less than 44. | |
1151 | */ | |
1152 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
1153 | { | |
1154 | if (c->x86 != 6) | |
1155 | return; | |
1156 | ||
1157 | switch (c->x86_model) { | |
1158 | case INTEL_FAM6_NEHALEM: | |
1159 | case INTEL_FAM6_WESTMERE: | |
1160 | case INTEL_FAM6_SANDYBRIDGE: | |
1161 | case INTEL_FAM6_IVYBRIDGE: | |
1162 | case INTEL_FAM6_HASWELL_CORE: | |
1163 | case INTEL_FAM6_HASWELL_ULT: | |
1164 | case INTEL_FAM6_HASWELL_GT3E: | |
1165 | case INTEL_FAM6_BROADWELL_CORE: | |
1166 | case INTEL_FAM6_BROADWELL_GT3E: | |
1167 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
1168 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
1169 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
1170 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
1171 | if (c->x86_cache_bits < 44) | |
1172 | c->x86_cache_bits = 44; | |
1173 | break; | |
1174 | } | |
1175 | } | |
1176 | ||
73ca9f47 KRW |
1177 | static void __init l1tf_select_mitigation(void) |
1178 | { | |
1179 | u64 half_pa; | |
1180 | ||
1181 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1182 | return; | |
1183 | ||
2a56e210 JP |
1184 | if (cpu_mitigations_off()) |
1185 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1186 | else if (cpu_mitigations_auto_nosmt()) | |
1187 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1188 | ||
f1f016ed AK |
1189 | override_cache_bits(&boot_cpu_data); |
1190 | ||
24fcb53c JK |
1191 | switch (l1tf_mitigation) { |
1192 | case L1TF_MITIGATION_OFF: | |
1193 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
1194 | case L1TF_MITIGATION_FLUSH: | |
1195 | break; | |
1196 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
1197 | case L1TF_MITIGATION_FULL: | |
1198 | cpu_smt_disable(false); | |
1199 | break; | |
1200 | case L1TF_MITIGATION_FULL_FORCE: | |
1201 | cpu_smt_disable(true); | |
1202 | break; | |
1203 | } | |
1204 | ||
73ca9f47 KRW |
1205 | #if CONFIG_PGTABLE_LEVELS == 2 |
1206 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1207 | return; | |
1208 | #endif | |
1209 | ||
73ca9f47 | 1210 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
5b9b29ca MH |
1211 | if (l1tf_mitigation != L1TF_MITIGATION_OFF && |
1212 | e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
73ca9f47 | 1213 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); |
f80e341a VB |
1214 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
1215 | half_pa); | |
1216 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
c7ed1048 | 1217 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); |
73ca9f47 KRW |
1218 | return; |
1219 | } | |
1220 | ||
1221 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1222 | } | |
24fcb53c JK |
1223 | |
1224 | static int __init l1tf_cmdline(char *str) | |
1225 | { | |
1226 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1227 | return 0; | |
1228 | ||
1229 | if (!str) | |
1230 | return -EINVAL; | |
1231 | ||
1232 | if (!strcmp(str, "off")) | |
1233 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1234 | else if (!strcmp(str, "flush,nowarn")) | |
1235 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1236 | else if (!strcmp(str, "flush")) | |
1237 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1238 | else if (!strcmp(str, "flush,nosmt")) | |
1239 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1240 | else if (!strcmp(str, "full")) | |
1241 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1242 | else if (!strcmp(str, "full,force")) | |
1243 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1244 | ||
1245 | return 0; | |
1246 | } | |
1247 | early_param("l1tf", l1tf_cmdline); | |
1248 | ||
73ca9f47 | 1249 | #undef pr_fmt |
0923e77e | 1250 | #define pr_fmt(fmt) fmt |
73ca9f47 | 1251 | |
61dc0f55 | 1252 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 1253 | |
b9cfedcd TG |
1254 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1255 | ||
1256 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 1257 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
1258 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1259 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1260 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1261 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1262 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 1263 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
1264 | }; |
1265 | ||
1266 | static ssize_t l1tf_show_state(char *buf) | |
1267 | { | |
1268 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1269 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1270 | ||
3899f7b1 PB |
1271 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1272 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 1273 | sched_smt_active())) { |
3899f7b1 PB |
1274 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1275 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 1276 | } |
3899f7b1 PB |
1277 | |
1278 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1279 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 1280 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
1281 | } |
1282 | #else | |
1283 | static ssize_t l1tf_show_state(char *buf) | |
1284 | { | |
1285 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1286 | } | |
1287 | #endif | |
1288 | ||
1122cc78 TG |
1289 | static ssize_t mds_show_state(char *buf) |
1290 | { | |
1291 | if (!hypervisor_is_type(X86_HYPER_NATIVE)) { | |
1292 | return sprintf(buf, "%s; SMT Host state unknown\n", | |
1293 | mds_strings[mds_mitigation]); | |
1294 | } | |
1295 | ||
1296 | if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { | |
1297 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
5c89a99c KRW |
1298 | (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : |
1299 | sched_smt_active() ? "mitigated" : "disabled")); | |
1122cc78 TG |
1300 | } |
1301 | ||
1302 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
1303 | sched_smt_active() ? "vulnerable" : "disabled"); | |
1304 | } | |
1305 | ||
2daa53e8 TC |
1306 | static char *stibp_state(void) |
1307 | { | |
4a8d91c8 TC |
1308 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1309 | return ""; | |
1310 | ||
6cd930f0 TG |
1311 | switch (spectre_v2_user) { |
1312 | case SPECTRE_V2_USER_NONE: | |
1313 | return ", STIBP: disabled"; | |
1314 | case SPECTRE_V2_USER_STRICT: | |
1315 | return ", STIBP: forced"; | |
fbed8eca TL |
1316 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
1317 | return ", STIBP: always-on"; | |
ac40ad3b | 1318 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 1319 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 TG |
1320 | if (static_key_enabled(&switch_to_cond_stibp)) |
1321 | return ", STIBP: conditional"; | |
6cd930f0 TG |
1322 | } |
1323 | return ""; | |
2daa53e8 TC |
1324 | } |
1325 | ||
1326 | static char *ibpb_state(void) | |
1327 | { | |
58b2d4c8 | 1328 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
2cdf6a58 | 1329 | if (static_key_enabled(&switch_mm_always_ibpb)) |
58b2d4c8 | 1330 | return ", IBPB: always-on"; |
2cdf6a58 TG |
1331 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1332 | return ", IBPB: conditional"; | |
1333 | return ", IBPB: disabled"; | |
58b2d4c8 TG |
1334 | } |
1335 | return ""; | |
2daa53e8 TC |
1336 | } |
1337 | ||
ace051d5 | 1338 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 1339 | char *buf, unsigned int bug) |
61dc0f55 | 1340 | { |
d2b8fc2d | 1341 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1342 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
1343 | |
1344 | switch (bug) { | |
1345 | case X86_BUG_CPU_MELTDOWN: | |
1346 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1347 | return sprintf(buf, "Mitigation: PTI\n"); | |
1348 | ||
1349 | break; | |
1350 | ||
1351 | case X86_BUG_SPECTRE_V1: | |
1592edce | 1352 | return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); |
d2b8fc2d KRW |
1353 | |
1354 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 1355 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 1356 | ibpb_state(), |
d2b8fc2d | 1357 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 1358 | stibp_state(), |
5e2fafd5 | 1359 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
1360 | spectre_v2_module_string()); |
1361 | ||
e63490c8 KRW |
1362 | case X86_BUG_SPEC_STORE_BYPASS: |
1363 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1364 | ||
05516ad8 AK |
1365 | case X86_BUG_L1TF: |
1366 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 1367 | return l1tf_show_state(buf); |
05516ad8 | 1368 | break; |
1122cc78 TG |
1369 | |
1370 | case X86_BUG_MDS: | |
1371 | return mds_show_state(buf); | |
1372 | ||
d2b8fc2d KRW |
1373 | default: |
1374 | break; | |
1375 | } | |
1376 | ||
61dc0f55 TG |
1377 | return sprintf(buf, "Vulnerable\n"); |
1378 | } | |
1379 | ||
d2b8fc2d KRW |
1380 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1381 | { | |
1382 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1383 | } | |
1384 | ||
713f1b95 | 1385 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1386 | { |
d2b8fc2d | 1387 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1388 | } |
1389 | ||
713f1b95 | 1390 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1391 | { |
d2b8fc2d | 1392 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1393 | } |
d7de9182 KRW |
1394 | |
1395 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1396 | { | |
1397 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1398 | } | |
05516ad8 AK |
1399 | |
1400 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1401 | { | |
1402 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1403 | } | |
1122cc78 TG |
1404 | |
1405 | ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) | |
1406 | { | |
1407 | return cpu_show_common(dev, attr, buf, X86_BUG_MDS); | |
1408 | } | |
61dc0f55 | 1409 | #endif |