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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1122cc78 | 33 | #include <asm/hypervisor.h> |
1353ebb4 | 34 | |
cceb8d48 TH |
35 | #include "cpu.h" |
36 | ||
1592edce | 37 | static void __init spectre_v1_select_mitigation(void); |
da285121 | 38 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 39 | static void __init ssb_select_mitigation(void); |
05516ad8 | 40 | static void __init l1tf_select_mitigation(void); |
fc5ee888 | 41 | static void __init mds_select_mitigation(void); |
b77e6ad0 | 42 | static void __init mds_print_mitigation(void); |
0f4086c4 | 43 | static void __init taa_select_mitigation(void); |
da285121 | 44 | |
7011f443 JK |
45 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
46 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 47 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 48 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 49 | |
d0c3bedd KRW |
50 | /* |
51 | * The vendor and possibly platform specific bits which can be modified in | |
52 | * x86_spec_ctrl_base. | |
53 | */ | |
e5f984ed | 54 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 55 | |
c37b94dd KRW |
56 | /* |
57 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 58 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
59 | */ |
60 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 61 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 62 | |
8edb388f | 63 | /* Control conditional STIBP in switch_to() */ |
6cd930f0 | 64 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
58b2d4c8 TG |
65 | /* Control conditional IBPB in switch_mm() */ |
66 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
67 | /* Control unconditional IBPB in switch_mm() */ | |
68 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
6cd930f0 | 69 | |
5ab15133 TG |
70 | /* Control MDS CPU buffer clear before returning to user space */ |
71 | DEFINE_STATIC_KEY_FALSE(mds_user_clear); | |
abf9852b | 72 | EXPORT_SYMBOL_GPL(mds_user_clear); |
f3eb8f09 TG |
73 | /* Control MDS CPU buffer clear before idling (halt, mwait) */ |
74 | DEFINE_STATIC_KEY_FALSE(mds_idle_clear); | |
75 | EXPORT_SYMBOL_GPL(mds_idle_clear); | |
5ab15133 | 76 | |
1353ebb4 JF |
77 | void __init check_bugs(void) |
78 | { | |
79 | identify_boot_cpu(); | |
55a36b65 | 80 | |
483ec3c6 TG |
81 | /* |
82 | * identify_boot_cpu() initialized SMT support information, let the | |
83 | * core code know. | |
84 | */ | |
67cd6fac | 85 | cpu_smt_check_topology(); |
483ec3c6 | 86 | |
62a67e12 BP |
87 | if (!IS_ENABLED(CONFIG_SMP)) { |
88 | pr_info("CPU: "); | |
89 | print_cpu_info(&boot_cpu_data); | |
90 | } | |
91 | ||
296b454a KRW |
92 | /* |
93 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
94 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
95 | * init code as it is not enumerated and depends on the family. | |
296b454a | 96 | */ |
50f9b919 | 97 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
98 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
99 | ||
e5f984ed TG |
100 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
101 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
102 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
103 | ||
1592edce JP |
104 | /* Select the proper CPU mitigations before patching alternatives: */ |
105 | spectre_v1_select_mitigation(); | |
da285121 | 106 | spectre_v2_select_mitigation(); |
e63490c8 | 107 | ssb_select_mitigation(); |
05516ad8 | 108 | l1tf_select_mitigation(); |
fc5ee888 | 109 | mds_select_mitigation(); |
0f4086c4 | 110 | taa_select_mitigation(); |
fc5ee888 | 111 | |
b77e6ad0 WL |
112 | /* |
113 | * As MDS and TAA mitigations are inter-related, print MDS | |
114 | * mitigation until after TAA mitigation selection is done. | |
115 | */ | |
116 | mds_print_mitigation(); | |
117 | ||
15ff73d9 JP |
118 | arch_smt_update(); |
119 | ||
62a67e12 | 120 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
121 | /* |
122 | * Check whether we are able to run this kernel safely on SMP. | |
123 | * | |
124 | * - i386 is no longer supported. | |
125 | * - In order to run on anything without a TSC, we need to be | |
126 | * compiled for a i486. | |
127 | */ | |
128 | if (boot_cpu_data.x86 < 4) | |
129 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
130 | ||
bfe4bb15 MV |
131 | init_utsname()->machine[1] = |
132 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 133 | alternative_instructions(); |
304bceda | 134 | |
4d164092 | 135 | fpu__init_check_bugs(); |
62a67e12 BP |
136 | #else /* CONFIG_X86_64 */ |
137 | alternative_instructions(); | |
138 | ||
139 | /* | |
140 | * Make sure the first 2MB area is not mapped by huge pages | |
141 | * There are typically fixed size MTRRs in there and overlapping | |
142 | * MTRRs into large pages causes slow downs. | |
143 | * | |
144 | * Right now we don't do that with gbpages because there seems | |
145 | * very little benefit for that case. | |
146 | */ | |
147 | if (!direct_gbpages) | |
148 | set_memory_4k((unsigned long)__va(0), 1); | |
149 | #endif | |
1353ebb4 | 150 | } |
61dc0f55 | 151 | |
12376b62 BP |
152 | void |
153 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 154 | { |
e5f984ed | 155 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 156 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 157 | |
50f9b919 | 158 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 159 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
160 | /* |
161 | * Restrict guest_spec_ctrl to supported values. Clear the | |
162 | * modifiable bits in the host base value and or the | |
163 | * modifiable bits from the guest value. | |
164 | */ | |
165 | guestval = hostval & ~x86_spec_ctrl_mask; | |
166 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
167 | ||
12376b62 | 168 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
169 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
170 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 171 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 172 | |
e0b04783 TC |
173 | /* Conditional STIBP enabled? */ |
174 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
175 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
176 | ||
e5f984ed TG |
177 | if (hostval != guestval) { |
178 | msrval = setguest ? guestval : hostval; | |
179 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
180 | } |
181 | } | |
1238ed31 TG |
182 | |
183 | /* | |
184 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
185 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
186 | */ | |
187 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
188 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
189 | return; | |
190 | ||
191 | /* | |
192 | * If the host has SSBD mitigation enabled, force it in the host's | |
193 | * virtual MSR value. If its not permanently enabled, evaluate | |
194 | * current's TIF_SSBD thread flag. | |
195 | */ | |
196 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
197 | hostval = SPEC_CTRL_SSBD; | |
198 | else | |
199 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
200 | ||
201 | /* Sanitize the guest value */ | |
202 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
203 | ||
204 | if (hostval != guestval) { | |
205 | unsigned long tif; | |
206 | ||
207 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
208 | ssbd_spec_ctrl_to_tif(hostval); | |
209 | ||
8fce7184 | 210 | speculation_ctrl_update(tif); |
1238ed31 | 211 | } |
19fff03f | 212 | } |
12376b62 | 213 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 214 | |
8fe36c9d | 215 | static void x86_amd_ssb_disable(void) |
c37b94dd | 216 | { |
8fe36c9d | 217 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 218 | |
65e02bbd TL |
219 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
220 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
221 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
222 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
223 | } | |
224 | ||
fc5ee888 TG |
225 | #undef pr_fmt |
226 | #define pr_fmt(fmt) "MDS: " fmt | |
227 | ||
64adee4f | 228 | /* Default mitigation for MDS-affected CPUs */ |
fc5ee888 | 229 | static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL; |
e2f3c337 | 230 | static bool mds_nosmt __ro_after_init = false; |
fc5ee888 TG |
231 | |
232 | static const char * const mds_strings[] = { | |
233 | [MDS_MITIGATION_OFF] = "Vulnerable", | |
ebf1e8cb TG |
234 | [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", |
235 | [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", | |
fc5ee888 TG |
236 | }; |
237 | ||
c7ed1048 | 238 | static void __init mds_select_mitigation(void) |
fc5ee888 | 239 | { |
7781f6db | 240 | if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { |
fc5ee888 TG |
241 | mds_mitigation = MDS_MITIGATION_OFF; |
242 | return; | |
243 | } | |
244 | ||
245 | if (mds_mitigation == MDS_MITIGATION_FULL) { | |
ebf1e8cb TG |
246 | if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) |
247 | mds_mitigation = MDS_MITIGATION_VMWERV; | |
e2f3c337 | 248 | |
ebf1e8cb | 249 | static_branch_enable(&mds_user_clear); |
e2f3c337 | 250 | |
7781f6db JP |
251 | if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && |
252 | (mds_nosmt || cpu_mitigations_auto_nosmt())) | |
e2f3c337 | 253 | cpu_smt_disable(false); |
fc5ee888 | 254 | } |
b77e6ad0 WL |
255 | } |
256 | ||
257 | static void __init mds_print_mitigation(void) | |
258 | { | |
259 | if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) | |
260 | return; | |
e2f3c337 | 261 | |
fc5ee888 TG |
262 | pr_info("%s\n", mds_strings[mds_mitigation]); |
263 | } | |
264 | ||
265 | static int __init mds_cmdline(char *str) | |
266 | { | |
267 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
268 | return 0; | |
269 | ||
270 | if (!str) | |
271 | return -EINVAL; | |
272 | ||
273 | if (!strcmp(str, "off")) | |
274 | mds_mitigation = MDS_MITIGATION_OFF; | |
275 | else if (!strcmp(str, "full")) | |
276 | mds_mitigation = MDS_MITIGATION_FULL; | |
e2f3c337 JP |
277 | else if (!strcmp(str, "full,nosmt")) { |
278 | mds_mitigation = MDS_MITIGATION_FULL; | |
279 | mds_nosmt = true; | |
280 | } | |
fc5ee888 TG |
281 | |
282 | return 0; | |
283 | } | |
284 | early_param("mds", mds_cmdline); | |
285 | ||
0f4086c4 PG |
286 | #undef pr_fmt |
287 | #define pr_fmt(fmt) "TAA: " fmt | |
288 | ||
289 | /* Default mitigation for TAA-affected CPUs */ | |
290 | static enum taa_mitigations taa_mitigation __ro_after_init = TAA_MITIGATION_VERW; | |
291 | static bool taa_nosmt __ro_after_init; | |
292 | ||
293 | static const char * const taa_strings[] = { | |
294 | [TAA_MITIGATION_OFF] = "Vulnerable", | |
295 | [TAA_MITIGATION_UCODE_NEEDED] = "Vulnerable: Clear CPU buffers attempted, no microcode", | |
296 | [TAA_MITIGATION_VERW] = "Mitigation: Clear CPU buffers", | |
297 | [TAA_MITIGATION_TSX_DISABLED] = "Mitigation: TSX disabled", | |
298 | }; | |
299 | ||
300 | static void __init taa_select_mitigation(void) | |
301 | { | |
302 | u64 ia32_cap; | |
303 | ||
304 | if (!boot_cpu_has_bug(X86_BUG_TAA)) { | |
305 | taa_mitigation = TAA_MITIGATION_OFF; | |
306 | return; | |
307 | } | |
308 | ||
309 | /* TSX previously disabled by tsx=off */ | |
310 | if (!boot_cpu_has(X86_FEATURE_RTM)) { | |
311 | taa_mitigation = TAA_MITIGATION_TSX_DISABLED; | |
312 | goto out; | |
313 | } | |
314 | ||
315 | if (cpu_mitigations_off()) { | |
316 | taa_mitigation = TAA_MITIGATION_OFF; | |
317 | return; | |
318 | } | |
319 | ||
daa83568 WL |
320 | /* |
321 | * TAA mitigation via VERW is turned off if both | |
322 | * tsx_async_abort=off and mds=off are specified. | |
323 | */ | |
324 | if (taa_mitigation == TAA_MITIGATION_OFF && | |
325 | mds_mitigation == MDS_MITIGATION_OFF) | |
0f4086c4 PG |
326 | goto out; |
327 | ||
328 | if (boot_cpu_has(X86_FEATURE_MD_CLEAR)) | |
329 | taa_mitigation = TAA_MITIGATION_VERW; | |
330 | else | |
331 | taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; | |
332 | ||
333 | /* | |
334 | * VERW doesn't clear the CPU buffers when MD_CLEAR=1 and MDS_NO=1. | |
335 | * A microcode update fixes this behavior to clear CPU buffers. It also | |
336 | * adds support for MSR_IA32_TSX_CTRL which is enumerated by the | |
337 | * ARCH_CAP_TSX_CTRL_MSR bit. | |
338 | * | |
339 | * On MDS_NO=1 CPUs if ARCH_CAP_TSX_CTRL_MSR is not set, microcode | |
340 | * update is required. | |
341 | */ | |
342 | ia32_cap = x86_read_arch_cap_msr(); | |
343 | if ( (ia32_cap & ARCH_CAP_MDS_NO) && | |
344 | !(ia32_cap & ARCH_CAP_TSX_CTRL_MSR)) | |
345 | taa_mitigation = TAA_MITIGATION_UCODE_NEEDED; | |
346 | ||
347 | /* | |
348 | * TSX is enabled, select alternate mitigation for TAA which is | |
349 | * the same as MDS. Enable MDS static branch to clear CPU buffers. | |
350 | * | |
351 | * For guests that can't determine whether the correct microcode is | |
352 | * present on host, enable the mitigation for UCODE_NEEDED as well. | |
353 | */ | |
354 | static_branch_enable(&mds_user_clear); | |
355 | ||
356 | if (taa_nosmt || cpu_mitigations_auto_nosmt()) | |
357 | cpu_smt_disable(false); | |
358 | ||
daa83568 WL |
359 | /* |
360 | * Update MDS mitigation, if necessary, as the mds_user_clear is | |
361 | * now enabled for TAA mitigation. | |
362 | */ | |
363 | if (mds_mitigation == MDS_MITIGATION_OFF && | |
364 | boot_cpu_has_bug(X86_BUG_MDS)) { | |
365 | mds_mitigation = MDS_MITIGATION_FULL; | |
366 | mds_select_mitigation(); | |
367 | } | |
0f4086c4 PG |
368 | out: |
369 | pr_info("%s\n", taa_strings[taa_mitigation]); | |
370 | } | |
371 | ||
372 | static int __init tsx_async_abort_parse_cmdline(char *str) | |
373 | { | |
374 | if (!boot_cpu_has_bug(X86_BUG_TAA)) | |
375 | return 0; | |
376 | ||
377 | if (!str) | |
378 | return -EINVAL; | |
379 | ||
380 | if (!strcmp(str, "off")) { | |
381 | taa_mitigation = TAA_MITIGATION_OFF; | |
382 | } else if (!strcmp(str, "full")) { | |
383 | taa_mitigation = TAA_MITIGATION_VERW; | |
384 | } else if (!strcmp(str, "full,nosmt")) { | |
385 | taa_mitigation = TAA_MITIGATION_VERW; | |
386 | taa_nosmt = true; | |
387 | } | |
388 | ||
389 | return 0; | |
390 | } | |
391 | early_param("tsx_async_abort", tsx_async_abort_parse_cmdline); | |
392 | ||
1592edce JP |
393 | #undef pr_fmt |
394 | #define pr_fmt(fmt) "Spectre V1 : " fmt | |
395 | ||
396 | enum spectre_v1_mitigation { | |
397 | SPECTRE_V1_MITIGATION_NONE, | |
398 | SPECTRE_V1_MITIGATION_AUTO, | |
399 | }; | |
400 | ||
401 | static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = | |
402 | SPECTRE_V1_MITIGATION_AUTO; | |
403 | ||
404 | static const char * const spectre_v1_strings[] = { | |
405 | [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", | |
406 | [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", | |
407 | }; | |
408 | ||
1592edce JP |
409 | /* |
410 | * Does SMAP provide full mitigation against speculative kernel access to | |
411 | * userspace? | |
412 | */ | |
413 | static bool smap_works_speculatively(void) | |
414 | { | |
415 | if (!boot_cpu_has(X86_FEATURE_SMAP)) | |
416 | return false; | |
417 | ||
418 | /* | |
419 | * On CPUs which are vulnerable to Meltdown, SMAP does not | |
420 | * prevent speculative access to user data in the L1 cache. | |
421 | * Consider SMAP to be non-functional as a mitigation on these | |
422 | * CPUs. | |
423 | */ | |
424 | if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) | |
425 | return false; | |
426 | ||
427 | return true; | |
428 | } | |
429 | ||
430 | static void __init spectre_v1_select_mitigation(void) | |
431 | { | |
432 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { | |
433 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | |
434 | return; | |
435 | } | |
436 | ||
437 | if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { | |
438 | /* | |
439 | * With Spectre v1, a user can speculatively control either | |
440 | * path of a conditional swapgs with a user-controlled GS | |
441 | * value. The mitigation is to add lfences to both code paths. | |
442 | * | |
443 | * If FSGSBASE is enabled, the user can put a kernel address in | |
444 | * GS, in which case SMAP provides no protection. | |
445 | * | |
446 | * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the | |
447 | * FSGSBASE enablement patches have been merged. ] | |
448 | * | |
449 | * If FSGSBASE is disabled, the user can only put a user space | |
450 | * address in GS. That makes an attack harder, but still | |
451 | * possible if there's no SMAP protection. | |
452 | */ | |
453 | if (!smap_works_speculatively()) { | |
454 | /* | |
455 | * Mitigation can be provided from SWAPGS itself or | |
456 | * PTI as the CR3 write in the Meltdown mitigation | |
457 | * is serializing. | |
458 | * | |
3536b6c0 TG |
459 | * If neither is there, mitigate with an LFENCE to |
460 | * stop speculation through swapgs. | |
1592edce | 461 | */ |
3536b6c0 TG |
462 | if (boot_cpu_has_bug(X86_BUG_SWAPGS) && |
463 | !boot_cpu_has(X86_FEATURE_PTI)) | |
1592edce JP |
464 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); |
465 | ||
466 | /* | |
467 | * Enable lfences in the kernel entry (non-swapgs) | |
468 | * paths, to prevent user entry from speculatively | |
469 | * skipping swapgs. | |
470 | */ | |
471 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); | |
472 | } | |
473 | } | |
474 | ||
475 | pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); | |
476 | } | |
477 | ||
478 | static int __init nospectre_v1_cmdline(char *str) | |
479 | { | |
480 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | |
481 | return 0; | |
482 | } | |
483 | early_param("nospectre_v1", nospectre_v1_cmdline); | |
484 | ||
aef0bebc TG |
485 | #undef pr_fmt |
486 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
487 | ||
488 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
489 | SPECTRE_V2_NONE; | |
490 | ||
6cd930f0 TG |
491 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
492 | SPECTRE_V2_USER_NONE; | |
493 | ||
e9a556ad | 494 | #ifdef CONFIG_RETPOLINE |
bb3c2578 TG |
495 | static bool spectre_v2_bad_module; |
496 | ||
d280282b AK |
497 | bool retpoline_module_ok(bool has_retpoline) |
498 | { | |
499 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
500 | return true; | |
501 | ||
c8b8e109 | 502 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
503 | spectre_v2_bad_module = true; |
504 | return false; | |
505 | } | |
bb3c2578 TG |
506 | |
507 | static inline const char *spectre_v2_module_string(void) | |
508 | { | |
509 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
510 | } | |
511 | #else | |
512 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 513 | #endif |
da285121 | 514 | |
da285121 DW |
515 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
516 | { | |
517 | int len = strlen(opt); | |
518 | ||
519 | return len == arglen && !strncmp(arg, opt, len); | |
520 | } | |
521 | ||
aef0bebc TG |
522 | /* The kernel command line selection for spectre v2 */ |
523 | enum spectre_v2_mitigation_cmd { | |
524 | SPECTRE_V2_CMD_NONE, | |
525 | SPECTRE_V2_CMD_AUTO, | |
526 | SPECTRE_V2_CMD_FORCE, | |
527 | SPECTRE_V2_CMD_RETPOLINE, | |
528 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
529 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
530 | }; | |
531 | ||
6cd930f0 TG |
532 | enum spectre_v2_user_cmd { |
533 | SPECTRE_V2_USER_CMD_NONE, | |
534 | SPECTRE_V2_USER_CMD_AUTO, | |
535 | SPECTRE_V2_USER_CMD_FORCE, | |
2cdf6a58 | 536 | SPECTRE_V2_USER_CMD_PRCTL, |
fd1b7023 | 537 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
1c3cf627 | 538 | SPECTRE_V2_USER_CMD_SECCOMP, |
fd1b7023 | 539 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
6cd930f0 TG |
540 | }; |
541 | ||
542 | static const char * const spectre_v2_user_strings[] = { | |
fbed8eca TL |
543 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", |
544 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
545 | [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", | |
546 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", | |
547 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", | |
6cd930f0 TG |
548 | }; |
549 | ||
550 | static const struct { | |
551 | const char *option; | |
552 | enum spectre_v2_user_cmd cmd; | |
553 | bool secure; | |
aedec1b9 | 554 | } v2_user_options[] __initconst = { |
fd1b7023 TG |
555 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
556 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
557 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
558 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
559 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
560 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
561 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
6cd930f0 TG |
562 | }; |
563 | ||
564 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
565 | { | |
566 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
567 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
568 | } | |
569 | ||
570 | static enum spectre_v2_user_cmd __init | |
571 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
572 | { | |
573 | char arg[20]; | |
574 | int ret, i; | |
575 | ||
576 | switch (v2_cmd) { | |
577 | case SPECTRE_V2_CMD_NONE: | |
578 | return SPECTRE_V2_USER_CMD_NONE; | |
579 | case SPECTRE_V2_CMD_FORCE: | |
580 | return SPECTRE_V2_USER_CMD_FORCE; | |
581 | default: | |
582 | break; | |
583 | } | |
584 | ||
585 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
586 | arg, sizeof(arg)); | |
587 | if (ret < 0) | |
588 | return SPECTRE_V2_USER_CMD_AUTO; | |
589 | ||
590 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
591 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
592 | spec_v2_user_print_cond(v2_user_options[i].option, | |
593 | v2_user_options[i].secure); | |
594 | return v2_user_options[i].cmd; | |
595 | } | |
596 | } | |
597 | ||
598 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
599 | return SPECTRE_V2_USER_CMD_AUTO; | |
600 | } | |
601 | ||
602 | static void __init | |
603 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
604 | { | |
605 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
606 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
fd1b7023 | 607 | enum spectre_v2_user_cmd cmd; |
6cd930f0 TG |
608 | |
609 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
610 | return; | |
611 | ||
612 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
613 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
614 | smt_possible = false; | |
615 | ||
fd1b7023 TG |
616 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
617 | switch (cmd) { | |
6cd930f0 TG |
618 | case SPECTRE_V2_USER_CMD_NONE: |
619 | goto set_mode; | |
620 | case SPECTRE_V2_USER_CMD_FORCE: | |
621 | mode = SPECTRE_V2_USER_STRICT; | |
622 | break; | |
2cdf6a58 | 623 | case SPECTRE_V2_USER_CMD_PRCTL: |
fd1b7023 | 624 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
2cdf6a58 TG |
625 | mode = SPECTRE_V2_USER_PRCTL; |
626 | break; | |
1c3cf627 TG |
627 | case SPECTRE_V2_USER_CMD_AUTO: |
628 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
fd1b7023 | 629 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
1c3cf627 TG |
630 | if (IS_ENABLED(CONFIG_SECCOMP)) |
631 | mode = SPECTRE_V2_USER_SECCOMP; | |
632 | else | |
633 | mode = SPECTRE_V2_USER_PRCTL; | |
634 | break; | |
6cd930f0 TG |
635 | } |
636 | ||
fbed8eca TL |
637 | /* |
638 | * At this point, an STIBP mode other than "off" has been set. | |
639 | * If STIBP support is not being forced, check if STIBP always-on | |
640 | * is preferred. | |
641 | */ | |
642 | if (mode != SPECTRE_V2_USER_STRICT && | |
643 | boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) | |
644 | mode = SPECTRE_V2_USER_STRICT_PREFERRED; | |
645 | ||
6cd930f0 TG |
646 | /* Initialize Indirect Branch Prediction Barrier */ |
647 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
648 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
58b2d4c8 | 649 | |
fd1b7023 TG |
650 | switch (cmd) { |
651 | case SPECTRE_V2_USER_CMD_FORCE: | |
652 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
653 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
58b2d4c8 TG |
654 | static_branch_enable(&switch_mm_always_ibpb); |
655 | break; | |
fd1b7023 TG |
656 | case SPECTRE_V2_USER_CMD_PRCTL: |
657 | case SPECTRE_V2_USER_CMD_AUTO: | |
658 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
2cdf6a58 TG |
659 | static_branch_enable(&switch_mm_cond_ibpb); |
660 | break; | |
58b2d4c8 TG |
661 | default: |
662 | break; | |
663 | } | |
664 | ||
665 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
fd1b7023 TG |
666 | static_key_enabled(&switch_mm_always_ibpb) ? |
667 | "always-on" : "conditional"); | |
6cd930f0 TG |
668 | } |
669 | ||
8edb388f | 670 | /* If enhanced IBRS is enabled no STIBP required */ |
6cd930f0 TG |
671 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
672 | return; | |
673 | ||
2cdf6a58 | 674 | /* |
8edb388f | 675 | * If SMT is not possible or STIBP is not available clear the STIBP |
2cdf6a58 TG |
676 | * mode. |
677 | */ | |
678 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
679 | mode = SPECTRE_V2_USER_NONE; | |
6cd930f0 TG |
680 | set_mode: |
681 | spectre_v2_user = mode; | |
682 | /* Only print the STIBP mode when SMT possible */ | |
683 | if (smt_possible) | |
684 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
685 | } | |
686 | ||
0eb5928b | 687 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
688 | [SPECTRE_V2_NONE] = "Vulnerable", |
689 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
690 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
691 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
692 | }; | |
693 | ||
17c33e7c KA |
694 | static const struct { |
695 | const char *option; | |
696 | enum spectre_v2_mitigation_cmd cmd; | |
697 | bool secure; | |
aedec1b9 | 698 | } mitigation_options[] __initconst = { |
aef0bebc TG |
699 | { "off", SPECTRE_V2_CMD_NONE, false }, |
700 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
701 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
702 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
703 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
704 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
705 | }; |
706 | ||
10640103 | 707 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 708 | { |
10640103 | 709 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
710 | pr_info("%s selected on command line.\n", reason); |
711 | } | |
712 | ||
da285121 DW |
713 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
714 | { | |
aef0bebc | 715 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 716 | char arg[20]; |
17c33e7c | 717 | int ret, i; |
17c33e7c | 718 | |
2a56e210 JP |
719 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || |
720 | cpu_mitigations_off()) | |
17c33e7c | 721 | return SPECTRE_V2_CMD_NONE; |
17c33e7c | 722 | |
4e8e955a TC |
723 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
724 | if (ret < 0) | |
725 | return SPECTRE_V2_CMD_AUTO; | |
726 | ||
727 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
728 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
729 | continue; | |
730 | cmd = mitigation_options[i].cmd; | |
731 | break; | |
732 | } | |
733 | ||
734 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
735 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
736 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
737 | } |
738 | ||
17c33e7c KA |
739 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
740 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
741 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
742 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 743 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 744 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
745 | } |
746 | ||
747 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
748 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
749 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
750 | return SPECTRE_V2_CMD_AUTO; | |
751 | } | |
752 | ||
10640103 TG |
753 | spec_v2_print_cond(mitigation_options[i].option, |
754 | mitigation_options[i].secure); | |
17c33e7c | 755 | return cmd; |
da285121 DW |
756 | } |
757 | ||
758 | static void __init spectre_v2_select_mitigation(void) | |
759 | { | |
760 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
761 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
762 | ||
763 | /* | |
764 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
765 | * then nothing to do. | |
766 | */ | |
767 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
768 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
769 | return; | |
770 | ||
771 | switch (cmd) { | |
772 | case SPECTRE_V2_CMD_NONE: | |
773 | return; | |
774 | ||
775 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 776 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
777 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
778 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
779 | /* Force it so VMEXIT will restore correctly */ | |
780 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
781 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
782 | goto specv2_set_mode; | |
783 | } | |
d0f293e0 DL |
784 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
785 | goto retpoline_auto; | |
786 | break; | |
da285121 DW |
787 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
788 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
789 | goto retpoline_amd; | |
790 | break; | |
791 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
792 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
793 | goto retpoline_generic; | |
794 | break; | |
795 | case SPECTRE_V2_CMD_RETPOLINE: | |
796 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
797 | goto retpoline_auto; | |
798 | break; | |
799 | } | |
713f1b95 | 800 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
801 | return; |
802 | ||
803 | retpoline_auto: | |
804 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
805 | retpoline_amd: | |
806 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 807 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
808 | goto retpoline_generic; |
809 | } | |
51dd01b5 | 810 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
811 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
812 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
813 | } else { | |
814 | retpoline_generic: | |
51dd01b5 | 815 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
816 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
817 | } | |
818 | ||
1044fde9 | 819 | specv2_set_mode: |
da285121 DW |
820 | spectre_v2_enabled = mode; |
821 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
822 | |
823 | /* | |
14623a43 JK |
824 | * If spectre v2 protection has been enabled, unconditionally fill |
825 | * RSB during a context switch; this protects against two independent | |
826 | * issues: | |
c995efd5 | 827 | * |
14623a43 JK |
828 | * - RSB underflow (and switch to BTB) on Skylake+ |
829 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 830 | */ |
14623a43 JK |
831 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
832 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 833 | |
390b99c3 DW |
834 | /* |
835 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
836 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
837 | * speculation around firmware calls only when Enhanced IBRS isn't | |
838 | * supported. | |
839 | * | |
840 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
841 | * the user might select retpoline on the kernel command line and if | |
842 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
843 | * enable IBRS around firmware calls. | |
390b99c3 | 844 | */ |
1044fde9 | 845 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
846 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
847 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
848 | } | |
7011f443 | 849 | |
6cd930f0 TG |
850 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
851 | spectre_v2_user_select_mitigation(cmd); | |
da285121 DW |
852 | } |
853 | ||
984d266f | 854 | static void update_stibp_msr(void * __unused) |
aef0bebc | 855 | { |
984d266f | 856 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
aef0bebc TG |
857 | } |
858 | ||
984d266f TG |
859 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
860 | static void update_stibp_strict(void) | |
aef0bebc | 861 | { |
984d266f TG |
862 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
863 | ||
864 | if (sched_smt_active()) | |
865 | mask |= SPEC_CTRL_STIBP; | |
866 | ||
867 | if (mask == x86_spec_ctrl_base) | |
868 | return; | |
869 | ||
870 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
871 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
872 | x86_spec_ctrl_base = mask; | |
873 | on_each_cpu(update_stibp_msr, NULL, 1); | |
aef0bebc TG |
874 | } |
875 | ||
2cdf6a58 TG |
876 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
877 | static void update_indir_branch_cond(void) | |
878 | { | |
879 | if (sched_smt_active()) | |
880 | static_branch_enable(&switch_to_cond_stibp); | |
881 | else | |
882 | static_branch_disable(&switch_to_cond_stibp); | |
883 | } | |
884 | ||
0923e77e JP |
885 | #undef pr_fmt |
886 | #define pr_fmt(fmt) fmt | |
887 | ||
fc5ee888 TG |
888 | /* Update the static key controlling the MDS CPU buffer clear in idle */ |
889 | static void update_mds_branch_idle(void) | |
890 | { | |
891 | /* | |
c7ed1048 TH |
892 | * Enable the idle clearing if SMT is active on CPUs which are |
893 | * affected only by MSBDS and not any other MDS variant. | |
894 | * | |
895 | * The other variants cannot be mitigated when SMT is enabled, so | |
896 | * clearing the buffers on idle just to prevent the Store Buffer | |
897 | * repartitioning leak would be a window dressing exercise. | |
fc5ee888 | 898 | */ |
c7ed1048 | 899 | if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) |
fc5ee888 TG |
900 | return; |
901 | ||
902 | if (sched_smt_active()) | |
903 | static_branch_enable(&mds_idle_clear); | |
904 | else | |
905 | static_branch_disable(&mds_idle_clear); | |
906 | } | |
907 | ||
0923e77e | 908 | #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" |
0f4086c4 | 909 | #define TAA_MSG_SMT "TAA CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/tsx_async_abort.html for more details.\n" |
0923e77e | 910 | |
aef0bebc TG |
911 | void arch_smt_update(void) |
912 | { | |
aef0bebc TG |
913 | mutex_lock(&spec_ctrl_mutex); |
914 | ||
984d266f TG |
915 | switch (spectre_v2_user) { |
916 | case SPECTRE_V2_USER_NONE: | |
917 | break; | |
918 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 919 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
984d266f TG |
920 | update_stibp_strict(); |
921 | break; | |
ac40ad3b | 922 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 923 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 | 924 | update_indir_branch_cond(); |
ac40ad3b | 925 | break; |
aef0bebc | 926 | } |
984d266f | 927 | |
c7ed1048 | 928 | switch (mds_mitigation) { |
ebf1e8cb TG |
929 | case MDS_MITIGATION_FULL: |
930 | case MDS_MITIGATION_VMWERV: | |
0923e77e JP |
931 | if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) |
932 | pr_warn_once(MDS_MSG_SMT); | |
fc5ee888 | 933 | update_mds_branch_idle(); |
ebf1e8cb TG |
934 | break; |
935 | case MDS_MITIGATION_OFF: | |
936 | break; | |
937 | } | |
fc5ee888 | 938 | |
0f4086c4 PG |
939 | switch (taa_mitigation) { |
940 | case TAA_MITIGATION_VERW: | |
941 | case TAA_MITIGATION_UCODE_NEEDED: | |
942 | if (sched_smt_active()) | |
943 | pr_warn_once(TAA_MSG_SMT); | |
944 | break; | |
945 | case TAA_MITIGATION_TSX_DISABLED: | |
946 | case TAA_MITIGATION_OFF: | |
947 | break; | |
948 | } | |
949 | ||
aef0bebc TG |
950 | mutex_unlock(&spec_ctrl_mutex); |
951 | } | |
952 | ||
e63490c8 KRW |
953 | #undef pr_fmt |
954 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
955 | ||
b5e6d77d | 956 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
957 | |
958 | /* The kernel command line selection */ | |
959 | enum ssb_mitigation_cmd { | |
960 | SPEC_STORE_BYPASS_CMD_NONE, | |
961 | SPEC_STORE_BYPASS_CMD_AUTO, | |
962 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 963 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 964 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
965 | }; |
966 | ||
0eb5928b | 967 | static const char * const ssb_strings[] = { |
e63490c8 | 968 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 969 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
970 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
971 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
972 | }; |
973 | ||
974 | static const struct { | |
975 | const char *option; | |
976 | enum ssb_mitigation_cmd cmd; | |
aedec1b9 | 977 | } ssb_mitigation_options[] __initconst = { |
c7416003 KC |
978 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
979 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
980 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
981 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
982 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
983 | }; |
984 | ||
985 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
986 | { | |
987 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
988 | char arg[20]; | |
989 | int ret, i; | |
990 | ||
2a56e210 JP |
991 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || |
992 | cpu_mitigations_off()) { | |
e63490c8 KRW |
993 | return SPEC_STORE_BYPASS_CMD_NONE; |
994 | } else { | |
995 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
996 | arg, sizeof(arg)); | |
997 | if (ret < 0) | |
998 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
999 | ||
1000 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
1001 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
1002 | continue; | |
1003 | ||
1004 | cmd = ssb_mitigation_options[i].cmd; | |
1005 | break; | |
1006 | } | |
1007 | ||
1008 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
1009 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
1010 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
1011 | } | |
1012 | } | |
1013 | ||
1014 | return cmd; | |
1015 | } | |
1016 | ||
dbe3009d | 1017 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
1018 | { |
1019 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
1020 | enum ssb_mitigation_cmd cmd; | |
1021 | ||
8fe36c9d | 1022 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
1023 | return mode; |
1024 | ||
1025 | cmd = ssb_parse_cmdline(); | |
1026 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
1027 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
1028 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
1029 | return mode; | |
1030 | ||
1031 | switch (cmd) { | |
1032 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
1033 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
1034 | /* | |
1035 | * Choose prctl+seccomp as the default mode if seccomp is | |
1036 | * enabled. | |
1037 | */ | |
1038 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
1039 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
1040 | else | |
1041 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 1042 | break; |
e63490c8 KRW |
1043 | case SPEC_STORE_BYPASS_CMD_ON: |
1044 | mode = SPEC_STORE_BYPASS_DISABLE; | |
1045 | break; | |
574dcf89 TG |
1046 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
1047 | mode = SPEC_STORE_BYPASS_PRCTL; | |
1048 | break; | |
e63490c8 KRW |
1049 | case SPEC_STORE_BYPASS_CMD_NONE: |
1050 | break; | |
1051 | } | |
1052 | ||
746685b8 AJ |
1053 | /* |
1054 | * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper | |
1055 | * bit in the mask to allow guests to use the mitigation even in the | |
1056 | * case where the host does not enable it. | |
1057 | */ | |
1058 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || | |
1059 | static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
1060 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; | |
1061 | } | |
1062 | ||
23b9eab9 KRW |
1063 | /* |
1064 | * We have three CPU feature flags that are in play here: | |
1065 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 1066 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
1067 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
1068 | */ | |
574dcf89 | 1069 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 1070 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 1071 | /* |
3b881627 KRW |
1072 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
1073 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 1074 | */ |
5005c716 TL |
1075 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
1076 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 1077 | x86_amd_ssb_disable(); |
5005c716 | 1078 | } else { |
8fe36c9d | 1079 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
208efa83 | 1080 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
1081 | } |
1082 | } | |
1083 | ||
e63490c8 KRW |
1084 | return mode; |
1085 | } | |
1086 | ||
043d480e | 1087 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
1088 | { |
1089 | ssb_mode = __ssb_select_mitigation(); | |
1090 | ||
1091 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1092 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
1093 | } | |
1094 | ||
da285121 | 1095 | #undef pr_fmt |
c7416003 | 1096 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 1097 | |
801d6893 | 1098 | static void task_update_spec_tif(struct task_struct *tsk) |
574dcf89 | 1099 | { |
801d6893 TG |
1100 | /* Force the update of the real TIF bits */ |
1101 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
d4595948 TG |
1102 | |
1103 | /* | |
1104 | * Immediately update the speculation control MSRs for the current | |
1105 | * task, but for a non-current task delay setting the CPU | |
1106 | * mitigation until it is scheduled next. | |
1107 | * | |
1108 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
1109 | * always the current task. | |
1110 | */ | |
801d6893 | 1111 | if (tsk == current) |
d4595948 TG |
1112 | speculation_ctrl_update_current(); |
1113 | } | |
1114 | ||
1115 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
1116 | { | |
c7416003 KC |
1117 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
1118 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
1119 | return -ENXIO; |
1120 | ||
733f4234 TG |
1121 | switch (ctrl) { |
1122 | case PR_SPEC_ENABLE: | |
1123 | /* If speculation is force disabled, enable is not allowed */ | |
1124 | if (task_spec_ssb_force_disable(task)) | |
1125 | return -EPERM; | |
1126 | task_clear_spec_ssb_disable(task); | |
801d6893 | 1127 | task_update_spec_tif(task); |
733f4234 TG |
1128 | break; |
1129 | case PR_SPEC_DISABLE: | |
1130 | task_set_spec_ssb_disable(task); | |
801d6893 | 1131 | task_update_spec_tif(task); |
733f4234 TG |
1132 | break; |
1133 | case PR_SPEC_FORCE_DISABLE: | |
1134 | task_set_spec_ssb_disable(task); | |
1135 | task_set_spec_ssb_force_disable(task); | |
801d6893 | 1136 | task_update_spec_tif(task); |
733f4234 TG |
1137 | break; |
1138 | default: | |
1139 | return -ERANGE; | |
1140 | } | |
574dcf89 TG |
1141 | return 0; |
1142 | } | |
1143 | ||
ac40ad3b TG |
1144 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
1145 | { | |
1146 | switch (ctrl) { | |
1147 | case PR_SPEC_ENABLE: | |
1148 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
1149 | return 0; | |
1150 | /* | |
1151 | * Indirect branch speculation is always disabled in strict | |
1152 | * mode. | |
1153 | */ | |
fbed8eca TL |
1154 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
1155 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
1156 | return -EPERM; |
1157 | task_clear_spec_ib_disable(task); | |
1158 | task_update_spec_tif(task); | |
1159 | break; | |
1160 | case PR_SPEC_DISABLE: | |
1161 | case PR_SPEC_FORCE_DISABLE: | |
1162 | /* | |
1163 | * Indirect branch speculation is always allowed when | |
1164 | * mitigation is force disabled. | |
1165 | */ | |
1166 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
1167 | return -EPERM; | |
fbed8eca TL |
1168 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
1169 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
1170 | return 0; |
1171 | task_set_spec_ib_disable(task); | |
1172 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
1173 | task_set_spec_ib_force_disable(task); | |
1174 | task_update_spec_tif(task); | |
1175 | break; | |
1176 | default: | |
1177 | return -ERANGE; | |
1178 | } | |
1179 | return 0; | |
1180 | } | |
1181 | ||
5b38e244 TG |
1182 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
1183 | unsigned long ctrl) | |
1184 | { | |
1185 | switch (which) { | |
1186 | case PR_SPEC_STORE_BYPASS: | |
1187 | return ssb_prctl_set(task, ctrl); | |
ac40ad3b TG |
1188 | case PR_SPEC_INDIRECT_BRANCH: |
1189 | return ib_prctl_set(task, ctrl); | |
5b38e244 TG |
1190 | default: |
1191 | return -ENODEV; | |
1192 | } | |
1193 | } | |
1194 | ||
1195 | #ifdef CONFIG_SECCOMP | |
1196 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
1197 | { | |
c7416003 KC |
1198 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
1199 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
1c3cf627 TG |
1200 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
1201 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
1202 | } |
1203 | #endif | |
1204 | ||
199bfed2 | 1205 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
1206 | { |
1207 | switch (ssb_mode) { | |
1208 | case SPEC_STORE_BYPASS_DISABLE: | |
1209 | return PR_SPEC_DISABLE; | |
c7416003 | 1210 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 1211 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
1212 | if (task_spec_ssb_force_disable(task)) |
1213 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
1214 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
1215 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
1216 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1217 | default: | |
1218 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1219 | return PR_SPEC_ENABLE; | |
1220 | return PR_SPEC_NOT_AFFECTED; | |
1221 | } | |
1222 | } | |
1223 | ||
ac40ad3b TG |
1224 | static int ib_prctl_get(struct task_struct *task) |
1225 | { | |
1226 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
1227 | return PR_SPEC_NOT_AFFECTED; | |
1228 | ||
1229 | switch (spectre_v2_user) { | |
1230 | case SPECTRE_V2_USER_NONE: | |
1231 | return PR_SPEC_ENABLE; | |
1232 | case SPECTRE_V2_USER_PRCTL: | |
1c3cf627 | 1233 | case SPECTRE_V2_USER_SECCOMP: |
ac40ad3b TG |
1234 | if (task_spec_ib_force_disable(task)) |
1235 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
1236 | if (task_spec_ib_disable(task)) | |
1237 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
1238 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1239 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 1240 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
ac40ad3b TG |
1241 | return PR_SPEC_DISABLE; |
1242 | default: | |
1243 | return PR_SPEC_NOT_AFFECTED; | |
1244 | } | |
1245 | } | |
1246 | ||
199bfed2 | 1247 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
1248 | { |
1249 | switch (which) { | |
1250 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 1251 | return ssb_prctl_get(task); |
ac40ad3b TG |
1252 | case PR_SPEC_INDIRECT_BRANCH: |
1253 | return ib_prctl_get(task); | |
574dcf89 TG |
1254 | default: |
1255 | return -ENODEV; | |
1256 | } | |
1257 | } | |
1258 | ||
23b9eab9 KRW |
1259 | void x86_spec_ctrl_setup_ap(void) |
1260 | { | |
50f9b919 | 1261 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 1262 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
1263 | |
1264 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 1265 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
1266 | } |
1267 | ||
5bfdb235 PB |
1268 | bool itlb_multihit_kvm_mitigation; |
1269 | EXPORT_SYMBOL_GPL(itlb_multihit_kvm_mitigation); | |
1270 | ||
73ca9f47 KRW |
1271 | #undef pr_fmt |
1272 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 1273 | |
24fcb53c JK |
1274 | /* Default mitigation for L1TF-affected CPUs */ |
1275 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 1276 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c | 1277 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
47bb1124 | 1278 | #endif |
522c7bed | 1279 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd | 1280 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
b9cfedcd | 1281 | |
f1f016ed AK |
1282 | /* |
1283 | * These CPUs all support 44bits physical address space internally in the | |
1284 | * cache but CPUID can report a smaller number of physical address bits. | |
1285 | * | |
1286 | * The L1TF mitigation uses the top most address bit for the inversion of | |
1287 | * non present PTEs. When the installed memory reaches into the top most | |
1288 | * address bit due to memory holes, which has been observed on machines | |
1289 | * which report 36bits physical address bits and have 32G RAM installed, | |
1290 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
1291 | * This is a false positive because the mitigation is still possible due to | |
1292 | * the fact that the cache uses 44bit internally. Use the cache bits | |
1293 | * instead of the reported physical bits and adjust them on the affected | |
1294 | * machines to 44bit if the reported bits are less than 44. | |
1295 | */ | |
1296 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
1297 | { | |
1298 | if (c->x86 != 6) | |
1299 | return; | |
1300 | ||
1301 | switch (c->x86_model) { | |
1302 | case INTEL_FAM6_NEHALEM: | |
1303 | case INTEL_FAM6_WESTMERE: | |
1304 | case INTEL_FAM6_SANDYBRIDGE: | |
1305 | case INTEL_FAM6_IVYBRIDGE: | |
1306 | case INTEL_FAM6_HASWELL_CORE: | |
1307 | case INTEL_FAM6_HASWELL_ULT: | |
1308 | case INTEL_FAM6_HASWELL_GT3E: | |
1309 | case INTEL_FAM6_BROADWELL_CORE: | |
1310 | case INTEL_FAM6_BROADWELL_GT3E: | |
1311 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
1312 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
1313 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
1314 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
1315 | if (c->x86_cache_bits < 44) | |
1316 | c->x86_cache_bits = 44; | |
1317 | break; | |
1318 | } | |
1319 | } | |
1320 | ||
73ca9f47 KRW |
1321 | static void __init l1tf_select_mitigation(void) |
1322 | { | |
1323 | u64 half_pa; | |
1324 | ||
1325 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1326 | return; | |
1327 | ||
2a56e210 JP |
1328 | if (cpu_mitigations_off()) |
1329 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1330 | else if (cpu_mitigations_auto_nosmt()) | |
1331 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1332 | ||
f1f016ed AK |
1333 | override_cache_bits(&boot_cpu_data); |
1334 | ||
24fcb53c JK |
1335 | switch (l1tf_mitigation) { |
1336 | case L1TF_MITIGATION_OFF: | |
1337 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
1338 | case L1TF_MITIGATION_FLUSH: | |
1339 | break; | |
1340 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
1341 | case L1TF_MITIGATION_FULL: | |
1342 | cpu_smt_disable(false); | |
1343 | break; | |
1344 | case L1TF_MITIGATION_FULL_FORCE: | |
1345 | cpu_smt_disable(true); | |
1346 | break; | |
1347 | } | |
1348 | ||
73ca9f47 KRW |
1349 | #if CONFIG_PGTABLE_LEVELS == 2 |
1350 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1351 | return; | |
1352 | #endif | |
1353 | ||
73ca9f47 | 1354 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
5b9b29ca MH |
1355 | if (l1tf_mitigation != L1TF_MITIGATION_OFF && |
1356 | e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
73ca9f47 | 1357 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); |
f80e341a VB |
1358 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
1359 | half_pa); | |
1360 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
c7ed1048 | 1361 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); |
73ca9f47 KRW |
1362 | return; |
1363 | } | |
1364 | ||
1365 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1366 | } | |
24fcb53c JK |
1367 | |
1368 | static int __init l1tf_cmdline(char *str) | |
1369 | { | |
1370 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1371 | return 0; | |
1372 | ||
1373 | if (!str) | |
1374 | return -EINVAL; | |
1375 | ||
1376 | if (!strcmp(str, "off")) | |
1377 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1378 | else if (!strcmp(str, "flush,nowarn")) | |
1379 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1380 | else if (!strcmp(str, "flush")) | |
1381 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1382 | else if (!strcmp(str, "flush,nosmt")) | |
1383 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1384 | else if (!strcmp(str, "full")) | |
1385 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1386 | else if (!strcmp(str, "full,force")) | |
1387 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1388 | ||
1389 | return 0; | |
1390 | } | |
1391 | early_param("l1tf", l1tf_cmdline); | |
1392 | ||
73ca9f47 | 1393 | #undef pr_fmt |
0923e77e | 1394 | #define pr_fmt(fmt) fmt |
73ca9f47 | 1395 | |
61dc0f55 | 1396 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 1397 | |
b9cfedcd TG |
1398 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1399 | ||
1400 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 1401 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
1402 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1403 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1404 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1405 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1406 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 1407 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
1408 | }; |
1409 | ||
1410 | static ssize_t l1tf_show_state(char *buf) | |
1411 | { | |
1412 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1413 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1414 | ||
3899f7b1 PB |
1415 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1416 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 1417 | sched_smt_active())) { |
3899f7b1 PB |
1418 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1419 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 1420 | } |
3899f7b1 PB |
1421 | |
1422 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1423 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 1424 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd | 1425 | } |
5bfdb235 PB |
1426 | |
1427 | static ssize_t itlb_multihit_show_state(char *buf) | |
1428 | { | |
1429 | if (itlb_multihit_kvm_mitigation) | |
1430 | return sprintf(buf, "KVM: Mitigation: Split huge pages\n"); | |
1431 | else | |
1432 | return sprintf(buf, "KVM: Vulnerable\n"); | |
1433 | } | |
b9cfedcd TG |
1434 | #else |
1435 | static ssize_t l1tf_show_state(char *buf) | |
1436 | { | |
1437 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1438 | } | |
b9cfedcd | 1439 | |
349806c4 PG |
1440 | static ssize_t itlb_multihit_show_state(char *buf) |
1441 | { | |
1442 | return sprintf(buf, "Processor vulnerable\n"); | |
1443 | } | |
5bfdb235 | 1444 | #endif |
349806c4 | 1445 | |
1122cc78 TG |
1446 | static ssize_t mds_show_state(char *buf) |
1447 | { | |
7e834f4c | 1448 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { |
1122cc78 TG |
1449 | return sprintf(buf, "%s; SMT Host state unknown\n", |
1450 | mds_strings[mds_mitigation]); | |
1451 | } | |
1452 | ||
1453 | if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { | |
1454 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
5c89a99c KRW |
1455 | (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : |
1456 | sched_smt_active() ? "mitigated" : "disabled")); | |
1122cc78 TG |
1457 | } |
1458 | ||
1459 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
1460 | sched_smt_active() ? "vulnerable" : "disabled"); | |
1461 | } | |
1462 | ||
c46d17ac PG |
1463 | static ssize_t tsx_async_abort_show_state(char *buf) |
1464 | { | |
1465 | if ((taa_mitigation == TAA_MITIGATION_TSX_DISABLED) || | |
1466 | (taa_mitigation == TAA_MITIGATION_OFF)) | |
1467 | return sprintf(buf, "%s\n", taa_strings[taa_mitigation]); | |
1468 | ||
1469 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { | |
1470 | return sprintf(buf, "%s; SMT Host state unknown\n", | |
1471 | taa_strings[taa_mitigation]); | |
1472 | } | |
1473 | ||
1474 | return sprintf(buf, "%s; SMT %s\n", taa_strings[taa_mitigation], | |
1475 | sched_smt_active() ? "vulnerable" : "disabled"); | |
1476 | } | |
1477 | ||
2daa53e8 TC |
1478 | static char *stibp_state(void) |
1479 | { | |
4a8d91c8 TC |
1480 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1481 | return ""; | |
1482 | ||
6cd930f0 TG |
1483 | switch (spectre_v2_user) { |
1484 | case SPECTRE_V2_USER_NONE: | |
1485 | return ", STIBP: disabled"; | |
1486 | case SPECTRE_V2_USER_STRICT: | |
1487 | return ", STIBP: forced"; | |
fbed8eca TL |
1488 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
1489 | return ", STIBP: always-on"; | |
ac40ad3b | 1490 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 1491 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 TG |
1492 | if (static_key_enabled(&switch_to_cond_stibp)) |
1493 | return ", STIBP: conditional"; | |
6cd930f0 TG |
1494 | } |
1495 | return ""; | |
2daa53e8 TC |
1496 | } |
1497 | ||
1498 | static char *ibpb_state(void) | |
1499 | { | |
58b2d4c8 | 1500 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
2cdf6a58 | 1501 | if (static_key_enabled(&switch_mm_always_ibpb)) |
58b2d4c8 | 1502 | return ", IBPB: always-on"; |
2cdf6a58 TG |
1503 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1504 | return ", IBPB: conditional"; | |
1505 | return ", IBPB: disabled"; | |
58b2d4c8 TG |
1506 | } |
1507 | return ""; | |
2daa53e8 TC |
1508 | } |
1509 | ||
ace051d5 | 1510 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 1511 | char *buf, unsigned int bug) |
61dc0f55 | 1512 | { |
d2b8fc2d | 1513 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1514 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
1515 | |
1516 | switch (bug) { | |
1517 | case X86_BUG_CPU_MELTDOWN: | |
1518 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1519 | return sprintf(buf, "Mitigation: PTI\n"); | |
1520 | ||
1521 | break; | |
1522 | ||
1523 | case X86_BUG_SPECTRE_V1: | |
1592edce | 1524 | return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); |
d2b8fc2d KRW |
1525 | |
1526 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 1527 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 1528 | ibpb_state(), |
d2b8fc2d | 1529 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 1530 | stibp_state(), |
5e2fafd5 | 1531 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
1532 | spectre_v2_module_string()); |
1533 | ||
e63490c8 KRW |
1534 | case X86_BUG_SPEC_STORE_BYPASS: |
1535 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1536 | ||
05516ad8 AK |
1537 | case X86_BUG_L1TF: |
1538 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 1539 | return l1tf_show_state(buf); |
05516ad8 | 1540 | break; |
1122cc78 TG |
1541 | |
1542 | case X86_BUG_MDS: | |
1543 | return mds_show_state(buf); | |
1544 | ||
c46d17ac PG |
1545 | case X86_BUG_TAA: |
1546 | return tsx_async_abort_show_state(buf); | |
1547 | ||
349806c4 PG |
1548 | case X86_BUG_ITLB_MULTIHIT: |
1549 | return itlb_multihit_show_state(buf); | |
1550 | ||
d2b8fc2d KRW |
1551 | default: |
1552 | break; | |
1553 | } | |
1554 | ||
61dc0f55 TG |
1555 | return sprintf(buf, "Vulnerable\n"); |
1556 | } | |
1557 | ||
d2b8fc2d KRW |
1558 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1559 | { | |
1560 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1561 | } | |
1562 | ||
713f1b95 | 1563 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1564 | { |
d2b8fc2d | 1565 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1566 | } |
1567 | ||
713f1b95 | 1568 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1569 | { |
d2b8fc2d | 1570 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1571 | } |
d7de9182 KRW |
1572 | |
1573 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1574 | { | |
1575 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1576 | } | |
05516ad8 AK |
1577 | |
1578 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1579 | { | |
1580 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1581 | } | |
1122cc78 TG |
1582 | |
1583 | ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) | |
1584 | { | |
1585 | return cpu_show_common(dev, attr, buf, X86_BUG_MDS); | |
1586 | } | |
c46d17ac PG |
1587 | |
1588 | ssize_t cpu_show_tsx_async_abort(struct device *dev, struct device_attribute *attr, char *buf) | |
1589 | { | |
1590 | return cpu_show_common(dev, attr, buf, X86_BUG_TAA); | |
1591 | } | |
349806c4 PG |
1592 | |
1593 | ssize_t cpu_show_itlb_multihit(struct device *dev, struct device_attribute *attr, char *buf) | |
1594 | { | |
1595 | return cpu_show_common(dev, attr, buf, X86_BUG_ITLB_MULTIHIT); | |
1596 | } | |
61dc0f55 | 1597 | #endif |