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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1353ebb4 | 2 | /* |
1353ebb4 JF |
3 | * Copyright (C) 1994 Linus Torvalds |
4 | * | |
5 | * Cyrix stuff, June 1998 by: | |
6 | * - Rafael R. Reilova (moved everything from head.S), | |
7 | * <rreilova@ececs.uc.edu> | |
8 | * - Channing Corn (tests & fixes), | |
9 | * - Andrew D. Balsa (code cleanup). | |
10 | */ | |
11 | #include <linux/init.h> | |
12 | #include <linux/utsname.h> | |
61dc0f55 | 13 | #include <linux/cpu.h> |
d280282b | 14 | #include <linux/module.h> |
574dcf89 TG |
15 | #include <linux/nospec.h> |
16 | #include <linux/prctl.h> | |
fc8944e3 | 17 | #include <linux/sched/smt.h> |
da285121 | 18 | |
d7a6a163 | 19 | #include <asm/spec-ctrl.h> |
da285121 | 20 | #include <asm/cmdline.h> |
91eb1b79 | 21 | #include <asm/bugs.h> |
1353ebb4 | 22 | #include <asm/processor.h> |
7ebad705 | 23 | #include <asm/processor-flags.h> |
952f07ec | 24 | #include <asm/fpu/internal.h> |
1353ebb4 | 25 | #include <asm/msr.h> |
b9cfedcd | 26 | #include <asm/vmx.h> |
1353ebb4 JF |
27 | #include <asm/paravirt.h> |
28 | #include <asm/alternative.h> | |
62a67e12 | 29 | #include <asm/pgtable.h> |
d1163651 | 30 | #include <asm/set_memory.h> |
c995efd5 | 31 | #include <asm/intel-family.h> |
05516ad8 | 32 | #include <asm/e820/api.h> |
1122cc78 | 33 | #include <asm/hypervisor.h> |
1353ebb4 | 34 | |
1592edce | 35 | static void __init spectre_v1_select_mitigation(void); |
da285121 | 36 | static void __init spectre_v2_select_mitigation(void); |
e63490c8 | 37 | static void __init ssb_select_mitigation(void); |
05516ad8 | 38 | static void __init l1tf_select_mitigation(void); |
fc5ee888 | 39 | static void __init mds_select_mitigation(void); |
da285121 | 40 | |
7011f443 JK |
41 | /* The base value of the SPEC_CTRL MSR that always has to be preserved. */ |
42 | u64 x86_spec_ctrl_base; | |
4ac9b1f9 | 43 | EXPORT_SYMBOL_GPL(x86_spec_ctrl_base); |
7011f443 | 44 | static DEFINE_MUTEX(spec_ctrl_mutex); |
296b454a | 45 | |
d0c3bedd KRW |
46 | /* |
47 | * The vendor and possibly platform specific bits which can be modified in | |
48 | * x86_spec_ctrl_base. | |
49 | */ | |
e5f984ed | 50 | static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; |
d0c3bedd | 51 | |
c37b94dd KRW |
52 | /* |
53 | * AMD specific MSR info for Speculative Store Bypass control. | |
8fe36c9d | 54 | * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu(). |
c37b94dd KRW |
55 | */ |
56 | u64 __ro_after_init x86_amd_ls_cfg_base; | |
8fe36c9d | 57 | u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 58 | |
8edb388f | 59 | /* Control conditional STIBP in switch_to() */ |
6cd930f0 | 60 | DEFINE_STATIC_KEY_FALSE(switch_to_cond_stibp); |
58b2d4c8 TG |
61 | /* Control conditional IBPB in switch_mm() */ |
62 | DEFINE_STATIC_KEY_FALSE(switch_mm_cond_ibpb); | |
63 | /* Control unconditional IBPB in switch_mm() */ | |
64 | DEFINE_STATIC_KEY_FALSE(switch_mm_always_ibpb); | |
6cd930f0 | 65 | |
5ab15133 TG |
66 | /* Control MDS CPU buffer clear before returning to user space */ |
67 | DEFINE_STATIC_KEY_FALSE(mds_user_clear); | |
abf9852b | 68 | EXPORT_SYMBOL_GPL(mds_user_clear); |
f3eb8f09 TG |
69 | /* Control MDS CPU buffer clear before idling (halt, mwait) */ |
70 | DEFINE_STATIC_KEY_FALSE(mds_idle_clear); | |
71 | EXPORT_SYMBOL_GPL(mds_idle_clear); | |
5ab15133 | 72 | |
1353ebb4 JF |
73 | void __init check_bugs(void) |
74 | { | |
75 | identify_boot_cpu(); | |
55a36b65 | 76 | |
483ec3c6 TG |
77 | /* |
78 | * identify_boot_cpu() initialized SMT support information, let the | |
79 | * core code know. | |
80 | */ | |
ade31b9e | 81 | cpu_smt_check_topology_early(); |
483ec3c6 | 82 | |
62a67e12 BP |
83 | if (!IS_ENABLED(CONFIG_SMP)) { |
84 | pr_info("CPU: "); | |
85 | print_cpu_info(&boot_cpu_data); | |
86 | } | |
87 | ||
296b454a KRW |
88 | /* |
89 | * Read the SPEC_CTRL MSR to account for reserved bits which may | |
c37b94dd KRW |
90 | * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD |
91 | * init code as it is not enumerated and depends on the family. | |
296b454a | 92 | */ |
50f9b919 | 93 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
296b454a KRW |
94 | rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
95 | ||
e5f984ed TG |
96 | /* Allow STIBP in MSR_SPEC_CTRL if supported */ |
97 | if (boot_cpu_has(X86_FEATURE_STIBP)) | |
98 | x86_spec_ctrl_mask |= SPEC_CTRL_STIBP; | |
99 | ||
1592edce JP |
100 | /* Select the proper CPU mitigations before patching alternatives: */ |
101 | spectre_v1_select_mitigation(); | |
da285121 | 102 | spectre_v2_select_mitigation(); |
e63490c8 | 103 | ssb_select_mitigation(); |
05516ad8 | 104 | l1tf_select_mitigation(); |
fc5ee888 TG |
105 | mds_select_mitigation(); |
106 | ||
15ff73d9 JP |
107 | arch_smt_update(); |
108 | ||
62a67e12 | 109 | #ifdef CONFIG_X86_32 |
55a36b65 BP |
110 | /* |
111 | * Check whether we are able to run this kernel safely on SMP. | |
112 | * | |
113 | * - i386 is no longer supported. | |
114 | * - In order to run on anything without a TSC, we need to be | |
115 | * compiled for a i486. | |
116 | */ | |
117 | if (boot_cpu_data.x86 < 4) | |
118 | panic("Kernel requires i486+ for 'invlpg' and other features"); | |
119 | ||
bfe4bb15 MV |
120 | init_utsname()->machine[1] = |
121 | '0' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86); | |
1353ebb4 | 122 | alternative_instructions(); |
304bceda | 123 | |
4d164092 | 124 | fpu__init_check_bugs(); |
62a67e12 BP |
125 | #else /* CONFIG_X86_64 */ |
126 | alternative_instructions(); | |
127 | ||
128 | /* | |
129 | * Make sure the first 2MB area is not mapped by huge pages | |
130 | * There are typically fixed size MTRRs in there and overlapping | |
131 | * MTRRs into large pages causes slow downs. | |
132 | * | |
133 | * Right now we don't do that with gbpages because there seems | |
134 | * very little benefit for that case. | |
135 | */ | |
136 | if (!direct_gbpages) | |
137 | set_memory_4k((unsigned long)__va(0), 1); | |
138 | #endif | |
1353ebb4 | 139 | } |
61dc0f55 | 140 | |
12376b62 BP |
141 | void |
142 | x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest) | |
19fff03f | 143 | { |
e5f984ed | 144 | u64 msrval, guestval, hostval = x86_spec_ctrl_base; |
12376b62 | 145 | struct thread_info *ti = current_thread_info(); |
5407b7f8 | 146 | |
50f9b919 | 147 | /* Is MSR_SPEC_CTRL implemented ? */ |
12376b62 | 148 | if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { |
e5f984ed TG |
149 | /* |
150 | * Restrict guest_spec_ctrl to supported values. Clear the | |
151 | * modifiable bits in the host base value and or the | |
152 | * modifiable bits from the guest value. | |
153 | */ | |
154 | guestval = hostval & ~x86_spec_ctrl_mask; | |
155 | guestval |= guest_spec_ctrl & x86_spec_ctrl_mask; | |
156 | ||
12376b62 | 157 | /* SSBD controlled in MSR_SPEC_CTRL */ |
5005c716 TL |
158 | if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || |
159 | static_cpu_has(X86_FEATURE_AMD_SSBD)) | |
e5f984ed | 160 | hostval |= ssbd_tif_to_spec_ctrl(ti->flags); |
12376b62 | 161 | |
e0b04783 TC |
162 | /* Conditional STIBP enabled? */ |
163 | if (static_branch_unlikely(&switch_to_cond_stibp)) | |
164 | hostval |= stibp_tif_to_spec_ctrl(ti->flags); | |
165 | ||
e5f984ed TG |
166 | if (hostval != guestval) { |
167 | msrval = setguest ? guestval : hostval; | |
168 | wrmsrl(MSR_IA32_SPEC_CTRL, msrval); | |
12376b62 BP |
169 | } |
170 | } | |
1238ed31 TG |
171 | |
172 | /* | |
173 | * If SSBD is not handled in MSR_SPEC_CTRL on AMD, update | |
174 | * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. | |
175 | */ | |
176 | if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && | |
177 | !static_cpu_has(X86_FEATURE_VIRT_SSBD)) | |
178 | return; | |
179 | ||
180 | /* | |
181 | * If the host has SSBD mitigation enabled, force it in the host's | |
182 | * virtual MSR value. If its not permanently enabled, evaluate | |
183 | * current's TIF_SSBD thread flag. | |
184 | */ | |
185 | if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) | |
186 | hostval = SPEC_CTRL_SSBD; | |
187 | else | |
188 | hostval = ssbd_tif_to_spec_ctrl(ti->flags); | |
189 | ||
190 | /* Sanitize the guest value */ | |
191 | guestval = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; | |
192 | ||
193 | if (hostval != guestval) { | |
194 | unsigned long tif; | |
195 | ||
196 | tif = setguest ? ssbd_spec_ctrl_to_tif(guestval) : | |
197 | ssbd_spec_ctrl_to_tif(hostval); | |
198 | ||
8fce7184 | 199 | speculation_ctrl_update(tif); |
1238ed31 | 200 | } |
19fff03f | 201 | } |
12376b62 | 202 | EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); |
19fff03f | 203 | |
8fe36c9d | 204 | static void x86_amd_ssb_disable(void) |
c37b94dd | 205 | { |
8fe36c9d | 206 | u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_ssbd_mask; |
c37b94dd | 207 | |
65e02bbd TL |
208 | if (boot_cpu_has(X86_FEATURE_VIRT_SSBD)) |
209 | wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, SPEC_CTRL_SSBD); | |
210 | else if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD)) | |
c37b94dd KRW |
211 | wrmsrl(MSR_AMD64_LS_CFG, msrval); |
212 | } | |
213 | ||
fc5ee888 TG |
214 | #undef pr_fmt |
215 | #define pr_fmt(fmt) "MDS: " fmt | |
216 | ||
64adee4f | 217 | /* Default mitigation for MDS-affected CPUs */ |
fc5ee888 | 218 | static enum mds_mitigations mds_mitigation __ro_after_init = MDS_MITIGATION_FULL; |
e2f3c337 | 219 | static bool mds_nosmt __ro_after_init = false; |
fc5ee888 TG |
220 | |
221 | static const char * const mds_strings[] = { | |
222 | [MDS_MITIGATION_OFF] = "Vulnerable", | |
ebf1e8cb TG |
223 | [MDS_MITIGATION_FULL] = "Mitigation: Clear CPU buffers", |
224 | [MDS_MITIGATION_VMWERV] = "Vulnerable: Clear CPU buffers attempted, no microcode", | |
fc5ee888 TG |
225 | }; |
226 | ||
c7ed1048 | 227 | static void __init mds_select_mitigation(void) |
fc5ee888 | 228 | { |
7781f6db | 229 | if (!boot_cpu_has_bug(X86_BUG_MDS) || cpu_mitigations_off()) { |
fc5ee888 TG |
230 | mds_mitigation = MDS_MITIGATION_OFF; |
231 | return; | |
232 | } | |
233 | ||
234 | if (mds_mitigation == MDS_MITIGATION_FULL) { | |
ebf1e8cb TG |
235 | if (!boot_cpu_has(X86_FEATURE_MD_CLEAR)) |
236 | mds_mitigation = MDS_MITIGATION_VMWERV; | |
e2f3c337 | 237 | |
ebf1e8cb | 238 | static_branch_enable(&mds_user_clear); |
e2f3c337 | 239 | |
7781f6db JP |
240 | if (!boot_cpu_has(X86_BUG_MSBDS_ONLY) && |
241 | (mds_nosmt || cpu_mitigations_auto_nosmt())) | |
e2f3c337 | 242 | cpu_smt_disable(false); |
fc5ee888 | 243 | } |
e2f3c337 | 244 | |
fc5ee888 TG |
245 | pr_info("%s\n", mds_strings[mds_mitigation]); |
246 | } | |
247 | ||
248 | static int __init mds_cmdline(char *str) | |
249 | { | |
250 | if (!boot_cpu_has_bug(X86_BUG_MDS)) | |
251 | return 0; | |
252 | ||
253 | if (!str) | |
254 | return -EINVAL; | |
255 | ||
256 | if (!strcmp(str, "off")) | |
257 | mds_mitigation = MDS_MITIGATION_OFF; | |
258 | else if (!strcmp(str, "full")) | |
259 | mds_mitigation = MDS_MITIGATION_FULL; | |
e2f3c337 JP |
260 | else if (!strcmp(str, "full,nosmt")) { |
261 | mds_mitigation = MDS_MITIGATION_FULL; | |
262 | mds_nosmt = true; | |
263 | } | |
fc5ee888 TG |
264 | |
265 | return 0; | |
266 | } | |
267 | early_param("mds", mds_cmdline); | |
268 | ||
1592edce JP |
269 | #undef pr_fmt |
270 | #define pr_fmt(fmt) "Spectre V1 : " fmt | |
271 | ||
272 | enum spectre_v1_mitigation { | |
273 | SPECTRE_V1_MITIGATION_NONE, | |
274 | SPECTRE_V1_MITIGATION_AUTO, | |
275 | }; | |
276 | ||
277 | static enum spectre_v1_mitigation spectre_v1_mitigation __ro_after_init = | |
278 | SPECTRE_V1_MITIGATION_AUTO; | |
279 | ||
280 | static const char * const spectre_v1_strings[] = { | |
281 | [SPECTRE_V1_MITIGATION_NONE] = "Vulnerable: __user pointer sanitization and usercopy barriers only; no swapgs barriers", | |
282 | [SPECTRE_V1_MITIGATION_AUTO] = "Mitigation: usercopy/swapgs barriers and __user pointer sanitization", | |
283 | }; | |
284 | ||
285 | static bool is_swapgs_serializing(void) | |
286 | { | |
287 | /* | |
288 | * Technically, swapgs isn't serializing on AMD (despite it previously | |
289 | * being documented as such in the APM). But according to AMD, %gs is | |
290 | * updated non-speculatively, and the issuing of %gs-relative memory | |
291 | * operands will be blocked until the %gs update completes, which is | |
292 | * good enough for our purposes. | |
293 | */ | |
294 | return boot_cpu_data.x86_vendor == X86_VENDOR_AMD; | |
295 | } | |
296 | ||
297 | /* | |
298 | * Does SMAP provide full mitigation against speculative kernel access to | |
299 | * userspace? | |
300 | */ | |
301 | static bool smap_works_speculatively(void) | |
302 | { | |
303 | if (!boot_cpu_has(X86_FEATURE_SMAP)) | |
304 | return false; | |
305 | ||
306 | /* | |
307 | * On CPUs which are vulnerable to Meltdown, SMAP does not | |
308 | * prevent speculative access to user data in the L1 cache. | |
309 | * Consider SMAP to be non-functional as a mitigation on these | |
310 | * CPUs. | |
311 | */ | |
312 | if (boot_cpu_has(X86_BUG_CPU_MELTDOWN)) | |
313 | return false; | |
314 | ||
315 | return true; | |
316 | } | |
317 | ||
318 | static void __init spectre_v1_select_mitigation(void) | |
319 | { | |
320 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V1) || cpu_mitigations_off()) { | |
321 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | |
322 | return; | |
323 | } | |
324 | ||
325 | if (spectre_v1_mitigation == SPECTRE_V1_MITIGATION_AUTO) { | |
326 | /* | |
327 | * With Spectre v1, a user can speculatively control either | |
328 | * path of a conditional swapgs with a user-controlled GS | |
329 | * value. The mitigation is to add lfences to both code paths. | |
330 | * | |
331 | * If FSGSBASE is enabled, the user can put a kernel address in | |
332 | * GS, in which case SMAP provides no protection. | |
333 | * | |
334 | * [ NOTE: Don't check for X86_FEATURE_FSGSBASE until the | |
335 | * FSGSBASE enablement patches have been merged. ] | |
336 | * | |
337 | * If FSGSBASE is disabled, the user can only put a user space | |
338 | * address in GS. That makes an attack harder, but still | |
339 | * possible if there's no SMAP protection. | |
340 | */ | |
341 | if (!smap_works_speculatively()) { | |
342 | /* | |
343 | * Mitigation can be provided from SWAPGS itself or | |
344 | * PTI as the CR3 write in the Meltdown mitigation | |
345 | * is serializing. | |
346 | * | |
347 | * If neither is there, mitigate with an LFENCE. | |
348 | */ | |
349 | if (!is_swapgs_serializing() && !boot_cpu_has(X86_FEATURE_PTI)) | |
350 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_USER); | |
351 | ||
352 | /* | |
353 | * Enable lfences in the kernel entry (non-swapgs) | |
354 | * paths, to prevent user entry from speculatively | |
355 | * skipping swapgs. | |
356 | */ | |
357 | setup_force_cpu_cap(X86_FEATURE_FENCE_SWAPGS_KERNEL); | |
358 | } | |
359 | } | |
360 | ||
361 | pr_info("%s\n", spectre_v1_strings[spectre_v1_mitigation]); | |
362 | } | |
363 | ||
364 | static int __init nospectre_v1_cmdline(char *str) | |
365 | { | |
366 | spectre_v1_mitigation = SPECTRE_V1_MITIGATION_NONE; | |
367 | return 0; | |
368 | } | |
369 | early_param("nospectre_v1", nospectre_v1_cmdline); | |
370 | ||
aef0bebc TG |
371 | #undef pr_fmt |
372 | #define pr_fmt(fmt) "Spectre V2 : " fmt | |
373 | ||
374 | static enum spectre_v2_mitigation spectre_v2_enabled __ro_after_init = | |
375 | SPECTRE_V2_NONE; | |
376 | ||
6cd930f0 TG |
377 | static enum spectre_v2_user_mitigation spectre_v2_user __ro_after_init = |
378 | SPECTRE_V2_USER_NONE; | |
379 | ||
e9a556ad | 380 | #ifdef CONFIG_RETPOLINE |
bb3c2578 TG |
381 | static bool spectre_v2_bad_module; |
382 | ||
d280282b AK |
383 | bool retpoline_module_ok(bool has_retpoline) |
384 | { | |
385 | if (spectre_v2_enabled == SPECTRE_V2_NONE || has_retpoline) | |
386 | return true; | |
387 | ||
c8b8e109 | 388 | pr_err("System may be vulnerable to spectre v2\n"); |
d280282b AK |
389 | spectre_v2_bad_module = true; |
390 | return false; | |
391 | } | |
bb3c2578 TG |
392 | |
393 | static inline const char *spectre_v2_module_string(void) | |
394 | { | |
395 | return spectre_v2_bad_module ? " - vulnerable module loaded" : ""; | |
396 | } | |
397 | #else | |
398 | static inline const char *spectre_v2_module_string(void) { return ""; } | |
d280282b | 399 | #endif |
da285121 | 400 | |
da285121 DW |
401 | static inline bool match_option(const char *arg, int arglen, const char *opt) |
402 | { | |
403 | int len = strlen(opt); | |
404 | ||
405 | return len == arglen && !strncmp(arg, opt, len); | |
406 | } | |
407 | ||
aef0bebc TG |
408 | /* The kernel command line selection for spectre v2 */ |
409 | enum spectre_v2_mitigation_cmd { | |
410 | SPECTRE_V2_CMD_NONE, | |
411 | SPECTRE_V2_CMD_AUTO, | |
412 | SPECTRE_V2_CMD_FORCE, | |
413 | SPECTRE_V2_CMD_RETPOLINE, | |
414 | SPECTRE_V2_CMD_RETPOLINE_GENERIC, | |
415 | SPECTRE_V2_CMD_RETPOLINE_AMD, | |
416 | }; | |
417 | ||
6cd930f0 TG |
418 | enum spectre_v2_user_cmd { |
419 | SPECTRE_V2_USER_CMD_NONE, | |
420 | SPECTRE_V2_USER_CMD_AUTO, | |
421 | SPECTRE_V2_USER_CMD_FORCE, | |
2cdf6a58 | 422 | SPECTRE_V2_USER_CMD_PRCTL, |
fd1b7023 | 423 | SPECTRE_V2_USER_CMD_PRCTL_IBPB, |
1c3cf627 | 424 | SPECTRE_V2_USER_CMD_SECCOMP, |
fd1b7023 | 425 | SPECTRE_V2_USER_CMD_SECCOMP_IBPB, |
6cd930f0 TG |
426 | }; |
427 | ||
428 | static const char * const spectre_v2_user_strings[] = { | |
fbed8eca TL |
429 | [SPECTRE_V2_USER_NONE] = "User space: Vulnerable", |
430 | [SPECTRE_V2_USER_STRICT] = "User space: Mitigation: STIBP protection", | |
431 | [SPECTRE_V2_USER_STRICT_PREFERRED] = "User space: Mitigation: STIBP always-on protection", | |
432 | [SPECTRE_V2_USER_PRCTL] = "User space: Mitigation: STIBP via prctl", | |
433 | [SPECTRE_V2_USER_SECCOMP] = "User space: Mitigation: STIBP via seccomp and prctl", | |
6cd930f0 TG |
434 | }; |
435 | ||
436 | static const struct { | |
437 | const char *option; | |
438 | enum spectre_v2_user_cmd cmd; | |
439 | bool secure; | |
440 | } v2_user_options[] __initdata = { | |
fd1b7023 TG |
441 | { "auto", SPECTRE_V2_USER_CMD_AUTO, false }, |
442 | { "off", SPECTRE_V2_USER_CMD_NONE, false }, | |
443 | { "on", SPECTRE_V2_USER_CMD_FORCE, true }, | |
444 | { "prctl", SPECTRE_V2_USER_CMD_PRCTL, false }, | |
445 | { "prctl,ibpb", SPECTRE_V2_USER_CMD_PRCTL_IBPB, false }, | |
446 | { "seccomp", SPECTRE_V2_USER_CMD_SECCOMP, false }, | |
447 | { "seccomp,ibpb", SPECTRE_V2_USER_CMD_SECCOMP_IBPB, false }, | |
6cd930f0 TG |
448 | }; |
449 | ||
450 | static void __init spec_v2_user_print_cond(const char *reason, bool secure) | |
451 | { | |
452 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) | |
453 | pr_info("spectre_v2_user=%s forced on command line.\n", reason); | |
454 | } | |
455 | ||
456 | static enum spectre_v2_user_cmd __init | |
457 | spectre_v2_parse_user_cmdline(enum spectre_v2_mitigation_cmd v2_cmd) | |
458 | { | |
459 | char arg[20]; | |
460 | int ret, i; | |
461 | ||
462 | switch (v2_cmd) { | |
463 | case SPECTRE_V2_CMD_NONE: | |
464 | return SPECTRE_V2_USER_CMD_NONE; | |
465 | case SPECTRE_V2_CMD_FORCE: | |
466 | return SPECTRE_V2_USER_CMD_FORCE; | |
467 | default: | |
468 | break; | |
469 | } | |
470 | ||
471 | ret = cmdline_find_option(boot_command_line, "spectre_v2_user", | |
472 | arg, sizeof(arg)); | |
473 | if (ret < 0) | |
474 | return SPECTRE_V2_USER_CMD_AUTO; | |
475 | ||
476 | for (i = 0; i < ARRAY_SIZE(v2_user_options); i++) { | |
477 | if (match_option(arg, ret, v2_user_options[i].option)) { | |
478 | spec_v2_user_print_cond(v2_user_options[i].option, | |
479 | v2_user_options[i].secure); | |
480 | return v2_user_options[i].cmd; | |
481 | } | |
482 | } | |
483 | ||
484 | pr_err("Unknown user space protection option (%s). Switching to AUTO select\n", arg); | |
485 | return SPECTRE_V2_USER_CMD_AUTO; | |
486 | } | |
487 | ||
488 | static void __init | |
489 | spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd) | |
490 | { | |
491 | enum spectre_v2_user_mitigation mode = SPECTRE_V2_USER_NONE; | |
492 | bool smt_possible = IS_ENABLED(CONFIG_SMP); | |
fd1b7023 | 493 | enum spectre_v2_user_cmd cmd; |
6cd930f0 TG |
494 | |
495 | if (!boot_cpu_has(X86_FEATURE_IBPB) && !boot_cpu_has(X86_FEATURE_STIBP)) | |
496 | return; | |
497 | ||
498 | if (cpu_smt_control == CPU_SMT_FORCE_DISABLED || | |
499 | cpu_smt_control == CPU_SMT_NOT_SUPPORTED) | |
500 | smt_possible = false; | |
501 | ||
fd1b7023 TG |
502 | cmd = spectre_v2_parse_user_cmdline(v2_cmd); |
503 | switch (cmd) { | |
6cd930f0 TG |
504 | case SPECTRE_V2_USER_CMD_NONE: |
505 | goto set_mode; | |
506 | case SPECTRE_V2_USER_CMD_FORCE: | |
507 | mode = SPECTRE_V2_USER_STRICT; | |
508 | break; | |
2cdf6a58 | 509 | case SPECTRE_V2_USER_CMD_PRCTL: |
fd1b7023 | 510 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: |
2cdf6a58 TG |
511 | mode = SPECTRE_V2_USER_PRCTL; |
512 | break; | |
1c3cf627 TG |
513 | case SPECTRE_V2_USER_CMD_AUTO: |
514 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
fd1b7023 | 515 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: |
1c3cf627 TG |
516 | if (IS_ENABLED(CONFIG_SECCOMP)) |
517 | mode = SPECTRE_V2_USER_SECCOMP; | |
518 | else | |
519 | mode = SPECTRE_V2_USER_PRCTL; | |
520 | break; | |
6cd930f0 TG |
521 | } |
522 | ||
fbed8eca TL |
523 | /* |
524 | * At this point, an STIBP mode other than "off" has been set. | |
525 | * If STIBP support is not being forced, check if STIBP always-on | |
526 | * is preferred. | |
527 | */ | |
528 | if (mode != SPECTRE_V2_USER_STRICT && | |
529 | boot_cpu_has(X86_FEATURE_AMD_STIBP_ALWAYS_ON)) | |
530 | mode = SPECTRE_V2_USER_STRICT_PREFERRED; | |
531 | ||
6cd930f0 TG |
532 | /* Initialize Indirect Branch Prediction Barrier */ |
533 | if (boot_cpu_has(X86_FEATURE_IBPB)) { | |
534 | setup_force_cpu_cap(X86_FEATURE_USE_IBPB); | |
58b2d4c8 | 535 | |
fd1b7023 TG |
536 | switch (cmd) { |
537 | case SPECTRE_V2_USER_CMD_FORCE: | |
538 | case SPECTRE_V2_USER_CMD_PRCTL_IBPB: | |
539 | case SPECTRE_V2_USER_CMD_SECCOMP_IBPB: | |
58b2d4c8 TG |
540 | static_branch_enable(&switch_mm_always_ibpb); |
541 | break; | |
fd1b7023 TG |
542 | case SPECTRE_V2_USER_CMD_PRCTL: |
543 | case SPECTRE_V2_USER_CMD_AUTO: | |
544 | case SPECTRE_V2_USER_CMD_SECCOMP: | |
2cdf6a58 TG |
545 | static_branch_enable(&switch_mm_cond_ibpb); |
546 | break; | |
58b2d4c8 TG |
547 | default: |
548 | break; | |
549 | } | |
550 | ||
551 | pr_info("mitigation: Enabling %s Indirect Branch Prediction Barrier\n", | |
fd1b7023 TG |
552 | static_key_enabled(&switch_mm_always_ibpb) ? |
553 | "always-on" : "conditional"); | |
6cd930f0 TG |
554 | } |
555 | ||
8edb388f | 556 | /* If enhanced IBRS is enabled no STIBP required */ |
6cd930f0 TG |
557 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
558 | return; | |
559 | ||
2cdf6a58 | 560 | /* |
8edb388f | 561 | * If SMT is not possible or STIBP is not available clear the STIBP |
2cdf6a58 TG |
562 | * mode. |
563 | */ | |
564 | if (!smt_possible || !boot_cpu_has(X86_FEATURE_STIBP)) | |
565 | mode = SPECTRE_V2_USER_NONE; | |
6cd930f0 TG |
566 | set_mode: |
567 | spectre_v2_user = mode; | |
568 | /* Only print the STIBP mode when SMT possible */ | |
569 | if (smt_possible) | |
570 | pr_info("%s\n", spectre_v2_user_strings[mode]); | |
571 | } | |
572 | ||
0eb5928b | 573 | static const char * const spectre_v2_strings[] = { |
aef0bebc TG |
574 | [SPECTRE_V2_NONE] = "Vulnerable", |
575 | [SPECTRE_V2_RETPOLINE_GENERIC] = "Mitigation: Full generic retpoline", | |
576 | [SPECTRE_V2_RETPOLINE_AMD] = "Mitigation: Full AMD retpoline", | |
577 | [SPECTRE_V2_IBRS_ENHANCED] = "Mitigation: Enhanced IBRS", | |
578 | }; | |
579 | ||
17c33e7c KA |
580 | static const struct { |
581 | const char *option; | |
582 | enum spectre_v2_mitigation_cmd cmd; | |
583 | bool secure; | |
5a76cb46 | 584 | } mitigation_options[] __initdata = { |
aef0bebc TG |
585 | { "off", SPECTRE_V2_CMD_NONE, false }, |
586 | { "on", SPECTRE_V2_CMD_FORCE, true }, | |
587 | { "retpoline", SPECTRE_V2_CMD_RETPOLINE, false }, | |
588 | { "retpoline,amd", SPECTRE_V2_CMD_RETPOLINE_AMD, false }, | |
589 | { "retpoline,generic", SPECTRE_V2_CMD_RETPOLINE_GENERIC, false }, | |
590 | { "auto", SPECTRE_V2_CMD_AUTO, false }, | |
17c33e7c KA |
591 | }; |
592 | ||
10640103 | 593 | static void __init spec_v2_print_cond(const char *reason, bool secure) |
aef0bebc | 594 | { |
10640103 | 595 | if (boot_cpu_has_bug(X86_BUG_SPECTRE_V2) != secure) |
aef0bebc TG |
596 | pr_info("%s selected on command line.\n", reason); |
597 | } | |
598 | ||
da285121 DW |
599 | static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) |
600 | { | |
aef0bebc | 601 | enum spectre_v2_mitigation_cmd cmd = SPECTRE_V2_CMD_AUTO; |
da285121 | 602 | char arg[20]; |
17c33e7c | 603 | int ret, i; |
17c33e7c | 604 | |
2a56e210 JP |
605 | if (cmdline_find_option_bool(boot_command_line, "nospectre_v2") || |
606 | cpu_mitigations_off()) | |
17c33e7c | 607 | return SPECTRE_V2_CMD_NONE; |
17c33e7c | 608 | |
4e8e955a TC |
609 | ret = cmdline_find_option(boot_command_line, "spectre_v2", arg, sizeof(arg)); |
610 | if (ret < 0) | |
611 | return SPECTRE_V2_CMD_AUTO; | |
612 | ||
613 | for (i = 0; i < ARRAY_SIZE(mitigation_options); i++) { | |
614 | if (!match_option(arg, ret, mitigation_options[i].option)) | |
615 | continue; | |
616 | cmd = mitigation_options[i].cmd; | |
617 | break; | |
618 | } | |
619 | ||
620 | if (i >= ARRAY_SIZE(mitigation_options)) { | |
621 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
622 | return SPECTRE_V2_CMD_AUTO; | |
da285121 DW |
623 | } |
624 | ||
17c33e7c KA |
625 | if ((cmd == SPECTRE_V2_CMD_RETPOLINE || |
626 | cmd == SPECTRE_V2_CMD_RETPOLINE_AMD || | |
627 | cmd == SPECTRE_V2_CMD_RETPOLINE_GENERIC) && | |
628 | !IS_ENABLED(CONFIG_RETPOLINE)) { | |
713f1b95 | 629 | pr_err("%s selected but not compiled in. Switching to AUTO select\n", mitigation_options[i].option); |
da285121 | 630 | return SPECTRE_V2_CMD_AUTO; |
17c33e7c KA |
631 | } |
632 | ||
633 | if (cmd == SPECTRE_V2_CMD_RETPOLINE_AMD && | |
634 | boot_cpu_data.x86_vendor != X86_VENDOR_AMD) { | |
635 | pr_err("retpoline,amd selected but CPU is not AMD. Switching to AUTO select\n"); | |
636 | return SPECTRE_V2_CMD_AUTO; | |
637 | } | |
638 | ||
10640103 TG |
639 | spec_v2_print_cond(mitigation_options[i].option, |
640 | mitigation_options[i].secure); | |
17c33e7c | 641 | return cmd; |
da285121 DW |
642 | } |
643 | ||
644 | static void __init spectre_v2_select_mitigation(void) | |
645 | { | |
646 | enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); | |
647 | enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; | |
648 | ||
649 | /* | |
650 | * If the CPU is not affected and the command line mode is NONE or AUTO | |
651 | * then nothing to do. | |
652 | */ | |
653 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2) && | |
654 | (cmd == SPECTRE_V2_CMD_NONE || cmd == SPECTRE_V2_CMD_AUTO)) | |
655 | return; | |
656 | ||
657 | switch (cmd) { | |
658 | case SPECTRE_V2_CMD_NONE: | |
659 | return; | |
660 | ||
661 | case SPECTRE_V2_CMD_FORCE: | |
da285121 | 662 | case SPECTRE_V2_CMD_AUTO: |
1044fde9 SP |
663 | if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { |
664 | mode = SPECTRE_V2_IBRS_ENHANCED; | |
665 | /* Force it so VMEXIT will restore correctly */ | |
666 | x86_spec_ctrl_base |= SPEC_CTRL_IBRS; | |
667 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); | |
668 | goto specv2_set_mode; | |
669 | } | |
d0f293e0 DL |
670 | if (IS_ENABLED(CONFIG_RETPOLINE)) |
671 | goto retpoline_auto; | |
672 | break; | |
da285121 DW |
673 | case SPECTRE_V2_CMD_RETPOLINE_AMD: |
674 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
675 | goto retpoline_amd; | |
676 | break; | |
677 | case SPECTRE_V2_CMD_RETPOLINE_GENERIC: | |
678 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
679 | goto retpoline_generic; | |
680 | break; | |
681 | case SPECTRE_V2_CMD_RETPOLINE: | |
682 | if (IS_ENABLED(CONFIG_RETPOLINE)) | |
683 | goto retpoline_auto; | |
684 | break; | |
685 | } | |
713f1b95 | 686 | pr_err("Spectre mitigation: kernel not compiled with retpoline; no mitigation available!"); |
da285121 DW |
687 | return; |
688 | ||
689 | retpoline_auto: | |
690 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { | |
691 | retpoline_amd: | |
692 | if (!boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { | |
713f1b95 | 693 | pr_err("Spectre mitigation: LFENCE not serializing, switching to generic retpoline\n"); |
da285121 DW |
694 | goto retpoline_generic; |
695 | } | |
51dd01b5 | 696 | mode = SPECTRE_V2_RETPOLINE_AMD; |
da285121 DW |
697 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE_AMD); |
698 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); | |
699 | } else { | |
700 | retpoline_generic: | |
51dd01b5 | 701 | mode = SPECTRE_V2_RETPOLINE_GENERIC; |
da285121 DW |
702 | setup_force_cpu_cap(X86_FEATURE_RETPOLINE); |
703 | } | |
704 | ||
1044fde9 | 705 | specv2_set_mode: |
da285121 DW |
706 | spectre_v2_enabled = mode; |
707 | pr_info("%s\n", spectre_v2_strings[mode]); | |
c995efd5 DW |
708 | |
709 | /* | |
14623a43 JK |
710 | * If spectre v2 protection has been enabled, unconditionally fill |
711 | * RSB during a context switch; this protects against two independent | |
712 | * issues: | |
c995efd5 | 713 | * |
14623a43 JK |
714 | * - RSB underflow (and switch to BTB) on Skylake+ |
715 | * - SpectreRSB variant of spectre v2 on X86_BUG_SPECTRE_V2 CPUs | |
c995efd5 | 716 | */ |
14623a43 JK |
717 | setup_force_cpu_cap(X86_FEATURE_RSB_CTXSW); |
718 | pr_info("Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch\n"); | |
bd12e896 | 719 | |
390b99c3 DW |
720 | /* |
721 | * Retpoline means the kernel is safe because it has no indirect | |
1044fde9 SP |
722 | * branches. Enhanced IBRS protects firmware too, so, enable restricted |
723 | * speculation around firmware calls only when Enhanced IBRS isn't | |
724 | * supported. | |
725 | * | |
726 | * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because | |
727 | * the user might select retpoline on the kernel command line and if | |
728 | * the CPU supports Enhanced IBRS, kernel might un-intentionally not | |
729 | * enable IBRS around firmware calls. | |
390b99c3 | 730 | */ |
1044fde9 | 731 | if (boot_cpu_has(X86_FEATURE_IBRS) && mode != SPECTRE_V2_IBRS_ENHANCED) { |
390b99c3 DW |
732 | setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); |
733 | pr_info("Enabling Restricted Speculation for firmware calls\n"); | |
734 | } | |
7011f443 | 735 | |
6cd930f0 TG |
736 | /* Set up IBPB and STIBP depending on the general spectre V2 command */ |
737 | spectre_v2_user_select_mitigation(cmd); | |
da285121 DW |
738 | } |
739 | ||
984d266f | 740 | static void update_stibp_msr(void * __unused) |
aef0bebc | 741 | { |
984d266f | 742 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
aef0bebc TG |
743 | } |
744 | ||
984d266f TG |
745 | /* Update x86_spec_ctrl_base in case SMT state changed. */ |
746 | static void update_stibp_strict(void) | |
aef0bebc | 747 | { |
984d266f TG |
748 | u64 mask = x86_spec_ctrl_base & ~SPEC_CTRL_STIBP; |
749 | ||
750 | if (sched_smt_active()) | |
751 | mask |= SPEC_CTRL_STIBP; | |
752 | ||
753 | if (mask == x86_spec_ctrl_base) | |
754 | return; | |
755 | ||
756 | pr_info("Update user space SMT mitigation: STIBP %s\n", | |
757 | mask & SPEC_CTRL_STIBP ? "always-on" : "off"); | |
758 | x86_spec_ctrl_base = mask; | |
759 | on_each_cpu(update_stibp_msr, NULL, 1); | |
aef0bebc TG |
760 | } |
761 | ||
2cdf6a58 TG |
762 | /* Update the static key controlling the evaluation of TIF_SPEC_IB */ |
763 | static void update_indir_branch_cond(void) | |
764 | { | |
765 | if (sched_smt_active()) | |
766 | static_branch_enable(&switch_to_cond_stibp); | |
767 | else | |
768 | static_branch_disable(&switch_to_cond_stibp); | |
769 | } | |
770 | ||
0923e77e JP |
771 | #undef pr_fmt |
772 | #define pr_fmt(fmt) fmt | |
773 | ||
fc5ee888 TG |
774 | /* Update the static key controlling the MDS CPU buffer clear in idle */ |
775 | static void update_mds_branch_idle(void) | |
776 | { | |
777 | /* | |
c7ed1048 TH |
778 | * Enable the idle clearing if SMT is active on CPUs which are |
779 | * affected only by MSBDS and not any other MDS variant. | |
780 | * | |
781 | * The other variants cannot be mitigated when SMT is enabled, so | |
782 | * clearing the buffers on idle just to prevent the Store Buffer | |
783 | * repartitioning leak would be a window dressing exercise. | |
fc5ee888 | 784 | */ |
c7ed1048 | 785 | if (!boot_cpu_has_bug(X86_BUG_MSBDS_ONLY)) |
fc5ee888 TG |
786 | return; |
787 | ||
788 | if (sched_smt_active()) | |
789 | static_branch_enable(&mds_idle_clear); | |
790 | else | |
791 | static_branch_disable(&mds_idle_clear); | |
792 | } | |
793 | ||
0923e77e JP |
794 | #define MDS_MSG_SMT "MDS CPU bug present and SMT on, data leak possible. See https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/mds.html for more details.\n" |
795 | ||
aef0bebc TG |
796 | void arch_smt_update(void) |
797 | { | |
984d266f TG |
798 | /* Enhanced IBRS implies STIBP. No update required. */ |
799 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) | |
aef0bebc TG |
800 | return; |
801 | ||
802 | mutex_lock(&spec_ctrl_mutex); | |
803 | ||
984d266f TG |
804 | switch (spectre_v2_user) { |
805 | case SPECTRE_V2_USER_NONE: | |
806 | break; | |
807 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 808 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
984d266f TG |
809 | update_stibp_strict(); |
810 | break; | |
ac40ad3b | 811 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 812 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 | 813 | update_indir_branch_cond(); |
ac40ad3b | 814 | break; |
aef0bebc | 815 | } |
984d266f | 816 | |
c7ed1048 | 817 | switch (mds_mitigation) { |
ebf1e8cb TG |
818 | case MDS_MITIGATION_FULL: |
819 | case MDS_MITIGATION_VMWERV: | |
0923e77e JP |
820 | if (sched_smt_active() && !boot_cpu_has(X86_BUG_MSBDS_ONLY)) |
821 | pr_warn_once(MDS_MSG_SMT); | |
fc5ee888 | 822 | update_mds_branch_idle(); |
ebf1e8cb TG |
823 | break; |
824 | case MDS_MITIGATION_OFF: | |
825 | break; | |
826 | } | |
fc5ee888 | 827 | |
aef0bebc TG |
828 | mutex_unlock(&spec_ctrl_mutex); |
829 | } | |
830 | ||
e63490c8 KRW |
831 | #undef pr_fmt |
832 | #define pr_fmt(fmt) "Speculative Store Bypass: " fmt | |
833 | ||
b5e6d77d | 834 | static enum ssb_mitigation ssb_mode __ro_after_init = SPEC_STORE_BYPASS_NONE; |
e63490c8 KRW |
835 | |
836 | /* The kernel command line selection */ | |
837 | enum ssb_mitigation_cmd { | |
838 | SPEC_STORE_BYPASS_CMD_NONE, | |
839 | SPEC_STORE_BYPASS_CMD_AUTO, | |
840 | SPEC_STORE_BYPASS_CMD_ON, | |
574dcf89 | 841 | SPEC_STORE_BYPASS_CMD_PRCTL, |
c7416003 | 842 | SPEC_STORE_BYPASS_CMD_SECCOMP, |
e63490c8 KRW |
843 | }; |
844 | ||
0eb5928b | 845 | static const char * const ssb_strings[] = { |
e63490c8 | 846 | [SPEC_STORE_BYPASS_NONE] = "Vulnerable", |
574dcf89 | 847 | [SPEC_STORE_BYPASS_DISABLE] = "Mitigation: Speculative Store Bypass disabled", |
c7416003 KC |
848 | [SPEC_STORE_BYPASS_PRCTL] = "Mitigation: Speculative Store Bypass disabled via prctl", |
849 | [SPEC_STORE_BYPASS_SECCOMP] = "Mitigation: Speculative Store Bypass disabled via prctl and seccomp", | |
e63490c8 KRW |
850 | }; |
851 | ||
852 | static const struct { | |
853 | const char *option; | |
854 | enum ssb_mitigation_cmd cmd; | |
5a76cb46 | 855 | } ssb_mitigation_options[] __initdata = { |
c7416003 KC |
856 | { "auto", SPEC_STORE_BYPASS_CMD_AUTO }, /* Platform decides */ |
857 | { "on", SPEC_STORE_BYPASS_CMD_ON }, /* Disable Speculative Store Bypass */ | |
858 | { "off", SPEC_STORE_BYPASS_CMD_NONE }, /* Don't touch Speculative Store Bypass */ | |
859 | { "prctl", SPEC_STORE_BYPASS_CMD_PRCTL }, /* Disable Speculative Store Bypass via prctl */ | |
860 | { "seccomp", SPEC_STORE_BYPASS_CMD_SECCOMP }, /* Disable Speculative Store Bypass via prctl and seccomp */ | |
e63490c8 KRW |
861 | }; |
862 | ||
863 | static enum ssb_mitigation_cmd __init ssb_parse_cmdline(void) | |
864 | { | |
865 | enum ssb_mitigation_cmd cmd = SPEC_STORE_BYPASS_CMD_AUTO; | |
866 | char arg[20]; | |
867 | int ret, i; | |
868 | ||
2a56e210 JP |
869 | if (cmdline_find_option_bool(boot_command_line, "nospec_store_bypass_disable") || |
870 | cpu_mitigations_off()) { | |
e63490c8 KRW |
871 | return SPEC_STORE_BYPASS_CMD_NONE; |
872 | } else { | |
873 | ret = cmdline_find_option(boot_command_line, "spec_store_bypass_disable", | |
874 | arg, sizeof(arg)); | |
875 | if (ret < 0) | |
876 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
877 | ||
878 | for (i = 0; i < ARRAY_SIZE(ssb_mitigation_options); i++) { | |
879 | if (!match_option(arg, ret, ssb_mitigation_options[i].option)) | |
880 | continue; | |
881 | ||
882 | cmd = ssb_mitigation_options[i].cmd; | |
883 | break; | |
884 | } | |
885 | ||
886 | if (i >= ARRAY_SIZE(ssb_mitigation_options)) { | |
887 | pr_err("unknown option (%s). Switching to AUTO select\n", arg); | |
888 | return SPEC_STORE_BYPASS_CMD_AUTO; | |
889 | } | |
890 | } | |
891 | ||
892 | return cmd; | |
893 | } | |
894 | ||
dbe3009d | 895 | static enum ssb_mitigation __init __ssb_select_mitigation(void) |
e63490c8 KRW |
896 | { |
897 | enum ssb_mitigation mode = SPEC_STORE_BYPASS_NONE; | |
898 | enum ssb_mitigation_cmd cmd; | |
899 | ||
8fe36c9d | 900 | if (!boot_cpu_has(X86_FEATURE_SSBD)) |
e63490c8 KRW |
901 | return mode; |
902 | ||
903 | cmd = ssb_parse_cmdline(); | |
904 | if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS) && | |
905 | (cmd == SPEC_STORE_BYPASS_CMD_NONE || | |
906 | cmd == SPEC_STORE_BYPASS_CMD_AUTO)) | |
907 | return mode; | |
908 | ||
909 | switch (cmd) { | |
910 | case SPEC_STORE_BYPASS_CMD_AUTO: | |
c7416003 KC |
911 | case SPEC_STORE_BYPASS_CMD_SECCOMP: |
912 | /* | |
913 | * Choose prctl+seccomp as the default mode if seccomp is | |
914 | * enabled. | |
915 | */ | |
916 | if (IS_ENABLED(CONFIG_SECCOMP)) | |
917 | mode = SPEC_STORE_BYPASS_SECCOMP; | |
918 | else | |
919 | mode = SPEC_STORE_BYPASS_PRCTL; | |
574dcf89 | 920 | break; |
e63490c8 KRW |
921 | case SPEC_STORE_BYPASS_CMD_ON: |
922 | mode = SPEC_STORE_BYPASS_DISABLE; | |
923 | break; | |
574dcf89 TG |
924 | case SPEC_STORE_BYPASS_CMD_PRCTL: |
925 | mode = SPEC_STORE_BYPASS_PRCTL; | |
926 | break; | |
e63490c8 KRW |
927 | case SPEC_STORE_BYPASS_CMD_NONE: |
928 | break; | |
929 | } | |
930 | ||
23b9eab9 KRW |
931 | /* |
932 | * We have three CPU feature flags that are in play here: | |
933 | * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible. | |
8fe36c9d | 934 | * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass |
23b9eab9 KRW |
935 | * - X86_FEATURE_SPEC_STORE_BYPASS_DISABLE - engage the mitigation |
936 | */ | |
574dcf89 | 937 | if (mode == SPEC_STORE_BYPASS_DISABLE) { |
e63490c8 | 938 | setup_force_cpu_cap(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE); |
23b9eab9 | 939 | /* |
3b881627 KRW |
940 | * Intel uses the SPEC CTRL MSR Bit(2) for this, while AMD may |
941 | * use a completely different MSR and bit dependent on family. | |
23b9eab9 | 942 | */ |
5005c716 TL |
943 | if (!static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) && |
944 | !static_cpu_has(X86_FEATURE_AMD_SSBD)) { | |
733c54c9 | 945 | x86_amd_ssb_disable(); |
5005c716 | 946 | } else { |
8fe36c9d | 947 | x86_spec_ctrl_base |= SPEC_CTRL_SSBD; |
e5f984ed | 948 | x86_spec_ctrl_mask |= SPEC_CTRL_SSBD; |
208efa83 | 949 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
23b9eab9 KRW |
950 | } |
951 | } | |
952 | ||
e63490c8 KRW |
953 | return mode; |
954 | } | |
955 | ||
043d480e | 956 | static void ssb_select_mitigation(void) |
e63490c8 KRW |
957 | { |
958 | ssb_mode = __ssb_select_mitigation(); | |
959 | ||
960 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
961 | pr_info("%s\n", ssb_strings[ssb_mode]); | |
962 | } | |
963 | ||
da285121 | 964 | #undef pr_fmt |
c7416003 | 965 | #define pr_fmt(fmt) "Speculation prctl: " fmt |
da285121 | 966 | |
801d6893 | 967 | static void task_update_spec_tif(struct task_struct *tsk) |
574dcf89 | 968 | { |
801d6893 TG |
969 | /* Force the update of the real TIF bits */ |
970 | set_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE); | |
d4595948 TG |
971 | |
972 | /* | |
973 | * Immediately update the speculation control MSRs for the current | |
974 | * task, but for a non-current task delay setting the CPU | |
975 | * mitigation until it is scheduled next. | |
976 | * | |
977 | * This can only happen for SECCOMP mitigation. For PRCTL it's | |
978 | * always the current task. | |
979 | */ | |
801d6893 | 980 | if (tsk == current) |
d4595948 TG |
981 | speculation_ctrl_update_current(); |
982 | } | |
983 | ||
984 | static int ssb_prctl_set(struct task_struct *task, unsigned long ctrl) | |
985 | { | |
c7416003 KC |
986 | if (ssb_mode != SPEC_STORE_BYPASS_PRCTL && |
987 | ssb_mode != SPEC_STORE_BYPASS_SECCOMP) | |
574dcf89 TG |
988 | return -ENXIO; |
989 | ||
733f4234 TG |
990 | switch (ctrl) { |
991 | case PR_SPEC_ENABLE: | |
992 | /* If speculation is force disabled, enable is not allowed */ | |
993 | if (task_spec_ssb_force_disable(task)) | |
994 | return -EPERM; | |
995 | task_clear_spec_ssb_disable(task); | |
801d6893 | 996 | task_update_spec_tif(task); |
733f4234 TG |
997 | break; |
998 | case PR_SPEC_DISABLE: | |
999 | task_set_spec_ssb_disable(task); | |
801d6893 | 1000 | task_update_spec_tif(task); |
733f4234 TG |
1001 | break; |
1002 | case PR_SPEC_FORCE_DISABLE: | |
1003 | task_set_spec_ssb_disable(task); | |
1004 | task_set_spec_ssb_force_disable(task); | |
801d6893 | 1005 | task_update_spec_tif(task); |
733f4234 TG |
1006 | break; |
1007 | default: | |
1008 | return -ERANGE; | |
1009 | } | |
574dcf89 TG |
1010 | return 0; |
1011 | } | |
1012 | ||
ac40ad3b TG |
1013 | static int ib_prctl_set(struct task_struct *task, unsigned long ctrl) |
1014 | { | |
1015 | switch (ctrl) { | |
1016 | case PR_SPEC_ENABLE: | |
1017 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
1018 | return 0; | |
1019 | /* | |
1020 | * Indirect branch speculation is always disabled in strict | |
1021 | * mode. | |
1022 | */ | |
fbed8eca TL |
1023 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
1024 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
1025 | return -EPERM; |
1026 | task_clear_spec_ib_disable(task); | |
1027 | task_update_spec_tif(task); | |
1028 | break; | |
1029 | case PR_SPEC_DISABLE: | |
1030 | case PR_SPEC_FORCE_DISABLE: | |
1031 | /* | |
1032 | * Indirect branch speculation is always allowed when | |
1033 | * mitigation is force disabled. | |
1034 | */ | |
1035 | if (spectre_v2_user == SPECTRE_V2_USER_NONE) | |
1036 | return -EPERM; | |
fbed8eca TL |
1037 | if (spectre_v2_user == SPECTRE_V2_USER_STRICT || |
1038 | spectre_v2_user == SPECTRE_V2_USER_STRICT_PREFERRED) | |
ac40ad3b TG |
1039 | return 0; |
1040 | task_set_spec_ib_disable(task); | |
1041 | if (ctrl == PR_SPEC_FORCE_DISABLE) | |
1042 | task_set_spec_ib_force_disable(task); | |
1043 | task_update_spec_tif(task); | |
1044 | break; | |
1045 | default: | |
1046 | return -ERANGE; | |
1047 | } | |
1048 | return 0; | |
1049 | } | |
1050 | ||
5b38e244 TG |
1051 | int arch_prctl_spec_ctrl_set(struct task_struct *task, unsigned long which, |
1052 | unsigned long ctrl) | |
1053 | { | |
1054 | switch (which) { | |
1055 | case PR_SPEC_STORE_BYPASS: | |
1056 | return ssb_prctl_set(task, ctrl); | |
ac40ad3b TG |
1057 | case PR_SPEC_INDIRECT_BRANCH: |
1058 | return ib_prctl_set(task, ctrl); | |
5b38e244 TG |
1059 | default: |
1060 | return -ENODEV; | |
1061 | } | |
1062 | } | |
1063 | ||
1064 | #ifdef CONFIG_SECCOMP | |
1065 | void arch_seccomp_spec_mitigate(struct task_struct *task) | |
1066 | { | |
c7416003 KC |
1067 | if (ssb_mode == SPEC_STORE_BYPASS_SECCOMP) |
1068 | ssb_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
1c3cf627 TG |
1069 | if (spectre_v2_user == SPECTRE_V2_USER_SECCOMP) |
1070 | ib_prctl_set(task, PR_SPEC_FORCE_DISABLE); | |
5b38e244 TG |
1071 | } |
1072 | #endif | |
1073 | ||
199bfed2 | 1074 | static int ssb_prctl_get(struct task_struct *task) |
574dcf89 TG |
1075 | { |
1076 | switch (ssb_mode) { | |
1077 | case SPEC_STORE_BYPASS_DISABLE: | |
1078 | return PR_SPEC_DISABLE; | |
c7416003 | 1079 | case SPEC_STORE_BYPASS_SECCOMP: |
574dcf89 | 1080 | case SPEC_STORE_BYPASS_PRCTL: |
733f4234 TG |
1081 | if (task_spec_ssb_force_disable(task)) |
1082 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
1083 | if (task_spec_ssb_disable(task)) | |
574dcf89 TG |
1084 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; |
1085 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1086 | default: | |
1087 | if (boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) | |
1088 | return PR_SPEC_ENABLE; | |
1089 | return PR_SPEC_NOT_AFFECTED; | |
1090 | } | |
1091 | } | |
1092 | ||
ac40ad3b TG |
1093 | static int ib_prctl_get(struct task_struct *task) |
1094 | { | |
1095 | if (!boot_cpu_has_bug(X86_BUG_SPECTRE_V2)) | |
1096 | return PR_SPEC_NOT_AFFECTED; | |
1097 | ||
1098 | switch (spectre_v2_user) { | |
1099 | case SPECTRE_V2_USER_NONE: | |
1100 | return PR_SPEC_ENABLE; | |
1101 | case SPECTRE_V2_USER_PRCTL: | |
1c3cf627 | 1102 | case SPECTRE_V2_USER_SECCOMP: |
ac40ad3b TG |
1103 | if (task_spec_ib_force_disable(task)) |
1104 | return PR_SPEC_PRCTL | PR_SPEC_FORCE_DISABLE; | |
1105 | if (task_spec_ib_disable(task)) | |
1106 | return PR_SPEC_PRCTL | PR_SPEC_DISABLE; | |
1107 | return PR_SPEC_PRCTL | PR_SPEC_ENABLE; | |
1108 | case SPECTRE_V2_USER_STRICT: | |
fbed8eca | 1109 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
ac40ad3b TG |
1110 | return PR_SPEC_DISABLE; |
1111 | default: | |
1112 | return PR_SPEC_NOT_AFFECTED; | |
1113 | } | |
1114 | } | |
1115 | ||
199bfed2 | 1116 | int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which) |
574dcf89 TG |
1117 | { |
1118 | switch (which) { | |
1119 | case PR_SPEC_STORE_BYPASS: | |
199bfed2 | 1120 | return ssb_prctl_get(task); |
ac40ad3b TG |
1121 | case PR_SPEC_INDIRECT_BRANCH: |
1122 | return ib_prctl_get(task); | |
574dcf89 TG |
1123 | default: |
1124 | return -ENODEV; | |
1125 | } | |
1126 | } | |
1127 | ||
23b9eab9 KRW |
1128 | void x86_spec_ctrl_setup_ap(void) |
1129 | { | |
50f9b919 | 1130 | if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) |
208efa83 | 1131 | wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); |
c37b94dd KRW |
1132 | |
1133 | if (ssb_mode == SPEC_STORE_BYPASS_DISABLE) | |
8fe36c9d | 1134 | x86_amd_ssb_disable(); |
23b9eab9 KRW |
1135 | } |
1136 | ||
73ca9f47 KRW |
1137 | #undef pr_fmt |
1138 | #define pr_fmt(fmt) "L1TF: " fmt | |
b9cfedcd | 1139 | |
24fcb53c JK |
1140 | /* Default mitigation for L1TF-affected CPUs */ |
1141 | enum l1tf_mitigations l1tf_mitigation __ro_after_init = L1TF_MITIGATION_FLUSH; | |
b9cfedcd | 1142 | #if IS_ENABLED(CONFIG_KVM_INTEL) |
24fcb53c | 1143 | EXPORT_SYMBOL_GPL(l1tf_mitigation); |
47bb1124 | 1144 | #endif |
522c7bed | 1145 | enum vmx_l1d_flush_state l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; |
b9cfedcd | 1146 | EXPORT_SYMBOL_GPL(l1tf_vmx_mitigation); |
b9cfedcd | 1147 | |
f1f016ed AK |
1148 | /* |
1149 | * These CPUs all support 44bits physical address space internally in the | |
1150 | * cache but CPUID can report a smaller number of physical address bits. | |
1151 | * | |
1152 | * The L1TF mitigation uses the top most address bit for the inversion of | |
1153 | * non present PTEs. When the installed memory reaches into the top most | |
1154 | * address bit due to memory holes, which has been observed on machines | |
1155 | * which report 36bits physical address bits and have 32G RAM installed, | |
1156 | * then the mitigation range check in l1tf_select_mitigation() triggers. | |
1157 | * This is a false positive because the mitigation is still possible due to | |
1158 | * the fact that the cache uses 44bit internally. Use the cache bits | |
1159 | * instead of the reported physical bits and adjust them on the affected | |
1160 | * machines to 44bit if the reported bits are less than 44. | |
1161 | */ | |
1162 | static void override_cache_bits(struct cpuinfo_x86 *c) | |
1163 | { | |
1164 | if (c->x86 != 6) | |
1165 | return; | |
1166 | ||
1167 | switch (c->x86_model) { | |
1168 | case INTEL_FAM6_NEHALEM: | |
1169 | case INTEL_FAM6_WESTMERE: | |
1170 | case INTEL_FAM6_SANDYBRIDGE: | |
1171 | case INTEL_FAM6_IVYBRIDGE: | |
1172 | case INTEL_FAM6_HASWELL_CORE: | |
1173 | case INTEL_FAM6_HASWELL_ULT: | |
1174 | case INTEL_FAM6_HASWELL_GT3E: | |
1175 | case INTEL_FAM6_BROADWELL_CORE: | |
1176 | case INTEL_FAM6_BROADWELL_GT3E: | |
1177 | case INTEL_FAM6_SKYLAKE_MOBILE: | |
1178 | case INTEL_FAM6_SKYLAKE_DESKTOP: | |
1179 | case INTEL_FAM6_KABYLAKE_MOBILE: | |
1180 | case INTEL_FAM6_KABYLAKE_DESKTOP: | |
1181 | if (c->x86_cache_bits < 44) | |
1182 | c->x86_cache_bits = 44; | |
1183 | break; | |
1184 | } | |
1185 | } | |
1186 | ||
73ca9f47 KRW |
1187 | static void __init l1tf_select_mitigation(void) |
1188 | { | |
1189 | u64 half_pa; | |
1190 | ||
1191 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1192 | return; | |
1193 | ||
2a56e210 JP |
1194 | if (cpu_mitigations_off()) |
1195 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1196 | else if (cpu_mitigations_auto_nosmt()) | |
1197 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1198 | ||
f1f016ed AK |
1199 | override_cache_bits(&boot_cpu_data); |
1200 | ||
24fcb53c JK |
1201 | switch (l1tf_mitigation) { |
1202 | case L1TF_MITIGATION_OFF: | |
1203 | case L1TF_MITIGATION_FLUSH_NOWARN: | |
1204 | case L1TF_MITIGATION_FLUSH: | |
1205 | break; | |
1206 | case L1TF_MITIGATION_FLUSH_NOSMT: | |
1207 | case L1TF_MITIGATION_FULL: | |
1208 | cpu_smt_disable(false); | |
1209 | break; | |
1210 | case L1TF_MITIGATION_FULL_FORCE: | |
1211 | cpu_smt_disable(true); | |
1212 | break; | |
1213 | } | |
1214 | ||
73ca9f47 KRW |
1215 | #if CONFIG_PGTABLE_LEVELS == 2 |
1216 | pr_warn("Kernel not compiled for PAE. No mitigation for L1TF\n"); | |
1217 | return; | |
1218 | #endif | |
1219 | ||
73ca9f47 KRW |
1220 | half_pa = (u64)l1tf_pfn_limit() << PAGE_SHIFT; |
1221 | if (e820__mapped_any(half_pa, ULLONG_MAX - half_pa, E820_TYPE_RAM)) { | |
1222 | pr_warn("System has more than MAX_PA/2 memory. L1TF mitigation not effective.\n"); | |
f80e341a VB |
1223 | pr_info("You may make it effective by booting the kernel with mem=%llu parameter.\n", |
1224 | half_pa); | |
1225 | pr_info("However, doing so will make a part of your RAM unusable.\n"); | |
c7ed1048 | 1226 | pr_info("Reading https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html might help you decide.\n"); |
73ca9f47 KRW |
1227 | return; |
1228 | } | |
1229 | ||
1230 | setup_force_cpu_cap(X86_FEATURE_L1TF_PTEINV); | |
1231 | } | |
24fcb53c JK |
1232 | |
1233 | static int __init l1tf_cmdline(char *str) | |
1234 | { | |
1235 | if (!boot_cpu_has_bug(X86_BUG_L1TF)) | |
1236 | return 0; | |
1237 | ||
1238 | if (!str) | |
1239 | return -EINVAL; | |
1240 | ||
1241 | if (!strcmp(str, "off")) | |
1242 | l1tf_mitigation = L1TF_MITIGATION_OFF; | |
1243 | else if (!strcmp(str, "flush,nowarn")) | |
1244 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOWARN; | |
1245 | else if (!strcmp(str, "flush")) | |
1246 | l1tf_mitigation = L1TF_MITIGATION_FLUSH; | |
1247 | else if (!strcmp(str, "flush,nosmt")) | |
1248 | l1tf_mitigation = L1TF_MITIGATION_FLUSH_NOSMT; | |
1249 | else if (!strcmp(str, "full")) | |
1250 | l1tf_mitigation = L1TF_MITIGATION_FULL; | |
1251 | else if (!strcmp(str, "full,force")) | |
1252 | l1tf_mitigation = L1TF_MITIGATION_FULL_FORCE; | |
1253 | ||
1254 | return 0; | |
1255 | } | |
1256 | early_param("l1tf", l1tf_cmdline); | |
1257 | ||
73ca9f47 | 1258 | #undef pr_fmt |
0923e77e | 1259 | #define pr_fmt(fmt) fmt |
73ca9f47 | 1260 | |
61dc0f55 | 1261 | #ifdef CONFIG_SYSFS |
d2b8fc2d | 1262 | |
b9cfedcd TG |
1263 | #define L1TF_DEFAULT_MSG "Mitigation: PTE Inversion" |
1264 | ||
1265 | #if IS_ENABLED(CONFIG_KVM_INTEL) | |
0eb5928b | 1266 | static const char * const l1tf_vmx_states[] = { |
1ead4979 TG |
1267 | [VMENTER_L1D_FLUSH_AUTO] = "auto", |
1268 | [VMENTER_L1D_FLUSH_NEVER] = "vulnerable", | |
1269 | [VMENTER_L1D_FLUSH_COND] = "conditional cache flushes", | |
1270 | [VMENTER_L1D_FLUSH_ALWAYS] = "cache flushes", | |
1271 | [VMENTER_L1D_FLUSH_EPT_DISABLED] = "EPT disabled", | |
364a4311 | 1272 | [VMENTER_L1D_FLUSH_NOT_REQUIRED] = "flush not necessary" |
b9cfedcd TG |
1273 | }; |
1274 | ||
1275 | static ssize_t l1tf_show_state(char *buf) | |
1276 | { | |
1277 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) | |
1278 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1279 | ||
3899f7b1 PB |
1280 | if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_EPT_DISABLED || |
1281 | (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER && | |
8bc59ba0 | 1282 | sched_smt_active())) { |
3899f7b1 PB |
1283 | return sprintf(buf, "%s; VMX: %s\n", L1TF_DEFAULT_MSG, |
1284 | l1tf_vmx_states[l1tf_vmx_mitigation]); | |
8bc59ba0 | 1285 | } |
3899f7b1 PB |
1286 | |
1287 | return sprintf(buf, "%s; VMX: %s, SMT %s\n", L1TF_DEFAULT_MSG, | |
1288 | l1tf_vmx_states[l1tf_vmx_mitigation], | |
8bc59ba0 | 1289 | sched_smt_active() ? "vulnerable" : "disabled"); |
b9cfedcd TG |
1290 | } |
1291 | #else | |
1292 | static ssize_t l1tf_show_state(char *buf) | |
1293 | { | |
1294 | return sprintf(buf, "%s\n", L1TF_DEFAULT_MSG); | |
1295 | } | |
1296 | #endif | |
1297 | ||
1122cc78 TG |
1298 | static ssize_t mds_show_state(char *buf) |
1299 | { | |
1300 | if (!hypervisor_is_type(X86_HYPER_NATIVE)) { | |
1301 | return sprintf(buf, "%s; SMT Host state unknown\n", | |
1302 | mds_strings[mds_mitigation]); | |
1303 | } | |
1304 | ||
1305 | if (boot_cpu_has(X86_BUG_MSBDS_ONLY)) { | |
1306 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
5c89a99c KRW |
1307 | (mds_mitigation == MDS_MITIGATION_OFF ? "vulnerable" : |
1308 | sched_smt_active() ? "mitigated" : "disabled")); | |
1122cc78 TG |
1309 | } |
1310 | ||
1311 | return sprintf(buf, "%s; SMT %s\n", mds_strings[mds_mitigation], | |
1312 | sched_smt_active() ? "vulnerable" : "disabled"); | |
1313 | } | |
1314 | ||
2daa53e8 TC |
1315 | static char *stibp_state(void) |
1316 | { | |
4a8d91c8 TC |
1317 | if (spectre_v2_enabled == SPECTRE_V2_IBRS_ENHANCED) |
1318 | return ""; | |
1319 | ||
6cd930f0 TG |
1320 | switch (spectre_v2_user) { |
1321 | case SPECTRE_V2_USER_NONE: | |
1322 | return ", STIBP: disabled"; | |
1323 | case SPECTRE_V2_USER_STRICT: | |
1324 | return ", STIBP: forced"; | |
fbed8eca TL |
1325 | case SPECTRE_V2_USER_STRICT_PREFERRED: |
1326 | return ", STIBP: always-on"; | |
ac40ad3b | 1327 | case SPECTRE_V2_USER_PRCTL: |
1c3cf627 | 1328 | case SPECTRE_V2_USER_SECCOMP: |
2cdf6a58 TG |
1329 | if (static_key_enabled(&switch_to_cond_stibp)) |
1330 | return ", STIBP: conditional"; | |
6cd930f0 TG |
1331 | } |
1332 | return ""; | |
2daa53e8 TC |
1333 | } |
1334 | ||
1335 | static char *ibpb_state(void) | |
1336 | { | |
58b2d4c8 | 1337 | if (boot_cpu_has(X86_FEATURE_IBPB)) { |
2cdf6a58 | 1338 | if (static_key_enabled(&switch_mm_always_ibpb)) |
58b2d4c8 | 1339 | return ", IBPB: always-on"; |
2cdf6a58 TG |
1340 | if (static_key_enabled(&switch_mm_cond_ibpb)) |
1341 | return ", IBPB: conditional"; | |
1342 | return ", IBPB: disabled"; | |
58b2d4c8 TG |
1343 | } |
1344 | return ""; | |
2daa53e8 TC |
1345 | } |
1346 | ||
ace051d5 | 1347 | static ssize_t cpu_show_common(struct device *dev, struct device_attribute *attr, |
043d480e | 1348 | char *buf, unsigned int bug) |
61dc0f55 | 1349 | { |
d2b8fc2d | 1350 | if (!boot_cpu_has_bug(bug)) |
61dc0f55 | 1351 | return sprintf(buf, "Not affected\n"); |
d2b8fc2d KRW |
1352 | |
1353 | switch (bug) { | |
1354 | case X86_BUG_CPU_MELTDOWN: | |
1355 | if (boot_cpu_has(X86_FEATURE_PTI)) | |
1356 | return sprintf(buf, "Mitigation: PTI\n"); | |
1357 | ||
1358 | break; | |
1359 | ||
1360 | case X86_BUG_SPECTRE_V1: | |
1592edce | 1361 | return sprintf(buf, "%s\n", spectre_v1_strings[spectre_v1_mitigation]); |
d2b8fc2d KRW |
1362 | |
1363 | case X86_BUG_SPECTRE_V2: | |
0b96b80d | 1364 | return sprintf(buf, "%s%s%s%s%s%s\n", spectre_v2_strings[spectre_v2_enabled], |
2daa53e8 | 1365 | ibpb_state(), |
d2b8fc2d | 1366 | boot_cpu_has(X86_FEATURE_USE_IBRS_FW) ? ", IBRS_FW" : "", |
2daa53e8 | 1367 | stibp_state(), |
5e2fafd5 | 1368 | boot_cpu_has(X86_FEATURE_RSB_CTXSW) ? ", RSB filling" : "", |
d2b8fc2d KRW |
1369 | spectre_v2_module_string()); |
1370 | ||
e63490c8 KRW |
1371 | case X86_BUG_SPEC_STORE_BYPASS: |
1372 | return sprintf(buf, "%s\n", ssb_strings[ssb_mode]); | |
1373 | ||
05516ad8 AK |
1374 | case X86_BUG_L1TF: |
1375 | if (boot_cpu_has(X86_FEATURE_L1TF_PTEINV)) | |
b9cfedcd | 1376 | return l1tf_show_state(buf); |
05516ad8 | 1377 | break; |
1122cc78 TG |
1378 | |
1379 | case X86_BUG_MDS: | |
1380 | return mds_show_state(buf); | |
1381 | ||
d2b8fc2d KRW |
1382 | default: |
1383 | break; | |
1384 | } | |
1385 | ||
61dc0f55 TG |
1386 | return sprintf(buf, "Vulnerable\n"); |
1387 | } | |
1388 | ||
d2b8fc2d KRW |
1389 | ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, char *buf) |
1390 | { | |
1391 | return cpu_show_common(dev, attr, buf, X86_BUG_CPU_MELTDOWN); | |
1392 | } | |
1393 | ||
713f1b95 | 1394 | ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1395 | { |
d2b8fc2d | 1396 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V1); |
61dc0f55 TG |
1397 | } |
1398 | ||
713f1b95 | 1399 | ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) |
61dc0f55 | 1400 | { |
d2b8fc2d | 1401 | return cpu_show_common(dev, attr, buf, X86_BUG_SPECTRE_V2); |
61dc0f55 | 1402 | } |
d7de9182 KRW |
1403 | |
1404 | ssize_t cpu_show_spec_store_bypass(struct device *dev, struct device_attribute *attr, char *buf) | |
1405 | { | |
1406 | return cpu_show_common(dev, attr, buf, X86_BUG_SPEC_STORE_BYPASS); | |
1407 | } | |
05516ad8 AK |
1408 | |
1409 | ssize_t cpu_show_l1tf(struct device *dev, struct device_attribute *attr, char *buf) | |
1410 | { | |
1411 | return cpu_show_common(dev, attr, buf, X86_BUG_L1TF); | |
1412 | } | |
1122cc78 TG |
1413 | |
1414 | ssize_t cpu_show_mds(struct device *dev, struct device_attribute *attr, char *buf) | |
1415 | { | |
1416 | return cpu_show_common(dev, attr, buf, X86_BUG_MDS); | |
1417 | } | |
61dc0f55 | 1418 | #endif |