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KVM: VMX: shadow VM_(ENTRY|EXIT)_CONTROLS vmcs field
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
2961e876
GN		 421 u32 vm_entry_controls_shadow;
422 u32 vm_exit_controls_shadow;
d462b819
NHE		 423 /*
424 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
425 * non-nested (L1) guest, it always points to vmcs01. For a nested
426 * guest (L2), it points to a different VMCS.
427 */
428 struct loaded_vmcs vmcs01;
429 struct loaded_vmcs *loaded_vmcs;
430 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 431 struct msr_autoload {
432 unsigned nr;
433 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
434 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
435 } msr_autoload;
a2fa3e9f
GH		 436 struct {
437 int loaded;
438 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 439#ifdef CONFIG_X86_64
440 u16 ds_sel, es_sel;
441#endif
152d3f2f
LV		 442 int gs_ldt_reload_needed;
443 int fs_reload_needed;
d77c26fc 444 } host_state;
9c8cba37 445 struct {
7ffd92c5 446 int vm86_active;
78ac8b47 447 ulong save_rflags;
f5f7b2fe
AK		 448 struct kvm_segment segs[8];
449 } rmode;
450 struct {
451 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 452 struct kvm_save_segment {
453 u16 selector;
454 unsigned long base;
455 u32 limit;
456 u32 ar;
f5f7b2fe 457 } seg[8];
2fb92db1 458 } segment_cache;
2384d2b3 459 int vpid;
04fa4d32 460 bool emulation_required;
3b86cd99
JK		 461
462 /* Support for vnmi-less CPUs */
463 int soft_vnmi_blocked;
464 ktime_t entry_time;
465 s64 vnmi_blocked_time;
a0861c02 466 u32 exit_reason;
4e47c7a6
SY		 467
468 bool rdtscp_enabled;
ec378aee 469
01e439be
YZ		 470 /* Posted interrupt descriptor */
471 struct pi_desc pi_desc;
472
ec378aee
NHE		 473 /* Support for a guest hypervisor (nested VMX) */
474 struct nested_vmx nested;
a2fa3e9f
GH		 475};
476
2fb92db1
AK		 477enum segment_cache_field {
478 SEG_FIELD_SEL = 0,
479 SEG_FIELD_BASE = 1,
480 SEG_FIELD_LIMIT = 2,
481 SEG_FIELD_AR = 3,
482
483 SEG_FIELD_NR = 4
484};
485
a2fa3e9f
GH		 486static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
487{
fb3f0f51 488 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 489}
490
22bd0358
NHE		 491#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
492#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
493#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
494 [number##_HIGH] = VMCS12_OFFSET(name)+4
495
4607c2d7
AG		 496
497static const unsigned long shadow_read_only_fields[] = {
498 /*
499 * We do NOT shadow fields that are modified when L0
500 * traps and emulates any vmx instruction (e.g. VMPTRLD,
501 * VMXON...) executed by L1.
502 * For example, VM_INSTRUCTION_ERROR is read
503 * by L1 if a vmx instruction fails (part of the error path).
504 * Note the code assumes this logic. If for some reason
505 * we start shadowing these fields then we need to
506 * force a shadow sync when L0 emulates vmx instructions
507 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
508 * by nested_vmx_failValid)
509 */
510 VM_EXIT_REASON,
511 VM_EXIT_INTR_INFO,
512 VM_EXIT_INSTRUCTION_LEN,
513 IDT_VECTORING_INFO_FIELD,
514 IDT_VECTORING_ERROR_CODE,
515 VM_EXIT_INTR_ERROR_CODE,
516 EXIT_QUALIFICATION,
517 GUEST_LINEAR_ADDRESS,
518 GUEST_PHYSICAL_ADDRESS
519};
520static const int max_shadow_read_only_fields =
521 ARRAY_SIZE(shadow_read_only_fields);
522
523static const unsigned long shadow_read_write_fields[] = {
524 GUEST_RIP,
525 GUEST_RSP,
526 GUEST_CR0,
527 GUEST_CR3,
528 GUEST_CR4,
529 GUEST_INTERRUPTIBILITY_INFO,
530 GUEST_RFLAGS,
531 GUEST_CS_SELECTOR,
532 GUEST_CS_AR_BYTES,
533 GUEST_CS_LIMIT,
534 GUEST_CS_BASE,
535 GUEST_ES_BASE,
536 CR0_GUEST_HOST_MASK,
537 CR0_READ_SHADOW,
538 CR4_READ_SHADOW,
539 TSC_OFFSET,
540 EXCEPTION_BITMAP,
541 CPU_BASED_VM_EXEC_CONTROL,
542 VM_ENTRY_EXCEPTION_ERROR_CODE,
543 VM_ENTRY_INTR_INFO_FIELD,
544 VM_ENTRY_INSTRUCTION_LEN,
545 VM_ENTRY_EXCEPTION_ERROR_CODE,
546 HOST_FS_BASE,
547 HOST_GS_BASE,
548 HOST_FS_SELECTOR,
549 HOST_GS_SELECTOR
550};
551static const int max_shadow_read_write_fields =
552 ARRAY_SIZE(shadow_read_write_fields);
553
772e0318 554static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 555 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
556 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
557 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
558 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
559 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
560 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
561 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
562 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
563 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
564 FIELD(HOST_ES_SELECTOR, host_es_selector),
565 FIELD(HOST_CS_SELECTOR, host_cs_selector),
566 FIELD(HOST_SS_SELECTOR, host_ss_selector),
567 FIELD(HOST_DS_SELECTOR, host_ds_selector),
568 FIELD(HOST_FS_SELECTOR, host_fs_selector),
569 FIELD(HOST_GS_SELECTOR, host_gs_selector),
570 FIELD(HOST_TR_SELECTOR, host_tr_selector),
571 FIELD64(IO_BITMAP_A, io_bitmap_a),
572 FIELD64(IO_BITMAP_B, io_bitmap_b),
573 FIELD64(MSR_BITMAP, msr_bitmap),
574 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
575 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
576 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
577 FIELD64(TSC_OFFSET, tsc_offset),
578 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
579 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
580 FIELD64(EPT_POINTER, ept_pointer),
581 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
582 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
583 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
584 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
585 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
586 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
587 FIELD64(GUEST_PDPTR0, guest_pdptr0),
588 FIELD64(GUEST_PDPTR1, guest_pdptr1),
589 FIELD64(GUEST_PDPTR2, guest_pdptr2),
590 FIELD64(GUEST_PDPTR3, guest_pdptr3),
591 FIELD64(HOST_IA32_PAT, host_ia32_pat),
592 FIELD64(HOST_IA32_EFER, host_ia32_efer),
593 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
594 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
595 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
596 FIELD(EXCEPTION_BITMAP, exception_bitmap),
597 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
598 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
599 FIELD(CR3_TARGET_COUNT, cr3_target_count),
600 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
601 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
602 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
603 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
604 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
605 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
606 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
607 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
608 FIELD(TPR_THRESHOLD, tpr_threshold),
609 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
610 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
611 FIELD(VM_EXIT_REASON, vm_exit_reason),
612 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
613 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
614 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
615 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
616 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
617 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
618 FIELD(GUEST_ES_LIMIT, guest_es_limit),
619 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
620 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
621 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
622 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
623 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
624 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
625 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
626 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
627 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
628 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
629 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
630 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
631 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
632 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
633 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
634 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
635 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
636 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
637 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
638 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
639 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 640 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 641 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
642 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
643 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
644 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
645 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
646 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
647 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
648 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
649 FIELD(EXIT_QUALIFICATION, exit_qualification),
650 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
651 FIELD(GUEST_CR0, guest_cr0),
652 FIELD(GUEST_CR3, guest_cr3),
653 FIELD(GUEST_CR4, guest_cr4),
654 FIELD(GUEST_ES_BASE, guest_es_base),
655 FIELD(GUEST_CS_BASE, guest_cs_base),
656 FIELD(GUEST_SS_BASE, guest_ss_base),
657 FIELD(GUEST_DS_BASE, guest_ds_base),
658 FIELD(GUEST_FS_BASE, guest_fs_base),
659 FIELD(GUEST_GS_BASE, guest_gs_base),
660 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
661 FIELD(GUEST_TR_BASE, guest_tr_base),
662 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
663 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
664 FIELD(GUEST_DR7, guest_dr7),
665 FIELD(GUEST_RSP, guest_rsp),
666 FIELD(GUEST_RIP, guest_rip),
667 FIELD(GUEST_RFLAGS, guest_rflags),
668 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
669 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
670 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
671 FIELD(HOST_CR0, host_cr0),
672 FIELD(HOST_CR3, host_cr3),
673 FIELD(HOST_CR4, host_cr4),
674 FIELD(HOST_FS_BASE, host_fs_base),
675 FIELD(HOST_GS_BASE, host_gs_base),
676 FIELD(HOST_TR_BASE, host_tr_base),
677 FIELD(HOST_GDTR_BASE, host_gdtr_base),
678 FIELD(HOST_IDTR_BASE, host_idtr_base),
679 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
680 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
681 FIELD(HOST_RSP, host_rsp),
682 FIELD(HOST_RIP, host_rip),
683};
684static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
685
686static inline short vmcs_field_to_offset(unsigned long field)
687{
688 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
689 return -1;
690 return vmcs_field_to_offset_table[field];
691}
692
a9d30f33
NHE		 693static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
694{
695 return to_vmx(vcpu)->nested.current_vmcs12;
696}
697
698static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
699{
700 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 701 if (is_error_page(page))
a9d30f33 702 return NULL;
32cad84f 703
a9d30f33
NHE		 704 return page;
705}
706
707static void nested_release_page(struct page *page)
708{
709 kvm_release_page_dirty(page);
710}
711
712static void nested_release_page_clean(struct page *page)
713{
714 kvm_release_page_clean(page);
715}
716
bfd0a56b 717static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 718static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 719static void kvm_cpu_vmxon(u64 addr);
720static void kvm_cpu_vmxoff(void);
776e58ea 721static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 722static void vmx_set_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
724static void vmx_get_segment(struct kvm_vcpu *vcpu,
725 struct kvm_segment *var, int seg);
d99e4152
GN		 726static bool guest_state_valid(struct kvm_vcpu *vcpu);
727static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 728static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 729static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 730static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 731
6aa8b732
AK		 732static DEFINE_PER_CPU(struct vmcs *, vmxarea);
733static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 734/*
735 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
736 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
737 */
738static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 739static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 740
3e7c73e9
AK		 741static unsigned long *vmx_io_bitmap_a;
742static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 743static unsigned long *vmx_msr_bitmap_legacy;
744static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 745static unsigned long *vmx_msr_bitmap_legacy_x2apic;
746static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 747static unsigned long *vmx_vmread_bitmap;
748static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 749
110312c8 750static bool cpu_has_load_ia32_efer;
8bf00a52 751static bool cpu_has_load_perf_global_ctrl;
110312c8 752
2384d2b3
SY		 753static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
754static DEFINE_SPINLOCK(vmx_vpid_lock);
755
1c3d14fe 756static struct vmcs_config {
6aa8b732
AK		 757 int size;
758 int order;
759 u32 revision_id;
1c3d14fe
YS		 760 u32 pin_based_exec_ctrl;
761 u32 cpu_based_exec_ctrl;
f78e0e2e 762 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 763 u32 vmexit_ctrl;
764 u32 vmentry_ctrl;
765} vmcs_config;
6aa8b732 766
efff9e53 767static struct vmx_capability {
d56f546d
SY		 768 u32 ept;
769 u32 vpid;
770} vmx_capability;
771
6aa8b732
AK		 772#define VMX_SEGMENT_FIELD(seg) \
773 [VCPU_SREG_##seg] = { \
774 .selector = GUEST_##seg##_SELECTOR, \
775 .base = GUEST_##seg##_BASE, \
776 .limit = GUEST_##seg##_LIMIT, \
777 .ar_bytes = GUEST_##seg##_AR_BYTES, \
778 }
779
772e0318 780static const struct kvm_vmx_segment_field {
6aa8b732
AK		 781 unsigned selector;
782 unsigned base;
783 unsigned limit;
784 unsigned ar_bytes;
785} kvm_vmx_segment_fields[] = {
786 VMX_SEGMENT_FIELD(CS),
787 VMX_SEGMENT_FIELD(DS),
788 VMX_SEGMENT_FIELD(ES),
789 VMX_SEGMENT_FIELD(FS),
790 VMX_SEGMENT_FIELD(GS),
791 VMX_SEGMENT_FIELD(SS),
792 VMX_SEGMENT_FIELD(TR),
793 VMX_SEGMENT_FIELD(LDTR),
794};
795
26bb0981
AK		 796static u64 host_efer;
797
6de4f3ad
AK		 798static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
799
4d56c8a7 800/*
8c06585d 801 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 802 * away by decrementing the array size.
803 */
6aa8b732 804static const u32 vmx_msr_index[] = {
05b3e0c2 805#ifdef CONFIG_X86_64
44ea2b17 806 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 807#endif
8c06585d 808 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 809};
9d8f549d 810#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 811
31299944 812static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 813{
814 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
815 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 816 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 817}
818
31299944 819static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 820{
821 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
822 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 823 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 824}
825
31299944 826static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 827{
828 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
829 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 830 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 831}
832
31299944 833static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 834{
835 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
836 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
837}
838
31299944 839static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 840{
841 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
842 INTR_INFO_VALID_MASK)) ==
843 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
844}
845
31299944 846static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 847{
04547156 848 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 849}
850
31299944 851static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 852{
04547156 853 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 854}
855
31299944 856static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 857{
04547156 858 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 859}
860
31299944 861static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 862{
04547156
SY		 863 return vmcs_config.cpu_based_exec_ctrl &
864 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 865}
866
774ead3a 867static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 868{
04547156
SY		 869 return vmcs_config.cpu_based_2nd_exec_ctrl &
870 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
871}
872
8d14695f
YZ		 873static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
874{
875 return vmcs_config.cpu_based_2nd_exec_ctrl &
876 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
877}
878
83d4c286
YZ		 879static inline bool cpu_has_vmx_apic_register_virt(void)
880{
881 return vmcs_config.cpu_based_2nd_exec_ctrl &
882 SECONDARY_EXEC_APIC_REGISTER_VIRT;
883}
884
c7c9c56c
YZ		 885static inline bool cpu_has_vmx_virtual_intr_delivery(void)
886{
887 return vmcs_config.cpu_based_2nd_exec_ctrl &
888 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
889}
890
01e439be
YZ		 891static inline bool cpu_has_vmx_posted_intr(void)
892{
893 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
894}
895
896static inline bool cpu_has_vmx_apicv(void)
897{
898 return cpu_has_vmx_apic_register_virt() &&
899 cpu_has_vmx_virtual_intr_delivery() &&
900 cpu_has_vmx_posted_intr();
901}
902
04547156
SY		 903static inline bool cpu_has_vmx_flexpriority(void)
904{
905 return cpu_has_vmx_tpr_shadow() &&
906 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 907}
908
e799794e
MT		 909static inline bool cpu_has_vmx_ept_execute_only(void)
910{
31299944 911 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 912}
913
914static inline bool cpu_has_vmx_eptp_uncacheable(void)
915{
31299944 916 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 917}
918
919static inline bool cpu_has_vmx_eptp_writeback(void)
920{
31299944 921 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 922}
923
924static inline bool cpu_has_vmx_ept_2m_page(void)
925{
31299944 926 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 927}
928
878403b7
SY		 929static inline bool cpu_has_vmx_ept_1g_page(void)
930{
31299944 931 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 932}
933
4bc9b982
SY		 934static inline bool cpu_has_vmx_ept_4levels(void)
935{
936 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
937}
938
83c3a331
XH		 939static inline bool cpu_has_vmx_ept_ad_bits(void)
940{
941 return vmx_capability.ept & VMX_EPT_AD_BIT;
942}
943
31299944 944static inline bool cpu_has_vmx_invept_context(void)
d56f546d 945{
31299944 946 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 947}
948
31299944 949static inline bool cpu_has_vmx_invept_global(void)
d56f546d 950{
31299944 951 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 952}
953
518c8aee
GJ		 954static inline bool cpu_has_vmx_invvpid_single(void)
955{
956 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
957}
958
b9d762fa
GJ		 959static inline bool cpu_has_vmx_invvpid_global(void)
960{
961 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
962}
963
31299944 964static inline bool cpu_has_vmx_ept(void)
d56f546d 965{
04547156
SY		 966 return vmcs_config.cpu_based_2nd_exec_ctrl &
967 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 968}
969
31299944 970static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 971{
972 return vmcs_config.cpu_based_2nd_exec_ctrl &
973 SECONDARY_EXEC_UNRESTRICTED_GUEST;
974}
975
31299944 976static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 977{
978 return vmcs_config.cpu_based_2nd_exec_ctrl &
979 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
980}
981
31299944 982static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 983{
6d3e435e 984 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 985}
986
31299944 987static inline bool cpu_has_vmx_vpid(void)
2384d2b3 988{
04547156
SY		 989 return vmcs_config.cpu_based_2nd_exec_ctrl &
990 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 991}
992
31299944 993static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 994{
995 return vmcs_config.cpu_based_2nd_exec_ctrl &
996 SECONDARY_EXEC_RDTSCP;
997}
998
ad756a16
MJ		 999static inline bool cpu_has_vmx_invpcid(void)
1000{
1001 return vmcs_config.cpu_based_2nd_exec_ctrl &
1002 SECONDARY_EXEC_ENABLE_INVPCID;
1003}
1004
31299944 1005static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1006{
1007 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1008}
1009
f5f48ee1
SY		 1010static inline bool cpu_has_vmx_wbinvd_exit(void)
1011{
1012 return vmcs_config.cpu_based_2nd_exec_ctrl &
1013 SECONDARY_EXEC_WBINVD_EXITING;
1014}
1015
abc4fc58
AG		 1016static inline bool cpu_has_vmx_shadow_vmcs(void)
1017{
1018 u64 vmx_msr;
1019 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1020 /* check if the cpu supports writing r/o exit information fields */
1021 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1022 return false;
1023
1024 return vmcs_config.cpu_based_2nd_exec_ctrl &
1025 SECONDARY_EXEC_SHADOW_VMCS;
1026}
1027
04547156
SY		 1028static inline bool report_flexpriority(void)
1029{
1030 return flexpriority_enabled;
1031}
1032
fe3ef05c
NHE		 1033static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1034{
1035 return vmcs12->cpu_based_vm_exec_control & bit;
1036}
1037
1038static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1039{
1040 return (vmcs12->cpu_based_vm_exec_control &
1041 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1042 (vmcs12->secondary_vm_exec_control & bit);
1043}
1044
f5c4368f 1045static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1046{
1047 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1048}
1049
155a97a3
NHE		 1050static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1051{
1052 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1053}
1054
644d711a
NHE		 1055static inline bool is_exception(u32 intr_info)
1056{
1057 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1058 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1059}
1060
1061static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1062static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1063 struct vmcs12 *vmcs12,
1064 u32 reason, unsigned long qualification);
1065
8b9cf98c 1066static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1067{
1068 int i;
1069
a2fa3e9f 1070 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1071 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1072 return i;
1073 return -1;
1074}
1075
2384d2b3
SY		 1076static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1077{
1078 struct {
1079 u64 vpid : 16;
1080 u64 rsvd : 48;
1081 u64 gva;
1082 } operand = { vpid, 0, gva };
1083
4ecac3fd 1084 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1085 /* CF==1 or ZF==1 --> rc = -1 */
1086 "; ja 1f ; ud2 ; 1:"
1087 : : "a"(&operand), "c"(ext) : "cc", "memory");
1088}
1089
1439442c
SY		 1090static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1091{
1092 struct {
1093 u64 eptp, gpa;
1094 } operand = {eptp, gpa};
1095
4ecac3fd 1096 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1097 /* CF==1 or ZF==1 --> rc = -1 */
1098 "; ja 1f ; ud2 ; 1:\n"
1099 : : "a" (&operand), "c" (ext) : "cc", "memory");
1100}
1101
26bb0981 1102static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1103{
1104 int i;
1105
8b9cf98c 1106 i = __find_msr_index(vmx, msr);
a75beee6 1107 if (i >= 0)
a2fa3e9f 1108 return &vmx->guest_msrs[i];
8b6d44c7 1109 return NULL;
7725f0ba
AK		 1110}
1111
6aa8b732
AK		 1112static void vmcs_clear(struct vmcs *vmcs)
1113{
1114 u64 phys_addr = __pa(vmcs);
1115 u8 error;
1116
4ecac3fd 1117 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1118 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1119 : "cc", "memory");
1120 if (error)
1121 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1122 vmcs, phys_addr);
1123}
1124
d462b819
NHE		 1125static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1126{
1127 vmcs_clear(loaded_vmcs->vmcs);
1128 loaded_vmcs->cpu = -1;
1129 loaded_vmcs->launched = 0;
1130}
1131
7725b894
DX		 1132static void vmcs_load(struct vmcs *vmcs)
1133{
1134 u64 phys_addr = __pa(vmcs);
1135 u8 error;
1136
1137 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1138 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1139 : "cc", "memory");
1140 if (error)
2844d849 1141 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1142 vmcs, phys_addr);
1143}
1144
8f536b76
ZY		 1145#ifdef CONFIG_KEXEC
1146/*
1147 * This bitmap is used to indicate whether the vmclear
1148 * operation is enabled on all cpus. All disabled by
1149 * default.
1150 */
1151static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1152
1153static inline void crash_enable_local_vmclear(int cpu)
1154{
1155 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1156}
1157
1158static inline void crash_disable_local_vmclear(int cpu)
1159{
1160 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1161}
1162
1163static inline int crash_local_vmclear_enabled(int cpu)
1164{
1165 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1166}
1167
1168static void crash_vmclear_local_loaded_vmcss(void)
1169{
1170 int cpu = raw_smp_processor_id();
1171 struct loaded_vmcs *v;
1172
1173 if (!crash_local_vmclear_enabled(cpu))
1174 return;
1175
1176 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1177 loaded_vmcss_on_cpu_link)
1178 vmcs_clear(v->vmcs);
1179}
1180#else
1181static inline void crash_enable_local_vmclear(int cpu) { }
1182static inline void crash_disable_local_vmclear(int cpu) { }
1183#endif /* CONFIG_KEXEC */
1184
d462b819 1185static void __loaded_vmcs_clear(void *arg)
6aa8b732 1186{
d462b819 1187 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1188 int cpu = raw_smp_processor_id();
6aa8b732 1189
d462b819
NHE		 1190 if (loaded_vmcs->cpu != cpu)
1191 return; /* vcpu migration can race with cpu offline */
1192 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1193 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1194 crash_disable_local_vmclear(cpu);
d462b819 1195 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1196
1197 /*
1198 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1199 * is before setting loaded_vmcs->vcpu to -1 which is done in
1200 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1201 * then adds the vmcs into percpu list before it is deleted.
1202 */
1203 smp_wmb();
1204
d462b819 1205 loaded_vmcs_init(loaded_vmcs);
8f536b76 1206 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1207}
1208
d462b819 1209static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1210{
e6c7d321
XG		 1211 int cpu = loaded_vmcs->cpu;
1212
1213 if (cpu != -1)
1214 smp_call_function_single(cpu,
1215 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1216}
1217
1760dd49 1218static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1219{
1220 if (vmx->vpid == 0)
1221 return;
1222
518c8aee
GJ		 1223 if (cpu_has_vmx_invvpid_single())
1224 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1225}
1226
b9d762fa
GJ		 1227static inline void vpid_sync_vcpu_global(void)
1228{
1229 if (cpu_has_vmx_invvpid_global())
1230 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1231}
1232
1233static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1234{
1235 if (cpu_has_vmx_invvpid_single())
1760dd49 1236 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1237 else
1238 vpid_sync_vcpu_global();
1239}
1240
1439442c
SY		 1241static inline void ept_sync_global(void)
1242{
1243 if (cpu_has_vmx_invept_global())
1244 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1245}
1246
1247static inline void ept_sync_context(u64 eptp)
1248{
089d034e 1249 if (enable_ept) {
1439442c
SY		 1250 if (cpu_has_vmx_invept_context())
1251 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1252 else
1253 ept_sync_global();
1254 }
1255}
1256
96304217 1257static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1258{
5e520e62 1259 unsigned long value;
6aa8b732 1260
5e520e62
AK		 1261 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1262 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1263 return value;
1264}
1265
96304217 1266static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1267{
1268 return vmcs_readl(field);
1269}
1270
96304217 1271static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1272{
1273 return vmcs_readl(field);
1274}
1275
96304217 1276static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1277{
05b3e0c2 1278#ifdef CONFIG_X86_64
6aa8b732
AK		 1279 return vmcs_readl(field);
1280#else
1281 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1282#endif
1283}
1284
e52de1b8
AK		 1285static noinline void vmwrite_error(unsigned long field, unsigned long value)
1286{
1287 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1288 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1289 dump_stack();
1290}
1291
6aa8b732
AK		 1292static void vmcs_writel(unsigned long field, unsigned long value)
1293{
1294 u8 error;
1295
4ecac3fd 1296 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1297 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1298 if (unlikely(error))
1299 vmwrite_error(field, value);
6aa8b732
AK		 1300}
1301
1302static void vmcs_write16(unsigned long field, u16 value)
1303{
1304 vmcs_writel(field, value);
1305}
1306
1307static void vmcs_write32(unsigned long field, u32 value)
1308{
1309 vmcs_writel(field, value);
1310}
1311
1312static void vmcs_write64(unsigned long field, u64 value)
1313{
6aa8b732 1314 vmcs_writel(field, value);
7682f2d0 1315#ifndef CONFIG_X86_64
6aa8b732
AK		 1316 asm volatile ("");
1317 vmcs_writel(field+1, value >> 32);
1318#endif
1319}
1320
2ab455cc
AL		 1321static void vmcs_clear_bits(unsigned long field, u32 mask)
1322{
1323 vmcs_writel(field, vmcs_readl(field) & ~mask);
1324}
1325
1326static void vmcs_set_bits(unsigned long field, u32 mask)
1327{
1328 vmcs_writel(field, vmcs_readl(field) | mask);
1329}
1330
2961e876
GN		 1331static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1332{
1333 vmcs_write32(VM_ENTRY_CONTROLS, val);
1334 vmx->vm_entry_controls_shadow = val;
1335}
1336
1337static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1338{
1339 if (vmx->vm_entry_controls_shadow != val)
1340 vm_entry_controls_init(vmx, val);
1341}
1342
1343static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1344{
1345 return vmx->vm_entry_controls_shadow;
1346}
1347
1348
1349static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1350{
1351 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1352}
1353
1354static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1355{
1356 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1357}
1358
1359static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1360{
1361 vmcs_write32(VM_EXIT_CONTROLS, val);
1362 vmx->vm_exit_controls_shadow = val;
1363}
1364
1365static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1366{
1367 if (vmx->vm_exit_controls_shadow != val)
1368 vm_exit_controls_init(vmx, val);
1369}
1370
1371static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1372{
1373 return vmx->vm_exit_controls_shadow;
1374}
1375
1376
1377static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1378{
1379 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1380}
1381
1382static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1383{
1384 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1385}
1386
2fb92db1
AK		 1387static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1388{
1389 vmx->segment_cache.bitmask = 0;
1390}
1391
1392static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1393 unsigned field)
1394{
1395 bool ret;
1396 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1397
1398 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1399 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1400 vmx->segment_cache.bitmask = 0;
1401 }
1402 ret = vmx->segment_cache.bitmask & mask;
1403 vmx->segment_cache.bitmask |= mask;
1404 return ret;
1405}
1406
1407static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1408{
1409 u16 *p = &vmx->segment_cache.seg[seg].selector;
1410
1411 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1412 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1413 return *p;
1414}
1415
1416static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1417{
1418 ulong *p = &vmx->segment_cache.seg[seg].base;
1419
1420 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1421 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1422 return *p;
1423}
1424
1425static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1426{
1427 u32 *p = &vmx->segment_cache.seg[seg].limit;
1428
1429 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1430 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1431 return *p;
1432}
1433
1434static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1435{
1436 u32 *p = &vmx->segment_cache.seg[seg].ar;
1437
1438 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1439 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1440 return *p;
1441}
1442
abd3f2d6
AK		 1443static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1444{
1445 u32 eb;
1446
fd7373cc
JK		 1447 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1448 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1449 if ((vcpu->guest_debug &
1450 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1451 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1452 eb |= 1u << BP_VECTOR;
7ffd92c5 1453 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1454 eb = ~0;
089d034e 1455 if (enable_ept)
1439442c 1456 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1457 if (vcpu->fpu_active)
1458 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1459
1460 /* When we are running a nested L2 guest and L1 specified for it a
1461 * certain exception bitmap, we must trap the same exceptions and pass
1462 * them to L1. When running L2, we will only handle the exceptions
1463 * specified above if L1 did not want them.
1464 */
1465 if (is_guest_mode(vcpu))
1466 eb |= get_vmcs12(vcpu)->exception_bitmap;
1467
abd3f2d6
AK		 1468 vmcs_write32(EXCEPTION_BITMAP, eb);
1469}
1470
2961e876
GN		 1471static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1472 unsigned long entry, unsigned long exit)
8bf00a52 1473{
2961e876
GN		 1474 vm_entry_controls_clearbit(vmx, entry);
1475 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1476}
1477
61d2ef2c
AK		 1478static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1479{
1480 unsigned i;
1481 struct msr_autoload *m = &vmx->msr_autoload;
1482
8bf00a52
GN		 1483 switch (msr) {
1484 case MSR_EFER:
1485 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1486 clear_atomic_switch_msr_special(vmx,
1487 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1488 VM_EXIT_LOAD_IA32_EFER);
1489 return;
1490 }
1491 break;
1492 case MSR_CORE_PERF_GLOBAL_CTRL:
1493 if (cpu_has_load_perf_global_ctrl) {
2961e876 1494 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1495 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1496 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1497 return;
1498 }
1499 break;
110312c8
AK		 1500 }
1501
61d2ef2c
AK		 1502 for (i = 0; i < m->nr; ++i)
1503 if (m->guest[i].index == msr)
1504 break;
1505
1506 if (i == m->nr)
1507 return;
1508 --m->nr;
1509 m->guest[i] = m->guest[m->nr];
1510 m->host[i] = m->host[m->nr];
1511 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1512 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1513}
1514
2961e876
GN		 1515static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1516 unsigned long entry, unsigned long exit,
1517 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1518 u64 guest_val, u64 host_val)
8bf00a52
GN		 1519{
1520 vmcs_write64(guest_val_vmcs, guest_val);
1521 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1522 vm_entry_controls_setbit(vmx, entry);
1523 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1524}
1525
61d2ef2c
AK		 1526static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1527 u64 guest_val, u64 host_val)
1528{
1529 unsigned i;
1530 struct msr_autoload *m = &vmx->msr_autoload;
1531
8bf00a52
GN		 1532 switch (msr) {
1533 case MSR_EFER:
1534 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1535 add_atomic_switch_msr_special(vmx,
1536 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1537 VM_EXIT_LOAD_IA32_EFER,
1538 GUEST_IA32_EFER,
1539 HOST_IA32_EFER,
1540 guest_val, host_val);
1541 return;
1542 }
1543 break;
1544 case MSR_CORE_PERF_GLOBAL_CTRL:
1545 if (cpu_has_load_perf_global_ctrl) {
2961e876 1546 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1547 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1548 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1549 GUEST_IA32_PERF_GLOBAL_CTRL,
1550 HOST_IA32_PERF_GLOBAL_CTRL,
1551 guest_val, host_val);
1552 return;
1553 }
1554 break;
110312c8
AK		 1555 }
1556
61d2ef2c
AK		 1557 for (i = 0; i < m->nr; ++i)
1558 if (m->guest[i].index == msr)
1559 break;
1560
e7fc6f93 1561 if (i == NR_AUTOLOAD_MSRS) {
60266204 1562 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1563 "Can't add msr %x\n", msr);
1564 return;
1565 } else if (i == m->nr) {
61d2ef2c
AK		 1566 ++m->nr;
1567 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1568 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1569 }
1570
1571 m->guest[i].index = msr;
1572 m->guest[i].value = guest_val;
1573 m->host[i].index = msr;
1574 m->host[i].value = host_val;
1575}
1576
33ed6329
AK		 1577static void reload_tss(void)
1578{
33ed6329
AK		 1579 /*
1580 * VT restores TR but not its size. Useless.
1581 */
d359192f 1582 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1583 struct desc_struct *descs;
33ed6329 1584
d359192f 1585 descs = (void *)gdt->address;
33ed6329
AK		 1586 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1587 load_TR_desc();
33ed6329
AK		 1588}
1589
92c0d900 1590static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1591{
3a34a881 1592 u64 guest_efer;
51c6cf66
AK		 1593 u64 ignore_bits;
1594
f6801dff 1595 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1596
51c6cf66 1597 /*
0fa06071 1598 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1599 * outside long mode
1600 */
1601 ignore_bits = EFER_NX | EFER_SCE;
1602#ifdef CONFIG_X86_64
1603 ignore_bits |= EFER_LMA | EFER_LME;
1604 /* SCE is meaningful only in long mode on Intel */
1605 if (guest_efer & EFER_LMA)
1606 ignore_bits &= ~(u64)EFER_SCE;
1607#endif
51c6cf66
AK		 1608 guest_efer &= ~ignore_bits;
1609 guest_efer |= host_efer & ignore_bits;
26bb0981 1610 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1611 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1612
1613 clear_atomic_switch_msr(vmx, MSR_EFER);
1614 /* On ept, can't emulate nx, and must switch nx atomically */
1615 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1616 guest_efer = vmx->vcpu.arch.efer;
1617 if (!(guest_efer & EFER_LMA))
1618 guest_efer &= ~EFER_LME;
1619 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1620 return false;
1621 }
1622
26bb0981 1623 return true;
51c6cf66
AK		 1624}
1625
2d49ec72
GN		 1626static unsigned long segment_base(u16 selector)
1627{
d359192f 1628 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1629 struct desc_struct *d;
1630 unsigned long table_base;
1631 unsigned long v;
1632
1633 if (!(selector & ~3))
1634 return 0;
1635
d359192f 1636 table_base = gdt->address;
2d49ec72
GN		 1637
1638 if (selector & 4) { /* from ldt */
1639 u16 ldt_selector = kvm_read_ldt();
1640
1641 if (!(ldt_selector & ~3))
1642 return 0;
1643
1644 table_base = segment_base(ldt_selector);
1645 }
1646 d = (struct desc_struct *)(table_base + (selector & ~7));
1647 v = get_desc_base(d);
1648#ifdef CONFIG_X86_64
1649 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1650 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1651#endif
1652 return v;
1653}
1654
1655static inline unsigned long kvm_read_tr_base(void)
1656{
1657 u16 tr;
1658 asm("str %0" : "=g"(tr));
1659 return segment_base(tr);
1660}
1661
04d2cc77 1662static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1663{
04d2cc77 1664 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1665 int i;
04d2cc77 1666
a2fa3e9f 1667 if (vmx->host_state.loaded)
33ed6329
AK		 1668 return;
1669
a2fa3e9f 1670 vmx->host_state.loaded = 1;
33ed6329
AK		 1671 /*
1672 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1673 * allow segment selectors with cpl > 0 or ti == 1.
1674 */
d6e88aec 1675 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1676 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1677 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1678 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1679 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1680 vmx->host_state.fs_reload_needed = 0;
1681 } else {
33ed6329 1682 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1683 vmx->host_state.fs_reload_needed = 1;
33ed6329 1684 }
9581d442 1685 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1686 if (!(vmx->host_state.gs_sel & 7))
1687 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1688 else {
1689 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1690 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1691 }
1692
b2da15ac
AK		 1693#ifdef CONFIG_X86_64
1694 savesegment(ds, vmx->host_state.ds_sel);
1695 savesegment(es, vmx->host_state.es_sel);
1696#endif
1697
33ed6329
AK		 1698#ifdef CONFIG_X86_64
1699 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1700 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1701#else
a2fa3e9f
GH		 1702 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1703 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1704#endif
707c0874
AK		 1705
1706#ifdef CONFIG_X86_64
c8770e7b
AK		 1707 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1708 if (is_long_mode(&vmx->vcpu))
44ea2b17 1709 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1710#endif
26bb0981
AK		 1711 for (i = 0; i < vmx->save_nmsrs; ++i)
1712 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1713 vmx->guest_msrs[i].data,
1714 vmx->guest_msrs[i].mask);
33ed6329
AK		 1715}
1716
a9b21b62 1717static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1718{
a2fa3e9f 1719 if (!vmx->host_state.loaded)
33ed6329
AK		 1720 return;
1721
e1beb1d3 1722 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1723 vmx->host_state.loaded = 0;
c8770e7b
AK		 1724#ifdef CONFIG_X86_64
1725 if (is_long_mode(&vmx->vcpu))
1726 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1727#endif
152d3f2f 1728 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1729 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1730#ifdef CONFIG_X86_64
9581d442 1731 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1732#else
1733 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1734#endif
33ed6329 1735 }
0a77fe4c
AK		 1736 if (vmx->host_state.fs_reload_needed)
1737 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1738#ifdef CONFIG_X86_64
1739 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1740 loadsegment(ds, vmx->host_state.ds_sel);
1741 loadsegment(es, vmx->host_state.es_sel);
1742 }
b2da15ac 1743#endif
152d3f2f 1744 reload_tss();
44ea2b17 1745#ifdef CONFIG_X86_64
c8770e7b 1746 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1747#endif
b1a74bf8
SS		 1748 /*
1749 * If the FPU is not active (through the host task or
1750 * the guest vcpu), then restore the cr0.TS bit.
1751 */
1752 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1753 stts();
3444d7da 1754 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1755}
1756
a9b21b62
AK		 1757static void vmx_load_host_state(struct vcpu_vmx *vmx)
1758{
1759 preempt_disable();
1760 __vmx_load_host_state(vmx);
1761 preempt_enable();
1762}
1763
6aa8b732
AK		 1764/*
1765 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1766 * vcpu mutex is already taken.
1767 */
15ad7146 1768static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1769{
a2fa3e9f 1770 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1771 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1772
4610c9cc
DX		 1773 if (!vmm_exclusive)
1774 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1775 else if (vmx->loaded_vmcs->cpu != cpu)
1776 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1777
d462b819
NHE		 1778 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1779 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1780 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1781 }
1782
d462b819 1783 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1784 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1785 unsigned long sysenter_esp;
1786
a8eeb04a 1787 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1788 local_irq_disable();
8f536b76 1789 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1790
1791 /*
1792 * Read loaded_vmcs->cpu should be before fetching
1793 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1794 * See the comments in __loaded_vmcs_clear().
1795 */
1796 smp_rmb();
1797
d462b819
NHE		 1798 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1799 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1800 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1801 local_irq_enable();
1802
6aa8b732
AK		 1803 /*
1804 * Linux uses per-cpu TSS and GDT, so set these when switching
1805 * processors.
1806 */
d6e88aec 1807 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1808 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1809
1810 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1811 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1812 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1813 }
6aa8b732
AK		 1814}
1815
1816static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1817{
a9b21b62 1818 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1819 if (!vmm_exclusive) {
d462b819
NHE		 1820 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1821 vcpu->cpu = -1;
4610c9cc
DX		 1822 kvm_cpu_vmxoff();
1823 }
6aa8b732
AK		 1824}
1825
5fd86fcf
AK		 1826static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1827{
81231c69
AK		 1828 ulong cr0;
1829
5fd86fcf
AK		 1830 if (vcpu->fpu_active)
1831 return;
1832 vcpu->fpu_active = 1;
81231c69
AK		 1833 cr0 = vmcs_readl(GUEST_CR0);
1834 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1835 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1836 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1837 update_exception_bitmap(vcpu);
edcafe3c 1838 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1839 if (is_guest_mode(vcpu))
1840 vcpu->arch.cr0_guest_owned_bits &=
1841 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1842 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1843}
1844
edcafe3c
AK		 1845static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1846
fe3ef05c
NHE		 1847/*
1848 * Return the cr0 value that a nested guest would read. This is a combination
1849 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1850 * its hypervisor (cr0_read_shadow).
1851 */
1852static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1853{
1854 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1855 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1856}
1857static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1858{
1859 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1860 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1861}
1862
5fd86fcf
AK		 1863static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1864{
36cf24e0
NHE		 1865 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1866 * set this *before* calling this function.
1867 */
edcafe3c 1868 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1869 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1870 update_exception_bitmap(vcpu);
edcafe3c
AK		 1871 vcpu->arch.cr0_guest_owned_bits = 0;
1872 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1873 if (is_guest_mode(vcpu)) {
1874 /*
1875 * L1's specified read shadow might not contain the TS bit,
1876 * so now that we turned on shadowing of this bit, we need to
1877 * set this bit of the shadow. Like in nested_vmx_run we need
1878 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1879 * up-to-date here because we just decached cr0.TS (and we'll
1880 * only update vmcs12->guest_cr0 on nested exit).
1881 */
1882 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1883 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1884 (vcpu->arch.cr0 & X86_CR0_TS);
1885 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1886 } else
1887 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1888}
1889
6aa8b732
AK		 1890static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1891{
78ac8b47 1892 unsigned long rflags, save_rflags;
345dcaa8 1893
6de12732
AK		 1894 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1895 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1896 rflags = vmcs_readl(GUEST_RFLAGS);
1897 if (to_vmx(vcpu)->rmode.vm86_active) {
1898 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1899 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1900 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1901 }
1902 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1903 }
6de12732 1904 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1905}
1906
1907static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1908{
6de12732
AK		 1909 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1910 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1911 if (to_vmx(vcpu)->rmode.vm86_active) {
1912 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1913 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1914 }
6aa8b732
AK		 1915 vmcs_writel(GUEST_RFLAGS, rflags);
1916}
1917
2809f5d2
GC		 1918static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1919{
1920 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1921 int ret = 0;
1922
1923 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1924 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1925 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1926 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1927
1928 return ret & mask;
1929}
1930
1931static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1932{
1933 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1934 u32 interruptibility = interruptibility_old;
1935
1936 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1937
48005f64 1938 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1939 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1940 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1941 interruptibility |= GUEST_INTR_STATE_STI;
1942
1943 if ((interruptibility != interruptibility_old))
1944 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1945}
1946
6aa8b732
AK		 1947static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1948{
1949 unsigned long rip;
6aa8b732 1950
5fdbf976 1951 rip = kvm_rip_read(vcpu);
6aa8b732 1952 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1953 kvm_rip_write(vcpu, rip);
6aa8b732 1954
2809f5d2
GC		 1955 /* skipping an emulated instruction also counts */
1956 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1957}
1958
0b6ac343
NHE		 1959/*
1960 * KVM wants to inject page-faults which it got to the guest. This function
1961 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1962 */
e011c663 1963static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1964{
1965 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1966
e011c663 1967 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1968 return 0;
1969
1970 nested_vmx_vmexit(vcpu);
1971 return 1;
1972}
1973
298101da 1974static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1975 bool has_error_code, u32 error_code,
1976 bool reinject)
298101da 1977{
77ab6db0 1978 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1979 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1980
e011c663
GN		 1981 if (!reinject && is_guest_mode(vcpu) &&
1982 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 1983 return;
1984
8ab2d2e2 1985 if (has_error_code) {
77ab6db0 1986 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1987 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1988 }
77ab6db0 1989
7ffd92c5 1990 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1991 int inc_eip = 0;
1992 if (kvm_exception_is_soft(nr))
1993 inc_eip = vcpu->arch.event_exit_inst_len;
1994 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1995 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1996 return;
1997 }
1998
66fd3f7f
GN		 1999 if (kvm_exception_is_soft(nr)) {
2000 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2001 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2002 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2003 } else
2004 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2005
2006 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2007}
2008
4e47c7a6
SY		 2009static bool vmx_rdtscp_supported(void)
2010{
2011 return cpu_has_vmx_rdtscp();
2012}
2013
ad756a16
MJ		 2014static bool vmx_invpcid_supported(void)
2015{
2016 return cpu_has_vmx_invpcid() && enable_ept;
2017}
2018
a75beee6
ED		 2019/*
2020 * Swap MSR entry in host/guest MSR entry array.
2021 */
8b9cf98c 2022static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2023{
26bb0981 2024 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2025
2026 tmp = vmx->guest_msrs[to];
2027 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2028 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2029}
2030
8d14695f
YZ		 2031static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2032{
2033 unsigned long *msr_bitmap;
2034
2035 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2036 if (is_long_mode(vcpu))
2037 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2038 else
2039 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2040 } else {
2041 if (is_long_mode(vcpu))
2042 msr_bitmap = vmx_msr_bitmap_longmode;
2043 else
2044 msr_bitmap = vmx_msr_bitmap_legacy;
2045 }
2046
2047 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2048}
2049
e38aea3e
AK		 2050/*
2051 * Set up the vmcs to automatically save and restore system
2052 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2053 * mode, as fiddling with msrs is very expensive.
2054 */
8b9cf98c 2055static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2056{
26bb0981 2057 int save_nmsrs, index;
e38aea3e 2058
a75beee6
ED		 2059 save_nmsrs = 0;
2060#ifdef CONFIG_X86_64
8b9cf98c 2061 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2062 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2063 if (index >= 0)
8b9cf98c
RR		 2064 move_msr_up(vmx, index, save_nmsrs++);
2065 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2066 if (index >= 0)
8b9cf98c
RR		 2067 move_msr_up(vmx, index, save_nmsrs++);
2068 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2069 if (index >= 0)
8b9cf98c 2070 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2071 index = __find_msr_index(vmx, MSR_TSC_AUX);
2072 if (index >= 0 && vmx->rdtscp_enabled)
2073 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2074 /*
8c06585d 2075 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2076 * if efer.sce is enabled.
2077 */
8c06585d 2078 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2079 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2080 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2081 }
2082#endif
92c0d900
AK		 2083 index = __find_msr_index(vmx, MSR_EFER);
2084 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2085 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2086
26bb0981 2087 vmx->save_nmsrs = save_nmsrs;
5897297b 2088
8d14695f
YZ		 2089 if (cpu_has_vmx_msr_bitmap())
2090 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2091}
2092
6aa8b732
AK		 2093/*
2094 * reads and returns guest's timestamp counter "register"
2095 * guest_tsc = host_tsc + tsc_offset -- 21.3
2096 */
2097static u64 guest_read_tsc(void)
2098{
2099 u64 host_tsc, tsc_offset;
2100
2101 rdtscll(host_tsc);
2102 tsc_offset = vmcs_read64(TSC_OFFSET);
2103 return host_tsc + tsc_offset;
2104}
2105
d5c1785d
NHE		 2106/*
2107 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2108 * counter, even if a nested guest (L2) is currently running.
2109 */
886b470c 2110u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2111{
886b470c 2112 u64 tsc_offset;
d5c1785d 2113
d5c1785d
NHE		 2114 tsc_offset = is_guest_mode(vcpu) ?
2115 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2116 vmcs_read64(TSC_OFFSET);
2117 return host_tsc + tsc_offset;
2118}
2119
4051b188 2120/*
cc578287
ZA		 2121 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2122 * software catchup for faster rates on slower CPUs.
4051b188 2123 */
cc578287 2124static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2125{
cc578287
ZA		 2126 if (!scale)
2127 return;
2128
2129 if (user_tsc_khz > tsc_khz) {
2130 vcpu->arch.tsc_catchup = 1;
2131 vcpu->arch.tsc_always_catchup = 1;
2132 } else
2133 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2134}
2135
ba904635
WA		 2136static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2137{
2138 return vmcs_read64(TSC_OFFSET);
2139}
2140
6aa8b732 2141/*
99e3e30a 2142 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2143 */
99e3e30a 2144static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2145{
27fc51b2 2146 if (is_guest_mode(vcpu)) {
7991825b 2147 /*
27fc51b2
NHE		 2148 * We're here if L1 chose not to trap WRMSR to TSC. According
2149 * to the spec, this should set L1's TSC; The offset that L1
2150 * set for L2 remains unchanged, and still needs to be added
2151 * to the newly set TSC to get L2's TSC.
7991825b 2152 */
27fc51b2
NHE		 2153 struct vmcs12 *vmcs12;
2154 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2155 /* recalculate vmcs02.TSC_OFFSET: */
2156 vmcs12 = get_vmcs12(vcpu);
2157 vmcs_write64(TSC_OFFSET, offset +
2158 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2159 vmcs12->tsc_offset : 0));
2160 } else {
489223ed
YY		 2161 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2162 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2163 vmcs_write64(TSC_OFFSET, offset);
2164 }
6aa8b732
AK		 2165}
2166
f1e2b260 2167static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2168{
2169 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2170
e48672fa 2171 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2172 if (is_guest_mode(vcpu)) {
2173 /* Even when running L2, the adjustment needs to apply to L1 */
2174 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2175 } else
2176 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2177 offset + adjustment);
e48672fa
ZA		 2178}
2179
857e4099
JR		 2180static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2181{
2182 return target_tsc - native_read_tsc();
2183}
2184
801d3424
NHE		 2185static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2186{
2187 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2188 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2189}
2190
2191/*
2192 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2193 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2194 * all guests if the "nested" module option is off, and can also be disabled
2195 * for a single guest by disabling its VMX cpuid bit.
2196 */
2197static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2198{
2199 return nested && guest_cpuid_has_vmx(vcpu);
2200}
2201
b87a51ae
NHE		 2202/*
2203 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2204 * returned for the various VMX controls MSRs when nested VMX is enabled.
2205 * The same values should also be used to verify that vmcs12 control fields are
2206 * valid during nested entry from L1 to L2.
2207 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2208 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2209 * bit in the high half is on if the corresponding bit in the control field
2210 * may be on. See also vmx_control_verify().
2211 * TODO: allow these variables to be modified (downgraded) by module options
2212 * or other means.
2213 */
2214static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2215static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2216static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2217static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2218static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2219static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2220static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2221static __init void nested_vmx_setup_ctls_msrs(void)
2222{
2223 /*
2224 * Note that as a general rule, the high half of the MSRs (bits in
2225 * the control fields which may be 1) should be initialized by the
2226 * intersection of the underlying hardware's MSR (i.e., features which
2227 * can be supported) and the list of features we want to expose -
2228 * because they are known to be properly supported in our code.
2229 * Also, usually, the low half of the MSRs (bits which must be 1) can
2230 * be set to 0, meaning that L1 may turn off any of these bits. The
2231 * reason is that if one of these bits is necessary, it will appear
2232 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2233 * fields of vmcs01 and vmcs02, will turn these bits off - and
2234 * nested_vmx_exit_handled() will not pass related exits to L1.
2235 * These rules have exceptions below.
2236 */
2237
2238 /* pin-based controls */
eabeaacc
JK		 2239 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2240 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2241 /*
2242 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2243 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2244 */
eabeaacc
JK		 2245 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2246 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2247 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2248 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2249 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2250
33fb20c3
JK		 2251 /*
2252 * Exit controls
2253 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2254 * 17 must be 1.
2255 */
c0dfee58
ACL		 2256 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2257 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2258 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2259 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
c0dfee58 2260 nested_vmx_exit_ctls_high &=
b87a51ae 2261#ifdef CONFIG_X86_64
c0dfee58 2262 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2263#endif
7854cbca
ACL		 2264 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT |
2265 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2266 if (!(nested_vmx_pinbased_ctls_high & PIN_BASED_VMX_PREEMPTION_TIMER) ||
2267 !(nested_vmx_exit_ctls_high & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)) {
2268 nested_vmx_exit_ctls_high &= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2269 nested_vmx_pinbased_ctls_high &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
2270 }
8049d651 2271 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
10ba54a5 2272 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER);
b87a51ae
NHE		 2273
2274 /* entry controls */
2275 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2276 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2277 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2278 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2279 nested_vmx_entry_ctls_high &=
57435349
JK		 2280#ifdef CONFIG_X86_64
2281 VM_ENTRY_IA32E_MODE |
2282#endif
2283 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2284 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2285 VM_ENTRY_LOAD_IA32_EFER);
57435349 2286
b87a51ae
NHE		 2287 /* cpu-based controls */
2288 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2289 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2290 nested_vmx_procbased_ctls_low = 0;
2291 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2292 CPU_BASED_VIRTUAL_INTR_PENDING |
2293 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2294 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2295 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2296 CPU_BASED_CR3_STORE_EXITING |
2297#ifdef CONFIG_X86_64
2298 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2299#endif
2300 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2301 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2302 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2303 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2304 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2305 /*
2306 * We can allow some features even when not supported by the
2307 * hardware. For example, L1 can specify an MSR bitmap - and we
2308 * can use it to avoid exits to L1 - even when L0 runs L2
2309 * without MSR bitmaps.
2310 */
2311 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2312
2313 /* secondary cpu-based controls */
2314 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2315 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2316 nested_vmx_secondary_ctls_low = 0;
2317 nested_vmx_secondary_ctls_high &=
d6851fbe 2318 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2319 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2320 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2321
afa61f75
NHE		 2322 if (enable_ept) {
2323 /* nested EPT: emulate EPT also to L1 */
2324 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2325 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2326 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2327 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2328 nested_vmx_ept_caps &= vmx_capability.ept;
2329 /*
2330 * Since invept is completely emulated we support both global
2331 * and context invalidation independent of what host cpu
2332 * supports
2333 */
2334 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2335 VMX_EPT_EXTENT_CONTEXT_BIT;
2336 } else
2337 nested_vmx_ept_caps = 0;
2338
c18911a2
JK		 2339 /* miscellaneous data */
2340 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2341 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2342 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2343 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2344}
2345
2346static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2347{
2348 /*
2349 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2350 */
2351 return ((control & high) | low) == control;
2352}
2353
2354static inline u64 vmx_control_msr(u32 low, u32 high)
2355{
2356 return low | ((u64)high << 32);
2357}
2358
2359/*
2360 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2361 * also let it use VMX-specific MSRs.
2362 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2363 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2364 * like all other MSRs).
2365 */
2366static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2367{
2368 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2369 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2370 /*
2371 * According to the spec, processors which do not support VMX
2372 * should throw a #GP(0) when VMX capability MSRs are read.
2373 */
2374 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2375 return 1;
2376 }
2377
2378 switch (msr_index) {
2379 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2380 if (nested_vmx_allowed(vcpu)) {
2381 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2382 break;
2383 }
2384 return 0;
b87a51ae
NHE		 2385 case MSR_IA32_VMX_BASIC:
2386 /*
2387 * This MSR reports some information about VMX support. We
2388 * should return information about the VMX we emulate for the
2389 * guest, and the VMCS structure we give it - not about the
2390 * VMX support of the underlying hardware.
2391 */
2392 *pdata = VMCS12_REVISION |
2393 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2394 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2395 break;
2396 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2397 case MSR_IA32_VMX_PINBASED_CTLS:
2398 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2399 nested_vmx_pinbased_ctls_high);
2400 break;
2401 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2402 case MSR_IA32_VMX_PROCBASED_CTLS:
2403 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2404 nested_vmx_procbased_ctls_high);
2405 break;
2406 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2407 case MSR_IA32_VMX_EXIT_CTLS:
2408 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2409 nested_vmx_exit_ctls_high);
2410 break;
2411 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2412 case MSR_IA32_VMX_ENTRY_CTLS:
2413 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2414 nested_vmx_entry_ctls_high);
2415 break;
2416 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2417 *pdata = vmx_control_msr(nested_vmx_misc_low,
2418 nested_vmx_misc_high);
b87a51ae
NHE		 2419 break;
2420 /*
2421 * These MSRs specify bits which the guest must keep fixed (on or off)
2422 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2423 * We picked the standard core2 setting.
2424 */
2425#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2426#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2427 case MSR_IA32_VMX_CR0_FIXED0:
2428 *pdata = VMXON_CR0_ALWAYSON;
2429 break;
2430 case MSR_IA32_VMX_CR0_FIXED1:
2431 *pdata = -1ULL;
2432 break;
2433 case MSR_IA32_VMX_CR4_FIXED0:
2434 *pdata = VMXON_CR4_ALWAYSON;
2435 break;
2436 case MSR_IA32_VMX_CR4_FIXED1:
2437 *pdata = -1ULL;
2438 break;
2439 case MSR_IA32_VMX_VMCS_ENUM:
2440 *pdata = 0x1f;
2441 break;
2442 case MSR_IA32_VMX_PROCBASED_CTLS2:
2443 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2444 nested_vmx_secondary_ctls_high);
2445 break;
2446 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2447 /* Currently, no nested vpid support */
2448 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2449 break;
2450 default:
2451 return 0;
2452 }
2453
2454 return 1;
2455}
2456
b3897a49 2457static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2458{
b3897a49
NHE		 2459 u32 msr_index = msr_info->index;
2460 u64 data = msr_info->data;
2461 bool host_initialized = msr_info->host_initiated;
2462
b87a51ae
NHE		 2463 if (!nested_vmx_allowed(vcpu))
2464 return 0;
2465
b3897a49
NHE		 2466 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2467 if (!host_initialized &&
2468 to_vmx(vcpu)->nested.msr_ia32_feature_control
2469 & FEATURE_CONTROL_LOCKED)
2470 return 0;
2471 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2472 return 1;
b3897a49
NHE		 2473 }
2474
b87a51ae
NHE		 2475 /*
2476 * No need to treat VMX capability MSRs specially: If we don't handle
2477 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2478 */
2479 return 0;
2480}
2481
6aa8b732
AK		 2482/*
2483 * Reads an msr value (of 'msr_index') into 'pdata'.
2484 * Returns 0 on success, non-0 otherwise.
2485 * Assumes vcpu_load() was already called.
2486 */
2487static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2488{
2489 u64 data;
26bb0981 2490 struct shared_msr_entry *msr;
6aa8b732
AK		 2491
2492 if (!pdata) {
2493 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2494 return -EINVAL;
2495 }
2496
2497 switch (msr_index) {
05b3e0c2 2498#ifdef CONFIG_X86_64
6aa8b732
AK		 2499 case MSR_FS_BASE:
2500 data = vmcs_readl(GUEST_FS_BASE);
2501 break;
2502 case MSR_GS_BASE:
2503 data = vmcs_readl(GUEST_GS_BASE);
2504 break;
44ea2b17
AK		 2505 case MSR_KERNEL_GS_BASE:
2506 vmx_load_host_state(to_vmx(vcpu));
2507 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2508 break;
26bb0981 2509#endif
6aa8b732 2510 case MSR_EFER:
3bab1f5d 2511 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2512 case MSR_IA32_TSC:
6aa8b732
AK		 2513 data = guest_read_tsc();
2514 break;
2515 case MSR_IA32_SYSENTER_CS:
2516 data = vmcs_read32(GUEST_SYSENTER_CS);
2517 break;
2518 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2519 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2520 break;
2521 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2522 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2523 break;
4e47c7a6
SY		 2524 case MSR_TSC_AUX:
2525 if (!to_vmx(vcpu)->rdtscp_enabled)
2526 return 1;
2527 /* Otherwise falls through */
6aa8b732 2528 default:
b87a51ae
NHE		 2529 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2530 return 0;
8b9cf98c 2531 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2532 if (msr) {
2533 data = msr->data;
2534 break;
6aa8b732 2535 }
3bab1f5d 2536 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2537 }
2538
2539 *pdata = data;
2540 return 0;
2541}
2542
2543/*
2544 * Writes msr value into into the appropriate "register".
2545 * Returns 0 on success, non-0 otherwise.
2546 * Assumes vcpu_load() was already called.
2547 */
8fe8ab46 2548static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2549{
a2fa3e9f 2550 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2551 struct shared_msr_entry *msr;
2cc51560 2552 int ret = 0;
8fe8ab46
WA		 2553 u32 msr_index = msr_info->index;
2554 u64 data = msr_info->data;
2cc51560 2555
6aa8b732 2556 switch (msr_index) {
3bab1f5d 2557 case MSR_EFER:
8fe8ab46 2558 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2559 break;
16175a79 2560#ifdef CONFIG_X86_64
6aa8b732 2561 case MSR_FS_BASE:
2fb92db1 2562 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2563 vmcs_writel(GUEST_FS_BASE, data);
2564 break;
2565 case MSR_GS_BASE:
2fb92db1 2566 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2567 vmcs_writel(GUEST_GS_BASE, data);
2568 break;
44ea2b17
AK		 2569 case MSR_KERNEL_GS_BASE:
2570 vmx_load_host_state(vmx);
2571 vmx->msr_guest_kernel_gs_base = data;
2572 break;
6aa8b732
AK		 2573#endif
2574 case MSR_IA32_SYSENTER_CS:
2575 vmcs_write32(GUEST_SYSENTER_CS, data);
2576 break;
2577 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2578 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2579 break;
2580 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2581 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2582 break;
af24a4e4 2583 case MSR_IA32_TSC:
8fe8ab46 2584 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2585 break;
468d472f
SY		 2586 case MSR_IA32_CR_PAT:
2587 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2588 vmcs_write64(GUEST_IA32_PAT, data);
2589 vcpu->arch.pat = data;
2590 break;
2591 }
8fe8ab46 2592 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2593 break;
ba904635
WA		 2594 case MSR_IA32_TSC_ADJUST:
2595 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2596 break;
2597 case MSR_TSC_AUX:
2598 if (!vmx->rdtscp_enabled)
2599 return 1;
2600 /* Check reserved bit, higher 32 bits should be zero */
2601 if ((data >> 32) != 0)
2602 return 1;
2603 /* Otherwise falls through */
6aa8b732 2604 default:
b3897a49 2605 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2606 break;
8b9cf98c 2607 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2608 if (msr) {
2609 msr->data = data;
2225fd56
AK		 2610 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2611 preempt_disable();
9ee73970
AK		 2612 kvm_set_shared_msr(msr->index, msr->data,
2613 msr->mask);
2225fd56
AK		 2614 preempt_enable();
2615 }
3bab1f5d 2616 break;
6aa8b732 2617 }
8fe8ab46 2618 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2619 }
2620
2cc51560 2621 return ret;
6aa8b732
AK		 2622}
2623
5fdbf976 2624static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2625{
5fdbf976
MT		 2626 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2627 switch (reg) {
2628 case VCPU_REGS_RSP:
2629 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2630 break;
2631 case VCPU_REGS_RIP:
2632 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2633 break;
6de4f3ad
AK		 2634 case VCPU_EXREG_PDPTR:
2635 if (enable_ept)
2636 ept_save_pdptrs(vcpu);
2637 break;
5fdbf976
MT		 2638 default:
2639 break;
2640 }
6aa8b732
AK		 2641}
2642
6aa8b732
AK		 2643static __init int cpu_has_kvm_support(void)
2644{
6210e37b 2645 return cpu_has_vmx();
6aa8b732
AK		 2646}
2647
2648static __init int vmx_disabled_by_bios(void)
2649{
2650 u64 msr;
2651
2652 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2653 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2654 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2655 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2656 && tboot_enabled())
2657 return 1;
23f3e991 2658 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2659 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2660 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2661 && !tboot_enabled()) {
2662 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2663 "activate TXT before enabling KVM\n");
cafd6659 2664 return 1;
f9335afe 2665 }
23f3e991
JC		 2666 /* launched w/o TXT and VMX disabled */
2667 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2668 && !tboot_enabled())
2669 return 1;
cafd6659
SW		 2670 }
2671
2672 return 0;
6aa8b732
AK		 2673}
2674
7725b894
DX		 2675static void kvm_cpu_vmxon(u64 addr)
2676{
2677 asm volatile (ASM_VMX_VMXON_RAX
2678 : : "a"(&addr), "m"(addr)
2679 : "memory", "cc");
2680}
2681
10474ae8 2682static int hardware_enable(void *garbage)
6aa8b732
AK		 2683{
2684 int cpu = raw_smp_processor_id();
2685 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2686 u64 old, test_bits;
6aa8b732 2687
10474ae8
AG		 2688 if (read_cr4() & X86_CR4_VMXE)
2689 return -EBUSY;
2690
d462b819 2691 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2692
2693 /*
2694 * Now we can enable the vmclear operation in kdump
2695 * since the loaded_vmcss_on_cpu list on this cpu
2696 * has been initialized.
2697 *
2698 * Though the cpu is not in VMX operation now, there
2699 * is no problem to enable the vmclear operation
2700 * for the loaded_vmcss_on_cpu list is empty!
2701 */
2702 crash_enable_local_vmclear(cpu);
2703
6aa8b732 2704 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2705
2706 test_bits = FEATURE_CONTROL_LOCKED;
2707 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2708 if (tboot_enabled())
2709 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2710
2711 if ((old & test_bits) != test_bits) {
6aa8b732 2712 /* enable and lock */
cafd6659
SW		 2713 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2714 }
66aee91a 2715 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2716
4610c9cc
DX		 2717 if (vmm_exclusive) {
2718 kvm_cpu_vmxon(phys_addr);
2719 ept_sync_global();
2720 }
10474ae8 2721
357d1226 2722 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2723
10474ae8 2724 return 0;
6aa8b732
AK		 2725}
2726
d462b819 2727static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2728{
2729 int cpu = raw_smp_processor_id();
d462b819 2730 struct loaded_vmcs *v, *n;
543e4243 2731
d462b819
NHE		 2732 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2733 loaded_vmcss_on_cpu_link)
2734 __loaded_vmcs_clear(v);
543e4243
AK		 2735}
2736
710ff4a8
EH		 2737
2738/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2739 * tricks.
2740 */
2741static void kvm_cpu_vmxoff(void)
6aa8b732 2742{
4ecac3fd 2743 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2744}
2745
710ff4a8
EH		 2746static void hardware_disable(void *garbage)
2747{
4610c9cc 2748 if (vmm_exclusive) {
d462b819 2749 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2750 kvm_cpu_vmxoff();
2751 }
7725b894 2752 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2753}
2754
1c3d14fe 2755static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2756 u32 msr, u32 *result)
1c3d14fe
YS		 2757{
2758 u32 vmx_msr_low, vmx_msr_high;
2759 u32 ctl = ctl_min | ctl_opt;
2760
2761 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2762
2763 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2764 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2765
2766 /* Ensure minimum (required) set of control bits are supported. */
2767 if (ctl_min & ~ctl)
002c7f7c 2768 return -EIO;
1c3d14fe
YS		 2769
2770 *result = ctl;
2771 return 0;
2772}
2773
110312c8
AK		 2774static __init bool allow_1_setting(u32 msr, u32 ctl)
2775{
2776 u32 vmx_msr_low, vmx_msr_high;
2777
2778 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2779 return vmx_msr_high & ctl;
2780}
2781
002c7f7c 2782static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2783{
2784 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2785 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2786 u32 _pin_based_exec_control = 0;
2787 u32 _cpu_based_exec_control = 0;
f78e0e2e 2788 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2789 u32 _vmexit_control = 0;
2790 u32 _vmentry_control = 0;
2791
10166744 2792 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2793#ifdef CONFIG_X86_64
2794 CPU_BASED_CR8_LOAD_EXITING |
2795 CPU_BASED_CR8_STORE_EXITING |
2796#endif
d56f546d
SY		 2797 CPU_BASED_CR3_LOAD_EXITING |
2798 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2799 CPU_BASED_USE_IO_BITMAPS |
2800 CPU_BASED_MOV_DR_EXITING |
a7052897 2801 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2802 CPU_BASED_MWAIT_EXITING |
2803 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2804 CPU_BASED_INVLPG_EXITING |
2805 CPU_BASED_RDPMC_EXITING;
443381a8 2806
f78e0e2e 2807 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2808 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2809 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2810 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2811 &_cpu_based_exec_control) < 0)
002c7f7c 2812 return -EIO;
6e5d865c
YS		 2813#ifdef CONFIG_X86_64
2814 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2815 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2816 ~CPU_BASED_CR8_STORE_EXITING;
2817#endif
f78e0e2e 2818 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2819 min2 = 0;
2820 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2821 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2822 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2823 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2824 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2825 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2826 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2827 SECONDARY_EXEC_RDTSCP |
83d4c286 2828 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2829 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2830 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2831 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2832 if (adjust_vmx_controls(min2, opt2,
2833 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2834 &_cpu_based_2nd_exec_control) < 0)
2835 return -EIO;
2836 }
2837#ifndef CONFIG_X86_64
2838 if (!(_cpu_based_2nd_exec_control &
2839 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2840 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2841#endif
83d4c286
YZ		 2842
2843 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2844 _cpu_based_2nd_exec_control &= ~(
8d14695f 2845 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2846 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2847 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2848
d56f546d 2849 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2850 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2851 enabled */
5fff7d27
GN		 2852 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2853 CPU_BASED_CR3_STORE_EXITING |
2854 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2855 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2856 vmx_capability.ept, vmx_capability.vpid);
2857 }
1c3d14fe
YS		 2858
2859 min = 0;
2860#ifdef CONFIG_X86_64
2861 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2862#endif
a547c6db
YZ		 2863 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2864 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2865 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2866 &_vmexit_control) < 0)
002c7f7c 2867 return -EIO;
1c3d14fe 2868
01e439be
YZ		 2869 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2870 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2871 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2872 &_pin_based_exec_control) < 0)
2873 return -EIO;
2874
2875 if (!(_cpu_based_2nd_exec_control &
2876 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2877 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2878 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2879
468d472f
SY		 2880 min = 0;
2881 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2882 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2883 &_vmentry_control) < 0)
002c7f7c 2884 return -EIO;
6aa8b732 2885
c68876fd 2886 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2887
2888 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2889 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2890 return -EIO;
1c3d14fe
YS		 2891
2892#ifdef CONFIG_X86_64
2893 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2894 if (vmx_msr_high & (1u<<16))
002c7f7c 2895 return -EIO;
1c3d14fe
YS		 2896#endif
2897
2898 /* Require Write-Back (WB) memory type for VMCS accesses. */
2899 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2900 return -EIO;
1c3d14fe 2901
002c7f7c
YS		 2902 vmcs_conf->size = vmx_msr_high & 0x1fff;
2903 vmcs_conf->order = get_order(vmcs_config.size);
2904 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2905
002c7f7c
YS		 2906 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2907 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2908 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2909 vmcs_conf->vmexit_ctrl = _vmexit_control;
2910 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2911
110312c8
AK		 2912 cpu_has_load_ia32_efer =
2913 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2914 VM_ENTRY_LOAD_IA32_EFER)
2915 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2916 VM_EXIT_LOAD_IA32_EFER);
2917
8bf00a52
GN		 2918 cpu_has_load_perf_global_ctrl =
2919 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2920 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2921 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2922 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2923
2924 /*
2925 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2926 * but due to arrata below it can't be used. Workaround is to use
2927 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2928 *
2929 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2930 *
2931 * AAK155 (model 26)
2932 * AAP115 (model 30)
2933 * AAT100 (model 37)
2934 * BC86,AAY89,BD102 (model 44)
2935 * BA97 (model 46)
2936 *
2937 */
2938 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2939 switch (boot_cpu_data.x86_model) {
2940 case 26:
2941 case 30:
2942 case 37:
2943 case 44:
2944 case 46:
2945 cpu_has_load_perf_global_ctrl = false;
2946 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2947 "does not work properly. Using workaround\n");
2948 break;
2949 default:
2950 break;
2951 }
2952 }
2953
1c3d14fe 2954 return 0;
c68876fd 2955}
6aa8b732
AK		 2956
2957static struct vmcs *alloc_vmcs_cpu(int cpu)
2958{
2959 int node = cpu_to_node(cpu);
2960 struct page *pages;
2961 struct vmcs *vmcs;
2962
6484eb3e 2963 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2964 if (!pages)
2965 return NULL;
2966 vmcs = page_address(pages);
1c3d14fe
YS		 2967 memset(vmcs, 0, vmcs_config.size);
2968 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2969 return vmcs;
2970}
2971
2972static struct vmcs *alloc_vmcs(void)
2973{
d3b2c338 2974 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2975}
2976
2977static void free_vmcs(struct vmcs *vmcs)
2978{
1c3d14fe 2979 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2980}
2981
d462b819
NHE		 2982/*
2983 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2984 */
2985static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2986{
2987 if (!loaded_vmcs->vmcs)
2988 return;
2989 loaded_vmcs_clear(loaded_vmcs);
2990 free_vmcs(loaded_vmcs->vmcs);
2991 loaded_vmcs->vmcs = NULL;
2992}
2993
39959588 2994static void free_kvm_area(void)
6aa8b732
AK		 2995{
2996 int cpu;
2997
3230bb47 2998 for_each_possible_cpu(cpu) {
6aa8b732 2999 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3000 per_cpu(vmxarea, cpu) = NULL;
3001 }
6aa8b732
AK		 3002}
3003
6aa8b732
AK		 3004static __init int alloc_kvm_area(void)
3005{
3006 int cpu;
3007
3230bb47 3008 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3009 struct vmcs *vmcs;
3010
3011 vmcs = alloc_vmcs_cpu(cpu);
3012 if (!vmcs) {
3013 free_kvm_area();
3014 return -ENOMEM;
3015 }
3016
3017 per_cpu(vmxarea, cpu) = vmcs;
3018 }
3019 return 0;
3020}
3021
3022static __init int hardware_setup(void)
3023{
002c7f7c
YS		 3024 if (setup_vmcs_config(&vmcs_config) < 0)
3025 return -EIO;
50a37eb4
JR		 3026
3027 if (boot_cpu_has(X86_FEATURE_NX))
3028 kvm_enable_efer_bits(EFER_NX);
3029
93ba03c2
SY		 3030 if (!cpu_has_vmx_vpid())
3031 enable_vpid = 0;
abc4fc58
AG		 3032 if (!cpu_has_vmx_shadow_vmcs())
3033 enable_shadow_vmcs = 0;
93ba03c2 3034
4bc9b982
SY		 3035 if (!cpu_has_vmx_ept() ||
3036 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3037 enable_ept = 0;
3a624e29 3038 enable_unrestricted_guest = 0;
83c3a331 3039 enable_ept_ad_bits = 0;
3a624e29
NK		 3040 }
3041
83c3a331
XH		 3042 if (!cpu_has_vmx_ept_ad_bits())
3043 enable_ept_ad_bits = 0;
3044
3a624e29
NK		 3045 if (!cpu_has_vmx_unrestricted_guest())
3046 enable_unrestricted_guest = 0;
93ba03c2
SY		 3047
3048 if (!cpu_has_vmx_flexpriority())
3049 flexpriority_enabled = 0;
3050
95ba8273
GN		 3051 if (!cpu_has_vmx_tpr_shadow())
3052 kvm_x86_ops->update_cr8_intercept = NULL;
3053
54dee993
MT		 3054 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3055 kvm_disable_largepages();
3056
4b8d54f9
ZE		 3057 if (!cpu_has_vmx_ple())
3058 ple_gap = 0;
3059
01e439be
YZ		 3060 if (!cpu_has_vmx_apicv())
3061 enable_apicv = 0;
c7c9c56c 3062
01e439be 3063 if (enable_apicv)
c7c9c56c 3064 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3065 else {
c7c9c56c 3066 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3067 kvm_x86_ops->deliver_posted_interrupt = NULL;
3068 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3069 }
83d4c286 3070
b87a51ae
NHE		 3071 if (nested)
3072 nested_vmx_setup_ctls_msrs();
3073
6aa8b732
AK		 3074 return alloc_kvm_area();
3075}
3076
3077static __exit void hardware_unsetup(void)
3078{
3079 free_kvm_area();
3080}
3081
14168786
GN		 3082static bool emulation_required(struct kvm_vcpu *vcpu)
3083{
3084 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3085}
3086
91b0aa2c 3087static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3088 struct kvm_segment *save)
6aa8b732 3089{
d99e4152
GN		 3090 if (!emulate_invalid_guest_state) {
3091 /*
3092 * CS and SS RPL should be equal during guest entry according
3093 * to VMX spec, but in reality it is not always so. Since vcpu
3094 * is in the middle of the transition from real mode to
3095 * protected mode it is safe to assume that RPL 0 is a good
3096 * default value.
3097 */
3098 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3099 save->selector &= ~SELECTOR_RPL_MASK;
3100 save->dpl = save->selector & SELECTOR_RPL_MASK;
3101 save->s = 1;
6aa8b732 3102 }
d99e4152 3103 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3104}
3105
3106static void enter_pmode(struct kvm_vcpu *vcpu)
3107{
3108 unsigned long flags;
a89a8fb9 3109 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3110
d99e4152
GN		 3111 /*
3112 * Update real mode segment cache. It may be not up-to-date if sement
3113 * register was written while vcpu was in a guest mode.
3114 */
3115 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3116 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3117 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3118 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3119 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3120 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3121
7ffd92c5 3122 vmx->rmode.vm86_active = 0;
6aa8b732 3123
2fb92db1
AK		 3124 vmx_segment_cache_clear(vmx);
3125
f5f7b2fe 3126 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3127
3128 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3129 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3130 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3131 vmcs_writel(GUEST_RFLAGS, flags);
3132
66aee91a
RR		 3133 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3134 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3135
3136 update_exception_bitmap(vcpu);
3137
91b0aa2c
GN		 3138 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3139 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3140 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3141 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3142 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3143 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3144
3145 /* CPL is always 0 when CPU enters protected mode */
3146 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3147 vmx->cpl = 0;
6aa8b732
AK		 3148}
3149
f5f7b2fe 3150static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3151{
772e0318 3152 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3153 struct kvm_segment var = *save;
3154
3155 var.dpl = 0x3;
3156 if (seg == VCPU_SREG_CS)
3157 var.type = 0x3;
3158
3159 if (!emulate_invalid_guest_state) {
3160 var.selector = var.base >> 4;
3161 var.base = var.base & 0xffff0;
3162 var.limit = 0xffff;
3163 var.g = 0;
3164 var.db = 0;
3165 var.present = 1;
3166 var.s = 1;
3167 var.l = 0;
3168 var.unusable = 0;
3169 var.type = 0x3;
3170 var.avl = 0;
3171 if (save->base & 0xf)
3172 printk_once(KERN_WARNING "kvm: segment base is not "
3173 "paragraph aligned when entering "
3174 "protected mode (seg=%d)", seg);
3175 }
6aa8b732 3176
d99e4152
GN		 3177 vmcs_write16(sf->selector, var.selector);
3178 vmcs_write32(sf->base, var.base);
3179 vmcs_write32(sf->limit, var.limit);
3180 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3181}
3182
3183static void enter_rmode(struct kvm_vcpu *vcpu)
3184{
3185 unsigned long flags;
a89a8fb9 3186 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3187
f5f7b2fe
AK		 3188 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3189 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3190 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3191 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3192 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3193 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3194 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3195
7ffd92c5 3196 vmx->rmode.vm86_active = 1;
6aa8b732 3197
776e58ea
GN		 3198 /*
3199 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3200 * vcpu. Warn the user that an update is overdue.
776e58ea 3201 */
4918c6ca 3202 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3203 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3204 "called before entering vcpu\n");
776e58ea 3205
2fb92db1
AK		 3206 vmx_segment_cache_clear(vmx);
3207
4918c6ca 3208 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3209 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3210 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3211
3212 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3213 vmx->rmode.save_rflags = flags;
6aa8b732 3214
053de044 3215 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3216
3217 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3218 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3219 update_exception_bitmap(vcpu);
3220
d99e4152
GN		 3221 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3222 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3223 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3224 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3225 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3226 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3227
8668a3c4 3228 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3229}
3230
401d10de
AS		 3231static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3232{
3233 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3234 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3235
3236 if (!msr)
3237 return;
401d10de 3238
44ea2b17
AK		 3239 /*
3240 * Force kernel_gs_base reloading before EFER changes, as control
3241 * of this msr depends on is_long_mode().
3242 */
3243 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3244 vcpu->arch.efer = efer;
401d10de 3245 if (efer & EFER_LMA) {
2961e876 3246 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3247 msr->data = efer;
3248 } else {
2961e876 3249 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3250
3251 msr->data = efer & ~EFER_LME;
3252 }
3253 setup_msrs(vmx);
3254}
3255
05b3e0c2 3256#ifdef CONFIG_X86_64
6aa8b732
AK		 3257
3258static void enter_lmode(struct kvm_vcpu *vcpu)
3259{
3260 u32 guest_tr_ar;
3261
2fb92db1
AK		 3262 vmx_segment_cache_clear(to_vmx(vcpu));
3263
6aa8b732
AK		 3264 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3265 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3266 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3267 __func__);
6aa8b732
AK		 3268 vmcs_write32(GUEST_TR_AR_BYTES,
3269 (guest_tr_ar & ~AR_TYPE_MASK)
3270 | AR_TYPE_BUSY_64_TSS);
3271 }
da38f438 3272 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3273}
3274
3275static void exit_lmode(struct kvm_vcpu *vcpu)
3276{
2961e876 3277 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3278 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3279}
3280
3281#endif
3282
2384d2b3
SY		 3283static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3284{
b9d762fa 3285 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3286 if (enable_ept) {
3287 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3288 return;
4e1096d2 3289 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3290 }
2384d2b3
SY		 3291}
3292
e8467fda
AK		 3293static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3294{
3295 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3296
3297 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3298 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3299}
3300
aff48baa
AK		 3301static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3302{
3303 if (enable_ept && is_paging(vcpu))
3304 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3305 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3306}
3307
25c4c276 3308static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3309{
fc78f519
AK		 3310 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3311
3312 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3313 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3314}
3315
1439442c
SY		 3316static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3317{
d0d538b9
GN		 3318 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3319
6de4f3ad
AK		 3320 if (!test_bit(VCPU_EXREG_PDPTR,
3321 (unsigned long *)&vcpu->arch.regs_dirty))
3322 return;
3323
1439442c 3324 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3325 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3326 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3327 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3328 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3329 }
3330}
3331
8f5d549f
AK		 3332static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3333{
d0d538b9
GN		 3334 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3335
8f5d549f 3336 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3337 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3338 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3339 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3340 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3341 }
6de4f3ad
AK		 3342
3343 __set_bit(VCPU_EXREG_PDPTR,
3344 (unsigned long *)&vcpu->arch.regs_avail);
3345 __set_bit(VCPU_EXREG_PDPTR,
3346 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3347}
3348
5e1746d6 3349static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3350
3351static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3352 unsigned long cr0,
3353 struct kvm_vcpu *vcpu)
3354{
5233dd51
MT		 3355 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3356 vmx_decache_cr3(vcpu);
1439442c
SY		 3357 if (!(cr0 & X86_CR0_PG)) {
3358 /* From paging/starting to nonpaging */
3359 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3360 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3361 (CPU_BASED_CR3_LOAD_EXITING |
3362 CPU_BASED_CR3_STORE_EXITING));
3363 vcpu->arch.cr0 = cr0;
fc78f519 3364 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3365 } else if (!is_paging(vcpu)) {
3366 /* From nonpaging to paging */
3367 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3368 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3369 ~(CPU_BASED_CR3_LOAD_EXITING |
3370 CPU_BASED_CR3_STORE_EXITING));
3371 vcpu->arch.cr0 = cr0;
fc78f519 3372 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3373 }
95eb84a7
SY		 3374
3375 if (!(cr0 & X86_CR0_WP))
3376 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3377}
3378
6aa8b732
AK		 3379static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3380{
7ffd92c5 3381 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3382 unsigned long hw_cr0;
3383
5037878e 3384 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3385 if (enable_unrestricted_guest)
5037878e 3386 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3387 else {
5037878e 3388 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3389
218e763f
GN		 3390 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3391 enter_pmode(vcpu);
6aa8b732 3392
218e763f
GN		 3393 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3394 enter_rmode(vcpu);
3395 }
6aa8b732 3396
05b3e0c2 3397#ifdef CONFIG_X86_64
f6801dff 3398 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3399 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3400 enter_lmode(vcpu);
707d92fa 3401 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3402 exit_lmode(vcpu);
3403 }
3404#endif
3405
089d034e 3406 if (enable_ept)
1439442c
SY		 3407 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3408
02daab21 3409 if (!vcpu->fpu_active)
81231c69 3410 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3411
6aa8b732 3412 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3413 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3414 vcpu->arch.cr0 = cr0;
14168786
GN		 3415
3416 /* depends on vcpu->arch.cr0 to be set to a new value */
3417 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3418}
3419
1439442c
SY		 3420static u64 construct_eptp(unsigned long root_hpa)
3421{
3422 u64 eptp;
3423
3424 /* TODO write the value reading from MSR */
3425 eptp = VMX_EPT_DEFAULT_MT |
3426 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3427 if (enable_ept_ad_bits)
3428 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3429 eptp |= (root_hpa & PAGE_MASK);
3430
3431 return eptp;
3432}
3433
6aa8b732
AK		 3434static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3435{
1439442c
SY		 3436 unsigned long guest_cr3;
3437 u64 eptp;
3438
3439 guest_cr3 = cr3;
089d034e 3440 if (enable_ept) {
1439442c
SY		 3441 eptp = construct_eptp(cr3);
3442 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3443 if (is_paging(vcpu) || is_guest_mode(vcpu))
3444 guest_cr3 = kvm_read_cr3(vcpu);
3445 else
3446 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3447 ept_load_pdptrs(vcpu);
1439442c
SY		 3448 }
3449
2384d2b3 3450 vmx_flush_tlb(vcpu);
1439442c 3451 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3452}
3453
5e1746d6 3454static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3455{
7ffd92c5 3456 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3457 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3458
5e1746d6
NHE		 3459 if (cr4 & X86_CR4_VMXE) {
3460 /*
3461 * To use VMXON (and later other VMX instructions), a guest
3462 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3463 * So basically the check on whether to allow nested VMX
3464 * is here.
3465 */
3466 if (!nested_vmx_allowed(vcpu))
3467 return 1;
1a0d74e6
JK		 3468 }
3469 if (to_vmx(vcpu)->nested.vmxon &&
3470 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3471 return 1;
3472
ad312c7c 3473 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3474 if (enable_ept) {
3475 if (!is_paging(vcpu)) {
3476 hw_cr4 &= ~X86_CR4_PAE;
3477 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3478 /*
3479 * SMEP is disabled if CPU is in non-paging mode in
3480 * hardware. However KVM always uses paging mode to
3481 * emulate guest non-paging mode with TDP.
3482 * To emulate this behavior, SMEP needs to be manually
3483 * disabled when guest switches to non-paging mode.
3484 */
3485 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3486 } else if (!(cr4 & X86_CR4_PAE)) {
3487 hw_cr4 &= ~X86_CR4_PAE;
3488 }
3489 }
1439442c
SY		 3490
3491 vmcs_writel(CR4_READ_SHADOW, cr4);
3492 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3493 return 0;
6aa8b732
AK		 3494}
3495
6aa8b732
AK		 3496static void vmx_get_segment(struct kvm_vcpu *vcpu,
3497 struct kvm_segment *var, int seg)
3498{
a9179499 3499 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3500 u32 ar;
3501
c6ad1153 3502 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3503 *var = vmx->rmode.segs[seg];
a9179499 3504 if (seg == VCPU_SREG_TR
2fb92db1 3505 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3506 return;
1390a28b
AK		 3507 var->base = vmx_read_guest_seg_base(vmx, seg);
3508 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3509 return;
a9179499 3510 }
2fb92db1
AK		 3511 var->base = vmx_read_guest_seg_base(vmx, seg);
3512 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3513 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3514 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3515 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3516 var->type = ar & 15;
3517 var->s = (ar >> 4) & 1;
3518 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3519 /*
3520 * Some userspaces do not preserve unusable property. Since usable
3521 * segment has to be present according to VMX spec we can use present
3522 * property to amend userspace bug by making unusable segment always
3523 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3524 * segment as unusable.
3525 */
3526 var->present = !var->unusable;
6aa8b732
AK		 3527 var->avl = (ar >> 12) & 1;
3528 var->l = (ar >> 13) & 1;
3529 var->db = (ar >> 14) & 1;
3530 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3531}
3532
a9179499
AK		 3533static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3534{
a9179499
AK		 3535 struct kvm_segment s;
3536
3537 if (to_vmx(vcpu)->rmode.vm86_active) {
3538 vmx_get_segment(vcpu, &s, seg);
3539 return s.base;
3540 }
2fb92db1 3541 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3542}
3543
b09408d0 3544static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3545{
b09408d0
MT		 3546 struct vcpu_vmx *vmx = to_vmx(vcpu);
3547
3eeb3288 3548 if (!is_protmode(vcpu))
2e4d2653
IE		 3549 return 0;
3550
f4c63e5d
AK		 3551 if (!is_long_mode(vcpu)
3552 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3553 return 3;
3554
69c73028
AK		 3555 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3556 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3557 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3558 }
d881e6f6
AK		 3559
3560 return vmx->cpl;
69c73028
AK		 3561}
3562
3563
653e3108 3564static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3565{
6aa8b732
AK		 3566 u32 ar;
3567
f0495f9b 3568 if (var->unusable || !var->present)
6aa8b732
AK		 3569 ar = 1 << 16;
3570 else {
3571 ar = var->type & 15;
3572 ar |= (var->s & 1) << 4;
3573 ar |= (var->dpl & 3) << 5;
3574 ar |= (var->present & 1) << 7;
3575 ar |= (var->avl & 1) << 12;
3576 ar |= (var->l & 1) << 13;
3577 ar |= (var->db & 1) << 14;
3578 ar |= (var->g & 1) << 15;
3579 }
653e3108
AK		 3580
3581 return ar;
3582}
3583
3584static void vmx_set_segment(struct kvm_vcpu *vcpu,
3585 struct kvm_segment *var, int seg)
3586{
7ffd92c5 3587 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3588 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3589
2fb92db1 3590 vmx_segment_cache_clear(vmx);
2f143240
GN		 3591 if (seg == VCPU_SREG_CS)
3592 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3593
1ecd50a9
GN		 3594 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3595 vmx->rmode.segs[seg] = *var;
3596 if (seg == VCPU_SREG_TR)
3597 vmcs_write16(sf->selector, var->selector);
3598 else if (var->s)
3599 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3600 goto out;
653e3108 3601 }
1ecd50a9 3602
653e3108
AK		 3603 vmcs_writel(sf->base, var->base);
3604 vmcs_write32(sf->limit, var->limit);
3605 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3606
3607 /*
3608 * Fix the "Accessed" bit in AR field of segment registers for older
3609 * qemu binaries.
3610 * IA32 arch specifies that at the time of processor reset the
3611 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3612 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3613 * state vmexit when "unrestricted guest" mode is turned on.
3614 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3615 * tree. Newer qemu binaries with that qemu fix would not need this
3616 * kvm hack.
3617 */
3618 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3619 var->type |= 0x1; /* Accessed */
3a624e29 3620
f924d66d 3621 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3622
3623out:
14168786 3624 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3625}
3626
6aa8b732
AK		 3627static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3628{
2fb92db1 3629 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3630
3631 *db = (ar >> 14) & 1;
3632 *l = (ar >> 13) & 1;
3633}
3634
89a27f4d 3635static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3636{
89a27f4d
GN		 3637 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3638 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3639}
3640
89a27f4d 3641static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3642{
89a27f4d
GN		 3643 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3644 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3645}
3646
89a27f4d 3647static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3648{
89a27f4d
GN		 3649 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3650 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3651}
3652
89a27f4d 3653static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3654{
89a27f4d
GN		 3655 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3656 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3657}
3658
648dfaa7
MG		 3659static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3660{
3661 struct kvm_segment var;
3662 u32 ar;
3663
3664 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3665 var.dpl = 0x3;
0647f4aa
GN		 3666 if (seg == VCPU_SREG_CS)
3667 var.type = 0x3;
648dfaa7
MG		 3668 ar = vmx_segment_access_rights(&var);
3669
3670 if (var.base != (var.selector << 4))
3671 return false;
89efbed0 3672 if (var.limit != 0xffff)
648dfaa7 3673 return false;
07f42f5f 3674 if (ar != 0xf3)
648dfaa7
MG		 3675 return false;
3676
3677 return true;
3678}
3679
3680static bool code_segment_valid(struct kvm_vcpu *vcpu)
3681{
3682 struct kvm_segment cs;
3683 unsigned int cs_rpl;
3684
3685 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3686 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3687
1872a3f4
AK		 3688 if (cs.unusable)
3689 return false;
648dfaa7
MG		 3690 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3691 return false;
3692 if (!cs.s)
3693 return false;
1872a3f4 3694 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3695 if (cs.dpl > cs_rpl)
3696 return false;
1872a3f4 3697 } else {
648dfaa7
MG		 3698 if (cs.dpl != cs_rpl)
3699 return false;
3700 }
3701 if (!cs.present)
3702 return false;
3703
3704 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3705 return true;
3706}
3707
3708static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3709{
3710 struct kvm_segment ss;
3711 unsigned int ss_rpl;
3712
3713 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3714 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3715
1872a3f4
AK		 3716 if (ss.unusable)
3717 return true;
3718 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3719 return false;
3720 if (!ss.s)
3721 return false;
3722 if (ss.dpl != ss_rpl) /* DPL != RPL */
3723 return false;
3724 if (!ss.present)
3725 return false;
3726
3727 return true;
3728}
3729
3730static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3731{
3732 struct kvm_segment var;
3733 unsigned int rpl;
3734
3735 vmx_get_segment(vcpu, &var, seg);
3736 rpl = var.selector & SELECTOR_RPL_MASK;
3737
1872a3f4
AK		 3738 if (var.unusable)
3739 return true;
648dfaa7
MG		 3740 if (!var.s)
3741 return false;
3742 if (!var.present)
3743 return false;
3744 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3745 if (var.dpl < rpl) /* DPL < RPL */
3746 return false;
3747 }
3748
3749 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3750 * rights flags
3751 */
3752 return true;
3753}
3754
3755static bool tr_valid(struct kvm_vcpu *vcpu)
3756{
3757 struct kvm_segment tr;
3758
3759 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3760
1872a3f4
AK		 3761 if (tr.unusable)
3762 return false;
648dfaa7
MG		 3763 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3764 return false;
1872a3f4 3765 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3766 return false;
3767 if (!tr.present)
3768 return false;
3769
3770 return true;
3771}
3772
3773static bool ldtr_valid(struct kvm_vcpu *vcpu)
3774{
3775 struct kvm_segment ldtr;
3776
3777 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3778
1872a3f4
AK		 3779 if (ldtr.unusable)
3780 return true;
648dfaa7
MG		 3781 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3782 return false;
3783 if (ldtr.type != 2)
3784 return false;
3785 if (!ldtr.present)
3786 return false;
3787
3788 return true;
3789}
3790
3791static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3792{
3793 struct kvm_segment cs, ss;
3794
3795 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3796 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3797
3798 return ((cs.selector & SELECTOR_RPL_MASK) ==
3799 (ss.selector & SELECTOR_RPL_MASK));
3800}
3801
3802/*
3803 * Check if guest state is valid. Returns true if valid, false if
3804 * not.
3805 * We assume that registers are always usable
3806 */
3807static bool guest_state_valid(struct kvm_vcpu *vcpu)
3808{
c5e97c80
GN		 3809 if (enable_unrestricted_guest)
3810 return true;
3811
648dfaa7 3812 /* real mode guest state checks */
f13882d8 3813 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3814 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3815 return false;
3816 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3817 return false;
3818 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3819 return false;
3820 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3821 return false;
3822 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3823 return false;
3824 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3825 return false;
3826 } else {
3827 /* protected mode guest state checks */
3828 if (!cs_ss_rpl_check(vcpu))
3829 return false;
3830 if (!code_segment_valid(vcpu))
3831 return false;
3832 if (!stack_segment_valid(vcpu))
3833 return false;
3834 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3835 return false;
3836 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3837 return false;
3838 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3839 return false;
3840 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3841 return false;
3842 if (!tr_valid(vcpu))
3843 return false;
3844 if (!ldtr_valid(vcpu))
3845 return false;
3846 }
3847 /* TODO:
3848 * - Add checks on RIP
3849 * - Add checks on RFLAGS
3850 */
3851
3852 return true;
3853}
3854
d77c26fc 3855static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3856{
40dcaa9f 3857 gfn_t fn;
195aefde 3858 u16 data = 0;
40dcaa9f 3859 int r, idx, ret = 0;
6aa8b732 3860
40dcaa9f 3861 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3862 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3863 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3864 if (r < 0)
10589a46 3865 goto out;
195aefde 3866 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3867 r = kvm_write_guest_page(kvm, fn++, &data,
3868 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3869 if (r < 0)
10589a46 3870 goto out;
195aefde
IE		 3871 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3872 if (r < 0)
10589a46 3873 goto out;
195aefde
IE		 3874 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3875 if (r < 0)
10589a46 3876 goto out;
195aefde 3877 data = ~0;
10589a46
MT		 3878 r = kvm_write_guest_page(kvm, fn, &data,
3879 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3880 sizeof(u8));
195aefde 3881 if (r < 0)
10589a46
MT		 3882 goto out;
3883
3884 ret = 1;
3885out:
40dcaa9f 3886 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3887 return ret;
6aa8b732
AK		 3888}
3889
b7ebfb05
SY		 3890static int init_rmode_identity_map(struct kvm *kvm)
3891{
40dcaa9f 3892 int i, idx, r, ret;
b7ebfb05
SY		 3893 pfn_t identity_map_pfn;
3894 u32 tmp;
3895
089d034e 3896 if (!enable_ept)
b7ebfb05
SY		 3897 return 1;
3898 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3899 printk(KERN_ERR "EPT: identity-mapping pagetable "
3900 "haven't been allocated!\n");
3901 return 0;
3902 }
3903 if (likely(kvm->arch.ept_identity_pagetable_done))
3904 return 1;
3905 ret = 0;
b927a3ce 3906 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3907 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3908 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3909 if (r < 0)
3910 goto out;
3911 /* Set up identity-mapping pagetable for EPT in real mode */
3912 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3913 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3914 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3915 r = kvm_write_guest_page(kvm, identity_map_pfn,
3916 &tmp, i * sizeof(tmp), sizeof(tmp));
3917 if (r < 0)
3918 goto out;
3919 }
3920 kvm->arch.ept_identity_pagetable_done = true;
3921 ret = 1;
3922out:
40dcaa9f 3923 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3924 return ret;
3925}
3926
6aa8b732
AK		 3927static void seg_setup(int seg)
3928{
772e0318 3929 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3930 unsigned int ar;
6aa8b732
AK		 3931
3932 vmcs_write16(sf->selector, 0);
3933 vmcs_writel(sf->base, 0);
3934 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3935 ar = 0x93;
3936 if (seg == VCPU_SREG_CS)
3937 ar |= 0x08; /* code segment */
3a624e29
NK		 3938
3939 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3940}
3941
f78e0e2e
SY		 3942static int alloc_apic_access_page(struct kvm *kvm)
3943{
4484141a 3944 struct page *page;
f78e0e2e
SY		 3945 struct kvm_userspace_memory_region kvm_userspace_mem;
3946 int r = 0;
3947
79fac95e 3948 mutex_lock(&kvm->slots_lock);
bfc6d222 3949 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3950 goto out;
3951 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3952 kvm_userspace_mem.flags = 0;
3953 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3954 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3955 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3956 if (r)
3957 goto out;
72dc67a6 3958
4484141a
XG		 3959 page = gfn_to_page(kvm, 0xfee00);
3960 if (is_error_page(page)) {
3961 r = -EFAULT;
3962 goto out;
3963 }
3964
3965 kvm->arch.apic_access_page = page;
f78e0e2e 3966out:
79fac95e 3967 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3968 return r;
3969}
3970
b7ebfb05
SY		 3971static int alloc_identity_pagetable(struct kvm *kvm)
3972{
4484141a 3973 struct page *page;
b7ebfb05
SY		 3974 struct kvm_userspace_memory_region kvm_userspace_mem;
3975 int r = 0;
3976
79fac95e 3977 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3978 if (kvm->arch.ept_identity_pagetable)
3979 goto out;
3980 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3981 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3982 kvm_userspace_mem.guest_phys_addr =
3983 kvm->arch.ept_identity_map_addr;
b7ebfb05 3984 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3985 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3986 if (r)
3987 goto out;
3988
4484141a
XG		 3989 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3990 if (is_error_page(page)) {
3991 r = -EFAULT;
3992 goto out;
3993 }
3994
3995 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3996out:
79fac95e 3997 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3998 return r;
3999}
4000
2384d2b3
SY		 4001static void allocate_vpid(struct vcpu_vmx *vmx)
4002{
4003 int vpid;
4004
4005 vmx->vpid = 0;
919818ab 4006 if (!enable_vpid)
2384d2b3
SY		 4007 return;
4008 spin_lock(&vmx_vpid_lock);
4009 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4010 if (vpid < VMX_NR_VPIDS) {
4011 vmx->vpid = vpid;
4012 __set_bit(vpid, vmx_vpid_bitmap);
4013 }
4014 spin_unlock(&vmx_vpid_lock);
4015}
4016
cdbecfc3
LJ		 4017static void free_vpid(struct vcpu_vmx *vmx)
4018{
4019 if (!enable_vpid)
4020 return;
4021 spin_lock(&vmx_vpid_lock);
4022 if (vmx->vpid != 0)
4023 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4024 spin_unlock(&vmx_vpid_lock);
4025}
4026
8d14695f
YZ		 4027#define MSR_TYPE_R 1
4028#define MSR_TYPE_W 2
4029static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4030 u32 msr, int type)
25c5f225 4031{
3e7c73e9 4032 int f = sizeof(unsigned long);
25c5f225
SY		 4033
4034 if (!cpu_has_vmx_msr_bitmap())
4035 return;
4036
4037 /*
4038 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4039 * have the write-low and read-high bitmap offsets the wrong way round.
4040 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4041 */
25c5f225 4042 if (msr <= 0x1fff) {
8d14695f
YZ		 4043 if (type & MSR_TYPE_R)
4044 /* read-low */
4045 __clear_bit(msr, msr_bitmap + 0x000 / f);
4046
4047 if (type & MSR_TYPE_W)
4048 /* write-low */
4049 __clear_bit(msr, msr_bitmap + 0x800 / f);
4050
25c5f225
SY		 4051 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4052 msr &= 0x1fff;
8d14695f
YZ		 4053 if (type & MSR_TYPE_R)
4054 /* read-high */
4055 __clear_bit(msr, msr_bitmap + 0x400 / f);
4056
4057 if (type & MSR_TYPE_W)
4058 /* write-high */
4059 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4060
4061 }
4062}
4063
4064static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4065 u32 msr, int type)
4066{
4067 int f = sizeof(unsigned long);
4068
4069 if (!cpu_has_vmx_msr_bitmap())
4070 return;
4071
4072 /*
4073 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4074 * have the write-low and read-high bitmap offsets the wrong way round.
4075 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4076 */
4077 if (msr <= 0x1fff) {
4078 if (type & MSR_TYPE_R)
4079 /* read-low */
4080 __set_bit(msr, msr_bitmap + 0x000 / f);
4081
4082 if (type & MSR_TYPE_W)
4083 /* write-low */
4084 __set_bit(msr, msr_bitmap + 0x800 / f);
4085
4086 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4087 msr &= 0x1fff;
4088 if (type & MSR_TYPE_R)
4089 /* read-high */
4090 __set_bit(msr, msr_bitmap + 0x400 / f);
4091
4092 if (type & MSR_TYPE_W)
4093 /* write-high */
4094 __set_bit(msr, msr_bitmap + 0xc00 / f);
4095
25c5f225 4096 }
25c5f225
SY		 4097}
4098
5897297b
AK		 4099static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4100{
4101 if (!longmode_only)
8d14695f
YZ		 4102 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4103 msr, MSR_TYPE_R | MSR_TYPE_W);
4104 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4105 msr, MSR_TYPE_R | MSR_TYPE_W);
4106}
4107
4108static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4109{
4110 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4111 msr, MSR_TYPE_R);
4112 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4113 msr, MSR_TYPE_R);
4114}
4115
4116static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4117{
4118 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4119 msr, MSR_TYPE_R);
4120 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4121 msr, MSR_TYPE_R);
4122}
4123
4124static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4125{
4126 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4127 msr, MSR_TYPE_W);
4128 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4129 msr, MSR_TYPE_W);
5897297b
AK		 4130}
4131
01e439be
YZ		 4132static int vmx_vm_has_apicv(struct kvm *kvm)
4133{
4134 return enable_apicv && irqchip_in_kernel(kvm);
4135}
4136
a20ed54d
YZ		 4137/*
4138 * Send interrupt to vcpu via posted interrupt way.
4139 * 1. If target vcpu is running(non-root mode), send posted interrupt
4140 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4141 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4142 * interrupt from PIR in next vmentry.
4143 */
4144static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4145{
4146 struct vcpu_vmx *vmx = to_vmx(vcpu);
4147 int r;
4148
4149 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4150 return;
4151
4152 r = pi_test_and_set_on(&vmx->pi_desc);
4153 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4154#ifdef CONFIG_SMP
a20ed54d
YZ		 4155 if (!r && (vcpu->mode == IN_GUEST_MODE))
4156 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4157 POSTED_INTR_VECTOR);
4158 else
6ffbbbba 4159#endif
a20ed54d
YZ		 4160 kvm_vcpu_kick(vcpu);
4161}
4162
4163static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4164{
4165 struct vcpu_vmx *vmx = to_vmx(vcpu);
4166
4167 if (!pi_test_and_clear_on(&vmx->pi_desc))
4168 return;
4169
4170 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4171}
4172
4173static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4174{
4175 return;
4176}
4177
a3a8ff8e
NHE		 4178/*
4179 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4180 * will not change in the lifetime of the guest.
4181 * Note that host-state that does change is set elsewhere. E.g., host-state
4182 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4183 */
a547c6db 4184static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4185{
4186 u32 low32, high32;
4187 unsigned long tmpl;
4188 struct desc_ptr dt;
4189
b1a74bf8 4190 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4191 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4192 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4193
4194 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4195#ifdef CONFIG_X86_64
4196 /*
4197 * Load null selectors, so we can avoid reloading them in
4198 * __vmx_load_host_state(), in case userspace uses the null selectors
4199 * too (the expected case).
4200 */
4201 vmcs_write16(HOST_DS_SELECTOR, 0);
4202 vmcs_write16(HOST_ES_SELECTOR, 0);
4203#else
a3a8ff8e
NHE		 4204 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4205 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4206#endif
a3a8ff8e
NHE		 4207 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4208 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4209
4210 native_store_idt(&dt);
4211 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4212 vmx->host_idt_base = dt.address;
a3a8ff8e 4213
83287ea4 4214 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4215
4216 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4217 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4218 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4219 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4220
4221 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4222 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4223 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4224 }
4225}
4226
bf8179a0
NHE		 4227static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4228{
4229 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4230 if (enable_ept)
4231 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4232 if (is_guest_mode(&vmx->vcpu))
4233 vmx->vcpu.arch.cr4_guest_owned_bits &=
4234 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4235 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4236}
4237
01e439be
YZ		 4238static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4239{
4240 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4241
4242 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4243 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4244 return pin_based_exec_ctrl;
4245}
4246
bf8179a0
NHE		 4247static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4248{
4249 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4250 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4251 exec_control &= ~CPU_BASED_TPR_SHADOW;
4252#ifdef CONFIG_X86_64
4253 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4254 CPU_BASED_CR8_LOAD_EXITING;
4255#endif
4256 }
4257 if (!enable_ept)
4258 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4259 CPU_BASED_CR3_LOAD_EXITING |
4260 CPU_BASED_INVLPG_EXITING;
4261 return exec_control;
4262}
4263
4264static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4265{
4266 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4267 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4268 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4269 if (vmx->vpid == 0)
4270 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4271 if (!enable_ept) {
4272 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4273 enable_unrestricted_guest = 0;
ad756a16
MJ		 4274 /* Enable INVPCID for non-ept guests may cause performance regression. */
4275 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4276 }
4277 if (!enable_unrestricted_guest)
4278 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4279 if (!ple_gap)
4280 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4281 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4282 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4283 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4284 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4285 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4286 (handle_vmptrld).
4287 We can NOT enable shadow_vmcs here because we don't have yet
4288 a current VMCS12
4289 */
4290 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4291 return exec_control;
4292}
4293
ce88decf
XG		 4294static void ept_set_mmio_spte_mask(void)
4295{
4296 /*
4297 * EPT Misconfigurations can be generated if the value of bits 2:0
4298 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4299 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4300 * spte.
4301 */
885032b9 4302 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4303}
4304
6aa8b732
AK		 4305/*
4306 * Sets up the vmcs for emulated real mode.
4307 */
8b9cf98c 4308static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4309{
2e4ce7f5 4310#ifdef CONFIG_X86_64
6aa8b732 4311 unsigned long a;
2e4ce7f5 4312#endif
6aa8b732 4313 int i;
6aa8b732 4314
6aa8b732 4315 /* I/O */
3e7c73e9
AK		 4316 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4317 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4318
4607c2d7
AG		 4319 if (enable_shadow_vmcs) {
4320 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4321 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4322 }
25c5f225 4323 if (cpu_has_vmx_msr_bitmap())
5897297b 4324 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4325
6aa8b732
AK		 4326 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4327
6aa8b732 4328 /* Control */
01e439be 4329 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4330
bf8179a0 4331 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4332
83ff3b9d 4333 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4334 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4335 vmx_secondary_exec_control(vmx));
83ff3b9d 4336 }
f78e0e2e 4337
01e439be 4338 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4339 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4340 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4341 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4342 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4343
4344 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4345
4346 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4347 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4348 }
4349
4b8d54f9
ZE		 4350 if (ple_gap) {
4351 vmcs_write32(PLE_GAP, ple_gap);
4352 vmcs_write32(PLE_WINDOW, ple_window);
4353 }
4354
c3707958
XG		 4355 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4356 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4357 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4358
9581d442
AK		 4359 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4360 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4361 vmx_set_constant_host_state(vmx);
05b3e0c2 4362#ifdef CONFIG_X86_64
6aa8b732
AK		 4363 rdmsrl(MSR_FS_BASE, a);
4364 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4365 rdmsrl(MSR_GS_BASE, a);
4366 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4367#else
4368 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4369 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4370#endif
4371
2cc51560
ED		 4372 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4373 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4374 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4375 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4376 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4377
468d472f 4378 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4379 u32 msr_low, msr_high;
4380 u64 host_pat;
468d472f
SY		 4381 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4382 host_pat = msr_low | ((u64) msr_high << 32);
4383 /* Write the default value follow host pat */
4384 vmcs_write64(GUEST_IA32_PAT, host_pat);
4385 /* Keep arch.pat sync with GUEST_IA32_PAT */
4386 vmx->vcpu.arch.pat = host_pat;
4387 }
4388
6aa8b732
AK		 4389 for (i = 0; i < NR_VMX_MSR; ++i) {
4390 u32 index = vmx_msr_index[i];
4391 u32 data_low, data_high;
a2fa3e9f 4392 int j = vmx->nmsrs;
6aa8b732
AK		 4393
4394 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4395 continue;
432bd6cb
AK		 4396 if (wrmsr_safe(index, data_low, data_high) < 0)
4397 continue;
26bb0981
AK		 4398 vmx->guest_msrs[j].index = i;
4399 vmx->guest_msrs[j].data = 0;
d5696725 4400 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4401 ++vmx->nmsrs;
6aa8b732 4402 }
6aa8b732 4403
2961e876
GN		 4404
4405 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4406
4407 /* 22.2.1, 20.8.1 */
2961e876 4408 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4409
e00c8cf2 4410 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4411 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4412
4413 return 0;
4414}
4415
57f252f2 4416static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4417{
4418 struct vcpu_vmx *vmx = to_vmx(vcpu);
4419 u64 msr;
e00c8cf2 4420
7ffd92c5 4421 vmx->rmode.vm86_active = 0;
e00c8cf2 4422
3b86cd99
JK		 4423 vmx->soft_vnmi_blocked = 0;
4424
ad312c7c 4425 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4426 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4427 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4428 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4429 msr |= MSR_IA32_APICBASE_BSP;
4430 kvm_set_apic_base(&vmx->vcpu, msr);
4431
2fb92db1
AK		 4432 vmx_segment_cache_clear(vmx);
4433
5706be0d 4434 seg_setup(VCPU_SREG_CS);
66450a21 4435 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4436 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4437
4438 seg_setup(VCPU_SREG_DS);
4439 seg_setup(VCPU_SREG_ES);
4440 seg_setup(VCPU_SREG_FS);
4441 seg_setup(VCPU_SREG_GS);
4442 seg_setup(VCPU_SREG_SS);
4443
4444 vmcs_write16(GUEST_TR_SELECTOR, 0);
4445 vmcs_writel(GUEST_TR_BASE, 0);
4446 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4447 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4448
4449 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4450 vmcs_writel(GUEST_LDTR_BASE, 0);
4451 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4452 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4453
4454 vmcs_write32(GUEST_SYSENTER_CS, 0);
4455 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4456 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4457
4458 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4459 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4460
e00c8cf2
AK		 4461 vmcs_writel(GUEST_GDTR_BASE, 0);
4462 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4463
4464 vmcs_writel(GUEST_IDTR_BASE, 0);
4465 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4466
443381a8 4467 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4468 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4469 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4470
e00c8cf2
AK		 4471 /* Special registers */
4472 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4473
4474 setup_msrs(vmx);
4475
6aa8b732
AK		 4476 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4477
f78e0e2e
SY		 4478 if (cpu_has_vmx_tpr_shadow()) {
4479 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4480 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4481 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4482 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4483 vmcs_write32(TPR_THRESHOLD, 0);
4484 }
4485
4486 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4487 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4488 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4489
01e439be
YZ		 4490 if (vmx_vm_has_apicv(vcpu->kvm))
4491 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4492
2384d2b3
SY		 4493 if (vmx->vpid != 0)
4494 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4495
fa40052c 4496 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4497 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4498 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4499 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4500 vmx_fpu_activate(&vmx->vcpu);
4501 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4502
b9d762fa 4503 vpid_sync_context(vmx);
6aa8b732
AK		 4504}
4505
b6f1250e
NHE		 4506/*
4507 * In nested virtualization, check if L1 asked to exit on external interrupts.
4508 * For most existing hypervisors, this will always return true.
4509 */
4510static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4511{
4512 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4513 PIN_BASED_EXT_INTR_MASK;
4514}
4515
ea8ceb83
JK		 4516static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4517{
4518 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4519 PIN_BASED_NMI_EXITING;
4520}
4521
730dca42 4522static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4523{
4524 u32 cpu_based_vm_exec_control;
730dca42
JK		 4525
4526 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4527 /*
4528 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4529 * inject to L1 now because L2 must run. The caller will have
4530 * to make L2 exit right after entry, so we can inject to L1
4531 * more promptly.
b6f1250e 4532 */
730dca42 4533 return -EBUSY;
3b86cd99
JK		 4534
4535 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4536 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4537 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4538 return 0;
3b86cd99
JK		 4539}
4540
03b28f81 4541static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4542{
4543 u32 cpu_based_vm_exec_control;
4544
03b28f81
JK		 4545 if (!cpu_has_virtual_nmis())
4546 return enable_irq_window(vcpu);
4547
4548 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4549 return enable_irq_window(vcpu);
3b86cd99
JK		 4550
4551 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4552 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4553 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4554 return 0;
3b86cd99
JK		 4555}
4556
66fd3f7f 4557static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4558{
9c8cba37 4559 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4560 uint32_t intr;
4561 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4562
229456fc 4563 trace_kvm_inj_virq(irq);
2714d1d3 4564
fa89a817 4565 ++vcpu->stat.irq_injections;
7ffd92c5 4566 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4567 int inc_eip = 0;
4568 if (vcpu->arch.interrupt.soft)
4569 inc_eip = vcpu->arch.event_exit_inst_len;
4570 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4571 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4572 return;
4573 }
66fd3f7f
GN		 4574 intr = irq | INTR_INFO_VALID_MASK;
4575 if (vcpu->arch.interrupt.soft) {
4576 intr |= INTR_TYPE_SOFT_INTR;
4577 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4578 vmx->vcpu.arch.event_exit_inst_len);
4579 } else
4580 intr |= INTR_TYPE_EXT_INTR;
4581 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4582}
4583
f08864b4
SY		 4584static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4585{
66a5a347
JK		 4586 struct vcpu_vmx *vmx = to_vmx(vcpu);
4587
0b6ac343
NHE		 4588 if (is_guest_mode(vcpu))
4589 return;
4590
3b86cd99
JK		 4591 if (!cpu_has_virtual_nmis()) {
4592 /*
4593 * Tracking the NMI-blocked state in software is built upon
4594 * finding the next open IRQ window. This, in turn, depends on
4595 * well-behaving guests: They have to keep IRQs disabled at
4596 * least as long as the NMI handler runs. Otherwise we may
4597 * cause NMI nesting, maybe breaking the guest. But as this is
4598 * highly unlikely, we can live with the residual risk.
4599 */
4600 vmx->soft_vnmi_blocked = 1;
4601 vmx->vnmi_blocked_time = 0;
4602 }
4603
487b391d 4604 ++vcpu->stat.nmi_injections;
9d58b931 4605 vmx->nmi_known_unmasked = false;
7ffd92c5 4606 if (vmx->rmode.vm86_active) {
71f9833b 4607 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4608 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4609 return;
4610 }
f08864b4
SY		 4611 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4612 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4613}
4614
3cfc3092
JK		 4615static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4616{
4617 if (!cpu_has_virtual_nmis())
4618 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4619 if (to_vmx(vcpu)->nmi_known_unmasked)
4620 return false;
c332c83a 4621 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4622}
4623
4624static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4625{
4626 struct vcpu_vmx *vmx = to_vmx(vcpu);
4627
4628 if (!cpu_has_virtual_nmis()) {
4629 if (vmx->soft_vnmi_blocked != masked) {
4630 vmx->soft_vnmi_blocked = masked;
4631 vmx->vnmi_blocked_time = 0;
4632 }
4633 } else {
9d58b931 4634 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4635 if (masked)
4636 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4637 GUEST_INTR_STATE_NMI);
4638 else
4639 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4640 GUEST_INTR_STATE_NMI);
4641 }
4642}
4643
2505dc9f
JK		 4644static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4645{
ea8ceb83
JK		 4646 if (is_guest_mode(vcpu)) {
4647 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4648
4649 if (to_vmx(vcpu)->nested.nested_run_pending)
4650 return 0;
4651 if (nested_exit_on_nmi(vcpu)) {
4652 nested_vmx_vmexit(vcpu);
4653 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4654 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4655 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4656 /*
4657 * The NMI-triggered VM exit counts as injection:
4658 * clear this one and block further NMIs.
4659 */
4660 vcpu->arch.nmi_pending = 0;
4661 vmx_set_nmi_mask(vcpu, true);
4662 return 0;
4663 }
4664 }
4665
2505dc9f
JK		 4666 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4667 return 0;
4668
4669 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4670 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4671 | GUEST_INTR_STATE_NMI));
4672}
4673
78646121
GN		 4674static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4675{
e8457c67 4676 if (is_guest_mode(vcpu)) {
51cfe38e 4677 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4678
4679 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4680 return 0;
e8457c67
JK		 4681 if (nested_exit_on_intr(vcpu)) {
4682 nested_vmx_vmexit(vcpu);
4683 vmcs12->vm_exit_reason =
4684 EXIT_REASON_EXTERNAL_INTERRUPT;
4685 vmcs12->vm_exit_intr_info = 0;
4686 /*
4687 * fall through to normal code, but now in L1, not L2
4688 */
4689 }
b6f1250e
NHE		 4690 }
4691
c4282df9
GN		 4692 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4693 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4694 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4695}
4696
cbc94022
IE		 4697static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4698{
4699 int ret;
4700 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4701 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4702 .guest_phys_addr = addr,
4703 .memory_size = PAGE_SIZE * 3,
4704 .flags = 0,
4705 };
4706
47ae31e2 4707 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4708 if (ret)
4709 return ret;
bfc6d222 4710 kvm->arch.tss_addr = addr;
93ea5388
GN		 4711 if (!init_rmode_tss(kvm))
4712 return -ENOMEM;
4713
cbc94022
IE		 4714 return 0;
4715}
4716
0ca1b4f4 4717static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4718{
77ab6db0 4719 switch (vec) {
77ab6db0 4720 case BP_VECTOR:
c573cd22
JK		 4721 /*
4722 * Update instruction length as we may reinject the exception
4723 * from user space while in guest debugging mode.
4724 */
4725 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4726 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4727 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4728 return false;
4729 /* fall through */
4730 case DB_VECTOR:
4731 if (vcpu->guest_debug &
4732 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4733 return false;
d0bfb940
JK		 4734 /* fall through */
4735 case DE_VECTOR:
77ab6db0
JK		 4736 case OF_VECTOR:
4737 case BR_VECTOR:
4738 case UD_VECTOR:
4739 case DF_VECTOR:
4740 case SS_VECTOR:
4741 case GP_VECTOR:
4742 case MF_VECTOR:
0ca1b4f4
GN		 4743 return true;
4744 break;
77ab6db0 4745 }
0ca1b4f4
GN		 4746 return false;
4747}
4748
4749static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4750 int vec, u32 err_code)
4751{
4752 /*
4753 * Instruction with address size override prefix opcode 0x67
4754 * Cause the #SS fault with 0 error code in VM86 mode.
4755 */
4756 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4757 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4758 if (vcpu->arch.halt_request) {
4759 vcpu->arch.halt_request = 0;
4760 return kvm_emulate_halt(vcpu);
4761 }
4762 return 1;
4763 }
4764 return 0;
4765 }
4766
4767 /*
4768 * Forward all other exceptions that are valid in real mode.
4769 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4770 * the required debugging infrastructure rework.
4771 */
4772 kvm_queue_exception(vcpu, vec);
4773 return 1;
6aa8b732
AK		 4774}
4775
a0861c02
AK		 4776/*
4777 * Trigger machine check on the host. We assume all the MSRs are already set up
4778 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4779 * We pass a fake environment to the machine check handler because we want
4780 * the guest to be always treated like user space, no matter what context
4781 * it used internally.
4782 */
4783static void kvm_machine_check(void)
4784{
4785#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4786 struct pt_regs regs = {
4787 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4788 .flags = X86_EFLAGS_IF,
4789 };
4790
4791 do_machine_check(&regs, 0);
4792#endif
4793}
4794
851ba692 4795static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4796{
4797 /* already handled by vcpu_run */
4798 return 1;
4799}
4800
851ba692 4801static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4802{
1155f76a 4803 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4804 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4805 u32 intr_info, ex_no, error_code;
42dbaa5a 4806 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4807 u32 vect_info;
4808 enum emulation_result er;
4809
1155f76a 4810 vect_info = vmx->idt_vectoring_info;
88786475 4811 intr_info = vmx->exit_intr_info;
6aa8b732 4812
a0861c02 4813 if (is_machine_check(intr_info))
851ba692 4814 return handle_machine_check(vcpu);
a0861c02 4815
e4a41889 4816 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4817 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4818
4819 if (is_no_device(intr_info)) {
5fd86fcf 4820 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4821 return 1;
4822 }
4823
7aa81cc0 4824 if (is_invalid_opcode(intr_info)) {
51d8b661 4825 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4826 if (er != EMULATE_DONE)
7ee5d940 4827 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4828 return 1;
4829 }
4830
6aa8b732 4831 error_code = 0;
2e11384c 4832 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4833 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4834
4835 /*
4836 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4837 * MMIO, it is better to report an internal error.
4838 * See the comments in vmx_handle_exit.
4839 */
4840 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4841 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4842 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4843 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4844 vcpu->run->internal.ndata = 2;
4845 vcpu->run->internal.data[0] = vect_info;
4846 vcpu->run->internal.data[1] = intr_info;
4847 return 0;
4848 }
4849
6aa8b732 4850 if (is_page_fault(intr_info)) {
1439442c 4851 /* EPT won't cause page fault directly */
cf3ace79 4852 BUG_ON(enable_ept);
6aa8b732 4853 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4854 trace_kvm_page_fault(cr2, error_code);
4855
3298b75c 4856 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4857 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4858 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4859 }
4860
d0bfb940 4861 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4862
4863 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4864 return handle_rmode_exception(vcpu, ex_no, error_code);
4865
42dbaa5a
JK		 4866 switch (ex_no) {
4867 case DB_VECTOR:
4868 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4869 if (!(vcpu->guest_debug &
4870 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4871 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4872 kvm_queue_exception(vcpu, DB_VECTOR);
4873 return 1;
4874 }
4875 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4876 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4877 /* fall through */
4878 case BP_VECTOR:
c573cd22
JK		 4879 /*
4880 * Update instruction length as we may reinject #BP from
4881 * user space while in guest debugging mode. Reading it for
4882 * #DB as well causes no harm, it is not used in that case.
4883 */
4884 vmx->vcpu.arch.event_exit_inst_len =
4885 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4886 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4887 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4888 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4889 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4890 break;
4891 default:
d0bfb940
JK		 4892 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4893 kvm_run->ex.exception = ex_no;
4894 kvm_run->ex.error_code = error_code;
42dbaa5a 4895 break;
6aa8b732 4896 }
6aa8b732
AK		 4897 return 0;
4898}
4899
851ba692 4900static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4901{
1165f5fe 4902 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4903 return 1;
4904}
4905
851ba692 4906static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4907{
851ba692 4908 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4909 return 0;
4910}
6aa8b732 4911
851ba692 4912static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4913{
bfdaab09 4914 unsigned long exit_qualification;
34c33d16 4915 int size, in, string;
039576c0 4916 unsigned port;
6aa8b732 4917
bfdaab09 4918 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4919 string = (exit_qualification & 16) != 0;
cf8f70bf 4920 in = (exit_qualification & 8) != 0;
e70669ab 4921
cf8f70bf 4922 ++vcpu->stat.io_exits;
e70669ab 4923
cf8f70bf 4924 if (string || in)
51d8b661 4925 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4926
cf8f70bf
GN		 4927 port = exit_qualification >> 16;
4928 size = (exit_qualification & 7) + 1;
e93f36bc 4929 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4930
4931 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4932}
4933
102d8325
IM		 4934static void
4935vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4936{
4937 /*
4938 * Patch in the VMCALL instruction:
4939 */
4940 hypercall[0] = 0x0f;
4941 hypercall[1] = 0x01;
4942 hypercall[2] = 0xc1;
102d8325
IM		 4943}
4944
92fbc7b1
JK		 4945static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4946{
4947 unsigned long always_on = VMXON_CR0_ALWAYSON;
4948
4949 if (nested_vmx_secondary_ctls_high &
4950 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4951 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4952 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4953 return (val & always_on) == always_on;
4954}
4955
0fa06071 4956/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4957static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4958{
eeadf9e7 4959 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4960 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4961 unsigned long orig_val = val;
4962
eeadf9e7
NHE		 4963 /*
4964 * We get here when L2 changed cr0 in a way that did not change
4965 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4966 * but did change L0 shadowed bits. So we first calculate the
4967 * effective cr0 value that L1 would like to write into the
4968 * hardware. It consists of the L2-owned bits from the new
4969 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4970 */
1a0d74e6
JK		 4971 val = (val & ~vmcs12->cr0_guest_host_mask) |
4972 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4973
92fbc7b1 4974 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 4975 return 1;
1a0d74e6
JK		 4976
4977 if (kvm_set_cr0(vcpu, val))
4978 return 1;
4979 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4980 return 0;
1a0d74e6
JK		 4981 } else {
4982 if (to_vmx(vcpu)->nested.vmxon &&
4983 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4984 return 1;
eeadf9e7 4985 return kvm_set_cr0(vcpu, val);
1a0d74e6 4986 }
eeadf9e7
NHE		 4987}
4988
4989static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4990{
4991 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4992 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4993 unsigned long orig_val = val;
4994
4995 /* analogously to handle_set_cr0 */
4996 val = (val & ~vmcs12->cr4_guest_host_mask) |
4997 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4998 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4999 return 1;
1a0d74e6 5000 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5001 return 0;
5002 } else
5003 return kvm_set_cr4(vcpu, val);
5004}
5005
5006/* called to set cr0 as approriate for clts instruction exit. */
5007static void handle_clts(struct kvm_vcpu *vcpu)
5008{
5009 if (is_guest_mode(vcpu)) {
5010 /*
5011 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5012 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5013 * just pretend it's off (also in arch.cr0 for fpu_activate).
5014 */
5015 vmcs_writel(CR0_READ_SHADOW,
5016 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5017 vcpu->arch.cr0 &= ~X86_CR0_TS;
5018 } else
5019 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5020}
5021
851ba692 5022static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5023{
229456fc 5024 unsigned long exit_qualification, val;
6aa8b732
AK		 5025 int cr;
5026 int reg;
49a9b07e 5027 int err;
6aa8b732 5028
bfdaab09 5029 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5030 cr = exit_qualification & 15;
5031 reg = (exit_qualification >> 8) & 15;
5032 switch ((exit_qualification >> 4) & 3) {
5033 case 0: /* mov to cr */
229456fc
MT		 5034 val = kvm_register_read(vcpu, reg);
5035 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5036 switch (cr) {
5037 case 0:
eeadf9e7 5038 err = handle_set_cr0(vcpu, val);
db8fcefa 5039 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5040 return 1;
5041 case 3:
2390218b 5042 err = kvm_set_cr3(vcpu, val);
db8fcefa 5043 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5044 return 1;
5045 case 4:
eeadf9e7 5046 err = handle_set_cr4(vcpu, val);
db8fcefa 5047 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5048 return 1;
0a5fff19
GN		 5049 case 8: {
5050 u8 cr8_prev = kvm_get_cr8(vcpu);
5051 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5052 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5053 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5054 if (irqchip_in_kernel(vcpu->kvm))
5055 return 1;
5056 if (cr8_prev <= cr8)
5057 return 1;
851ba692 5058 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5059 return 0;
5060 }
4b8073e4 5061 }
6aa8b732 5062 break;
25c4c276 5063 case 2: /* clts */
eeadf9e7 5064 handle_clts(vcpu);
4d4ec087 5065 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5066 skip_emulated_instruction(vcpu);
6b52d186 5067 vmx_fpu_activate(vcpu);
25c4c276 5068 return 1;
6aa8b732
AK		 5069 case 1: /*mov from cr*/
5070 switch (cr) {
5071 case 3:
9f8fe504
AK		 5072 val = kvm_read_cr3(vcpu);
5073 kvm_register_write(vcpu, reg, val);
5074 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5075 skip_emulated_instruction(vcpu);
5076 return 1;
5077 case 8:
229456fc
MT		 5078 val = kvm_get_cr8(vcpu);
5079 kvm_register_write(vcpu, reg, val);
5080 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5081 skip_emulated_instruction(vcpu);
5082 return 1;
5083 }
5084 break;
5085 case 3: /* lmsw */
a1f83a74 5086 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5087 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5088 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5089
5090 skip_emulated_instruction(vcpu);
5091 return 1;
5092 default:
5093 break;
5094 }
851ba692 5095 vcpu->run->exit_reason = 0;
a737f256 5096 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5097 (int)(exit_qualification >> 4) & 3, cr);
5098 return 0;
5099}
5100
851ba692 5101static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5102{
bfdaab09 5103 unsigned long exit_qualification;
6aa8b732
AK		 5104 int dr, reg;
5105
f2483415 5106 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5107 if (!kvm_require_cpl(vcpu, 0))
5108 return 1;
42dbaa5a
JK		 5109 dr = vmcs_readl(GUEST_DR7);
5110 if (dr & DR7_GD) {
5111 /*
5112 * As the vm-exit takes precedence over the debug trap, we
5113 * need to emulate the latter, either for the host or the
5114 * guest debugging itself.
5115 */
5116 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5117 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5118 vcpu->run->debug.arch.dr7 = dr;
5119 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5120 vmcs_readl(GUEST_CS_BASE) +
5121 vmcs_readl(GUEST_RIP);
851ba692
AK		 5122 vcpu->run->debug.arch.exception = DB_VECTOR;
5123 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5124 return 0;
5125 } else {
5126 vcpu->arch.dr7 &= ~DR7_GD;
5127 vcpu->arch.dr6 |= DR6_BD;
5128 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5129 kvm_queue_exception(vcpu, DB_VECTOR);
5130 return 1;
5131 }
5132 }
5133
bfdaab09 5134 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5135 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5136 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5137 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5138 unsigned long val;
5139 if (!kvm_get_dr(vcpu, dr, &val))
5140 kvm_register_write(vcpu, reg, val);
5141 } else
5142 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5143 skip_emulated_instruction(vcpu);
5144 return 1;
5145}
5146
020df079
GN		 5147static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5148{
5149 vmcs_writel(GUEST_DR7, val);
5150}
5151
851ba692 5152static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5153{
06465c5a
AK		 5154 kvm_emulate_cpuid(vcpu);
5155 return 1;
6aa8b732
AK		 5156}
5157
851ba692 5158static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5159{
ad312c7c 5160 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5161 u64 data;
5162
5163 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5164 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5165 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5166 return 1;
5167 }
5168
229456fc 5169 trace_kvm_msr_read(ecx, data);
2714d1d3 5170
6aa8b732 5171 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5172 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5173 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5174 skip_emulated_instruction(vcpu);
5175 return 1;
5176}
5177
851ba692 5178static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5179{
8fe8ab46 5180 struct msr_data msr;
ad312c7c
ZX		 5181 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5182 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5183 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5184
8fe8ab46
WA		 5185 msr.data = data;
5186 msr.index = ecx;
5187 msr.host_initiated = false;
5188 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5189 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5190 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5191 return 1;
5192 }
5193
59200273 5194 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5195 skip_emulated_instruction(vcpu);
5196 return 1;
5197}
5198
851ba692 5199static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5200{
3842d135 5201 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5202 return 1;
5203}
5204
851ba692 5205static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5206{
85f455f7
ED		 5207 u32 cpu_based_vm_exec_control;
5208
5209 /* clear pending irq */
5210 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5211 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5212 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5213
3842d135
AK		 5214 kvm_make_request(KVM_REQ_EVENT, vcpu);
5215
a26bf12a 5216 ++vcpu->stat.irq_window_exits;
2714d1d3 5217
c1150d8c
DL		 5218 /*
5219 * If the user space waits to inject interrupts, exit as soon as
5220 * possible
5221 */
8061823a 5222 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5223 vcpu->run->request_interrupt_window &&
8061823a 5224 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5225 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5226 return 0;
5227 }
6aa8b732
AK		 5228 return 1;
5229}
5230
851ba692 5231static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5232{
5233 skip_emulated_instruction(vcpu);
d3bef15f 5234 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5235}
5236
851ba692 5237static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5238{
510043da 5239 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5240 kvm_emulate_hypercall(vcpu);
5241 return 1;
c21415e8
IM		 5242}
5243
ec25d5e6
GN		 5244static int handle_invd(struct kvm_vcpu *vcpu)
5245{
51d8b661 5246 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5247}
5248
851ba692 5249static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5250{
f9c617f6 5251 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5252
5253 kvm_mmu_invlpg(vcpu, exit_qualification);
5254 skip_emulated_instruction(vcpu);
5255 return 1;
5256}
5257
fee84b07
AK		 5258static int handle_rdpmc(struct kvm_vcpu *vcpu)
5259{
5260 int err;
5261
5262 err = kvm_rdpmc(vcpu);
5263 kvm_complete_insn_gp(vcpu, err);
5264
5265 return 1;
5266}
5267
851ba692 5268static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5269{
5270 skip_emulated_instruction(vcpu);
f5f48ee1 5271 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5272 return 1;
5273}
5274
2acf923e
DC		 5275static int handle_xsetbv(struct kvm_vcpu *vcpu)
5276{
5277 u64 new_bv = kvm_read_edx_eax(vcpu);
5278 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5279
5280 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5281 skip_emulated_instruction(vcpu);
5282 return 1;
5283}
5284
851ba692 5285static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5286{
58fbbf26
KT		 5287 if (likely(fasteoi)) {
5288 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5289 int access_type, offset;
5290
5291 access_type = exit_qualification & APIC_ACCESS_TYPE;
5292 offset = exit_qualification & APIC_ACCESS_OFFSET;
5293 /*
5294 * Sane guest uses MOV to write EOI, with written value
5295 * not cared. So make a short-circuit here by avoiding
5296 * heavy instruction emulation.
5297 */
5298 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5299 (offset == APIC_EOI)) {
5300 kvm_lapic_set_eoi(vcpu);
5301 skip_emulated_instruction(vcpu);
5302 return 1;
5303 }
5304 }
51d8b661 5305 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5306}
5307
c7c9c56c
YZ		 5308static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5309{
5310 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5311 int vector = exit_qualification & 0xff;
5312
5313 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5314 kvm_apic_set_eoi_accelerated(vcpu, vector);
5315 return 1;
5316}
5317
83d4c286
YZ		 5318static int handle_apic_write(struct kvm_vcpu *vcpu)
5319{
5320 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5321 u32 offset = exit_qualification & 0xfff;
5322
5323 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5324 kvm_apic_write_nodecode(vcpu, offset);
5325 return 1;
5326}
5327
851ba692 5328static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5329{
60637aac 5330 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5331 unsigned long exit_qualification;
e269fb21
JK		 5332 bool has_error_code = false;
5333 u32 error_code = 0;
37817f29 5334 u16 tss_selector;
7f3d35fd 5335 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5336
5337 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5338 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5339 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5340
5341 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5342
5343 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5344 if (reason == TASK_SWITCH_GATE && idt_v) {
5345 switch (type) {
5346 case INTR_TYPE_NMI_INTR:
5347 vcpu->arch.nmi_injected = false;
654f06fc 5348 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5349 break;
5350 case INTR_TYPE_EXT_INTR:
66fd3f7f 5351 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5352 kvm_clear_interrupt_queue(vcpu);
5353 break;
5354 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5355 if (vmx->idt_vectoring_info &
5356 VECTORING_INFO_DELIVER_CODE_MASK) {
5357 has_error_code = true;
5358 error_code =
5359 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5360 }
5361 /* fall through */
64a7ec06
GN		 5362 case INTR_TYPE_SOFT_EXCEPTION:
5363 kvm_clear_exception_queue(vcpu);
5364 break;
5365 default:
5366 break;
5367 }
60637aac 5368 }
37817f29
IE		 5369 tss_selector = exit_qualification;
5370
64a7ec06
GN		 5371 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5372 type != INTR_TYPE_EXT_INTR &&
5373 type != INTR_TYPE_NMI_INTR))
5374 skip_emulated_instruction(vcpu);
5375
7f3d35fd
KW		 5376 if (kvm_task_switch(vcpu, tss_selector,
5377 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5378 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5379 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5380 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5381 vcpu->run->internal.ndata = 0;
42dbaa5a 5382 return 0;
acb54517 5383 }
42dbaa5a
JK		 5384
5385 /* clear all local breakpoint enable flags */
5386 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5387
5388 /*
5389 * TODO: What about debug traps on tss switch?
5390 * Are we supposed to inject them and update dr6?
5391 */
5392
5393 return 1;
37817f29
IE		 5394}
5395
851ba692 5396static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5397{
f9c617f6 5398 unsigned long exit_qualification;
1439442c 5399 gpa_t gpa;
4f5982a5 5400 u32 error_code;
1439442c 5401 int gla_validity;
1439442c 5402
f9c617f6 5403 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5404
1439442c
SY		 5405 gla_validity = (exit_qualification >> 7) & 0x3;
5406 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5407 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5408 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5409 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5410 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5411 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5412 (long unsigned int)exit_qualification);
851ba692
AK		 5413 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5414 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5415 return 0;
1439442c
SY		 5416 }
5417
0be9c7a8
GN		 5418 /*
5419 * EPT violation happened while executing iret from NMI,
5420 * "blocked by NMI" bit has to be set before next VM entry.
5421 * There are errata that may cause this bit to not be set:
5422 * AAK134, BY25.
5423 */
bcd1c294
GN		 5424 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5425 cpu_has_virtual_nmis() &&
5426 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5427 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5428
1439442c 5429 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5430 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5431
5432 /* It is a write fault? */
5433 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5434 /* It is a fetch fault? */
5435 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5436 /* ept page table is present? */
5437 error_code |= (exit_qualification >> 3) & 0x1;
5438
25d92081
YZ		 5439 vcpu->arch.exit_qualification = exit_qualification;
5440
4f5982a5 5441 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5442}
5443
68f89400
MT		 5444static u64 ept_rsvd_mask(u64 spte, int level)
5445{
5446 int i;
5447 u64 mask = 0;
5448
5449 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5450 mask |= (1ULL << i);
5451
5452 if (level > 2)
5453 /* bits 7:3 reserved */
5454 mask |= 0xf8;
5455 else if (level == 2) {
5456 if (spte & (1ULL << 7))
5457 /* 2MB ref, bits 20:12 reserved */
5458 mask |= 0x1ff000;
5459 else
5460 /* bits 6:3 reserved */
5461 mask |= 0x78;
5462 }
5463
5464 return mask;
5465}
5466
5467static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5468 int level)
5469{
5470 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5471
5472 /* 010b (write-only) */
5473 WARN_ON((spte & 0x7) == 0x2);
5474
5475 /* 110b (write/execute) */
5476 WARN_ON((spte & 0x7) == 0x6);
5477
5478 /* 100b (execute-only) and value not supported by logical processor */
5479 if (!cpu_has_vmx_ept_execute_only())
5480 WARN_ON((spte & 0x7) == 0x4);
5481
5482 /* not 000b */
5483 if ((spte & 0x7)) {
5484 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5485
5486 if (rsvd_bits != 0) {
5487 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5488 __func__, rsvd_bits);
5489 WARN_ON(1);
5490 }
5491
5492 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5493 u64 ept_mem_type = (spte & 0x38) >> 3;
5494
5495 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5496 ept_mem_type == 7) {
5497 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5498 __func__, ept_mem_type);
5499 WARN_ON(1);
5500 }
5501 }
5502 }
5503}
5504
851ba692 5505static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5506{
5507 u64 sptes[4];
ce88decf 5508 int nr_sptes, i, ret;
68f89400
MT		 5509 gpa_t gpa;
5510
5511 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5512
ce88decf 5513 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5514 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5515 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5516 EMULATE_DONE;
f8f55942
XG		 5517
5518 if (unlikely(ret == RET_MMIO_PF_INVALID))
5519 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5520
b37fbea6 5521 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5522 return 1;
5523
5524 /* It is the real ept misconfig */
68f89400
MT		 5525 printk(KERN_ERR "EPT: Misconfiguration.\n");
5526 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5527
5528 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5529
5530 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5531 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5532
851ba692
AK		 5533 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5534 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5535
5536 return 0;
5537}
5538
851ba692 5539static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5540{
5541 u32 cpu_based_vm_exec_control;
5542
5543 /* clear pending NMI */
5544 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5545 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5546 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5547 ++vcpu->stat.nmi_window_exits;
3842d135 5548 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5549
5550 return 1;
5551}
5552
80ced186 5553static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5554{
8b3079a5
AK		 5555 struct vcpu_vmx *vmx = to_vmx(vcpu);
5556 enum emulation_result err = EMULATE_DONE;
80ced186 5557 int ret = 1;
49e9d557
AK		 5558 u32 cpu_exec_ctrl;
5559 bool intr_window_requested;
b8405c18 5560 unsigned count = 130;
49e9d557
AK		 5561
5562 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5563 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5564
b8405c18 5565 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5566 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5567 return handle_interrupt_window(&vmx->vcpu);
5568
de87dcdd
AK		 5569 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5570 return 1;
5571
991eebf9 5572 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5573
ac0a48c3 5574 if (err == EMULATE_USER_EXIT) {
94452b9e 5575 ++vcpu->stat.mmio_exits;
80ced186
MG		 5576 ret = 0;
5577 goto out;
5578 }
1d5a4d9b 5579
de5f70e0
AK		 5580 if (err != EMULATE_DONE) {
5581 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5582 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5583 vcpu->run->internal.ndata = 0;
6d77dbfc 5584 return 0;
de5f70e0 5585 }
ea953ef0 5586
8d76c49e
GN		 5587 if (vcpu->arch.halt_request) {
5588 vcpu->arch.halt_request = 0;
5589 ret = kvm_emulate_halt(vcpu);
5590 goto out;
5591 }
5592
ea953ef0 5593 if (signal_pending(current))
80ced186 5594 goto out;
ea953ef0
MG		 5595 if (need_resched())
5596 schedule();
5597 }
5598
14168786 5599 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5600out:
5601 return ret;
ea953ef0
MG		 5602}
5603
4b8d54f9
ZE		 5604/*
5605 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5606 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5607 */
9fb41ba8 5608static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5609{
5610 skip_emulated_instruction(vcpu);
5611 kvm_vcpu_on_spin(vcpu);
5612
5613 return 1;
5614}
5615
59708670
SY		 5616static int handle_invalid_op(struct kvm_vcpu *vcpu)
5617{
5618 kvm_queue_exception(vcpu, UD_VECTOR);
5619 return 1;
5620}
5621
ff2f6fe9
NHE		 5622/*
5623 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5624 * We could reuse a single VMCS for all the L2 guests, but we also want the
5625 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5626 * allows keeping them loaded on the processor, and in the future will allow
5627 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5628 * every entry if they never change.
5629 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5630 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5631 *
5632 * The following functions allocate and free a vmcs02 in this pool.
5633 */
5634
5635/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5636static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5637{
5638 struct vmcs02_list *item;
5639 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5640 if (item->vmptr == vmx->nested.current_vmptr) {
5641 list_move(&item->list, &vmx->nested.vmcs02_pool);
5642 return &item->vmcs02;
5643 }
5644
5645 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5646 /* Recycle the least recently used VMCS. */
5647 item = list_entry(vmx->nested.vmcs02_pool.prev,
5648 struct vmcs02_list, list);
5649 item->vmptr = vmx->nested.current_vmptr;
5650 list_move(&item->list, &vmx->nested.vmcs02_pool);
5651 return &item->vmcs02;
5652 }
5653
5654 /* Create a new VMCS */
0fa24ce3 5655 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5656 if (!item)
5657 return NULL;
5658 item->vmcs02.vmcs = alloc_vmcs();
5659 if (!item->vmcs02.vmcs) {
5660 kfree(item);
5661 return NULL;
5662 }
5663 loaded_vmcs_init(&item->vmcs02);
5664 item->vmptr = vmx->nested.current_vmptr;
5665 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5666 vmx->nested.vmcs02_num++;
5667 return &item->vmcs02;
5668}
5669
5670/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5671static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5672{
5673 struct vmcs02_list *item;
5674 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5675 if (item->vmptr == vmptr) {
5676 free_loaded_vmcs(&item->vmcs02);
5677 list_del(&item->list);
5678 kfree(item);
5679 vmx->nested.vmcs02_num--;
5680 return;
5681 }
5682}
5683
5684/*
5685 * Free all VMCSs saved for this vcpu, except the one pointed by
5686 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5687 * currently used, if running L2), and vmcs01 when running L2.
5688 */
5689static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5690{
5691 struct vmcs02_list *item, *n;
5692 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5693 if (vmx->loaded_vmcs != &item->vmcs02)
5694 free_loaded_vmcs(&item->vmcs02);
5695 list_del(&item->list);
5696 kfree(item);
5697 }
5698 vmx->nested.vmcs02_num = 0;
5699
5700 if (vmx->loaded_vmcs != &vmx->vmcs01)
5701 free_loaded_vmcs(&vmx->vmcs01);
5702}
5703
0658fbaa
ACL		 5704/*
5705 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5706 * set the success or error code of an emulated VMX instruction, as specified
5707 * by Vol 2B, VMX Instruction Reference, "Conventions".
5708 */
5709static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5710{
5711 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5712 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5713 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5714}
5715
5716static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5717{
5718 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5719 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5720 X86_EFLAGS_SF | X86_EFLAGS_OF))
5721 | X86_EFLAGS_CF);
5722}
5723
145c28dd 5724static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5725 u32 vm_instruction_error)
5726{
5727 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5728 /*
5729 * failValid writes the error number to the current VMCS, which
5730 * can't be done there isn't a current VMCS.
5731 */
5732 nested_vmx_failInvalid(vcpu);
5733 return;
5734 }
5735 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5736 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5737 X86_EFLAGS_SF | X86_EFLAGS_OF))
5738 | X86_EFLAGS_ZF);
5739 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5740 /*
5741 * We don't need to force a shadow sync because
5742 * VM_INSTRUCTION_ERROR is not shadowed
5743 */
5744}
145c28dd 5745
ec378aee
NHE		 5746/*
5747 * Emulate the VMXON instruction.
5748 * Currently, we just remember that VMX is active, and do not save or even
5749 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5750 * do not currently need to store anything in that guest-allocated memory
5751 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5752 * argument is different from the VMXON pointer (which the spec says they do).
5753 */
5754static int handle_vmon(struct kvm_vcpu *vcpu)
5755{
5756 struct kvm_segment cs;
5757 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5758 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5759 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5760 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5761
5762 /* The Intel VMX Instruction Reference lists a bunch of bits that
5763 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5764 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5765 * Otherwise, we should fail with #UD. We test these now:
5766 */
5767 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5768 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5769 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5770 kvm_queue_exception(vcpu, UD_VECTOR);
5771 return 1;
5772 }
5773
5774 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5775 if (is_long_mode(vcpu) && !cs.l) {
5776 kvm_queue_exception(vcpu, UD_VECTOR);
5777 return 1;
5778 }
5779
5780 if (vmx_get_cpl(vcpu)) {
5781 kvm_inject_gp(vcpu, 0);
5782 return 1;
5783 }
145c28dd
AG		 5784 if (vmx->nested.vmxon) {
5785 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5786 skip_emulated_instruction(vcpu);
5787 return 1;
5788 }
b3897a49
NHE		 5789
5790 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5791 != VMXON_NEEDED_FEATURES) {
5792 kvm_inject_gp(vcpu, 0);
5793 return 1;
5794 }
5795
8de48833
AG		 5796 if (enable_shadow_vmcs) {
5797 shadow_vmcs = alloc_vmcs();
5798 if (!shadow_vmcs)
5799 return -ENOMEM;
5800 /* mark vmcs as shadow */
5801 shadow_vmcs->revision_id |= (1u << 31);
5802 /* init shadow vmcs */
5803 vmcs_clear(shadow_vmcs);
5804 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5805 }
ec378aee 5806
ff2f6fe9
NHE		 5807 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5808 vmx->nested.vmcs02_num = 0;
5809
ec378aee
NHE		 5810 vmx->nested.vmxon = true;
5811
5812 skip_emulated_instruction(vcpu);
a25eb114 5813 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5814 return 1;
5815}
5816
5817/*
5818 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5819 * for running VMX instructions (except VMXON, whose prerequisites are
5820 * slightly different). It also specifies what exception to inject otherwise.
5821 */
5822static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5823{
5824 struct kvm_segment cs;
5825 struct vcpu_vmx *vmx = to_vmx(vcpu);
5826
5827 if (!vmx->nested.vmxon) {
5828 kvm_queue_exception(vcpu, UD_VECTOR);
5829 return 0;
5830 }
5831
5832 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5833 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5834 (is_long_mode(vcpu) && !cs.l)) {
5835 kvm_queue_exception(vcpu, UD_VECTOR);
5836 return 0;
5837 }
5838
5839 if (vmx_get_cpl(vcpu)) {
5840 kvm_inject_gp(vcpu, 0);
5841 return 0;
5842 }
5843
5844 return 1;
5845}
5846
e7953d7f
AG		 5847static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5848{
8a1b9dd0 5849 u32 exec_control;
012f83cb
AG		 5850 if (enable_shadow_vmcs) {
5851 if (vmx->nested.current_vmcs12 != NULL) {
5852 /* copy to memory all shadowed fields in case
5853 they were modified */
5854 copy_shadow_to_vmcs12(vmx);
5855 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5856 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5857 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5858 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5859 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5860 }
5861 }
e7953d7f
AG		 5862 kunmap(vmx->nested.current_vmcs12_page);
5863 nested_release_page(vmx->nested.current_vmcs12_page);
5864}
5865
ec378aee
NHE		 5866/*
5867 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5868 * just stops using VMX.
5869 */
5870static void free_nested(struct vcpu_vmx *vmx)
5871{
5872 if (!vmx->nested.vmxon)
5873 return;
5874 vmx->nested.vmxon = false;
a9d30f33 5875 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5876 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5877 vmx->nested.current_vmptr = -1ull;
5878 vmx->nested.current_vmcs12 = NULL;
5879 }
e7953d7f
AG		 5880 if (enable_shadow_vmcs)
5881 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5882 /* Unpin physical memory we referred to in current vmcs02 */
5883 if (vmx->nested.apic_access_page) {
5884 nested_release_page(vmx->nested.apic_access_page);
5885 vmx->nested.apic_access_page = 0;
5886 }
ff2f6fe9
NHE		 5887
5888 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5889}
5890
5891/* Emulate the VMXOFF instruction */
5892static int handle_vmoff(struct kvm_vcpu *vcpu)
5893{
5894 if (!nested_vmx_check_permission(vcpu))
5895 return 1;
5896 free_nested(to_vmx(vcpu));
5897 skip_emulated_instruction(vcpu);
a25eb114 5898 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5899 return 1;
5900}
5901
064aea77
NHE		 5902/*
5903 * Decode the memory-address operand of a vmx instruction, as recorded on an
5904 * exit caused by such an instruction (run by a guest hypervisor).
5905 * On success, returns 0. When the operand is invalid, returns 1 and throws
5906 * #UD or #GP.
5907 */
5908static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5909 unsigned long exit_qualification,
5910 u32 vmx_instruction_info, gva_t *ret)
5911{
5912 /*
5913 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5914 * Execution", on an exit, vmx_instruction_info holds most of the
5915 * addressing components of the operand. Only the displacement part
5916 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5917 * For how an actual address is calculated from all these components,
5918 * refer to Vol. 1, "Operand Addressing".
5919 */
5920 int scaling = vmx_instruction_info & 3;
5921 int addr_size = (vmx_instruction_info >> 7) & 7;
5922 bool is_reg = vmx_instruction_info & (1u << 10);
5923 int seg_reg = (vmx_instruction_info >> 15) & 7;
5924 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5925 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5926 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5927 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5928
5929 if (is_reg) {
5930 kvm_queue_exception(vcpu, UD_VECTOR);
5931 return 1;
5932 }
5933
5934 /* Addr = segment_base + offset */
5935 /* offset = base + [index * scale] + displacement */
5936 *ret = vmx_get_segment_base(vcpu, seg_reg);
5937 if (base_is_valid)
5938 *ret += kvm_register_read(vcpu, base_reg);
5939 if (index_is_valid)
5940 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5941 *ret += exit_qualification; /* holds the displacement */
5942
5943 if (addr_size == 1) /* 32 bit */
5944 *ret &= 0xffffffff;
5945
5946 /*
5947 * TODO: throw #GP (and return 1) in various cases that the VM*
5948 * instructions require it - e.g., offset beyond segment limit,
5949 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5950 * address, and so on. Currently these are not checked.
5951 */
5952 return 0;
5953}
5954
27d6c865
NHE		 5955/* Emulate the VMCLEAR instruction */
5956static int handle_vmclear(struct kvm_vcpu *vcpu)
5957{
5958 struct vcpu_vmx *vmx = to_vmx(vcpu);
5959 gva_t gva;
5960 gpa_t vmptr;
5961 struct vmcs12 *vmcs12;
5962 struct page *page;
5963 struct x86_exception e;
5964
5965 if (!nested_vmx_check_permission(vcpu))
5966 return 1;
5967
5968 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5969 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5970 return 1;
5971
5972 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5973 sizeof(vmptr), &e)) {
5974 kvm_inject_page_fault(vcpu, &e);
5975 return 1;
5976 }
5977
5978 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5979 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5980 skip_emulated_instruction(vcpu);
5981 return 1;
5982 }
5983
5984 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5985 nested_release_vmcs12(vmx);
27d6c865
NHE		 5986 vmx->nested.current_vmptr = -1ull;
5987 vmx->nested.current_vmcs12 = NULL;
5988 }
5989
5990 page = nested_get_page(vcpu, vmptr);
5991 if (page == NULL) {
5992 /*
5993 * For accurate processor emulation, VMCLEAR beyond available
5994 * physical memory should do nothing at all. However, it is
5995 * possible that a nested vmx bug, not a guest hypervisor bug,
5996 * resulted in this case, so let's shut down before doing any
5997 * more damage:
5998 */
5999 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6000 return 1;
6001 }
6002 vmcs12 = kmap(page);
6003 vmcs12->launch_state = 0;
6004 kunmap(page);
6005 nested_release_page(page);
6006
6007 nested_free_vmcs02(vmx, vmptr);
6008
6009 skip_emulated_instruction(vcpu);
6010 nested_vmx_succeed(vcpu);
6011 return 1;
6012}
6013
cd232ad0
NHE		 6014static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6015
6016/* Emulate the VMLAUNCH instruction */
6017static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6018{
6019 return nested_vmx_run(vcpu, true);
6020}
6021
6022/* Emulate the VMRESUME instruction */
6023static int handle_vmresume(struct kvm_vcpu *vcpu)
6024{
6025
6026 return nested_vmx_run(vcpu, false);
6027}
6028
49f705c5
NHE		 6029enum vmcs_field_type {
6030 VMCS_FIELD_TYPE_U16 = 0,
6031 VMCS_FIELD_TYPE_U64 = 1,
6032 VMCS_FIELD_TYPE_U32 = 2,
6033 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6034};
6035
6036static inline int vmcs_field_type(unsigned long field)
6037{
6038 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6039 return VMCS_FIELD_TYPE_U32;
6040 return (field >> 13) & 0x3 ;
6041}
6042
6043static inline int vmcs_field_readonly(unsigned long field)
6044{
6045 return (((field >> 10) & 0x3) == 1);
6046}
6047
6048/*
6049 * Read a vmcs12 field. Since these can have varying lengths and we return
6050 * one type, we chose the biggest type (u64) and zero-extend the return value
6051 * to that size. Note that the caller, handle_vmread, might need to use only
6052 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6053 * 64-bit fields are to be returned).
6054 */
6055static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6056 unsigned long field, u64 *ret)
6057{
6058 short offset = vmcs_field_to_offset(field);
6059 char *p;
6060
6061 if (offset < 0)
6062 return 0;
6063
6064 p = ((char *)(get_vmcs12(vcpu))) + offset;
6065
6066 switch (vmcs_field_type(field)) {
6067 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6068 *ret = *((natural_width *)p);
6069 return 1;
6070 case VMCS_FIELD_TYPE_U16:
6071 *ret = *((u16 *)p);
6072 return 1;
6073 case VMCS_FIELD_TYPE_U32:
6074 *ret = *((u32 *)p);
6075 return 1;
6076 case VMCS_FIELD_TYPE_U64:
6077 *ret = *((u64 *)p);
6078 return 1;
6079 default:
6080 return 0; /* can never happen. */
6081 }
6082}
6083
20b97fea
AG		 6084
6085static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6086 unsigned long field, u64 field_value){
6087 short offset = vmcs_field_to_offset(field);
6088 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6089 if (offset < 0)
6090 return false;
6091
6092 switch (vmcs_field_type(field)) {
6093 case VMCS_FIELD_TYPE_U16:
6094 *(u16 *)p = field_value;
6095 return true;
6096 case VMCS_FIELD_TYPE_U32:
6097 *(u32 *)p = field_value;
6098 return true;
6099 case VMCS_FIELD_TYPE_U64:
6100 *(u64 *)p = field_value;
6101 return true;
6102 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6103 *(natural_width *)p = field_value;
6104 return true;
6105 default:
6106 return false; /* can never happen. */
6107 }
6108
6109}
6110
16f5b903
AG		 6111static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6112{
6113 int i;
6114 unsigned long field;
6115 u64 field_value;
6116 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6117 const unsigned long *fields = shadow_read_write_fields;
6118 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6119
6120 vmcs_load(shadow_vmcs);
6121
6122 for (i = 0; i < num_fields; i++) {
6123 field = fields[i];
6124 switch (vmcs_field_type(field)) {
6125 case VMCS_FIELD_TYPE_U16:
6126 field_value = vmcs_read16(field);
6127 break;
6128 case VMCS_FIELD_TYPE_U32:
6129 field_value = vmcs_read32(field);
6130 break;
6131 case VMCS_FIELD_TYPE_U64:
6132 field_value = vmcs_read64(field);
6133 break;
6134 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6135 field_value = vmcs_readl(field);
6136 break;
6137 }
6138 vmcs12_write_any(&vmx->vcpu, field, field_value);
6139 }
6140
6141 vmcs_clear(shadow_vmcs);
6142 vmcs_load(vmx->loaded_vmcs->vmcs);
6143}
6144
c3114420
AG		 6145static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6146{
c2bae893
MK		 6147 const unsigned long *fields[] = {
6148 shadow_read_write_fields,
6149 shadow_read_only_fields
c3114420 6150 };
c2bae893 6151 const int max_fields[] = {
c3114420
AG		 6152 max_shadow_read_write_fields,
6153 max_shadow_read_only_fields
6154 };
6155 int i, q;
6156 unsigned long field;
6157 u64 field_value = 0;
6158 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6159
6160 vmcs_load(shadow_vmcs);
6161
c2bae893 6162 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6163 for (i = 0; i < max_fields[q]; i++) {
6164 field = fields[q][i];
6165 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6166
6167 switch (vmcs_field_type(field)) {
6168 case VMCS_FIELD_TYPE_U16:
6169 vmcs_write16(field, (u16)field_value);
6170 break;
6171 case VMCS_FIELD_TYPE_U32:
6172 vmcs_write32(field, (u32)field_value);
6173 break;
6174 case VMCS_FIELD_TYPE_U64:
6175 vmcs_write64(field, (u64)field_value);
6176 break;
6177 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6178 vmcs_writel(field, (long)field_value);
6179 break;
6180 }
6181 }
6182 }
6183
6184 vmcs_clear(shadow_vmcs);
6185 vmcs_load(vmx->loaded_vmcs->vmcs);
6186}
6187
49f705c5
NHE		 6188/*
6189 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6190 * used before) all generate the same failure when it is missing.
6191 */
6192static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6193{
6194 struct vcpu_vmx *vmx = to_vmx(vcpu);
6195 if (vmx->nested.current_vmptr == -1ull) {
6196 nested_vmx_failInvalid(vcpu);
6197 skip_emulated_instruction(vcpu);
6198 return 0;
6199 }
6200 return 1;
6201}
6202
6203static int handle_vmread(struct kvm_vcpu *vcpu)
6204{
6205 unsigned long field;
6206 u64 field_value;
6207 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6208 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6209 gva_t gva = 0;
6210
6211 if (!nested_vmx_check_permission(vcpu) ||
6212 !nested_vmx_check_vmcs12(vcpu))
6213 return 1;
6214
6215 /* Decode instruction info and find the field to read */
6216 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6217 /* Read the field, zero-extended to a u64 field_value */
6218 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6219 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6220 skip_emulated_instruction(vcpu);
6221 return 1;
6222 }
6223 /*
6224 * Now copy part of this value to register or memory, as requested.
6225 * Note that the number of bits actually copied is 32 or 64 depending
6226 * on the guest's mode (32 or 64 bit), not on the given field's length.
6227 */
6228 if (vmx_instruction_info & (1u << 10)) {
6229 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6230 field_value);
6231 } else {
6232 if (get_vmx_mem_address(vcpu, exit_qualification,
6233 vmx_instruction_info, &gva))
6234 return 1;
6235 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6236 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6237 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6238 }
6239
6240 nested_vmx_succeed(vcpu);
6241 skip_emulated_instruction(vcpu);
6242 return 1;
6243}
6244
6245
6246static int handle_vmwrite(struct kvm_vcpu *vcpu)
6247{
6248 unsigned long field;
6249 gva_t gva;
6250 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6251 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6252 /* The value to write might be 32 or 64 bits, depending on L1's long
6253 * mode, and eventually we need to write that into a field of several
6254 * possible lengths. The code below first zero-extends the value to 64
6255 * bit (field_value), and then copies only the approriate number of
6256 * bits into the vmcs12 field.
6257 */
6258 u64 field_value = 0;
6259 struct x86_exception e;
6260
6261 if (!nested_vmx_check_permission(vcpu) ||
6262 !nested_vmx_check_vmcs12(vcpu))
6263 return 1;
6264
6265 if (vmx_instruction_info & (1u << 10))
6266 field_value = kvm_register_read(vcpu,
6267 (((vmx_instruction_info) >> 3) & 0xf));
6268 else {
6269 if (get_vmx_mem_address(vcpu, exit_qualification,
6270 vmx_instruction_info, &gva))
6271 return 1;
6272 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6273 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6274 kvm_inject_page_fault(vcpu, &e);
6275 return 1;
6276 }
6277 }
6278
6279
6280 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6281 if (vmcs_field_readonly(field)) {
6282 nested_vmx_failValid(vcpu,
6283 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6284 skip_emulated_instruction(vcpu);
6285 return 1;
6286 }
6287
20b97fea 6288 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6289 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6290 skip_emulated_instruction(vcpu);
6291 return 1;
6292 }
6293
6294 nested_vmx_succeed(vcpu);
6295 skip_emulated_instruction(vcpu);
6296 return 1;
6297}
6298
63846663
NHE		 6299/* Emulate the VMPTRLD instruction */
6300static int handle_vmptrld(struct kvm_vcpu *vcpu)
6301{
6302 struct vcpu_vmx *vmx = to_vmx(vcpu);
6303 gva_t gva;
6304 gpa_t vmptr;
6305 struct x86_exception e;
8a1b9dd0 6306 u32 exec_control;
63846663
NHE		 6307
6308 if (!nested_vmx_check_permission(vcpu))
6309 return 1;
6310
6311 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6312 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6313 return 1;
6314
6315 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6316 sizeof(vmptr), &e)) {
6317 kvm_inject_page_fault(vcpu, &e);
6318 return 1;
6319 }
6320
6321 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6322 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6323 skip_emulated_instruction(vcpu);
6324 return 1;
6325 }
6326
6327 if (vmx->nested.current_vmptr != vmptr) {
6328 struct vmcs12 *new_vmcs12;
6329 struct page *page;
6330 page = nested_get_page(vcpu, vmptr);
6331 if (page == NULL) {
6332 nested_vmx_failInvalid(vcpu);
6333 skip_emulated_instruction(vcpu);
6334 return 1;
6335 }
6336 new_vmcs12 = kmap(page);
6337 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6338 kunmap(page);
6339 nested_release_page_clean(page);
6340 nested_vmx_failValid(vcpu,
6341 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6342 skip_emulated_instruction(vcpu);
6343 return 1;
6344 }
e7953d7f
AG		 6345 if (vmx->nested.current_vmptr != -1ull)
6346 nested_release_vmcs12(vmx);
63846663
NHE		 6347
6348 vmx->nested.current_vmptr = vmptr;
6349 vmx->nested.current_vmcs12 = new_vmcs12;
6350 vmx->nested.current_vmcs12_page = page;
012f83cb 6351 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6352 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6353 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6354 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6355 vmcs_write64(VMCS_LINK_POINTER,
6356 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6357 vmx->nested.sync_shadow_vmcs = true;
6358 }
63846663
NHE		 6359 }
6360
6361 nested_vmx_succeed(vcpu);
6362 skip_emulated_instruction(vcpu);
6363 return 1;
6364}
6365
6a4d7550
NHE		 6366/* Emulate the VMPTRST instruction */
6367static int handle_vmptrst(struct kvm_vcpu *vcpu)
6368{
6369 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6370 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6371 gva_t vmcs_gva;
6372 struct x86_exception e;
6373
6374 if (!nested_vmx_check_permission(vcpu))
6375 return 1;
6376
6377 if (get_vmx_mem_address(vcpu, exit_qualification,
6378 vmx_instruction_info, &vmcs_gva))
6379 return 1;
6380 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6381 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6382 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6383 sizeof(u64), &e)) {
6384 kvm_inject_page_fault(vcpu, &e);
6385 return 1;
6386 }
6387 nested_vmx_succeed(vcpu);
6388 skip_emulated_instruction(vcpu);
6389 return 1;
6390}
6391
bfd0a56b
NHE		 6392/* Emulate the INVEPT instruction */
6393static int handle_invept(struct kvm_vcpu *vcpu)
6394{
6395 u32 vmx_instruction_info, types;
6396 unsigned long type;
6397 gva_t gva;
6398 struct x86_exception e;
6399 struct {
6400 u64 eptp, gpa;
6401 } operand;
6402 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6403
6404 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6405 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6406 kvm_queue_exception(vcpu, UD_VECTOR);
6407 return 1;
6408 }
6409
6410 if (!nested_vmx_check_permission(vcpu))
6411 return 1;
6412
6413 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6414 kvm_queue_exception(vcpu, UD_VECTOR);
6415 return 1;
6416 }
6417
6418 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6419 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6420
6421 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6422
6423 if (!(types & (1UL << type))) {
6424 nested_vmx_failValid(vcpu,
6425 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6426 return 1;
6427 }
6428
6429 /* According to the Intel VMX instruction reference, the memory
6430 * operand is read even if it isn't needed (e.g., for type==global)
6431 */
6432 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6433 vmx_instruction_info, &gva))
6434 return 1;
6435 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6436 sizeof(operand), &e)) {
6437 kvm_inject_page_fault(vcpu, &e);
6438 return 1;
6439 }
6440
6441 switch (type) {
6442 case VMX_EPT_EXTENT_CONTEXT:
6443 if ((operand.eptp & eptp_mask) !=
6444 (nested_ept_get_cr3(vcpu) & eptp_mask))
6445 break;
6446 case VMX_EPT_EXTENT_GLOBAL:
6447 kvm_mmu_sync_roots(vcpu);
6448 kvm_mmu_flush_tlb(vcpu);
6449 nested_vmx_succeed(vcpu);
6450 break;
6451 default:
6452 BUG_ON(1);
6453 break;
6454 }
6455
6456 skip_emulated_instruction(vcpu);
6457 return 1;
6458}
6459
6aa8b732
AK		 6460/*
6461 * The exit handlers return 1 if the exit was handled fully and guest execution
6462 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6463 * to be done to userspace and return 0.
6464 */
772e0318 6465static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6466 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6467 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6468 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6469 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6470 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6471 [EXIT_REASON_CR_ACCESS] = handle_cr,
6472 [EXIT_REASON_DR_ACCESS] = handle_dr,
6473 [EXIT_REASON_CPUID] = handle_cpuid,
6474 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6475 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6476 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6477 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6478 [EXIT_REASON_INVD] = handle_invd,
a7052897 6479 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6480 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6481 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6482 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6483 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6484 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6485 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6486 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6487 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6488 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6489 [EXIT_REASON_VMOFF] = handle_vmoff,
6490 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6491 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6492 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6493 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6494 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6495 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6496 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6497 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6498 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6499 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6500 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6501 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6502 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6503 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6504 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6505};
6506
6507static const int kvm_vmx_max_exit_handlers =
50a3485c 6508 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6509
908a7bdd
JK		 6510static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6511 struct vmcs12 *vmcs12)
6512{
6513 unsigned long exit_qualification;
6514 gpa_t bitmap, last_bitmap;
6515 unsigned int port;
6516 int size;
6517 u8 b;
6518
6519 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6520 return 1;
6521
6522 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6523 return 0;
6524
6525 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6526
6527 port = exit_qualification >> 16;
6528 size = (exit_qualification & 7) + 1;
6529
6530 last_bitmap = (gpa_t)-1;
6531 b = -1;
6532
6533 while (size > 0) {
6534 if (port < 0x8000)
6535 bitmap = vmcs12->io_bitmap_a;
6536 else if (port < 0x10000)
6537 bitmap = vmcs12->io_bitmap_b;
6538 else
6539 return 1;
6540 bitmap += (port & 0x7fff) / 8;
6541
6542 if (last_bitmap != bitmap)
6543 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6544 return 1;
6545 if (b & (1 << (port & 7)))
6546 return 1;
6547
6548 port++;
6549 size--;
6550 last_bitmap = bitmap;
6551 }
6552
6553 return 0;
6554}
6555
644d711a
NHE		 6556/*
6557 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6558 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6559 * disinterest in the current event (read or write a specific MSR) by using an
6560 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6561 */
6562static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6563 struct vmcs12 *vmcs12, u32 exit_reason)
6564{
6565 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6566 gpa_t bitmap;
6567
cbd29cb6 6568 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6569 return 1;
6570
6571 /*
6572 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6573 * for the four combinations of read/write and low/high MSR numbers.
6574 * First we need to figure out which of the four to use:
6575 */
6576 bitmap = vmcs12->msr_bitmap;
6577 if (exit_reason == EXIT_REASON_MSR_WRITE)
6578 bitmap += 2048;
6579 if (msr_index >= 0xc0000000) {
6580 msr_index -= 0xc0000000;
6581 bitmap += 1024;
6582 }
6583
6584 /* Then read the msr_index'th bit from this bitmap: */
6585 if (msr_index < 1024*8) {
6586 unsigned char b;
bd31a7f5
JK		 6587 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6588 return 1;
644d711a
NHE		 6589 return 1 & (b >> (msr_index & 7));
6590 } else
6591 return 1; /* let L1 handle the wrong parameter */
6592}
6593
6594/*
6595 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6596 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6597 * intercept (via guest_host_mask etc.) the current event.
6598 */
6599static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6600 struct vmcs12 *vmcs12)
6601{
6602 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6603 int cr = exit_qualification & 15;
6604 int reg = (exit_qualification >> 8) & 15;
6605 unsigned long val = kvm_register_read(vcpu, reg);
6606
6607 switch ((exit_qualification >> 4) & 3) {
6608 case 0: /* mov to cr */
6609 switch (cr) {
6610 case 0:
6611 if (vmcs12->cr0_guest_host_mask &
6612 (val ^ vmcs12->cr0_read_shadow))
6613 return 1;
6614 break;
6615 case 3:
6616 if ((vmcs12->cr3_target_count >= 1 &&
6617 vmcs12->cr3_target_value0 == val) ||
6618 (vmcs12->cr3_target_count >= 2 &&
6619 vmcs12->cr3_target_value1 == val) ||
6620 (vmcs12->cr3_target_count >= 3 &&
6621 vmcs12->cr3_target_value2 == val) ||
6622 (vmcs12->cr3_target_count >= 4 &&
6623 vmcs12->cr3_target_value3 == val))
6624 return 0;
6625 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6626 return 1;
6627 break;
6628 case 4:
6629 if (vmcs12->cr4_guest_host_mask &
6630 (vmcs12->cr4_read_shadow ^ val))
6631 return 1;
6632 break;
6633 case 8:
6634 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6635 return 1;
6636 break;
6637 }
6638 break;
6639 case 2: /* clts */
6640 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6641 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6642 return 1;
6643 break;
6644 case 1: /* mov from cr */
6645 switch (cr) {
6646 case 3:
6647 if (vmcs12->cpu_based_vm_exec_control &
6648 CPU_BASED_CR3_STORE_EXITING)
6649 return 1;
6650 break;
6651 case 8:
6652 if (vmcs12->cpu_based_vm_exec_control &
6653 CPU_BASED_CR8_STORE_EXITING)
6654 return 1;
6655 break;
6656 }
6657 break;
6658 case 3: /* lmsw */
6659 /*
6660 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6661 * cr0. Other attempted changes are ignored, with no exit.
6662 */
6663 if (vmcs12->cr0_guest_host_mask & 0xe &
6664 (val ^ vmcs12->cr0_read_shadow))
6665 return 1;
6666 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6667 !(vmcs12->cr0_read_shadow & 0x1) &&
6668 (val & 0x1))
6669 return 1;
6670 break;
6671 }
6672 return 0;
6673}
6674
6675/*
6676 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6677 * should handle it ourselves in L0 (and then continue L2). Only call this
6678 * when in is_guest_mode (L2).
6679 */
6680static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6681{
644d711a
NHE		 6682 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6683 struct vcpu_vmx *vmx = to_vmx(vcpu);
6684 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6685 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6686
6687 if (vmx->nested.nested_run_pending)
6688 return 0;
6689
6690 if (unlikely(vmx->fail)) {
bd80158a
JK		 6691 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6692 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6693 return 1;
6694 }
6695
6696 switch (exit_reason) {
6697 case EXIT_REASON_EXCEPTION_NMI:
6698 if (!is_exception(intr_info))
6699 return 0;
6700 else if (is_page_fault(intr_info))
6701 return enable_ept;
e504c909
AB		 6702 else if (is_no_device(intr_info) &&
6703 !(nested_read_cr0(vmcs12) & X86_CR0_TS))
6704 return 0;
644d711a
NHE		 6705 return vmcs12->exception_bitmap &
6706 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6707 case EXIT_REASON_EXTERNAL_INTERRUPT:
6708 return 0;
6709 case EXIT_REASON_TRIPLE_FAULT:
6710 return 1;
6711 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6712 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6713 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6714 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6715 case EXIT_REASON_TASK_SWITCH:
6716 return 1;
6717 case EXIT_REASON_CPUID:
6718 return 1;
6719 case EXIT_REASON_HLT:
6720 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6721 case EXIT_REASON_INVD:
6722 return 1;
6723 case EXIT_REASON_INVLPG:
6724 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6725 case EXIT_REASON_RDPMC:
6726 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6727 case EXIT_REASON_RDTSC:
6728 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6729 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6730 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6731 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6732 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6733 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6734 case EXIT_REASON_INVEPT:
644d711a
NHE		 6735 /*
6736 * VMX instructions trap unconditionally. This allows L1 to
6737 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6738 */
6739 return 1;
6740 case EXIT_REASON_CR_ACCESS:
6741 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6742 case EXIT_REASON_DR_ACCESS:
6743 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6744 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6745 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6746 case EXIT_REASON_MSR_READ:
6747 case EXIT_REASON_MSR_WRITE:
6748 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6749 case EXIT_REASON_INVALID_STATE:
6750 return 1;
6751 case EXIT_REASON_MWAIT_INSTRUCTION:
6752 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6753 case EXIT_REASON_MONITOR_INSTRUCTION:
6754 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6755 case EXIT_REASON_PAUSE_INSTRUCTION:
6756 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6757 nested_cpu_has2(vmcs12,
6758 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6759 case EXIT_REASON_MCE_DURING_VMENTRY:
6760 return 0;
6761 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6762 return 1;
6763 case EXIT_REASON_APIC_ACCESS:
6764 return nested_cpu_has2(vmcs12,
6765 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6766 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6767 /*
6768 * L0 always deals with the EPT violation. If nested EPT is
6769 * used, and the nested mmu code discovers that the address is
6770 * missing in the guest EPT table (EPT12), the EPT violation
6771 * will be injected with nested_ept_inject_page_fault()
6772 */
6773 return 0;
644d711a 6774 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6775 /*
6776 * L2 never uses directly L1's EPT, but rather L0's own EPT
6777 * table (shadow on EPT) or a merged EPT table that L0 built
6778 * (EPT on EPT). So any problems with the structure of the
6779 * table is L0's fault.
6780 */
644d711a 6781 return 0;
0238ea91
JK		 6782 case EXIT_REASON_PREEMPTION_TIMER:
6783 return vmcs12->pin_based_vm_exec_control &
6784 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6785 case EXIT_REASON_WBINVD:
6786 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6787 case EXIT_REASON_XSETBV:
6788 return 1;
6789 default:
6790 return 1;
6791 }
6792}
6793
586f9607
AK		 6794static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6795{
6796 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6797 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6798}
6799
7854cbca
ACL		 6800static void nested_adjust_preemption_timer(struct kvm_vcpu *vcpu)
6801{
6802 u64 delta_tsc_l1;
6803 u32 preempt_val_l1, preempt_val_l2, preempt_scale;
6804
6805 if (!(get_vmcs12(vcpu)->pin_based_vm_exec_control &
6806 PIN_BASED_VMX_PREEMPTION_TIMER))
6807 return;
6808 preempt_scale = native_read_msr(MSR_IA32_VMX_MISC) &
6809 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE;
6810 preempt_val_l2 = vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
6811 delta_tsc_l1 = vmx_read_l1_tsc(vcpu, native_read_tsc())
6812 - vcpu->arch.last_guest_tsc;
6813 preempt_val_l1 = delta_tsc_l1 >> preempt_scale;
6814 if (preempt_val_l2 <= preempt_val_l1)
6815 preempt_val_l2 = 0;
6816 else
6817 preempt_val_l2 -= preempt_val_l1;
6818 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, preempt_val_l2);
6819}
6820
6aa8b732
AK		 6821/*
6822 * The guest has exited. See if we can fix it or if we need userspace
6823 * assistance.
6824 */
851ba692 6825static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6826{
29bd8a78 6827 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6828 u32 exit_reason = vmx->exit_reason;
1155f76a 6829 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6830
80ced186 6831 /* If guest state is invalid, start emulating */
14168786 6832 if (vmx->emulation_required)
80ced186 6833 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6834
644d711a
NHE		 6835 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6836 nested_vmx_vmexit(vcpu);
6837 return 1;
6838 }
6839
5120702e
MG		 6840 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6841 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6842 vcpu->run->fail_entry.hardware_entry_failure_reason
6843 = exit_reason;
6844 return 0;
6845 }
6846
29bd8a78 6847 if (unlikely(vmx->fail)) {
851ba692
AK		 6848 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6849 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6850 = vmcs_read32(VM_INSTRUCTION_ERROR);
6851 return 0;
6852 }
6aa8b732 6853
b9bf6882
XG		 6854 /*
6855 * Note:
6856 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6857 * delivery event since it indicates guest is accessing MMIO.
6858 * The vm-exit can be triggered again after return to guest that
6859 * will cause infinite loop.
6860 */
d77c26fc 6861 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6862 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6863 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6864 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6865 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6866 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6867 vcpu->run->internal.ndata = 2;
6868 vcpu->run->internal.data[0] = vectoring_info;
6869 vcpu->run->internal.data[1] = exit_reason;
6870 return 0;
6871 }
3b86cd99 6872
644d711a
NHE		 6873 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6874 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6875 get_vmcs12(vcpu))))) {
c4282df9 6876 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6877 vmx->soft_vnmi_blocked = 0;
3b86cd99 6878 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6879 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6880 /*
6881 * This CPU don't support us in finding the end of an
6882 * NMI-blocked window if the guest runs with IRQs
6883 * disabled. So we pull the trigger after 1 s of
6884 * futile waiting, but inform the user about this.
6885 */
6886 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6887 "state on VCPU %d after 1 s timeout\n",
6888 __func__, vcpu->vcpu_id);
6889 vmx->soft_vnmi_blocked = 0;
3b86cd99 6890 }
3b86cd99
JK		 6891 }
6892
6aa8b732
AK		 6893 if (exit_reason < kvm_vmx_max_exit_handlers
6894 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6895 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6896 else {
851ba692
AK		 6897 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6898 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6899 }
6900 return 0;
6901}
6902
95ba8273 6903static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6904{
95ba8273 6905 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6906 vmcs_write32(TPR_THRESHOLD, 0);
6907 return;
6908 }
6909
95ba8273 6910 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6911}
6912
8d14695f
YZ		 6913static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6914{
6915 u32 sec_exec_control;
6916
6917 /*
6918 * There is not point to enable virtualize x2apic without enable
6919 * apicv
6920 */
c7c9c56c
YZ		 6921 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6922 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6923 return;
6924
6925 if (!vm_need_tpr_shadow(vcpu->kvm))
6926 return;
6927
6928 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6929
6930 if (set) {
6931 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6932 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6933 } else {
6934 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6935 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6936 }
6937 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6938
6939 vmx_set_msr_bitmap(vcpu);
6940}
6941
c7c9c56c
YZ		 6942static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6943{
6944 u16 status;
6945 u8 old;
6946
6947 if (!vmx_vm_has_apicv(kvm))
6948 return;
6949
6950 if (isr == -1)
6951 isr = 0;
6952
6953 status = vmcs_read16(GUEST_INTR_STATUS);
6954 old = status >> 8;
6955 if (isr != old) {
6956 status &= 0xff;
6957 status |= isr << 8;
6958 vmcs_write16(GUEST_INTR_STATUS, status);
6959 }
6960}
6961
6962static void vmx_set_rvi(int vector)
6963{
6964 u16 status;
6965 u8 old;
6966
6967 status = vmcs_read16(GUEST_INTR_STATUS);
6968 old = (u8)status & 0xff;
6969 if ((u8)vector != old) {
6970 status &= ~0xff;
6971 status |= (u8)vector;
6972 vmcs_write16(GUEST_INTR_STATUS, status);
6973 }
6974}
6975
6976static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6977{
6978 if (max_irr == -1)
6979 return;
6980
6981 vmx_set_rvi(max_irr);
6982}
6983
6984static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6985{
3d81bc7e
YZ		 6986 if (!vmx_vm_has_apicv(vcpu->kvm))
6987 return;
6988
c7c9c56c
YZ		 6989 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6990 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6991 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6992 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6993}
6994
51aa01d1 6995static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6996{
00eba012
AK		 6997 u32 exit_intr_info;
6998
6999 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7000 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7001 return;
7002
c5ca8e57 7003 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7004 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7005
7006 /* Handle machine checks before interrupts are enabled */
00eba012 7007 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7008 kvm_machine_check();
7009
20f65983 7010 /* We need to handle NMIs before interrupts are enabled */
00eba012 7011 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7012 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7013 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7014 asm("int $2");
ff9d07a0
ZY		 7015 kvm_after_handle_nmi(&vmx->vcpu);
7016 }
51aa01d1 7017}
20f65983 7018
a547c6db
YZ		 7019static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7020{
7021 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7022
7023 /*
7024 * If external interrupt exists, IF bit is set in rflags/eflags on the
7025 * interrupt stack frame, and interrupt will be enabled on a return
7026 * from interrupt handler.
7027 */
7028 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7029 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7030 unsigned int vector;
7031 unsigned long entry;
7032 gate_desc *desc;
7033 struct vcpu_vmx *vmx = to_vmx(vcpu);
7034#ifdef CONFIG_X86_64
7035 unsigned long tmp;
7036#endif
7037
7038 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7039 desc = (gate_desc *)vmx->host_idt_base + vector;
7040 entry = gate_offset(*desc);
7041 asm volatile(
7042#ifdef CONFIG_X86_64
7043 "mov %%" _ASM_SP ", %[sp]\n\t"
7044 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7045 "push $%c[ss]\n\t"
7046 "push %[sp]\n\t"
7047#endif
7048 "pushf\n\t"
7049 "orl $0x200, (%%" _ASM_SP ")\n\t"
7050 __ASM_SIZE(push) " $%c[cs]\n\t"
7051 "call *%[entry]\n\t"
7052 :
7053#ifdef CONFIG_X86_64
7054 [sp]"=&r"(tmp)
7055#endif
7056 :
7057 [entry]"r"(entry),
7058 [ss]"i"(__KERNEL_DS),
7059 [cs]"i"(__KERNEL_CS)
7060 );
7061 } else
7062 local_irq_enable();
7063}
7064
51aa01d1
AK		 7065static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7066{
c5ca8e57 7067 u32 exit_intr_info;
51aa01d1
AK		 7068 bool unblock_nmi;
7069 u8 vector;
7070 bool idtv_info_valid;
7071
7072 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7073
cf393f75 7074 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7075 if (vmx->nmi_known_unmasked)
7076 return;
c5ca8e57
AK		 7077 /*
7078 * Can't use vmx->exit_intr_info since we're not sure what
7079 * the exit reason is.
7080 */
7081 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7082 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7083 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7084 /*
7b4a25cb 7085 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7086 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7087 * a guest IRET fault.
7b4a25cb
GN		 7088 * SDM 3: 23.2.2 (September 2008)
7089 * Bit 12 is undefined in any of the following cases:
7090 * If the VM exit sets the valid bit in the IDT-vectoring
7091 * information field.
7092 * If the VM exit is due to a double fault.
cf393f75 7093 */
7b4a25cb
GN		 7094 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7095 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7096 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7097 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7098 else
7099 vmx->nmi_known_unmasked =
7100 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7101 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7102 } else if (unlikely(vmx->soft_vnmi_blocked))
7103 vmx->vnmi_blocked_time +=
7104 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7105}
7106
3ab66e8a 7107static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7108 u32 idt_vectoring_info,
7109 int instr_len_field,
7110 int error_code_field)
51aa01d1 7111{
51aa01d1
AK		 7112 u8 vector;
7113 int type;
7114 bool idtv_info_valid;
7115
7116 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7117
3ab66e8a
JK		 7118 vcpu->arch.nmi_injected = false;
7119 kvm_clear_exception_queue(vcpu);
7120 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7121
7122 if (!idtv_info_valid)
7123 return;
7124
3ab66e8a 7125 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7126
668f612f
AK		 7127 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7128 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7129
64a7ec06 7130 switch (type) {
37b96e98 7131 case INTR_TYPE_NMI_INTR:
3ab66e8a 7132 vcpu->arch.nmi_injected = true;
668f612f 7133 /*
7b4a25cb 7134 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7135 * Clear bit "block by NMI" before VM entry if a NMI
7136 * delivery faulted.
668f612f 7137 */
3ab66e8a 7138 vmx_set_nmi_mask(vcpu, false);
37b96e98 7139 break;
37b96e98 7140 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7141 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7142 /* fall through */
7143 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7144 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7145 u32 err = vmcs_read32(error_code_field);
851eb667 7146 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7147 } else
851eb667 7148 kvm_requeue_exception(vcpu, vector);
37b96e98 7149 break;
66fd3f7f 7150 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7151 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7152 /* fall through */
37b96e98 7153 case INTR_TYPE_EXT_INTR:
3ab66e8a 7154 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7155 break;
7156 default:
7157 break;
f7d9238f 7158 }
cf393f75
AK		 7159}
7160
83422e17
AK		 7161static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7162{
3ab66e8a 7163 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7164 VM_EXIT_INSTRUCTION_LEN,
7165 IDT_VECTORING_ERROR_CODE);
7166}
7167
b463a6f7
AK		 7168static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7169{
3ab66e8a 7170 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7171 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7172 VM_ENTRY_INSTRUCTION_LEN,
7173 VM_ENTRY_EXCEPTION_ERROR_CODE);
7174
7175 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7176}
7177
d7cd9796
GN		 7178static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7179{
7180 int i, nr_msrs;
7181 struct perf_guest_switch_msr *msrs;
7182
7183 msrs = perf_guest_get_msrs(&nr_msrs);
7184
7185 if (!msrs)
7186 return;
7187
7188 for (i = 0; i < nr_msrs; i++)
7189 if (msrs[i].host == msrs[i].guest)
7190 clear_atomic_switch_msr(vmx, msrs[i].msr);
7191 else
7192 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7193 msrs[i].host);
7194}
7195
a3b5ba49 7196static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7197{
a2fa3e9f 7198 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7199 unsigned long debugctlmsr;
104f226b
AK		 7200
7201 /* Record the guest's net vcpu time for enforced NMI injections. */
7202 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7203 vmx->entry_time = ktime_get();
7204
7205 /* Don't enter VMX if guest state is invalid, let the exit handler
7206 start emulation until we arrive back to a valid state */
14168786 7207 if (vmx->emulation_required)
104f226b
AK		 7208 return;
7209
012f83cb
AG		 7210 if (vmx->nested.sync_shadow_vmcs) {
7211 copy_vmcs12_to_shadow(vmx);
7212 vmx->nested.sync_shadow_vmcs = false;
7213 }
7214
104f226b
AK		 7215 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7216 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7217 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7218 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7219
7220 /* When single-stepping over STI and MOV SS, we must clear the
7221 * corresponding interruptibility bits in the guest state. Otherwise
7222 * vmentry fails as it then expects bit 14 (BS) in pending debug
7223 * exceptions being set, but that's not correct for the guest debugging
7224 * case. */
7225 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7226 vmx_set_interrupt_shadow(vcpu, 0);
7227
d7cd9796 7228 atomic_switch_perf_msrs(vmx);
2a7921b7 7229 debugctlmsr = get_debugctlmsr();
d7cd9796 7230
7854cbca
ACL		 7231 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending)
7232 nested_adjust_preemption_timer(vcpu);
d462b819 7233 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7234 asm(
6aa8b732 7235 /* Store host registers */
b188c81f
AK		 7236 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7237 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7238 "push %%" _ASM_CX " \n\t"
7239 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7240 "je 1f \n\t"
b188c81f 7241 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7242 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7243 "1: \n\t"
d3edefc0 7244 /* Reload cr2 if changed */
b188c81f
AK		 7245 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7246 "mov %%cr2, %%" _ASM_DX " \n\t"
7247 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7248 "je 2f \n\t"
b188c81f 7249 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7250 "2: \n\t"
6aa8b732 7251 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7252 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7253 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7254 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7255 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7256 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7257 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7258 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7259 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7260#ifdef CONFIG_X86_64
e08aa78a
AK		 7261 "mov %c[r8](%0), %%r8 \n\t"
7262 "mov %c[r9](%0), %%r9 \n\t"
7263 "mov %c[r10](%0), %%r10 \n\t"
7264 "mov %c[r11](%0), %%r11 \n\t"
7265 "mov %c[r12](%0), %%r12 \n\t"
7266 "mov %c[r13](%0), %%r13 \n\t"
7267 "mov %c[r14](%0), %%r14 \n\t"
7268 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7269#endif
b188c81f 7270 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7271
6aa8b732 7272 /* Enter guest mode */
83287ea4 7273 "jne 1f \n\t"
4ecac3fd 7274 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7275 "jmp 2f \n\t"
7276 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7277 "2: "
6aa8b732 7278 /* Save guest registers, load host registers, keep flags */
b188c81f 7279 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7280 "pop %0 \n\t"
b188c81f
AK		 7281 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7282 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7283 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7284 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7285 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7286 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7287 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7288#ifdef CONFIG_X86_64
e08aa78a
AK		 7289 "mov %%r8, %c[r8](%0) \n\t"
7290 "mov %%r9, %c[r9](%0) \n\t"
7291 "mov %%r10, %c[r10](%0) \n\t"
7292 "mov %%r11, %c[r11](%0) \n\t"
7293 "mov %%r12, %c[r12](%0) \n\t"
7294 "mov %%r13, %c[r13](%0) \n\t"
7295 "mov %%r14, %c[r14](%0) \n\t"
7296 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7297#endif
b188c81f
AK		 7298 "mov %%cr2, %%" _ASM_AX " \n\t"
7299 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7300
b188c81f 7301 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7302 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7303 ".pushsection .rodata \n\t"
7304 ".global vmx_return \n\t"
7305 "vmx_return: " _ASM_PTR " 2b \n\t"
7306 ".popsection"
e08aa78a 7307 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7308 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7309 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7310 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7311 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7312 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7313 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7314 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7315 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7316 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7317 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7318#ifdef CONFIG_X86_64
ad312c7c
ZX		 7319 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7320 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7321 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7322 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7323 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7324 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7325 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7326 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7327#endif
40712fae
AK		 7328 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7329 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7330 : "cc", "memory"
7331#ifdef CONFIG_X86_64
b188c81f 7332 , "rax", "rbx", "rdi", "rsi"
c2036300 7333 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7334#else
7335 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7336#endif
7337 );
6aa8b732 7338
2a7921b7
GN		 7339 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7340 if (debugctlmsr)
7341 update_debugctlmsr(debugctlmsr);
7342
aa67f609
AK		 7343#ifndef CONFIG_X86_64
7344 /*
7345 * The sysexit path does not restore ds/es, so we must set them to
7346 * a reasonable value ourselves.
7347 *
7348 * We can't defer this to vmx_load_host_state() since that function
7349 * may be executed in interrupt context, which saves and restore segments
7350 * around it, nullifying its effect.
7351 */
7352 loadsegment(ds, __USER_DS);
7353 loadsegment(es, __USER_DS);
7354#endif
7355
6de4f3ad 7356 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7357 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7358 | (1 << VCPU_EXREG_CPL)
aff48baa 7359 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7360 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7361 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7362 vcpu->arch.regs_dirty = 0;
7363
1155f76a
AK		 7364 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7365
d462b819 7366 vmx->loaded_vmcs->launched = 1;
1b6269db 7367
51aa01d1 7368 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7369 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7370
e0b890d3
GN		 7371 /*
7372 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7373 * we did not inject a still-pending event to L1 now because of
7374 * nested_run_pending, we need to re-enable this bit.
7375 */
7376 if (vmx->nested.nested_run_pending)
7377 kvm_make_request(KVM_REQ_EVENT, vcpu);
7378
7379 vmx->nested.nested_run_pending = 0;
7380
51aa01d1
AK		 7381 vmx_complete_atomic_exit(vmx);
7382 vmx_recover_nmi_blocking(vmx);
cf393f75 7383 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7384}
7385
6aa8b732
AK		 7386static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7387{
fb3f0f51
RR		 7388 struct vcpu_vmx *vmx = to_vmx(vcpu);
7389
cdbecfc3 7390 free_vpid(vmx);
ec378aee 7391 free_nested(vmx);
d462b819 7392 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7393 kfree(vmx->guest_msrs);
7394 kvm_vcpu_uninit(vcpu);
a4770347 7395 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7396}
7397
fb3f0f51 7398static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7399{
fb3f0f51 7400 int err;
c16f862d 7401 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7402 int cpu;
6aa8b732 7403
a2fa3e9f 7404 if (!vmx)
fb3f0f51
RR		 7405 return ERR_PTR(-ENOMEM);
7406
2384d2b3
SY		 7407 allocate_vpid(vmx);
7408
fb3f0f51
RR		 7409 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7410 if (err)
7411 goto free_vcpu;
965b58a5 7412
a2fa3e9f 7413 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7414 err = -ENOMEM;
fb3f0f51 7415 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7416 goto uninit_vcpu;
7417 }
965b58a5 7418
d462b819
NHE		 7419 vmx->loaded_vmcs = &vmx->vmcs01;
7420 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7421 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7422 goto free_msrs;
d462b819
NHE		 7423 if (!vmm_exclusive)
7424 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7425 loaded_vmcs_init(vmx->loaded_vmcs);
7426 if (!vmm_exclusive)
7427 kvm_cpu_vmxoff();
a2fa3e9f 7428
15ad7146
AK		 7429 cpu = get_cpu();
7430 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7431 vmx->vcpu.cpu = cpu;
8b9cf98c 7432 err = vmx_vcpu_setup(vmx);
fb3f0f51 7433 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7434 put_cpu();
fb3f0f51
RR		 7435 if (err)
7436 goto free_vmcs;
a63cb560 7437 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7438 err = alloc_apic_access_page(kvm);
7439 if (err)
5e4a0b3c 7440 goto free_vmcs;
a63cb560 7441 }
fb3f0f51 7442
b927a3ce
SY		 7443 if (enable_ept) {
7444 if (!kvm->arch.ept_identity_map_addr)
7445 kvm->arch.ept_identity_map_addr =
7446 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7447 err = -ENOMEM;
b7ebfb05
SY		 7448 if (alloc_identity_pagetable(kvm) != 0)
7449 goto free_vmcs;
93ea5388
GN		 7450 if (!init_rmode_identity_map(kvm))
7451 goto free_vmcs;
b927a3ce 7452 }
b7ebfb05 7453
a9d30f33
NHE		 7454 vmx->nested.current_vmptr = -1ull;
7455 vmx->nested.current_vmcs12 = NULL;
7456
fb3f0f51
RR		 7457 return &vmx->vcpu;
7458
7459free_vmcs:
5f3fbc34 7460 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7461free_msrs:
fb3f0f51
RR		 7462 kfree(vmx->guest_msrs);
7463uninit_vcpu:
7464 kvm_vcpu_uninit(&vmx->vcpu);
7465free_vcpu:
cdbecfc3 7466 free_vpid(vmx);
a4770347 7467 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7468 return ERR_PTR(err);
6aa8b732
AK		 7469}
7470
002c7f7c
YS		 7471static void __init vmx_check_processor_compat(void *rtn)
7472{
7473 struct vmcs_config vmcs_conf;
7474
7475 *(int *)rtn = 0;
7476 if (setup_vmcs_config(&vmcs_conf) < 0)
7477 *(int *)rtn = -EIO;
7478 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7479 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7480 smp_processor_id());
7481 *(int *)rtn = -EIO;
7482 }
7483}
7484
67253af5
SY		 7485static int get_ept_level(void)
7486{
7487 return VMX_EPT_DEFAULT_GAW + 1;
7488}
7489
4b12f0de 7490static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7491{
4b12f0de
SY		 7492 u64 ret;
7493
522c68c4
SY		 7494 /* For VT-d and EPT combination
7495 * 1. MMIO: always map as UC
7496 * 2. EPT with VT-d:
7497 * a. VT-d without snooping control feature: can't guarantee the
7498 * result, try to trust guest.
7499 * b. VT-d with snooping control feature: snooping control feature of
7500 * VT-d engine can guarantee the cache correctness. Just set it
7501 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7502 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7503 * consistent with host MTRR
7504 */
4b12f0de
SY		 7505 if (is_mmio)
7506 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7507 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7508 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7509 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7510 else
522c68c4 7511 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7512 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7513
7514 return ret;
64d4d521
SY		 7515}
7516
17cc3935 7517static int vmx_get_lpage_level(void)
344f414f 7518{
878403b7
SY		 7519 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7520 return PT_DIRECTORY_LEVEL;
7521 else
7522 /* For shadow and EPT supported 1GB page */
7523 return PT_PDPE_LEVEL;
344f414f
JR		 7524}
7525
0e851880
SY		 7526static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7527{
4e47c7a6
SY		 7528 struct kvm_cpuid_entry2 *best;
7529 struct vcpu_vmx *vmx = to_vmx(vcpu);
7530 u32 exec_control;
7531
7532 vmx->rdtscp_enabled = false;
7533 if (vmx_rdtscp_supported()) {
7534 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7535 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7536 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7537 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7538 vmx->rdtscp_enabled = true;
7539 else {
7540 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7541 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7542 exec_control);
7543 }
7544 }
7545 }
ad756a16 7546
ad756a16
MJ		 7547 /* Exposing INVPCID only when PCID is exposed */
7548 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7549 if (vmx_invpcid_supported() &&
4f977045 7550 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7551 guest_cpuid_has_pcid(vcpu)) {
29282fde 7552 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7553 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7554 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7555 exec_control);
7556 } else {
29282fde
TI		 7557 if (cpu_has_secondary_exec_ctrls()) {
7558 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7559 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7560 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7561 exec_control);
7562 }
ad756a16 7563 if (best)
4f977045 7564 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7565 }
0e851880
SY		 7566}
7567
d4330ef2
JR		 7568static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7569{
7b8050f5
NHE		 7570 if (func == 1 && nested)
7571 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7572}
7573
25d92081
YZ		 7574static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7575 struct x86_exception *fault)
7576{
7577 struct vmcs12 *vmcs12;
7578 nested_vmx_vmexit(vcpu);
7579 vmcs12 = get_vmcs12(vcpu);
7580
7581 if (fault->error_code & PFERR_RSVD_MASK)
7582 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7583 else
7584 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7585 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7586 vmcs12->guest_physical_address = fault->address;
7587}
7588
155a97a3
NHE		 7589/* Callbacks for nested_ept_init_mmu_context: */
7590
7591static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7592{
7593 /* return the page table to be shadowed - in our case, EPT12 */
7594 return get_vmcs12(vcpu)->ept_pointer;
7595}
7596
8a3c1a33 7597static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7598{
8a3c1a33 7599 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7600 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7601
7602 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7603 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7604 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7605
7606 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7607}
7608
7609static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7610{
7611 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7612}
7613
feaf0c7d
GN		 7614static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7615 struct x86_exception *fault)
7616{
7617 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7618
7619 WARN_ON(!is_guest_mode(vcpu));
7620
7621 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7622 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
7623 nested_vmx_vmexit(vcpu);
7624 else
7625 kvm_inject_page_fault(vcpu, fault);
7626}
7627
fe3ef05c
NHE		 7628/*
7629 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7630 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7631 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7632 * guest in a way that will both be appropriate to L1's requests, and our
7633 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7634 * function also has additional necessary side-effects, like setting various
7635 * vcpu->arch fields.
7636 */
7637static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7638{
7639 struct vcpu_vmx *vmx = to_vmx(vcpu);
7640 u32 exec_control;
7854cbca 7641 u32 exit_control;
fe3ef05c
NHE		 7642
7643 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7644 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7645 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7646 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7647 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7648 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7649 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7650 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7651 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7652 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7653 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7654 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7655 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7656 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7657 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7658 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7659 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7660 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7661 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7662 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7663 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7664 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7665 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7666 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7667 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7668 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7669 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7670 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7671 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7672 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7673 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7674 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7675 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7676 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7677 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7678 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7679
7680 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7681 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7682 vmcs12->vm_entry_intr_info_field);
7683 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7684 vmcs12->vm_entry_exception_error_code);
7685 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7686 vmcs12->vm_entry_instruction_len);
7687 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7688 vmcs12->guest_interruptibility_info);
fe3ef05c 7689 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7690 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7691 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7692 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7693 vmcs12->guest_pending_dbg_exceptions);
7694 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7695 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7696
7697 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7698
7699 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7700 (vmcs_config.pin_based_exec_ctrl |
7701 vmcs12->pin_based_vm_exec_control));
7702
0238ea91
JK		 7703 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7704 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7705 vmcs12->vmx_preemption_timer_value);
7706
fe3ef05c
NHE		 7707 /*
7708 * Whether page-faults are trapped is determined by a combination of
7709 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7710 * If enable_ept, L0 doesn't care about page faults and we should
7711 * set all of these to L1's desires. However, if !enable_ept, L0 does
7712 * care about (at least some) page faults, and because it is not easy
7713 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7714 * to exit on each and every L2 page fault. This is done by setting
7715 * MASK=MATCH=0 and (see below) EB.PF=1.
7716 * Note that below we don't need special code to set EB.PF beyond the
7717 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7718 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7719 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7720 *
7721 * A problem with this approach (when !enable_ept) is that L1 may be
7722 * injected with more page faults than it asked for. This could have
7723 * caused problems, but in practice existing hypervisors don't care.
7724 * To fix this, we will need to emulate the PFEC checking (on the L1
7725 * page tables), using walk_addr(), when injecting PFs to L1.
7726 */
7727 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7728 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7729 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7730 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7731
7732 if (cpu_has_secondary_exec_ctrls()) {
7733 u32 exec_control = vmx_secondary_exec_control(vmx);
7734 if (!vmx->rdtscp_enabled)
7735 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7736 /* Take the following fields only from vmcs12 */
7737 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7738 if (nested_cpu_has(vmcs12,
7739 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7740 exec_control |= vmcs12->secondary_vm_exec_control;
7741
7742 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7743 /*
7744 * Translate L1 physical address to host physical
7745 * address for vmcs02. Keep the page pinned, so this
7746 * physical address remains valid. We keep a reference
7747 * to it so we can release it later.
7748 */
7749 if (vmx->nested.apic_access_page) /* shouldn't happen */
7750 nested_release_page(vmx->nested.apic_access_page);
7751 vmx->nested.apic_access_page =
7752 nested_get_page(vcpu, vmcs12->apic_access_addr);
7753 /*
7754 * If translation failed, no matter: This feature asks
7755 * to exit when accessing the given address, and if it
7756 * can never be accessed, this feature won't do
7757 * anything anyway.
7758 */
7759 if (!vmx->nested.apic_access_page)
7760 exec_control &=
7761 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7762 else
7763 vmcs_write64(APIC_ACCESS_ADDR,
7764 page_to_phys(vmx->nested.apic_access_page));
7765 }
7766
7767 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7768 }
7769
7770
7771 /*
7772 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7773 * Some constant fields are set here by vmx_set_constant_host_state().
7774 * Other fields are different per CPU, and will be set later when
7775 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7776 */
a547c6db 7777 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7778
7779 /*
7780 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7781 * entry, but only if the current (host) sp changed from the value
7782 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7783 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7784 * here we just force the write to happen on entry.
7785 */
7786 vmx->host_rsp = 0;
7787
7788 exec_control = vmx_exec_control(vmx); /* L0's desires */
7789 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7790 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7791 exec_control &= ~CPU_BASED_TPR_SHADOW;
7792 exec_control |= vmcs12->cpu_based_vm_exec_control;
7793 /*
7794 * Merging of IO and MSR bitmaps not currently supported.
7795 * Rather, exit every time.
7796 */
7797 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7798 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7799 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7800
7801 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7802
7803 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7804 * bitwise-or of what L1 wants to trap for L2, and what we want to
7805 * trap. Note that CR0.TS also needs updating - we do this later.
7806 */
7807 update_exception_bitmap(vcpu);
7808 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7809 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7810
8049d651
NHE		 7811 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7812 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7813 * bits are further modified by vmx_set_efer() below.
7814 */
7854cbca
ACL		 7815 exit_control = vmcs_config.vmexit_ctrl;
7816 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7817 exit_control |= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER;
2961e876 7818 vm_exit_controls_init(vmx, exit_control);
8049d651
NHE		 7819
7820 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7821 * emulated by vmx_set_efer(), below.
7822 */
2961e876 7823 vm_entry_controls_init(vmx,
8049d651
NHE		 7824 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7825 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7826 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7827
44811c02 7828 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7829 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7830 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7831 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7832 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7833
7834
7835 set_cr4_guest_host_mask(vmx);
7836
27fc51b2
NHE		 7837 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7838 vmcs_write64(TSC_OFFSET,
7839 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7840 else
7841 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7842
7843 if (enable_vpid) {
7844 /*
7845 * Trivially support vpid by letting L2s share their parent
7846 * L1's vpid. TODO: move to a more elaborate solution, giving
7847 * each L2 its own vpid and exposing the vpid feature to L1.
7848 */
7849 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7850 vmx_flush_tlb(vcpu);
7851 }
7852
155a97a3
NHE		 7853 if (nested_cpu_has_ept(vmcs12)) {
7854 kvm_mmu_unload(vcpu);
7855 nested_ept_init_mmu_context(vcpu);
7856 }
7857
fe3ef05c
NHE		 7858 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7859 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7860 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7861 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7862 else
7863 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7864 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7865 vmx_set_efer(vcpu, vcpu->arch.efer);
7866
7867 /*
7868 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7869 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7870 * The CR0_READ_SHADOW is what L2 should have expected to read given
7871 * the specifications by L1; It's not enough to take
7872 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7873 * have more bits than L1 expected.
7874 */
7875 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7876 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7877
7878 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7879 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7880
7881 /* shadow page tables on either EPT or shadow page tables */
7882 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7883 kvm_mmu_reset_context(vcpu);
7884
feaf0c7d
GN		 7885 if (!enable_ept)
7886 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
7887
3633cfc3
NHE		 7888 /*
7889 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7890 */
7891 if (enable_ept) {
7892 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7893 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7894 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7895 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7896 }
7897
fe3ef05c
NHE		 7898 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7899 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7900}
7901
cd232ad0
NHE		 7902/*
7903 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7904 * for running an L2 nested guest.
7905 */
7906static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7907{
7908 struct vmcs12 *vmcs12;
7909 struct vcpu_vmx *vmx = to_vmx(vcpu);
7910 int cpu;
7911 struct loaded_vmcs *vmcs02;
384bb783 7912 bool ia32e;
cd232ad0
NHE		 7913
7914 if (!nested_vmx_check_permission(vcpu) ||
7915 !nested_vmx_check_vmcs12(vcpu))
7916 return 1;
7917
7918 skip_emulated_instruction(vcpu);
7919 vmcs12 = get_vmcs12(vcpu);
7920
012f83cb
AG		 7921 if (enable_shadow_vmcs)
7922 copy_shadow_to_vmcs12(vmx);
7923
7c177938
NHE		 7924 /*
7925 * The nested entry process starts with enforcing various prerequisites
7926 * on vmcs12 as required by the Intel SDM, and act appropriately when
7927 * they fail: As the SDM explains, some conditions should cause the
7928 * instruction to fail, while others will cause the instruction to seem
7929 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7930 * To speed up the normal (success) code path, we should avoid checking
7931 * for misconfigurations which will anyway be caught by the processor
7932 * when using the merged vmcs02.
7933 */
7934 if (vmcs12->launch_state == launch) {
7935 nested_vmx_failValid(vcpu,
7936 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7937 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7938 return 1;
7939 }
7940
26539bd0
PB		 7941 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7942 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7943 return 1;
7944 }
7945
7c177938
NHE		 7946 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7947 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7948 /*TODO: Also verify bits beyond physical address width are 0*/
7949 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7950 return 1;
7951 }
7952
7953 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7954 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7955 /*TODO: Also verify bits beyond physical address width are 0*/
7956 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7957 return 1;
7958 }
7959
7960 if (vmcs12->vm_entry_msr_load_count > 0 ||
7961 vmcs12->vm_exit_msr_load_count > 0 ||
7962 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7963 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7964 __func__);
7c177938
NHE		 7965 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7966 return 1;
7967 }
7968
7969 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7970 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7971 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7972 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7973 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7974 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7975 !vmx_control_verify(vmcs12->vm_exit_controls,
7976 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7977 !vmx_control_verify(vmcs12->vm_entry_controls,
7978 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7979 {
7980 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7981 return 1;
7982 }
7983
7984 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7985 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7986 nested_vmx_failValid(vcpu,
7987 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7988 return 1;
7989 }
7990
92fbc7b1 7991 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 7992 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7993 nested_vmx_entry_failure(vcpu, vmcs12,
7994 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7995 return 1;
7996 }
7997 if (vmcs12->vmcs_link_pointer != -1ull) {
7998 nested_vmx_entry_failure(vcpu, vmcs12,
7999 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8000 return 1;
8001 }
8002
384bb783 8003 /*
cb0c8cda 8004 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8005 * are performed on the field for the IA32_EFER MSR:
8006 * - Bits reserved in the IA32_EFER MSR must be 0.
8007 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8008 * the IA-32e mode guest VM-exit control. It must also be identical
8009 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8010 * CR0.PG) is 1.
8011 */
8012 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8013 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8014 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8015 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8016 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8017 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8018 nested_vmx_entry_failure(vcpu, vmcs12,
8019 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8020 return 1;
8021 }
8022 }
8023
8024 /*
8025 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8026 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8027 * the values of the LMA and LME bits in the field must each be that of
8028 * the host address-space size VM-exit control.
8029 */
8030 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8031 ia32e = (vmcs12->vm_exit_controls &
8032 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8033 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8034 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8035 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8036 nested_vmx_entry_failure(vcpu, vmcs12,
8037 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8038 return 1;
8039 }
8040 }
8041
7c177938
NHE		 8042 /*
8043 * We're finally done with prerequisite checking, and can start with
8044 * the nested entry.
8045 */
8046
cd232ad0
NHE		 8047 vmcs02 = nested_get_current_vmcs02(vmx);
8048 if (!vmcs02)
8049 return -ENOMEM;
8050
8051 enter_guest_mode(vcpu);
8052
e0b890d3
GN		 8053 vmx->nested.nested_run_pending = 1;
8054
cd232ad0
NHE		 8055 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8056
8057 cpu = get_cpu();
8058 vmx->loaded_vmcs = vmcs02;
8059 vmx_vcpu_put(vcpu);
8060 vmx_vcpu_load(vcpu, cpu);
8061 vcpu->cpu = cpu;
8062 put_cpu();
8063
36c3cc42
JK		 8064 vmx_segment_cache_clear(vmx);
8065
cd232ad0
NHE		 8066 vmcs12->launch_state = 1;
8067
8068 prepare_vmcs02(vcpu, vmcs12);
8069
8070 /*
8071 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8072 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8073 * returned as far as L1 is concerned. It will only return (and set
8074 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8075 */
8076 return 1;
8077}
8078
4704d0be
NHE		 8079/*
8080 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8081 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8082 * This function returns the new value we should put in vmcs12.guest_cr0.
8083 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8084 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8085 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8086 * didn't trap the bit, because if L1 did, so would L0).
8087 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8088 * been modified by L2, and L1 knows it. So just leave the old value of
8089 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8090 * isn't relevant, because if L0 traps this bit it can set it to anything.
8091 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8092 * changed these bits, and therefore they need to be updated, but L0
8093 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8094 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8095 */
8096static inline unsigned long
8097vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8098{
8099 return
8100 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8101 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8102 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8103 vcpu->arch.cr0_guest_owned_bits));
8104}
8105
8106static inline unsigned long
8107vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8108{
8109 return
8110 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8111 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8112 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8113 vcpu->arch.cr4_guest_owned_bits));
8114}
8115
5f3d5799
JK		 8116static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8117 struct vmcs12 *vmcs12)
8118{
8119 u32 idt_vectoring;
8120 unsigned int nr;
8121
851eb667 8122 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8123 nr = vcpu->arch.exception.nr;
8124 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8125
8126 if (kvm_exception_is_soft(nr)) {
8127 vmcs12->vm_exit_instruction_len =
8128 vcpu->arch.event_exit_inst_len;
8129 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8130 } else
8131 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8132
8133 if (vcpu->arch.exception.has_error_code) {
8134 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8135 vmcs12->idt_vectoring_error_code =
8136 vcpu->arch.exception.error_code;
8137 }
8138
8139 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8140 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8141 vmcs12->idt_vectoring_info_field =
8142 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8143 } else if (vcpu->arch.interrupt.pending) {
8144 nr = vcpu->arch.interrupt.nr;
8145 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8146
8147 if (vcpu->arch.interrupt.soft) {
8148 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8149 vmcs12->vm_entry_instruction_len =
8150 vcpu->arch.event_exit_inst_len;
8151 } else
8152 idt_vectoring |= INTR_TYPE_EXT_INTR;
8153
8154 vmcs12->idt_vectoring_info_field = idt_vectoring;
8155 }
8156}
8157
4704d0be
NHE		 8158/*
8159 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8160 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8161 * and this function updates it to reflect the changes to the guest state while
8162 * L2 was running (and perhaps made some exits which were handled directly by L0
8163 * without going back to L1), and to reflect the exit reason.
8164 * Note that we do not have to copy here all VMCS fields, just those that
8165 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8166 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8167 * which already writes to vmcs12 directly.
8168 */
733568f9 8169static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8170{
8171 /* update guest state fields: */
8172 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8173 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8174
8175 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8176 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8177 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8178 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8179
8180 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8181 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8182 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8183 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8184 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8185 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8186 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8187 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8188 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8189 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8190 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8191 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8192 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8193 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8194 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8195 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8196 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8197 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8198 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8199 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8200 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8201 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8202 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8203 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8204 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8205 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8206 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8207 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8208 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8209 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8210 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8211 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8212 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8213 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8214 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8215 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8216
4704d0be
NHE		 8217 vmcs12->guest_interruptibility_info =
8218 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8219 vmcs12->guest_pending_dbg_exceptions =
8220 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8221
7854cbca
ACL		 8222 if ((vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER) &&
8223 (vmcs12->vm_exit_controls & VM_EXIT_SAVE_VMX_PREEMPTION_TIMER))
8224 vmcs12->vmx_preemption_timer_value =
8225 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE);
8226
3633cfc3
NHE		 8227 /*
8228 * In some cases (usually, nested EPT), L2 is allowed to change its
8229 * own CR3 without exiting. If it has changed it, we must keep it.
8230 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8231 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8232 *
8233 * Additionally, restore L2's PDPTR to vmcs12.
8234 */
8235 if (enable_ept) {
8236 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8237 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8238 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8239 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8240 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8241 }
8242
c18911a2
JK		 8243 vmcs12->vm_entry_controls =
8244 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8245 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8246
4704d0be
NHE		 8247 /* TODO: These cannot have changed unless we have MSR bitmaps and
8248 * the relevant bit asks not to trap the change */
8249 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8250 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8251 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8252 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8253 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8254 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8255 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8256 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8257
8258 /* update exit information fields: */
8259
957c897e 8260 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8261 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8262
8263 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8264 if ((vmcs12->vm_exit_intr_info &
8265 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8266 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8267 vmcs12->vm_exit_intr_error_code =
8268 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8269 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8270 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8271 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8272
5f3d5799
JK		 8273 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8274 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8275 * instead of reading the real value. */
4704d0be 8276 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8277
8278 /*
8279 * Transfer the event that L0 or L1 may wanted to inject into
8280 * L2 to IDT_VECTORING_INFO_FIELD.
8281 */
8282 vmcs12_save_pending_event(vcpu, vmcs12);
8283 }
8284
8285 /*
8286 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8287 * preserved above and would only end up incorrectly in L1.
8288 */
8289 vcpu->arch.nmi_injected = false;
8290 kvm_clear_exception_queue(vcpu);
8291 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8292}
8293
8294/*
8295 * A part of what we need to when the nested L2 guest exits and we want to
8296 * run its L1 parent, is to reset L1's guest state to the host state specified
8297 * in vmcs12.
8298 * This function is to be called not only on normal nested exit, but also on
8299 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8300 * Failures During or After Loading Guest State").
8301 * This function should be called when the active VMCS is L1's (vmcs01).
8302 */
733568f9
JK		 8303static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8304 struct vmcs12 *vmcs12)
4704d0be 8305{
21feb4eb
ACL		 8306 struct kvm_segment seg;
8307
4704d0be
NHE		 8308 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8309 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8310 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8311 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8312 else
8313 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8314 vmx_set_efer(vcpu, vcpu->arch.efer);
8315
8316 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8317 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8318 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8319 /*
8320 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8321 * actually changed, because it depends on the current state of
8322 * fpu_active (which may have changed).
8323 * Note that vmx_set_cr0 refers to efer set above.
8324 */
9e3e4dbf 8325 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8326 /*
8327 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8328 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8329 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8330 */
8331 update_exception_bitmap(vcpu);
8332 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8333 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8334
8335 /*
8336 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8337 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8338 */
8339 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8340 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8341
155a97a3
NHE		 8342 if (nested_cpu_has_ept(vmcs12))
8343 nested_ept_uninit_mmu_context(vcpu);
8344
4704d0be
NHE		 8345 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8346 kvm_mmu_reset_context(vcpu);
8347
feaf0c7d
GN		 8348 if (!enable_ept)
8349 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8350
4704d0be
NHE		 8351 if (enable_vpid) {
8352 /*
8353 * Trivially support vpid by letting L2s share their parent
8354 * L1's vpid. TODO: move to a more elaborate solution, giving
8355 * each L2 its own vpid and exposing the vpid feature to L1.
8356 */
8357 vmx_flush_tlb(vcpu);
8358 }
8359
8360
8361 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8362 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8363 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8364 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8365 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8366
44811c02 8367 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8368 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8369 vcpu->arch.pat = vmcs12->host_ia32_pat;
8370 }
4704d0be
NHE		 8371 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8372 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8373 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8374
21feb4eb
ACL		 8375 /* Set L1 segment info according to Intel SDM
8376 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8377 seg = (struct kvm_segment) {
8378 .base = 0,
8379 .limit = 0xFFFFFFFF,
8380 .selector = vmcs12->host_cs_selector,
8381 .type = 11,
8382 .present = 1,
8383 .s = 1,
8384 .g = 1
8385 };
8386 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8387 seg.l = 1;
8388 else
8389 seg.db = 1;
8390 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8391 seg = (struct kvm_segment) {
8392 .base = 0,
8393 .limit = 0xFFFFFFFF,
8394 .type = 3,
8395 .present = 1,
8396 .s = 1,
8397 .db = 1,
8398 .g = 1
8399 };
8400 seg.selector = vmcs12->host_ds_selector;
8401 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8402 seg.selector = vmcs12->host_es_selector;
8403 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8404 seg.selector = vmcs12->host_ss_selector;
8405 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8406 seg.selector = vmcs12->host_fs_selector;
8407 seg.base = vmcs12->host_fs_base;
8408 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8409 seg.selector = vmcs12->host_gs_selector;
8410 seg.base = vmcs12->host_gs_base;
8411 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8412 seg = (struct kvm_segment) {
205befd9 8413 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8414 .limit = 0x67,
8415 .selector = vmcs12->host_tr_selector,
8416 .type = 11,
8417 .present = 1
8418 };
8419 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8420
503cd0c5
JK		 8421 kvm_set_dr(vcpu, 7, 0x400);
8422 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8423}
8424
8425/*
8426 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8427 * and modify vmcs12 to make it see what it would expect to see there if
8428 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8429 */
8430static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8431{
8432 struct vcpu_vmx *vmx = to_vmx(vcpu);
8433 int cpu;
8434 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8435
5f3d5799
JK		 8436 /* trying to cancel vmlaunch/vmresume is a bug */
8437 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8438
4704d0be
NHE		 8439 leave_guest_mode(vcpu);
8440 prepare_vmcs12(vcpu, vmcs12);
8441
8442 cpu = get_cpu();
8443 vmx->loaded_vmcs = &vmx->vmcs01;
8444 vmx_vcpu_put(vcpu);
8445 vmx_vcpu_load(vcpu, cpu);
8446 vcpu->cpu = cpu;
8447 put_cpu();
8448
2961e876
GN		 8449 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8450 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8451 vmx_segment_cache_clear(vmx);
8452
4704d0be
NHE		 8453 /* if no vmcs02 cache requested, remove the one we used */
8454 if (VMCS02_POOL_SIZE == 0)
8455 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8456
8457 load_vmcs12_host_state(vcpu, vmcs12);
8458
27fc51b2 8459 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8460 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8461
8462 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8463 vmx->host_rsp = 0;
8464
8465 /* Unpin physical memory we referred to in vmcs02 */
8466 if (vmx->nested.apic_access_page) {
8467 nested_release_page(vmx->nested.apic_access_page);
8468 vmx->nested.apic_access_page = 0;
8469 }
8470
8471 /*
8472 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8473 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8474 * success or failure flag accordingly.
8475 */
8476 if (unlikely(vmx->fail)) {
8477 vmx->fail = 0;
8478 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8479 } else
8480 nested_vmx_succeed(vcpu);
012f83cb
AG		 8481 if (enable_shadow_vmcs)
8482 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8483}
8484
7c177938
NHE		 8485/*
8486 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8487 * 23.7 "VM-entry failures during or after loading guest state" (this also
8488 * lists the acceptable exit-reason and exit-qualification parameters).
8489 * It should only be called before L2 actually succeeded to run, and when
8490 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8491 */
8492static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8493 struct vmcs12 *vmcs12,
8494 u32 reason, unsigned long qualification)
8495{
8496 load_vmcs12_host_state(vcpu, vmcs12);
8497 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8498 vmcs12->exit_qualification = qualification;
8499 nested_vmx_succeed(vcpu);
012f83cb
AG		 8500 if (enable_shadow_vmcs)
8501 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8502}
8503
8a76d7f2
JR		 8504static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8505 struct x86_instruction_info *info,
8506 enum x86_intercept_stage stage)
8507{
8508 return X86EMUL_CONTINUE;
8509}
8510
cbdd1bea 8511static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8512 .cpu_has_kvm_support = cpu_has_kvm_support,
8513 .disabled_by_bios = vmx_disabled_by_bios,
8514 .hardware_setup = hardware_setup,
8515 .hardware_unsetup = hardware_unsetup,
002c7f7c 8516 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8517 .hardware_enable = hardware_enable,
8518 .hardware_disable = hardware_disable,
04547156 8519 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8520
8521 .vcpu_create = vmx_create_vcpu,
8522 .vcpu_free = vmx_free_vcpu,
04d2cc77 8523 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8524
04d2cc77 8525 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8526 .vcpu_load = vmx_vcpu_load,
8527 .vcpu_put = vmx_vcpu_put,
8528
c8639010 8529 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8530 .get_msr = vmx_get_msr,
8531 .set_msr = vmx_set_msr,
8532 .get_segment_base = vmx_get_segment_base,
8533 .get_segment = vmx_get_segment,
8534 .set_segment = vmx_set_segment,
2e4d2653 8535 .get_cpl = vmx_get_cpl,
6aa8b732 8536 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8537 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8538 .decache_cr3 = vmx_decache_cr3,
25c4c276 8539 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8540 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8541 .set_cr3 = vmx_set_cr3,
8542 .set_cr4 = vmx_set_cr4,
6aa8b732 8543 .set_efer = vmx_set_efer,
6aa8b732
AK		 8544 .get_idt = vmx_get_idt,
8545 .set_idt = vmx_set_idt,
8546 .get_gdt = vmx_get_gdt,
8547 .set_gdt = vmx_set_gdt,
020df079 8548 .set_dr7 = vmx_set_dr7,
5fdbf976 8549 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8550 .get_rflags = vmx_get_rflags,
8551 .set_rflags = vmx_set_rflags,
ebcbab4c 8552 .fpu_activate = vmx_fpu_activate,
02daab21 8553 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8554
8555 .tlb_flush = vmx_flush_tlb,
6aa8b732 8556
6aa8b732 8557 .run = vmx_vcpu_run,
6062d012 8558 .handle_exit = vmx_handle_exit,
6aa8b732 8559 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8560 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8561 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8562 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8563 .set_irq = vmx_inject_irq,
95ba8273 8564 .set_nmi = vmx_inject_nmi,
298101da 8565 .queue_exception = vmx_queue_exception,
b463a6f7 8566 .cancel_injection = vmx_cancel_injection,
78646121 8567 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8568 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8569 .get_nmi_mask = vmx_get_nmi_mask,
8570 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8571 .enable_nmi_window = enable_nmi_window,
8572 .enable_irq_window = enable_irq_window,
8573 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8574 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8575 .vm_has_apicv = vmx_vm_has_apicv,
8576 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8577 .hwapic_irr_update = vmx_hwapic_irr_update,
8578 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8579 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8580 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8581
cbc94022 8582 .set_tss_addr = vmx_set_tss_addr,
67253af5 8583 .get_tdp_level = get_ept_level,
4b12f0de 8584 .get_mt_mask = vmx_get_mt_mask,
229456fc 8585
586f9607 8586 .get_exit_info = vmx_get_exit_info,
586f9607 8587
17cc3935 8588 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8589
8590 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8591
8592 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8593 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8594
8595 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8596
8597 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8598
4051b188 8599 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8600 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8601 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8602 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8603 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8604 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8605
8606 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8607
8608 .check_intercept = vmx_check_intercept,
a547c6db 8609 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8610};
8611
8612static int __init vmx_init(void)
8613{
8d14695f 8614 int r, i, msr;
26bb0981
AK		 8615
8616 rdmsrl_safe(MSR_EFER, &host_efer);
8617
8618 for (i = 0; i < NR_VMX_MSR; ++i)
8619 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8620
3e7c73e9 8621 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8622 if (!vmx_io_bitmap_a)
8623 return -ENOMEM;
8624
2106a548
GC		 8625 r = -ENOMEM;
8626
3e7c73e9 8627 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8628 if (!vmx_io_bitmap_b)
fdef3ad1 8629 goto out;
fdef3ad1 8630
5897297b 8631 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8632 if (!vmx_msr_bitmap_legacy)
25c5f225 8633 goto out1;
2106a548 8634
8d14695f
YZ		 8635 vmx_msr_bitmap_legacy_x2apic =
8636 (unsigned long *)__get_free_page(GFP_KERNEL);
8637 if (!vmx_msr_bitmap_legacy_x2apic)
8638 goto out2;
25c5f225 8639
5897297b 8640 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8641 if (!vmx_msr_bitmap_longmode)
8d14695f 8642 goto out3;
2106a548 8643
8d14695f
YZ		 8644 vmx_msr_bitmap_longmode_x2apic =
8645 (unsigned long *)__get_free_page(GFP_KERNEL);
8646 if (!vmx_msr_bitmap_longmode_x2apic)
8647 goto out4;
4607c2d7
AG		 8648 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8649 if (!vmx_vmread_bitmap)
8650 goto out5;
8651
8652 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8653 if (!vmx_vmwrite_bitmap)
8654 goto out6;
8655
8656 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8657 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8658 /* shadowed read/write fields */
8659 for (i = 0; i < max_shadow_read_write_fields; i++) {
8660 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8661 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8662 }
8663 /* shadowed read only fields */
8664 for (i = 0; i < max_shadow_read_only_fields; i++)
8665 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8666
fdef3ad1
HQ		 8667 /*
8668 * Allow direct access to the PC debug port (it is often used for I/O
8669 * delays, but the vmexits simply slow things down).
8670 */
3e7c73e9
AK		 8671 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8672 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8673
3e7c73e9 8674 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8675
5897297b
AK		 8676 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8677 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8678
2384d2b3
SY		 8679 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8680
0ee75bea
AK		 8681 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8682 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8683 if (r)
4607c2d7 8684 goto out7;
25c5f225 8685
8f536b76
ZY		 8686#ifdef CONFIG_KEXEC
8687 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8688 crash_vmclear_local_loaded_vmcss);
8689#endif
8690
5897297b
AK		 8691 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8692 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8693 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8694 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8695 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8696 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8697 memcpy(vmx_msr_bitmap_legacy_x2apic,
8698 vmx_msr_bitmap_legacy, PAGE_SIZE);
8699 memcpy(vmx_msr_bitmap_longmode_x2apic,
8700 vmx_msr_bitmap_longmode, PAGE_SIZE);
8701
01e439be 8702 if (enable_apicv) {
8d14695f
YZ		 8703 for (msr = 0x800; msr <= 0x8ff; msr++)
8704 vmx_disable_intercept_msr_read_x2apic(msr);
8705
8706 /* According SDM, in x2apic mode, the whole id reg is used.
8707 * But in KVM, it only use the highest eight bits. Need to
8708 * intercept it */
8709 vmx_enable_intercept_msr_read_x2apic(0x802);
8710 /* TMCCT */
8711 vmx_enable_intercept_msr_read_x2apic(0x839);
8712 /* TPR */
8713 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8714 /* EOI */
8715 vmx_disable_intercept_msr_write_x2apic(0x80b);
8716 /* SELF-IPI */
8717 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8718 }
fdef3ad1 8719
089d034e 8720 if (enable_ept) {
3f6d8c8a
XH		 8721 kvm_mmu_set_mask_ptes(0ull,
8722 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8723 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8724 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8725 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8726 kvm_enable_tdp();
8727 } else
8728 kvm_disable_tdp();
1439442c 8729
fdef3ad1
HQ		 8730 return 0;
8731
4607c2d7
AG		 8732out7:
8733 free_page((unsigned long)vmx_vmwrite_bitmap);
8734out6:
8735 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8736out5:
8737 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8738out4:
5897297b 8739 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8740out3:
8741 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8742out2:
5897297b 8743 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8744out1:
3e7c73e9 8745 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8746out:
3e7c73e9 8747 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8748 return r;
6aa8b732
AK		 8749}
8750
8751static void __exit vmx_exit(void)
8752{
8d14695f
YZ		 8753 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8754 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8755 free_page((unsigned long)vmx_msr_bitmap_legacy);
8756 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8757 free_page((unsigned long)vmx_io_bitmap_b);
8758 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8759 free_page((unsigned long)vmx_vmwrite_bitmap);
8760 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8761
8f536b76
ZY		 8762#ifdef CONFIG_KEXEC
8763 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8764 synchronize_rcu();
8765#endif
8766
cb498ea2 8767 kvm_exit();
6aa8b732
AK		 8768}
8769
8770module_init(vmx_init)
8771module_exit(vmx_exit)
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