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nVMX: Keep arch.pat in sync on L1-L2 switches
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
b3897a49 376 u64 msr_ia32_feature_control;
ec378aee
NHE		 377};
378
01e439be
YZ		 379#define POSTED_INTR_ON 0
380/* Posted-Interrupt Descriptor */
381struct pi_desc {
382 u32 pir[8]; /* Posted interrupt requested */
383 u32 control; /* bit 0 of control is outstanding notification bit */
384 u32 rsvd[7];
385} __aligned(64);
386
a20ed54d
YZ		 387static bool pi_test_and_set_on(struct pi_desc *pi_desc)
388{
389 return test_and_set_bit(POSTED_INTR_ON,
390 (unsigned long *)&pi_desc->control);
391}
392
393static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
394{
395 return test_and_clear_bit(POSTED_INTR_ON,
396 (unsigned long *)&pi_desc->control);
397}
398
399static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
402}
403
a2fa3e9f 404struct vcpu_vmx {
fb3f0f51 405 struct kvm_vcpu vcpu;
313dbd49 406 unsigned long host_rsp;
29bd8a78 407 u8 fail;
69c73028 408 u8 cpl;
9d58b931 409 bool nmi_known_unmasked;
51aa01d1 410 u32 exit_intr_info;
1155f76a 411 u32 idt_vectoring_info;
6de12732 412 ulong rflags;
26bb0981 413 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 414 int nmsrs;
415 int save_nmsrs;
a547c6db 416 unsigned long host_idt_base;
a2fa3e9f 417#ifdef CONFIG_X86_64
44ea2b17
AK		 418 u64 msr_host_kernel_gs_base;
419 u64 msr_guest_kernel_gs_base;
a2fa3e9f 420#endif
d462b819
NHE		 421 /*
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
425 */
426 struct loaded_vmcs vmcs01;
427 struct loaded_vmcs *loaded_vmcs;
428 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 429 struct msr_autoload {
430 unsigned nr;
431 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
432 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
433 } msr_autoload;
a2fa3e9f
GH		 434 struct {
435 int loaded;
436 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 437#ifdef CONFIG_X86_64
438 u16 ds_sel, es_sel;
439#endif
152d3f2f
LV		 440 int gs_ldt_reload_needed;
441 int fs_reload_needed;
d77c26fc 442 } host_state;
9c8cba37 443 struct {
7ffd92c5 444 int vm86_active;
78ac8b47 445 ulong save_rflags;
f5f7b2fe
AK		 446 struct kvm_segment segs[8];
447 } rmode;
448 struct {
449 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 450 struct kvm_save_segment {
451 u16 selector;
452 unsigned long base;
453 u32 limit;
454 u32 ar;
f5f7b2fe 455 } seg[8];
2fb92db1 456 } segment_cache;
2384d2b3 457 int vpid;
04fa4d32 458 bool emulation_required;
3b86cd99
JK		 459
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked;
462 ktime_t entry_time;
463 s64 vnmi_blocked_time;
a0861c02 464 u32 exit_reason;
4e47c7a6
SY		 465
466 bool rdtscp_enabled;
ec378aee 467
01e439be
YZ		 468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc;
470
ec378aee
NHE		 471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested;
a2fa3e9f
GH		 473};
474
2fb92db1
AK		 475enum segment_cache_field {
476 SEG_FIELD_SEL = 0,
477 SEG_FIELD_BASE = 1,
478 SEG_FIELD_LIMIT = 2,
479 SEG_FIELD_AR = 3,
480
481 SEG_FIELD_NR = 4
482};
483
a2fa3e9f
GH		 484static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
485{
fb3f0f51 486 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 487}
488
22bd0358
NHE		 489#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
493
4607c2d7
AG		 494
495static const unsigned long shadow_read_only_fields[] = {
496 /*
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
507 */
508 VM_EXIT_REASON,
509 VM_EXIT_INTR_INFO,
510 VM_EXIT_INSTRUCTION_LEN,
511 IDT_VECTORING_INFO_FIELD,
512 IDT_VECTORING_ERROR_CODE,
513 VM_EXIT_INTR_ERROR_CODE,
514 EXIT_QUALIFICATION,
515 GUEST_LINEAR_ADDRESS,
516 GUEST_PHYSICAL_ADDRESS
517};
518static const int max_shadow_read_only_fields =
519 ARRAY_SIZE(shadow_read_only_fields);
520
521static const unsigned long shadow_read_write_fields[] = {
522 GUEST_RIP,
523 GUEST_RSP,
524 GUEST_CR0,
525 GUEST_CR3,
526 GUEST_CR4,
527 GUEST_INTERRUPTIBILITY_INFO,
528 GUEST_RFLAGS,
529 GUEST_CS_SELECTOR,
530 GUEST_CS_AR_BYTES,
531 GUEST_CS_LIMIT,
532 GUEST_CS_BASE,
533 GUEST_ES_BASE,
534 CR0_GUEST_HOST_MASK,
535 CR0_READ_SHADOW,
536 CR4_READ_SHADOW,
537 TSC_OFFSET,
538 EXCEPTION_BITMAP,
539 CPU_BASED_VM_EXEC_CONTROL,
540 VM_ENTRY_EXCEPTION_ERROR_CODE,
541 VM_ENTRY_INTR_INFO_FIELD,
542 VM_ENTRY_INSTRUCTION_LEN,
543 VM_ENTRY_EXCEPTION_ERROR_CODE,
544 HOST_FS_BASE,
545 HOST_GS_BASE,
546 HOST_FS_SELECTOR,
547 HOST_GS_SELECTOR
548};
549static const int max_shadow_read_write_fields =
550 ARRAY_SIZE(shadow_read_write_fields);
551
772e0318 552static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 553 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
554 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
555 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
556 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
557 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
558 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
559 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
560 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
561 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
562 FIELD(HOST_ES_SELECTOR, host_es_selector),
563 FIELD(HOST_CS_SELECTOR, host_cs_selector),
564 FIELD(HOST_SS_SELECTOR, host_ss_selector),
565 FIELD(HOST_DS_SELECTOR, host_ds_selector),
566 FIELD(HOST_FS_SELECTOR, host_fs_selector),
567 FIELD(HOST_GS_SELECTOR, host_gs_selector),
568 FIELD(HOST_TR_SELECTOR, host_tr_selector),
569 FIELD64(IO_BITMAP_A, io_bitmap_a),
570 FIELD64(IO_BITMAP_B, io_bitmap_b),
571 FIELD64(MSR_BITMAP, msr_bitmap),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
575 FIELD64(TSC_OFFSET, tsc_offset),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
577 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
578 FIELD64(EPT_POINTER, ept_pointer),
579 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
580 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
581 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
582 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
583 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
585 FIELD64(GUEST_PDPTR0, guest_pdptr0),
586 FIELD64(GUEST_PDPTR1, guest_pdptr1),
587 FIELD64(GUEST_PDPTR2, guest_pdptr2),
588 FIELD64(GUEST_PDPTR3, guest_pdptr3),
589 FIELD64(HOST_IA32_PAT, host_ia32_pat),
590 FIELD64(HOST_IA32_EFER, host_ia32_efer),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
594 FIELD(EXCEPTION_BITMAP, exception_bitmap),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
597 FIELD(CR3_TARGET_COUNT, cr3_target_count),
598 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
599 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
601 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
606 FIELD(TPR_THRESHOLD, tpr_threshold),
607 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
608 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
609 FIELD(VM_EXIT_REASON, vm_exit_reason),
610 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
611 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
612 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
613 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
614 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
615 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
616 FIELD(GUEST_ES_LIMIT, guest_es_limit),
617 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
618 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
619 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
620 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
621 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
622 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
623 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
624 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
625 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
626 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
627 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
628 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
629 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
630 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
631 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
632 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
633 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
635 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
636 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
637 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 638 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 639 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
640 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
641 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
642 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
643 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
644 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
645 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
646 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
647 FIELD(EXIT_QUALIFICATION, exit_qualification),
648 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
649 FIELD(GUEST_CR0, guest_cr0),
650 FIELD(GUEST_CR3, guest_cr3),
651 FIELD(GUEST_CR4, guest_cr4),
652 FIELD(GUEST_ES_BASE, guest_es_base),
653 FIELD(GUEST_CS_BASE, guest_cs_base),
654 FIELD(GUEST_SS_BASE, guest_ss_base),
655 FIELD(GUEST_DS_BASE, guest_ds_base),
656 FIELD(GUEST_FS_BASE, guest_fs_base),
657 FIELD(GUEST_GS_BASE, guest_gs_base),
658 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
659 FIELD(GUEST_TR_BASE, guest_tr_base),
660 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
661 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
662 FIELD(GUEST_DR7, guest_dr7),
663 FIELD(GUEST_RSP, guest_rsp),
664 FIELD(GUEST_RIP, guest_rip),
665 FIELD(GUEST_RFLAGS, guest_rflags),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
667 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
668 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
669 FIELD(HOST_CR0, host_cr0),
670 FIELD(HOST_CR3, host_cr3),
671 FIELD(HOST_CR4, host_cr4),
672 FIELD(HOST_FS_BASE, host_fs_base),
673 FIELD(HOST_GS_BASE, host_gs_base),
674 FIELD(HOST_TR_BASE, host_tr_base),
675 FIELD(HOST_GDTR_BASE, host_gdtr_base),
676 FIELD(HOST_IDTR_BASE, host_idtr_base),
677 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
678 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
679 FIELD(HOST_RSP, host_rsp),
680 FIELD(HOST_RIP, host_rip),
681};
682static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
683
684static inline short vmcs_field_to_offset(unsigned long field)
685{
686 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
687 return -1;
688 return vmcs_field_to_offset_table[field];
689}
690
a9d30f33
NHE		 691static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
692{
693 return to_vmx(vcpu)->nested.current_vmcs12;
694}
695
696static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
697{
698 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 699 if (is_error_page(page))
a9d30f33 700 return NULL;
32cad84f 701
a9d30f33
NHE		 702 return page;
703}
704
705static void nested_release_page(struct page *page)
706{
707 kvm_release_page_dirty(page);
708}
709
710static void nested_release_page_clean(struct page *page)
711{
712 kvm_release_page_clean(page);
713}
714
bfd0a56b 715static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 716static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 717static void kvm_cpu_vmxon(u64 addr);
718static void kvm_cpu_vmxoff(void);
776e58ea 719static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 720static void vmx_set_segment(struct kvm_vcpu *vcpu,
721 struct kvm_segment *var, int seg);
722static void vmx_get_segment(struct kvm_vcpu *vcpu,
723 struct kvm_segment *var, int seg);
d99e4152
GN		 724static bool guest_state_valid(struct kvm_vcpu *vcpu);
725static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 726static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 727static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 728static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 729
6aa8b732
AK		 730static DEFINE_PER_CPU(struct vmcs *, vmxarea);
731static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 732/*
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
735 */
736static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 737static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 738
3e7c73e9
AK		 739static unsigned long *vmx_io_bitmap_a;
740static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 741static unsigned long *vmx_msr_bitmap_legacy;
742static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 743static unsigned long *vmx_msr_bitmap_legacy_x2apic;
744static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 745static unsigned long *vmx_vmread_bitmap;
746static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 747
110312c8 748static bool cpu_has_load_ia32_efer;
8bf00a52 749static bool cpu_has_load_perf_global_ctrl;
110312c8 750
2384d2b3
SY		 751static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
752static DEFINE_SPINLOCK(vmx_vpid_lock);
753
1c3d14fe 754static struct vmcs_config {
6aa8b732
AK		 755 int size;
756 int order;
757 u32 revision_id;
1c3d14fe
YS		 758 u32 pin_based_exec_ctrl;
759 u32 cpu_based_exec_ctrl;
f78e0e2e 760 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 761 u32 vmexit_ctrl;
762 u32 vmentry_ctrl;
763} vmcs_config;
6aa8b732 764
efff9e53 765static struct vmx_capability {
d56f546d
SY		 766 u32 ept;
767 u32 vpid;
768} vmx_capability;
769
6aa8b732
AK		 770#define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
776 }
777
772e0318 778static const struct kvm_vmx_segment_field {
6aa8b732
AK		 779 unsigned selector;
780 unsigned base;
781 unsigned limit;
782 unsigned ar_bytes;
783} kvm_vmx_segment_fields[] = {
784 VMX_SEGMENT_FIELD(CS),
785 VMX_SEGMENT_FIELD(DS),
786 VMX_SEGMENT_FIELD(ES),
787 VMX_SEGMENT_FIELD(FS),
788 VMX_SEGMENT_FIELD(GS),
789 VMX_SEGMENT_FIELD(SS),
790 VMX_SEGMENT_FIELD(TR),
791 VMX_SEGMENT_FIELD(LDTR),
792};
793
26bb0981
AK		 794static u64 host_efer;
795
6de4f3ad
AK		 796static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
797
4d56c8a7 798/*
8c06585d 799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 800 * away by decrementing the array size.
801 */
6aa8b732 802static const u32 vmx_msr_index[] = {
05b3e0c2 803#ifdef CONFIG_X86_64
44ea2b17 804 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 805#endif
8c06585d 806 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 807};
9d8f549d 808#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 809
31299944 810static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 811{
812 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
813 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 814 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 815}
816
31299944 817static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 818{
819 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
820 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 821 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 822}
823
31299944 824static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 825{
826 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
827 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 828 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 829}
830
31299944 831static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 832{
833 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
834 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
835}
836
31299944 837static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 838{
839 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
840 INTR_INFO_VALID_MASK)) ==
841 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
842}
843
31299944 844static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 845{
04547156 846 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 847}
848
31299944 849static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 850{
04547156 851 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 852}
853
31299944 854static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 855{
04547156 856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 857}
858
31299944 859static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 860{
04547156
SY		 861 return vmcs_config.cpu_based_exec_ctrl &
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 863}
864
774ead3a 865static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 866{
04547156
SY		 867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
869}
870
8d14695f
YZ		 871static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
872{
873 return vmcs_config.cpu_based_2nd_exec_ctrl &
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
875}
876
83d4c286
YZ		 877static inline bool cpu_has_vmx_apic_register_virt(void)
878{
879 return vmcs_config.cpu_based_2nd_exec_ctrl &
880 SECONDARY_EXEC_APIC_REGISTER_VIRT;
881}
882
c7c9c56c
YZ		 883static inline bool cpu_has_vmx_virtual_intr_delivery(void)
884{
885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
887}
888
01e439be
YZ		 889static inline bool cpu_has_vmx_posted_intr(void)
890{
891 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
892}
893
894static inline bool cpu_has_vmx_apicv(void)
895{
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
899}
900
04547156
SY		 901static inline bool cpu_has_vmx_flexpriority(void)
902{
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 905}
906
e799794e
MT		 907static inline bool cpu_has_vmx_ept_execute_only(void)
908{
31299944 909 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 910}
911
912static inline bool cpu_has_vmx_eptp_uncacheable(void)
913{
31299944 914 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 915}
916
917static inline bool cpu_has_vmx_eptp_writeback(void)
918{
31299944 919 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 920}
921
922static inline bool cpu_has_vmx_ept_2m_page(void)
923{
31299944 924 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 925}
926
878403b7
SY		 927static inline bool cpu_has_vmx_ept_1g_page(void)
928{
31299944 929 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 930}
931
4bc9b982
SY		 932static inline bool cpu_has_vmx_ept_4levels(void)
933{
934 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
935}
936
83c3a331
XH		 937static inline bool cpu_has_vmx_ept_ad_bits(void)
938{
939 return vmx_capability.ept & VMX_EPT_AD_BIT;
940}
941
31299944 942static inline bool cpu_has_vmx_invept_context(void)
d56f546d 943{
31299944 944 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 945}
946
31299944 947static inline bool cpu_has_vmx_invept_global(void)
d56f546d 948{
31299944 949 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 950}
951
518c8aee
GJ		 952static inline bool cpu_has_vmx_invvpid_single(void)
953{
954 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
955}
956
b9d762fa
GJ		 957static inline bool cpu_has_vmx_invvpid_global(void)
958{
959 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
960}
961
31299944 962static inline bool cpu_has_vmx_ept(void)
d56f546d 963{
04547156
SY		 964 return vmcs_config.cpu_based_2nd_exec_ctrl &
965 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 966}
967
31299944 968static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 969{
970 return vmcs_config.cpu_based_2nd_exec_ctrl &
971 SECONDARY_EXEC_UNRESTRICTED_GUEST;
972}
973
31299944 974static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 975{
976 return vmcs_config.cpu_based_2nd_exec_ctrl &
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
978}
979
31299944 980static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 981{
6d3e435e 982 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 983}
984
31299944 985static inline bool cpu_has_vmx_vpid(void)
2384d2b3 986{
04547156
SY		 987 return vmcs_config.cpu_based_2nd_exec_ctrl &
988 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 989}
990
31299944 991static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 992{
993 return vmcs_config.cpu_based_2nd_exec_ctrl &
994 SECONDARY_EXEC_RDTSCP;
995}
996
ad756a16
MJ		 997static inline bool cpu_has_vmx_invpcid(void)
998{
999 return vmcs_config.cpu_based_2nd_exec_ctrl &
1000 SECONDARY_EXEC_ENABLE_INVPCID;
1001}
1002
31299944 1003static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1004{
1005 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1006}
1007
f5f48ee1
SY		 1008static inline bool cpu_has_vmx_wbinvd_exit(void)
1009{
1010 return vmcs_config.cpu_based_2nd_exec_ctrl &
1011 SECONDARY_EXEC_WBINVD_EXITING;
1012}
1013
abc4fc58
AG		 1014static inline bool cpu_has_vmx_shadow_vmcs(void)
1015{
1016 u64 vmx_msr;
1017 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1020 return false;
1021
1022 return vmcs_config.cpu_based_2nd_exec_ctrl &
1023 SECONDARY_EXEC_SHADOW_VMCS;
1024}
1025
04547156
SY		 1026static inline bool report_flexpriority(void)
1027{
1028 return flexpriority_enabled;
1029}
1030
fe3ef05c
NHE		 1031static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1032{
1033 return vmcs12->cpu_based_vm_exec_control & bit;
1034}
1035
1036static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1037{
1038 return (vmcs12->cpu_based_vm_exec_control &
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1040 (vmcs12->secondary_vm_exec_control & bit);
1041}
1042
f5c4368f 1043static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1044{
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
155a97a3
NHE		 1048static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1049{
1050 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1051}
1052
644d711a
NHE		 1053static inline bool is_exception(u32 intr_info)
1054{
1055 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1056 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1057}
1058
1059static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1060static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1061 struct vmcs12 *vmcs12,
1062 u32 reason, unsigned long qualification);
1063
8b9cf98c 1064static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1065{
1066 int i;
1067
a2fa3e9f 1068 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1069 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1070 return i;
1071 return -1;
1072}
1073
2384d2b3
SY		 1074static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1075{
1076 struct {
1077 u64 vpid : 16;
1078 u64 rsvd : 48;
1079 u64 gva;
1080 } operand = { vpid, 0, gva };
1081
4ecac3fd 1082 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand), "c"(ext) : "cc", "memory");
1086}
1087
1439442c
SY		 1088static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1089{
1090 struct {
1091 u64 eptp, gpa;
1092 } operand = {eptp, gpa};
1093
4ecac3fd 1094 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand), "c" (ext) : "cc", "memory");
1098}
1099
26bb0981 1100static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1101{
1102 int i;
1103
8b9cf98c 1104 i = __find_msr_index(vmx, msr);
a75beee6 1105 if (i >= 0)
a2fa3e9f 1106 return &vmx->guest_msrs[i];
8b6d44c7 1107 return NULL;
7725f0ba
AK		 1108}
1109
6aa8b732
AK		 1110static void vmcs_clear(struct vmcs *vmcs)
1111{
1112 u64 phys_addr = __pa(vmcs);
1113 u8 error;
1114
4ecac3fd 1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1116 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1117 : "cc", "memory");
1118 if (error)
1119 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1120 vmcs, phys_addr);
1121}
1122
d462b819
NHE		 1123static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1124{
1125 vmcs_clear(loaded_vmcs->vmcs);
1126 loaded_vmcs->cpu = -1;
1127 loaded_vmcs->launched = 0;
1128}
1129
7725b894
DX		 1130static void vmcs_load(struct vmcs *vmcs)
1131{
1132 u64 phys_addr = __pa(vmcs);
1133 u8 error;
1134
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1136 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1137 : "cc", "memory");
1138 if (error)
2844d849 1139 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1140 vmcs, phys_addr);
1141}
1142
8f536b76
ZY		 1143#ifdef CONFIG_KEXEC
1144/*
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1147 * default.
1148 */
1149static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1150
1151static inline void crash_enable_local_vmclear(int cpu)
1152{
1153 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static inline void crash_disable_local_vmclear(int cpu)
1157{
1158 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static inline int crash_local_vmclear_enabled(int cpu)
1162{
1163 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1164}
1165
1166static void crash_vmclear_local_loaded_vmcss(void)
1167{
1168 int cpu = raw_smp_processor_id();
1169 struct loaded_vmcs *v;
1170
1171 if (!crash_local_vmclear_enabled(cpu))
1172 return;
1173
1174 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1175 loaded_vmcss_on_cpu_link)
1176 vmcs_clear(v->vmcs);
1177}
1178#else
1179static inline void crash_enable_local_vmclear(int cpu) { }
1180static inline void crash_disable_local_vmclear(int cpu) { }
1181#endif /* CONFIG_KEXEC */
1182
d462b819 1183static void __loaded_vmcs_clear(void *arg)
6aa8b732 1184{
d462b819 1185 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1186 int cpu = raw_smp_processor_id();
6aa8b732 1187
d462b819
NHE		 1188 if (loaded_vmcs->cpu != cpu)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1191 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1192 crash_disable_local_vmclear(cpu);
d462b819 1193 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1194
1195 /*
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1200 */
1201 smp_wmb();
1202
d462b819 1203 loaded_vmcs_init(loaded_vmcs);
8f536b76 1204 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1205}
1206
d462b819 1207static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1208{
e6c7d321
XG		 1209 int cpu = loaded_vmcs->cpu;
1210
1211 if (cpu != -1)
1212 smp_call_function_single(cpu,
1213 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1214}
1215
1760dd49 1216static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1217{
1218 if (vmx->vpid == 0)
1219 return;
1220
518c8aee
GJ		 1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1223}
1224
b9d762fa
GJ		 1225static inline void vpid_sync_vcpu_global(void)
1226{
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1229}
1230
1231static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1232{
1233 if (cpu_has_vmx_invvpid_single())
1760dd49 1234 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1235 else
1236 vpid_sync_vcpu_global();
1237}
1238
1439442c
SY		 1239static inline void ept_sync_global(void)
1240{
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1243}
1244
1245static inline void ept_sync_context(u64 eptp)
1246{
089d034e 1247 if (enable_ept) {
1439442c
SY		 1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1250 else
1251 ept_sync_global();
1252 }
1253}
1254
96304217 1255static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1256{
5e520e62 1257 unsigned long value;
6aa8b732 1258
5e520e62
AK		 1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1260 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1261 return value;
1262}
1263
96304217 1264static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1265{
1266 return vmcs_readl(field);
1267}
1268
96304217 1269static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1270{
1271 return vmcs_readl(field);
1272}
1273
96304217 1274static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1275{
05b3e0c2 1276#ifdef CONFIG_X86_64
6aa8b732
AK		 1277 return vmcs_readl(field);
1278#else
1279 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1280#endif
1281}
1282
e52de1b8
AK		 1283static noinline void vmwrite_error(unsigned long field, unsigned long value)
1284{
1285 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1286 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1287 dump_stack();
1288}
1289
6aa8b732
AK		 1290static void vmcs_writel(unsigned long field, unsigned long value)
1291{
1292 u8 error;
1293
4ecac3fd 1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1295 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1296 if (unlikely(error))
1297 vmwrite_error(field, value);
6aa8b732
AK		 1298}
1299
1300static void vmcs_write16(unsigned long field, u16 value)
1301{
1302 vmcs_writel(field, value);
1303}
1304
1305static void vmcs_write32(unsigned long field, u32 value)
1306{
1307 vmcs_writel(field, value);
1308}
1309
1310static void vmcs_write64(unsigned long field, u64 value)
1311{
6aa8b732 1312 vmcs_writel(field, value);
7682f2d0 1313#ifndef CONFIG_X86_64
6aa8b732
AK		 1314 asm volatile ("");
1315 vmcs_writel(field+1, value >> 32);
1316#endif
1317}
1318
2ab455cc
AL		 1319static void vmcs_clear_bits(unsigned long field, u32 mask)
1320{
1321 vmcs_writel(field, vmcs_readl(field) & ~mask);
1322}
1323
1324static void vmcs_set_bits(unsigned long field, u32 mask)
1325{
1326 vmcs_writel(field, vmcs_readl(field) | mask);
1327}
1328
2fb92db1
AK		 1329static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1330{
1331 vmx->segment_cache.bitmask = 0;
1332}
1333
1334static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1335 unsigned field)
1336{
1337 bool ret;
1338 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1339
1340 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1341 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1342 vmx->segment_cache.bitmask = 0;
1343 }
1344 ret = vmx->segment_cache.bitmask & mask;
1345 vmx->segment_cache.bitmask |= mask;
1346 return ret;
1347}
1348
1349static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1350{
1351 u16 *p = &vmx->segment_cache.seg[seg].selector;
1352
1353 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1354 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1355 return *p;
1356}
1357
1358static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1359{
1360 ulong *p = &vmx->segment_cache.seg[seg].base;
1361
1362 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1363 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1364 return *p;
1365}
1366
1367static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1368{
1369 u32 *p = &vmx->segment_cache.seg[seg].limit;
1370
1371 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1372 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1373 return *p;
1374}
1375
1376static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1377{
1378 u32 *p = &vmx->segment_cache.seg[seg].ar;
1379
1380 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1381 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1382 return *p;
1383}
1384
abd3f2d6
AK		 1385static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1386{
1387 u32 eb;
1388
fd7373cc
JK		 1389 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1390 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1391 if ((vcpu->guest_debug &
1392 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1393 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1394 eb |= 1u << BP_VECTOR;
7ffd92c5 1395 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1396 eb = ~0;
089d034e 1397 if (enable_ept)
1439442c 1398 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1399 if (vcpu->fpu_active)
1400 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1401
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1406 */
1407 if (is_guest_mode(vcpu))
1408 eb |= get_vmcs12(vcpu)->exception_bitmap;
1409
abd3f2d6
AK		 1410 vmcs_write32(EXCEPTION_BITMAP, eb);
1411}
1412
8bf00a52
GN		 1413static void clear_atomic_switch_msr_special(unsigned long entry,
1414 unsigned long exit)
1415{
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1418}
1419
61d2ef2c
AK		 1420static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1421{
1422 unsigned i;
1423 struct msr_autoload *m = &vmx->msr_autoload;
1424
8bf00a52
GN		 1425 switch (msr) {
1426 case MSR_EFER:
1427 if (cpu_has_load_ia32_efer) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1429 VM_EXIT_LOAD_IA32_EFER);
1430 return;
1431 }
1432 break;
1433 case MSR_CORE_PERF_GLOBAL_CTRL:
1434 if (cpu_has_load_perf_global_ctrl) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1438 return;
1439 }
1440 break;
110312c8
AK		 1441 }
1442
61d2ef2c
AK		 1443 for (i = 0; i < m->nr; ++i)
1444 if (m->guest[i].index == msr)
1445 break;
1446
1447 if (i == m->nr)
1448 return;
1449 --m->nr;
1450 m->guest[i] = m->guest[m->nr];
1451 m->host[i] = m->host[m->nr];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1454}
1455
8bf00a52
GN		 1456static void add_atomic_switch_msr_special(unsigned long entry,
1457 unsigned long exit, unsigned long guest_val_vmcs,
1458 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1459{
1460 vmcs_write64(guest_val_vmcs, guest_val);
1461 vmcs_write64(host_val_vmcs, host_val);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1463 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1464}
1465
61d2ef2c
AK		 1466static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1467 u64 guest_val, u64 host_val)
1468{
1469 unsigned i;
1470 struct msr_autoload *m = &vmx->msr_autoload;
1471
8bf00a52
GN		 1472 switch (msr) {
1473 case MSR_EFER:
1474 if (cpu_has_load_ia32_efer) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1476 VM_EXIT_LOAD_IA32_EFER,
1477 GUEST_IA32_EFER,
1478 HOST_IA32_EFER,
1479 guest_val, host_val);
1480 return;
1481 }
1482 break;
1483 case MSR_CORE_PERF_GLOBAL_CTRL:
1484 if (cpu_has_load_perf_global_ctrl) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1488 GUEST_IA32_PERF_GLOBAL_CTRL,
1489 HOST_IA32_PERF_GLOBAL_CTRL,
1490 guest_val, host_val);
1491 return;
1492 }
1493 break;
110312c8
AK		 1494 }
1495
61d2ef2c
AK		 1496 for (i = 0; i < m->nr; ++i)
1497 if (m->guest[i].index == msr)
1498 break;
1499
e7fc6f93
GN		 1500 if (i == NR_AUTOLOAD_MSRS) {
1501 printk_once(KERN_WARNING"Not enough mst switch entries. "
1502 "Can't add msr %x\n", msr);
1503 return;
1504 } else if (i == m->nr) {
61d2ef2c
AK		 1505 ++m->nr;
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1508 }
1509
1510 m->guest[i].index = msr;
1511 m->guest[i].value = guest_val;
1512 m->host[i].index = msr;
1513 m->host[i].value = host_val;
1514}
1515
33ed6329
AK		 1516static void reload_tss(void)
1517{
33ed6329
AK		 1518 /*
1519 * VT restores TR but not its size. Useless.
1520 */
d359192f 1521 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1522 struct desc_struct *descs;
33ed6329 1523
d359192f 1524 descs = (void *)gdt->address;
33ed6329
AK		 1525 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1526 load_TR_desc();
33ed6329
AK		 1527}
1528
92c0d900 1529static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1530{
3a34a881 1531 u64 guest_efer;
51c6cf66
AK		 1532 u64 ignore_bits;
1533
f6801dff 1534 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1535
51c6cf66 1536 /*
0fa06071 1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1538 * outside long mode
1539 */
1540 ignore_bits = EFER_NX | EFER_SCE;
1541#ifdef CONFIG_X86_64
1542 ignore_bits |= EFER_LMA | EFER_LME;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer & EFER_LMA)
1545 ignore_bits &= ~(u64)EFER_SCE;
1546#endif
51c6cf66
AK		 1547 guest_efer &= ~ignore_bits;
1548 guest_efer |= host_efer & ignore_bits;
26bb0981 1549 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1550 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1551
1552 clear_atomic_switch_msr(vmx, MSR_EFER);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1555 guest_efer = vmx->vcpu.arch.efer;
1556 if (!(guest_efer & EFER_LMA))
1557 guest_efer &= ~EFER_LME;
1558 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1559 return false;
1560 }
1561
26bb0981 1562 return true;
51c6cf66
AK		 1563}
1564
2d49ec72
GN		 1565static unsigned long segment_base(u16 selector)
1566{
d359192f 1567 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1568 struct desc_struct *d;
1569 unsigned long table_base;
1570 unsigned long v;
1571
1572 if (!(selector & ~3))
1573 return 0;
1574
d359192f 1575 table_base = gdt->address;
2d49ec72
GN		 1576
1577 if (selector & 4) { /* from ldt */
1578 u16 ldt_selector = kvm_read_ldt();
1579
1580 if (!(ldt_selector & ~3))
1581 return 0;
1582
1583 table_base = segment_base(ldt_selector);
1584 }
1585 d = (struct desc_struct *)(table_base + (selector & ~7));
1586 v = get_desc_base(d);
1587#ifdef CONFIG_X86_64
1588 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1589 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1590#endif
1591 return v;
1592}
1593
1594static inline unsigned long kvm_read_tr_base(void)
1595{
1596 u16 tr;
1597 asm("str %0" : "=g"(tr));
1598 return segment_base(tr);
1599}
1600
04d2cc77 1601static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1602{
04d2cc77 1603 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1604 int i;
04d2cc77 1605
a2fa3e9f 1606 if (vmx->host_state.loaded)
33ed6329
AK		 1607 return;
1608
a2fa3e9f 1609 vmx->host_state.loaded = 1;
33ed6329
AK		 1610 /*
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1613 */
d6e88aec 1614 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1615 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1616 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1617 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1618 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1619 vmx->host_state.fs_reload_needed = 0;
1620 } else {
33ed6329 1621 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1622 vmx->host_state.fs_reload_needed = 1;
33ed6329 1623 }
9581d442 1624 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1625 if (!(vmx->host_state.gs_sel & 7))
1626 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1627 else {
1628 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1629 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1630 }
1631
b2da15ac
AK		 1632#ifdef CONFIG_X86_64
1633 savesegment(ds, vmx->host_state.ds_sel);
1634 savesegment(es, vmx->host_state.es_sel);
1635#endif
1636
33ed6329
AK		 1637#ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1639 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1640#else
a2fa3e9f
GH		 1641 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1642 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1643#endif
707c0874
AK		 1644
1645#ifdef CONFIG_X86_64
c8770e7b
AK		 1646 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1647 if (is_long_mode(&vmx->vcpu))
44ea2b17 1648 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1649#endif
26bb0981
AK		 1650 for (i = 0; i < vmx->save_nmsrs; ++i)
1651 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1652 vmx->guest_msrs[i].data,
1653 vmx->guest_msrs[i].mask);
33ed6329
AK		 1654}
1655
a9b21b62 1656static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1657{
a2fa3e9f 1658 if (!vmx->host_state.loaded)
33ed6329
AK		 1659 return;
1660
e1beb1d3 1661 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1662 vmx->host_state.loaded = 0;
c8770e7b
AK		 1663#ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx->vcpu))
1665 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1666#endif
152d3f2f 1667 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1668 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1669#ifdef CONFIG_X86_64
9581d442 1670 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1671#else
1672 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1673#endif
33ed6329 1674 }
0a77fe4c
AK		 1675 if (vmx->host_state.fs_reload_needed)
1676 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1677#ifdef CONFIG_X86_64
1678 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1679 loadsegment(ds, vmx->host_state.ds_sel);
1680 loadsegment(es, vmx->host_state.es_sel);
1681 }
b2da15ac 1682#endif
152d3f2f 1683 reload_tss();
44ea2b17 1684#ifdef CONFIG_X86_64
c8770e7b 1685 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1686#endif
b1a74bf8
SS		 1687 /*
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1690 */
1691 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1692 stts();
3444d7da 1693 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1694}
1695
a9b21b62
AK		 1696static void vmx_load_host_state(struct vcpu_vmx *vmx)
1697{
1698 preempt_disable();
1699 __vmx_load_host_state(vmx);
1700 preempt_enable();
1701}
1702
6aa8b732
AK		 1703/*
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1706 */
15ad7146 1707static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1708{
a2fa3e9f 1709 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1710 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1711
4610c9cc
DX		 1712 if (!vmm_exclusive)
1713 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1714 else if (vmx->loaded_vmcs->cpu != cpu)
1715 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1716
d462b819
NHE		 1717 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1718 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1719 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1720 }
1721
d462b819 1722 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1723 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1724 unsigned long sysenter_esp;
1725
a8eeb04a 1726 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1727 local_irq_disable();
8f536b76 1728 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1729
1730 /*
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1734 */
1735 smp_rmb();
1736
d462b819
NHE		 1737 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1738 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1739 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1740 local_irq_enable();
1741
6aa8b732
AK		 1742 /*
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1744 * processors.
1745 */
d6e88aec 1746 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1747 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1748
1749 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1751 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1752 }
6aa8b732
AK		 1753}
1754
1755static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1756{
a9b21b62 1757 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1758 if (!vmm_exclusive) {
d462b819
NHE		 1759 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1760 vcpu->cpu = -1;
4610c9cc
DX		 1761 kvm_cpu_vmxoff();
1762 }
6aa8b732
AK		 1763}
1764
5fd86fcf
AK		 1765static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1766{
81231c69
AK		 1767 ulong cr0;
1768
5fd86fcf
AK		 1769 if (vcpu->fpu_active)
1770 return;
1771 vcpu->fpu_active = 1;
81231c69
AK		 1772 cr0 = vmcs_readl(GUEST_CR0);
1773 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1774 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1775 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1776 update_exception_bitmap(vcpu);
edcafe3c 1777 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1778 if (is_guest_mode(vcpu))
1779 vcpu->arch.cr0_guest_owned_bits &=
1780 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1781 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1782}
1783
edcafe3c
AK		 1784static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1785
fe3ef05c
NHE		 1786/*
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1790 */
1791static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1792{
1793 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1794 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1795}
1796static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1797{
1798 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1799 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1800}
1801
5fd86fcf
AK		 1802static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1803{
36cf24e0
NHE		 1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1806 */
edcafe3c 1807 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1808 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1809 update_exception_bitmap(vcpu);
edcafe3c
AK		 1810 vcpu->arch.cr0_guest_owned_bits = 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1812 if (is_guest_mode(vcpu)) {
1813 /*
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1820 */
1821 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1822 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1823 (vcpu->arch.cr0 & X86_CR0_TS);
1824 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1825 } else
1826 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1827}
1828
6aa8b732
AK		 1829static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1830{
78ac8b47 1831 unsigned long rflags, save_rflags;
345dcaa8 1832
6de12732
AK		 1833 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1834 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1835 rflags = vmcs_readl(GUEST_RFLAGS);
1836 if (to_vmx(vcpu)->rmode.vm86_active) {
1837 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1838 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1839 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1840 }
1841 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1842 }
6de12732 1843 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1844}
1845
1846static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1847{
6de12732
AK		 1848 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1849 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1850 if (to_vmx(vcpu)->rmode.vm86_active) {
1851 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1852 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1853 }
6aa8b732
AK		 1854 vmcs_writel(GUEST_RFLAGS, rflags);
1855}
1856
2809f5d2
GC		 1857static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1858{
1859 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1860 int ret = 0;
1861
1862 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1863 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1864 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1865 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1866
1867 return ret & mask;
1868}
1869
1870static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1871{
1872 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1873 u32 interruptibility = interruptibility_old;
1874
1875 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1876
48005f64 1877 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1878 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1879 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1880 interruptibility |= GUEST_INTR_STATE_STI;
1881
1882 if ((interruptibility != interruptibility_old))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1884}
1885
6aa8b732
AK		 1886static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1887{
1888 unsigned long rip;
6aa8b732 1889
5fdbf976 1890 rip = kvm_rip_read(vcpu);
6aa8b732 1891 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1892 kvm_rip_write(vcpu, rip);
6aa8b732 1893
2809f5d2
GC		 1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1896}
1897
0b6ac343
NHE		 1898/*
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
1901 * This function assumes it is called with the exit reason in vmcs02 being
1902 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1903 * is running).
1904 */
1905static int nested_pf_handled(struct kvm_vcpu *vcpu)
1906{
1907 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1908
1909 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1910 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1911 return 0;
1912
1913 nested_vmx_vmexit(vcpu);
1914 return 1;
1915}
1916
298101da 1917static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1918 bool has_error_code, u32 error_code,
1919 bool reinject)
298101da 1920{
77ab6db0 1921 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1922 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1923
0b6ac343 1924 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
5a2892ce 1925 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
0b6ac343
NHE		 1926 return;
1927
8ab2d2e2 1928 if (has_error_code) {
77ab6db0 1929 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1930 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1931 }
77ab6db0 1932
7ffd92c5 1933 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1934 int inc_eip = 0;
1935 if (kvm_exception_is_soft(nr))
1936 inc_eip = vcpu->arch.event_exit_inst_len;
1937 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1938 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1939 return;
1940 }
1941
66fd3f7f
GN		 1942 if (kvm_exception_is_soft(nr)) {
1943 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1944 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1945 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1946 } else
1947 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1948
1949 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1950}
1951
4e47c7a6
SY		 1952static bool vmx_rdtscp_supported(void)
1953{
1954 return cpu_has_vmx_rdtscp();
1955}
1956
ad756a16
MJ		 1957static bool vmx_invpcid_supported(void)
1958{
1959 return cpu_has_vmx_invpcid() && enable_ept;
1960}
1961
a75beee6
ED		 1962/*
1963 * Swap MSR entry in host/guest MSR entry array.
1964 */
8b9cf98c 1965static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1966{
26bb0981 1967 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1968
1969 tmp = vmx->guest_msrs[to];
1970 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1971 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1972}
1973
8d14695f
YZ		 1974static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1975{
1976 unsigned long *msr_bitmap;
1977
1978 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1979 if (is_long_mode(vcpu))
1980 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1981 else
1982 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1983 } else {
1984 if (is_long_mode(vcpu))
1985 msr_bitmap = vmx_msr_bitmap_longmode;
1986 else
1987 msr_bitmap = vmx_msr_bitmap_legacy;
1988 }
1989
1990 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1991}
1992
e38aea3e
AK		 1993/*
1994 * Set up the vmcs to automatically save and restore system
1995 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1996 * mode, as fiddling with msrs is very expensive.
1997 */
8b9cf98c 1998static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1999{
26bb0981 2000 int save_nmsrs, index;
e38aea3e 2001
a75beee6
ED		 2002 save_nmsrs = 0;
2003#ifdef CONFIG_X86_64
8b9cf98c 2004 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2005 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2006 if (index >= 0)
8b9cf98c
RR		 2007 move_msr_up(vmx, index, save_nmsrs++);
2008 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2009 if (index >= 0)
8b9cf98c
RR		 2010 move_msr_up(vmx, index, save_nmsrs++);
2011 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2012 if (index >= 0)
8b9cf98c 2013 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2014 index = __find_msr_index(vmx, MSR_TSC_AUX);
2015 if (index >= 0 && vmx->rdtscp_enabled)
2016 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2017 /*
8c06585d 2018 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2019 * if efer.sce is enabled.
2020 */
8c06585d 2021 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2022 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2023 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2024 }
2025#endif
92c0d900
AK		 2026 index = __find_msr_index(vmx, MSR_EFER);
2027 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2028 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2029
26bb0981 2030 vmx->save_nmsrs = save_nmsrs;
5897297b 2031
8d14695f
YZ		 2032 if (cpu_has_vmx_msr_bitmap())
2033 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2034}
2035
6aa8b732
AK		 2036/*
2037 * reads and returns guest's timestamp counter "register"
2038 * guest_tsc = host_tsc + tsc_offset -- 21.3
2039 */
2040static u64 guest_read_tsc(void)
2041{
2042 u64 host_tsc, tsc_offset;
2043
2044 rdtscll(host_tsc);
2045 tsc_offset = vmcs_read64(TSC_OFFSET);
2046 return host_tsc + tsc_offset;
2047}
2048
d5c1785d
NHE		 2049/*
2050 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2051 * counter, even if a nested guest (L2) is currently running.
2052 */
886b470c 2053u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2054{
886b470c 2055 u64 tsc_offset;
d5c1785d 2056
d5c1785d
NHE		 2057 tsc_offset = is_guest_mode(vcpu) ?
2058 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2059 vmcs_read64(TSC_OFFSET);
2060 return host_tsc + tsc_offset;
2061}
2062
4051b188 2063/*
cc578287
ZA		 2064 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2065 * software catchup for faster rates on slower CPUs.
4051b188 2066 */
cc578287 2067static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2068{
cc578287
ZA		 2069 if (!scale)
2070 return;
2071
2072 if (user_tsc_khz > tsc_khz) {
2073 vcpu->arch.tsc_catchup = 1;
2074 vcpu->arch.tsc_always_catchup = 1;
2075 } else
2076 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2077}
2078
ba904635
WA		 2079static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2080{
2081 return vmcs_read64(TSC_OFFSET);
2082}
2083
6aa8b732 2084/*
99e3e30a 2085 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2086 */
99e3e30a 2087static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2088{
27fc51b2 2089 if (is_guest_mode(vcpu)) {
7991825b 2090 /*
27fc51b2
NHE		 2091 * We're here if L1 chose not to trap WRMSR to TSC. According
2092 * to the spec, this should set L1's TSC; The offset that L1
2093 * set for L2 remains unchanged, and still needs to be added
2094 * to the newly set TSC to get L2's TSC.
7991825b 2095 */
27fc51b2
NHE		 2096 struct vmcs12 *vmcs12;
2097 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2098 /* recalculate vmcs02.TSC_OFFSET: */
2099 vmcs12 = get_vmcs12(vcpu);
2100 vmcs_write64(TSC_OFFSET, offset +
2101 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2102 vmcs12->tsc_offset : 0));
2103 } else {
489223ed
YY		 2104 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2105 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2106 vmcs_write64(TSC_OFFSET, offset);
2107 }
6aa8b732
AK		 2108}
2109
f1e2b260 2110static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2111{
2112 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2113
e48672fa 2114 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2115 if (is_guest_mode(vcpu)) {
2116 /* Even when running L2, the adjustment needs to apply to L1 */
2117 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2118 } else
2119 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2120 offset + adjustment);
e48672fa
ZA		 2121}
2122
857e4099
JR		 2123static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2124{
2125 return target_tsc - native_read_tsc();
2126}
2127
801d3424
NHE		 2128static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2129{
2130 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2131 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2132}
2133
2134/*
2135 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2136 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2137 * all guests if the "nested" module option is off, and can also be disabled
2138 * for a single guest by disabling its VMX cpuid bit.
2139 */
2140static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2141{
2142 return nested && guest_cpuid_has_vmx(vcpu);
2143}
2144
b87a51ae
NHE		 2145/*
2146 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2147 * returned for the various VMX controls MSRs when nested VMX is enabled.
2148 * The same values should also be used to verify that vmcs12 control fields are
2149 * valid during nested entry from L1 to L2.
2150 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2151 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2152 * bit in the high half is on if the corresponding bit in the control field
2153 * may be on. See also vmx_control_verify().
2154 * TODO: allow these variables to be modified (downgraded) by module options
2155 * or other means.
2156 */
2157static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2158static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2159static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2160static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2161static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2162static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2163static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2164static __init void nested_vmx_setup_ctls_msrs(void)
2165{
2166 /*
2167 * Note that as a general rule, the high half of the MSRs (bits in
2168 * the control fields which may be 1) should be initialized by the
2169 * intersection of the underlying hardware's MSR (i.e., features which
2170 * can be supported) and the list of features we want to expose -
2171 * because they are known to be properly supported in our code.
2172 * Also, usually, the low half of the MSRs (bits which must be 1) can
2173 * be set to 0, meaning that L1 may turn off any of these bits. The
2174 * reason is that if one of these bits is necessary, it will appear
2175 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2176 * fields of vmcs01 and vmcs02, will turn these bits off - and
2177 * nested_vmx_exit_handled() will not pass related exits to L1.
2178 * These rules have exceptions below.
2179 */
2180
2181 /* pin-based controls */
eabeaacc
JK		 2182 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2183 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2184 /*
2185 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2186 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2187 */
eabeaacc
JK		 2188 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2189 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2190 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2191 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2192 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2193
33fb20c3
JK		 2194 /*
2195 * Exit controls
2196 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2197 * 17 must be 1.
2198 */
2199 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2200 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2201#ifdef CONFIG_X86_64
2202 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2203#else
2204 nested_vmx_exit_ctls_high = 0;
2205#endif
8049d651
NHE		 2206 nested_vmx_exit_ctls_high |= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2207 VM_EXIT_LOAD_IA32_EFER);
b87a51ae
NHE		 2208
2209 /* entry controls */
2210 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2211 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2212 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2213 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2214 nested_vmx_entry_ctls_high &=
2215 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
8049d651
NHE		 2216 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2217 VM_ENTRY_LOAD_IA32_EFER);
b87a51ae
NHE		 2218 /* cpu-based controls */
2219 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2220 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2221 nested_vmx_procbased_ctls_low = 0;
2222 nested_vmx_procbased_ctls_high &=
2223 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2224 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2225 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2226 CPU_BASED_CR3_STORE_EXITING |
2227#ifdef CONFIG_X86_64
2228 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2229#endif
2230 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2231 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2232 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2233 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2234 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2235 /*
2236 * We can allow some features even when not supported by the
2237 * hardware. For example, L1 can specify an MSR bitmap - and we
2238 * can use it to avoid exits to L1 - even when L0 runs L2
2239 * without MSR bitmaps.
2240 */
2241 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2242
2243 /* secondary cpu-based controls */
2244 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2245 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2246 nested_vmx_secondary_ctls_low = 0;
2247 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2248 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2249 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2250
afa61f75
NHE		 2251 if (enable_ept) {
2252 /* nested EPT: emulate EPT also to L1 */
2253 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
2254 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT;
2255 nested_vmx_ept_caps |= VMX_EPT_INVEPT_BIT;
2256 nested_vmx_ept_caps &= vmx_capability.ept;
2257 /*
2258 * Since invept is completely emulated we support both global
2259 * and context invalidation independent of what host cpu
2260 * supports
2261 */
2262 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT |
2263 VMX_EPT_EXTENT_CONTEXT_BIT;
2264 } else
2265 nested_vmx_ept_caps = 0;
2266
c18911a2
JK		 2267 /* miscellaneous data */
2268 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2269 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2270 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2271 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2272}
2273
2274static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2275{
2276 /*
2277 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2278 */
2279 return ((control & high) | low) == control;
2280}
2281
2282static inline u64 vmx_control_msr(u32 low, u32 high)
2283{
2284 return low | ((u64)high << 32);
2285}
2286
2287/*
2288 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2289 * also let it use VMX-specific MSRs.
2290 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2291 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2292 * like all other MSRs).
2293 */
2294static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2295{
2296 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2297 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2298 /*
2299 * According to the spec, processors which do not support VMX
2300 * should throw a #GP(0) when VMX capability MSRs are read.
2301 */
2302 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2303 return 1;
2304 }
2305
2306 switch (msr_index) {
2307 case MSR_IA32_FEATURE_CONTROL:
b3897a49
NHE		 2308 if (nested_vmx_allowed(vcpu)) {
2309 *pdata = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2310 break;
2311 }
2312 return 0;
b87a51ae
NHE		 2313 case MSR_IA32_VMX_BASIC:
2314 /*
2315 * This MSR reports some information about VMX support. We
2316 * should return information about the VMX we emulate for the
2317 * guest, and the VMCS structure we give it - not about the
2318 * VMX support of the underlying hardware.
2319 */
2320 *pdata = VMCS12_REVISION |
2321 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2322 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2323 break;
2324 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2325 case MSR_IA32_VMX_PINBASED_CTLS:
2326 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2327 nested_vmx_pinbased_ctls_high);
2328 break;
2329 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2330 case MSR_IA32_VMX_PROCBASED_CTLS:
2331 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2332 nested_vmx_procbased_ctls_high);
2333 break;
2334 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2335 case MSR_IA32_VMX_EXIT_CTLS:
2336 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2337 nested_vmx_exit_ctls_high);
2338 break;
2339 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2340 case MSR_IA32_VMX_ENTRY_CTLS:
2341 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2342 nested_vmx_entry_ctls_high);
2343 break;
2344 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2345 *pdata = vmx_control_msr(nested_vmx_misc_low,
2346 nested_vmx_misc_high);
b87a51ae
NHE		 2347 break;
2348 /*
2349 * These MSRs specify bits which the guest must keep fixed (on or off)
2350 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2351 * We picked the standard core2 setting.
2352 */
2353#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2354#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2355 case MSR_IA32_VMX_CR0_FIXED0:
2356 *pdata = VMXON_CR0_ALWAYSON;
2357 break;
2358 case MSR_IA32_VMX_CR0_FIXED1:
2359 *pdata = -1ULL;
2360 break;
2361 case MSR_IA32_VMX_CR4_FIXED0:
2362 *pdata = VMXON_CR4_ALWAYSON;
2363 break;
2364 case MSR_IA32_VMX_CR4_FIXED1:
2365 *pdata = -1ULL;
2366 break;
2367 case MSR_IA32_VMX_VMCS_ENUM:
2368 *pdata = 0x1f;
2369 break;
2370 case MSR_IA32_VMX_PROCBASED_CTLS2:
2371 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2372 nested_vmx_secondary_ctls_high);
2373 break;
2374 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2375 /* Currently, no nested vpid support */
2376 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2377 break;
2378 default:
2379 return 0;
2380 }
2381
2382 return 1;
2383}
2384
b3897a49 2385static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
b87a51ae 2386{
b3897a49
NHE		 2387 u32 msr_index = msr_info->index;
2388 u64 data = msr_info->data;
2389 bool host_initialized = msr_info->host_initiated;
2390
b87a51ae
NHE		 2391 if (!nested_vmx_allowed(vcpu))
2392 return 0;
2393
b3897a49
NHE		 2394 if (msr_index == MSR_IA32_FEATURE_CONTROL) {
2395 if (!host_initialized &&
2396 to_vmx(vcpu)->nested.msr_ia32_feature_control
2397 & FEATURE_CONTROL_LOCKED)
2398 return 0;
2399 to_vmx(vcpu)->nested.msr_ia32_feature_control = data;
b87a51ae 2400 return 1;
b3897a49
NHE		 2401 }
2402
b87a51ae
NHE		 2403 /*
2404 * No need to treat VMX capability MSRs specially: If we don't handle
2405 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2406 */
2407 return 0;
2408}
2409
6aa8b732
AK		 2410/*
2411 * Reads an msr value (of 'msr_index') into 'pdata'.
2412 * Returns 0 on success, non-0 otherwise.
2413 * Assumes vcpu_load() was already called.
2414 */
2415static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2416{
2417 u64 data;
26bb0981 2418 struct shared_msr_entry *msr;
6aa8b732
AK		 2419
2420 if (!pdata) {
2421 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2422 return -EINVAL;
2423 }
2424
2425 switch (msr_index) {
05b3e0c2 2426#ifdef CONFIG_X86_64
6aa8b732
AK		 2427 case MSR_FS_BASE:
2428 data = vmcs_readl(GUEST_FS_BASE);
2429 break;
2430 case MSR_GS_BASE:
2431 data = vmcs_readl(GUEST_GS_BASE);
2432 break;
44ea2b17
AK		 2433 case MSR_KERNEL_GS_BASE:
2434 vmx_load_host_state(to_vmx(vcpu));
2435 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2436 break;
26bb0981 2437#endif
6aa8b732 2438 case MSR_EFER:
3bab1f5d 2439 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2440 case MSR_IA32_TSC:
6aa8b732
AK		 2441 data = guest_read_tsc();
2442 break;
2443 case MSR_IA32_SYSENTER_CS:
2444 data = vmcs_read32(GUEST_SYSENTER_CS);
2445 break;
2446 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2447 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2448 break;
2449 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2450 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2451 break;
4e47c7a6
SY		 2452 case MSR_TSC_AUX:
2453 if (!to_vmx(vcpu)->rdtscp_enabled)
2454 return 1;
2455 /* Otherwise falls through */
6aa8b732 2456 default:
b87a51ae
NHE		 2457 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2458 return 0;
8b9cf98c 2459 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2460 if (msr) {
2461 data = msr->data;
2462 break;
6aa8b732 2463 }
3bab1f5d 2464 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2465 }
2466
2467 *pdata = data;
2468 return 0;
2469}
2470
2471/*
2472 * Writes msr value into into the appropriate "register".
2473 * Returns 0 on success, non-0 otherwise.
2474 * Assumes vcpu_load() was already called.
2475 */
8fe8ab46 2476static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2477{
a2fa3e9f 2478 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2479 struct shared_msr_entry *msr;
2cc51560 2480 int ret = 0;
8fe8ab46
WA		 2481 u32 msr_index = msr_info->index;
2482 u64 data = msr_info->data;
2cc51560 2483
6aa8b732 2484 switch (msr_index) {
3bab1f5d 2485 case MSR_EFER:
8fe8ab46 2486 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2487 break;
16175a79 2488#ifdef CONFIG_X86_64
6aa8b732 2489 case MSR_FS_BASE:
2fb92db1 2490 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2491 vmcs_writel(GUEST_FS_BASE, data);
2492 break;
2493 case MSR_GS_BASE:
2fb92db1 2494 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2495 vmcs_writel(GUEST_GS_BASE, data);
2496 break;
44ea2b17
AK		 2497 case MSR_KERNEL_GS_BASE:
2498 vmx_load_host_state(vmx);
2499 vmx->msr_guest_kernel_gs_base = data;
2500 break;
6aa8b732
AK		 2501#endif
2502 case MSR_IA32_SYSENTER_CS:
2503 vmcs_write32(GUEST_SYSENTER_CS, data);
2504 break;
2505 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2506 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2507 break;
2508 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2509 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2510 break;
af24a4e4 2511 case MSR_IA32_TSC:
8fe8ab46 2512 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2513 break;
468d472f
SY		 2514 case MSR_IA32_CR_PAT:
2515 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2516 vmcs_write64(GUEST_IA32_PAT, data);
2517 vcpu->arch.pat = data;
2518 break;
2519 }
8fe8ab46 2520 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2521 break;
ba904635
WA		 2522 case MSR_IA32_TSC_ADJUST:
2523 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2524 break;
2525 case MSR_TSC_AUX:
2526 if (!vmx->rdtscp_enabled)
2527 return 1;
2528 /* Check reserved bit, higher 32 bits should be zero */
2529 if ((data >> 32) != 0)
2530 return 1;
2531 /* Otherwise falls through */
6aa8b732 2532 default:
b3897a49 2533 if (vmx_set_vmx_msr(vcpu, msr_info))
b87a51ae 2534 break;
8b9cf98c 2535 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2536 if (msr) {
2537 msr->data = data;
2225fd56
AK		 2538 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2539 preempt_disable();
9ee73970
AK		 2540 kvm_set_shared_msr(msr->index, msr->data,
2541 msr->mask);
2225fd56
AK		 2542 preempt_enable();
2543 }
3bab1f5d 2544 break;
6aa8b732 2545 }
8fe8ab46 2546 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2547 }
2548
2cc51560 2549 return ret;
6aa8b732
AK		 2550}
2551
5fdbf976 2552static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2553{
5fdbf976
MT		 2554 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2555 switch (reg) {
2556 case VCPU_REGS_RSP:
2557 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2558 break;
2559 case VCPU_REGS_RIP:
2560 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2561 break;
6de4f3ad
AK		 2562 case VCPU_EXREG_PDPTR:
2563 if (enable_ept)
2564 ept_save_pdptrs(vcpu);
2565 break;
5fdbf976
MT		 2566 default:
2567 break;
2568 }
6aa8b732
AK		 2569}
2570
6aa8b732
AK		 2571static __init int cpu_has_kvm_support(void)
2572{
6210e37b 2573 return cpu_has_vmx();
6aa8b732
AK		 2574}
2575
2576static __init int vmx_disabled_by_bios(void)
2577{
2578 u64 msr;
2579
2580 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2581 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2582 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2583 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2584 && tboot_enabled())
2585 return 1;
23f3e991 2586 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2587 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2588 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2589 && !tboot_enabled()) {
2590 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2591 "activate TXT before enabling KVM\n");
cafd6659 2592 return 1;
f9335afe 2593 }
23f3e991
JC		 2594 /* launched w/o TXT and VMX disabled */
2595 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2596 && !tboot_enabled())
2597 return 1;
cafd6659
SW		 2598 }
2599
2600 return 0;
6aa8b732
AK		 2601}
2602
7725b894
DX		 2603static void kvm_cpu_vmxon(u64 addr)
2604{
2605 asm volatile (ASM_VMX_VMXON_RAX
2606 : : "a"(&addr), "m"(addr)
2607 : "memory", "cc");
2608}
2609
10474ae8 2610static int hardware_enable(void *garbage)
6aa8b732
AK		 2611{
2612 int cpu = raw_smp_processor_id();
2613 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2614 u64 old, test_bits;
6aa8b732 2615
10474ae8
AG		 2616 if (read_cr4() & X86_CR4_VMXE)
2617 return -EBUSY;
2618
d462b819 2619 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2620
2621 /*
2622 * Now we can enable the vmclear operation in kdump
2623 * since the loaded_vmcss_on_cpu list on this cpu
2624 * has been initialized.
2625 *
2626 * Though the cpu is not in VMX operation now, there
2627 * is no problem to enable the vmclear operation
2628 * for the loaded_vmcss_on_cpu list is empty!
2629 */
2630 crash_enable_local_vmclear(cpu);
2631
6aa8b732 2632 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2633
2634 test_bits = FEATURE_CONTROL_LOCKED;
2635 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2636 if (tboot_enabled())
2637 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2638
2639 if ((old & test_bits) != test_bits) {
6aa8b732 2640 /* enable and lock */
cafd6659
SW		 2641 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2642 }
66aee91a 2643 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2644
4610c9cc
DX		 2645 if (vmm_exclusive) {
2646 kvm_cpu_vmxon(phys_addr);
2647 ept_sync_global();
2648 }
10474ae8 2649
357d1226 2650 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2651
10474ae8 2652 return 0;
6aa8b732
AK		 2653}
2654
d462b819 2655static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2656{
2657 int cpu = raw_smp_processor_id();
d462b819 2658 struct loaded_vmcs *v, *n;
543e4243 2659
d462b819
NHE		 2660 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2661 loaded_vmcss_on_cpu_link)
2662 __loaded_vmcs_clear(v);
543e4243
AK		 2663}
2664
710ff4a8
EH		 2665
2666/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2667 * tricks.
2668 */
2669static void kvm_cpu_vmxoff(void)
6aa8b732 2670{
4ecac3fd 2671 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2672}
2673
710ff4a8
EH		 2674static void hardware_disable(void *garbage)
2675{
4610c9cc 2676 if (vmm_exclusive) {
d462b819 2677 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2678 kvm_cpu_vmxoff();
2679 }
7725b894 2680 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2681}
2682
1c3d14fe 2683static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2684 u32 msr, u32 *result)
1c3d14fe
YS		 2685{
2686 u32 vmx_msr_low, vmx_msr_high;
2687 u32 ctl = ctl_min | ctl_opt;
2688
2689 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2690
2691 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2692 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2693
2694 /* Ensure minimum (required) set of control bits are supported. */
2695 if (ctl_min & ~ctl)
002c7f7c 2696 return -EIO;
1c3d14fe
YS		 2697
2698 *result = ctl;
2699 return 0;
2700}
2701
110312c8
AK		 2702static __init bool allow_1_setting(u32 msr, u32 ctl)
2703{
2704 u32 vmx_msr_low, vmx_msr_high;
2705
2706 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2707 return vmx_msr_high & ctl;
2708}
2709
002c7f7c 2710static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2711{
2712 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2713 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2714 u32 _pin_based_exec_control = 0;
2715 u32 _cpu_based_exec_control = 0;
f78e0e2e 2716 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2717 u32 _vmexit_control = 0;
2718 u32 _vmentry_control = 0;
2719
10166744 2720 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2721#ifdef CONFIG_X86_64
2722 CPU_BASED_CR8_LOAD_EXITING |
2723 CPU_BASED_CR8_STORE_EXITING |
2724#endif
d56f546d
SY		 2725 CPU_BASED_CR3_LOAD_EXITING |
2726 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2727 CPU_BASED_USE_IO_BITMAPS |
2728 CPU_BASED_MOV_DR_EXITING |
a7052897 2729 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2730 CPU_BASED_MWAIT_EXITING |
2731 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2732 CPU_BASED_INVLPG_EXITING |
2733 CPU_BASED_RDPMC_EXITING;
443381a8 2734
f78e0e2e 2735 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2736 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2738 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2739 &_cpu_based_exec_control) < 0)
002c7f7c 2740 return -EIO;
6e5d865c
YS		 2741#ifdef CONFIG_X86_64
2742 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2743 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2744 ~CPU_BASED_CR8_STORE_EXITING;
2745#endif
f78e0e2e 2746 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2747 min2 = 0;
2748 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2749 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2750 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2751 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2752 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2753 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2754 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2755 SECONDARY_EXEC_RDTSCP |
83d4c286 2756 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2757 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2758 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2759 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2760 if (adjust_vmx_controls(min2, opt2,
2761 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2762 &_cpu_based_2nd_exec_control) < 0)
2763 return -EIO;
2764 }
2765#ifndef CONFIG_X86_64
2766 if (!(_cpu_based_2nd_exec_control &
2767 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2768 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2769#endif
83d4c286
YZ		 2770
2771 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2772 _cpu_based_2nd_exec_control &= ~(
8d14695f 2773 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2774 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2775 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2776
d56f546d 2777 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2778 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2779 enabled */
5fff7d27
GN		 2780 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2781 CPU_BASED_CR3_STORE_EXITING |
2782 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2783 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2784 vmx_capability.ept, vmx_capability.vpid);
2785 }
1c3d14fe
YS		 2786
2787 min = 0;
2788#ifdef CONFIG_X86_64
2789 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2790#endif
a547c6db
YZ		 2791 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2792 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2793 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2794 &_vmexit_control) < 0)
002c7f7c 2795 return -EIO;
1c3d14fe 2796
01e439be
YZ		 2797 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2798 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2799 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2800 &_pin_based_exec_control) < 0)
2801 return -EIO;
2802
2803 if (!(_cpu_based_2nd_exec_control &
2804 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2805 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2806 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2807
468d472f
SY		 2808 min = 0;
2809 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2810 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2811 &_vmentry_control) < 0)
002c7f7c 2812 return -EIO;
6aa8b732 2813
c68876fd 2814 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2815
2816 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2817 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2818 return -EIO;
1c3d14fe
YS		 2819
2820#ifdef CONFIG_X86_64
2821 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2822 if (vmx_msr_high & (1u<<16))
002c7f7c 2823 return -EIO;
1c3d14fe
YS		 2824#endif
2825
2826 /* Require Write-Back (WB) memory type for VMCS accesses. */
2827 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2828 return -EIO;
1c3d14fe 2829
002c7f7c
YS		 2830 vmcs_conf->size = vmx_msr_high & 0x1fff;
2831 vmcs_conf->order = get_order(vmcs_config.size);
2832 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2833
002c7f7c
YS		 2834 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2835 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2836 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2837 vmcs_conf->vmexit_ctrl = _vmexit_control;
2838 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2839
110312c8
AK		 2840 cpu_has_load_ia32_efer =
2841 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2842 VM_ENTRY_LOAD_IA32_EFER)
2843 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2844 VM_EXIT_LOAD_IA32_EFER);
2845
8bf00a52
GN		 2846 cpu_has_load_perf_global_ctrl =
2847 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2848 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2849 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2850 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2851
2852 /*
2853 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2854 * but due to arrata below it can't be used. Workaround is to use
2855 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2856 *
2857 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2858 *
2859 * AAK155 (model 26)
2860 * AAP115 (model 30)
2861 * AAT100 (model 37)
2862 * BC86,AAY89,BD102 (model 44)
2863 * BA97 (model 46)
2864 *
2865 */
2866 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2867 switch (boot_cpu_data.x86_model) {
2868 case 26:
2869 case 30:
2870 case 37:
2871 case 44:
2872 case 46:
2873 cpu_has_load_perf_global_ctrl = false;
2874 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2875 "does not work properly. Using workaround\n");
2876 break;
2877 default:
2878 break;
2879 }
2880 }
2881
1c3d14fe 2882 return 0;
c68876fd 2883}
6aa8b732
AK		 2884
2885static struct vmcs *alloc_vmcs_cpu(int cpu)
2886{
2887 int node = cpu_to_node(cpu);
2888 struct page *pages;
2889 struct vmcs *vmcs;
2890
6484eb3e 2891 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2892 if (!pages)
2893 return NULL;
2894 vmcs = page_address(pages);
1c3d14fe
YS		 2895 memset(vmcs, 0, vmcs_config.size);
2896 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2897 return vmcs;
2898}
2899
2900static struct vmcs *alloc_vmcs(void)
2901{
d3b2c338 2902 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2903}
2904
2905static void free_vmcs(struct vmcs *vmcs)
2906{
1c3d14fe 2907 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2908}
2909
d462b819
NHE		 2910/*
2911 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2912 */
2913static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2914{
2915 if (!loaded_vmcs->vmcs)
2916 return;
2917 loaded_vmcs_clear(loaded_vmcs);
2918 free_vmcs(loaded_vmcs->vmcs);
2919 loaded_vmcs->vmcs = NULL;
2920}
2921
39959588 2922static void free_kvm_area(void)
6aa8b732
AK		 2923{
2924 int cpu;
2925
3230bb47 2926 for_each_possible_cpu(cpu) {
6aa8b732 2927 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2928 per_cpu(vmxarea, cpu) = NULL;
2929 }
6aa8b732
AK		 2930}
2931
6aa8b732
AK		 2932static __init int alloc_kvm_area(void)
2933{
2934 int cpu;
2935
3230bb47 2936 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2937 struct vmcs *vmcs;
2938
2939 vmcs = alloc_vmcs_cpu(cpu);
2940 if (!vmcs) {
2941 free_kvm_area();
2942 return -ENOMEM;
2943 }
2944
2945 per_cpu(vmxarea, cpu) = vmcs;
2946 }
2947 return 0;
2948}
2949
2950static __init int hardware_setup(void)
2951{
002c7f7c
YS		 2952 if (setup_vmcs_config(&vmcs_config) < 0)
2953 return -EIO;
50a37eb4
JR		 2954
2955 if (boot_cpu_has(X86_FEATURE_NX))
2956 kvm_enable_efer_bits(EFER_NX);
2957
93ba03c2
SY		 2958 if (!cpu_has_vmx_vpid())
2959 enable_vpid = 0;
abc4fc58
AG		 2960 if (!cpu_has_vmx_shadow_vmcs())
2961 enable_shadow_vmcs = 0;
93ba03c2 2962
4bc9b982
SY		 2963 if (!cpu_has_vmx_ept() ||
2964 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2965 enable_ept = 0;
3a624e29 2966 enable_unrestricted_guest = 0;
83c3a331 2967 enable_ept_ad_bits = 0;
3a624e29
NK		 2968 }
2969
83c3a331
XH		 2970 if (!cpu_has_vmx_ept_ad_bits())
2971 enable_ept_ad_bits = 0;
2972
3a624e29
NK		 2973 if (!cpu_has_vmx_unrestricted_guest())
2974 enable_unrestricted_guest = 0;
93ba03c2
SY		 2975
2976 if (!cpu_has_vmx_flexpriority())
2977 flexpriority_enabled = 0;
2978
95ba8273
GN		 2979 if (!cpu_has_vmx_tpr_shadow())
2980 kvm_x86_ops->update_cr8_intercept = NULL;
2981
54dee993
MT		 2982 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2983 kvm_disable_largepages();
2984
4b8d54f9
ZE		 2985 if (!cpu_has_vmx_ple())
2986 ple_gap = 0;
2987
01e439be
YZ		 2988 if (!cpu_has_vmx_apicv())
2989 enable_apicv = 0;
c7c9c56c 2990
01e439be 2991 if (enable_apicv)
c7c9c56c 2992 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2993 else {
c7c9c56c 2994 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2995 kvm_x86_ops->deliver_posted_interrupt = NULL;
2996 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2997 }
83d4c286 2998
b87a51ae
NHE		 2999 if (nested)
3000 nested_vmx_setup_ctls_msrs();
3001
6aa8b732
AK		 3002 return alloc_kvm_area();
3003}
3004
3005static __exit void hardware_unsetup(void)
3006{
3007 free_kvm_area();
3008}
3009
14168786
GN		 3010static bool emulation_required(struct kvm_vcpu *vcpu)
3011{
3012 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3013}
3014
91b0aa2c 3015static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3016 struct kvm_segment *save)
6aa8b732 3017{
d99e4152
GN		 3018 if (!emulate_invalid_guest_state) {
3019 /*
3020 * CS and SS RPL should be equal during guest entry according
3021 * to VMX spec, but in reality it is not always so. Since vcpu
3022 * is in the middle of the transition from real mode to
3023 * protected mode it is safe to assume that RPL 0 is a good
3024 * default value.
3025 */
3026 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3027 save->selector &= ~SELECTOR_RPL_MASK;
3028 save->dpl = save->selector & SELECTOR_RPL_MASK;
3029 save->s = 1;
6aa8b732 3030 }
d99e4152 3031 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3032}
3033
3034static void enter_pmode(struct kvm_vcpu *vcpu)
3035{
3036 unsigned long flags;
a89a8fb9 3037 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3038
d99e4152
GN		 3039 /*
3040 * Update real mode segment cache. It may be not up-to-date if sement
3041 * register was written while vcpu was in a guest mode.
3042 */
3043 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3044 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3045 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3046 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3047 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3048 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3049
7ffd92c5 3050 vmx->rmode.vm86_active = 0;
6aa8b732 3051
2fb92db1
AK		 3052 vmx_segment_cache_clear(vmx);
3053
f5f7b2fe 3054 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3055
3056 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3057 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3058 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3059 vmcs_writel(GUEST_RFLAGS, flags);
3060
66aee91a
RR		 3061 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3062 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3063
3064 update_exception_bitmap(vcpu);
3065
91b0aa2c
GN		 3066 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3067 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3068 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3069 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3070 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3071 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3072
3073 /* CPL is always 0 when CPU enters protected mode */
3074 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3075 vmx->cpl = 0;
6aa8b732
AK		 3076}
3077
f5f7b2fe 3078static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3079{
772e0318 3080 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3081 struct kvm_segment var = *save;
3082
3083 var.dpl = 0x3;
3084 if (seg == VCPU_SREG_CS)
3085 var.type = 0x3;
3086
3087 if (!emulate_invalid_guest_state) {
3088 var.selector = var.base >> 4;
3089 var.base = var.base & 0xffff0;
3090 var.limit = 0xffff;
3091 var.g = 0;
3092 var.db = 0;
3093 var.present = 1;
3094 var.s = 1;
3095 var.l = 0;
3096 var.unusable = 0;
3097 var.type = 0x3;
3098 var.avl = 0;
3099 if (save->base & 0xf)
3100 printk_once(KERN_WARNING "kvm: segment base is not "
3101 "paragraph aligned when entering "
3102 "protected mode (seg=%d)", seg);
3103 }
6aa8b732 3104
d99e4152
GN		 3105 vmcs_write16(sf->selector, var.selector);
3106 vmcs_write32(sf->base, var.base);
3107 vmcs_write32(sf->limit, var.limit);
3108 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3109}
3110
3111static void enter_rmode(struct kvm_vcpu *vcpu)
3112{
3113 unsigned long flags;
a89a8fb9 3114 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3115
f5f7b2fe
AK		 3116 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3117 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3118 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3119 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3120 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3121 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3122 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3123
7ffd92c5 3124 vmx->rmode.vm86_active = 1;
6aa8b732 3125
776e58ea
GN		 3126 /*
3127 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3128 * vcpu. Warn the user that an update is overdue.
776e58ea 3129 */
4918c6ca 3130 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3131 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3132 "called before entering vcpu\n");
776e58ea 3133
2fb92db1
AK		 3134 vmx_segment_cache_clear(vmx);
3135
4918c6ca 3136 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3137 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3138 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3139
3140 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3141 vmx->rmode.save_rflags = flags;
6aa8b732 3142
053de044 3143 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3144
3145 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3146 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3147 update_exception_bitmap(vcpu);
3148
d99e4152
GN		 3149 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3150 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3151 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3152 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3153 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3154 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3155
8668a3c4 3156 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3157}
3158
401d10de
AS		 3159static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3160{
3161 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3162 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3163
3164 if (!msr)
3165 return;
401d10de 3166
44ea2b17
AK		 3167 /*
3168 * Force kernel_gs_base reloading before EFER changes, as control
3169 * of this msr depends on is_long_mode().
3170 */
3171 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3172 vcpu->arch.efer = efer;
401d10de
AS		 3173 if (efer & EFER_LMA) {
3174 vmcs_write32(VM_ENTRY_CONTROLS,
3175 vmcs_read32(VM_ENTRY_CONTROLS) |
3176 VM_ENTRY_IA32E_MODE);
3177 msr->data = efer;
3178 } else {
3179 vmcs_write32(VM_ENTRY_CONTROLS,
3180 vmcs_read32(VM_ENTRY_CONTROLS) &
3181 ~VM_ENTRY_IA32E_MODE);
3182
3183 msr->data = efer & ~EFER_LME;
3184 }
3185 setup_msrs(vmx);
3186}
3187
05b3e0c2 3188#ifdef CONFIG_X86_64
6aa8b732
AK		 3189
3190static void enter_lmode(struct kvm_vcpu *vcpu)
3191{
3192 u32 guest_tr_ar;
3193
2fb92db1
AK		 3194 vmx_segment_cache_clear(to_vmx(vcpu));
3195
6aa8b732
AK		 3196 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3197 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3198 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3199 __func__);
6aa8b732
AK		 3200 vmcs_write32(GUEST_TR_AR_BYTES,
3201 (guest_tr_ar & ~AR_TYPE_MASK)
3202 | AR_TYPE_BUSY_64_TSS);
3203 }
da38f438 3204 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3205}
3206
3207static void exit_lmode(struct kvm_vcpu *vcpu)
3208{
6aa8b732
AK		 3209 vmcs_write32(VM_ENTRY_CONTROLS,
3210 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3211 & ~VM_ENTRY_IA32E_MODE);
da38f438 3212 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3213}
3214
3215#endif
3216
2384d2b3
SY		 3217static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3218{
b9d762fa 3219 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3220 if (enable_ept) {
3221 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3222 return;
4e1096d2 3223 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3224 }
2384d2b3
SY		 3225}
3226
e8467fda
AK		 3227static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3228{
3229 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3230
3231 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3232 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3233}
3234
aff48baa
AK		 3235static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3236{
3237 if (enable_ept && is_paging(vcpu))
3238 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3239 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3240}
3241
25c4c276 3242static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3243{
fc78f519
AK		 3244 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3245
3246 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3247 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3248}
3249
1439442c
SY		 3250static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3251{
6de4f3ad
AK		 3252 if (!test_bit(VCPU_EXREG_PDPTR,
3253 (unsigned long *)&vcpu->arch.regs_dirty))
3254 return;
3255
1439442c 3256 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3257 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3258 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3259 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3260 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3261 }
3262}
3263
8f5d549f
AK		 3264static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3265{
3266 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3267 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3268 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3269 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3270 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3271 }
6de4f3ad
AK		 3272
3273 __set_bit(VCPU_EXREG_PDPTR,
3274 (unsigned long *)&vcpu->arch.regs_avail);
3275 __set_bit(VCPU_EXREG_PDPTR,
3276 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3277}
3278
5e1746d6 3279static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3280
3281static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3282 unsigned long cr0,
3283 struct kvm_vcpu *vcpu)
3284{
5233dd51
MT		 3285 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3286 vmx_decache_cr3(vcpu);
1439442c
SY		 3287 if (!(cr0 & X86_CR0_PG)) {
3288 /* From paging/starting to nonpaging */
3289 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3290 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3291 (CPU_BASED_CR3_LOAD_EXITING |
3292 CPU_BASED_CR3_STORE_EXITING));
3293 vcpu->arch.cr0 = cr0;
fc78f519 3294 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3295 } else if (!is_paging(vcpu)) {
3296 /* From nonpaging to paging */
3297 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3298 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3299 ~(CPU_BASED_CR3_LOAD_EXITING |
3300 CPU_BASED_CR3_STORE_EXITING));
3301 vcpu->arch.cr0 = cr0;
fc78f519 3302 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3303 }
95eb84a7
SY		 3304
3305 if (!(cr0 & X86_CR0_WP))
3306 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3307}
3308
6aa8b732
AK		 3309static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3310{
7ffd92c5 3311 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3312 unsigned long hw_cr0;
3313
5037878e 3314 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3315 if (enable_unrestricted_guest)
5037878e 3316 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3317 else {
5037878e 3318 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3319
218e763f
GN		 3320 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3321 enter_pmode(vcpu);
6aa8b732 3322
218e763f
GN		 3323 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3324 enter_rmode(vcpu);
3325 }
6aa8b732 3326
05b3e0c2 3327#ifdef CONFIG_X86_64
f6801dff 3328 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3329 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3330 enter_lmode(vcpu);
707d92fa 3331 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3332 exit_lmode(vcpu);
3333 }
3334#endif
3335
089d034e 3336 if (enable_ept)
1439442c
SY		 3337 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3338
02daab21 3339 if (!vcpu->fpu_active)
81231c69 3340 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3341
6aa8b732 3342 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3343 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3344 vcpu->arch.cr0 = cr0;
14168786
GN		 3345
3346 /* depends on vcpu->arch.cr0 to be set to a new value */
3347 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3348}
3349
1439442c
SY		 3350static u64 construct_eptp(unsigned long root_hpa)
3351{
3352 u64 eptp;
3353
3354 /* TODO write the value reading from MSR */
3355 eptp = VMX_EPT_DEFAULT_MT |
3356 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3357 if (enable_ept_ad_bits)
3358 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3359 eptp |= (root_hpa & PAGE_MASK);
3360
3361 return eptp;
3362}
3363
6aa8b732
AK		 3364static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3365{
1439442c
SY		 3366 unsigned long guest_cr3;
3367 u64 eptp;
3368
3369 guest_cr3 = cr3;
089d034e 3370 if (enable_ept) {
1439442c
SY		 3371 eptp = construct_eptp(cr3);
3372 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3373 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3374 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3375 ept_load_pdptrs(vcpu);
1439442c
SY		 3376 }
3377
2384d2b3 3378 vmx_flush_tlb(vcpu);
1439442c 3379 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3380}
3381
5e1746d6 3382static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3383{
7ffd92c5 3384 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3385 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3386
5e1746d6
NHE		 3387 if (cr4 & X86_CR4_VMXE) {
3388 /*
3389 * To use VMXON (and later other VMX instructions), a guest
3390 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3391 * So basically the check on whether to allow nested VMX
3392 * is here.
3393 */
3394 if (!nested_vmx_allowed(vcpu))
3395 return 1;
1a0d74e6
JK		 3396 }
3397 if (to_vmx(vcpu)->nested.vmxon &&
3398 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3399 return 1;
3400
ad312c7c 3401 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3402 if (enable_ept) {
3403 if (!is_paging(vcpu)) {
3404 hw_cr4 &= ~X86_CR4_PAE;
3405 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3406 /*
3407 * SMEP is disabled if CPU is in non-paging mode in
3408 * hardware. However KVM always uses paging mode to
3409 * emulate guest non-paging mode with TDP.
3410 * To emulate this behavior, SMEP needs to be manually
3411 * disabled when guest switches to non-paging mode.
3412 */
3413 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3414 } else if (!(cr4 & X86_CR4_PAE)) {
3415 hw_cr4 &= ~X86_CR4_PAE;
3416 }
3417 }
1439442c
SY		 3418
3419 vmcs_writel(CR4_READ_SHADOW, cr4);
3420 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3421 return 0;
6aa8b732
AK		 3422}
3423
6aa8b732
AK		 3424static void vmx_get_segment(struct kvm_vcpu *vcpu,
3425 struct kvm_segment *var, int seg)
3426{
a9179499 3427 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3428 u32 ar;
3429
c6ad1153 3430 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3431 *var = vmx->rmode.segs[seg];
a9179499 3432 if (seg == VCPU_SREG_TR
2fb92db1 3433 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3434 return;
1390a28b
AK		 3435 var->base = vmx_read_guest_seg_base(vmx, seg);
3436 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3437 return;
a9179499 3438 }
2fb92db1
AK		 3439 var->base = vmx_read_guest_seg_base(vmx, seg);
3440 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3441 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3442 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3443 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3444 var->type = ar & 15;
3445 var->s = (ar >> 4) & 1;
3446 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3447 /*
3448 * Some userspaces do not preserve unusable property. Since usable
3449 * segment has to be present according to VMX spec we can use present
3450 * property to amend userspace bug by making unusable segment always
3451 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3452 * segment as unusable.
3453 */
3454 var->present = !var->unusable;
6aa8b732
AK		 3455 var->avl = (ar >> 12) & 1;
3456 var->l = (ar >> 13) & 1;
3457 var->db = (ar >> 14) & 1;
3458 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3459}
3460
a9179499
AK		 3461static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3462{
a9179499
AK		 3463 struct kvm_segment s;
3464
3465 if (to_vmx(vcpu)->rmode.vm86_active) {
3466 vmx_get_segment(vcpu, &s, seg);
3467 return s.base;
3468 }
2fb92db1 3469 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3470}
3471
b09408d0 3472static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3473{
b09408d0
MT		 3474 struct vcpu_vmx *vmx = to_vmx(vcpu);
3475
3eeb3288 3476 if (!is_protmode(vcpu))
2e4d2653
IE		 3477 return 0;
3478
f4c63e5d
AK		 3479 if (!is_long_mode(vcpu)
3480 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3481 return 3;
3482
69c73028
AK		 3483 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3484 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3485 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3486 }
d881e6f6
AK		 3487
3488 return vmx->cpl;
69c73028
AK		 3489}
3490
3491
653e3108 3492static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3493{
6aa8b732
AK		 3494 u32 ar;
3495
f0495f9b 3496 if (var->unusable || !var->present)
6aa8b732
AK		 3497 ar = 1 << 16;
3498 else {
3499 ar = var->type & 15;
3500 ar |= (var->s & 1) << 4;
3501 ar |= (var->dpl & 3) << 5;
3502 ar |= (var->present & 1) << 7;
3503 ar |= (var->avl & 1) << 12;
3504 ar |= (var->l & 1) << 13;
3505 ar |= (var->db & 1) << 14;
3506 ar |= (var->g & 1) << 15;
3507 }
653e3108
AK		 3508
3509 return ar;
3510}
3511
3512static void vmx_set_segment(struct kvm_vcpu *vcpu,
3513 struct kvm_segment *var, int seg)
3514{
7ffd92c5 3515 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3516 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3517
2fb92db1 3518 vmx_segment_cache_clear(vmx);
2f143240
GN		 3519 if (seg == VCPU_SREG_CS)
3520 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3521
1ecd50a9
GN		 3522 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3523 vmx->rmode.segs[seg] = *var;
3524 if (seg == VCPU_SREG_TR)
3525 vmcs_write16(sf->selector, var->selector);
3526 else if (var->s)
3527 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3528 goto out;
653e3108 3529 }
1ecd50a9 3530
653e3108
AK		 3531 vmcs_writel(sf->base, var->base);
3532 vmcs_write32(sf->limit, var->limit);
3533 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3534
3535 /*
3536 * Fix the "Accessed" bit in AR field of segment registers for older
3537 * qemu binaries.
3538 * IA32 arch specifies that at the time of processor reset the
3539 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3540 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3541 * state vmexit when "unrestricted guest" mode is turned on.
3542 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3543 * tree. Newer qemu binaries with that qemu fix would not need this
3544 * kvm hack.
3545 */
3546 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3547 var->type |= 0x1; /* Accessed */
3a624e29 3548
f924d66d 3549 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3550
3551out:
14168786 3552 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3553}
3554
6aa8b732
AK		 3555static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3556{
2fb92db1 3557 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3558
3559 *db = (ar >> 14) & 1;
3560 *l = (ar >> 13) & 1;
3561}
3562
89a27f4d 3563static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3564{
89a27f4d
GN		 3565 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3566 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3567}
3568
89a27f4d 3569static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3570{
89a27f4d
GN		 3571 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3572 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3573}
3574
89a27f4d 3575static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3576{
89a27f4d
GN		 3577 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3578 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3579}
3580
89a27f4d 3581static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3582{
89a27f4d
GN		 3583 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3584 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3585}
3586
648dfaa7
MG		 3587static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3588{
3589 struct kvm_segment var;
3590 u32 ar;
3591
3592 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3593 var.dpl = 0x3;
0647f4aa
GN		 3594 if (seg == VCPU_SREG_CS)
3595 var.type = 0x3;
648dfaa7
MG		 3596 ar = vmx_segment_access_rights(&var);
3597
3598 if (var.base != (var.selector << 4))
3599 return false;
89efbed0 3600 if (var.limit != 0xffff)
648dfaa7 3601 return false;
07f42f5f 3602 if (ar != 0xf3)
648dfaa7
MG		 3603 return false;
3604
3605 return true;
3606}
3607
3608static bool code_segment_valid(struct kvm_vcpu *vcpu)
3609{
3610 struct kvm_segment cs;
3611 unsigned int cs_rpl;
3612
3613 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3614 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3615
1872a3f4
AK		 3616 if (cs.unusable)
3617 return false;
648dfaa7
MG		 3618 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3619 return false;
3620 if (!cs.s)
3621 return false;
1872a3f4 3622 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3623 if (cs.dpl > cs_rpl)
3624 return false;
1872a3f4 3625 } else {
648dfaa7
MG		 3626 if (cs.dpl != cs_rpl)
3627 return false;
3628 }
3629 if (!cs.present)
3630 return false;
3631
3632 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3633 return true;
3634}
3635
3636static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3637{
3638 struct kvm_segment ss;
3639 unsigned int ss_rpl;
3640
3641 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3642 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3643
1872a3f4
AK		 3644 if (ss.unusable)
3645 return true;
3646 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3647 return false;
3648 if (!ss.s)
3649 return false;
3650 if (ss.dpl != ss_rpl) /* DPL != RPL */
3651 return false;
3652 if (!ss.present)
3653 return false;
3654
3655 return true;
3656}
3657
3658static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3659{
3660 struct kvm_segment var;
3661 unsigned int rpl;
3662
3663 vmx_get_segment(vcpu, &var, seg);
3664 rpl = var.selector & SELECTOR_RPL_MASK;
3665
1872a3f4
AK		 3666 if (var.unusable)
3667 return true;
648dfaa7
MG		 3668 if (!var.s)
3669 return false;
3670 if (!var.present)
3671 return false;
3672 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3673 if (var.dpl < rpl) /* DPL < RPL */
3674 return false;
3675 }
3676
3677 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3678 * rights flags
3679 */
3680 return true;
3681}
3682
3683static bool tr_valid(struct kvm_vcpu *vcpu)
3684{
3685 struct kvm_segment tr;
3686
3687 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3688
1872a3f4
AK		 3689 if (tr.unusable)
3690 return false;
648dfaa7
MG		 3691 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3692 return false;
1872a3f4 3693 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3694 return false;
3695 if (!tr.present)
3696 return false;
3697
3698 return true;
3699}
3700
3701static bool ldtr_valid(struct kvm_vcpu *vcpu)
3702{
3703 struct kvm_segment ldtr;
3704
3705 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3706
1872a3f4
AK		 3707 if (ldtr.unusable)
3708 return true;
648dfaa7
MG		 3709 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3710 return false;
3711 if (ldtr.type != 2)
3712 return false;
3713 if (!ldtr.present)
3714 return false;
3715
3716 return true;
3717}
3718
3719static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3720{
3721 struct kvm_segment cs, ss;
3722
3723 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3724 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3725
3726 return ((cs.selector & SELECTOR_RPL_MASK) ==
3727 (ss.selector & SELECTOR_RPL_MASK));
3728}
3729
3730/*
3731 * Check if guest state is valid. Returns true if valid, false if
3732 * not.
3733 * We assume that registers are always usable
3734 */
3735static bool guest_state_valid(struct kvm_vcpu *vcpu)
3736{
c5e97c80
GN		 3737 if (enable_unrestricted_guest)
3738 return true;
3739
648dfaa7 3740 /* real mode guest state checks */
f13882d8 3741 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3742 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3743 return false;
3744 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3745 return false;
3746 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3747 return false;
3748 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3749 return false;
3750 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3751 return false;
3752 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3753 return false;
3754 } else {
3755 /* protected mode guest state checks */
3756 if (!cs_ss_rpl_check(vcpu))
3757 return false;
3758 if (!code_segment_valid(vcpu))
3759 return false;
3760 if (!stack_segment_valid(vcpu))
3761 return false;
3762 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3763 return false;
3764 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3765 return false;
3766 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3767 return false;
3768 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3769 return false;
3770 if (!tr_valid(vcpu))
3771 return false;
3772 if (!ldtr_valid(vcpu))
3773 return false;
3774 }
3775 /* TODO:
3776 * - Add checks on RIP
3777 * - Add checks on RFLAGS
3778 */
3779
3780 return true;
3781}
3782
d77c26fc 3783static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3784{
40dcaa9f 3785 gfn_t fn;
195aefde 3786 u16 data = 0;
40dcaa9f 3787 int r, idx, ret = 0;
6aa8b732 3788
40dcaa9f 3789 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3790 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3791 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3792 if (r < 0)
10589a46 3793 goto out;
195aefde 3794 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3795 r = kvm_write_guest_page(kvm, fn++, &data,
3796 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3797 if (r < 0)
10589a46 3798 goto out;
195aefde
IE		 3799 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3800 if (r < 0)
10589a46 3801 goto out;
195aefde
IE		 3802 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3803 if (r < 0)
10589a46 3804 goto out;
195aefde 3805 data = ~0;
10589a46
MT		 3806 r = kvm_write_guest_page(kvm, fn, &data,
3807 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3808 sizeof(u8));
195aefde 3809 if (r < 0)
10589a46
MT		 3810 goto out;
3811
3812 ret = 1;
3813out:
40dcaa9f 3814 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3815 return ret;
6aa8b732
AK		 3816}
3817
b7ebfb05
SY		 3818static int init_rmode_identity_map(struct kvm *kvm)
3819{
40dcaa9f 3820 int i, idx, r, ret;
b7ebfb05
SY		 3821 pfn_t identity_map_pfn;
3822 u32 tmp;
3823
089d034e 3824 if (!enable_ept)
b7ebfb05
SY		 3825 return 1;
3826 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3827 printk(KERN_ERR "EPT: identity-mapping pagetable "
3828 "haven't been allocated!\n");
3829 return 0;
3830 }
3831 if (likely(kvm->arch.ept_identity_pagetable_done))
3832 return 1;
3833 ret = 0;
b927a3ce 3834 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3835 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3836 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3837 if (r < 0)
3838 goto out;
3839 /* Set up identity-mapping pagetable for EPT in real mode */
3840 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3841 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3842 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3843 r = kvm_write_guest_page(kvm, identity_map_pfn,
3844 &tmp, i * sizeof(tmp), sizeof(tmp));
3845 if (r < 0)
3846 goto out;
3847 }
3848 kvm->arch.ept_identity_pagetable_done = true;
3849 ret = 1;
3850out:
40dcaa9f 3851 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3852 return ret;
3853}
3854
6aa8b732
AK		 3855static void seg_setup(int seg)
3856{
772e0318 3857 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3858 unsigned int ar;
6aa8b732
AK		 3859
3860 vmcs_write16(sf->selector, 0);
3861 vmcs_writel(sf->base, 0);
3862 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3863 ar = 0x93;
3864 if (seg == VCPU_SREG_CS)
3865 ar |= 0x08; /* code segment */
3a624e29
NK		 3866
3867 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3868}
3869
f78e0e2e
SY		 3870static int alloc_apic_access_page(struct kvm *kvm)
3871{
4484141a 3872 struct page *page;
f78e0e2e
SY		 3873 struct kvm_userspace_memory_region kvm_userspace_mem;
3874 int r = 0;
3875
79fac95e 3876 mutex_lock(&kvm->slots_lock);
bfc6d222 3877 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3878 goto out;
3879 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3880 kvm_userspace_mem.flags = 0;
3881 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3882 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3883 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3884 if (r)
3885 goto out;
72dc67a6 3886
4484141a
XG		 3887 page = gfn_to_page(kvm, 0xfee00);
3888 if (is_error_page(page)) {
3889 r = -EFAULT;
3890 goto out;
3891 }
3892
3893 kvm->arch.apic_access_page = page;
f78e0e2e 3894out:
79fac95e 3895 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3896 return r;
3897}
3898
b7ebfb05
SY		 3899static int alloc_identity_pagetable(struct kvm *kvm)
3900{
4484141a 3901 struct page *page;
b7ebfb05
SY		 3902 struct kvm_userspace_memory_region kvm_userspace_mem;
3903 int r = 0;
3904
79fac95e 3905 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3906 if (kvm->arch.ept_identity_pagetable)
3907 goto out;
3908 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3909 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3910 kvm_userspace_mem.guest_phys_addr =
3911 kvm->arch.ept_identity_map_addr;
b7ebfb05 3912 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3913 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3914 if (r)
3915 goto out;
3916
4484141a
XG		 3917 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3918 if (is_error_page(page)) {
3919 r = -EFAULT;
3920 goto out;
3921 }
3922
3923 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3924out:
79fac95e 3925 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3926 return r;
3927}
3928
2384d2b3
SY		 3929static void allocate_vpid(struct vcpu_vmx *vmx)
3930{
3931 int vpid;
3932
3933 vmx->vpid = 0;
919818ab 3934 if (!enable_vpid)
2384d2b3
SY		 3935 return;
3936 spin_lock(&vmx_vpid_lock);
3937 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3938 if (vpid < VMX_NR_VPIDS) {
3939 vmx->vpid = vpid;
3940 __set_bit(vpid, vmx_vpid_bitmap);
3941 }
3942 spin_unlock(&vmx_vpid_lock);
3943}
3944
cdbecfc3
LJ		 3945static void free_vpid(struct vcpu_vmx *vmx)
3946{
3947 if (!enable_vpid)
3948 return;
3949 spin_lock(&vmx_vpid_lock);
3950 if (vmx->vpid != 0)
3951 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3952 spin_unlock(&vmx_vpid_lock);
3953}
3954
8d14695f
YZ		 3955#define MSR_TYPE_R 1
3956#define MSR_TYPE_W 2
3957static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3958 u32 msr, int type)
25c5f225 3959{
3e7c73e9 3960 int f = sizeof(unsigned long);
25c5f225
SY		 3961
3962 if (!cpu_has_vmx_msr_bitmap())
3963 return;
3964
3965 /*
3966 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3967 * have the write-low and read-high bitmap offsets the wrong way round.
3968 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3969 */
25c5f225 3970 if (msr <= 0x1fff) {
8d14695f
YZ		 3971 if (type & MSR_TYPE_R)
3972 /* read-low */
3973 __clear_bit(msr, msr_bitmap + 0x000 / f);
3974
3975 if (type & MSR_TYPE_W)
3976 /* write-low */
3977 __clear_bit(msr, msr_bitmap + 0x800 / f);
3978
25c5f225
SY		 3979 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3980 msr &= 0x1fff;
8d14695f
YZ		 3981 if (type & MSR_TYPE_R)
3982 /* read-high */
3983 __clear_bit(msr, msr_bitmap + 0x400 / f);
3984
3985 if (type & MSR_TYPE_W)
3986 /* write-high */
3987 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3988
3989 }
3990}
3991
3992static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3993 u32 msr, int type)
3994{
3995 int f = sizeof(unsigned long);
3996
3997 if (!cpu_has_vmx_msr_bitmap())
3998 return;
3999
4000 /*
4001 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4002 * have the write-low and read-high bitmap offsets the wrong way round.
4003 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4004 */
4005 if (msr <= 0x1fff) {
4006 if (type & MSR_TYPE_R)
4007 /* read-low */
4008 __set_bit(msr, msr_bitmap + 0x000 / f);
4009
4010 if (type & MSR_TYPE_W)
4011 /* write-low */
4012 __set_bit(msr, msr_bitmap + 0x800 / f);
4013
4014 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4015 msr &= 0x1fff;
4016 if (type & MSR_TYPE_R)
4017 /* read-high */
4018 __set_bit(msr, msr_bitmap + 0x400 / f);
4019
4020 if (type & MSR_TYPE_W)
4021 /* write-high */
4022 __set_bit(msr, msr_bitmap + 0xc00 / f);
4023
25c5f225 4024 }
25c5f225
SY		 4025}
4026
5897297b
AK		 4027static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4028{
4029 if (!longmode_only)
8d14695f
YZ		 4030 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4031 msr, MSR_TYPE_R | MSR_TYPE_W);
4032 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4033 msr, MSR_TYPE_R | MSR_TYPE_W);
4034}
4035
4036static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4037{
4038 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4039 msr, MSR_TYPE_R);
4040 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4041 msr, MSR_TYPE_R);
4042}
4043
4044static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4045{
4046 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4047 msr, MSR_TYPE_R);
4048 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4049 msr, MSR_TYPE_R);
4050}
4051
4052static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4053{
4054 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4055 msr, MSR_TYPE_W);
4056 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4057 msr, MSR_TYPE_W);
5897297b
AK		 4058}
4059
01e439be
YZ		 4060static int vmx_vm_has_apicv(struct kvm *kvm)
4061{
4062 return enable_apicv && irqchip_in_kernel(kvm);
4063}
4064
a20ed54d
YZ		 4065/*
4066 * Send interrupt to vcpu via posted interrupt way.
4067 * 1. If target vcpu is running(non-root mode), send posted interrupt
4068 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4069 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4070 * interrupt from PIR in next vmentry.
4071 */
4072static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4073{
4074 struct vcpu_vmx *vmx = to_vmx(vcpu);
4075 int r;
4076
4077 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4078 return;
4079
4080 r = pi_test_and_set_on(&vmx->pi_desc);
4081 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4082#ifdef CONFIG_SMP
a20ed54d
YZ		 4083 if (!r && (vcpu->mode == IN_GUEST_MODE))
4084 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4085 POSTED_INTR_VECTOR);
4086 else
6ffbbbba 4087#endif
a20ed54d
YZ		 4088 kvm_vcpu_kick(vcpu);
4089}
4090
4091static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4092{
4093 struct vcpu_vmx *vmx = to_vmx(vcpu);
4094
4095 if (!pi_test_and_clear_on(&vmx->pi_desc))
4096 return;
4097
4098 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4099}
4100
4101static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4102{
4103 return;
4104}
4105
a3a8ff8e
NHE		 4106/*
4107 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4108 * will not change in the lifetime of the guest.
4109 * Note that host-state that does change is set elsewhere. E.g., host-state
4110 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4111 */
a547c6db 4112static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4113{
4114 u32 low32, high32;
4115 unsigned long tmpl;
4116 struct desc_ptr dt;
4117
b1a74bf8 4118 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4119 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4120 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4121
4122 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4123#ifdef CONFIG_X86_64
4124 /*
4125 * Load null selectors, so we can avoid reloading them in
4126 * __vmx_load_host_state(), in case userspace uses the null selectors
4127 * too (the expected case).
4128 */
4129 vmcs_write16(HOST_DS_SELECTOR, 0);
4130 vmcs_write16(HOST_ES_SELECTOR, 0);
4131#else
a3a8ff8e
NHE		 4132 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4133 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4134#endif
a3a8ff8e
NHE		 4135 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4136 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4137
4138 native_store_idt(&dt);
4139 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4140 vmx->host_idt_base = dt.address;
a3a8ff8e 4141
83287ea4 4142 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4143
4144 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4145 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4146 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4147 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4148
4149 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4150 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4151 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4152 }
4153}
4154
bf8179a0
NHE		 4155static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4156{
4157 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4158 if (enable_ept)
4159 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4160 if (is_guest_mode(&vmx->vcpu))
4161 vmx->vcpu.arch.cr4_guest_owned_bits &=
4162 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4163 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4164}
4165
01e439be
YZ		 4166static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4167{
4168 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4169
4170 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4171 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4172 return pin_based_exec_ctrl;
4173}
4174
bf8179a0
NHE		 4175static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4176{
4177 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4178 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4179 exec_control &= ~CPU_BASED_TPR_SHADOW;
4180#ifdef CONFIG_X86_64
4181 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4182 CPU_BASED_CR8_LOAD_EXITING;
4183#endif
4184 }
4185 if (!enable_ept)
4186 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4187 CPU_BASED_CR3_LOAD_EXITING |
4188 CPU_BASED_INVLPG_EXITING;
4189 return exec_control;
4190}
4191
4192static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4193{
4194 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4195 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4196 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4197 if (vmx->vpid == 0)
4198 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4199 if (!enable_ept) {
4200 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4201 enable_unrestricted_guest = 0;
ad756a16
MJ		 4202 /* Enable INVPCID for non-ept guests may cause performance regression. */
4203 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4204 }
4205 if (!enable_unrestricted_guest)
4206 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4207 if (!ple_gap)
4208 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4209 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4210 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4211 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4212 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4213 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4214 (handle_vmptrld).
4215 We can NOT enable shadow_vmcs here because we don't have yet
4216 a current VMCS12
4217 */
4218 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4219 return exec_control;
4220}
4221
ce88decf
XG		 4222static void ept_set_mmio_spte_mask(void)
4223{
4224 /*
4225 * EPT Misconfigurations can be generated if the value of bits 2:0
4226 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4227 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4228 * spte.
4229 */
885032b9 4230 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4231}
4232
6aa8b732
AK		 4233/*
4234 * Sets up the vmcs for emulated real mode.
4235 */
8b9cf98c 4236static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4237{
2e4ce7f5 4238#ifdef CONFIG_X86_64
6aa8b732 4239 unsigned long a;
2e4ce7f5 4240#endif
6aa8b732 4241 int i;
6aa8b732 4242
6aa8b732 4243 /* I/O */
3e7c73e9
AK		 4244 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4245 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4246
4607c2d7
AG		 4247 if (enable_shadow_vmcs) {
4248 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4249 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4250 }
25c5f225 4251 if (cpu_has_vmx_msr_bitmap())
5897297b 4252 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4253
6aa8b732
AK		 4254 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4255
6aa8b732 4256 /* Control */
01e439be 4257 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4258
bf8179a0 4259 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4260
83ff3b9d 4261 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4262 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4263 vmx_secondary_exec_control(vmx));
83ff3b9d 4264 }
f78e0e2e 4265
01e439be 4266 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4267 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4268 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4269 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4270 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4271
4272 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4273
4274 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4275 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4276 }
4277
4b8d54f9
ZE		 4278 if (ple_gap) {
4279 vmcs_write32(PLE_GAP, ple_gap);
4280 vmcs_write32(PLE_WINDOW, ple_window);
4281 }
4282
c3707958
XG		 4283 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4284 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4285 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4286
9581d442
AK		 4287 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4288 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4289 vmx_set_constant_host_state(vmx);
05b3e0c2 4290#ifdef CONFIG_X86_64
6aa8b732
AK		 4291 rdmsrl(MSR_FS_BASE, a);
4292 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4293 rdmsrl(MSR_GS_BASE, a);
4294 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4295#else
4296 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4297 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4298#endif
4299
2cc51560
ED		 4300 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4301 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4302 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4303 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4304 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4305
468d472f 4306 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4307 u32 msr_low, msr_high;
4308 u64 host_pat;
468d472f
SY		 4309 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4310 host_pat = msr_low | ((u64) msr_high << 32);
4311 /* Write the default value follow host pat */
4312 vmcs_write64(GUEST_IA32_PAT, host_pat);
4313 /* Keep arch.pat sync with GUEST_IA32_PAT */
4314 vmx->vcpu.arch.pat = host_pat;
4315 }
4316
6aa8b732
AK		 4317 for (i = 0; i < NR_VMX_MSR; ++i) {
4318 u32 index = vmx_msr_index[i];
4319 u32 data_low, data_high;
a2fa3e9f 4320 int j = vmx->nmsrs;
6aa8b732
AK		 4321
4322 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4323 continue;
432bd6cb
AK		 4324 if (wrmsr_safe(index, data_low, data_high) < 0)
4325 continue;
26bb0981
AK		 4326 vmx->guest_msrs[j].index = i;
4327 vmx->guest_msrs[j].data = 0;
d5696725 4328 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4329 ++vmx->nmsrs;
6aa8b732 4330 }
6aa8b732 4331
1c3d14fe 4332 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4333
4334 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4335 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4336
e00c8cf2 4337 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4338 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4339
4340 return 0;
4341}
4342
57f252f2 4343static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4344{
4345 struct vcpu_vmx *vmx = to_vmx(vcpu);
4346 u64 msr;
e00c8cf2 4347
7ffd92c5 4348 vmx->rmode.vm86_active = 0;
e00c8cf2 4349
3b86cd99
JK		 4350 vmx->soft_vnmi_blocked = 0;
4351
ad312c7c 4352 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4353 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4354 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4355 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4356 msr |= MSR_IA32_APICBASE_BSP;
4357 kvm_set_apic_base(&vmx->vcpu, msr);
4358
2fb92db1
AK		 4359 vmx_segment_cache_clear(vmx);
4360
5706be0d 4361 seg_setup(VCPU_SREG_CS);
66450a21 4362 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4363 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4364
4365 seg_setup(VCPU_SREG_DS);
4366 seg_setup(VCPU_SREG_ES);
4367 seg_setup(VCPU_SREG_FS);
4368 seg_setup(VCPU_SREG_GS);
4369 seg_setup(VCPU_SREG_SS);
4370
4371 vmcs_write16(GUEST_TR_SELECTOR, 0);
4372 vmcs_writel(GUEST_TR_BASE, 0);
4373 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4374 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4375
4376 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4377 vmcs_writel(GUEST_LDTR_BASE, 0);
4378 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4379 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4380
4381 vmcs_write32(GUEST_SYSENTER_CS, 0);
4382 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4383 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4384
4385 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4386 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4387
e00c8cf2
AK		 4388 vmcs_writel(GUEST_GDTR_BASE, 0);
4389 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4390
4391 vmcs_writel(GUEST_IDTR_BASE, 0);
4392 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4393
443381a8 4394 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4395 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4396 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4397
e00c8cf2
AK		 4398 /* Special registers */
4399 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4400
4401 setup_msrs(vmx);
4402
6aa8b732
AK		 4403 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4404
f78e0e2e
SY		 4405 if (cpu_has_vmx_tpr_shadow()) {
4406 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4407 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4408 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4409 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4410 vmcs_write32(TPR_THRESHOLD, 0);
4411 }
4412
4413 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4414 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4415 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4416
01e439be
YZ		 4417 if (vmx_vm_has_apicv(vcpu->kvm))
4418 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4419
2384d2b3
SY		 4420 if (vmx->vpid != 0)
4421 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4422
fa40052c 4423 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4424 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4425 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4426 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4427 vmx_fpu_activate(&vmx->vcpu);
4428 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4429
b9d762fa 4430 vpid_sync_context(vmx);
6aa8b732
AK		 4431}
4432
b6f1250e
NHE		 4433/*
4434 * In nested virtualization, check if L1 asked to exit on external interrupts.
4435 * For most existing hypervisors, this will always return true.
4436 */
4437static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4438{
4439 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4440 PIN_BASED_EXT_INTR_MASK;
4441}
4442
ea8ceb83
JK		 4443static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4444{
4445 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4446 PIN_BASED_NMI_EXITING;
4447}
4448
730dca42 4449static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4450{
4451 u32 cpu_based_vm_exec_control;
730dca42
JK		 4452
4453 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4454 /*
4455 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4456 * inject to L1 now because L2 must run. The caller will have
4457 * to make L2 exit right after entry, so we can inject to L1
4458 * more promptly.
b6f1250e 4459 */
730dca42 4460 return -EBUSY;
3b86cd99
JK		 4461
4462 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4463 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4464 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4465 return 0;
3b86cd99
JK		 4466}
4467
03b28f81 4468static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4469{
4470 u32 cpu_based_vm_exec_control;
4471
03b28f81
JK		 4472 if (!cpu_has_virtual_nmis())
4473 return enable_irq_window(vcpu);
4474
4475 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4476 return enable_irq_window(vcpu);
3b86cd99
JK		 4477
4478 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4479 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4480 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4481 return 0;
3b86cd99
JK		 4482}
4483
66fd3f7f 4484static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4485{
9c8cba37 4486 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4487 uint32_t intr;
4488 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4489
229456fc 4490 trace_kvm_inj_virq(irq);
2714d1d3 4491
fa89a817 4492 ++vcpu->stat.irq_injections;
7ffd92c5 4493 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4494 int inc_eip = 0;
4495 if (vcpu->arch.interrupt.soft)
4496 inc_eip = vcpu->arch.event_exit_inst_len;
4497 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4498 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4499 return;
4500 }
66fd3f7f
GN		 4501 intr = irq | INTR_INFO_VALID_MASK;
4502 if (vcpu->arch.interrupt.soft) {
4503 intr |= INTR_TYPE_SOFT_INTR;
4504 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4505 vmx->vcpu.arch.event_exit_inst_len);
4506 } else
4507 intr |= INTR_TYPE_EXT_INTR;
4508 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4509}
4510
f08864b4
SY		 4511static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4512{
66a5a347
JK		 4513 struct vcpu_vmx *vmx = to_vmx(vcpu);
4514
0b6ac343
NHE		 4515 if (is_guest_mode(vcpu))
4516 return;
4517
3b86cd99
JK		 4518 if (!cpu_has_virtual_nmis()) {
4519 /*
4520 * Tracking the NMI-blocked state in software is built upon
4521 * finding the next open IRQ window. This, in turn, depends on
4522 * well-behaving guests: They have to keep IRQs disabled at
4523 * least as long as the NMI handler runs. Otherwise we may
4524 * cause NMI nesting, maybe breaking the guest. But as this is
4525 * highly unlikely, we can live with the residual risk.
4526 */
4527 vmx->soft_vnmi_blocked = 1;
4528 vmx->vnmi_blocked_time = 0;
4529 }
4530
487b391d 4531 ++vcpu->stat.nmi_injections;
9d58b931 4532 vmx->nmi_known_unmasked = false;
7ffd92c5 4533 if (vmx->rmode.vm86_active) {
71f9833b 4534 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4535 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4536 return;
4537 }
f08864b4
SY		 4538 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4539 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4540}
4541
3cfc3092
JK		 4542static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4543{
4544 if (!cpu_has_virtual_nmis())
4545 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4546 if (to_vmx(vcpu)->nmi_known_unmasked)
4547 return false;
c332c83a 4548 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4549}
4550
4551static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4552{
4553 struct vcpu_vmx *vmx = to_vmx(vcpu);
4554
4555 if (!cpu_has_virtual_nmis()) {
4556 if (vmx->soft_vnmi_blocked != masked) {
4557 vmx->soft_vnmi_blocked = masked;
4558 vmx->vnmi_blocked_time = 0;
4559 }
4560 } else {
9d58b931 4561 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4562 if (masked)
4563 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4564 GUEST_INTR_STATE_NMI);
4565 else
4566 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4567 GUEST_INTR_STATE_NMI);
4568 }
4569}
4570
2505dc9f
JK		 4571static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4572{
ea8ceb83
JK		 4573 if (is_guest_mode(vcpu)) {
4574 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4575
4576 if (to_vmx(vcpu)->nested.nested_run_pending)
4577 return 0;
4578 if (nested_exit_on_nmi(vcpu)) {
4579 nested_vmx_vmexit(vcpu);
4580 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4581 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4582 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4583 /*
4584 * The NMI-triggered VM exit counts as injection:
4585 * clear this one and block further NMIs.
4586 */
4587 vcpu->arch.nmi_pending = 0;
4588 vmx_set_nmi_mask(vcpu, true);
4589 return 0;
4590 }
4591 }
4592
2505dc9f
JK		 4593 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4594 return 0;
4595
4596 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4597 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4598 | GUEST_INTR_STATE_NMI));
4599}
4600
78646121
GN		 4601static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4602{
e8457c67 4603 if (is_guest_mode(vcpu)) {
51cfe38e 4604 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4605
4606 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4607 return 0;
e8457c67
JK		 4608 if (nested_exit_on_intr(vcpu)) {
4609 nested_vmx_vmexit(vcpu);
4610 vmcs12->vm_exit_reason =
4611 EXIT_REASON_EXTERNAL_INTERRUPT;
4612 vmcs12->vm_exit_intr_info = 0;
4613 /*
4614 * fall through to normal code, but now in L1, not L2
4615 */
4616 }
b6f1250e
NHE		 4617 }
4618
c4282df9
GN		 4619 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4620 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4621 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4622}
4623
cbc94022
IE		 4624static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4625{
4626 int ret;
4627 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4628 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4629 .guest_phys_addr = addr,
4630 .memory_size = PAGE_SIZE * 3,
4631 .flags = 0,
4632 };
4633
47ae31e2 4634 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4635 if (ret)
4636 return ret;
bfc6d222 4637 kvm->arch.tss_addr = addr;
93ea5388
GN		 4638 if (!init_rmode_tss(kvm))
4639 return -ENOMEM;
4640
cbc94022
IE		 4641 return 0;
4642}
4643
0ca1b4f4 4644static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4645{
77ab6db0 4646 switch (vec) {
77ab6db0 4647 case BP_VECTOR:
c573cd22
JK		 4648 /*
4649 * Update instruction length as we may reinject the exception
4650 * from user space while in guest debugging mode.
4651 */
4652 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4653 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4654 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4655 return false;
4656 /* fall through */
4657 case DB_VECTOR:
4658 if (vcpu->guest_debug &
4659 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4660 return false;
d0bfb940
JK		 4661 /* fall through */
4662 case DE_VECTOR:
77ab6db0
JK		 4663 case OF_VECTOR:
4664 case BR_VECTOR:
4665 case UD_VECTOR:
4666 case DF_VECTOR:
4667 case SS_VECTOR:
4668 case GP_VECTOR:
4669 case MF_VECTOR:
0ca1b4f4
GN		 4670 return true;
4671 break;
77ab6db0 4672 }
0ca1b4f4
GN		 4673 return false;
4674}
4675
4676static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4677 int vec, u32 err_code)
4678{
4679 /*
4680 * Instruction with address size override prefix opcode 0x67
4681 * Cause the #SS fault with 0 error code in VM86 mode.
4682 */
4683 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4684 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4685 if (vcpu->arch.halt_request) {
4686 vcpu->arch.halt_request = 0;
4687 return kvm_emulate_halt(vcpu);
4688 }
4689 return 1;
4690 }
4691 return 0;
4692 }
4693
4694 /*
4695 * Forward all other exceptions that are valid in real mode.
4696 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4697 * the required debugging infrastructure rework.
4698 */
4699 kvm_queue_exception(vcpu, vec);
4700 return 1;
6aa8b732
AK		 4701}
4702
a0861c02
AK		 4703/*
4704 * Trigger machine check on the host. We assume all the MSRs are already set up
4705 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4706 * We pass a fake environment to the machine check handler because we want
4707 * the guest to be always treated like user space, no matter what context
4708 * it used internally.
4709 */
4710static void kvm_machine_check(void)
4711{
4712#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4713 struct pt_regs regs = {
4714 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4715 .flags = X86_EFLAGS_IF,
4716 };
4717
4718 do_machine_check(&regs, 0);
4719#endif
4720}
4721
851ba692 4722static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4723{
4724 /* already handled by vcpu_run */
4725 return 1;
4726}
4727
851ba692 4728static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4729{
1155f76a 4730 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4731 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4732 u32 intr_info, ex_no, error_code;
42dbaa5a 4733 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4734 u32 vect_info;
4735 enum emulation_result er;
4736
1155f76a 4737 vect_info = vmx->idt_vectoring_info;
88786475 4738 intr_info = vmx->exit_intr_info;
6aa8b732 4739
a0861c02 4740 if (is_machine_check(intr_info))
851ba692 4741 return handle_machine_check(vcpu);
a0861c02 4742
e4a41889 4743 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4744 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4745
4746 if (is_no_device(intr_info)) {
5fd86fcf 4747 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4748 return 1;
4749 }
4750
7aa81cc0 4751 if (is_invalid_opcode(intr_info)) {
51d8b661 4752 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4753 if (er != EMULATE_DONE)
7ee5d940 4754 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4755 return 1;
4756 }
4757
6aa8b732 4758 error_code = 0;
2e11384c 4759 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4760 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4761
4762 /*
4763 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4764 * MMIO, it is better to report an internal error.
4765 * See the comments in vmx_handle_exit.
4766 */
4767 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4768 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4769 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4770 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4771 vcpu->run->internal.ndata = 2;
4772 vcpu->run->internal.data[0] = vect_info;
4773 vcpu->run->internal.data[1] = intr_info;
4774 return 0;
4775 }
4776
6aa8b732 4777 if (is_page_fault(intr_info)) {
1439442c 4778 /* EPT won't cause page fault directly */
cf3ace79 4779 BUG_ON(enable_ept);
6aa8b732 4780 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4781 trace_kvm_page_fault(cr2, error_code);
4782
3298b75c 4783 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4784 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4785 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4786 }
4787
d0bfb940 4788 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4789
4790 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4791 return handle_rmode_exception(vcpu, ex_no, error_code);
4792
42dbaa5a
JK		 4793 switch (ex_no) {
4794 case DB_VECTOR:
4795 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4796 if (!(vcpu->guest_debug &
4797 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4798 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4799 kvm_queue_exception(vcpu, DB_VECTOR);
4800 return 1;
4801 }
4802 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4803 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4804 /* fall through */
4805 case BP_VECTOR:
c573cd22
JK		 4806 /*
4807 * Update instruction length as we may reinject #BP from
4808 * user space while in guest debugging mode. Reading it for
4809 * #DB as well causes no harm, it is not used in that case.
4810 */
4811 vmx->vcpu.arch.event_exit_inst_len =
4812 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4813 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4814 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4815 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4816 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4817 break;
4818 default:
d0bfb940
JK		 4819 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4820 kvm_run->ex.exception = ex_no;
4821 kvm_run->ex.error_code = error_code;
42dbaa5a 4822 break;
6aa8b732 4823 }
6aa8b732
AK		 4824 return 0;
4825}
4826
851ba692 4827static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4828{
1165f5fe 4829 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4830 return 1;
4831}
4832
851ba692 4833static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4834{
851ba692 4835 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4836 return 0;
4837}
6aa8b732 4838
851ba692 4839static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4840{
bfdaab09 4841 unsigned long exit_qualification;
34c33d16 4842 int size, in, string;
039576c0 4843 unsigned port;
6aa8b732 4844
bfdaab09 4845 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4846 string = (exit_qualification & 16) != 0;
cf8f70bf 4847 in = (exit_qualification & 8) != 0;
e70669ab 4848
cf8f70bf 4849 ++vcpu->stat.io_exits;
e70669ab 4850
cf8f70bf 4851 if (string || in)
51d8b661 4852 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4853
cf8f70bf
GN		 4854 port = exit_qualification >> 16;
4855 size = (exit_qualification & 7) + 1;
e93f36bc 4856 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4857
4858 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4859}
4860
102d8325
IM		 4861static void
4862vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4863{
4864 /*
4865 * Patch in the VMCALL instruction:
4866 */
4867 hypercall[0] = 0x0f;
4868 hypercall[1] = 0x01;
4869 hypercall[2] = 0xc1;
102d8325
IM		 4870}
4871
0fa06071 4872/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4873static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4874{
eeadf9e7 4875 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4876 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4877 unsigned long orig_val = val;
4878
eeadf9e7
NHE		 4879 /*
4880 * We get here when L2 changed cr0 in a way that did not change
4881 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4882 * but did change L0 shadowed bits. So we first calculate the
4883 * effective cr0 value that L1 would like to write into the
4884 * hardware. It consists of the L2-owned bits from the new
4885 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4886 */
1a0d74e6
JK		 4887 val = (val & ~vmcs12->cr0_guest_host_mask) |
4888 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4889
4890 /* TODO: will have to take unrestricted guest mode into
4891 * account */
4892 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4893 return 1;
1a0d74e6
JK		 4894
4895 if (kvm_set_cr0(vcpu, val))
4896 return 1;
4897 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4898 return 0;
1a0d74e6
JK		 4899 } else {
4900 if (to_vmx(vcpu)->nested.vmxon &&
4901 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4902 return 1;
eeadf9e7 4903 return kvm_set_cr0(vcpu, val);
1a0d74e6 4904 }
eeadf9e7
NHE		 4905}
4906
4907static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4908{
4909 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4910 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4911 unsigned long orig_val = val;
4912
4913 /* analogously to handle_set_cr0 */
4914 val = (val & ~vmcs12->cr4_guest_host_mask) |
4915 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4916 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4917 return 1;
1a0d74e6 4918 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4919 return 0;
4920 } else
4921 return kvm_set_cr4(vcpu, val);
4922}
4923
4924/* called to set cr0 as approriate for clts instruction exit. */
4925static void handle_clts(struct kvm_vcpu *vcpu)
4926{
4927 if (is_guest_mode(vcpu)) {
4928 /*
4929 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4930 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4931 * just pretend it's off (also in arch.cr0 for fpu_activate).
4932 */
4933 vmcs_writel(CR0_READ_SHADOW,
4934 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4935 vcpu->arch.cr0 &= ~X86_CR0_TS;
4936 } else
4937 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4938}
4939
851ba692 4940static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4941{
229456fc 4942 unsigned long exit_qualification, val;
6aa8b732
AK		 4943 int cr;
4944 int reg;
49a9b07e 4945 int err;
6aa8b732 4946
bfdaab09 4947 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4948 cr = exit_qualification & 15;
4949 reg = (exit_qualification >> 8) & 15;
4950 switch ((exit_qualification >> 4) & 3) {
4951 case 0: /* mov to cr */
229456fc
MT		 4952 val = kvm_register_read(vcpu, reg);
4953 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4954 switch (cr) {
4955 case 0:
eeadf9e7 4956 err = handle_set_cr0(vcpu, val);
db8fcefa 4957 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4958 return 1;
4959 case 3:
2390218b 4960 err = kvm_set_cr3(vcpu, val);
db8fcefa 4961 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4962 return 1;
4963 case 4:
eeadf9e7 4964 err = handle_set_cr4(vcpu, val);
db8fcefa 4965 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4966 return 1;
0a5fff19
GN		 4967 case 8: {
4968 u8 cr8_prev = kvm_get_cr8(vcpu);
4969 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4970 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4971 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4972 if (irqchip_in_kernel(vcpu->kvm))
4973 return 1;
4974 if (cr8_prev <= cr8)
4975 return 1;
851ba692 4976 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4977 return 0;
4978 }
4b8073e4 4979 }
6aa8b732 4980 break;
25c4c276 4981 case 2: /* clts */
eeadf9e7 4982 handle_clts(vcpu);
4d4ec087 4983 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4984 skip_emulated_instruction(vcpu);
6b52d186 4985 vmx_fpu_activate(vcpu);
25c4c276 4986 return 1;
6aa8b732
AK		 4987 case 1: /*mov from cr*/
4988 switch (cr) {
4989 case 3:
9f8fe504
AK		 4990 val = kvm_read_cr3(vcpu);
4991 kvm_register_write(vcpu, reg, val);
4992 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4993 skip_emulated_instruction(vcpu);
4994 return 1;
4995 case 8:
229456fc
MT		 4996 val = kvm_get_cr8(vcpu);
4997 kvm_register_write(vcpu, reg, val);
4998 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4999 skip_emulated_instruction(vcpu);
5000 return 1;
5001 }
5002 break;
5003 case 3: /* lmsw */
a1f83a74 5004 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5005 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5006 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5007
5008 skip_emulated_instruction(vcpu);
5009 return 1;
5010 default:
5011 break;
5012 }
851ba692 5013 vcpu->run->exit_reason = 0;
a737f256 5014 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5015 (int)(exit_qualification >> 4) & 3, cr);
5016 return 0;
5017}
5018
851ba692 5019static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5020{
bfdaab09 5021 unsigned long exit_qualification;
6aa8b732
AK		 5022 int dr, reg;
5023
f2483415 5024 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5025 if (!kvm_require_cpl(vcpu, 0))
5026 return 1;
42dbaa5a
JK		 5027 dr = vmcs_readl(GUEST_DR7);
5028 if (dr & DR7_GD) {
5029 /*
5030 * As the vm-exit takes precedence over the debug trap, we
5031 * need to emulate the latter, either for the host or the
5032 * guest debugging itself.
5033 */
5034 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5035 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5036 vcpu->run->debug.arch.dr7 = dr;
5037 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5038 vmcs_readl(GUEST_CS_BASE) +
5039 vmcs_readl(GUEST_RIP);
851ba692
AK		 5040 vcpu->run->debug.arch.exception = DB_VECTOR;
5041 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5042 return 0;
5043 } else {
5044 vcpu->arch.dr7 &= ~DR7_GD;
5045 vcpu->arch.dr6 |= DR6_BD;
5046 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5047 kvm_queue_exception(vcpu, DB_VECTOR);
5048 return 1;
5049 }
5050 }
5051
bfdaab09 5052 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5053 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5054 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5055 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5056 unsigned long val;
5057 if (!kvm_get_dr(vcpu, dr, &val))
5058 kvm_register_write(vcpu, reg, val);
5059 } else
5060 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5061 skip_emulated_instruction(vcpu);
5062 return 1;
5063}
5064
020df079
GN		 5065static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5066{
5067 vmcs_writel(GUEST_DR7, val);
5068}
5069
851ba692 5070static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5071{
06465c5a
AK		 5072 kvm_emulate_cpuid(vcpu);
5073 return 1;
6aa8b732
AK		 5074}
5075
851ba692 5076static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5077{
ad312c7c 5078 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5079 u64 data;
5080
5081 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5082 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5083 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5084 return 1;
5085 }
5086
229456fc 5087 trace_kvm_msr_read(ecx, data);
2714d1d3 5088
6aa8b732 5089 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5090 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5091 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5092 skip_emulated_instruction(vcpu);
5093 return 1;
5094}
5095
851ba692 5096static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5097{
8fe8ab46 5098 struct msr_data msr;
ad312c7c
ZX		 5099 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5100 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5101 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5102
8fe8ab46
WA		 5103 msr.data = data;
5104 msr.index = ecx;
5105 msr.host_initiated = false;
5106 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5107 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5108 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5109 return 1;
5110 }
5111
59200273 5112 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5113 skip_emulated_instruction(vcpu);
5114 return 1;
5115}
5116
851ba692 5117static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5118{
3842d135 5119 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5120 return 1;
5121}
5122
851ba692 5123static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5124{
85f455f7
ED		 5125 u32 cpu_based_vm_exec_control;
5126
5127 /* clear pending irq */
5128 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5129 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5130 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5131
3842d135
AK		 5132 kvm_make_request(KVM_REQ_EVENT, vcpu);
5133
a26bf12a 5134 ++vcpu->stat.irq_window_exits;
2714d1d3 5135
c1150d8c
DL		 5136 /*
5137 * If the user space waits to inject interrupts, exit as soon as
5138 * possible
5139 */
8061823a 5140 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5141 vcpu->run->request_interrupt_window &&
8061823a 5142 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5143 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5144 return 0;
5145 }
6aa8b732
AK		 5146 return 1;
5147}
5148
851ba692 5149static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5150{
5151 skip_emulated_instruction(vcpu);
d3bef15f 5152 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5153}
5154
851ba692 5155static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5156{
510043da 5157 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5158 kvm_emulate_hypercall(vcpu);
5159 return 1;
c21415e8
IM		 5160}
5161
ec25d5e6
GN		 5162static int handle_invd(struct kvm_vcpu *vcpu)
5163{
51d8b661 5164 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5165}
5166
851ba692 5167static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5168{
f9c617f6 5169 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5170
5171 kvm_mmu_invlpg(vcpu, exit_qualification);
5172 skip_emulated_instruction(vcpu);
5173 return 1;
5174}
5175
fee84b07
AK		 5176static int handle_rdpmc(struct kvm_vcpu *vcpu)
5177{
5178 int err;
5179
5180 err = kvm_rdpmc(vcpu);
5181 kvm_complete_insn_gp(vcpu, err);
5182
5183 return 1;
5184}
5185
851ba692 5186static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5187{
5188 skip_emulated_instruction(vcpu);
f5f48ee1 5189 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5190 return 1;
5191}
5192
2acf923e
DC		 5193static int handle_xsetbv(struct kvm_vcpu *vcpu)
5194{
5195 u64 new_bv = kvm_read_edx_eax(vcpu);
5196 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5197
5198 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5199 skip_emulated_instruction(vcpu);
5200 return 1;
5201}
5202
851ba692 5203static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5204{
58fbbf26
KT		 5205 if (likely(fasteoi)) {
5206 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5207 int access_type, offset;
5208
5209 access_type = exit_qualification & APIC_ACCESS_TYPE;
5210 offset = exit_qualification & APIC_ACCESS_OFFSET;
5211 /*
5212 * Sane guest uses MOV to write EOI, with written value
5213 * not cared. So make a short-circuit here by avoiding
5214 * heavy instruction emulation.
5215 */
5216 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5217 (offset == APIC_EOI)) {
5218 kvm_lapic_set_eoi(vcpu);
5219 skip_emulated_instruction(vcpu);
5220 return 1;
5221 }
5222 }
51d8b661 5223 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5224}
5225
c7c9c56c
YZ		 5226static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5227{
5228 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5229 int vector = exit_qualification & 0xff;
5230
5231 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5232 kvm_apic_set_eoi_accelerated(vcpu, vector);
5233 return 1;
5234}
5235
83d4c286
YZ		 5236static int handle_apic_write(struct kvm_vcpu *vcpu)
5237{
5238 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5239 u32 offset = exit_qualification & 0xfff;
5240
5241 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5242 kvm_apic_write_nodecode(vcpu, offset);
5243 return 1;
5244}
5245
851ba692 5246static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5247{
60637aac 5248 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5249 unsigned long exit_qualification;
e269fb21
JK		 5250 bool has_error_code = false;
5251 u32 error_code = 0;
37817f29 5252 u16 tss_selector;
7f3d35fd 5253 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5254
5255 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5256 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5257 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5258
5259 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5260
5261 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5262 if (reason == TASK_SWITCH_GATE && idt_v) {
5263 switch (type) {
5264 case INTR_TYPE_NMI_INTR:
5265 vcpu->arch.nmi_injected = false;
654f06fc 5266 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5267 break;
5268 case INTR_TYPE_EXT_INTR:
66fd3f7f 5269 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5270 kvm_clear_interrupt_queue(vcpu);
5271 break;
5272 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5273 if (vmx->idt_vectoring_info &
5274 VECTORING_INFO_DELIVER_CODE_MASK) {
5275 has_error_code = true;
5276 error_code =
5277 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5278 }
5279 /* fall through */
64a7ec06
GN		 5280 case INTR_TYPE_SOFT_EXCEPTION:
5281 kvm_clear_exception_queue(vcpu);
5282 break;
5283 default:
5284 break;
5285 }
60637aac 5286 }
37817f29
IE		 5287 tss_selector = exit_qualification;
5288
64a7ec06
GN		 5289 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5290 type != INTR_TYPE_EXT_INTR &&
5291 type != INTR_TYPE_NMI_INTR))
5292 skip_emulated_instruction(vcpu);
5293
7f3d35fd
KW		 5294 if (kvm_task_switch(vcpu, tss_selector,
5295 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5296 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5297 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5298 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5299 vcpu->run->internal.ndata = 0;
42dbaa5a 5300 return 0;
acb54517 5301 }
42dbaa5a
JK		 5302
5303 /* clear all local breakpoint enable flags */
5304 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5305
5306 /*
5307 * TODO: What about debug traps on tss switch?
5308 * Are we supposed to inject them and update dr6?
5309 */
5310
5311 return 1;
37817f29
IE		 5312}
5313
851ba692 5314static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5315{
f9c617f6 5316 unsigned long exit_qualification;
1439442c 5317 gpa_t gpa;
4f5982a5 5318 u32 error_code;
1439442c 5319 int gla_validity;
1439442c 5320
f9c617f6 5321 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5322
1439442c
SY		 5323 gla_validity = (exit_qualification >> 7) & 0x3;
5324 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5325 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5326 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5327 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5328 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5329 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5330 (long unsigned int)exit_qualification);
851ba692
AK		 5331 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5332 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5333 return 0;
1439442c
SY		 5334 }
5335
5336 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5337 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5338
5339 /* It is a write fault? */
5340 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5341 /* It is a fetch fault? */
5342 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5343 /* ept page table is present? */
5344 error_code |= (exit_qualification >> 3) & 0x1;
5345
25d92081
YZ		 5346 vcpu->arch.exit_qualification = exit_qualification;
5347
4f5982a5 5348 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5349}
5350
68f89400
MT		 5351static u64 ept_rsvd_mask(u64 spte, int level)
5352{
5353 int i;
5354 u64 mask = 0;
5355
5356 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5357 mask |= (1ULL << i);
5358
5359 if (level > 2)
5360 /* bits 7:3 reserved */
5361 mask |= 0xf8;
5362 else if (level == 2) {
5363 if (spte & (1ULL << 7))
5364 /* 2MB ref, bits 20:12 reserved */
5365 mask |= 0x1ff000;
5366 else
5367 /* bits 6:3 reserved */
5368 mask |= 0x78;
5369 }
5370
5371 return mask;
5372}
5373
5374static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5375 int level)
5376{
5377 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5378
5379 /* 010b (write-only) */
5380 WARN_ON((spte & 0x7) == 0x2);
5381
5382 /* 110b (write/execute) */
5383 WARN_ON((spte & 0x7) == 0x6);
5384
5385 /* 100b (execute-only) and value not supported by logical processor */
5386 if (!cpu_has_vmx_ept_execute_only())
5387 WARN_ON((spte & 0x7) == 0x4);
5388
5389 /* not 000b */
5390 if ((spte & 0x7)) {
5391 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5392
5393 if (rsvd_bits != 0) {
5394 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5395 __func__, rsvd_bits);
5396 WARN_ON(1);
5397 }
5398
5399 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5400 u64 ept_mem_type = (spte & 0x38) >> 3;
5401
5402 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5403 ept_mem_type == 7) {
5404 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5405 __func__, ept_mem_type);
5406 WARN_ON(1);
5407 }
5408 }
5409 }
5410}
5411
851ba692 5412static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5413{
5414 u64 sptes[4];
ce88decf 5415 int nr_sptes, i, ret;
68f89400
MT		 5416 gpa_t gpa;
5417
5418 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5419
ce88decf 5420 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5421 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5422 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5423 EMULATE_DONE;
f8f55942
XG		 5424
5425 if (unlikely(ret == RET_MMIO_PF_INVALID))
5426 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5427
b37fbea6 5428 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5429 return 1;
5430
5431 /* It is the real ept misconfig */
68f89400
MT		 5432 printk(KERN_ERR "EPT: Misconfiguration.\n");
5433 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5434
5435 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5436
5437 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5438 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5439
851ba692
AK		 5440 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5441 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5442
5443 return 0;
5444}
5445
851ba692 5446static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5447{
5448 u32 cpu_based_vm_exec_control;
5449
5450 /* clear pending NMI */
5451 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5452 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5453 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5454 ++vcpu->stat.nmi_window_exits;
3842d135 5455 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5456
5457 return 1;
5458}
5459
80ced186 5460static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5461{
8b3079a5
AK		 5462 struct vcpu_vmx *vmx = to_vmx(vcpu);
5463 enum emulation_result err = EMULATE_DONE;
80ced186 5464 int ret = 1;
49e9d557
AK		 5465 u32 cpu_exec_ctrl;
5466 bool intr_window_requested;
b8405c18 5467 unsigned count = 130;
49e9d557
AK		 5468
5469 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5470 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5471
b8405c18 5472 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5473 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5474 return handle_interrupt_window(&vmx->vcpu);
5475
de87dcdd
AK		 5476 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5477 return 1;
5478
991eebf9 5479 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5480
ac0a48c3 5481 if (err == EMULATE_USER_EXIT) {
80ced186
MG		 5482 ret = 0;
5483 goto out;
5484 }
1d5a4d9b 5485
de5f70e0
AK		 5486 if (err != EMULATE_DONE) {
5487 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5488 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5489 vcpu->run->internal.ndata = 0;
6d77dbfc 5490 return 0;
de5f70e0 5491 }
ea953ef0 5492
8d76c49e
GN		 5493 if (vcpu->arch.halt_request) {
5494 vcpu->arch.halt_request = 0;
5495 ret = kvm_emulate_halt(vcpu);
5496 goto out;
5497 }
5498
ea953ef0 5499 if (signal_pending(current))
80ced186 5500 goto out;
ea953ef0
MG		 5501 if (need_resched())
5502 schedule();
5503 }
5504
14168786 5505 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5506out:
5507 return ret;
ea953ef0
MG		 5508}
5509
4b8d54f9
ZE		 5510/*
5511 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5512 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5513 */
9fb41ba8 5514static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5515{
5516 skip_emulated_instruction(vcpu);
5517 kvm_vcpu_on_spin(vcpu);
5518
5519 return 1;
5520}
5521
59708670
SY		 5522static int handle_invalid_op(struct kvm_vcpu *vcpu)
5523{
5524 kvm_queue_exception(vcpu, UD_VECTOR);
5525 return 1;
5526}
5527
ff2f6fe9
NHE		 5528/*
5529 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5530 * We could reuse a single VMCS for all the L2 guests, but we also want the
5531 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5532 * allows keeping them loaded on the processor, and in the future will allow
5533 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5534 * every entry if they never change.
5535 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5536 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5537 *
5538 * The following functions allocate and free a vmcs02 in this pool.
5539 */
5540
5541/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5542static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5543{
5544 struct vmcs02_list *item;
5545 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5546 if (item->vmptr == vmx->nested.current_vmptr) {
5547 list_move(&item->list, &vmx->nested.vmcs02_pool);
5548 return &item->vmcs02;
5549 }
5550
5551 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5552 /* Recycle the least recently used VMCS. */
5553 item = list_entry(vmx->nested.vmcs02_pool.prev,
5554 struct vmcs02_list, list);
5555 item->vmptr = vmx->nested.current_vmptr;
5556 list_move(&item->list, &vmx->nested.vmcs02_pool);
5557 return &item->vmcs02;
5558 }
5559
5560 /* Create a new VMCS */
0fa24ce3 5561 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5562 if (!item)
5563 return NULL;
5564 item->vmcs02.vmcs = alloc_vmcs();
5565 if (!item->vmcs02.vmcs) {
5566 kfree(item);
5567 return NULL;
5568 }
5569 loaded_vmcs_init(&item->vmcs02);
5570 item->vmptr = vmx->nested.current_vmptr;
5571 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5572 vmx->nested.vmcs02_num++;
5573 return &item->vmcs02;
5574}
5575
5576/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5577static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5578{
5579 struct vmcs02_list *item;
5580 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5581 if (item->vmptr == vmptr) {
5582 free_loaded_vmcs(&item->vmcs02);
5583 list_del(&item->list);
5584 kfree(item);
5585 vmx->nested.vmcs02_num--;
5586 return;
5587 }
5588}
5589
5590/*
5591 * Free all VMCSs saved for this vcpu, except the one pointed by
5592 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5593 * currently used, if running L2), and vmcs01 when running L2.
5594 */
5595static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5596{
5597 struct vmcs02_list *item, *n;
5598 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5599 if (vmx->loaded_vmcs != &item->vmcs02)
5600 free_loaded_vmcs(&item->vmcs02);
5601 list_del(&item->list);
5602 kfree(item);
5603 }
5604 vmx->nested.vmcs02_num = 0;
5605
5606 if (vmx->loaded_vmcs != &vmx->vmcs01)
5607 free_loaded_vmcs(&vmx->vmcs01);
5608}
5609
0658fbaa
ACL		 5610/*
5611 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5612 * set the success or error code of an emulated VMX instruction, as specified
5613 * by Vol 2B, VMX Instruction Reference, "Conventions".
5614 */
5615static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5616{
5617 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5618 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5619 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5620}
5621
5622static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5623{
5624 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5625 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5626 X86_EFLAGS_SF | X86_EFLAGS_OF))
5627 | X86_EFLAGS_CF);
5628}
5629
145c28dd 5630static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5631 u32 vm_instruction_error)
5632{
5633 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5634 /*
5635 * failValid writes the error number to the current VMCS, which
5636 * can't be done there isn't a current VMCS.
5637 */
5638 nested_vmx_failInvalid(vcpu);
5639 return;
5640 }
5641 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5642 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5643 X86_EFLAGS_SF | X86_EFLAGS_OF))
5644 | X86_EFLAGS_ZF);
5645 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5646 /*
5647 * We don't need to force a shadow sync because
5648 * VM_INSTRUCTION_ERROR is not shadowed
5649 */
5650}
145c28dd 5651
ec378aee
NHE		 5652/*
5653 * Emulate the VMXON instruction.
5654 * Currently, we just remember that VMX is active, and do not save or even
5655 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5656 * do not currently need to store anything in that guest-allocated memory
5657 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5658 * argument is different from the VMXON pointer (which the spec says they do).
5659 */
5660static int handle_vmon(struct kvm_vcpu *vcpu)
5661{
5662 struct kvm_segment cs;
5663 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5664 struct vmcs *shadow_vmcs;
b3897a49
NHE		 5665 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
5666 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 5667
5668 /* The Intel VMX Instruction Reference lists a bunch of bits that
5669 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5670 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5671 * Otherwise, we should fail with #UD. We test these now:
5672 */
5673 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5674 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5675 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5676 kvm_queue_exception(vcpu, UD_VECTOR);
5677 return 1;
5678 }
5679
5680 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5681 if (is_long_mode(vcpu) && !cs.l) {
5682 kvm_queue_exception(vcpu, UD_VECTOR);
5683 return 1;
5684 }
5685
5686 if (vmx_get_cpl(vcpu)) {
5687 kvm_inject_gp(vcpu, 0);
5688 return 1;
5689 }
145c28dd
AG		 5690 if (vmx->nested.vmxon) {
5691 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5692 skip_emulated_instruction(vcpu);
5693 return 1;
5694 }
b3897a49
NHE		 5695
5696 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
5697 != VMXON_NEEDED_FEATURES) {
5698 kvm_inject_gp(vcpu, 0);
5699 return 1;
5700 }
5701
8de48833
AG		 5702 if (enable_shadow_vmcs) {
5703 shadow_vmcs = alloc_vmcs();
5704 if (!shadow_vmcs)
5705 return -ENOMEM;
5706 /* mark vmcs as shadow */
5707 shadow_vmcs->revision_id |= (1u << 31);
5708 /* init shadow vmcs */
5709 vmcs_clear(shadow_vmcs);
5710 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5711 }
ec378aee 5712
ff2f6fe9
NHE		 5713 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5714 vmx->nested.vmcs02_num = 0;
5715
ec378aee
NHE		 5716 vmx->nested.vmxon = true;
5717
5718 skip_emulated_instruction(vcpu);
a25eb114 5719 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5720 return 1;
5721}
5722
5723/*
5724 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5725 * for running VMX instructions (except VMXON, whose prerequisites are
5726 * slightly different). It also specifies what exception to inject otherwise.
5727 */
5728static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5729{
5730 struct kvm_segment cs;
5731 struct vcpu_vmx *vmx = to_vmx(vcpu);
5732
5733 if (!vmx->nested.vmxon) {
5734 kvm_queue_exception(vcpu, UD_VECTOR);
5735 return 0;
5736 }
5737
5738 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5739 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5740 (is_long_mode(vcpu) && !cs.l)) {
5741 kvm_queue_exception(vcpu, UD_VECTOR);
5742 return 0;
5743 }
5744
5745 if (vmx_get_cpl(vcpu)) {
5746 kvm_inject_gp(vcpu, 0);
5747 return 0;
5748 }
5749
5750 return 1;
5751}
5752
e7953d7f
AG		 5753static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5754{
8a1b9dd0 5755 u32 exec_control;
012f83cb
AG		 5756 if (enable_shadow_vmcs) {
5757 if (vmx->nested.current_vmcs12 != NULL) {
5758 /* copy to memory all shadowed fields in case
5759 they were modified */
5760 copy_shadow_to_vmcs12(vmx);
5761 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5762 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5763 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5764 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5765 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5766 }
5767 }
e7953d7f
AG		 5768 kunmap(vmx->nested.current_vmcs12_page);
5769 nested_release_page(vmx->nested.current_vmcs12_page);
5770}
5771
ec378aee
NHE		 5772/*
5773 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5774 * just stops using VMX.
5775 */
5776static void free_nested(struct vcpu_vmx *vmx)
5777{
5778 if (!vmx->nested.vmxon)
5779 return;
5780 vmx->nested.vmxon = false;
a9d30f33 5781 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5782 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5783 vmx->nested.current_vmptr = -1ull;
5784 vmx->nested.current_vmcs12 = NULL;
5785 }
e7953d7f
AG		 5786 if (enable_shadow_vmcs)
5787 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5788 /* Unpin physical memory we referred to in current vmcs02 */
5789 if (vmx->nested.apic_access_page) {
5790 nested_release_page(vmx->nested.apic_access_page);
5791 vmx->nested.apic_access_page = 0;
5792 }
ff2f6fe9
NHE		 5793
5794 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5795}
5796
5797/* Emulate the VMXOFF instruction */
5798static int handle_vmoff(struct kvm_vcpu *vcpu)
5799{
5800 if (!nested_vmx_check_permission(vcpu))
5801 return 1;
5802 free_nested(to_vmx(vcpu));
5803 skip_emulated_instruction(vcpu);
a25eb114 5804 nested_vmx_succeed(vcpu);
ec378aee
NHE		 5805 return 1;
5806}
5807
064aea77
NHE		 5808/*
5809 * Decode the memory-address operand of a vmx instruction, as recorded on an
5810 * exit caused by such an instruction (run by a guest hypervisor).
5811 * On success, returns 0. When the operand is invalid, returns 1 and throws
5812 * #UD or #GP.
5813 */
5814static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5815 unsigned long exit_qualification,
5816 u32 vmx_instruction_info, gva_t *ret)
5817{
5818 /*
5819 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5820 * Execution", on an exit, vmx_instruction_info holds most of the
5821 * addressing components of the operand. Only the displacement part
5822 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5823 * For how an actual address is calculated from all these components,
5824 * refer to Vol. 1, "Operand Addressing".
5825 */
5826 int scaling = vmx_instruction_info & 3;
5827 int addr_size = (vmx_instruction_info >> 7) & 7;
5828 bool is_reg = vmx_instruction_info & (1u << 10);
5829 int seg_reg = (vmx_instruction_info >> 15) & 7;
5830 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5831 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5832 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5833 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5834
5835 if (is_reg) {
5836 kvm_queue_exception(vcpu, UD_VECTOR);
5837 return 1;
5838 }
5839
5840 /* Addr = segment_base + offset */
5841 /* offset = base + [index * scale] + displacement */
5842 *ret = vmx_get_segment_base(vcpu, seg_reg);
5843 if (base_is_valid)
5844 *ret += kvm_register_read(vcpu, base_reg);
5845 if (index_is_valid)
5846 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5847 *ret += exit_qualification; /* holds the displacement */
5848
5849 if (addr_size == 1) /* 32 bit */
5850 *ret &= 0xffffffff;
5851
5852 /*
5853 * TODO: throw #GP (and return 1) in various cases that the VM*
5854 * instructions require it - e.g., offset beyond segment limit,
5855 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5856 * address, and so on. Currently these are not checked.
5857 */
5858 return 0;
5859}
5860
27d6c865
NHE		 5861/* Emulate the VMCLEAR instruction */
5862static int handle_vmclear(struct kvm_vcpu *vcpu)
5863{
5864 struct vcpu_vmx *vmx = to_vmx(vcpu);
5865 gva_t gva;
5866 gpa_t vmptr;
5867 struct vmcs12 *vmcs12;
5868 struct page *page;
5869 struct x86_exception e;
5870
5871 if (!nested_vmx_check_permission(vcpu))
5872 return 1;
5873
5874 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5875 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5876 return 1;
5877
5878 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5879 sizeof(vmptr), &e)) {
5880 kvm_inject_page_fault(vcpu, &e);
5881 return 1;
5882 }
5883
5884 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5885 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5886 skip_emulated_instruction(vcpu);
5887 return 1;
5888 }
5889
5890 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5891 nested_release_vmcs12(vmx);
27d6c865
NHE		 5892 vmx->nested.current_vmptr = -1ull;
5893 vmx->nested.current_vmcs12 = NULL;
5894 }
5895
5896 page = nested_get_page(vcpu, vmptr);
5897 if (page == NULL) {
5898 /*
5899 * For accurate processor emulation, VMCLEAR beyond available
5900 * physical memory should do nothing at all. However, it is
5901 * possible that a nested vmx bug, not a guest hypervisor bug,
5902 * resulted in this case, so let's shut down before doing any
5903 * more damage:
5904 */
5905 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5906 return 1;
5907 }
5908 vmcs12 = kmap(page);
5909 vmcs12->launch_state = 0;
5910 kunmap(page);
5911 nested_release_page(page);
5912
5913 nested_free_vmcs02(vmx, vmptr);
5914
5915 skip_emulated_instruction(vcpu);
5916 nested_vmx_succeed(vcpu);
5917 return 1;
5918}
5919
cd232ad0
NHE		 5920static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5921
5922/* Emulate the VMLAUNCH instruction */
5923static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5924{
5925 return nested_vmx_run(vcpu, true);
5926}
5927
5928/* Emulate the VMRESUME instruction */
5929static int handle_vmresume(struct kvm_vcpu *vcpu)
5930{
5931
5932 return nested_vmx_run(vcpu, false);
5933}
5934
49f705c5
NHE		 5935enum vmcs_field_type {
5936 VMCS_FIELD_TYPE_U16 = 0,
5937 VMCS_FIELD_TYPE_U64 = 1,
5938 VMCS_FIELD_TYPE_U32 = 2,
5939 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5940};
5941
5942static inline int vmcs_field_type(unsigned long field)
5943{
5944 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5945 return VMCS_FIELD_TYPE_U32;
5946 return (field >> 13) & 0x3 ;
5947}
5948
5949static inline int vmcs_field_readonly(unsigned long field)
5950{
5951 return (((field >> 10) & 0x3) == 1);
5952}
5953
5954/*
5955 * Read a vmcs12 field. Since these can have varying lengths and we return
5956 * one type, we chose the biggest type (u64) and zero-extend the return value
5957 * to that size. Note that the caller, handle_vmread, might need to use only
5958 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5959 * 64-bit fields are to be returned).
5960 */
5961static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5962 unsigned long field, u64 *ret)
5963{
5964 short offset = vmcs_field_to_offset(field);
5965 char *p;
5966
5967 if (offset < 0)
5968 return 0;
5969
5970 p = ((char *)(get_vmcs12(vcpu))) + offset;
5971
5972 switch (vmcs_field_type(field)) {
5973 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5974 *ret = *((natural_width *)p);
5975 return 1;
5976 case VMCS_FIELD_TYPE_U16:
5977 *ret = *((u16 *)p);
5978 return 1;
5979 case VMCS_FIELD_TYPE_U32:
5980 *ret = *((u32 *)p);
5981 return 1;
5982 case VMCS_FIELD_TYPE_U64:
5983 *ret = *((u64 *)p);
5984 return 1;
5985 default:
5986 return 0; /* can never happen. */
5987 }
5988}
5989
20b97fea
AG		 5990
5991static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5992 unsigned long field, u64 field_value){
5993 short offset = vmcs_field_to_offset(field);
5994 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5995 if (offset < 0)
5996 return false;
5997
5998 switch (vmcs_field_type(field)) {
5999 case VMCS_FIELD_TYPE_U16:
6000 *(u16 *)p = field_value;
6001 return true;
6002 case VMCS_FIELD_TYPE_U32:
6003 *(u32 *)p = field_value;
6004 return true;
6005 case VMCS_FIELD_TYPE_U64:
6006 *(u64 *)p = field_value;
6007 return true;
6008 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6009 *(natural_width *)p = field_value;
6010 return true;
6011 default:
6012 return false; /* can never happen. */
6013 }
6014
6015}
6016
16f5b903
AG		 6017static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6018{
6019 int i;
6020 unsigned long field;
6021 u64 field_value;
6022 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6023 const unsigned long *fields = shadow_read_write_fields;
6024 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6025
6026 vmcs_load(shadow_vmcs);
6027
6028 for (i = 0; i < num_fields; i++) {
6029 field = fields[i];
6030 switch (vmcs_field_type(field)) {
6031 case VMCS_FIELD_TYPE_U16:
6032 field_value = vmcs_read16(field);
6033 break;
6034 case VMCS_FIELD_TYPE_U32:
6035 field_value = vmcs_read32(field);
6036 break;
6037 case VMCS_FIELD_TYPE_U64:
6038 field_value = vmcs_read64(field);
6039 break;
6040 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6041 field_value = vmcs_readl(field);
6042 break;
6043 }
6044 vmcs12_write_any(&vmx->vcpu, field, field_value);
6045 }
6046
6047 vmcs_clear(shadow_vmcs);
6048 vmcs_load(vmx->loaded_vmcs->vmcs);
6049}
6050
c3114420
AG		 6051static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6052{
c2bae893
MK		 6053 const unsigned long *fields[] = {
6054 shadow_read_write_fields,
6055 shadow_read_only_fields
c3114420 6056 };
c2bae893 6057 const int max_fields[] = {
c3114420
AG		 6058 max_shadow_read_write_fields,
6059 max_shadow_read_only_fields
6060 };
6061 int i, q;
6062 unsigned long field;
6063 u64 field_value = 0;
6064 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6065
6066 vmcs_load(shadow_vmcs);
6067
c2bae893 6068 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6069 for (i = 0; i < max_fields[q]; i++) {
6070 field = fields[q][i];
6071 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6072
6073 switch (vmcs_field_type(field)) {
6074 case VMCS_FIELD_TYPE_U16:
6075 vmcs_write16(field, (u16)field_value);
6076 break;
6077 case VMCS_FIELD_TYPE_U32:
6078 vmcs_write32(field, (u32)field_value);
6079 break;
6080 case VMCS_FIELD_TYPE_U64:
6081 vmcs_write64(field, (u64)field_value);
6082 break;
6083 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6084 vmcs_writel(field, (long)field_value);
6085 break;
6086 }
6087 }
6088 }
6089
6090 vmcs_clear(shadow_vmcs);
6091 vmcs_load(vmx->loaded_vmcs->vmcs);
6092}
6093
49f705c5
NHE		 6094/*
6095 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6096 * used before) all generate the same failure when it is missing.
6097 */
6098static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6099{
6100 struct vcpu_vmx *vmx = to_vmx(vcpu);
6101 if (vmx->nested.current_vmptr == -1ull) {
6102 nested_vmx_failInvalid(vcpu);
6103 skip_emulated_instruction(vcpu);
6104 return 0;
6105 }
6106 return 1;
6107}
6108
6109static int handle_vmread(struct kvm_vcpu *vcpu)
6110{
6111 unsigned long field;
6112 u64 field_value;
6113 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6114 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6115 gva_t gva = 0;
6116
6117 if (!nested_vmx_check_permission(vcpu) ||
6118 !nested_vmx_check_vmcs12(vcpu))
6119 return 1;
6120
6121 /* Decode instruction info and find the field to read */
6122 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6123 /* Read the field, zero-extended to a u64 field_value */
6124 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6125 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6126 skip_emulated_instruction(vcpu);
6127 return 1;
6128 }
6129 /*
6130 * Now copy part of this value to register or memory, as requested.
6131 * Note that the number of bits actually copied is 32 or 64 depending
6132 * on the guest's mode (32 or 64 bit), not on the given field's length.
6133 */
6134 if (vmx_instruction_info & (1u << 10)) {
6135 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6136 field_value);
6137 } else {
6138 if (get_vmx_mem_address(vcpu, exit_qualification,
6139 vmx_instruction_info, &gva))
6140 return 1;
6141 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6142 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6143 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6144 }
6145
6146 nested_vmx_succeed(vcpu);
6147 skip_emulated_instruction(vcpu);
6148 return 1;
6149}
6150
6151
6152static int handle_vmwrite(struct kvm_vcpu *vcpu)
6153{
6154 unsigned long field;
6155 gva_t gva;
6156 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6157 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6158 /* The value to write might be 32 or 64 bits, depending on L1's long
6159 * mode, and eventually we need to write that into a field of several
6160 * possible lengths. The code below first zero-extends the value to 64
6161 * bit (field_value), and then copies only the approriate number of
6162 * bits into the vmcs12 field.
6163 */
6164 u64 field_value = 0;
6165 struct x86_exception e;
6166
6167 if (!nested_vmx_check_permission(vcpu) ||
6168 !nested_vmx_check_vmcs12(vcpu))
6169 return 1;
6170
6171 if (vmx_instruction_info & (1u << 10))
6172 field_value = kvm_register_read(vcpu,
6173 (((vmx_instruction_info) >> 3) & 0xf));
6174 else {
6175 if (get_vmx_mem_address(vcpu, exit_qualification,
6176 vmx_instruction_info, &gva))
6177 return 1;
6178 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6179 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6180 kvm_inject_page_fault(vcpu, &e);
6181 return 1;
6182 }
6183 }
6184
6185
6186 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6187 if (vmcs_field_readonly(field)) {
6188 nested_vmx_failValid(vcpu,
6189 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6190 skip_emulated_instruction(vcpu);
6191 return 1;
6192 }
6193
20b97fea 6194 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6195 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6196 skip_emulated_instruction(vcpu);
6197 return 1;
6198 }
6199
6200 nested_vmx_succeed(vcpu);
6201 skip_emulated_instruction(vcpu);
6202 return 1;
6203}
6204
63846663
NHE		 6205/* Emulate the VMPTRLD instruction */
6206static int handle_vmptrld(struct kvm_vcpu *vcpu)
6207{
6208 struct vcpu_vmx *vmx = to_vmx(vcpu);
6209 gva_t gva;
6210 gpa_t vmptr;
6211 struct x86_exception e;
8a1b9dd0 6212 u32 exec_control;
63846663
NHE		 6213
6214 if (!nested_vmx_check_permission(vcpu))
6215 return 1;
6216
6217 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6218 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6219 return 1;
6220
6221 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6222 sizeof(vmptr), &e)) {
6223 kvm_inject_page_fault(vcpu, &e);
6224 return 1;
6225 }
6226
6227 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6228 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6229 skip_emulated_instruction(vcpu);
6230 return 1;
6231 }
6232
6233 if (vmx->nested.current_vmptr != vmptr) {
6234 struct vmcs12 *new_vmcs12;
6235 struct page *page;
6236 page = nested_get_page(vcpu, vmptr);
6237 if (page == NULL) {
6238 nested_vmx_failInvalid(vcpu);
6239 skip_emulated_instruction(vcpu);
6240 return 1;
6241 }
6242 new_vmcs12 = kmap(page);
6243 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6244 kunmap(page);
6245 nested_release_page_clean(page);
6246 nested_vmx_failValid(vcpu,
6247 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6248 skip_emulated_instruction(vcpu);
6249 return 1;
6250 }
e7953d7f
AG		 6251 if (vmx->nested.current_vmptr != -1ull)
6252 nested_release_vmcs12(vmx);
63846663
NHE		 6253
6254 vmx->nested.current_vmptr = vmptr;
6255 vmx->nested.current_vmcs12 = new_vmcs12;
6256 vmx->nested.current_vmcs12_page = page;
012f83cb 6257 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6258 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6259 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6260 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6261 vmcs_write64(VMCS_LINK_POINTER,
6262 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6263 vmx->nested.sync_shadow_vmcs = true;
6264 }
63846663
NHE		 6265 }
6266
6267 nested_vmx_succeed(vcpu);
6268 skip_emulated_instruction(vcpu);
6269 return 1;
6270}
6271
6a4d7550
NHE		 6272/* Emulate the VMPTRST instruction */
6273static int handle_vmptrst(struct kvm_vcpu *vcpu)
6274{
6275 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6276 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6277 gva_t vmcs_gva;
6278 struct x86_exception e;
6279
6280 if (!nested_vmx_check_permission(vcpu))
6281 return 1;
6282
6283 if (get_vmx_mem_address(vcpu, exit_qualification,
6284 vmx_instruction_info, &vmcs_gva))
6285 return 1;
6286 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6287 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6288 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6289 sizeof(u64), &e)) {
6290 kvm_inject_page_fault(vcpu, &e);
6291 return 1;
6292 }
6293 nested_vmx_succeed(vcpu);
6294 skip_emulated_instruction(vcpu);
6295 return 1;
6296}
6297
bfd0a56b
NHE		 6298/* Emulate the INVEPT instruction */
6299static int handle_invept(struct kvm_vcpu *vcpu)
6300{
6301 u32 vmx_instruction_info, types;
6302 unsigned long type;
6303 gva_t gva;
6304 struct x86_exception e;
6305 struct {
6306 u64 eptp, gpa;
6307 } operand;
6308 u64 eptp_mask = ((1ull << 51) - 1) & PAGE_MASK;
6309
6310 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6311 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6312 kvm_queue_exception(vcpu, UD_VECTOR);
6313 return 1;
6314 }
6315
6316 if (!nested_vmx_check_permission(vcpu))
6317 return 1;
6318
6319 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6320 kvm_queue_exception(vcpu, UD_VECTOR);
6321 return 1;
6322 }
6323
6324 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6325 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6326
6327 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6328
6329 if (!(types & (1UL << type))) {
6330 nested_vmx_failValid(vcpu,
6331 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6332 return 1;
6333 }
6334
6335 /* According to the Intel VMX instruction reference, the memory
6336 * operand is read even if it isn't needed (e.g., for type==global)
6337 */
6338 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6339 vmx_instruction_info, &gva))
6340 return 1;
6341 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6342 sizeof(operand), &e)) {
6343 kvm_inject_page_fault(vcpu, &e);
6344 return 1;
6345 }
6346
6347 switch (type) {
6348 case VMX_EPT_EXTENT_CONTEXT:
6349 if ((operand.eptp & eptp_mask) !=
6350 (nested_ept_get_cr3(vcpu) & eptp_mask))
6351 break;
6352 case VMX_EPT_EXTENT_GLOBAL:
6353 kvm_mmu_sync_roots(vcpu);
6354 kvm_mmu_flush_tlb(vcpu);
6355 nested_vmx_succeed(vcpu);
6356 break;
6357 default:
6358 BUG_ON(1);
6359 break;
6360 }
6361
6362 skip_emulated_instruction(vcpu);
6363 return 1;
6364}
6365
6aa8b732
AK		 6366/*
6367 * The exit handlers return 1 if the exit was handled fully and guest execution
6368 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6369 * to be done to userspace and return 0.
6370 */
772e0318 6371static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6372 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6373 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6374 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6375 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6376 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6377 [EXIT_REASON_CR_ACCESS] = handle_cr,
6378 [EXIT_REASON_DR_ACCESS] = handle_dr,
6379 [EXIT_REASON_CPUID] = handle_cpuid,
6380 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6381 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6382 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6383 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6384 [EXIT_REASON_INVD] = handle_invd,
a7052897 6385 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6386 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6387 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6388 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6389 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6390 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6391 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6392 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6393 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6394 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6395 [EXIT_REASON_VMOFF] = handle_vmoff,
6396 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6397 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6398 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6399 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6400 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6401 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6402 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6403 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6404 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6405 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6406 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6407 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6408 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6409 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
bfd0a56b 6410 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6411};
6412
6413static const int kvm_vmx_max_exit_handlers =
50a3485c 6414 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6415
908a7bdd
JK		 6416static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6417 struct vmcs12 *vmcs12)
6418{
6419 unsigned long exit_qualification;
6420 gpa_t bitmap, last_bitmap;
6421 unsigned int port;
6422 int size;
6423 u8 b;
6424
6425 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6426 return 1;
6427
6428 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6429 return 0;
6430
6431 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6432
6433 port = exit_qualification >> 16;
6434 size = (exit_qualification & 7) + 1;
6435
6436 last_bitmap = (gpa_t)-1;
6437 b = -1;
6438
6439 while (size > 0) {
6440 if (port < 0x8000)
6441 bitmap = vmcs12->io_bitmap_a;
6442 else if (port < 0x10000)
6443 bitmap = vmcs12->io_bitmap_b;
6444 else
6445 return 1;
6446 bitmap += (port & 0x7fff) / 8;
6447
6448 if (last_bitmap != bitmap)
6449 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6450 return 1;
6451 if (b & (1 << (port & 7)))
6452 return 1;
6453
6454 port++;
6455 size--;
6456 last_bitmap = bitmap;
6457 }
6458
6459 return 0;
6460}
6461
644d711a
NHE		 6462/*
6463 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6464 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6465 * disinterest in the current event (read or write a specific MSR) by using an
6466 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6467 */
6468static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6469 struct vmcs12 *vmcs12, u32 exit_reason)
6470{
6471 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6472 gpa_t bitmap;
6473
cbd29cb6 6474 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6475 return 1;
6476
6477 /*
6478 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6479 * for the four combinations of read/write and low/high MSR numbers.
6480 * First we need to figure out which of the four to use:
6481 */
6482 bitmap = vmcs12->msr_bitmap;
6483 if (exit_reason == EXIT_REASON_MSR_WRITE)
6484 bitmap += 2048;
6485 if (msr_index >= 0xc0000000) {
6486 msr_index -= 0xc0000000;
6487 bitmap += 1024;
6488 }
6489
6490 /* Then read the msr_index'th bit from this bitmap: */
6491 if (msr_index < 1024*8) {
6492 unsigned char b;
bd31a7f5
JK		 6493 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6494 return 1;
644d711a
NHE		 6495 return 1 & (b >> (msr_index & 7));
6496 } else
6497 return 1; /* let L1 handle the wrong parameter */
6498}
6499
6500/*
6501 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6502 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6503 * intercept (via guest_host_mask etc.) the current event.
6504 */
6505static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6506 struct vmcs12 *vmcs12)
6507{
6508 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6509 int cr = exit_qualification & 15;
6510 int reg = (exit_qualification >> 8) & 15;
6511 unsigned long val = kvm_register_read(vcpu, reg);
6512
6513 switch ((exit_qualification >> 4) & 3) {
6514 case 0: /* mov to cr */
6515 switch (cr) {
6516 case 0:
6517 if (vmcs12->cr0_guest_host_mask &
6518 (val ^ vmcs12->cr0_read_shadow))
6519 return 1;
6520 break;
6521 case 3:
6522 if ((vmcs12->cr3_target_count >= 1 &&
6523 vmcs12->cr3_target_value0 == val) ||
6524 (vmcs12->cr3_target_count >= 2 &&
6525 vmcs12->cr3_target_value1 == val) ||
6526 (vmcs12->cr3_target_count >= 3 &&
6527 vmcs12->cr3_target_value2 == val) ||
6528 (vmcs12->cr3_target_count >= 4 &&
6529 vmcs12->cr3_target_value3 == val))
6530 return 0;
6531 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6532 return 1;
6533 break;
6534 case 4:
6535 if (vmcs12->cr4_guest_host_mask &
6536 (vmcs12->cr4_read_shadow ^ val))
6537 return 1;
6538 break;
6539 case 8:
6540 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6541 return 1;
6542 break;
6543 }
6544 break;
6545 case 2: /* clts */
6546 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6547 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6548 return 1;
6549 break;
6550 case 1: /* mov from cr */
6551 switch (cr) {
6552 case 3:
6553 if (vmcs12->cpu_based_vm_exec_control &
6554 CPU_BASED_CR3_STORE_EXITING)
6555 return 1;
6556 break;
6557 case 8:
6558 if (vmcs12->cpu_based_vm_exec_control &
6559 CPU_BASED_CR8_STORE_EXITING)
6560 return 1;
6561 break;
6562 }
6563 break;
6564 case 3: /* lmsw */
6565 /*
6566 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6567 * cr0. Other attempted changes are ignored, with no exit.
6568 */
6569 if (vmcs12->cr0_guest_host_mask & 0xe &
6570 (val ^ vmcs12->cr0_read_shadow))
6571 return 1;
6572 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6573 !(vmcs12->cr0_read_shadow & 0x1) &&
6574 (val & 0x1))
6575 return 1;
6576 break;
6577 }
6578 return 0;
6579}
6580
6581/*
6582 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6583 * should handle it ourselves in L0 (and then continue L2). Only call this
6584 * when in is_guest_mode (L2).
6585 */
6586static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6587{
644d711a
NHE		 6588 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6589 struct vcpu_vmx *vmx = to_vmx(vcpu);
6590 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6591 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6592
6593 if (vmx->nested.nested_run_pending)
6594 return 0;
6595
6596 if (unlikely(vmx->fail)) {
bd80158a
JK		 6597 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6598 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6599 return 1;
6600 }
6601
6602 switch (exit_reason) {
6603 case EXIT_REASON_EXCEPTION_NMI:
6604 if (!is_exception(intr_info))
6605 return 0;
6606 else if (is_page_fault(intr_info))
6607 return enable_ept;
6608 return vmcs12->exception_bitmap &
6609 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6610 case EXIT_REASON_EXTERNAL_INTERRUPT:
6611 return 0;
6612 case EXIT_REASON_TRIPLE_FAULT:
6613 return 1;
6614 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6615 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6616 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6617 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6618 case EXIT_REASON_TASK_SWITCH:
6619 return 1;
6620 case EXIT_REASON_CPUID:
6621 return 1;
6622 case EXIT_REASON_HLT:
6623 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6624 case EXIT_REASON_INVD:
6625 return 1;
6626 case EXIT_REASON_INVLPG:
6627 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6628 case EXIT_REASON_RDPMC:
6629 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6630 case EXIT_REASON_RDTSC:
6631 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6632 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6633 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6634 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6635 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6636 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6637 case EXIT_REASON_INVEPT:
644d711a
NHE		 6638 /*
6639 * VMX instructions trap unconditionally. This allows L1 to
6640 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6641 */
6642 return 1;
6643 case EXIT_REASON_CR_ACCESS:
6644 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6645 case EXIT_REASON_DR_ACCESS:
6646 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6647 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6648 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6649 case EXIT_REASON_MSR_READ:
6650 case EXIT_REASON_MSR_WRITE:
6651 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6652 case EXIT_REASON_INVALID_STATE:
6653 return 1;
6654 case EXIT_REASON_MWAIT_INSTRUCTION:
6655 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6656 case EXIT_REASON_MONITOR_INSTRUCTION:
6657 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6658 case EXIT_REASON_PAUSE_INSTRUCTION:
6659 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6660 nested_cpu_has2(vmcs12,
6661 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6662 case EXIT_REASON_MCE_DURING_VMENTRY:
6663 return 0;
6664 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6665 return 1;
6666 case EXIT_REASON_APIC_ACCESS:
6667 return nested_cpu_has2(vmcs12,
6668 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6669 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6670 /*
6671 * L0 always deals with the EPT violation. If nested EPT is
6672 * used, and the nested mmu code discovers that the address is
6673 * missing in the guest EPT table (EPT12), the EPT violation
6674 * will be injected with nested_ept_inject_page_fault()
6675 */
6676 return 0;
644d711a 6677 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6678 /*
6679 * L2 never uses directly L1's EPT, but rather L0's own EPT
6680 * table (shadow on EPT) or a merged EPT table that L0 built
6681 * (EPT on EPT). So any problems with the structure of the
6682 * table is L0's fault.
6683 */
644d711a 6684 return 0;
0238ea91
JK		 6685 case EXIT_REASON_PREEMPTION_TIMER:
6686 return vmcs12->pin_based_vm_exec_control &
6687 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6688 case EXIT_REASON_WBINVD:
6689 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6690 case EXIT_REASON_XSETBV:
6691 return 1;
6692 default:
6693 return 1;
6694 }
6695}
6696
586f9607
AK		 6697static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6698{
6699 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6700 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6701}
6702
6aa8b732
AK		 6703/*
6704 * The guest has exited. See if we can fix it or if we need userspace
6705 * assistance.
6706 */
851ba692 6707static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6708{
29bd8a78 6709 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6710 u32 exit_reason = vmx->exit_reason;
1155f76a 6711 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6712
80ced186 6713 /* If guest state is invalid, start emulating */
14168786 6714 if (vmx->emulation_required)
80ced186 6715 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6716
b6f1250e
NHE		 6717 /*
6718 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6719 * we did not inject a still-pending event to L1 now because of
6720 * nested_run_pending, we need to re-enable this bit.
6721 */
6722 if (vmx->nested.nested_run_pending)
6723 kvm_make_request(KVM_REQ_EVENT, vcpu);
6724
509c75ea
NHE		 6725 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6726 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6727 vmx->nested.nested_run_pending = 1;
6728 else
6729 vmx->nested.nested_run_pending = 0;
6730
6731 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6732 nested_vmx_vmexit(vcpu);
6733 return 1;
6734 }
6735
5120702e
MG		 6736 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6737 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6738 vcpu->run->fail_entry.hardware_entry_failure_reason
6739 = exit_reason;
6740 return 0;
6741 }
6742
29bd8a78 6743 if (unlikely(vmx->fail)) {
851ba692
AK		 6744 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6745 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6746 = vmcs_read32(VM_INSTRUCTION_ERROR);
6747 return 0;
6748 }
6aa8b732 6749
b9bf6882
XG		 6750 /*
6751 * Note:
6752 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6753 * delivery event since it indicates guest is accessing MMIO.
6754 * The vm-exit can be triggered again after return to guest that
6755 * will cause infinite loop.
6756 */
d77c26fc 6757 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6758 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6759 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6760 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6761 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6762 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6763 vcpu->run->internal.ndata = 2;
6764 vcpu->run->internal.data[0] = vectoring_info;
6765 vcpu->run->internal.data[1] = exit_reason;
6766 return 0;
6767 }
3b86cd99 6768
644d711a
NHE		 6769 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6770 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 6771 get_vmcs12(vcpu))))) {
c4282df9 6772 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6773 vmx->soft_vnmi_blocked = 0;
3b86cd99 6774 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6775 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6776 /*
6777 * This CPU don't support us in finding the end of an
6778 * NMI-blocked window if the guest runs with IRQs
6779 * disabled. So we pull the trigger after 1 s of
6780 * futile waiting, but inform the user about this.
6781 */
6782 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6783 "state on VCPU %d after 1 s timeout\n",
6784 __func__, vcpu->vcpu_id);
6785 vmx->soft_vnmi_blocked = 0;
3b86cd99 6786 }
3b86cd99
JK		 6787 }
6788
6aa8b732
AK		 6789 if (exit_reason < kvm_vmx_max_exit_handlers
6790 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6791 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6792 else {
851ba692
AK		 6793 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6794 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6795 }
6796 return 0;
6797}
6798
95ba8273 6799static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6800{
95ba8273 6801 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6802 vmcs_write32(TPR_THRESHOLD, 0);
6803 return;
6804 }
6805
95ba8273 6806 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6807}
6808
8d14695f
YZ		 6809static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6810{
6811 u32 sec_exec_control;
6812
6813 /*
6814 * There is not point to enable virtualize x2apic without enable
6815 * apicv
6816 */
c7c9c56c
YZ		 6817 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6818 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6819 return;
6820
6821 if (!vm_need_tpr_shadow(vcpu->kvm))
6822 return;
6823
6824 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6825
6826 if (set) {
6827 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6828 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6829 } else {
6830 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6831 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6832 }
6833 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6834
6835 vmx_set_msr_bitmap(vcpu);
6836}
6837
c7c9c56c
YZ		 6838static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6839{
6840 u16 status;
6841 u8 old;
6842
6843 if (!vmx_vm_has_apicv(kvm))
6844 return;
6845
6846 if (isr == -1)
6847 isr = 0;
6848
6849 status = vmcs_read16(GUEST_INTR_STATUS);
6850 old = status >> 8;
6851 if (isr != old) {
6852 status &= 0xff;
6853 status |= isr << 8;
6854 vmcs_write16(GUEST_INTR_STATUS, status);
6855 }
6856}
6857
6858static void vmx_set_rvi(int vector)
6859{
6860 u16 status;
6861 u8 old;
6862
6863 status = vmcs_read16(GUEST_INTR_STATUS);
6864 old = (u8)status & 0xff;
6865 if ((u8)vector != old) {
6866 status &= ~0xff;
6867 status |= (u8)vector;
6868 vmcs_write16(GUEST_INTR_STATUS, status);
6869 }
6870}
6871
6872static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6873{
6874 if (max_irr == -1)
6875 return;
6876
6877 vmx_set_rvi(max_irr);
6878}
6879
6880static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6881{
3d81bc7e
YZ		 6882 if (!vmx_vm_has_apicv(vcpu->kvm))
6883 return;
6884
c7c9c56c
YZ		 6885 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6886 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6887 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6888 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6889}
6890
51aa01d1 6891static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6892{
00eba012
AK		 6893 u32 exit_intr_info;
6894
6895 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6896 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6897 return;
6898
c5ca8e57 6899 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6900 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6901
6902 /* Handle machine checks before interrupts are enabled */
00eba012 6903 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6904 kvm_machine_check();
6905
20f65983 6906 /* We need to handle NMIs before interrupts are enabled */
00eba012 6907 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6908 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6909 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6910 asm("int $2");
ff9d07a0
ZY		 6911 kvm_after_handle_nmi(&vmx->vcpu);
6912 }
51aa01d1 6913}
20f65983 6914
a547c6db
YZ		 6915static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6916{
6917 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6918
6919 /*
6920 * If external interrupt exists, IF bit is set in rflags/eflags on the
6921 * interrupt stack frame, and interrupt will be enabled on a return
6922 * from interrupt handler.
6923 */
6924 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6925 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6926 unsigned int vector;
6927 unsigned long entry;
6928 gate_desc *desc;
6929 struct vcpu_vmx *vmx = to_vmx(vcpu);
6930#ifdef CONFIG_X86_64
6931 unsigned long tmp;
6932#endif
6933
6934 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6935 desc = (gate_desc *)vmx->host_idt_base + vector;
6936 entry = gate_offset(*desc);
6937 asm volatile(
6938#ifdef CONFIG_X86_64
6939 "mov %%" _ASM_SP ", %[sp]\n\t"
6940 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6941 "push $%c[ss]\n\t"
6942 "push %[sp]\n\t"
6943#endif
6944 "pushf\n\t"
6945 "orl $0x200, (%%" _ASM_SP ")\n\t"
6946 __ASM_SIZE(push) " $%c[cs]\n\t"
6947 "call *%[entry]\n\t"
6948 :
6949#ifdef CONFIG_X86_64
6950 [sp]"=&r"(tmp)
6951#endif
6952 :
6953 [entry]"r"(entry),
6954 [ss]"i"(__KERNEL_DS),
6955 [cs]"i"(__KERNEL_CS)
6956 );
6957 } else
6958 local_irq_enable();
6959}
6960
51aa01d1
AK		 6961static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6962{
c5ca8e57 6963 u32 exit_intr_info;
51aa01d1
AK		 6964 bool unblock_nmi;
6965 u8 vector;
6966 bool idtv_info_valid;
6967
6968 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6969
cf393f75 6970 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6971 if (vmx->nmi_known_unmasked)
6972 return;
c5ca8e57
AK		 6973 /*
6974 * Can't use vmx->exit_intr_info since we're not sure what
6975 * the exit reason is.
6976 */
6977 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6978 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6979 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6980 /*
7b4a25cb 6981 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6982 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6983 * a guest IRET fault.
7b4a25cb
GN		 6984 * SDM 3: 23.2.2 (September 2008)
6985 * Bit 12 is undefined in any of the following cases:
6986 * If the VM exit sets the valid bit in the IDT-vectoring
6987 * information field.
6988 * If the VM exit is due to a double fault.
cf393f75 6989 */
7b4a25cb
GN		 6990 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6991 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6992 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6993 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6994 else
6995 vmx->nmi_known_unmasked =
6996 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6997 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6998 } else if (unlikely(vmx->soft_vnmi_blocked))
6999 vmx->vnmi_blocked_time +=
7000 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7001}
7002
3ab66e8a 7003static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7004 u32 idt_vectoring_info,
7005 int instr_len_field,
7006 int error_code_field)
51aa01d1 7007{
51aa01d1
AK		 7008 u8 vector;
7009 int type;
7010 bool idtv_info_valid;
7011
7012 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7013
3ab66e8a
JK		 7014 vcpu->arch.nmi_injected = false;
7015 kvm_clear_exception_queue(vcpu);
7016 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7017
7018 if (!idtv_info_valid)
7019 return;
7020
3ab66e8a 7021 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7022
668f612f
AK		 7023 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7024 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7025
64a7ec06 7026 switch (type) {
37b96e98 7027 case INTR_TYPE_NMI_INTR:
3ab66e8a 7028 vcpu->arch.nmi_injected = true;
668f612f 7029 /*
7b4a25cb 7030 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7031 * Clear bit "block by NMI" before VM entry if a NMI
7032 * delivery faulted.
668f612f 7033 */
3ab66e8a 7034 vmx_set_nmi_mask(vcpu, false);
37b96e98 7035 break;
37b96e98 7036 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7037 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7038 /* fall through */
7039 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7040 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7041 u32 err = vmcs_read32(error_code_field);
3ab66e8a 7042 kvm_queue_exception_e(vcpu, vector, err);
35920a35 7043 } else
3ab66e8a 7044 kvm_queue_exception(vcpu, vector);
37b96e98 7045 break;
66fd3f7f 7046 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7047 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7048 /* fall through */
37b96e98 7049 case INTR_TYPE_EXT_INTR:
3ab66e8a 7050 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7051 break;
7052 default:
7053 break;
f7d9238f 7054 }
cf393f75
AK		 7055}
7056
83422e17
AK		 7057static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7058{
3ab66e8a 7059 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7060 VM_EXIT_INSTRUCTION_LEN,
7061 IDT_VECTORING_ERROR_CODE);
7062}
7063
b463a6f7
AK		 7064static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7065{
3ab66e8a 7066 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7067 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7068 VM_ENTRY_INSTRUCTION_LEN,
7069 VM_ENTRY_EXCEPTION_ERROR_CODE);
7070
7071 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7072}
7073
d7cd9796
GN		 7074static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7075{
7076 int i, nr_msrs;
7077 struct perf_guest_switch_msr *msrs;
7078
7079 msrs = perf_guest_get_msrs(&nr_msrs);
7080
7081 if (!msrs)
7082 return;
7083
7084 for (i = 0; i < nr_msrs; i++)
7085 if (msrs[i].host == msrs[i].guest)
7086 clear_atomic_switch_msr(vmx, msrs[i].msr);
7087 else
7088 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7089 msrs[i].host);
7090}
7091
a3b5ba49 7092static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7093{
a2fa3e9f 7094 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7095 unsigned long debugctlmsr;
104f226b
AK		 7096
7097 /* Record the guest's net vcpu time for enforced NMI injections. */
7098 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7099 vmx->entry_time = ktime_get();
7100
7101 /* Don't enter VMX if guest state is invalid, let the exit handler
7102 start emulation until we arrive back to a valid state */
14168786 7103 if (vmx->emulation_required)
104f226b
AK		 7104 return;
7105
012f83cb
AG		 7106 if (vmx->nested.sync_shadow_vmcs) {
7107 copy_vmcs12_to_shadow(vmx);
7108 vmx->nested.sync_shadow_vmcs = false;
7109 }
7110
104f226b
AK		 7111 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7112 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7113 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7114 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7115
7116 /* When single-stepping over STI and MOV SS, we must clear the
7117 * corresponding interruptibility bits in the guest state. Otherwise
7118 * vmentry fails as it then expects bit 14 (BS) in pending debug
7119 * exceptions being set, but that's not correct for the guest debugging
7120 * case. */
7121 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7122 vmx_set_interrupt_shadow(vcpu, 0);
7123
d7cd9796 7124 atomic_switch_perf_msrs(vmx);
2a7921b7 7125 debugctlmsr = get_debugctlmsr();
d7cd9796 7126
d462b819 7127 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7128 asm(
6aa8b732 7129 /* Store host registers */
b188c81f
AK		 7130 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7131 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7132 "push %%" _ASM_CX " \n\t"
7133 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7134 "je 1f \n\t"
b188c81f 7135 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7136 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7137 "1: \n\t"
d3edefc0 7138 /* Reload cr2 if changed */
b188c81f
AK		 7139 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7140 "mov %%cr2, %%" _ASM_DX " \n\t"
7141 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7142 "je 2f \n\t"
b188c81f 7143 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7144 "2: \n\t"
6aa8b732 7145 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7146 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7147 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7148 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7149 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7150 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7151 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7152 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7153 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7154#ifdef CONFIG_X86_64
e08aa78a
AK		 7155 "mov %c[r8](%0), %%r8 \n\t"
7156 "mov %c[r9](%0), %%r9 \n\t"
7157 "mov %c[r10](%0), %%r10 \n\t"
7158 "mov %c[r11](%0), %%r11 \n\t"
7159 "mov %c[r12](%0), %%r12 \n\t"
7160 "mov %c[r13](%0), %%r13 \n\t"
7161 "mov %c[r14](%0), %%r14 \n\t"
7162 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7163#endif
b188c81f 7164 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7165
6aa8b732 7166 /* Enter guest mode */
83287ea4 7167 "jne 1f \n\t"
4ecac3fd 7168 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7169 "jmp 2f \n\t"
7170 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7171 "2: "
6aa8b732 7172 /* Save guest registers, load host registers, keep flags */
b188c81f 7173 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7174 "pop %0 \n\t"
b188c81f
AK		 7175 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7176 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7177 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7178 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7179 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7180 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7181 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7182#ifdef CONFIG_X86_64
e08aa78a
AK		 7183 "mov %%r8, %c[r8](%0) \n\t"
7184 "mov %%r9, %c[r9](%0) \n\t"
7185 "mov %%r10, %c[r10](%0) \n\t"
7186 "mov %%r11, %c[r11](%0) \n\t"
7187 "mov %%r12, %c[r12](%0) \n\t"
7188 "mov %%r13, %c[r13](%0) \n\t"
7189 "mov %%r14, %c[r14](%0) \n\t"
7190 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7191#endif
b188c81f
AK		 7192 "mov %%cr2, %%" _ASM_AX " \n\t"
7193 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7194
b188c81f 7195 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7196 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7197 ".pushsection .rodata \n\t"
7198 ".global vmx_return \n\t"
7199 "vmx_return: " _ASM_PTR " 2b \n\t"
7200 ".popsection"
e08aa78a 7201 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7202 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7203 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7204 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7205 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7206 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7207 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7208 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7209 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7210 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7211 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7212#ifdef CONFIG_X86_64
ad312c7c
ZX		 7213 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7214 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7215 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7216 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7217 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7218 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7219 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7220 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7221#endif
40712fae
AK		 7222 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7223 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7224 : "cc", "memory"
7225#ifdef CONFIG_X86_64
b188c81f 7226 , "rax", "rbx", "rdi", "rsi"
c2036300 7227 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7228#else
7229 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7230#endif
7231 );
6aa8b732 7232
2a7921b7
GN		 7233 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7234 if (debugctlmsr)
7235 update_debugctlmsr(debugctlmsr);
7236
aa67f609
AK		 7237#ifndef CONFIG_X86_64
7238 /*
7239 * The sysexit path does not restore ds/es, so we must set them to
7240 * a reasonable value ourselves.
7241 *
7242 * We can't defer this to vmx_load_host_state() since that function
7243 * may be executed in interrupt context, which saves and restore segments
7244 * around it, nullifying its effect.
7245 */
7246 loadsegment(ds, __USER_DS);
7247 loadsegment(es, __USER_DS);
7248#endif
7249
6de4f3ad 7250 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7251 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7252 | (1 << VCPU_EXREG_CPL)
aff48baa 7253 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7254 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7255 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7256 vcpu->arch.regs_dirty = 0;
7257
1155f76a
AK		 7258 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7259
d462b819 7260 vmx->loaded_vmcs->launched = 1;
1b6269db 7261
51aa01d1 7262 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7263 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 7264
7265 vmx_complete_atomic_exit(vmx);
7266 vmx_recover_nmi_blocking(vmx);
cf393f75 7267 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7268}
7269
6aa8b732
AK		 7270static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7271{
fb3f0f51
RR		 7272 struct vcpu_vmx *vmx = to_vmx(vcpu);
7273
cdbecfc3 7274 free_vpid(vmx);
ec378aee 7275 free_nested(vmx);
d462b819 7276 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7277 kfree(vmx->guest_msrs);
7278 kvm_vcpu_uninit(vcpu);
a4770347 7279 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7280}
7281
fb3f0f51 7282static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7283{
fb3f0f51 7284 int err;
c16f862d 7285 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7286 int cpu;
6aa8b732 7287
a2fa3e9f 7288 if (!vmx)
fb3f0f51
RR		 7289 return ERR_PTR(-ENOMEM);
7290
2384d2b3
SY		 7291 allocate_vpid(vmx);
7292
fb3f0f51
RR		 7293 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7294 if (err)
7295 goto free_vcpu;
965b58a5 7296
a2fa3e9f 7297 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7298 err = -ENOMEM;
fb3f0f51 7299 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7300 goto uninit_vcpu;
7301 }
965b58a5 7302
d462b819
NHE		 7303 vmx->loaded_vmcs = &vmx->vmcs01;
7304 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7305 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7306 goto free_msrs;
d462b819
NHE		 7307 if (!vmm_exclusive)
7308 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7309 loaded_vmcs_init(vmx->loaded_vmcs);
7310 if (!vmm_exclusive)
7311 kvm_cpu_vmxoff();
a2fa3e9f 7312
15ad7146
AK		 7313 cpu = get_cpu();
7314 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7315 vmx->vcpu.cpu = cpu;
8b9cf98c 7316 err = vmx_vcpu_setup(vmx);
fb3f0f51 7317 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7318 put_cpu();
fb3f0f51
RR		 7319 if (err)
7320 goto free_vmcs;
a63cb560 7321 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7322 err = alloc_apic_access_page(kvm);
7323 if (err)
5e4a0b3c 7324 goto free_vmcs;
a63cb560 7325 }
fb3f0f51 7326
b927a3ce
SY		 7327 if (enable_ept) {
7328 if (!kvm->arch.ept_identity_map_addr)
7329 kvm->arch.ept_identity_map_addr =
7330 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7331 err = -ENOMEM;
b7ebfb05
SY		 7332 if (alloc_identity_pagetable(kvm) != 0)
7333 goto free_vmcs;
93ea5388
GN		 7334 if (!init_rmode_identity_map(kvm))
7335 goto free_vmcs;
b927a3ce 7336 }
b7ebfb05 7337
a9d30f33
NHE		 7338 vmx->nested.current_vmptr = -1ull;
7339 vmx->nested.current_vmcs12 = NULL;
7340
fb3f0f51
RR		 7341 return &vmx->vcpu;
7342
7343free_vmcs:
5f3fbc34 7344 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7345free_msrs:
fb3f0f51
RR		 7346 kfree(vmx->guest_msrs);
7347uninit_vcpu:
7348 kvm_vcpu_uninit(&vmx->vcpu);
7349free_vcpu:
cdbecfc3 7350 free_vpid(vmx);
a4770347 7351 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7352 return ERR_PTR(err);
6aa8b732
AK		 7353}
7354
002c7f7c
YS		 7355static void __init vmx_check_processor_compat(void *rtn)
7356{
7357 struct vmcs_config vmcs_conf;
7358
7359 *(int *)rtn = 0;
7360 if (setup_vmcs_config(&vmcs_conf) < 0)
7361 *(int *)rtn = -EIO;
7362 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7363 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7364 smp_processor_id());
7365 *(int *)rtn = -EIO;
7366 }
7367}
7368
67253af5
SY		 7369static int get_ept_level(void)
7370{
7371 return VMX_EPT_DEFAULT_GAW + 1;
7372}
7373
4b12f0de 7374static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7375{
4b12f0de
SY		 7376 u64 ret;
7377
522c68c4
SY		 7378 /* For VT-d and EPT combination
7379 * 1. MMIO: always map as UC
7380 * 2. EPT with VT-d:
7381 * a. VT-d without snooping control feature: can't guarantee the
7382 * result, try to trust guest.
7383 * b. VT-d with snooping control feature: snooping control feature of
7384 * VT-d engine can guarantee the cache correctness. Just set it
7385 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7386 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7387 * consistent with host MTRR
7388 */
4b12f0de
SY		 7389 if (is_mmio)
7390 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7391 else if (vcpu->kvm->arch.iommu_domain &&
7392 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7393 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7394 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7395 else
522c68c4 7396 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7397 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7398
7399 return ret;
64d4d521
SY		 7400}
7401
17cc3935 7402static int vmx_get_lpage_level(void)
344f414f 7403{
878403b7
SY		 7404 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7405 return PT_DIRECTORY_LEVEL;
7406 else
7407 /* For shadow and EPT supported 1GB page */
7408 return PT_PDPE_LEVEL;
344f414f
JR		 7409}
7410
0e851880
SY		 7411static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7412{
4e47c7a6
SY		 7413 struct kvm_cpuid_entry2 *best;
7414 struct vcpu_vmx *vmx = to_vmx(vcpu);
7415 u32 exec_control;
7416
7417 vmx->rdtscp_enabled = false;
7418 if (vmx_rdtscp_supported()) {
7419 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7420 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7421 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7422 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7423 vmx->rdtscp_enabled = true;
7424 else {
7425 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7426 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7427 exec_control);
7428 }
7429 }
7430 }
ad756a16 7431
ad756a16
MJ		 7432 /* Exposing INVPCID only when PCID is exposed */
7433 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7434 if (vmx_invpcid_supported() &&
4f977045 7435 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7436 guest_cpuid_has_pcid(vcpu)) {
29282fde 7437 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7438 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7439 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7440 exec_control);
7441 } else {
29282fde
TI		 7442 if (cpu_has_secondary_exec_ctrls()) {
7443 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7444 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7445 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7446 exec_control);
7447 }
ad756a16 7448 if (best)
4f977045 7449 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7450 }
0e851880
SY		 7451}
7452
d4330ef2
JR		 7453static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7454{
7b8050f5
NHE		 7455 if (func == 1 && nested)
7456 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7457}
7458
25d92081
YZ		 7459static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7460 struct x86_exception *fault)
7461{
7462 struct vmcs12 *vmcs12;
7463 nested_vmx_vmexit(vcpu);
7464 vmcs12 = get_vmcs12(vcpu);
7465
7466 if (fault->error_code & PFERR_RSVD_MASK)
7467 vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
7468 else
7469 vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
7470 vmcs12->exit_qualification = vcpu->arch.exit_qualification;
7471 vmcs12->guest_physical_address = fault->address;
7472}
7473
155a97a3
NHE		 7474/* Callbacks for nested_ept_init_mmu_context: */
7475
7476static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7477{
7478 /* return the page table to be shadowed - in our case, EPT12 */
7479 return get_vmcs12(vcpu)->ept_pointer;
7480}
7481
7482static int nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
7483{
7484 int r = kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
7485 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7486
7487 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7488 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7489 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7490
7491 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
7492
7493 return r;
7494}
7495
7496static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7497{
7498 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7499}
7500
fe3ef05c
NHE		 7501/*
7502 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7503 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7504 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7505 * guest in a way that will both be appropriate to L1's requests, and our
7506 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7507 * function also has additional necessary side-effects, like setting various
7508 * vcpu->arch fields.
7509 */
7510static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7511{
7512 struct vcpu_vmx *vmx = to_vmx(vcpu);
7513 u32 exec_control;
7514
7515 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7516 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7517 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7518 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7519 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7520 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7521 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7522 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7523 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7524 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7525 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7526 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7527 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7528 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7529 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7530 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7531 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7532 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7533 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7534 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7535 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7536 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7537 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7538 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7539 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7540 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7541 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7542 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7543 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7544 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7545 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7546 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7547 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7548 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7549 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7550 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7551
7552 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7553 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7554 vmcs12->vm_entry_intr_info_field);
7555 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7556 vmcs12->vm_entry_exception_error_code);
7557 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7558 vmcs12->vm_entry_instruction_len);
7559 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7560 vmcs12->guest_interruptibility_info);
fe3ef05c 7561 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7562 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
63fbf59f 7563 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7564 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7565 vmcs12->guest_pending_dbg_exceptions);
7566 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7567 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7568
7569 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7570
7571 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7572 (vmcs_config.pin_based_exec_ctrl |
7573 vmcs12->pin_based_vm_exec_control));
7574
0238ea91
JK		 7575 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7576 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7577 vmcs12->vmx_preemption_timer_value);
7578
fe3ef05c
NHE		 7579 /*
7580 * Whether page-faults are trapped is determined by a combination of
7581 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7582 * If enable_ept, L0 doesn't care about page faults and we should
7583 * set all of these to L1's desires. However, if !enable_ept, L0 does
7584 * care about (at least some) page faults, and because it is not easy
7585 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7586 * to exit on each and every L2 page fault. This is done by setting
7587 * MASK=MATCH=0 and (see below) EB.PF=1.
7588 * Note that below we don't need special code to set EB.PF beyond the
7589 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7590 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7591 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7592 *
7593 * A problem with this approach (when !enable_ept) is that L1 may be
7594 * injected with more page faults than it asked for. This could have
7595 * caused problems, but in practice existing hypervisors don't care.
7596 * To fix this, we will need to emulate the PFEC checking (on the L1
7597 * page tables), using walk_addr(), when injecting PFs to L1.
7598 */
7599 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7600 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7601 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7602 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7603
7604 if (cpu_has_secondary_exec_ctrls()) {
7605 u32 exec_control = vmx_secondary_exec_control(vmx);
7606 if (!vmx->rdtscp_enabled)
7607 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7608 /* Take the following fields only from vmcs12 */
7609 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7610 if (nested_cpu_has(vmcs12,
7611 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7612 exec_control |= vmcs12->secondary_vm_exec_control;
7613
7614 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7615 /*
7616 * Translate L1 physical address to host physical
7617 * address for vmcs02. Keep the page pinned, so this
7618 * physical address remains valid. We keep a reference
7619 * to it so we can release it later.
7620 */
7621 if (vmx->nested.apic_access_page) /* shouldn't happen */
7622 nested_release_page(vmx->nested.apic_access_page);
7623 vmx->nested.apic_access_page =
7624 nested_get_page(vcpu, vmcs12->apic_access_addr);
7625 /*
7626 * If translation failed, no matter: This feature asks
7627 * to exit when accessing the given address, and if it
7628 * can never be accessed, this feature won't do
7629 * anything anyway.
7630 */
7631 if (!vmx->nested.apic_access_page)
7632 exec_control &=
7633 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7634 else
7635 vmcs_write64(APIC_ACCESS_ADDR,
7636 page_to_phys(vmx->nested.apic_access_page));
7637 }
7638
7639 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7640 }
7641
7642
7643 /*
7644 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7645 * Some constant fields are set here by vmx_set_constant_host_state().
7646 * Other fields are different per CPU, and will be set later when
7647 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7648 */
a547c6db 7649 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7650
7651 /*
7652 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7653 * entry, but only if the current (host) sp changed from the value
7654 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7655 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7656 * here we just force the write to happen on entry.
7657 */
7658 vmx->host_rsp = 0;
7659
7660 exec_control = vmx_exec_control(vmx); /* L0's desires */
7661 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7662 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7663 exec_control &= ~CPU_BASED_TPR_SHADOW;
7664 exec_control |= vmcs12->cpu_based_vm_exec_control;
7665 /*
7666 * Merging of IO and MSR bitmaps not currently supported.
7667 * Rather, exit every time.
7668 */
7669 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7670 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7671 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7672
7673 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7674
7675 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7676 * bitwise-or of what L1 wants to trap for L2, and what we want to
7677 * trap. Note that CR0.TS also needs updating - we do this later.
7678 */
7679 update_exception_bitmap(vcpu);
7680 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7681 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7682
8049d651
NHE		 7683 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7684 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7685 * bits are further modified by vmx_set_efer() below.
7686 */
7687 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
7688
7689 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7690 * emulated by vmx_set_efer(), below.
7691 */
7692 vmcs_write32(VM_ENTRY_CONTROLS,
7693 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
7694 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 7695 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7696
44811c02 7697 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 7698 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 7699 vcpu->arch.pat = vmcs12->guest_ia32_pat;
7700 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 7701 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7702
7703
7704 set_cr4_guest_host_mask(vmx);
7705
27fc51b2
NHE		 7706 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7707 vmcs_write64(TSC_OFFSET,
7708 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7709 else
7710 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7711
7712 if (enable_vpid) {
7713 /*
7714 * Trivially support vpid by letting L2s share their parent
7715 * L1's vpid. TODO: move to a more elaborate solution, giving
7716 * each L2 its own vpid and exposing the vpid feature to L1.
7717 */
7718 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7719 vmx_flush_tlb(vcpu);
7720 }
7721
155a97a3
NHE		 7722 if (nested_cpu_has_ept(vmcs12)) {
7723 kvm_mmu_unload(vcpu);
7724 nested_ept_init_mmu_context(vcpu);
7725 }
7726
fe3ef05c
NHE		 7727 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7728 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7729 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7730 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7731 else
7732 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7733 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7734 vmx_set_efer(vcpu, vcpu->arch.efer);
7735
7736 /*
7737 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7738 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7739 * The CR0_READ_SHADOW is what L2 should have expected to read given
7740 * the specifications by L1; It's not enough to take
7741 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7742 * have more bits than L1 expected.
7743 */
7744 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7745 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7746
7747 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7748 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7749
7750 /* shadow page tables on either EPT or shadow page tables */
7751 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7752 kvm_mmu_reset_context(vcpu);
7753
3633cfc3
NHE		 7754 /*
7755 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7756 */
7757 if (enable_ept) {
7758 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
7759 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
7760 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
7761 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
7762 }
7763
fe3ef05c
NHE		 7764 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7765 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7766}
7767
cd232ad0
NHE		 7768/*
7769 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7770 * for running an L2 nested guest.
7771 */
7772static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7773{
7774 struct vmcs12 *vmcs12;
7775 struct vcpu_vmx *vmx = to_vmx(vcpu);
7776 int cpu;
7777 struct loaded_vmcs *vmcs02;
384bb783 7778 bool ia32e;
cd232ad0
NHE		 7779
7780 if (!nested_vmx_check_permission(vcpu) ||
7781 !nested_vmx_check_vmcs12(vcpu))
7782 return 1;
7783
7784 skip_emulated_instruction(vcpu);
7785 vmcs12 = get_vmcs12(vcpu);
7786
012f83cb
AG		 7787 if (enable_shadow_vmcs)
7788 copy_shadow_to_vmcs12(vmx);
7789
7c177938
NHE		 7790 /*
7791 * The nested entry process starts with enforcing various prerequisites
7792 * on vmcs12 as required by the Intel SDM, and act appropriately when
7793 * they fail: As the SDM explains, some conditions should cause the
7794 * instruction to fail, while others will cause the instruction to seem
7795 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7796 * To speed up the normal (success) code path, we should avoid checking
7797 * for misconfigurations which will anyway be caught by the processor
7798 * when using the merged vmcs02.
7799 */
7800 if (vmcs12->launch_state == launch) {
7801 nested_vmx_failValid(vcpu,
7802 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7803 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7804 return 1;
7805 }
7806
26539bd0
PB		 7807 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7808 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7809 return 1;
7810 }
7811
7c177938
NHE		 7812 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7813 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7814 /*TODO: Also verify bits beyond physical address width are 0*/
7815 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7816 return 1;
7817 }
7818
7819 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7820 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7821 /*TODO: Also verify bits beyond physical address width are 0*/
7822 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7823 return 1;
7824 }
7825
7826 if (vmcs12->vm_entry_msr_load_count > 0 ||
7827 vmcs12->vm_exit_msr_load_count > 0 ||
7828 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7829 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7830 __func__);
7c177938
NHE		 7831 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7832 return 1;
7833 }
7834
7835 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7836 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7837 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7838 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7839 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7840 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7841 !vmx_control_verify(vmcs12->vm_exit_controls,
7842 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7843 !vmx_control_verify(vmcs12->vm_entry_controls,
7844 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7845 {
7846 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7847 return 1;
7848 }
7849
7850 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7851 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7852 nested_vmx_failValid(vcpu,
7853 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7854 return 1;
7855 }
7856
7857 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7858 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7859 nested_vmx_entry_failure(vcpu, vmcs12,
7860 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7861 return 1;
7862 }
7863 if (vmcs12->vmcs_link_pointer != -1ull) {
7864 nested_vmx_entry_failure(vcpu, vmcs12,
7865 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7866 return 1;
7867 }
7868
384bb783 7869 /*
cb0c8cda 7870 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7871 * are performed on the field for the IA32_EFER MSR:
7872 * - Bits reserved in the IA32_EFER MSR must be 0.
7873 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7874 * the IA-32e mode guest VM-exit control. It must also be identical
7875 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7876 * CR0.PG) is 1.
7877 */
7878 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7879 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7880 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7881 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7882 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7883 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7884 nested_vmx_entry_failure(vcpu, vmcs12,
7885 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7886 return 1;
7887 }
7888 }
7889
7890 /*
7891 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7892 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7893 * the values of the LMA and LME bits in the field must each be that of
7894 * the host address-space size VM-exit control.
7895 */
7896 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7897 ia32e = (vmcs12->vm_exit_controls &
7898 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7899 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7900 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7901 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7902 nested_vmx_entry_failure(vcpu, vmcs12,
7903 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7904 return 1;
7905 }
7906 }
7907
7c177938
NHE		 7908 /*
7909 * We're finally done with prerequisite checking, and can start with
7910 * the nested entry.
7911 */
7912
cd232ad0
NHE		 7913 vmcs02 = nested_get_current_vmcs02(vmx);
7914 if (!vmcs02)
7915 return -ENOMEM;
7916
7917 enter_guest_mode(vcpu);
7918
7919 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7920
7921 cpu = get_cpu();
7922 vmx->loaded_vmcs = vmcs02;
7923 vmx_vcpu_put(vcpu);
7924 vmx_vcpu_load(vcpu, cpu);
7925 vcpu->cpu = cpu;
7926 put_cpu();
7927
36c3cc42
JK		 7928 vmx_segment_cache_clear(vmx);
7929
cd232ad0
NHE		 7930 vmcs12->launch_state = 1;
7931
7932 prepare_vmcs02(vcpu, vmcs12);
7933
7934 /*
7935 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7936 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7937 * returned as far as L1 is concerned. It will only return (and set
7938 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7939 */
7940 return 1;
7941}
7942
4704d0be
NHE		 7943/*
7944 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7945 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7946 * This function returns the new value we should put in vmcs12.guest_cr0.
7947 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7948 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7949 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7950 * didn't trap the bit, because if L1 did, so would L0).
7951 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7952 * been modified by L2, and L1 knows it. So just leave the old value of
7953 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7954 * isn't relevant, because if L0 traps this bit it can set it to anything.
7955 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7956 * changed these bits, and therefore they need to be updated, but L0
7957 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7958 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7959 */
7960static inline unsigned long
7961vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7962{
7963 return
7964 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7965 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7966 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7967 vcpu->arch.cr0_guest_owned_bits));
7968}
7969
7970static inline unsigned long
7971vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7972{
7973 return
7974 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7975 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7976 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7977 vcpu->arch.cr4_guest_owned_bits));
7978}
7979
5f3d5799
JK		 7980static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7981 struct vmcs12 *vmcs12)
7982{
7983 u32 idt_vectoring;
7984 unsigned int nr;
7985
7986 if (vcpu->arch.exception.pending) {
7987 nr = vcpu->arch.exception.nr;
7988 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7989
7990 if (kvm_exception_is_soft(nr)) {
7991 vmcs12->vm_exit_instruction_len =
7992 vcpu->arch.event_exit_inst_len;
7993 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7994 } else
7995 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7996
7997 if (vcpu->arch.exception.has_error_code) {
7998 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7999 vmcs12->idt_vectoring_error_code =
8000 vcpu->arch.exception.error_code;
8001 }
8002
8003 vmcs12->idt_vectoring_info_field = idt_vectoring;
8004 } else if (vcpu->arch.nmi_pending) {
8005 vmcs12->idt_vectoring_info_field =
8006 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8007 } else if (vcpu->arch.interrupt.pending) {
8008 nr = vcpu->arch.interrupt.nr;
8009 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8010
8011 if (vcpu->arch.interrupt.soft) {
8012 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8013 vmcs12->vm_entry_instruction_len =
8014 vcpu->arch.event_exit_inst_len;
8015 } else
8016 idt_vectoring |= INTR_TYPE_EXT_INTR;
8017
8018 vmcs12->idt_vectoring_info_field = idt_vectoring;
8019 }
8020}
8021
4704d0be
NHE		 8022/*
8023 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8024 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8025 * and this function updates it to reflect the changes to the guest state while
8026 * L2 was running (and perhaps made some exits which were handled directly by L0
8027 * without going back to L1), and to reflect the exit reason.
8028 * Note that we do not have to copy here all VMCS fields, just those that
8029 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8030 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8031 * which already writes to vmcs12 directly.
8032 */
733568f9 8033static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 8034{
8035 /* update guest state fields: */
8036 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8037 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8038
8039 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8040 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8041 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8042 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8043
8044 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8045 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8046 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8047 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8048 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8049 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8050 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8051 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8052 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8053 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8054 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8055 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8056 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8057 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8058 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8059 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8060 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8061 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8062 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8063 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8064 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8065 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8066 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8067 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8068 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8069 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8070 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8071 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8072 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8073 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8074 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8075 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8076 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8077 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8078 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8079 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8080
4704d0be
NHE		 8081 vmcs12->guest_interruptibility_info =
8082 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8083 vmcs12->guest_pending_dbg_exceptions =
8084 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
8085
3633cfc3
NHE		 8086 /*
8087 * In some cases (usually, nested EPT), L2 is allowed to change its
8088 * own CR3 without exiting. If it has changed it, we must keep it.
8089 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8090 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8091 *
8092 * Additionally, restore L2's PDPTR to vmcs12.
8093 */
8094 if (enable_ept) {
8095 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8096 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8097 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8098 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8099 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8100 }
8101
c18911a2
JK		 8102 vmcs12->vm_entry_controls =
8103 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
8104 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
8105
4704d0be
NHE		 8106 /* TODO: These cannot have changed unless we have MSR bitmaps and
8107 * the relevant bit asks not to trap the change */
8108 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 8109 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 8110 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
8111 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8112 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8113 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
8114
8115 /* update exit information fields: */
8116
957c897e 8117 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 8118 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
8119
8120 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 8121 if ((vmcs12->vm_exit_intr_info &
8122 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8123 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8124 vmcs12->vm_exit_intr_error_code =
8125 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8126 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8127 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8128 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8129
5f3d5799
JK		 8130 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8131 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8132 * instead of reading the real value. */
4704d0be 8133 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8134
8135 /*
8136 * Transfer the event that L0 or L1 may wanted to inject into
8137 * L2 to IDT_VECTORING_INFO_FIELD.
8138 */
8139 vmcs12_save_pending_event(vcpu, vmcs12);
8140 }
8141
8142 /*
8143 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8144 * preserved above and would only end up incorrectly in L1.
8145 */
8146 vcpu->arch.nmi_injected = false;
8147 kvm_clear_exception_queue(vcpu);
8148 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8149}
8150
8151/*
8152 * A part of what we need to when the nested L2 guest exits and we want to
8153 * run its L1 parent, is to reset L1's guest state to the host state specified
8154 * in vmcs12.
8155 * This function is to be called not only on normal nested exit, but also on
8156 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8157 * Failures During or After Loading Guest State").
8158 * This function should be called when the active VMCS is L1's (vmcs01).
8159 */
733568f9
JK		 8160static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8161 struct vmcs12 *vmcs12)
4704d0be 8162{
21feb4eb
ACL		 8163 struct kvm_segment seg;
8164
4704d0be
NHE		 8165 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8166 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8167 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8168 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8169 else
8170 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8171 vmx_set_efer(vcpu, vcpu->arch.efer);
8172
8173 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8174 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8175 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8176 /*
8177 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8178 * actually changed, because it depends on the current state of
8179 * fpu_active (which may have changed).
8180 * Note that vmx_set_cr0 refers to efer set above.
8181 */
8182 kvm_set_cr0(vcpu, vmcs12->host_cr0);
8183 /*
8184 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8185 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8186 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8187 */
8188 update_exception_bitmap(vcpu);
8189 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8190 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8191
8192 /*
8193 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8194 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8195 */
8196 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8197 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8198
155a97a3
NHE		 8199 if (nested_cpu_has_ept(vmcs12))
8200 nested_ept_uninit_mmu_context(vcpu);
8201
4704d0be
NHE		 8202 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8203 kvm_mmu_reset_context(vcpu);
8204
8205 if (enable_vpid) {
8206 /*
8207 * Trivially support vpid by letting L2s share their parent
8208 * L1's vpid. TODO: move to a more elaborate solution, giving
8209 * each L2 its own vpid and exposing the vpid feature to L1.
8210 */
8211 vmx_flush_tlb(vcpu);
8212 }
8213
8214
8215 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8216 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8217 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8218 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8219 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8220
44811c02 8221 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8222 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8223 vcpu->arch.pat = vmcs12->host_ia32_pat;
8224 }
4704d0be
NHE		 8225 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8226 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8227 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8228
21feb4eb
ACL		 8229 /* Set L1 segment info according to Intel SDM
8230 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8231 seg = (struct kvm_segment) {
8232 .base = 0,
8233 .limit = 0xFFFFFFFF,
8234 .selector = vmcs12->host_cs_selector,
8235 .type = 11,
8236 .present = 1,
8237 .s = 1,
8238 .g = 1
8239 };
8240 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8241 seg.l = 1;
8242 else
8243 seg.db = 1;
8244 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8245 seg = (struct kvm_segment) {
8246 .base = 0,
8247 .limit = 0xFFFFFFFF,
8248 .type = 3,
8249 .present = 1,
8250 .s = 1,
8251 .db = 1,
8252 .g = 1
8253 };
8254 seg.selector = vmcs12->host_ds_selector;
8255 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8256 seg.selector = vmcs12->host_es_selector;
8257 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8258 seg.selector = vmcs12->host_ss_selector;
8259 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8260 seg.selector = vmcs12->host_fs_selector;
8261 seg.base = vmcs12->host_fs_base;
8262 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8263 seg.selector = vmcs12->host_gs_selector;
8264 seg.base = vmcs12->host_gs_base;
8265 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8266 seg = (struct kvm_segment) {
205befd9 8267 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8268 .limit = 0x67,
8269 .selector = vmcs12->host_tr_selector,
8270 .type = 11,
8271 .present = 1
8272 };
8273 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8274
503cd0c5
JK		 8275 kvm_set_dr(vcpu, 7, 0x400);
8276 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8277}
8278
8279/*
8280 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8281 * and modify vmcs12 to make it see what it would expect to see there if
8282 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8283 */
8284static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8285{
8286 struct vcpu_vmx *vmx = to_vmx(vcpu);
8287 int cpu;
8288 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8289
5f3d5799
JK		 8290 /* trying to cancel vmlaunch/vmresume is a bug */
8291 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8292
4704d0be
NHE		 8293 leave_guest_mode(vcpu);
8294 prepare_vmcs12(vcpu, vmcs12);
8295
8296 cpu = get_cpu();
8297 vmx->loaded_vmcs = &vmx->vmcs01;
8298 vmx_vcpu_put(vcpu);
8299 vmx_vcpu_load(vcpu, cpu);
8300 vcpu->cpu = cpu;
8301 put_cpu();
8302
36c3cc42
JK		 8303 vmx_segment_cache_clear(vmx);
8304
4704d0be
NHE		 8305 /* if no vmcs02 cache requested, remove the one we used */
8306 if (VMCS02_POOL_SIZE == 0)
8307 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8308
8309 load_vmcs12_host_state(vcpu, vmcs12);
8310
27fc51b2 8311 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8312 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8313
8314 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8315 vmx->host_rsp = 0;
8316
8317 /* Unpin physical memory we referred to in vmcs02 */
8318 if (vmx->nested.apic_access_page) {
8319 nested_release_page(vmx->nested.apic_access_page);
8320 vmx->nested.apic_access_page = 0;
8321 }
8322
8323 /*
8324 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8325 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8326 * success or failure flag accordingly.
8327 */
8328 if (unlikely(vmx->fail)) {
8329 vmx->fail = 0;
8330 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8331 } else
8332 nested_vmx_succeed(vcpu);
012f83cb
AG		 8333 if (enable_shadow_vmcs)
8334 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8335}
8336
7c177938
NHE		 8337/*
8338 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8339 * 23.7 "VM-entry failures during or after loading guest state" (this also
8340 * lists the acceptable exit-reason and exit-qualification parameters).
8341 * It should only be called before L2 actually succeeded to run, and when
8342 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8343 */
8344static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8345 struct vmcs12 *vmcs12,
8346 u32 reason, unsigned long qualification)
8347{
8348 load_vmcs12_host_state(vcpu, vmcs12);
8349 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8350 vmcs12->exit_qualification = qualification;
8351 nested_vmx_succeed(vcpu);
012f83cb
AG		 8352 if (enable_shadow_vmcs)
8353 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8354}
8355
8a76d7f2
JR		 8356static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8357 struct x86_instruction_info *info,
8358 enum x86_intercept_stage stage)
8359{
8360 return X86EMUL_CONTINUE;
8361}
8362
cbdd1bea 8363static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8364 .cpu_has_kvm_support = cpu_has_kvm_support,
8365 .disabled_by_bios = vmx_disabled_by_bios,
8366 .hardware_setup = hardware_setup,
8367 .hardware_unsetup = hardware_unsetup,
002c7f7c 8368 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8369 .hardware_enable = hardware_enable,
8370 .hardware_disable = hardware_disable,
04547156 8371 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8372
8373 .vcpu_create = vmx_create_vcpu,
8374 .vcpu_free = vmx_free_vcpu,
04d2cc77 8375 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8376
04d2cc77 8377 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8378 .vcpu_load = vmx_vcpu_load,
8379 .vcpu_put = vmx_vcpu_put,
8380
c8639010 8381 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8382 .get_msr = vmx_get_msr,
8383 .set_msr = vmx_set_msr,
8384 .get_segment_base = vmx_get_segment_base,
8385 .get_segment = vmx_get_segment,
8386 .set_segment = vmx_set_segment,
2e4d2653 8387 .get_cpl = vmx_get_cpl,
6aa8b732 8388 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8389 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8390 .decache_cr3 = vmx_decache_cr3,
25c4c276 8391 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8392 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8393 .set_cr3 = vmx_set_cr3,
8394 .set_cr4 = vmx_set_cr4,
6aa8b732 8395 .set_efer = vmx_set_efer,
6aa8b732
AK		 8396 .get_idt = vmx_get_idt,
8397 .set_idt = vmx_set_idt,
8398 .get_gdt = vmx_get_gdt,
8399 .set_gdt = vmx_set_gdt,
020df079 8400 .set_dr7 = vmx_set_dr7,
5fdbf976 8401 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8402 .get_rflags = vmx_get_rflags,
8403 .set_rflags = vmx_set_rflags,
ebcbab4c 8404 .fpu_activate = vmx_fpu_activate,
02daab21 8405 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8406
8407 .tlb_flush = vmx_flush_tlb,
6aa8b732 8408
6aa8b732 8409 .run = vmx_vcpu_run,
6062d012 8410 .handle_exit = vmx_handle_exit,
6aa8b732 8411 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8412 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8413 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8414 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8415 .set_irq = vmx_inject_irq,
95ba8273 8416 .set_nmi = vmx_inject_nmi,
298101da 8417 .queue_exception = vmx_queue_exception,
b463a6f7 8418 .cancel_injection = vmx_cancel_injection,
78646121 8419 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8420 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8421 .get_nmi_mask = vmx_get_nmi_mask,
8422 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8423 .enable_nmi_window = enable_nmi_window,
8424 .enable_irq_window = enable_irq_window,
8425 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8426 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8427 .vm_has_apicv = vmx_vm_has_apicv,
8428 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8429 .hwapic_irr_update = vmx_hwapic_irr_update,
8430 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8431 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8432 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8433
cbc94022 8434 .set_tss_addr = vmx_set_tss_addr,
67253af5 8435 .get_tdp_level = get_ept_level,
4b12f0de 8436 .get_mt_mask = vmx_get_mt_mask,
229456fc 8437
586f9607 8438 .get_exit_info = vmx_get_exit_info,
586f9607 8439
17cc3935 8440 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8441
8442 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8443
8444 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8445 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8446
8447 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8448
8449 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8450
4051b188 8451 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8452 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8453 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8454 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8455 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8456 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8457
8458 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8459
8460 .check_intercept = vmx_check_intercept,
a547c6db 8461 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8462};
8463
8464static int __init vmx_init(void)
8465{
8d14695f 8466 int r, i, msr;
26bb0981
AK		 8467
8468 rdmsrl_safe(MSR_EFER, &host_efer);
8469
8470 for (i = 0; i < NR_VMX_MSR; ++i)
8471 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8472
3e7c73e9 8473 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8474 if (!vmx_io_bitmap_a)
8475 return -ENOMEM;
8476
2106a548
GC		 8477 r = -ENOMEM;
8478
3e7c73e9 8479 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8480 if (!vmx_io_bitmap_b)
fdef3ad1 8481 goto out;
fdef3ad1 8482
5897297b 8483 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8484 if (!vmx_msr_bitmap_legacy)
25c5f225 8485 goto out1;
2106a548 8486
8d14695f
YZ		 8487 vmx_msr_bitmap_legacy_x2apic =
8488 (unsigned long *)__get_free_page(GFP_KERNEL);
8489 if (!vmx_msr_bitmap_legacy_x2apic)
8490 goto out2;
25c5f225 8491
5897297b 8492 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8493 if (!vmx_msr_bitmap_longmode)
8d14695f 8494 goto out3;
2106a548 8495
8d14695f
YZ		 8496 vmx_msr_bitmap_longmode_x2apic =
8497 (unsigned long *)__get_free_page(GFP_KERNEL);
8498 if (!vmx_msr_bitmap_longmode_x2apic)
8499 goto out4;
4607c2d7
AG		 8500 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8501 if (!vmx_vmread_bitmap)
8502 goto out5;
8503
8504 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8505 if (!vmx_vmwrite_bitmap)
8506 goto out6;
8507
8508 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8509 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8510 /* shadowed read/write fields */
8511 for (i = 0; i < max_shadow_read_write_fields; i++) {
8512 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8513 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8514 }
8515 /* shadowed read only fields */
8516 for (i = 0; i < max_shadow_read_only_fields; i++)
8517 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8518
fdef3ad1
HQ		 8519 /*
8520 * Allow direct access to the PC debug port (it is often used for I/O
8521 * delays, but the vmexits simply slow things down).
8522 */
3e7c73e9
AK		 8523 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8524 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8525
3e7c73e9 8526 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8527
5897297b
AK		 8528 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8529 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8530
2384d2b3
SY		 8531 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8532
0ee75bea
AK		 8533 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8534 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8535 if (r)
4607c2d7 8536 goto out7;
25c5f225 8537
8f536b76
ZY		 8538#ifdef CONFIG_KEXEC
8539 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8540 crash_vmclear_local_loaded_vmcss);
8541#endif
8542
5897297b
AK		 8543 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8544 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8545 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8546 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8547 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8548 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8549 memcpy(vmx_msr_bitmap_legacy_x2apic,
8550 vmx_msr_bitmap_legacy, PAGE_SIZE);
8551 memcpy(vmx_msr_bitmap_longmode_x2apic,
8552 vmx_msr_bitmap_longmode, PAGE_SIZE);
8553
01e439be 8554 if (enable_apicv) {
8d14695f
YZ		 8555 for (msr = 0x800; msr <= 0x8ff; msr++)
8556 vmx_disable_intercept_msr_read_x2apic(msr);
8557
8558 /* According SDM, in x2apic mode, the whole id reg is used.
8559 * But in KVM, it only use the highest eight bits. Need to
8560 * intercept it */
8561 vmx_enable_intercept_msr_read_x2apic(0x802);
8562 /* TMCCT */
8563 vmx_enable_intercept_msr_read_x2apic(0x839);
8564 /* TPR */
8565 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8566 /* EOI */
8567 vmx_disable_intercept_msr_write_x2apic(0x80b);
8568 /* SELF-IPI */
8569 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8570 }
fdef3ad1 8571
089d034e 8572 if (enable_ept) {
3f6d8c8a
XH		 8573 kvm_mmu_set_mask_ptes(0ull,
8574 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8575 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8576 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8577 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8578 kvm_enable_tdp();
8579 } else
8580 kvm_disable_tdp();
1439442c 8581
fdef3ad1
HQ		 8582 return 0;
8583
4607c2d7
AG		 8584out7:
8585 free_page((unsigned long)vmx_vmwrite_bitmap);
8586out6:
8587 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8588out5:
8589 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8590out4:
5897297b 8591 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8592out3:
8593 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8594out2:
5897297b 8595 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8596out1:
3e7c73e9 8597 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8598out:
3e7c73e9 8599 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8600 return r;
6aa8b732
AK		 8601}
8602
8603static void __exit vmx_exit(void)
8604{
8d14695f
YZ		 8605 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8606 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8607 free_page((unsigned long)vmx_msr_bitmap_legacy);
8608 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8609 free_page((unsigned long)vmx_io_bitmap_b);
8610 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8611 free_page((unsigned long)vmx_vmwrite_bitmap);
8612 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8613
8f536b76
ZY		 8614#ifdef CONFIG_KEXEC
8615 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8616 synchronize_rcu();
8617#endif
8618
cb498ea2 8619 kvm_exit();
6aa8b732
AK		 8620}
8621
8622module_init(vmx_init)
8623module_exit(vmx_exit)
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