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KVM: nVMX: Fix returned value of MSR_IA32_VMX_VMCS_ENUM
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
f4124500 34#include <linux/hrtimer.h>
5fdbf976 35#include "kvm_cache_regs.h"
35920a35 36#include "x86.h"
e495606d 37
6aa8b732 38#include <asm/io.h>
3b3be0d1 39#include <asm/desc.h>
13673a90 40#include <asm/vmx.h>
6210e37b 41#include <asm/virtext.h>
a0861c02 42#include <asm/mce.h>
2acf923e
DC		 43#include <asm/i387.h>
44#include <asm/xcr.h>
d7cd9796 45#include <asm/perf_event.h>
81908bf4 46#include <asm/debugreg.h>
8f536b76 47#include <asm/kexec.h>
6aa8b732 48
229456fc
MT		 49#include "trace.h"
50
4ecac3fd 51#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 52#define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 54
6aa8b732
AK		 55MODULE_AUTHOR("Qumranet");
56MODULE_LICENSE("GPL");
57
e9bda3b3
JT		 58static const struct x86_cpu_id vmx_cpu_id[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX),
60 {}
61};
62MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
63
476bc001 64static bool __read_mostly enable_vpid = 1;
736caefe 65module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 66
476bc001 67static bool __read_mostly flexpriority_enabled = 1;
736caefe 68module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 69
476bc001 70static bool __read_mostly enable_ept = 1;
736caefe 71module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 72
476bc001 73static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 74module_param_named(unrestricted_guest,
75 enable_unrestricted_guest, bool, S_IRUGO);
76
83c3a331
XH		 77static bool __read_mostly enable_ept_ad_bits = 1;
78module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
79
a27685c3 80static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 81module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 82
476bc001 83static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 84module_param(vmm_exclusive, bool, S_IRUGO);
85
476bc001 86static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 87module_param(fasteoi, bool, S_IRUGO);
88
5a71785d 89static bool __read_mostly enable_apicv = 1;
01e439be 90module_param(enable_apicv, bool, S_IRUGO);
83d4c286 91
abc4fc58
AG		 92static bool __read_mostly enable_shadow_vmcs = 1;
93module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 94/*
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
98 */
476bc001 99static bool __read_mostly nested = 0;
801d3424
NHE		 100module_param(nested, bool, S_IRUGO);
101
5037878e
GN		 102#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 104#define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 106#define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
109
cdc0e244
AK		 110#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
112
78ac8b47
AK		 113#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114
f4124500
JK		 115#define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
116
4b8d54f9
ZE		 117/*
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 121 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
127 */
00c25bce 128#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 129#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
131module_param(ple_gap, int, S_IRUGO);
132
133static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
134module_param(ple_window, int, S_IRUGO);
135
83287ea4
AK		 136extern const ulong vmx_return;
137
8bf00a52 138#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 139#define VMCS02_POOL_SIZE 1
61d2ef2c 140
a2fa3e9f
GH		 141struct vmcs {
142 u32 revision_id;
143 u32 abort;
144 char data[0];
145};
146
d462b819
NHE		 147/*
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
151 */
152struct loaded_vmcs {
153 struct vmcs *vmcs;
154 int cpu;
155 int launched;
156 struct list_head loaded_vmcss_on_cpu_link;
157};
158
26bb0981
AK		 159struct shared_msr_entry {
160 unsigned index;
161 u64 data;
d5696725 162 u64 mask;
26bb0981
AK		 163};
164
a9d30f33
NHE		 165/*
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
177 */
22bd0358 178typedef u64 natural_width;
a9d30f33
NHE		 179struct __packed vmcs12 {
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
182 */
183 u32 revision_id;
184 u32 abort;
22bd0358 185
27d6c865
NHE		 186 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding[7]; /* room for future expansion */
188
22bd0358
NHE		 189 u64 io_bitmap_a;
190 u64 io_bitmap_b;
191 u64 msr_bitmap;
192 u64 vm_exit_msr_store_addr;
193 u64 vm_exit_msr_load_addr;
194 u64 vm_entry_msr_load_addr;
195 u64 tsc_offset;
196 u64 virtual_apic_page_addr;
197 u64 apic_access_addr;
198 u64 ept_pointer;
199 u64 guest_physical_address;
200 u64 vmcs_link_pointer;
201 u64 guest_ia32_debugctl;
202 u64 guest_ia32_pat;
203 u64 guest_ia32_efer;
204 u64 guest_ia32_perf_global_ctrl;
205 u64 guest_pdptr0;
206 u64 guest_pdptr1;
207 u64 guest_pdptr2;
208 u64 guest_pdptr3;
36be0b9d 209 u64 guest_bndcfgs;
22bd0358
NHE		 210 u64 host_ia32_pat;
211 u64 host_ia32_efer;
212 u64 host_ia32_perf_global_ctrl;
213 u64 padding64[8]; /* room for future expansion */
214 /*
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
219 */
220 natural_width cr0_guest_host_mask;
221 natural_width cr4_guest_host_mask;
222 natural_width cr0_read_shadow;
223 natural_width cr4_read_shadow;
224 natural_width cr3_target_value0;
225 natural_width cr3_target_value1;
226 natural_width cr3_target_value2;
227 natural_width cr3_target_value3;
228 natural_width exit_qualification;
229 natural_width guest_linear_address;
230 natural_width guest_cr0;
231 natural_width guest_cr3;
232 natural_width guest_cr4;
233 natural_width guest_es_base;
234 natural_width guest_cs_base;
235 natural_width guest_ss_base;
236 natural_width guest_ds_base;
237 natural_width guest_fs_base;
238 natural_width guest_gs_base;
239 natural_width guest_ldtr_base;
240 natural_width guest_tr_base;
241 natural_width guest_gdtr_base;
242 natural_width guest_idtr_base;
243 natural_width guest_dr7;
244 natural_width guest_rsp;
245 natural_width guest_rip;
246 natural_width guest_rflags;
247 natural_width guest_pending_dbg_exceptions;
248 natural_width guest_sysenter_esp;
249 natural_width guest_sysenter_eip;
250 natural_width host_cr0;
251 natural_width host_cr3;
252 natural_width host_cr4;
253 natural_width host_fs_base;
254 natural_width host_gs_base;
255 natural_width host_tr_base;
256 natural_width host_gdtr_base;
257 natural_width host_idtr_base;
258 natural_width host_ia32_sysenter_esp;
259 natural_width host_ia32_sysenter_eip;
260 natural_width host_rsp;
261 natural_width host_rip;
262 natural_width paddingl[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control;
264 u32 cpu_based_vm_exec_control;
265 u32 exception_bitmap;
266 u32 page_fault_error_code_mask;
267 u32 page_fault_error_code_match;
268 u32 cr3_target_count;
269 u32 vm_exit_controls;
270 u32 vm_exit_msr_store_count;
271 u32 vm_exit_msr_load_count;
272 u32 vm_entry_controls;
273 u32 vm_entry_msr_load_count;
274 u32 vm_entry_intr_info_field;
275 u32 vm_entry_exception_error_code;
276 u32 vm_entry_instruction_len;
277 u32 tpr_threshold;
278 u32 secondary_vm_exec_control;
279 u32 vm_instruction_error;
280 u32 vm_exit_reason;
281 u32 vm_exit_intr_info;
282 u32 vm_exit_intr_error_code;
283 u32 idt_vectoring_info_field;
284 u32 idt_vectoring_error_code;
285 u32 vm_exit_instruction_len;
286 u32 vmx_instruction_info;
287 u32 guest_es_limit;
288 u32 guest_cs_limit;
289 u32 guest_ss_limit;
290 u32 guest_ds_limit;
291 u32 guest_fs_limit;
292 u32 guest_gs_limit;
293 u32 guest_ldtr_limit;
294 u32 guest_tr_limit;
295 u32 guest_gdtr_limit;
296 u32 guest_idtr_limit;
297 u32 guest_es_ar_bytes;
298 u32 guest_cs_ar_bytes;
299 u32 guest_ss_ar_bytes;
300 u32 guest_ds_ar_bytes;
301 u32 guest_fs_ar_bytes;
302 u32 guest_gs_ar_bytes;
303 u32 guest_ldtr_ar_bytes;
304 u32 guest_tr_ar_bytes;
305 u32 guest_interruptibility_info;
306 u32 guest_activity_state;
307 u32 guest_sysenter_cs;
308 u32 host_ia32_sysenter_cs;
0238ea91
JK		 309 u32 vmx_preemption_timer_value;
310 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 311 u16 virtual_processor_id;
312 u16 guest_es_selector;
313 u16 guest_cs_selector;
314 u16 guest_ss_selector;
315 u16 guest_ds_selector;
316 u16 guest_fs_selector;
317 u16 guest_gs_selector;
318 u16 guest_ldtr_selector;
319 u16 guest_tr_selector;
320 u16 host_es_selector;
321 u16 host_cs_selector;
322 u16 host_ss_selector;
323 u16 host_ds_selector;
324 u16 host_fs_selector;
325 u16 host_gs_selector;
326 u16 host_tr_selector;
a9d30f33
NHE		 327};
328
329/*
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
333 */
334#define VMCS12_REVISION 0x11e57ed0
335
336/*
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
340 */
341#define VMCS12_SIZE 0x1000
342
ff2f6fe9
NHE		 343/* Used to remember the last vmcs02 used for some recently used vmcs12s */
344struct vmcs02_list {
345 struct list_head list;
346 gpa_t vmptr;
347 struct loaded_vmcs vmcs02;
348};
349
ec378aee
NHE		 350/*
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
353 */
354struct nested_vmx {
355 /* Has the level1 guest done vmxon? */
356 bool vmxon;
3573e22c 357 gpa_t vmxon_ptr;
a9d30f33
NHE		 358
359 /* The guest-physical address of the current VMCS L1 keeps for L2 */
360 gpa_t current_vmptr;
361 /* The host-usable pointer to the above */
362 struct page *current_vmcs12_page;
363 struct vmcs12 *current_vmcs12;
8de48833 364 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 365 /*
366 * Indicates if the shadow vmcs must be updated with the
367 * data hold by vmcs12
368 */
369 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 370
371 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
372 struct list_head vmcs02_pool;
373 int vmcs02_num;
fe3ef05c 374 u64 vmcs01_tsc_offset;
644d711a
NHE		 375 /* L2 must run next, and mustn't decide to exit to L1. */
376 bool nested_run_pending;
fe3ef05c
NHE		 377 /*
378 * Guest pages referred to in vmcs02 with host-physical pointers, so
379 * we must keep them pinned while L2 runs.
380 */
381 struct page *apic_access_page;
b3897a49 382 u64 msr_ia32_feature_control;
f4124500
JK		 383
384 struct hrtimer preemption_timer;
385 bool preemption_timer_expired;
2996fca0
JK		 386
387 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
388 u64 vmcs01_debugctl;
ec378aee
NHE		 389};
390
01e439be
YZ		 391#define POSTED_INTR_ON 0
392/* Posted-Interrupt Descriptor */
393struct pi_desc {
394 u32 pir[8]; /* Posted interrupt requested */
395 u32 control; /* bit 0 of control is outstanding notification bit */
396 u32 rsvd[7];
397} __aligned(64);
398
a20ed54d
YZ		 399static bool pi_test_and_set_on(struct pi_desc *pi_desc)
400{
401 return test_and_set_bit(POSTED_INTR_ON,
402 (unsigned long *)&pi_desc->control);
403}
404
405static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
406{
407 return test_and_clear_bit(POSTED_INTR_ON,
408 (unsigned long *)&pi_desc->control);
409}
410
411static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
412{
413 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
414}
415
a2fa3e9f 416struct vcpu_vmx {
fb3f0f51 417 struct kvm_vcpu vcpu;
313dbd49 418 unsigned long host_rsp;
29bd8a78 419 u8 fail;
9d58b931 420 bool nmi_known_unmasked;
51aa01d1 421 u32 exit_intr_info;
1155f76a 422 u32 idt_vectoring_info;
6de12732 423 ulong rflags;
26bb0981 424 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 425 int nmsrs;
426 int save_nmsrs;
a547c6db 427 unsigned long host_idt_base;
a2fa3e9f 428#ifdef CONFIG_X86_64
44ea2b17
AK		 429 u64 msr_host_kernel_gs_base;
430 u64 msr_guest_kernel_gs_base;
a2fa3e9f 431#endif
2961e876
GN		 432 u32 vm_entry_controls_shadow;
433 u32 vm_exit_controls_shadow;
d462b819
NHE		 434 /*
435 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
436 * non-nested (L1) guest, it always points to vmcs01. For a nested
437 * guest (L2), it points to a different VMCS.
438 */
439 struct loaded_vmcs vmcs01;
440 struct loaded_vmcs *loaded_vmcs;
441 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 442 struct msr_autoload {
443 unsigned nr;
444 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
445 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
446 } msr_autoload;
a2fa3e9f
GH		 447 struct {
448 int loaded;
449 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 450#ifdef CONFIG_X86_64
451 u16 ds_sel, es_sel;
452#endif
152d3f2f
LV		 453 int gs_ldt_reload_needed;
454 int fs_reload_needed;
da8999d3 455 u64 msr_host_bndcfgs;
d77c26fc 456 } host_state;
9c8cba37 457 struct {
7ffd92c5 458 int vm86_active;
78ac8b47 459 ulong save_rflags;
f5f7b2fe
AK		 460 struct kvm_segment segs[8];
461 } rmode;
462 struct {
463 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 464 struct kvm_save_segment {
465 u16 selector;
466 unsigned long base;
467 u32 limit;
468 u32 ar;
f5f7b2fe 469 } seg[8];
2fb92db1 470 } segment_cache;
2384d2b3 471 int vpid;
04fa4d32 472 bool emulation_required;
3b86cd99
JK		 473
474 /* Support for vnmi-less CPUs */
475 int soft_vnmi_blocked;
476 ktime_t entry_time;
477 s64 vnmi_blocked_time;
a0861c02 478 u32 exit_reason;
4e47c7a6
SY		 479
480 bool rdtscp_enabled;
ec378aee 481
01e439be
YZ		 482 /* Posted interrupt descriptor */
483 struct pi_desc pi_desc;
484
ec378aee
NHE		 485 /* Support for a guest hypervisor (nested VMX) */
486 struct nested_vmx nested;
a2fa3e9f
GH		 487};
488
2fb92db1
AK		 489enum segment_cache_field {
490 SEG_FIELD_SEL = 0,
491 SEG_FIELD_BASE = 1,
492 SEG_FIELD_LIMIT = 2,
493 SEG_FIELD_AR = 3,
494
495 SEG_FIELD_NR = 4
496};
497
a2fa3e9f
GH		 498static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
499{
fb3f0f51 500 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 501}
502
22bd0358
NHE		 503#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
504#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
505#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
506 [number##_HIGH] = VMCS12_OFFSET(name)+4
507
4607c2d7 508
fe2b201b 509static unsigned long shadow_read_only_fields[] = {
4607c2d7
AG		 510 /*
511 * We do NOT shadow fields that are modified when L0
512 * traps and emulates any vmx instruction (e.g. VMPTRLD,
513 * VMXON...) executed by L1.
514 * For example, VM_INSTRUCTION_ERROR is read
515 * by L1 if a vmx instruction fails (part of the error path).
516 * Note the code assumes this logic. If for some reason
517 * we start shadowing these fields then we need to
518 * force a shadow sync when L0 emulates vmx instructions
519 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
520 * by nested_vmx_failValid)
521 */
522 VM_EXIT_REASON,
523 VM_EXIT_INTR_INFO,
524 VM_EXIT_INSTRUCTION_LEN,
525 IDT_VECTORING_INFO_FIELD,
526 IDT_VECTORING_ERROR_CODE,
527 VM_EXIT_INTR_ERROR_CODE,
528 EXIT_QUALIFICATION,
529 GUEST_LINEAR_ADDRESS,
530 GUEST_PHYSICAL_ADDRESS
531};
fe2b201b 532static int max_shadow_read_only_fields =
4607c2d7
AG		 533 ARRAY_SIZE(shadow_read_only_fields);
534
fe2b201b 535static unsigned long shadow_read_write_fields[] = {
4607c2d7
AG		 536 GUEST_RIP,
537 GUEST_RSP,
538 GUEST_CR0,
539 GUEST_CR3,
540 GUEST_CR4,
541 GUEST_INTERRUPTIBILITY_INFO,
542 GUEST_RFLAGS,
543 GUEST_CS_SELECTOR,
544 GUEST_CS_AR_BYTES,
545 GUEST_CS_LIMIT,
546 GUEST_CS_BASE,
547 GUEST_ES_BASE,
36be0b9d 548 GUEST_BNDCFGS,
4607c2d7
AG		 549 CR0_GUEST_HOST_MASK,
550 CR0_READ_SHADOW,
551 CR4_READ_SHADOW,
552 TSC_OFFSET,
553 EXCEPTION_BITMAP,
554 CPU_BASED_VM_EXEC_CONTROL,
555 VM_ENTRY_EXCEPTION_ERROR_CODE,
556 VM_ENTRY_INTR_INFO_FIELD,
557 VM_ENTRY_INSTRUCTION_LEN,
558 VM_ENTRY_EXCEPTION_ERROR_CODE,
559 HOST_FS_BASE,
560 HOST_GS_BASE,
561 HOST_FS_SELECTOR,
562 HOST_GS_SELECTOR
563};
fe2b201b 564static int max_shadow_read_write_fields =
4607c2d7
AG		 565 ARRAY_SIZE(shadow_read_write_fields);
566
772e0318 567static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 568 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
569 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
570 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
571 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
572 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
573 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
574 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
575 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
576 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
577 FIELD(HOST_ES_SELECTOR, host_es_selector),
578 FIELD(HOST_CS_SELECTOR, host_cs_selector),
579 FIELD(HOST_SS_SELECTOR, host_ss_selector),
580 FIELD(HOST_DS_SELECTOR, host_ds_selector),
581 FIELD(HOST_FS_SELECTOR, host_fs_selector),
582 FIELD(HOST_GS_SELECTOR, host_gs_selector),
583 FIELD(HOST_TR_SELECTOR, host_tr_selector),
584 FIELD64(IO_BITMAP_A, io_bitmap_a),
585 FIELD64(IO_BITMAP_B, io_bitmap_b),
586 FIELD64(MSR_BITMAP, msr_bitmap),
587 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
588 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
589 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
590 FIELD64(TSC_OFFSET, tsc_offset),
591 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
592 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
593 FIELD64(EPT_POINTER, ept_pointer),
594 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
595 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
596 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
597 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
598 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
599 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
600 FIELD64(GUEST_PDPTR0, guest_pdptr0),
601 FIELD64(GUEST_PDPTR1, guest_pdptr1),
602 FIELD64(GUEST_PDPTR2, guest_pdptr2),
603 FIELD64(GUEST_PDPTR3, guest_pdptr3),
36be0b9d 604 FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
22bd0358
NHE		 605 FIELD64(HOST_IA32_PAT, host_ia32_pat),
606 FIELD64(HOST_IA32_EFER, host_ia32_efer),
607 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
608 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
609 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
610 FIELD(EXCEPTION_BITMAP, exception_bitmap),
611 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
612 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
613 FIELD(CR3_TARGET_COUNT, cr3_target_count),
614 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
615 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
616 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
617 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
618 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
619 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
620 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
621 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
622 FIELD(TPR_THRESHOLD, tpr_threshold),
623 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
624 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
625 FIELD(VM_EXIT_REASON, vm_exit_reason),
626 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
627 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
628 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
629 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
630 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
631 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
632 FIELD(GUEST_ES_LIMIT, guest_es_limit),
633 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
634 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
635 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
636 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
637 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
638 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
639 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
640 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
641 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
642 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
643 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
644 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
645 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
646 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
647 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
648 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
649 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
650 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
651 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
652 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
653 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 654 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 655 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
656 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
657 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
658 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
659 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
660 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
661 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
662 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
663 FIELD(EXIT_QUALIFICATION, exit_qualification),
664 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
665 FIELD(GUEST_CR0, guest_cr0),
666 FIELD(GUEST_CR3, guest_cr3),
667 FIELD(GUEST_CR4, guest_cr4),
668 FIELD(GUEST_ES_BASE, guest_es_base),
669 FIELD(GUEST_CS_BASE, guest_cs_base),
670 FIELD(GUEST_SS_BASE, guest_ss_base),
671 FIELD(GUEST_DS_BASE, guest_ds_base),
672 FIELD(GUEST_FS_BASE, guest_fs_base),
673 FIELD(GUEST_GS_BASE, guest_gs_base),
674 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
675 FIELD(GUEST_TR_BASE, guest_tr_base),
676 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
677 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
678 FIELD(GUEST_DR7, guest_dr7),
679 FIELD(GUEST_RSP, guest_rsp),
680 FIELD(GUEST_RIP, guest_rip),
681 FIELD(GUEST_RFLAGS, guest_rflags),
682 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
683 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
684 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
685 FIELD(HOST_CR0, host_cr0),
686 FIELD(HOST_CR3, host_cr3),
687 FIELD(HOST_CR4, host_cr4),
688 FIELD(HOST_FS_BASE, host_fs_base),
689 FIELD(HOST_GS_BASE, host_gs_base),
690 FIELD(HOST_TR_BASE, host_tr_base),
691 FIELD(HOST_GDTR_BASE, host_gdtr_base),
692 FIELD(HOST_IDTR_BASE, host_idtr_base),
693 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
694 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
695 FIELD(HOST_RSP, host_rsp),
696 FIELD(HOST_RIP, host_rip),
697};
698static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
699
700static inline short vmcs_field_to_offset(unsigned long field)
701{
702 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
703 return -1;
704 return vmcs_field_to_offset_table[field];
705}
706
a9d30f33
NHE		 707static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
708{
709 return to_vmx(vcpu)->nested.current_vmcs12;
710}
711
712static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
713{
714 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 715 if (is_error_page(page))
a9d30f33 716 return NULL;
32cad84f 717
a9d30f33
NHE		 718 return page;
719}
720
721static void nested_release_page(struct page *page)
722{
723 kvm_release_page_dirty(page);
724}
725
726static void nested_release_page_clean(struct page *page)
727{
728 kvm_release_page_clean(page);
729}
730
bfd0a56b 731static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
4e1096d2 732static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 733static void kvm_cpu_vmxon(u64 addr);
734static void kvm_cpu_vmxoff(void);
93c4adc7 735static bool vmx_mpx_supported(void);
776e58ea 736static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 737static void vmx_set_segment(struct kvm_vcpu *vcpu,
738 struct kvm_segment *var, int seg);
739static void vmx_get_segment(struct kvm_vcpu *vcpu,
740 struct kvm_segment *var, int seg);
d99e4152
GN		 741static bool guest_state_valid(struct kvm_vcpu *vcpu);
742static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 743static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 744static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 745static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
36be0b9d 746static bool vmx_mpx_supported(void);
75880a01 747
6aa8b732
AK		 748static DEFINE_PER_CPU(struct vmcs *, vmxarea);
749static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 750/*
751 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
752 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
753 */
754static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 755static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 756
3e7c73e9
AK		 757static unsigned long *vmx_io_bitmap_a;
758static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 759static unsigned long *vmx_msr_bitmap_legacy;
760static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 761static unsigned long *vmx_msr_bitmap_legacy_x2apic;
762static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 763static unsigned long *vmx_vmread_bitmap;
764static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 765
110312c8 766static bool cpu_has_load_ia32_efer;
8bf00a52 767static bool cpu_has_load_perf_global_ctrl;
110312c8 768
2384d2b3
SY		 769static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
770static DEFINE_SPINLOCK(vmx_vpid_lock);
771
1c3d14fe 772static struct vmcs_config {
6aa8b732
AK		 773 int size;
774 int order;
775 u32 revision_id;
1c3d14fe
YS		 776 u32 pin_based_exec_ctrl;
777 u32 cpu_based_exec_ctrl;
f78e0e2e 778 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 779 u32 vmexit_ctrl;
780 u32 vmentry_ctrl;
781} vmcs_config;
6aa8b732 782
efff9e53 783static struct vmx_capability {
d56f546d
SY		 784 u32 ept;
785 u32 vpid;
786} vmx_capability;
787
6aa8b732
AK		 788#define VMX_SEGMENT_FIELD(seg) \
789 [VCPU_SREG_##seg] = { \
790 .selector = GUEST_##seg##_SELECTOR, \
791 .base = GUEST_##seg##_BASE, \
792 .limit = GUEST_##seg##_LIMIT, \
793 .ar_bytes = GUEST_##seg##_AR_BYTES, \
794 }
795
772e0318 796static const struct kvm_vmx_segment_field {
6aa8b732
AK		 797 unsigned selector;
798 unsigned base;
799 unsigned limit;
800 unsigned ar_bytes;
801} kvm_vmx_segment_fields[] = {
802 VMX_SEGMENT_FIELD(CS),
803 VMX_SEGMENT_FIELD(DS),
804 VMX_SEGMENT_FIELD(ES),
805 VMX_SEGMENT_FIELD(FS),
806 VMX_SEGMENT_FIELD(GS),
807 VMX_SEGMENT_FIELD(SS),
808 VMX_SEGMENT_FIELD(TR),
809 VMX_SEGMENT_FIELD(LDTR),
810};
811
26bb0981
AK		 812static u64 host_efer;
813
6de4f3ad
AK		 814static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
815
4d56c8a7 816/*
8c06585d 817 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 818 * away by decrementing the array size.
819 */
6aa8b732 820static const u32 vmx_msr_index[] = {
05b3e0c2 821#ifdef CONFIG_X86_64
44ea2b17 822 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 823#endif
8c06585d 824 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 825};
9d8f549d 826#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 827
31299944 828static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 829{
830 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
831 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 832 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 833}
834
31299944 835static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 836{
837 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
838 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 839 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 840}
841
31299944 842static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 843{
844 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
845 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 846 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 847}
848
31299944 849static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 850{
851 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
852 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
853}
854
31299944 855static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 856{
857 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
858 INTR_INFO_VALID_MASK)) ==
859 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
860}
861
31299944 862static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 863{
04547156 864 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 865}
866
31299944 867static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 868{
04547156 869 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 870}
871
31299944 872static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 873{
04547156 874 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 875}
876
31299944 877static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 878{
04547156
SY		 879 return vmcs_config.cpu_based_exec_ctrl &
880 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 881}
882
774ead3a 883static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 884{
04547156
SY		 885 return vmcs_config.cpu_based_2nd_exec_ctrl &
886 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
887}
888
8d14695f
YZ		 889static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
890{
891 return vmcs_config.cpu_based_2nd_exec_ctrl &
892 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
893}
894
83d4c286
YZ		 895static inline bool cpu_has_vmx_apic_register_virt(void)
896{
897 return vmcs_config.cpu_based_2nd_exec_ctrl &
898 SECONDARY_EXEC_APIC_REGISTER_VIRT;
899}
900
c7c9c56c
YZ		 901static inline bool cpu_has_vmx_virtual_intr_delivery(void)
902{
903 return vmcs_config.cpu_based_2nd_exec_ctrl &
904 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
905}
906
01e439be
YZ		 907static inline bool cpu_has_vmx_posted_intr(void)
908{
909 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
910}
911
912static inline bool cpu_has_vmx_apicv(void)
913{
914 return cpu_has_vmx_apic_register_virt() &&
915 cpu_has_vmx_virtual_intr_delivery() &&
916 cpu_has_vmx_posted_intr();
917}
918
04547156
SY		 919static inline bool cpu_has_vmx_flexpriority(void)
920{
921 return cpu_has_vmx_tpr_shadow() &&
922 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 923}
924
e799794e
MT		 925static inline bool cpu_has_vmx_ept_execute_only(void)
926{
31299944 927 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 928}
929
930static inline bool cpu_has_vmx_eptp_uncacheable(void)
931{
31299944 932 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 933}
934
935static inline bool cpu_has_vmx_eptp_writeback(void)
936{
31299944 937 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 938}
939
940static inline bool cpu_has_vmx_ept_2m_page(void)
941{
31299944 942 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 943}
944
878403b7
SY		 945static inline bool cpu_has_vmx_ept_1g_page(void)
946{
31299944 947 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 948}
949
4bc9b982
SY		 950static inline bool cpu_has_vmx_ept_4levels(void)
951{
952 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
953}
954
83c3a331
XH		 955static inline bool cpu_has_vmx_ept_ad_bits(void)
956{
957 return vmx_capability.ept & VMX_EPT_AD_BIT;
958}
959
31299944 960static inline bool cpu_has_vmx_invept_context(void)
d56f546d 961{
31299944 962 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 963}
964
31299944 965static inline bool cpu_has_vmx_invept_global(void)
d56f546d 966{
31299944 967 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 968}
969
518c8aee
GJ		 970static inline bool cpu_has_vmx_invvpid_single(void)
971{
972 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
973}
974
b9d762fa
GJ		 975static inline bool cpu_has_vmx_invvpid_global(void)
976{
977 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
978}
979
31299944 980static inline bool cpu_has_vmx_ept(void)
d56f546d 981{
04547156
SY		 982 return vmcs_config.cpu_based_2nd_exec_ctrl &
983 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 984}
985
31299944 986static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 987{
988 return vmcs_config.cpu_based_2nd_exec_ctrl &
989 SECONDARY_EXEC_UNRESTRICTED_GUEST;
990}
991
31299944 992static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 993{
994 return vmcs_config.cpu_based_2nd_exec_ctrl &
995 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
996}
997
31299944 998static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 999{
6d3e435e 1000 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 1001}
1002
31299944 1003static inline bool cpu_has_vmx_vpid(void)
2384d2b3 1004{
04547156
SY		 1005 return vmcs_config.cpu_based_2nd_exec_ctrl &
1006 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 1007}
1008
31299944 1009static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 1010{
1011 return vmcs_config.cpu_based_2nd_exec_ctrl &
1012 SECONDARY_EXEC_RDTSCP;
1013}
1014
ad756a16
MJ		 1015static inline bool cpu_has_vmx_invpcid(void)
1016{
1017 return vmcs_config.cpu_based_2nd_exec_ctrl &
1018 SECONDARY_EXEC_ENABLE_INVPCID;
1019}
1020
31299944 1021static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1022{
1023 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1024}
1025
f5f48ee1
SY		 1026static inline bool cpu_has_vmx_wbinvd_exit(void)
1027{
1028 return vmcs_config.cpu_based_2nd_exec_ctrl &
1029 SECONDARY_EXEC_WBINVD_EXITING;
1030}
1031
abc4fc58
AG		 1032static inline bool cpu_has_vmx_shadow_vmcs(void)
1033{
1034 u64 vmx_msr;
1035 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1036 /* check if the cpu supports writing r/o exit information fields */
1037 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1038 return false;
1039
1040 return vmcs_config.cpu_based_2nd_exec_ctrl &
1041 SECONDARY_EXEC_SHADOW_VMCS;
1042}
1043
04547156
SY		 1044static inline bool report_flexpriority(void)
1045{
1046 return flexpriority_enabled;
1047}
1048
fe3ef05c
NHE		 1049static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1050{
1051 return vmcs12->cpu_based_vm_exec_control & bit;
1052}
1053
1054static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1055{
1056 return (vmcs12->cpu_based_vm_exec_control &
1057 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1058 (vmcs12->secondary_vm_exec_control & bit);
1059}
1060
f5c4368f 1061static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
644d711a
NHE		 1062{
1063 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1064}
1065
f4124500
JK		 1066static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1067{
1068 return vmcs12->pin_based_vm_exec_control &
1069 PIN_BASED_VMX_PREEMPTION_TIMER;
1070}
1071
155a97a3
NHE		 1072static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1073{
1074 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1075}
1076
644d711a
NHE		 1077static inline bool is_exception(u32 intr_info)
1078{
1079 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1080 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1081}
1082
533558bc
JK		 1083static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1084 u32 exit_intr_info,
1085 unsigned long exit_qualification);
7c177938
NHE		 1086static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1087 struct vmcs12 *vmcs12,
1088 u32 reason, unsigned long qualification);
1089
8b9cf98c 1090static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1091{
1092 int i;
1093
a2fa3e9f 1094 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1095 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1096 return i;
1097 return -1;
1098}
1099
2384d2b3
SY		 1100static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1101{
1102 struct {
1103 u64 vpid : 16;
1104 u64 rsvd : 48;
1105 u64 gva;
1106 } operand = { vpid, 0, gva };
1107
4ecac3fd 1108 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1109 /* CF==1 or ZF==1 --> rc = -1 */
1110 "; ja 1f ; ud2 ; 1:"
1111 : : "a"(&operand), "c"(ext) : "cc", "memory");
1112}
1113
1439442c
SY		 1114static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1115{
1116 struct {
1117 u64 eptp, gpa;
1118 } operand = {eptp, gpa};
1119
4ecac3fd 1120 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1121 /* CF==1 or ZF==1 --> rc = -1 */
1122 "; ja 1f ; ud2 ; 1:\n"
1123 : : "a" (&operand), "c" (ext) : "cc", "memory");
1124}
1125
26bb0981 1126static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1127{
1128 int i;
1129
8b9cf98c 1130 i = __find_msr_index(vmx, msr);
a75beee6 1131 if (i >= 0)
a2fa3e9f 1132 return &vmx->guest_msrs[i];
8b6d44c7 1133 return NULL;
7725f0ba
AK		 1134}
1135
6aa8b732
AK		 1136static void vmcs_clear(struct vmcs *vmcs)
1137{
1138 u64 phys_addr = __pa(vmcs);
1139 u8 error;
1140
4ecac3fd 1141 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1142 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1143 : "cc", "memory");
1144 if (error)
1145 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1146 vmcs, phys_addr);
1147}
1148
d462b819
NHE		 1149static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1150{
1151 vmcs_clear(loaded_vmcs->vmcs);
1152 loaded_vmcs->cpu = -1;
1153 loaded_vmcs->launched = 0;
1154}
1155
7725b894
DX		 1156static void vmcs_load(struct vmcs *vmcs)
1157{
1158 u64 phys_addr = __pa(vmcs);
1159 u8 error;
1160
1161 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1162 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1163 : "cc", "memory");
1164 if (error)
2844d849 1165 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1166 vmcs, phys_addr);
1167}
1168
8f536b76
ZY		 1169#ifdef CONFIG_KEXEC
1170/*
1171 * This bitmap is used to indicate whether the vmclear
1172 * operation is enabled on all cpus. All disabled by
1173 * default.
1174 */
1175static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1176
1177static inline void crash_enable_local_vmclear(int cpu)
1178{
1179 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1180}
1181
1182static inline void crash_disable_local_vmclear(int cpu)
1183{
1184 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1185}
1186
1187static inline int crash_local_vmclear_enabled(int cpu)
1188{
1189 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1190}
1191
1192static void crash_vmclear_local_loaded_vmcss(void)
1193{
1194 int cpu = raw_smp_processor_id();
1195 struct loaded_vmcs *v;
1196
1197 if (!crash_local_vmclear_enabled(cpu))
1198 return;
1199
1200 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1201 loaded_vmcss_on_cpu_link)
1202 vmcs_clear(v->vmcs);
1203}
1204#else
1205static inline void crash_enable_local_vmclear(int cpu) { }
1206static inline void crash_disable_local_vmclear(int cpu) { }
1207#endif /* CONFIG_KEXEC */
1208
d462b819 1209static void __loaded_vmcs_clear(void *arg)
6aa8b732 1210{
d462b819 1211 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1212 int cpu = raw_smp_processor_id();
6aa8b732 1213
d462b819
NHE		 1214 if (loaded_vmcs->cpu != cpu)
1215 return; /* vcpu migration can race with cpu offline */
1216 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1217 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1218 crash_disable_local_vmclear(cpu);
d462b819 1219 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1220
1221 /*
1222 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1223 * is before setting loaded_vmcs->vcpu to -1 which is done in
1224 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1225 * then adds the vmcs into percpu list before it is deleted.
1226 */
1227 smp_wmb();
1228
d462b819 1229 loaded_vmcs_init(loaded_vmcs);
8f536b76 1230 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1231}
1232
d462b819 1233static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1234{
e6c7d321
XG		 1235 int cpu = loaded_vmcs->cpu;
1236
1237 if (cpu != -1)
1238 smp_call_function_single(cpu,
1239 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1240}
1241
1760dd49 1242static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1243{
1244 if (vmx->vpid == 0)
1245 return;
1246
518c8aee
GJ		 1247 if (cpu_has_vmx_invvpid_single())
1248 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1249}
1250
b9d762fa
GJ		 1251static inline void vpid_sync_vcpu_global(void)
1252{
1253 if (cpu_has_vmx_invvpid_global())
1254 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1255}
1256
1257static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1258{
1259 if (cpu_has_vmx_invvpid_single())
1760dd49 1260 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1261 else
1262 vpid_sync_vcpu_global();
1263}
1264
1439442c
SY		 1265static inline void ept_sync_global(void)
1266{
1267 if (cpu_has_vmx_invept_global())
1268 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1269}
1270
1271static inline void ept_sync_context(u64 eptp)
1272{
089d034e 1273 if (enable_ept) {
1439442c
SY		 1274 if (cpu_has_vmx_invept_context())
1275 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1276 else
1277 ept_sync_global();
1278 }
1279}
1280
96304217 1281static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1282{
5e520e62 1283 unsigned long value;
6aa8b732 1284
5e520e62
AK		 1285 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1286 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1287 return value;
1288}
1289
96304217 1290static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1291{
1292 return vmcs_readl(field);
1293}
1294
96304217 1295static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1296{
1297 return vmcs_readl(field);
1298}
1299
96304217 1300static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1301{
05b3e0c2 1302#ifdef CONFIG_X86_64
6aa8b732
AK		 1303 return vmcs_readl(field);
1304#else
1305 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1306#endif
1307}
1308
e52de1b8
AK		 1309static noinline void vmwrite_error(unsigned long field, unsigned long value)
1310{
1311 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1312 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1313 dump_stack();
1314}
1315
6aa8b732
AK		 1316static void vmcs_writel(unsigned long field, unsigned long value)
1317{
1318 u8 error;
1319
4ecac3fd 1320 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1321 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1322 if (unlikely(error))
1323 vmwrite_error(field, value);
6aa8b732
AK		 1324}
1325
1326static void vmcs_write16(unsigned long field, u16 value)
1327{
1328 vmcs_writel(field, value);
1329}
1330
1331static void vmcs_write32(unsigned long field, u32 value)
1332{
1333 vmcs_writel(field, value);
1334}
1335
1336static void vmcs_write64(unsigned long field, u64 value)
1337{
6aa8b732 1338 vmcs_writel(field, value);
7682f2d0 1339#ifndef CONFIG_X86_64
6aa8b732
AK		 1340 asm volatile ("");
1341 vmcs_writel(field+1, value >> 32);
1342#endif
1343}
1344
2ab455cc
AL		 1345static void vmcs_clear_bits(unsigned long field, u32 mask)
1346{
1347 vmcs_writel(field, vmcs_readl(field) & ~mask);
1348}
1349
1350static void vmcs_set_bits(unsigned long field, u32 mask)
1351{
1352 vmcs_writel(field, vmcs_readl(field) | mask);
1353}
1354
2961e876
GN		 1355static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1356{
1357 vmcs_write32(VM_ENTRY_CONTROLS, val);
1358 vmx->vm_entry_controls_shadow = val;
1359}
1360
1361static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1362{
1363 if (vmx->vm_entry_controls_shadow != val)
1364 vm_entry_controls_init(vmx, val);
1365}
1366
1367static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1368{
1369 return vmx->vm_entry_controls_shadow;
1370}
1371
1372
1373static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1374{
1375 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1376}
1377
1378static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1379{
1380 vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1381}
1382
1383static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1384{
1385 vmcs_write32(VM_EXIT_CONTROLS, val);
1386 vmx->vm_exit_controls_shadow = val;
1387}
1388
1389static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1390{
1391 if (vmx->vm_exit_controls_shadow != val)
1392 vm_exit_controls_init(vmx, val);
1393}
1394
1395static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1396{
1397 return vmx->vm_exit_controls_shadow;
1398}
1399
1400
1401static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1402{
1403 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1404}
1405
1406static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1407{
1408 vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1409}
1410
2fb92db1
AK		 1411static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1412{
1413 vmx->segment_cache.bitmask = 0;
1414}
1415
1416static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1417 unsigned field)
1418{
1419 bool ret;
1420 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1421
1422 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1423 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1424 vmx->segment_cache.bitmask = 0;
1425 }
1426 ret = vmx->segment_cache.bitmask & mask;
1427 vmx->segment_cache.bitmask |= mask;
1428 return ret;
1429}
1430
1431static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1432{
1433 u16 *p = &vmx->segment_cache.seg[seg].selector;
1434
1435 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1436 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1437 return *p;
1438}
1439
1440static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1441{
1442 ulong *p = &vmx->segment_cache.seg[seg].base;
1443
1444 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1445 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1446 return *p;
1447}
1448
1449static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1450{
1451 u32 *p = &vmx->segment_cache.seg[seg].limit;
1452
1453 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1454 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1455 return *p;
1456}
1457
1458static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1459{
1460 u32 *p = &vmx->segment_cache.seg[seg].ar;
1461
1462 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1463 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1464 return *p;
1465}
1466
abd3f2d6
AK		 1467static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1468{
1469 u32 eb;
1470
fd7373cc
JK		 1471 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1472 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1473 if ((vcpu->guest_debug &
1474 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1475 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1476 eb |= 1u << BP_VECTOR;
7ffd92c5 1477 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1478 eb = ~0;
089d034e 1479 if (enable_ept)
1439442c 1480 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1481 if (vcpu->fpu_active)
1482 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1483
1484 /* When we are running a nested L2 guest and L1 specified for it a
1485 * certain exception bitmap, we must trap the same exceptions and pass
1486 * them to L1. When running L2, we will only handle the exceptions
1487 * specified above if L1 did not want them.
1488 */
1489 if (is_guest_mode(vcpu))
1490 eb |= get_vmcs12(vcpu)->exception_bitmap;
1491
abd3f2d6
AK		 1492 vmcs_write32(EXCEPTION_BITMAP, eb);
1493}
1494
2961e876
GN		 1495static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1496 unsigned long entry, unsigned long exit)
8bf00a52 1497{
2961e876
GN		 1498 vm_entry_controls_clearbit(vmx, entry);
1499 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 1500}
1501
61d2ef2c
AK		 1502static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1503{
1504 unsigned i;
1505 struct msr_autoload *m = &vmx->msr_autoload;
1506
8bf00a52
GN		 1507 switch (msr) {
1508 case MSR_EFER:
1509 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1510 clear_atomic_switch_msr_special(vmx,
1511 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1512 VM_EXIT_LOAD_IA32_EFER);
1513 return;
1514 }
1515 break;
1516 case MSR_CORE_PERF_GLOBAL_CTRL:
1517 if (cpu_has_load_perf_global_ctrl) {
2961e876 1518 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1519 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1520 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1521 return;
1522 }
1523 break;
110312c8
AK		 1524 }
1525
61d2ef2c
AK		 1526 for (i = 0; i < m->nr; ++i)
1527 if (m->guest[i].index == msr)
1528 break;
1529
1530 if (i == m->nr)
1531 return;
1532 --m->nr;
1533 m->guest[i] = m->guest[m->nr];
1534 m->host[i] = m->host[m->nr];
1535 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1536 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1537}
1538
2961e876
GN		 1539static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1540 unsigned long entry, unsigned long exit,
1541 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1542 u64 guest_val, u64 host_val)
8bf00a52
GN		 1543{
1544 vmcs_write64(guest_val_vmcs, guest_val);
1545 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 1546 vm_entry_controls_setbit(vmx, entry);
1547 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 1548}
1549
61d2ef2c
AK		 1550static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1551 u64 guest_val, u64 host_val)
1552{
1553 unsigned i;
1554 struct msr_autoload *m = &vmx->msr_autoload;
1555
8bf00a52
GN		 1556 switch (msr) {
1557 case MSR_EFER:
1558 if (cpu_has_load_ia32_efer) {
2961e876
GN		 1559 add_atomic_switch_msr_special(vmx,
1560 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 1561 VM_EXIT_LOAD_IA32_EFER,
1562 GUEST_IA32_EFER,
1563 HOST_IA32_EFER,
1564 guest_val, host_val);
1565 return;
1566 }
1567 break;
1568 case MSR_CORE_PERF_GLOBAL_CTRL:
1569 if (cpu_has_load_perf_global_ctrl) {
2961e876 1570 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 1571 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1572 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1573 GUEST_IA32_PERF_GLOBAL_CTRL,
1574 HOST_IA32_PERF_GLOBAL_CTRL,
1575 guest_val, host_val);
1576 return;
1577 }
1578 break;
110312c8
AK		 1579 }
1580
61d2ef2c
AK		 1581 for (i = 0; i < m->nr; ++i)
1582 if (m->guest[i].index == msr)
1583 break;
1584
e7fc6f93 1585 if (i == NR_AUTOLOAD_MSRS) {
60266204 1586 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 1587 "Can't add msr %x\n", msr);
1588 return;
1589 } else if (i == m->nr) {
61d2ef2c
AK		 1590 ++m->nr;
1591 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1592 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1593 }
1594
1595 m->guest[i].index = msr;
1596 m->guest[i].value = guest_val;
1597 m->host[i].index = msr;
1598 m->host[i].value = host_val;
1599}
1600
33ed6329
AK		 1601static void reload_tss(void)
1602{
33ed6329
AK		 1603 /*
1604 * VT restores TR but not its size. Useless.
1605 */
d359192f 1606 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1607 struct desc_struct *descs;
33ed6329 1608
d359192f 1609 descs = (void *)gdt->address;
33ed6329
AK		 1610 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1611 load_TR_desc();
33ed6329
AK		 1612}
1613
92c0d900 1614static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1615{
3a34a881 1616 u64 guest_efer;
51c6cf66
AK		 1617 u64 ignore_bits;
1618
f6801dff 1619 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1620
51c6cf66 1621 /*
0fa06071 1622 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1623 * outside long mode
1624 */
1625 ignore_bits = EFER_NX | EFER_SCE;
1626#ifdef CONFIG_X86_64
1627 ignore_bits |= EFER_LMA | EFER_LME;
1628 /* SCE is meaningful only in long mode on Intel */
1629 if (guest_efer & EFER_LMA)
1630 ignore_bits &= ~(u64)EFER_SCE;
1631#endif
51c6cf66
AK		 1632 guest_efer &= ~ignore_bits;
1633 guest_efer |= host_efer & ignore_bits;
26bb0981 1634 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1635 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1636
1637 clear_atomic_switch_msr(vmx, MSR_EFER);
1638 /* On ept, can't emulate nx, and must switch nx atomically */
1639 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1640 guest_efer = vmx->vcpu.arch.efer;
1641 if (!(guest_efer & EFER_LMA))
1642 guest_efer &= ~EFER_LME;
1643 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1644 return false;
1645 }
1646
26bb0981 1647 return true;
51c6cf66
AK		 1648}
1649
2d49ec72
GN		 1650static unsigned long segment_base(u16 selector)
1651{
d359192f 1652 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1653 struct desc_struct *d;
1654 unsigned long table_base;
1655 unsigned long v;
1656
1657 if (!(selector & ~3))
1658 return 0;
1659
d359192f 1660 table_base = gdt->address;
2d49ec72
GN		 1661
1662 if (selector & 4) { /* from ldt */
1663 u16 ldt_selector = kvm_read_ldt();
1664
1665 if (!(ldt_selector & ~3))
1666 return 0;
1667
1668 table_base = segment_base(ldt_selector);
1669 }
1670 d = (struct desc_struct *)(table_base + (selector & ~7));
1671 v = get_desc_base(d);
1672#ifdef CONFIG_X86_64
1673 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1674 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1675#endif
1676 return v;
1677}
1678
1679static inline unsigned long kvm_read_tr_base(void)
1680{
1681 u16 tr;
1682 asm("str %0" : "=g"(tr));
1683 return segment_base(tr);
1684}
1685
04d2cc77 1686static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1687{
04d2cc77 1688 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1689 int i;
04d2cc77 1690
a2fa3e9f 1691 if (vmx->host_state.loaded)
33ed6329
AK		 1692 return;
1693
a2fa3e9f 1694 vmx->host_state.loaded = 1;
33ed6329
AK		 1695 /*
1696 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1697 * allow segment selectors with cpl > 0 or ti == 1.
1698 */
d6e88aec 1699 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1700 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1701 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1702 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1703 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1704 vmx->host_state.fs_reload_needed = 0;
1705 } else {
33ed6329 1706 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1707 vmx->host_state.fs_reload_needed = 1;
33ed6329 1708 }
9581d442 1709 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1710 if (!(vmx->host_state.gs_sel & 7))
1711 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1712 else {
1713 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1714 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1715 }
1716
b2da15ac
AK		 1717#ifdef CONFIG_X86_64
1718 savesegment(ds, vmx->host_state.ds_sel);
1719 savesegment(es, vmx->host_state.es_sel);
1720#endif
1721
33ed6329
AK		 1722#ifdef CONFIG_X86_64
1723 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1724 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1725#else
a2fa3e9f
GH		 1726 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1727 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1728#endif
707c0874
AK		 1729
1730#ifdef CONFIG_X86_64
c8770e7b
AK		 1731 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1732 if (is_long_mode(&vmx->vcpu))
44ea2b17 1733 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1734#endif
da8999d3
LJ		 1735 if (boot_cpu_has(X86_FEATURE_MPX))
1736 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
26bb0981
AK		 1737 for (i = 0; i < vmx->save_nmsrs; ++i)
1738 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1739 vmx->guest_msrs[i].data,
1740 vmx->guest_msrs[i].mask);
33ed6329
AK		 1741}
1742
a9b21b62 1743static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1744{
a2fa3e9f 1745 if (!vmx->host_state.loaded)
33ed6329
AK		 1746 return;
1747
e1beb1d3 1748 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1749 vmx->host_state.loaded = 0;
c8770e7b
AK		 1750#ifdef CONFIG_X86_64
1751 if (is_long_mode(&vmx->vcpu))
1752 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1753#endif
152d3f2f 1754 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1755 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1756#ifdef CONFIG_X86_64
9581d442 1757 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1758#else
1759 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1760#endif
33ed6329 1761 }
0a77fe4c
AK		 1762 if (vmx->host_state.fs_reload_needed)
1763 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1764#ifdef CONFIG_X86_64
1765 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1766 loadsegment(ds, vmx->host_state.ds_sel);
1767 loadsegment(es, vmx->host_state.es_sel);
1768 }
b2da15ac 1769#endif
152d3f2f 1770 reload_tss();
44ea2b17 1771#ifdef CONFIG_X86_64
c8770e7b 1772 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1773#endif
da8999d3
LJ		 1774 if (vmx->host_state.msr_host_bndcfgs)
1775 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
b1a74bf8
SS		 1776 /*
1777 * If the FPU is not active (through the host task or
1778 * the guest vcpu), then restore the cr0.TS bit.
1779 */
1780 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1781 stts();
3444d7da 1782 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1783}
1784
a9b21b62
AK		 1785static void vmx_load_host_state(struct vcpu_vmx *vmx)
1786{
1787 preempt_disable();
1788 __vmx_load_host_state(vmx);
1789 preempt_enable();
1790}
1791
6aa8b732
AK		 1792/*
1793 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1794 * vcpu mutex is already taken.
1795 */
15ad7146 1796static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1797{
a2fa3e9f 1798 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1799 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1800
4610c9cc
DX		 1801 if (!vmm_exclusive)
1802 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1803 else if (vmx->loaded_vmcs->cpu != cpu)
1804 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1805
d462b819
NHE		 1806 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1807 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1808 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1809 }
1810
d462b819 1811 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1812 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1813 unsigned long sysenter_esp;
1814
a8eeb04a 1815 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1816 local_irq_disable();
8f536b76 1817 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1818
1819 /*
1820 * Read loaded_vmcs->cpu should be before fetching
1821 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1822 * See the comments in __loaded_vmcs_clear().
1823 */
1824 smp_rmb();
1825
d462b819
NHE		 1826 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1827 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1828 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1829 local_irq_enable();
1830
6aa8b732
AK		 1831 /*
1832 * Linux uses per-cpu TSS and GDT, so set these when switching
1833 * processors.
1834 */
d6e88aec 1835 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1836 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1837
1838 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1839 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1840 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1841 }
6aa8b732
AK		 1842}
1843
1844static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1845{
a9b21b62 1846 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1847 if (!vmm_exclusive) {
d462b819
NHE		 1848 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1849 vcpu->cpu = -1;
4610c9cc
DX		 1850 kvm_cpu_vmxoff();
1851 }
6aa8b732
AK		 1852}
1853
5fd86fcf
AK		 1854static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1855{
81231c69
AK		 1856 ulong cr0;
1857
5fd86fcf
AK		 1858 if (vcpu->fpu_active)
1859 return;
1860 vcpu->fpu_active = 1;
81231c69
AK		 1861 cr0 = vmcs_readl(GUEST_CR0);
1862 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1863 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1864 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1865 update_exception_bitmap(vcpu);
edcafe3c 1866 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1867 if (is_guest_mode(vcpu))
1868 vcpu->arch.cr0_guest_owned_bits &=
1869 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1870 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1871}
1872
edcafe3c
AK		 1873static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1874
fe3ef05c
NHE		 1875/*
1876 * Return the cr0 value that a nested guest would read. This is a combination
1877 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1878 * its hypervisor (cr0_read_shadow).
1879 */
1880static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1881{
1882 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1883 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1884}
1885static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1886{
1887 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1888 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1889}
1890
5fd86fcf
AK		 1891static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1892{
36cf24e0
NHE		 1893 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1894 * set this *before* calling this function.
1895 */
edcafe3c 1896 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1897 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1898 update_exception_bitmap(vcpu);
edcafe3c
AK		 1899 vcpu->arch.cr0_guest_owned_bits = 0;
1900 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1901 if (is_guest_mode(vcpu)) {
1902 /*
1903 * L1's specified read shadow might not contain the TS bit,
1904 * so now that we turned on shadowing of this bit, we need to
1905 * set this bit of the shadow. Like in nested_vmx_run we need
1906 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1907 * up-to-date here because we just decached cr0.TS (and we'll
1908 * only update vmcs12->guest_cr0 on nested exit).
1909 */
1910 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1911 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1912 (vcpu->arch.cr0 & X86_CR0_TS);
1913 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1914 } else
1915 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1916}
1917
6aa8b732
AK		 1918static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1919{
78ac8b47 1920 unsigned long rflags, save_rflags;
345dcaa8 1921
6de12732
AK		 1922 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1923 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1924 rflags = vmcs_readl(GUEST_RFLAGS);
1925 if (to_vmx(vcpu)->rmode.vm86_active) {
1926 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1927 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1928 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1929 }
1930 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1931 }
6de12732 1932 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1933}
1934
1935static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1936{
6de12732
AK		 1937 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1938 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1939 if (to_vmx(vcpu)->rmode.vm86_active) {
1940 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1941 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1942 }
6aa8b732
AK		 1943 vmcs_writel(GUEST_RFLAGS, rflags);
1944}
1945
2809f5d2
GC		 1946static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1947{
1948 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1949 int ret = 0;
1950
1951 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1952 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1953 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1954 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1955
1956 return ret & mask;
1957}
1958
1959static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1960{
1961 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1962 u32 interruptibility = interruptibility_old;
1963
1964 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1965
48005f64 1966 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1967 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1968 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1969 interruptibility |= GUEST_INTR_STATE_STI;
1970
1971 if ((interruptibility != interruptibility_old))
1972 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1973}
1974
6aa8b732
AK		 1975static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1976{
1977 unsigned long rip;
6aa8b732 1978
5fdbf976 1979 rip = kvm_rip_read(vcpu);
6aa8b732 1980 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1981 kvm_rip_write(vcpu, rip);
6aa8b732 1982
2809f5d2
GC		 1983 /* skipping an emulated instruction also counts */
1984 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1985}
1986
0b6ac343
NHE		 1987/*
1988 * KVM wants to inject page-faults which it got to the guest. This function
1989 * checks whether in a nested guest, we need to inject them to L1 or L2.
0b6ac343 1990 */
e011c663 1991static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
0b6ac343
NHE		 1992{
1993 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1994
e011c663 1995 if (!(vmcs12->exception_bitmap & (1u << nr)))
0b6ac343
NHE		 1996 return 0;
1997
533558bc
JK		 1998 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
1999 vmcs_read32(VM_EXIT_INTR_INFO),
2000 vmcs_readl(EXIT_QUALIFICATION));
0b6ac343
NHE		 2001 return 1;
2002}
2003
298101da 2004static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 2005 bool has_error_code, u32 error_code,
2006 bool reinject)
298101da 2007{
77ab6db0 2008 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 2009 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 2010
e011c663
GN		 2011 if (!reinject && is_guest_mode(vcpu) &&
2012 nested_vmx_check_exception(vcpu, nr))
0b6ac343
NHE		 2013 return;
2014
8ab2d2e2 2015 if (has_error_code) {
77ab6db0 2016 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 2017 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2018 }
77ab6db0 2019
7ffd92c5 2020 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2021 int inc_eip = 0;
2022 if (kvm_exception_is_soft(nr))
2023 inc_eip = vcpu->arch.event_exit_inst_len;
2024 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 2025 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 2026 return;
2027 }
2028
66fd3f7f
GN		 2029 if (kvm_exception_is_soft(nr)) {
2030 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2031 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 2032 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2033 } else
2034 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2035
2036 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 2037}
2038
4e47c7a6
SY		 2039static bool vmx_rdtscp_supported(void)
2040{
2041 return cpu_has_vmx_rdtscp();
2042}
2043
ad756a16
MJ		 2044static bool vmx_invpcid_supported(void)
2045{
2046 return cpu_has_vmx_invpcid() && enable_ept;
2047}
2048
a75beee6
ED		 2049/*
2050 * Swap MSR entry in host/guest MSR entry array.
2051 */
8b9cf98c 2052static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 2053{
26bb0981 2054 struct shared_msr_entry tmp;
a2fa3e9f
GH		 2055
2056 tmp = vmx->guest_msrs[to];
2057 vmx->guest_msrs[to] = vmx->guest_msrs[from];
2058 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 2059}
2060
8d14695f
YZ		 2061static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2062{
2063 unsigned long *msr_bitmap;
2064
2065 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
2066 if (is_long_mode(vcpu))
2067 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2068 else
2069 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2070 } else {
2071 if (is_long_mode(vcpu))
2072 msr_bitmap = vmx_msr_bitmap_longmode;
2073 else
2074 msr_bitmap = vmx_msr_bitmap_legacy;
2075 }
2076
2077 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2078}
2079
e38aea3e
AK		 2080/*
2081 * Set up the vmcs to automatically save and restore system
2082 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2083 * mode, as fiddling with msrs is very expensive.
2084 */
8b9cf98c 2085static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 2086{
26bb0981 2087 int save_nmsrs, index;
e38aea3e 2088
a75beee6
ED		 2089 save_nmsrs = 0;
2090#ifdef CONFIG_X86_64
8b9cf98c 2091 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2092 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2093 if (index >= 0)
8b9cf98c
RR		 2094 move_msr_up(vmx, index, save_nmsrs++);
2095 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2096 if (index >= 0)
8b9cf98c
RR		 2097 move_msr_up(vmx, index, save_nmsrs++);
2098 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2099 if (index >= 0)
8b9cf98c 2100 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2101 index = __find_msr_index(vmx, MSR_TSC_AUX);
2102 if (index >= 0 && vmx->rdtscp_enabled)
2103 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2104 /*
8c06585d 2105 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2106 * if efer.sce is enabled.
2107 */
8c06585d 2108 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2109 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2110 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2111 }
2112#endif
92c0d900
AK		 2113 index = __find_msr_index(vmx, MSR_EFER);
2114 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2115 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2116
26bb0981 2117 vmx->save_nmsrs = save_nmsrs;
5897297b 2118
8d14695f
YZ		 2119 if (cpu_has_vmx_msr_bitmap())
2120 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2121}
2122
6aa8b732
AK		 2123/*
2124 * reads and returns guest's timestamp counter "register"
2125 * guest_tsc = host_tsc + tsc_offset -- 21.3
2126 */
2127static u64 guest_read_tsc(void)
2128{
2129 u64 host_tsc, tsc_offset;
2130
2131 rdtscll(host_tsc);
2132 tsc_offset = vmcs_read64(TSC_OFFSET);
2133 return host_tsc + tsc_offset;
2134}
2135
d5c1785d
NHE		 2136/*
2137 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2138 * counter, even if a nested guest (L2) is currently running.
2139 */
886b470c 2140u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2141{
886b470c 2142 u64 tsc_offset;
d5c1785d 2143
d5c1785d
NHE		 2144 tsc_offset = is_guest_mode(vcpu) ?
2145 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2146 vmcs_read64(TSC_OFFSET);
2147 return host_tsc + tsc_offset;
2148}
2149
4051b188 2150/*
cc578287
ZA		 2151 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2152 * software catchup for faster rates on slower CPUs.
4051b188 2153 */
cc578287 2154static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2155{
cc578287
ZA		 2156 if (!scale)
2157 return;
2158
2159 if (user_tsc_khz > tsc_khz) {
2160 vcpu->arch.tsc_catchup = 1;
2161 vcpu->arch.tsc_always_catchup = 1;
2162 } else
2163 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2164}
2165
ba904635
WA		 2166static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2167{
2168 return vmcs_read64(TSC_OFFSET);
2169}
2170
6aa8b732 2171/*
99e3e30a 2172 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2173 */
99e3e30a 2174static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2175{
27fc51b2 2176 if (is_guest_mode(vcpu)) {
7991825b 2177 /*
27fc51b2
NHE		 2178 * We're here if L1 chose not to trap WRMSR to TSC. According
2179 * to the spec, this should set L1's TSC; The offset that L1
2180 * set for L2 remains unchanged, and still needs to be added
2181 * to the newly set TSC to get L2's TSC.
7991825b 2182 */
27fc51b2
NHE		 2183 struct vmcs12 *vmcs12;
2184 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2185 /* recalculate vmcs02.TSC_OFFSET: */
2186 vmcs12 = get_vmcs12(vcpu);
2187 vmcs_write64(TSC_OFFSET, offset +
2188 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2189 vmcs12->tsc_offset : 0));
2190 } else {
489223ed
YY		 2191 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2192 vmcs_read64(TSC_OFFSET), offset);
27fc51b2
NHE		 2193 vmcs_write64(TSC_OFFSET, offset);
2194 }
6aa8b732
AK		 2195}
2196
f1e2b260 2197static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2198{
2199 u64 offset = vmcs_read64(TSC_OFFSET);
489223ed 2200
e48672fa 2201 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2202 if (is_guest_mode(vcpu)) {
2203 /* Even when running L2, the adjustment needs to apply to L1 */
2204 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
489223ed
YY		 2205 } else
2206 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2207 offset + adjustment);
e48672fa
ZA		 2208}
2209
857e4099
JR		 2210static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2211{
2212 return target_tsc - native_read_tsc();
2213}
2214
801d3424
NHE		 2215static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2216{
2217 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2218 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2219}
2220
2221/*
2222 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2223 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2224 * all guests if the "nested" module option is off, and can also be disabled
2225 * for a single guest by disabling its VMX cpuid bit.
2226 */
2227static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2228{
2229 return nested && guest_cpuid_has_vmx(vcpu);
2230}
2231
b87a51ae
NHE		 2232/*
2233 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2234 * returned for the various VMX controls MSRs when nested VMX is enabled.
2235 * The same values should also be used to verify that vmcs12 control fields are
2236 * valid during nested entry from L1 to L2.
2237 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2238 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2239 * bit in the high half is on if the corresponding bit in the control field
2240 * may be on. See also vmx_control_verify().
2241 * TODO: allow these variables to be modified (downgraded) by module options
2242 * or other means.
2243 */
2244static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
3dcdf3ec 2245static u32 nested_vmx_true_procbased_ctls_low;
b87a51ae
NHE		 2246static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2247static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2248static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2996fca0 2249static u32 nested_vmx_true_exit_ctls_low;
b87a51ae 2250static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
2996fca0 2251static u32 nested_vmx_true_entry_ctls_low;
c18911a2 2252static u32 nested_vmx_misc_low, nested_vmx_misc_high;
bfd0a56b 2253static u32 nested_vmx_ept_caps;
b87a51ae
NHE		 2254static __init void nested_vmx_setup_ctls_msrs(void)
2255{
2256 /*
2257 * Note that as a general rule, the high half of the MSRs (bits in
2258 * the control fields which may be 1) should be initialized by the
2259 * intersection of the underlying hardware's MSR (i.e., features which
2260 * can be supported) and the list of features we want to expose -
2261 * because they are known to be properly supported in our code.
2262 * Also, usually, the low half of the MSRs (bits which must be 1) can
2263 * be set to 0, meaning that L1 may turn off any of these bits. The
2264 * reason is that if one of these bits is necessary, it will appear
2265 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2266 * fields of vmcs01 and vmcs02, will turn these bits off - and
2267 * nested_vmx_exit_handled() will not pass related exits to L1.
2268 * These rules have exceptions below.
2269 */
2270
2271 /* pin-based controls */
eabeaacc
JK		 2272 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2273 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
eabeaacc
JK		 2274 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2275 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
f4124500
JK		 2276 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS;
2277 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
0238ea91 2278 PIN_BASED_VMX_PREEMPTION_TIMER;
b87a51ae 2279
3dbcd8da 2280 /* exit controls */
c0dfee58
ACL		 2281 rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2282 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high);
33fb20c3 2283 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
e0ba1a6f 2284
c0dfee58 2285 nested_vmx_exit_ctls_high &=
b87a51ae 2286#ifdef CONFIG_X86_64
c0dfee58 2287 VM_EXIT_HOST_ADDR_SPACE_SIZE |
b87a51ae 2288#endif
f4124500
JK		 2289 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2290 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2291 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
e0ba1a6f
BD		 2292 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2293
36be0b9d
PB		 2294 if (vmx_mpx_supported())
2295 nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
b87a51ae 2296
2996fca0
JK		 2297 /* We support free control of debug control saving. */
2298 nested_vmx_true_exit_ctls_low = nested_vmx_exit_ctls_low &
2299 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2300
b87a51ae
NHE		 2301 /* entry controls */
2302 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2303 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3 2304 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2305 nested_vmx_entry_ctls_high &=
57435349
JK		 2306#ifdef CONFIG_X86_64
2307 VM_ENTRY_IA32E_MODE |
2308#endif
2309 VM_ENTRY_LOAD_IA32_PAT;
8049d651
NHE		 2310 nested_vmx_entry_ctls_high |= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR |
2311 VM_ENTRY_LOAD_IA32_EFER);
36be0b9d
PB		 2312 if (vmx_mpx_supported())
2313 nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
57435349 2314
2996fca0
JK		 2315 /* We support free control of debug control loading. */
2316 nested_vmx_true_entry_ctls_low = nested_vmx_entry_ctls_low &
2317 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2318
b87a51ae
NHE		 2319 /* cpu-based controls */
2320 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2321 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
560b7ee1 2322 nested_vmx_procbased_ctls_low = CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2323 nested_vmx_procbased_ctls_high &=
a294c9bb
JK		 2324 CPU_BASED_VIRTUAL_INTR_PENDING |
2325 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
b87a51ae
NHE		 2326 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2327 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2328 CPU_BASED_CR3_STORE_EXITING |
2329#ifdef CONFIG_X86_64
2330 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2331#endif
2332 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2333 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2334 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2335 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2336 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2337 /*
2338 * We can allow some features even when not supported by the
2339 * hardware. For example, L1 can specify an MSR bitmap - and we
2340 * can use it to avoid exits to L1 - even when L0 runs L2
2341 * without MSR bitmaps.
2342 */
560b7ee1
JK		 2343 nested_vmx_procbased_ctls_high |= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2344 CPU_BASED_USE_MSR_BITMAPS;
b87a51ae 2345
3dcdf3ec
JK		 2346 /* We support free control of CR3 access interception. */
2347 nested_vmx_true_procbased_ctls_low = nested_vmx_procbased_ctls_low &
2348 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2349
b87a51ae
NHE		 2350 /* secondary cpu-based controls */
2351 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2352 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2353 nested_vmx_secondary_ctls_low = 0;
2354 nested_vmx_secondary_ctls_high &=
d6851fbe 2355 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
92fbc7b1 2356 SECONDARY_EXEC_UNRESTRICTED_GUEST |
d6851fbe 2357 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2 2358
afa61f75
NHE		 2359 if (enable_ept) {
2360 /* nested EPT: emulate EPT also to L1 */
2361 nested_vmx_secondary_ctls_high |= SECONDARY_EXEC_ENABLE_EPT;
ca72d970 2362 nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
d3134dbf
JK		 2363 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2364 VMX_EPT_INVEPT_BIT;
afa61f75
NHE		 2365 nested_vmx_ept_caps &= vmx_capability.ept;
2366 /*
4b855078
BD		 2367 * For nested guests, we don't do anything specific
2368 * for single context invalidation. Hence, only advertise
2369 * support for global context invalidation.
afa61f75 2370 */
4b855078 2371 nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
afa61f75
NHE		 2372 } else
2373 nested_vmx_ept_caps = 0;
2374
c18911a2
JK		 2375 /* miscellaneous data */
2376 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
f4124500
JK		 2377 nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2378 nested_vmx_misc_low |= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2379 VMX_MISC_ACTIVITY_HLT;
c18911a2 2380 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2381}
2382
2383static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2384{
2385 /*
2386 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2387 */
2388 return ((control & high) | low) == control;
2389}
2390
2391static inline u64 vmx_control_msr(u32 low, u32 high)
2392{
2393 return low | ((u64)high << 32);
2394}
2395
cae50139 2396/* Returns 0 on success, non-0 otherwise. */
b87a51ae
NHE		 2397static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2398{
b87a51ae 2399 switch (msr_index) {
b87a51ae
NHE		 2400 case MSR_IA32_VMX_BASIC:
2401 /*
2402 * This MSR reports some information about VMX support. We
2403 * should return information about the VMX we emulate for the
2404 * guest, and the VMCS structure we give it - not about the
2405 * VMX support of the underlying hardware.
2406 */
3dbcd8da 2407 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
b87a51ae
NHE		 2408 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2409 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2410 break;
2411 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2412 case MSR_IA32_VMX_PINBASED_CTLS:
2413 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2414 nested_vmx_pinbased_ctls_high);
2415 break;
2416 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
3dcdf3ec
JK		 2417 *pdata = vmx_control_msr(nested_vmx_true_procbased_ctls_low,
2418 nested_vmx_procbased_ctls_high);
2419 break;
b87a51ae
NHE		 2420 case MSR_IA32_VMX_PROCBASED_CTLS:
2421 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2422 nested_vmx_procbased_ctls_high);
2423 break;
2424 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2996fca0
JK		 2425 *pdata = vmx_control_msr(nested_vmx_true_exit_ctls_low,
2426 nested_vmx_exit_ctls_high);
2427 break;
b87a51ae
NHE		 2428 case MSR_IA32_VMX_EXIT_CTLS:
2429 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2430 nested_vmx_exit_ctls_high);
2431 break;
2432 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2996fca0
JK		 2433 *pdata = vmx_control_msr(nested_vmx_true_entry_ctls_low,
2434 nested_vmx_entry_ctls_high);
2435 break;
b87a51ae
NHE		 2436 case MSR_IA32_VMX_ENTRY_CTLS:
2437 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2438 nested_vmx_entry_ctls_high);
2439 break;
2440 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2441 *pdata = vmx_control_msr(nested_vmx_misc_low,
2442 nested_vmx_misc_high);
b87a51ae
NHE		 2443 break;
2444 /*
2445 * These MSRs specify bits which the guest must keep fixed (on or off)
2446 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2447 * We picked the standard core2 setting.
2448 */
2449#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2450#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2451 case MSR_IA32_VMX_CR0_FIXED0:
2452 *pdata = VMXON_CR0_ALWAYSON;
2453 break;
2454 case MSR_IA32_VMX_CR0_FIXED1:
2455 *pdata = -1ULL;
2456 break;
2457 case MSR_IA32_VMX_CR4_FIXED0:
2458 *pdata = VMXON_CR4_ALWAYSON;
2459 break;
2460 case MSR_IA32_VMX_CR4_FIXED1:
2461 *pdata = -1ULL;
2462 break;
2463 case MSR_IA32_VMX_VMCS_ENUM:
5381417f 2464 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
b87a51ae
NHE		 2465 break;
2466 case MSR_IA32_VMX_PROCBASED_CTLS2:
2467 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2468 nested_vmx_secondary_ctls_high);
2469 break;
2470 case MSR_IA32_VMX_EPT_VPID_CAP:
afa61f75
NHE		 2471 /* Currently, no nested vpid support */
2472 *pdata = nested_vmx_ept_caps;
b87a51ae
NHE		 2473 break;
2474 default:
b87a51ae 2475 return 1;
b3897a49
NHE		 2476 }
2477
b87a51ae
NHE		 2478 return 0;
2479}
2480
6aa8b732
AK		 2481/*
2482 * Reads an msr value (of 'msr_index') into 'pdata'.
2483 * Returns 0 on success, non-0 otherwise.
2484 * Assumes vcpu_load() was already called.
2485 */
2486static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2487{
2488 u64 data;
26bb0981 2489 struct shared_msr_entry *msr;
6aa8b732
AK		 2490
2491 if (!pdata) {
2492 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2493 return -EINVAL;
2494 }
2495
2496 switch (msr_index) {
05b3e0c2 2497#ifdef CONFIG_X86_64
6aa8b732
AK		 2498 case MSR_FS_BASE:
2499 data = vmcs_readl(GUEST_FS_BASE);
2500 break;
2501 case MSR_GS_BASE:
2502 data = vmcs_readl(GUEST_GS_BASE);
2503 break;
44ea2b17
AK		 2504 case MSR_KERNEL_GS_BASE:
2505 vmx_load_host_state(to_vmx(vcpu));
2506 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2507 break;
26bb0981 2508#endif
6aa8b732 2509 case MSR_EFER:
3bab1f5d 2510 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2511 case MSR_IA32_TSC:
6aa8b732
AK		 2512 data = guest_read_tsc();
2513 break;
2514 case MSR_IA32_SYSENTER_CS:
2515 data = vmcs_read32(GUEST_SYSENTER_CS);
2516 break;
2517 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2518 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2519 break;
2520 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2521 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2522 break;
0dd376e7 2523 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2524 if (!vmx_mpx_supported())
2525 return 1;
0dd376e7
LJ		 2526 data = vmcs_read64(GUEST_BNDCFGS);
2527 break;
cae50139
JK		 2528 case MSR_IA32_FEATURE_CONTROL:
2529 if (!nested_vmx_allowed(vcpu))
2530 return 1;
2531 data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2532 break;
2533 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2534 if (!nested_vmx_allowed(vcpu))
2535 return 1;
2536 return vmx_get_vmx_msr(vcpu, msr_index, pdata);
4e47c7a6
SY		 2537 case MSR_TSC_AUX:
2538 if (!to_vmx(vcpu)->rdtscp_enabled)
2539 return 1;
2540 /* Otherwise falls through */
6aa8b732 2541 default:
8b9cf98c 2542 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2543 if (msr) {
2544 data = msr->data;
2545 break;
6aa8b732 2546 }
3bab1f5d 2547 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2548 }
2549
2550 *pdata = data;
2551 return 0;
2552}
2553
cae50139
JK		 2554static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2555
6aa8b732
AK		 2556/*
2557 * Writes msr value into into the appropriate "register".
2558 * Returns 0 on success, non-0 otherwise.
2559 * Assumes vcpu_load() was already called.
2560 */
8fe8ab46 2561static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2562{
a2fa3e9f 2563 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2564 struct shared_msr_entry *msr;
2cc51560 2565 int ret = 0;
8fe8ab46
WA		 2566 u32 msr_index = msr_info->index;
2567 u64 data = msr_info->data;
2cc51560 2568
6aa8b732 2569 switch (msr_index) {
3bab1f5d 2570 case MSR_EFER:
8fe8ab46 2571 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2572 break;
16175a79 2573#ifdef CONFIG_X86_64
6aa8b732 2574 case MSR_FS_BASE:
2fb92db1 2575 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2576 vmcs_writel(GUEST_FS_BASE, data);
2577 break;
2578 case MSR_GS_BASE:
2fb92db1 2579 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2580 vmcs_writel(GUEST_GS_BASE, data);
2581 break;
44ea2b17
AK		 2582 case MSR_KERNEL_GS_BASE:
2583 vmx_load_host_state(vmx);
2584 vmx->msr_guest_kernel_gs_base = data;
2585 break;
6aa8b732
AK		 2586#endif
2587 case MSR_IA32_SYSENTER_CS:
2588 vmcs_write32(GUEST_SYSENTER_CS, data);
2589 break;
2590 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2591 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2592 break;
2593 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2594 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2595 break;
0dd376e7 2596 case MSR_IA32_BNDCFGS:
93c4adc7
PB		 2597 if (!vmx_mpx_supported())
2598 return 1;
0dd376e7
LJ		 2599 vmcs_write64(GUEST_BNDCFGS, data);
2600 break;
af24a4e4 2601 case MSR_IA32_TSC:
8fe8ab46 2602 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2603 break;
468d472f
SY		 2604 case MSR_IA32_CR_PAT:
2605 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2606 vmcs_write64(GUEST_IA32_PAT, data);
2607 vcpu->arch.pat = data;
2608 break;
2609 }
8fe8ab46 2610 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2611 break;
ba904635
WA		 2612 case MSR_IA32_TSC_ADJUST:
2613 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2614 break;
cae50139
JK		 2615 case MSR_IA32_FEATURE_CONTROL:
2616 if (!nested_vmx_allowed(vcpu) ||
2617 (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2618 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2619 return 1;
2620 vmx->nested.msr_ia32_feature_control = data;
2621 if (msr_info->host_initiated && data == 0)
2622 vmx_leave_nested(vcpu);
2623 break;
2624 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2625 return 1; /* they are read-only */
4e47c7a6
SY		 2626 case MSR_TSC_AUX:
2627 if (!vmx->rdtscp_enabled)
2628 return 1;
2629 /* Check reserved bit, higher 32 bits should be zero */
2630 if ((data >> 32) != 0)
2631 return 1;
2632 /* Otherwise falls through */
6aa8b732 2633 default:
8b9cf98c 2634 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2635 if (msr) {
2636 msr->data = data;
2225fd56
AK		 2637 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2638 preempt_disable();
9ee73970
AK		 2639 kvm_set_shared_msr(msr->index, msr->data,
2640 msr->mask);
2225fd56
AK		 2641 preempt_enable();
2642 }
3bab1f5d 2643 break;
6aa8b732 2644 }
8fe8ab46 2645 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2646 }
2647
2cc51560 2648 return ret;
6aa8b732
AK		 2649}
2650
5fdbf976 2651static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2652{
5fdbf976
MT		 2653 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2654 switch (reg) {
2655 case VCPU_REGS_RSP:
2656 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2657 break;
2658 case VCPU_REGS_RIP:
2659 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2660 break;
6de4f3ad
AK		 2661 case VCPU_EXREG_PDPTR:
2662 if (enable_ept)
2663 ept_save_pdptrs(vcpu);
2664 break;
5fdbf976
MT		 2665 default:
2666 break;
2667 }
6aa8b732
AK		 2668}
2669
6aa8b732
AK		 2670static __init int cpu_has_kvm_support(void)
2671{
6210e37b 2672 return cpu_has_vmx();
6aa8b732
AK		 2673}
2674
2675static __init int vmx_disabled_by_bios(void)
2676{
2677 u64 msr;
2678
2679 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2680 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2681 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2682 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2683 && tboot_enabled())
2684 return 1;
23f3e991 2685 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2686 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2687 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2688 && !tboot_enabled()) {
2689 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2690 "activate TXT before enabling KVM\n");
cafd6659 2691 return 1;
f9335afe 2692 }
23f3e991
JC		 2693 /* launched w/o TXT and VMX disabled */
2694 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2695 && !tboot_enabled())
2696 return 1;
cafd6659
SW		 2697 }
2698
2699 return 0;
6aa8b732
AK		 2700}
2701
7725b894
DX		 2702static void kvm_cpu_vmxon(u64 addr)
2703{
2704 asm volatile (ASM_VMX_VMXON_RAX
2705 : : "a"(&addr), "m"(addr)
2706 : "memory", "cc");
2707}
2708
10474ae8 2709static int hardware_enable(void *garbage)
6aa8b732
AK		 2710{
2711 int cpu = raw_smp_processor_id();
2712 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2713 u64 old, test_bits;
6aa8b732 2714
10474ae8
AG		 2715 if (read_cr4() & X86_CR4_VMXE)
2716 return -EBUSY;
2717
d462b819 2718 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2719
2720 /*
2721 * Now we can enable the vmclear operation in kdump
2722 * since the loaded_vmcss_on_cpu list on this cpu
2723 * has been initialized.
2724 *
2725 * Though the cpu is not in VMX operation now, there
2726 * is no problem to enable the vmclear operation
2727 * for the loaded_vmcss_on_cpu list is empty!
2728 */
2729 crash_enable_local_vmclear(cpu);
2730
6aa8b732 2731 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2732
2733 test_bits = FEATURE_CONTROL_LOCKED;
2734 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2735 if (tboot_enabled())
2736 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2737
2738 if ((old & test_bits) != test_bits) {
6aa8b732 2739 /* enable and lock */
cafd6659
SW		 2740 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2741 }
66aee91a 2742 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2743
4610c9cc
DX		 2744 if (vmm_exclusive) {
2745 kvm_cpu_vmxon(phys_addr);
2746 ept_sync_global();
2747 }
10474ae8 2748
357d1226 2749 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2750
10474ae8 2751 return 0;
6aa8b732
AK		 2752}
2753
d462b819 2754static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2755{
2756 int cpu = raw_smp_processor_id();
d462b819 2757 struct loaded_vmcs *v, *n;
543e4243 2758
d462b819
NHE		 2759 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2760 loaded_vmcss_on_cpu_link)
2761 __loaded_vmcs_clear(v);
543e4243
AK		 2762}
2763
710ff4a8
EH		 2764
2765/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2766 * tricks.
2767 */
2768static void kvm_cpu_vmxoff(void)
6aa8b732 2769{
4ecac3fd 2770 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2771}
2772
710ff4a8
EH		 2773static void hardware_disable(void *garbage)
2774{
4610c9cc 2775 if (vmm_exclusive) {
d462b819 2776 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2777 kvm_cpu_vmxoff();
2778 }
7725b894 2779 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2780}
2781
1c3d14fe 2782static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2783 u32 msr, u32 *result)
1c3d14fe
YS		 2784{
2785 u32 vmx_msr_low, vmx_msr_high;
2786 u32 ctl = ctl_min | ctl_opt;
2787
2788 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2789
2790 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2791 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2792
2793 /* Ensure minimum (required) set of control bits are supported. */
2794 if (ctl_min & ~ctl)
002c7f7c 2795 return -EIO;
1c3d14fe
YS		 2796
2797 *result = ctl;
2798 return 0;
2799}
2800
110312c8
AK		 2801static __init bool allow_1_setting(u32 msr, u32 ctl)
2802{
2803 u32 vmx_msr_low, vmx_msr_high;
2804
2805 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2806 return vmx_msr_high & ctl;
2807}
2808
002c7f7c 2809static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2810{
2811 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2812 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2813 u32 _pin_based_exec_control = 0;
2814 u32 _cpu_based_exec_control = 0;
f78e0e2e 2815 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2816 u32 _vmexit_control = 0;
2817 u32 _vmentry_control = 0;
2818
10166744 2819 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2820#ifdef CONFIG_X86_64
2821 CPU_BASED_CR8_LOAD_EXITING |
2822 CPU_BASED_CR8_STORE_EXITING |
2823#endif
d56f546d
SY		 2824 CPU_BASED_CR3_LOAD_EXITING |
2825 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2826 CPU_BASED_USE_IO_BITMAPS |
2827 CPU_BASED_MOV_DR_EXITING |
a7052897 2828 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2829 CPU_BASED_MWAIT_EXITING |
2830 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2831 CPU_BASED_INVLPG_EXITING |
2832 CPU_BASED_RDPMC_EXITING;
443381a8 2833
f78e0e2e 2834 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2835 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2836 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2837 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2838 &_cpu_based_exec_control) < 0)
002c7f7c 2839 return -EIO;
6e5d865c
YS		 2840#ifdef CONFIG_X86_64
2841 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2842 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2843 ~CPU_BASED_CR8_STORE_EXITING;
2844#endif
f78e0e2e 2845 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2846 min2 = 0;
2847 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2848 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2849 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2850 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2851 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2852 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2853 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2854 SECONDARY_EXEC_RDTSCP |
83d4c286 2855 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2856 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2857 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2858 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2859 if (adjust_vmx_controls(min2, opt2,
2860 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2861 &_cpu_based_2nd_exec_control) < 0)
2862 return -EIO;
2863 }
2864#ifndef CONFIG_X86_64
2865 if (!(_cpu_based_2nd_exec_control &
2866 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2867 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2868#endif
83d4c286
YZ		 2869
2870 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2871 _cpu_based_2nd_exec_control &= ~(
8d14695f 2872 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2873 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2874 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2875
d56f546d 2876 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2877 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2878 enabled */
5fff7d27
GN		 2879 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2880 CPU_BASED_CR3_STORE_EXITING |
2881 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2882 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2883 vmx_capability.ept, vmx_capability.vpid);
2884 }
1c3d14fe 2885
81908bf4 2886 min = VM_EXIT_SAVE_DEBUG_CONTROLS;
1c3d14fe
YS		 2887#ifdef CONFIG_X86_64
2888 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2889#endif
a547c6db 2890 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
da8999d3 2891 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2892 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2893 &_vmexit_control) < 0)
002c7f7c 2894 return -EIO;
1c3d14fe 2895
01e439be
YZ		 2896 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2897 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2898 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2899 &_pin_based_exec_control) < 0)
2900 return -EIO;
2901
2902 if (!(_cpu_based_2nd_exec_control &
2903 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2904 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2905 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2906
c845f9c6 2907 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
da8999d3 2908 opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2909 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2910 &_vmentry_control) < 0)
002c7f7c 2911 return -EIO;
6aa8b732 2912
c68876fd 2913 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2914
2915 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2916 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2917 return -EIO;
1c3d14fe
YS		 2918
2919#ifdef CONFIG_X86_64
2920 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2921 if (vmx_msr_high & (1u<<16))
002c7f7c 2922 return -EIO;
1c3d14fe
YS		 2923#endif
2924
2925 /* Require Write-Back (WB) memory type for VMCS accesses. */
2926 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2927 return -EIO;
1c3d14fe 2928
002c7f7c
YS		 2929 vmcs_conf->size = vmx_msr_high & 0x1fff;
2930 vmcs_conf->order = get_order(vmcs_config.size);
2931 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2932
002c7f7c
YS		 2933 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2934 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2935 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2936 vmcs_conf->vmexit_ctrl = _vmexit_control;
2937 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2938
110312c8
AK		 2939 cpu_has_load_ia32_efer =
2940 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2941 VM_ENTRY_LOAD_IA32_EFER)
2942 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2943 VM_EXIT_LOAD_IA32_EFER);
2944
8bf00a52
GN		 2945 cpu_has_load_perf_global_ctrl =
2946 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2947 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2948 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2949 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2950
2951 /*
2952 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2953 * but due to arrata below it can't be used. Workaround is to use
2954 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2955 *
2956 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2957 *
2958 * AAK155 (model 26)
2959 * AAP115 (model 30)
2960 * AAT100 (model 37)
2961 * BC86,AAY89,BD102 (model 44)
2962 * BA97 (model 46)
2963 *
2964 */
2965 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2966 switch (boot_cpu_data.x86_model) {
2967 case 26:
2968 case 30:
2969 case 37:
2970 case 44:
2971 case 46:
2972 cpu_has_load_perf_global_ctrl = false;
2973 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2974 "does not work properly. Using workaround\n");
2975 break;
2976 default:
2977 break;
2978 }
2979 }
2980
1c3d14fe 2981 return 0;
c68876fd 2982}
6aa8b732
AK		 2983
2984static struct vmcs *alloc_vmcs_cpu(int cpu)
2985{
2986 int node = cpu_to_node(cpu);
2987 struct page *pages;
2988 struct vmcs *vmcs;
2989
6484eb3e 2990 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2991 if (!pages)
2992 return NULL;
2993 vmcs = page_address(pages);
1c3d14fe
YS		 2994 memset(vmcs, 0, vmcs_config.size);
2995 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2996 return vmcs;
2997}
2998
2999static struct vmcs *alloc_vmcs(void)
3000{
d3b2c338 3001 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 3002}
3003
3004static void free_vmcs(struct vmcs *vmcs)
3005{
1c3d14fe 3006 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 3007}
3008
d462b819
NHE		 3009/*
3010 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3011 */
3012static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3013{
3014 if (!loaded_vmcs->vmcs)
3015 return;
3016 loaded_vmcs_clear(loaded_vmcs);
3017 free_vmcs(loaded_vmcs->vmcs);
3018 loaded_vmcs->vmcs = NULL;
3019}
3020
39959588 3021static void free_kvm_area(void)
6aa8b732
AK		 3022{
3023 int cpu;
3024
3230bb47 3025 for_each_possible_cpu(cpu) {
6aa8b732 3026 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 3027 per_cpu(vmxarea, cpu) = NULL;
3028 }
6aa8b732
AK		 3029}
3030
fe2b201b
BD		 3031static void init_vmcs_shadow_fields(void)
3032{
3033 int i, j;
3034
3035 /* No checks for read only fields yet */
3036
3037 for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3038 switch (shadow_read_write_fields[i]) {
3039 case GUEST_BNDCFGS:
3040 if (!vmx_mpx_supported())
3041 continue;
3042 break;
3043 default:
3044 break;
3045 }
3046
3047 if (j < i)
3048 shadow_read_write_fields[j] =
3049 shadow_read_write_fields[i];
3050 j++;
3051 }
3052 max_shadow_read_write_fields = j;
3053
3054 /* shadowed fields guest access without vmexit */
3055 for (i = 0; i < max_shadow_read_write_fields; i++) {
3056 clear_bit(shadow_read_write_fields[i],
3057 vmx_vmwrite_bitmap);
3058 clear_bit(shadow_read_write_fields[i],
3059 vmx_vmread_bitmap);
3060 }
3061 for (i = 0; i < max_shadow_read_only_fields; i++)
3062 clear_bit(shadow_read_only_fields[i],
3063 vmx_vmread_bitmap);
3064}
3065
6aa8b732
AK		 3066static __init int alloc_kvm_area(void)
3067{
3068 int cpu;
3069
3230bb47 3070 for_each_possible_cpu(cpu) {
6aa8b732
AK		 3071 struct vmcs *vmcs;
3072
3073 vmcs = alloc_vmcs_cpu(cpu);
3074 if (!vmcs) {
3075 free_kvm_area();
3076 return -ENOMEM;
3077 }
3078
3079 per_cpu(vmxarea, cpu) = vmcs;
3080 }
3081 return 0;
3082}
3083
3084static __init int hardware_setup(void)
3085{
002c7f7c
YS		 3086 if (setup_vmcs_config(&vmcs_config) < 0)
3087 return -EIO;
50a37eb4
JR		 3088
3089 if (boot_cpu_has(X86_FEATURE_NX))
3090 kvm_enable_efer_bits(EFER_NX);
3091
93ba03c2
SY		 3092 if (!cpu_has_vmx_vpid())
3093 enable_vpid = 0;
abc4fc58
AG		 3094 if (!cpu_has_vmx_shadow_vmcs())
3095 enable_shadow_vmcs = 0;
fe2b201b
BD		 3096 if (enable_shadow_vmcs)
3097 init_vmcs_shadow_fields();
93ba03c2 3098
4bc9b982
SY		 3099 if (!cpu_has_vmx_ept() ||
3100 !cpu_has_vmx_ept_4levels()) {
93ba03c2 3101 enable_ept = 0;
3a624e29 3102 enable_unrestricted_guest = 0;
83c3a331 3103 enable_ept_ad_bits = 0;
3a624e29
NK		 3104 }
3105
83c3a331
XH		 3106 if (!cpu_has_vmx_ept_ad_bits())
3107 enable_ept_ad_bits = 0;
3108
3a624e29
NK		 3109 if (!cpu_has_vmx_unrestricted_guest())
3110 enable_unrestricted_guest = 0;
93ba03c2
SY		 3111
3112 if (!cpu_has_vmx_flexpriority())
3113 flexpriority_enabled = 0;
3114
95ba8273
GN		 3115 if (!cpu_has_vmx_tpr_shadow())
3116 kvm_x86_ops->update_cr8_intercept = NULL;
3117
54dee993
MT		 3118 if (enable_ept && !cpu_has_vmx_ept_2m_page())
3119 kvm_disable_largepages();
3120
4b8d54f9
ZE		 3121 if (!cpu_has_vmx_ple())
3122 ple_gap = 0;
3123
01e439be
YZ		 3124 if (!cpu_has_vmx_apicv())
3125 enable_apicv = 0;
c7c9c56c 3126
01e439be 3127 if (enable_apicv)
c7c9c56c 3128 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 3129 else {
c7c9c56c 3130 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 3131 kvm_x86_ops->deliver_posted_interrupt = NULL;
3132 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
3133 }
83d4c286 3134
b87a51ae
NHE		 3135 if (nested)
3136 nested_vmx_setup_ctls_msrs();
3137
6aa8b732
AK		 3138 return alloc_kvm_area();
3139}
3140
3141static __exit void hardware_unsetup(void)
3142{
3143 free_kvm_area();
3144}
3145
14168786
GN		 3146static bool emulation_required(struct kvm_vcpu *vcpu)
3147{
3148 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3149}
3150
91b0aa2c 3151static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 3152 struct kvm_segment *save)
6aa8b732 3153{
d99e4152
GN		 3154 if (!emulate_invalid_guest_state) {
3155 /*
3156 * CS and SS RPL should be equal during guest entry according
3157 * to VMX spec, but in reality it is not always so. Since vcpu
3158 * is in the middle of the transition from real mode to
3159 * protected mode it is safe to assume that RPL 0 is a good
3160 * default value.
3161 */
3162 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3163 save->selector &= ~SELECTOR_RPL_MASK;
3164 save->dpl = save->selector & SELECTOR_RPL_MASK;
3165 save->s = 1;
6aa8b732 3166 }
d99e4152 3167 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 3168}
3169
3170static void enter_pmode(struct kvm_vcpu *vcpu)
3171{
3172 unsigned long flags;
a89a8fb9 3173 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3174
d99e4152
GN		 3175 /*
3176 * Update real mode segment cache. It may be not up-to-date if sement
3177 * register was written while vcpu was in a guest mode.
3178 */
3179 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3180 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3181 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3182 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3183 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3184 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3185
7ffd92c5 3186 vmx->rmode.vm86_active = 0;
6aa8b732 3187
2fb92db1
AK		 3188 vmx_segment_cache_clear(vmx);
3189
f5f7b2fe 3190 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3191
3192 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3193 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3194 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3195 vmcs_writel(GUEST_RFLAGS, flags);
3196
66aee91a
RR		 3197 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3198 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3199
3200 update_exception_bitmap(vcpu);
3201
91b0aa2c
GN		 3202 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3203 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3204 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3205 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3206 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3207 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 3208}
3209
f5f7b2fe 3210static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3211{
772e0318 3212 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3213 struct kvm_segment var = *save;
3214
3215 var.dpl = 0x3;
3216 if (seg == VCPU_SREG_CS)
3217 var.type = 0x3;
3218
3219 if (!emulate_invalid_guest_state) {
3220 var.selector = var.base >> 4;
3221 var.base = var.base & 0xffff0;
3222 var.limit = 0xffff;
3223 var.g = 0;
3224 var.db = 0;
3225 var.present = 1;
3226 var.s = 1;
3227 var.l = 0;
3228 var.unusable = 0;
3229 var.type = 0x3;
3230 var.avl = 0;
3231 if (save->base & 0xf)
3232 printk_once(KERN_WARNING "kvm: segment base is not "
3233 "paragraph aligned when entering "
3234 "protected mode (seg=%d)", seg);
3235 }
6aa8b732 3236
d99e4152
GN		 3237 vmcs_write16(sf->selector, var.selector);
3238 vmcs_write32(sf->base, var.base);
3239 vmcs_write32(sf->limit, var.limit);
3240 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3241}
3242
3243static void enter_rmode(struct kvm_vcpu *vcpu)
3244{
3245 unsigned long flags;
a89a8fb9 3246 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3247
f5f7b2fe
AK		 3248 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3249 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3250 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3251 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3252 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3253 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3254 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3255
7ffd92c5 3256 vmx->rmode.vm86_active = 1;
6aa8b732 3257
776e58ea
GN		 3258 /*
3259 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3260 * vcpu. Warn the user that an update is overdue.
776e58ea 3261 */
4918c6ca 3262 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3263 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3264 "called before entering vcpu\n");
776e58ea 3265
2fb92db1
AK		 3266 vmx_segment_cache_clear(vmx);
3267
4918c6ca 3268 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3269 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3270 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3271
3272 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3273 vmx->rmode.save_rflags = flags;
6aa8b732 3274
053de044 3275 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3276
3277 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3278 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3279 update_exception_bitmap(vcpu);
3280
d99e4152
GN		 3281 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3282 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3283 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3284 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3285 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3286 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3287
8668a3c4 3288 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3289}
3290
401d10de
AS		 3291static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3292{
3293 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3294 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3295
3296 if (!msr)
3297 return;
401d10de 3298
44ea2b17
AK		 3299 /*
3300 * Force kernel_gs_base reloading before EFER changes, as control
3301 * of this msr depends on is_long_mode().
3302 */
3303 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3304 vcpu->arch.efer = efer;
401d10de 3305 if (efer & EFER_LMA) {
2961e876 3306 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3307 msr->data = efer;
3308 } else {
2961e876 3309 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 3310
3311 msr->data = efer & ~EFER_LME;
3312 }
3313 setup_msrs(vmx);
3314}
3315
05b3e0c2 3316#ifdef CONFIG_X86_64
6aa8b732
AK		 3317
3318static void enter_lmode(struct kvm_vcpu *vcpu)
3319{
3320 u32 guest_tr_ar;
3321
2fb92db1
AK		 3322 vmx_segment_cache_clear(to_vmx(vcpu));
3323
6aa8b732
AK		 3324 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3325 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3326 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3327 __func__);
6aa8b732
AK		 3328 vmcs_write32(GUEST_TR_AR_BYTES,
3329 (guest_tr_ar & ~AR_TYPE_MASK)
3330 | AR_TYPE_BUSY_64_TSS);
3331 }
da38f438 3332 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3333}
3334
3335static void exit_lmode(struct kvm_vcpu *vcpu)
3336{
2961e876 3337 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 3338 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3339}
3340
3341#endif
3342
2384d2b3
SY		 3343static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3344{
b9d762fa 3345 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3346 if (enable_ept) {
3347 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3348 return;
4e1096d2 3349 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3350 }
2384d2b3
SY		 3351}
3352
e8467fda
AK		 3353static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3354{
3355 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3356
3357 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3358 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3359}
3360
aff48baa
AK		 3361static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3362{
3363 if (enable_ept && is_paging(vcpu))
3364 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3365 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3366}
3367
25c4c276 3368static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3369{
fc78f519
AK		 3370 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3371
3372 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3373 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3374}
3375
1439442c
SY		 3376static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3377{
d0d538b9
GN		 3378 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3379
6de4f3ad
AK		 3380 if (!test_bit(VCPU_EXREG_PDPTR,
3381 (unsigned long *)&vcpu->arch.regs_dirty))
3382 return;
3383
1439442c 3384 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3385 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3386 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3387 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3388 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 3389 }
3390}
3391
8f5d549f
AK		 3392static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3393{
d0d538b9
GN		 3394 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3395
8f5d549f 3396 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 3397 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3398 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3399 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3400 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3401 }
6de4f3ad
AK		 3402
3403 __set_bit(VCPU_EXREG_PDPTR,
3404 (unsigned long *)&vcpu->arch.regs_avail);
3405 __set_bit(VCPU_EXREG_PDPTR,
3406 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3407}
3408
5e1746d6 3409static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3410
3411static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3412 unsigned long cr0,
3413 struct kvm_vcpu *vcpu)
3414{
5233dd51
MT		 3415 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3416 vmx_decache_cr3(vcpu);
1439442c
SY		 3417 if (!(cr0 & X86_CR0_PG)) {
3418 /* From paging/starting to nonpaging */
3419 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3420 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3421 (CPU_BASED_CR3_LOAD_EXITING |
3422 CPU_BASED_CR3_STORE_EXITING));
3423 vcpu->arch.cr0 = cr0;
fc78f519 3424 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3425 } else if (!is_paging(vcpu)) {
3426 /* From nonpaging to paging */
3427 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3428 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3429 ~(CPU_BASED_CR3_LOAD_EXITING |
3430 CPU_BASED_CR3_STORE_EXITING));
3431 vcpu->arch.cr0 = cr0;
fc78f519 3432 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3433 }
95eb84a7
SY		 3434
3435 if (!(cr0 & X86_CR0_WP))
3436 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3437}
3438
6aa8b732
AK		 3439static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3440{
7ffd92c5 3441 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3442 unsigned long hw_cr0;
3443
5037878e 3444 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3445 if (enable_unrestricted_guest)
5037878e 3446 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3447 else {
5037878e 3448 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3449
218e763f
GN		 3450 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3451 enter_pmode(vcpu);
6aa8b732 3452
218e763f
GN		 3453 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3454 enter_rmode(vcpu);
3455 }
6aa8b732 3456
05b3e0c2 3457#ifdef CONFIG_X86_64
f6801dff 3458 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3459 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3460 enter_lmode(vcpu);
707d92fa 3461 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3462 exit_lmode(vcpu);
3463 }
3464#endif
3465
089d034e 3466 if (enable_ept)
1439442c
SY		 3467 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3468
02daab21 3469 if (!vcpu->fpu_active)
81231c69 3470 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3471
6aa8b732 3472 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3473 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3474 vcpu->arch.cr0 = cr0;
14168786
GN		 3475
3476 /* depends on vcpu->arch.cr0 to be set to a new value */
3477 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3478}
3479
1439442c
SY		 3480static u64 construct_eptp(unsigned long root_hpa)
3481{
3482 u64 eptp;
3483
3484 /* TODO write the value reading from MSR */
3485 eptp = VMX_EPT_DEFAULT_MT |
3486 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3487 if (enable_ept_ad_bits)
3488 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3489 eptp |= (root_hpa & PAGE_MASK);
3490
3491 return eptp;
3492}
3493
6aa8b732
AK		 3494static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3495{
1439442c
SY		 3496 unsigned long guest_cr3;
3497 u64 eptp;
3498
3499 guest_cr3 = cr3;
089d034e 3500 if (enable_ept) {
1439442c
SY		 3501 eptp = construct_eptp(cr3);
3502 vmcs_write64(EPT_POINTER, eptp);
59ab5a8f
JK		 3503 if (is_paging(vcpu) || is_guest_mode(vcpu))
3504 guest_cr3 = kvm_read_cr3(vcpu);
3505 else
3506 guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3507 ept_load_pdptrs(vcpu);
1439442c
SY		 3508 }
3509
2384d2b3 3510 vmx_flush_tlb(vcpu);
1439442c 3511 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3512}
3513
5e1746d6 3514static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3515{
7ffd92c5 3516 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3517 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3518
5e1746d6
NHE		 3519 if (cr4 & X86_CR4_VMXE) {
3520 /*
3521 * To use VMXON (and later other VMX instructions), a guest
3522 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3523 * So basically the check on whether to allow nested VMX
3524 * is here.
3525 */
3526 if (!nested_vmx_allowed(vcpu))
3527 return 1;
1a0d74e6
JK		 3528 }
3529 if (to_vmx(vcpu)->nested.vmxon &&
3530 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3531 return 1;
3532
ad312c7c 3533 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3534 if (enable_ept) {
3535 if (!is_paging(vcpu)) {
3536 hw_cr4 &= ~X86_CR4_PAE;
3537 hw_cr4 |= X86_CR4_PSE;
c08800a5 3538 /*
e1e746b3
FW		 3539 * SMEP/SMAP is disabled if CPU is in non-paging mode
3540 * in hardware. However KVM always uses paging mode to
c08800a5 3541 * emulate guest non-paging mode with TDP.
e1e746b3
FW		 3542 * To emulate this behavior, SMEP/SMAP needs to be
3543 * manually disabled when guest switches to non-paging
3544 * mode.
c08800a5 3545 */
e1e746b3 3546 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
bc23008b
AK		 3547 } else if (!(cr4 & X86_CR4_PAE)) {
3548 hw_cr4 &= ~X86_CR4_PAE;
3549 }
3550 }
1439442c
SY		 3551
3552 vmcs_writel(CR4_READ_SHADOW, cr4);
3553 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3554 return 0;
6aa8b732
AK		 3555}
3556
6aa8b732
AK		 3557static void vmx_get_segment(struct kvm_vcpu *vcpu,
3558 struct kvm_segment *var, int seg)
3559{
a9179499 3560 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3561 u32 ar;
3562
c6ad1153 3563 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3564 *var = vmx->rmode.segs[seg];
a9179499 3565 if (seg == VCPU_SREG_TR
2fb92db1 3566 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3567 return;
1390a28b
AK		 3568 var->base = vmx_read_guest_seg_base(vmx, seg);
3569 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3570 return;
a9179499 3571 }
2fb92db1
AK		 3572 var->base = vmx_read_guest_seg_base(vmx, seg);
3573 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3574 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3575 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 3576 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 3577 var->type = ar & 15;
3578 var->s = (ar >> 4) & 1;
3579 var->dpl = (ar >> 5) & 3;
03617c18
GN		 3580 /*
3581 * Some userspaces do not preserve unusable property. Since usable
3582 * segment has to be present according to VMX spec we can use present
3583 * property to amend userspace bug by making unusable segment always
3584 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3585 * segment as unusable.
3586 */
3587 var->present = !var->unusable;
6aa8b732
AK		 3588 var->avl = (ar >> 12) & 1;
3589 var->l = (ar >> 13) & 1;
3590 var->db = (ar >> 14) & 1;
3591 var->g = (ar >> 15) & 1;
6aa8b732
AK		 3592}
3593
a9179499
AK		 3594static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3595{
a9179499
AK		 3596 struct kvm_segment s;
3597
3598 if (to_vmx(vcpu)->rmode.vm86_active) {
3599 vmx_get_segment(vcpu, &s, seg);
3600 return s.base;
3601 }
2fb92db1 3602 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3603}
3604
b09408d0 3605static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3606{
b09408d0
MT		 3607 struct vcpu_vmx *vmx = to_vmx(vcpu);
3608
ae9fedc7 3609 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 3610 return 0;
ae9fedc7
PB		 3611 else {
3612 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3613 return AR_DPL(ar);
69c73028 3614 }
69c73028
AK		 3615}
3616
653e3108 3617static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3618{
6aa8b732
AK		 3619 u32 ar;
3620
f0495f9b 3621 if (var->unusable || !var->present)
6aa8b732
AK		 3622 ar = 1 << 16;
3623 else {
3624 ar = var->type & 15;
3625 ar |= (var->s & 1) << 4;
3626 ar |= (var->dpl & 3) << 5;
3627 ar |= (var->present & 1) << 7;
3628 ar |= (var->avl & 1) << 12;
3629 ar |= (var->l & 1) << 13;
3630 ar |= (var->db & 1) << 14;
3631 ar |= (var->g & 1) << 15;
3632 }
653e3108
AK		 3633
3634 return ar;
3635}
3636
3637static void vmx_set_segment(struct kvm_vcpu *vcpu,
3638 struct kvm_segment *var, int seg)
3639{
7ffd92c5 3640 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3641 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3642
2fb92db1
AK		 3643 vmx_segment_cache_clear(vmx);
3644
1ecd50a9
GN		 3645 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3646 vmx->rmode.segs[seg] = *var;
3647 if (seg == VCPU_SREG_TR)
3648 vmcs_write16(sf->selector, var->selector);
3649 else if (var->s)
3650 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3651 goto out;
653e3108 3652 }
1ecd50a9 3653
653e3108
AK		 3654 vmcs_writel(sf->base, var->base);
3655 vmcs_write32(sf->limit, var->limit);
3656 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3657
3658 /*
3659 * Fix the "Accessed" bit in AR field of segment registers for older
3660 * qemu binaries.
3661 * IA32 arch specifies that at the time of processor reset the
3662 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3663 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3664 * state vmexit when "unrestricted guest" mode is turned on.
3665 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3666 * tree. Newer qemu binaries with that qemu fix would not need this
3667 * kvm hack.
3668 */
3669 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3670 var->type |= 0x1; /* Accessed */
3a624e29 3671
f924d66d 3672 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3673
3674out:
14168786 3675 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3676}
3677
6aa8b732
AK		 3678static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3679{
2fb92db1 3680 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3681
3682 *db = (ar >> 14) & 1;
3683 *l = (ar >> 13) & 1;
3684}
3685
89a27f4d 3686static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3687{
89a27f4d
GN		 3688 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3689 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3690}
3691
89a27f4d 3692static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3693{
89a27f4d
GN		 3694 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3695 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3696}
3697
89a27f4d 3698static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3699{
89a27f4d
GN		 3700 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3701 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3702}
3703
89a27f4d 3704static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3705{
89a27f4d
GN		 3706 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3707 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3708}
3709
648dfaa7
MG		 3710static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3711{
3712 struct kvm_segment var;
3713 u32 ar;
3714
3715 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3716 var.dpl = 0x3;
0647f4aa
GN		 3717 if (seg == VCPU_SREG_CS)
3718 var.type = 0x3;
648dfaa7
MG		 3719 ar = vmx_segment_access_rights(&var);
3720
3721 if (var.base != (var.selector << 4))
3722 return false;
89efbed0 3723 if (var.limit != 0xffff)
648dfaa7 3724 return false;
07f42f5f 3725 if (ar != 0xf3)
648dfaa7
MG		 3726 return false;
3727
3728 return true;
3729}
3730
3731static bool code_segment_valid(struct kvm_vcpu *vcpu)
3732{
3733 struct kvm_segment cs;
3734 unsigned int cs_rpl;
3735
3736 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3737 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3738
1872a3f4
AK		 3739 if (cs.unusable)
3740 return false;
648dfaa7
MG		 3741 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3742 return false;
3743 if (!cs.s)
3744 return false;
1872a3f4 3745 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3746 if (cs.dpl > cs_rpl)
3747 return false;
1872a3f4 3748 } else {
648dfaa7
MG		 3749 if (cs.dpl != cs_rpl)
3750 return false;
3751 }
3752 if (!cs.present)
3753 return false;
3754
3755 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3756 return true;
3757}
3758
3759static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3760{
3761 struct kvm_segment ss;
3762 unsigned int ss_rpl;
3763
3764 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3765 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3766
1872a3f4
AK		 3767 if (ss.unusable)
3768 return true;
3769 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3770 return false;
3771 if (!ss.s)
3772 return false;
3773 if (ss.dpl != ss_rpl) /* DPL != RPL */
3774 return false;
3775 if (!ss.present)
3776 return false;
3777
3778 return true;
3779}
3780
3781static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3782{
3783 struct kvm_segment var;
3784 unsigned int rpl;
3785
3786 vmx_get_segment(vcpu, &var, seg);
3787 rpl = var.selector & SELECTOR_RPL_MASK;
3788
1872a3f4
AK		 3789 if (var.unusable)
3790 return true;
648dfaa7
MG		 3791 if (!var.s)
3792 return false;
3793 if (!var.present)
3794 return false;
3795 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3796 if (var.dpl < rpl) /* DPL < RPL */
3797 return false;
3798 }
3799
3800 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3801 * rights flags
3802 */
3803 return true;
3804}
3805
3806static bool tr_valid(struct kvm_vcpu *vcpu)
3807{
3808 struct kvm_segment tr;
3809
3810 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3811
1872a3f4
AK		 3812 if (tr.unusable)
3813 return false;
648dfaa7
MG		 3814 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3815 return false;
1872a3f4 3816 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3817 return false;
3818 if (!tr.present)
3819 return false;
3820
3821 return true;
3822}
3823
3824static bool ldtr_valid(struct kvm_vcpu *vcpu)
3825{
3826 struct kvm_segment ldtr;
3827
3828 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3829
1872a3f4
AK		 3830 if (ldtr.unusable)
3831 return true;
648dfaa7
MG		 3832 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3833 return false;
3834 if (ldtr.type != 2)
3835 return false;
3836 if (!ldtr.present)
3837 return false;
3838
3839 return true;
3840}
3841
3842static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3843{
3844 struct kvm_segment cs, ss;
3845
3846 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3847 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3848
3849 return ((cs.selector & SELECTOR_RPL_MASK) ==
3850 (ss.selector & SELECTOR_RPL_MASK));
3851}
3852
3853/*
3854 * Check if guest state is valid. Returns true if valid, false if
3855 * not.
3856 * We assume that registers are always usable
3857 */
3858static bool guest_state_valid(struct kvm_vcpu *vcpu)
3859{
c5e97c80
GN		 3860 if (enable_unrestricted_guest)
3861 return true;
3862
648dfaa7 3863 /* real mode guest state checks */
f13882d8 3864 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3865 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3866 return false;
3867 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3868 return false;
3869 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3870 return false;
3871 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3872 return false;
3873 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3874 return false;
3875 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3876 return false;
3877 } else {
3878 /* protected mode guest state checks */
3879 if (!cs_ss_rpl_check(vcpu))
3880 return false;
3881 if (!code_segment_valid(vcpu))
3882 return false;
3883 if (!stack_segment_valid(vcpu))
3884 return false;
3885 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3886 return false;
3887 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3888 return false;
3889 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3890 return false;
3891 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3892 return false;
3893 if (!tr_valid(vcpu))
3894 return false;
3895 if (!ldtr_valid(vcpu))
3896 return false;
3897 }
3898 /* TODO:
3899 * - Add checks on RIP
3900 * - Add checks on RFLAGS
3901 */
3902
3903 return true;
3904}
3905
d77c26fc 3906static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3907{
40dcaa9f 3908 gfn_t fn;
195aefde 3909 u16 data = 0;
40dcaa9f 3910 int r, idx, ret = 0;
6aa8b732 3911
40dcaa9f 3912 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3913 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3914 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3915 if (r < 0)
10589a46 3916 goto out;
195aefde 3917 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3918 r = kvm_write_guest_page(kvm, fn++, &data,
3919 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3920 if (r < 0)
10589a46 3921 goto out;
195aefde
IE		 3922 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3923 if (r < 0)
10589a46 3924 goto out;
195aefde
IE		 3925 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3926 if (r < 0)
10589a46 3927 goto out;
195aefde 3928 data = ~0;
10589a46
MT		 3929 r = kvm_write_guest_page(kvm, fn, &data,
3930 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3931 sizeof(u8));
195aefde 3932 if (r < 0)
10589a46
MT		 3933 goto out;
3934
3935 ret = 1;
3936out:
40dcaa9f 3937 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3938 return ret;
6aa8b732
AK		 3939}
3940
b7ebfb05
SY		 3941static int init_rmode_identity_map(struct kvm *kvm)
3942{
40dcaa9f 3943 int i, idx, r, ret;
b7ebfb05
SY		 3944 pfn_t identity_map_pfn;
3945 u32 tmp;
3946
089d034e 3947 if (!enable_ept)
b7ebfb05
SY		 3948 return 1;
3949 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3950 printk(KERN_ERR "EPT: identity-mapping pagetable "
3951 "haven't been allocated!\n");
3952 return 0;
3953 }
3954 if (likely(kvm->arch.ept_identity_pagetable_done))
3955 return 1;
3956 ret = 0;
b927a3ce 3957 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3958 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3959 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3960 if (r < 0)
3961 goto out;
3962 /* Set up identity-mapping pagetable for EPT in real mode */
3963 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3964 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3965 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3966 r = kvm_write_guest_page(kvm, identity_map_pfn,
3967 &tmp, i * sizeof(tmp), sizeof(tmp));
3968 if (r < 0)
3969 goto out;
3970 }
3971 kvm->arch.ept_identity_pagetable_done = true;
3972 ret = 1;
3973out:
40dcaa9f 3974 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3975 return ret;
3976}
3977
6aa8b732
AK		 3978static void seg_setup(int seg)
3979{
772e0318 3980 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3981 unsigned int ar;
6aa8b732
AK		 3982
3983 vmcs_write16(sf->selector, 0);
3984 vmcs_writel(sf->base, 0);
3985 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3986 ar = 0x93;
3987 if (seg == VCPU_SREG_CS)
3988 ar |= 0x08; /* code segment */
3a624e29
NK		 3989
3990 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3991}
3992
f78e0e2e
SY		 3993static int alloc_apic_access_page(struct kvm *kvm)
3994{
4484141a 3995 struct page *page;
f78e0e2e
SY		 3996 struct kvm_userspace_memory_region kvm_userspace_mem;
3997 int r = 0;
3998
79fac95e 3999 mutex_lock(&kvm->slots_lock);
bfc6d222 4000 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 4001 goto out;
4002 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
4003 kvm_userspace_mem.flags = 0;
4004 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
4005 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4006 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 4007 if (r)
4008 goto out;
72dc67a6 4009
4484141a
XG		 4010 page = gfn_to_page(kvm, 0xfee00);
4011 if (is_error_page(page)) {
4012 r = -EFAULT;
4013 goto out;
4014 }
4015
4016 kvm->arch.apic_access_page = page;
f78e0e2e 4017out:
79fac95e 4018 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 4019 return r;
4020}
4021
b7ebfb05
SY		 4022static int alloc_identity_pagetable(struct kvm *kvm)
4023{
4484141a 4024 struct page *page;
b7ebfb05
SY		 4025 struct kvm_userspace_memory_region kvm_userspace_mem;
4026 int r = 0;
4027
79fac95e 4028 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 4029 if (kvm->arch.ept_identity_pagetable)
4030 goto out;
4031 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
4032 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 4033 kvm_userspace_mem.guest_phys_addr =
4034 kvm->arch.ept_identity_map_addr;
b7ebfb05 4035 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 4036 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 4037 if (r)
4038 goto out;
4039
4484141a
XG		 4040 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
4041 if (is_error_page(page)) {
4042 r = -EFAULT;
4043 goto out;
4044 }
4045
4046 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 4047out:
79fac95e 4048 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 4049 return r;
4050}
4051
2384d2b3
SY		 4052static void allocate_vpid(struct vcpu_vmx *vmx)
4053{
4054 int vpid;
4055
4056 vmx->vpid = 0;
919818ab 4057 if (!enable_vpid)
2384d2b3
SY		 4058 return;
4059 spin_lock(&vmx_vpid_lock);
4060 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4061 if (vpid < VMX_NR_VPIDS) {
4062 vmx->vpid = vpid;
4063 __set_bit(vpid, vmx_vpid_bitmap);
4064 }
4065 spin_unlock(&vmx_vpid_lock);
4066}
4067
cdbecfc3
LJ		 4068static void free_vpid(struct vcpu_vmx *vmx)
4069{
4070 if (!enable_vpid)
4071 return;
4072 spin_lock(&vmx_vpid_lock);
4073 if (vmx->vpid != 0)
4074 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
4075 spin_unlock(&vmx_vpid_lock);
4076}
4077
8d14695f
YZ		 4078#define MSR_TYPE_R 1
4079#define MSR_TYPE_W 2
4080static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4081 u32 msr, int type)
25c5f225 4082{
3e7c73e9 4083 int f = sizeof(unsigned long);
25c5f225
SY		 4084
4085 if (!cpu_has_vmx_msr_bitmap())
4086 return;
4087
4088 /*
4089 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4090 * have the write-low and read-high bitmap offsets the wrong way round.
4091 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4092 */
25c5f225 4093 if (msr <= 0x1fff) {
8d14695f
YZ		 4094 if (type & MSR_TYPE_R)
4095 /* read-low */
4096 __clear_bit(msr, msr_bitmap + 0x000 / f);
4097
4098 if (type & MSR_TYPE_W)
4099 /* write-low */
4100 __clear_bit(msr, msr_bitmap + 0x800 / f);
4101
25c5f225
SY		 4102 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4103 msr &= 0x1fff;
8d14695f
YZ		 4104 if (type & MSR_TYPE_R)
4105 /* read-high */
4106 __clear_bit(msr, msr_bitmap + 0x400 / f);
4107
4108 if (type & MSR_TYPE_W)
4109 /* write-high */
4110 __clear_bit(msr, msr_bitmap + 0xc00 / f);
4111
4112 }
4113}
4114
4115static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4116 u32 msr, int type)
4117{
4118 int f = sizeof(unsigned long);
4119
4120 if (!cpu_has_vmx_msr_bitmap())
4121 return;
4122
4123 /*
4124 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4125 * have the write-low and read-high bitmap offsets the wrong way round.
4126 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4127 */
4128 if (msr <= 0x1fff) {
4129 if (type & MSR_TYPE_R)
4130 /* read-low */
4131 __set_bit(msr, msr_bitmap + 0x000 / f);
4132
4133 if (type & MSR_TYPE_W)
4134 /* write-low */
4135 __set_bit(msr, msr_bitmap + 0x800 / f);
4136
4137 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4138 msr &= 0x1fff;
4139 if (type & MSR_TYPE_R)
4140 /* read-high */
4141 __set_bit(msr, msr_bitmap + 0x400 / f);
4142
4143 if (type & MSR_TYPE_W)
4144 /* write-high */
4145 __set_bit(msr, msr_bitmap + 0xc00 / f);
4146
25c5f225 4147 }
25c5f225
SY		 4148}
4149
5897297b
AK		 4150static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4151{
4152 if (!longmode_only)
8d14695f
YZ		 4153 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4154 msr, MSR_TYPE_R | MSR_TYPE_W);
4155 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4156 msr, MSR_TYPE_R | MSR_TYPE_W);
4157}
4158
4159static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4160{
4161 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4162 msr, MSR_TYPE_R);
4163 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4164 msr, MSR_TYPE_R);
4165}
4166
4167static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4168{
4169 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4170 msr, MSR_TYPE_R);
4171 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4172 msr, MSR_TYPE_R);
4173}
4174
4175static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4176{
4177 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4178 msr, MSR_TYPE_W);
4179 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4180 msr, MSR_TYPE_W);
5897297b
AK		 4181}
4182
01e439be
YZ		 4183static int vmx_vm_has_apicv(struct kvm *kvm)
4184{
4185 return enable_apicv && irqchip_in_kernel(kvm);
4186}
4187
a20ed54d
YZ		 4188/*
4189 * Send interrupt to vcpu via posted interrupt way.
4190 * 1. If target vcpu is running(non-root mode), send posted interrupt
4191 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4192 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4193 * interrupt from PIR in next vmentry.
4194 */
4195static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4196{
4197 struct vcpu_vmx *vmx = to_vmx(vcpu);
4198 int r;
4199
4200 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4201 return;
4202
4203 r = pi_test_and_set_on(&vmx->pi_desc);
4204 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4205#ifdef CONFIG_SMP
a20ed54d
YZ		 4206 if (!r && (vcpu->mode == IN_GUEST_MODE))
4207 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4208 POSTED_INTR_VECTOR);
4209 else
6ffbbbba 4210#endif
a20ed54d
YZ		 4211 kvm_vcpu_kick(vcpu);
4212}
4213
4214static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4215{
4216 struct vcpu_vmx *vmx = to_vmx(vcpu);
4217
4218 if (!pi_test_and_clear_on(&vmx->pi_desc))
4219 return;
4220
4221 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4222}
4223
4224static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4225{
4226 return;
4227}
4228
a3a8ff8e
NHE		 4229/*
4230 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4231 * will not change in the lifetime of the guest.
4232 * Note that host-state that does change is set elsewhere. E.g., host-state
4233 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4234 */
a547c6db 4235static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4236{
4237 u32 low32, high32;
4238 unsigned long tmpl;
4239 struct desc_ptr dt;
4240
b1a74bf8 4241 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4242 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4243 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4244
4245 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4246#ifdef CONFIG_X86_64
4247 /*
4248 * Load null selectors, so we can avoid reloading them in
4249 * __vmx_load_host_state(), in case userspace uses the null selectors
4250 * too (the expected case).
4251 */
4252 vmcs_write16(HOST_DS_SELECTOR, 0);
4253 vmcs_write16(HOST_ES_SELECTOR, 0);
4254#else
a3a8ff8e
NHE		 4255 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4256 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4257#endif
a3a8ff8e
NHE		 4258 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4259 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4260
4261 native_store_idt(&dt);
4262 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4263 vmx->host_idt_base = dt.address;
a3a8ff8e 4264
83287ea4 4265 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4266
4267 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4268 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4269 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4270 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4271
4272 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4273 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4274 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4275 }
4276}
4277
bf8179a0
NHE		 4278static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4279{
4280 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4281 if (enable_ept)
4282 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4283 if (is_guest_mode(&vmx->vcpu))
4284 vmx->vcpu.arch.cr4_guest_owned_bits &=
4285 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4286 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4287}
4288
01e439be
YZ		 4289static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4290{
4291 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4292
4293 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4294 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4295 return pin_based_exec_ctrl;
4296}
4297
bf8179a0
NHE		 4298static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4299{
4300 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
d16c293e
PB		 4301
4302 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4303 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4304
bf8179a0
NHE		 4305 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4306 exec_control &= ~CPU_BASED_TPR_SHADOW;
4307#ifdef CONFIG_X86_64
4308 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4309 CPU_BASED_CR8_LOAD_EXITING;
4310#endif
4311 }
4312 if (!enable_ept)
4313 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4314 CPU_BASED_CR3_LOAD_EXITING |
4315 CPU_BASED_INVLPG_EXITING;
4316 return exec_control;
4317}
4318
4319static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4320{
4321 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4322 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4323 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4324 if (vmx->vpid == 0)
4325 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4326 if (!enable_ept) {
4327 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4328 enable_unrestricted_guest = 0;
ad756a16
MJ		 4329 /* Enable INVPCID for non-ept guests may cause performance regression. */
4330 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4331 }
4332 if (!enable_unrestricted_guest)
4333 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4334 if (!ple_gap)
4335 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4336 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4337 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4338 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4339 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4340 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4341 (handle_vmptrld).
4342 We can NOT enable shadow_vmcs here because we don't have yet
4343 a current VMCS12
4344 */
4345 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4346 return exec_control;
4347}
4348
ce88decf
XG		 4349static void ept_set_mmio_spte_mask(void)
4350{
4351 /*
4352 * EPT Misconfigurations can be generated if the value of bits 2:0
4353 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4354 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4355 * spte.
4356 */
885032b9 4357 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4358}
4359
6aa8b732
AK		 4360/*
4361 * Sets up the vmcs for emulated real mode.
4362 */
8b9cf98c 4363static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4364{
2e4ce7f5 4365#ifdef CONFIG_X86_64
6aa8b732 4366 unsigned long a;
2e4ce7f5 4367#endif
6aa8b732 4368 int i;
6aa8b732 4369
6aa8b732 4370 /* I/O */
3e7c73e9
AK		 4371 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4372 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4373
4607c2d7
AG		 4374 if (enable_shadow_vmcs) {
4375 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4376 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4377 }
25c5f225 4378 if (cpu_has_vmx_msr_bitmap())
5897297b 4379 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4380
6aa8b732
AK		 4381 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4382
6aa8b732 4383 /* Control */
01e439be 4384 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4385
bf8179a0 4386 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4387
83ff3b9d 4388 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4389 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4390 vmx_secondary_exec_control(vmx));
83ff3b9d 4391 }
f78e0e2e 4392
01e439be 4393 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4394 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4395 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4396 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4397 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4398
4399 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4400
4401 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4402 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4403 }
4404
4b8d54f9
ZE		 4405 if (ple_gap) {
4406 vmcs_write32(PLE_GAP, ple_gap);
4407 vmcs_write32(PLE_WINDOW, ple_window);
4408 }
4409
c3707958
XG		 4410 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4411 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4412 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4413
9581d442
AK		 4414 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4415 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4416 vmx_set_constant_host_state(vmx);
05b3e0c2 4417#ifdef CONFIG_X86_64
6aa8b732
AK		 4418 rdmsrl(MSR_FS_BASE, a);
4419 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4420 rdmsrl(MSR_GS_BASE, a);
4421 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4422#else
4423 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4424 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4425#endif
4426
2cc51560
ED		 4427 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4428 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4429 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4430 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4431 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4432
468d472f 4433 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4434 u32 msr_low, msr_high;
4435 u64 host_pat;
468d472f
SY		 4436 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4437 host_pat = msr_low | ((u64) msr_high << 32);
4438 /* Write the default value follow host pat */
4439 vmcs_write64(GUEST_IA32_PAT, host_pat);
4440 /* Keep arch.pat sync with GUEST_IA32_PAT */
4441 vmx->vcpu.arch.pat = host_pat;
4442 }
4443
6aa8b732
AK		 4444 for (i = 0; i < NR_VMX_MSR; ++i) {
4445 u32 index = vmx_msr_index[i];
4446 u32 data_low, data_high;
a2fa3e9f 4447 int j = vmx->nmsrs;
6aa8b732
AK		 4448
4449 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4450 continue;
432bd6cb
AK		 4451 if (wrmsr_safe(index, data_low, data_high) < 0)
4452 continue;
26bb0981
AK		 4453 vmx->guest_msrs[j].index = i;
4454 vmx->guest_msrs[j].data = 0;
d5696725 4455 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4456 ++vmx->nmsrs;
6aa8b732 4457 }
6aa8b732 4458
2961e876
GN		 4459
4460 vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4461
4462 /* 22.2.1, 20.8.1 */
2961e876 4463 vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
1c3d14fe 4464
e00c8cf2 4465 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4466 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4467
4468 return 0;
4469}
4470
57f252f2 4471static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4472{
4473 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 4474 struct msr_data apic_base_msr;
e00c8cf2 4475
7ffd92c5 4476 vmx->rmode.vm86_active = 0;
e00c8cf2 4477
3b86cd99
JK		 4478 vmx->soft_vnmi_blocked = 0;
4479
ad312c7c 4480 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4481 kvm_set_cr8(&vmx->vcpu, 0);
58cb628d 4482 apic_base_msr.data = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4483 if (kvm_vcpu_is_bsp(&vmx->vcpu))
58cb628d
JK		 4484 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4485 apic_base_msr.host_initiated = true;
4486 kvm_set_apic_base(&vmx->vcpu, &apic_base_msr);
e00c8cf2 4487
2fb92db1
AK		 4488 vmx_segment_cache_clear(vmx);
4489
5706be0d 4490 seg_setup(VCPU_SREG_CS);
66450a21 4491 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4492 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4493
4494 seg_setup(VCPU_SREG_DS);
4495 seg_setup(VCPU_SREG_ES);
4496 seg_setup(VCPU_SREG_FS);
4497 seg_setup(VCPU_SREG_GS);
4498 seg_setup(VCPU_SREG_SS);
4499
4500 vmcs_write16(GUEST_TR_SELECTOR, 0);
4501 vmcs_writel(GUEST_TR_BASE, 0);
4502 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4503 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4504
4505 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4506 vmcs_writel(GUEST_LDTR_BASE, 0);
4507 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4508 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4509
4510 vmcs_write32(GUEST_SYSENTER_CS, 0);
4511 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4512 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4513
4514 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4515 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4516
e00c8cf2
AK		 4517 vmcs_writel(GUEST_GDTR_BASE, 0);
4518 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4519
4520 vmcs_writel(GUEST_IDTR_BASE, 0);
4521 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4522
443381a8 4523 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4524 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4525 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4526
e00c8cf2
AK		 4527 /* Special registers */
4528 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4529
4530 setup_msrs(vmx);
4531
6aa8b732
AK		 4532 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4533
f78e0e2e
SY		 4534 if (cpu_has_vmx_tpr_shadow()) {
4535 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4536 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4537 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4538 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4539 vmcs_write32(TPR_THRESHOLD, 0);
4540 }
4541
4542 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4543 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4544 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4545
01e439be
YZ		 4546 if (vmx_vm_has_apicv(vcpu->kvm))
4547 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4548
2384d2b3
SY		 4549 if (vmx->vpid != 0)
4550 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4551
fa40052c 4552 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4553 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4554 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4555 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4556 vmx_fpu_activate(&vmx->vcpu);
4557 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4558
b9d762fa 4559 vpid_sync_context(vmx);
6aa8b732
AK		 4560}
4561
b6f1250e
NHE		 4562/*
4563 * In nested virtualization, check if L1 asked to exit on external interrupts.
4564 * For most existing hypervisors, this will always return true.
4565 */
4566static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4567{
4568 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4569 PIN_BASED_EXT_INTR_MASK;
4570}
4571
77b0f5d6
BD		 4572/*
4573 * In nested virtualization, check if L1 has set
4574 * VM_EXIT_ACK_INTR_ON_EXIT
4575 */
4576static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4577{
4578 return get_vmcs12(vcpu)->vm_exit_controls &
4579 VM_EXIT_ACK_INTR_ON_EXIT;
4580}
4581
ea8ceb83
JK		 4582static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4583{
4584 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4585 PIN_BASED_NMI_EXITING;
4586}
4587
c9a7953f 4588static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4589{
4590 u32 cpu_based_vm_exec_control;
730dca42 4591
3b86cd99
JK		 4592 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4593 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4594 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4595}
4596
c9a7953f 4597static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4598{
4599 u32 cpu_based_vm_exec_control;
4600
c9a7953f
JK		 4601 if (!cpu_has_virtual_nmis() ||
4602 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4603 enable_irq_window(vcpu);
4604 return;
4605 }
3b86cd99
JK		 4606
4607 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4608 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4609 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4610}
4611
66fd3f7f 4612static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4613{
9c8cba37 4614 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4615 uint32_t intr;
4616 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4617
229456fc 4618 trace_kvm_inj_virq(irq);
2714d1d3 4619
fa89a817 4620 ++vcpu->stat.irq_injections;
7ffd92c5 4621 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4622 int inc_eip = 0;
4623 if (vcpu->arch.interrupt.soft)
4624 inc_eip = vcpu->arch.event_exit_inst_len;
4625 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4626 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4627 return;
4628 }
66fd3f7f
GN		 4629 intr = irq | INTR_INFO_VALID_MASK;
4630 if (vcpu->arch.interrupt.soft) {
4631 intr |= INTR_TYPE_SOFT_INTR;
4632 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4633 vmx->vcpu.arch.event_exit_inst_len);
4634 } else
4635 intr |= INTR_TYPE_EXT_INTR;
4636 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4637}
4638
f08864b4
SY		 4639static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4640{
66a5a347
JK		 4641 struct vcpu_vmx *vmx = to_vmx(vcpu);
4642
0b6ac343
NHE		 4643 if (is_guest_mode(vcpu))
4644 return;
4645
3b86cd99
JK		 4646 if (!cpu_has_virtual_nmis()) {
4647 /*
4648 * Tracking the NMI-blocked state in software is built upon
4649 * finding the next open IRQ window. This, in turn, depends on
4650 * well-behaving guests: They have to keep IRQs disabled at
4651 * least as long as the NMI handler runs. Otherwise we may
4652 * cause NMI nesting, maybe breaking the guest. But as this is
4653 * highly unlikely, we can live with the residual risk.
4654 */
4655 vmx->soft_vnmi_blocked = 1;
4656 vmx->vnmi_blocked_time = 0;
4657 }
4658
487b391d 4659 ++vcpu->stat.nmi_injections;
9d58b931 4660 vmx->nmi_known_unmasked = false;
7ffd92c5 4661 if (vmx->rmode.vm86_active) {
71f9833b 4662 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4663 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4664 return;
4665 }
f08864b4
SY		 4666 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4667 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4668}
4669
3cfc3092
JK		 4670static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4671{
4672 if (!cpu_has_virtual_nmis())
4673 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4674 if (to_vmx(vcpu)->nmi_known_unmasked)
4675 return false;
c332c83a 4676 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4677}
4678
4679static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4680{
4681 struct vcpu_vmx *vmx = to_vmx(vcpu);
4682
4683 if (!cpu_has_virtual_nmis()) {
4684 if (vmx->soft_vnmi_blocked != masked) {
4685 vmx->soft_vnmi_blocked = masked;
4686 vmx->vnmi_blocked_time = 0;
4687 }
4688 } else {
9d58b931 4689 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4690 if (masked)
4691 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4692 GUEST_INTR_STATE_NMI);
4693 else
4694 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4695 GUEST_INTR_STATE_NMI);
4696 }
4697}
4698
2505dc9f
JK		 4699static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4700{
b6b8a145
JK		 4701 if (to_vmx(vcpu)->nested.nested_run_pending)
4702 return 0;
ea8ceb83 4703
2505dc9f
JK		 4704 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4705 return 0;
4706
4707 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4708 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4709 | GUEST_INTR_STATE_NMI));
4710}
4711
78646121
GN		 4712static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4713{
b6b8a145
JK		 4714 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4715 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4716 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4717 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4718}
4719
cbc94022
IE		 4720static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4721{
4722 int ret;
4723 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4724 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4725 .guest_phys_addr = addr,
4726 .memory_size = PAGE_SIZE * 3,
4727 .flags = 0,
4728 };
4729
47ae31e2 4730 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4731 if (ret)
4732 return ret;
bfc6d222 4733 kvm->arch.tss_addr = addr;
93ea5388
GN		 4734 if (!init_rmode_tss(kvm))
4735 return -ENOMEM;
4736
cbc94022
IE		 4737 return 0;
4738}
4739
0ca1b4f4 4740static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4741{
77ab6db0 4742 switch (vec) {
77ab6db0 4743 case BP_VECTOR:
c573cd22
JK		 4744 /*
4745 * Update instruction length as we may reinject the exception
4746 * from user space while in guest debugging mode.
4747 */
4748 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4749 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4750 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4751 return false;
4752 /* fall through */
4753 case DB_VECTOR:
4754 if (vcpu->guest_debug &
4755 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4756 return false;
d0bfb940
JK		 4757 /* fall through */
4758 case DE_VECTOR:
77ab6db0
JK		 4759 case OF_VECTOR:
4760 case BR_VECTOR:
4761 case UD_VECTOR:
4762 case DF_VECTOR:
4763 case SS_VECTOR:
4764 case GP_VECTOR:
4765 case MF_VECTOR:
0ca1b4f4
GN		 4766 return true;
4767 break;
77ab6db0 4768 }
0ca1b4f4
GN		 4769 return false;
4770}
4771
4772static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4773 int vec, u32 err_code)
4774{
4775 /*
4776 * Instruction with address size override prefix opcode 0x67
4777 * Cause the #SS fault with 0 error code in VM86 mode.
4778 */
4779 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4780 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4781 if (vcpu->arch.halt_request) {
4782 vcpu->arch.halt_request = 0;
4783 return kvm_emulate_halt(vcpu);
4784 }
4785 return 1;
4786 }
4787 return 0;
4788 }
4789
4790 /*
4791 * Forward all other exceptions that are valid in real mode.
4792 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4793 * the required debugging infrastructure rework.
4794 */
4795 kvm_queue_exception(vcpu, vec);
4796 return 1;
6aa8b732
AK		 4797}
4798
a0861c02
AK		 4799/*
4800 * Trigger machine check on the host. We assume all the MSRs are already set up
4801 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4802 * We pass a fake environment to the machine check handler because we want
4803 * the guest to be always treated like user space, no matter what context
4804 * it used internally.
4805 */
4806static void kvm_machine_check(void)
4807{
4808#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4809 struct pt_regs regs = {
4810 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4811 .flags = X86_EFLAGS_IF,
4812 };
4813
4814 do_machine_check(&regs, 0);
4815#endif
4816}
4817
851ba692 4818static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4819{
4820 /* already handled by vcpu_run */
4821 return 1;
4822}
4823
851ba692 4824static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4825{
1155f76a 4826 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4827 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4828 u32 intr_info, ex_no, error_code;
42dbaa5a 4829 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4830 u32 vect_info;
4831 enum emulation_result er;
4832
1155f76a 4833 vect_info = vmx->idt_vectoring_info;
88786475 4834 intr_info = vmx->exit_intr_info;
6aa8b732 4835
a0861c02 4836 if (is_machine_check(intr_info))
851ba692 4837 return handle_machine_check(vcpu);
a0861c02 4838
e4a41889 4839 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4840 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4841
4842 if (is_no_device(intr_info)) {
5fd86fcf 4843 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4844 return 1;
4845 }
4846
7aa81cc0 4847 if (is_invalid_opcode(intr_info)) {
51d8b661 4848 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4849 if (er != EMULATE_DONE)
7ee5d940 4850 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4851 return 1;
4852 }
4853
6aa8b732 4854 error_code = 0;
2e11384c 4855 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4856 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4857
4858 /*
4859 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4860 * MMIO, it is better to report an internal error.
4861 * See the comments in vmx_handle_exit.
4862 */
4863 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4864 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4865 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4866 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4867 vcpu->run->internal.ndata = 2;
4868 vcpu->run->internal.data[0] = vect_info;
4869 vcpu->run->internal.data[1] = intr_info;
4870 return 0;
4871 }
4872
6aa8b732 4873 if (is_page_fault(intr_info)) {
1439442c 4874 /* EPT won't cause page fault directly */
cf3ace79 4875 BUG_ON(enable_ept);
6aa8b732 4876 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4877 trace_kvm_page_fault(cr2, error_code);
4878
3298b75c 4879 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4880 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4881 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4882 }
4883
d0bfb940 4884 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4885
4886 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4887 return handle_rmode_exception(vcpu, ex_no, error_code);
4888
42dbaa5a
JK		 4889 switch (ex_no) {
4890 case DB_VECTOR:
4891 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4892 if (!(vcpu->guest_debug &
4893 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52
JK		 4894 vcpu->arch.dr6 &= ~15;
4895 vcpu->arch.dr6 |= dr6;
fd2a445a
HD		 4896 if (!(dr6 & ~DR6_RESERVED)) /* icebp */
4897 skip_emulated_instruction(vcpu);
4898
42dbaa5a
JK		 4899 kvm_queue_exception(vcpu, DB_VECTOR);
4900 return 1;
4901 }
4902 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4903 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4904 /* fall through */
4905 case BP_VECTOR:
c573cd22
JK		 4906 /*
4907 * Update instruction length as we may reinject #BP from
4908 * user space while in guest debugging mode. Reading it for
4909 * #DB as well causes no harm, it is not used in that case.
4910 */
4911 vmx->vcpu.arch.event_exit_inst_len =
4912 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4913 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4914 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4915 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4916 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4917 break;
4918 default:
d0bfb940
JK		 4919 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4920 kvm_run->ex.exception = ex_no;
4921 kvm_run->ex.error_code = error_code;
42dbaa5a 4922 break;
6aa8b732 4923 }
6aa8b732
AK		 4924 return 0;
4925}
4926
851ba692 4927static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4928{
1165f5fe 4929 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4930 return 1;
4931}
4932
851ba692 4933static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4934{
851ba692 4935 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4936 return 0;
4937}
6aa8b732 4938
851ba692 4939static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4940{
bfdaab09 4941 unsigned long exit_qualification;
34c33d16 4942 int size, in, string;
039576c0 4943 unsigned port;
6aa8b732 4944
bfdaab09 4945 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4946 string = (exit_qualification & 16) != 0;
cf8f70bf 4947 in = (exit_qualification & 8) != 0;
e70669ab 4948
cf8f70bf 4949 ++vcpu->stat.io_exits;
e70669ab 4950
cf8f70bf 4951 if (string || in)
51d8b661 4952 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4953
cf8f70bf
GN		 4954 port = exit_qualification >> 16;
4955 size = (exit_qualification & 7) + 1;
e93f36bc 4956 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4957
4958 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4959}
4960
102d8325
IM		 4961static void
4962vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4963{
4964 /*
4965 * Patch in the VMCALL instruction:
4966 */
4967 hypercall[0] = 0x0f;
4968 hypercall[1] = 0x01;
4969 hypercall[2] = 0xc1;
102d8325
IM		 4970}
4971
92fbc7b1
JK		 4972static bool nested_cr0_valid(struct vmcs12 *vmcs12, unsigned long val)
4973{
4974 unsigned long always_on = VMXON_CR0_ALWAYSON;
4975
4976 if (nested_vmx_secondary_ctls_high &
4977 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
4978 nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
4979 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
4980 return (val & always_on) == always_on;
4981}
4982
0fa06071 4983/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4984static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4985{
eeadf9e7 4986 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4987 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4988 unsigned long orig_val = val;
4989
eeadf9e7
NHE		 4990 /*
4991 * We get here when L2 changed cr0 in a way that did not change
4992 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4993 * but did change L0 shadowed bits. So we first calculate the
4994 * effective cr0 value that L1 would like to write into the
4995 * hardware. It consists of the L2-owned bits from the new
4996 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4997 */
1a0d74e6
JK		 4998 val = (val & ~vmcs12->cr0_guest_host_mask) |
4999 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5000
92fbc7b1 5001 if (!nested_cr0_valid(vmcs12, val))
eeadf9e7 5002 return 1;
1a0d74e6
JK		 5003
5004 if (kvm_set_cr0(vcpu, val))
5005 return 1;
5006 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 5007 return 0;
1a0d74e6
JK		 5008 } else {
5009 if (to_vmx(vcpu)->nested.vmxon &&
5010 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5011 return 1;
eeadf9e7 5012 return kvm_set_cr0(vcpu, val);
1a0d74e6 5013 }
eeadf9e7
NHE		 5014}
5015
5016static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5017{
5018 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 5019 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5020 unsigned long orig_val = val;
5021
5022 /* analogously to handle_set_cr0 */
5023 val = (val & ~vmcs12->cr4_guest_host_mask) |
5024 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5025 if (kvm_set_cr4(vcpu, val))
eeadf9e7 5026 return 1;
1a0d74e6 5027 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 5028 return 0;
5029 } else
5030 return kvm_set_cr4(vcpu, val);
5031}
5032
5033/* called to set cr0 as approriate for clts instruction exit. */
5034static void handle_clts(struct kvm_vcpu *vcpu)
5035{
5036 if (is_guest_mode(vcpu)) {
5037 /*
5038 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5039 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5040 * just pretend it's off (also in arch.cr0 for fpu_activate).
5041 */
5042 vmcs_writel(CR0_READ_SHADOW,
5043 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5044 vcpu->arch.cr0 &= ~X86_CR0_TS;
5045 } else
5046 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5047}
5048
851ba692 5049static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 5050{
229456fc 5051 unsigned long exit_qualification, val;
6aa8b732
AK		 5052 int cr;
5053 int reg;
49a9b07e 5054 int err;
6aa8b732 5055
bfdaab09 5056 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 5057 cr = exit_qualification & 15;
5058 reg = (exit_qualification >> 8) & 15;
5059 switch ((exit_qualification >> 4) & 3) {
5060 case 0: /* mov to cr */
229456fc
MT		 5061 val = kvm_register_read(vcpu, reg);
5062 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 5063 switch (cr) {
5064 case 0:
eeadf9e7 5065 err = handle_set_cr0(vcpu, val);
db8fcefa 5066 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5067 return 1;
5068 case 3:
2390218b 5069 err = kvm_set_cr3(vcpu, val);
db8fcefa 5070 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 5071 return 1;
5072 case 4:
eeadf9e7 5073 err = handle_set_cr4(vcpu, val);
db8fcefa 5074 kvm_complete_insn_gp(vcpu, err);
6aa8b732 5075 return 1;
0a5fff19
GN		 5076 case 8: {
5077 u8 cr8_prev = kvm_get_cr8(vcpu);
5078 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 5079 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 5080 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 5081 if (irqchip_in_kernel(vcpu->kvm))
5082 return 1;
5083 if (cr8_prev <= cr8)
5084 return 1;
851ba692 5085 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 5086 return 0;
5087 }
4b8073e4 5088 }
6aa8b732 5089 break;
25c4c276 5090 case 2: /* clts */
eeadf9e7 5091 handle_clts(vcpu);
4d4ec087 5092 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 5093 skip_emulated_instruction(vcpu);
6b52d186 5094 vmx_fpu_activate(vcpu);
25c4c276 5095 return 1;
6aa8b732
AK		 5096 case 1: /*mov from cr*/
5097 switch (cr) {
5098 case 3:
9f8fe504
AK		 5099 val = kvm_read_cr3(vcpu);
5100 kvm_register_write(vcpu, reg, val);
5101 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5102 skip_emulated_instruction(vcpu);
5103 return 1;
5104 case 8:
229456fc
MT		 5105 val = kvm_get_cr8(vcpu);
5106 kvm_register_write(vcpu, reg, val);
5107 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 5108 skip_emulated_instruction(vcpu);
5109 return 1;
5110 }
5111 break;
5112 case 3: /* lmsw */
a1f83a74 5113 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 5114 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 5115 kvm_lmsw(vcpu, val);
6aa8b732
AK		 5116
5117 skip_emulated_instruction(vcpu);
5118 return 1;
5119 default:
5120 break;
5121 }
851ba692 5122 vcpu->run->exit_reason = 0;
a737f256 5123 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 5124 (int)(exit_qualification >> 4) & 3, cr);
5125 return 0;
5126}
5127
851ba692 5128static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 5129{
bfdaab09 5130 unsigned long exit_qualification;
6aa8b732
AK		 5131 int dr, reg;
5132
f2483415 5133 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 5134 if (!kvm_require_cpl(vcpu, 0))
5135 return 1;
42dbaa5a
JK		 5136 dr = vmcs_readl(GUEST_DR7);
5137 if (dr & DR7_GD) {
5138 /*
5139 * As the vm-exit takes precedence over the debug trap, we
5140 * need to emulate the latter, either for the host or the
5141 * guest debugging itself.
5142 */
5143 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 5144 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5145 vcpu->run->debug.arch.dr7 = dr;
5146 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 5147 vmcs_readl(GUEST_CS_BASE) +
5148 vmcs_readl(GUEST_RIP);
851ba692
AK		 5149 vcpu->run->debug.arch.exception = DB_VECTOR;
5150 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 5151 return 0;
5152 } else {
5153 vcpu->arch.dr7 &= ~DR7_GD;
5154 vcpu->arch.dr6 |= DR6_BD;
5155 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
5156 kvm_queue_exception(vcpu, DB_VECTOR);
5157 return 1;
5158 }
5159 }
5160
81908bf4
PB		 5161 if (vcpu->guest_debug == 0) {
5162 u32 cpu_based_vm_exec_control;
5163
5164 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5165 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5166 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5167
5168 /*
5169 * No more DR vmexits; force a reload of the debug registers
5170 * and reenter on this instruction. The next vmexit will
5171 * retrieve the full state of the debug registers.
5172 */
5173 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5174 return 1;
5175 }
5176
bfdaab09 5177 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5178 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5179 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5180 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 5181 unsigned long val;
4c4d563b
JK		 5182
5183 if (kvm_get_dr(vcpu, dr, &val))
5184 return 1;
5185 kvm_register_write(vcpu, reg, val);
020df079 5186 } else
a4ab9d0c 5187 if (kvm_set_dr(vcpu, dr, kvm_register_read(vcpu, reg)))
4c4d563b
JK		 5188 return 1;
5189
6aa8b732
AK		 5190 skip_emulated_instruction(vcpu);
5191 return 1;
5192}
5193
73aaf249
JK		 5194static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5195{
5196 return vcpu->arch.dr6;
5197}
5198
5199static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5200{
5201}
5202
81908bf4
PB		 5203static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5204{
5205 u32 cpu_based_vm_exec_control;
5206
5207 get_debugreg(vcpu->arch.db[0], 0);
5208 get_debugreg(vcpu->arch.db[1], 1);
5209 get_debugreg(vcpu->arch.db[2], 2);
5210 get_debugreg(vcpu->arch.db[3], 3);
5211 get_debugreg(vcpu->arch.dr6, 6);
5212 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5213
5214 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5215
5216 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5217 cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5218 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5219}
5220
020df079
GN		 5221static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5222{
5223 vmcs_writel(GUEST_DR7, val);
5224}
5225
851ba692 5226static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5227{
06465c5a
AK		 5228 kvm_emulate_cpuid(vcpu);
5229 return 1;
6aa8b732
AK		 5230}
5231
851ba692 5232static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5233{
ad312c7c 5234 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5235 u64 data;
5236
5237 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5238 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5239 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5240 return 1;
5241 }
5242
229456fc 5243 trace_kvm_msr_read(ecx, data);
2714d1d3 5244
6aa8b732 5245 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5246 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5247 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5248 skip_emulated_instruction(vcpu);
5249 return 1;
5250}
5251
851ba692 5252static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5253{
8fe8ab46 5254 struct msr_data msr;
ad312c7c
ZX		 5255 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5256 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5257 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5258
8fe8ab46
WA		 5259 msr.data = data;
5260 msr.index = ecx;
5261 msr.host_initiated = false;
5262 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5263 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5264 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5265 return 1;
5266 }
5267
59200273 5268 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5269 skip_emulated_instruction(vcpu);
5270 return 1;
5271}
5272
851ba692 5273static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5274{
3842d135 5275 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5276 return 1;
5277}
5278
851ba692 5279static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5280{
85f455f7
ED		 5281 u32 cpu_based_vm_exec_control;
5282
5283 /* clear pending irq */
5284 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5285 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5286 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5287
3842d135
AK		 5288 kvm_make_request(KVM_REQ_EVENT, vcpu);
5289
a26bf12a 5290 ++vcpu->stat.irq_window_exits;
2714d1d3 5291
c1150d8c
DL		 5292 /*
5293 * If the user space waits to inject interrupts, exit as soon as
5294 * possible
5295 */
8061823a 5296 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5297 vcpu->run->request_interrupt_window &&
8061823a 5298 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5299 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5300 return 0;
5301 }
6aa8b732
AK		 5302 return 1;
5303}
5304
851ba692 5305static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5306{
5307 skip_emulated_instruction(vcpu);
d3bef15f 5308 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5309}
5310
851ba692 5311static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5312{
510043da 5313 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5314 kvm_emulate_hypercall(vcpu);
5315 return 1;
c21415e8
IM		 5316}
5317
ec25d5e6
GN		 5318static int handle_invd(struct kvm_vcpu *vcpu)
5319{
51d8b661 5320 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5321}
5322
851ba692 5323static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5324{
f9c617f6 5325 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5326
5327 kvm_mmu_invlpg(vcpu, exit_qualification);
5328 skip_emulated_instruction(vcpu);
5329 return 1;
5330}
5331
fee84b07
AK		 5332static int handle_rdpmc(struct kvm_vcpu *vcpu)
5333{
5334 int err;
5335
5336 err = kvm_rdpmc(vcpu);
5337 kvm_complete_insn_gp(vcpu, err);
5338
5339 return 1;
5340}
5341
851ba692 5342static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5343{
5344 skip_emulated_instruction(vcpu);
f5f48ee1 5345 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5346 return 1;
5347}
5348
2acf923e
DC		 5349static int handle_xsetbv(struct kvm_vcpu *vcpu)
5350{
5351 u64 new_bv = kvm_read_edx_eax(vcpu);
5352 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5353
5354 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5355 skip_emulated_instruction(vcpu);
5356 return 1;
5357}
5358
851ba692 5359static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5360{
58fbbf26
KT		 5361 if (likely(fasteoi)) {
5362 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5363 int access_type, offset;
5364
5365 access_type = exit_qualification & APIC_ACCESS_TYPE;
5366 offset = exit_qualification & APIC_ACCESS_OFFSET;
5367 /*
5368 * Sane guest uses MOV to write EOI, with written value
5369 * not cared. So make a short-circuit here by avoiding
5370 * heavy instruction emulation.
5371 */
5372 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5373 (offset == APIC_EOI)) {
5374 kvm_lapic_set_eoi(vcpu);
5375 skip_emulated_instruction(vcpu);
5376 return 1;
5377 }
5378 }
51d8b661 5379 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5380}
5381
c7c9c56c
YZ		 5382static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5383{
5384 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5385 int vector = exit_qualification & 0xff;
5386
5387 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5388 kvm_apic_set_eoi_accelerated(vcpu, vector);
5389 return 1;
5390}
5391
83d4c286
YZ		 5392static int handle_apic_write(struct kvm_vcpu *vcpu)
5393{
5394 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5395 u32 offset = exit_qualification & 0xfff;
5396
5397 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5398 kvm_apic_write_nodecode(vcpu, offset);
5399 return 1;
5400}
5401
851ba692 5402static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5403{
60637aac 5404 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5405 unsigned long exit_qualification;
e269fb21
JK		 5406 bool has_error_code = false;
5407 u32 error_code = 0;
37817f29 5408 u16 tss_selector;
7f3d35fd 5409 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5410
5411 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5412 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5413 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5414
5415 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5416
5417 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5418 if (reason == TASK_SWITCH_GATE && idt_v) {
5419 switch (type) {
5420 case INTR_TYPE_NMI_INTR:
5421 vcpu->arch.nmi_injected = false;
654f06fc 5422 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5423 break;
5424 case INTR_TYPE_EXT_INTR:
66fd3f7f 5425 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5426 kvm_clear_interrupt_queue(vcpu);
5427 break;
5428 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5429 if (vmx->idt_vectoring_info &
5430 VECTORING_INFO_DELIVER_CODE_MASK) {
5431 has_error_code = true;
5432 error_code =
5433 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5434 }
5435 /* fall through */
64a7ec06
GN		 5436 case INTR_TYPE_SOFT_EXCEPTION:
5437 kvm_clear_exception_queue(vcpu);
5438 break;
5439 default:
5440 break;
5441 }
60637aac 5442 }
37817f29
IE		 5443 tss_selector = exit_qualification;
5444
64a7ec06
GN		 5445 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5446 type != INTR_TYPE_EXT_INTR &&
5447 type != INTR_TYPE_NMI_INTR))
5448 skip_emulated_instruction(vcpu);
5449
7f3d35fd
KW		 5450 if (kvm_task_switch(vcpu, tss_selector,
5451 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5452 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5453 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5454 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5455 vcpu->run->internal.ndata = 0;
42dbaa5a 5456 return 0;
acb54517 5457 }
42dbaa5a
JK		 5458
5459 /* clear all local breakpoint enable flags */
1f854112 5460 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~0x55);
42dbaa5a
JK		 5461
5462 /*
5463 * TODO: What about debug traps on tss switch?
5464 * Are we supposed to inject them and update dr6?
5465 */
5466
5467 return 1;
37817f29
IE		 5468}
5469
851ba692 5470static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5471{
f9c617f6 5472 unsigned long exit_qualification;
1439442c 5473 gpa_t gpa;
4f5982a5 5474 u32 error_code;
1439442c 5475 int gla_validity;
1439442c 5476
f9c617f6 5477 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5478
1439442c
SY		 5479 gla_validity = (exit_qualification >> 7) & 0x3;
5480 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5481 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5482 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5483 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5484 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5485 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5486 (long unsigned int)exit_qualification);
851ba692
AK		 5487 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5488 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5489 return 0;
1439442c
SY		 5490 }
5491
0be9c7a8
GN		 5492 /*
5493 * EPT violation happened while executing iret from NMI,
5494 * "blocked by NMI" bit has to be set before next VM entry.
5495 * There are errata that may cause this bit to not be set:
5496 * AAK134, BY25.
5497 */
bcd1c294
GN		 5498 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5499 cpu_has_virtual_nmis() &&
5500 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 5501 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5502
1439442c 5503 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5504 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5505
5506 /* It is a write fault? */
5507 error_code = exit_qualification & (1U << 1);
25d92081
YZ		 5508 /* It is a fetch fault? */
5509 error_code |= (exit_qualification & (1U << 2)) << 2;
4f5982a5
XG		 5510 /* ept page table is present? */
5511 error_code |= (exit_qualification >> 3) & 0x1;
5512
25d92081
YZ		 5513 vcpu->arch.exit_qualification = exit_qualification;
5514
4f5982a5 5515 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5516}
5517
68f89400
MT		 5518static u64 ept_rsvd_mask(u64 spte, int level)
5519{
5520 int i;
5521 u64 mask = 0;
5522
5523 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5524 mask |= (1ULL << i);
5525
5526 if (level > 2)
5527 /* bits 7:3 reserved */
5528 mask |= 0xf8;
5529 else if (level == 2) {
5530 if (spte & (1ULL << 7))
5531 /* 2MB ref, bits 20:12 reserved */
5532 mask |= 0x1ff000;
5533 else
5534 /* bits 6:3 reserved */
5535 mask |= 0x78;
5536 }
5537
5538 return mask;
5539}
5540
5541static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5542 int level)
5543{
5544 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5545
5546 /* 010b (write-only) */
5547 WARN_ON((spte & 0x7) == 0x2);
5548
5549 /* 110b (write/execute) */
5550 WARN_ON((spte & 0x7) == 0x6);
5551
5552 /* 100b (execute-only) and value not supported by logical processor */
5553 if (!cpu_has_vmx_ept_execute_only())
5554 WARN_ON((spte & 0x7) == 0x4);
5555
5556 /* not 000b */
5557 if ((spte & 0x7)) {
5558 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5559
5560 if (rsvd_bits != 0) {
5561 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5562 __func__, rsvd_bits);
5563 WARN_ON(1);
5564 }
5565
5566 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5567 u64 ept_mem_type = (spte & 0x38) >> 3;
5568
5569 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5570 ept_mem_type == 7) {
5571 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5572 __func__, ept_mem_type);
5573 WARN_ON(1);
5574 }
5575 }
5576 }
5577}
5578
851ba692 5579static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5580{
5581 u64 sptes[4];
ce88decf 5582 int nr_sptes, i, ret;
68f89400
MT		 5583 gpa_t gpa;
5584
5585 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
68c3b4d1
MT		 5586 if (!kvm_io_bus_write(vcpu->kvm, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5587 skip_emulated_instruction(vcpu);
5588 return 1;
5589 }
68f89400 5590
ce88decf 5591 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5592 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5593 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5594 EMULATE_DONE;
f8f55942
XG		 5595
5596 if (unlikely(ret == RET_MMIO_PF_INVALID))
5597 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5598
b37fbea6 5599 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5600 return 1;
5601
5602 /* It is the real ept misconfig */
68f89400
MT		 5603 printk(KERN_ERR "EPT: Misconfiguration.\n");
5604 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5605
5606 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5607
5608 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5609 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5610
851ba692
AK		 5611 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5612 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5613
5614 return 0;
5615}
5616
851ba692 5617static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5618{
5619 u32 cpu_based_vm_exec_control;
5620
5621 /* clear pending NMI */
5622 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5623 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5624 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5625 ++vcpu->stat.nmi_window_exits;
3842d135 5626 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5627
5628 return 1;
5629}
5630
80ced186 5631static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5632{
8b3079a5
AK		 5633 struct vcpu_vmx *vmx = to_vmx(vcpu);
5634 enum emulation_result err = EMULATE_DONE;
80ced186 5635 int ret = 1;
49e9d557
AK		 5636 u32 cpu_exec_ctrl;
5637 bool intr_window_requested;
b8405c18 5638 unsigned count = 130;
49e9d557
AK		 5639
5640 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5641 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5642
b8405c18 5643 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5644 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5645 return handle_interrupt_window(&vmx->vcpu);
5646
de87dcdd
AK		 5647 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5648 return 1;
5649
991eebf9 5650 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5651
ac0a48c3 5652 if (err == EMULATE_USER_EXIT) {
94452b9e 5653 ++vcpu->stat.mmio_exits;
80ced186
MG		 5654 ret = 0;
5655 goto out;
5656 }
1d5a4d9b 5657
de5f70e0
AK		 5658 if (err != EMULATE_DONE) {
5659 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5660 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5661 vcpu->run->internal.ndata = 0;
6d77dbfc 5662 return 0;
de5f70e0 5663 }
ea953ef0 5664
8d76c49e
GN		 5665 if (vcpu->arch.halt_request) {
5666 vcpu->arch.halt_request = 0;
5667 ret = kvm_emulate_halt(vcpu);
5668 goto out;
5669 }
5670
ea953ef0 5671 if (signal_pending(current))
80ced186 5672 goto out;
ea953ef0
MG		 5673 if (need_resched())
5674 schedule();
5675 }
5676
14168786 5677 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5678out:
5679 return ret;
ea953ef0
MG		 5680}
5681
4b8d54f9
ZE		 5682/*
5683 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5684 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5685 */
9fb41ba8 5686static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5687{
5688 skip_emulated_instruction(vcpu);
5689 kvm_vcpu_on_spin(vcpu);
5690
5691 return 1;
5692}
5693
87c00572 5694static int handle_nop(struct kvm_vcpu *vcpu)
59708670 5695{
87c00572 5696 skip_emulated_instruction(vcpu);
59708670
SY		 5697 return 1;
5698}
5699
87c00572
GS		 5700static int handle_mwait(struct kvm_vcpu *vcpu)
5701{
5702 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
5703 return handle_nop(vcpu);
5704}
5705
5706static int handle_monitor(struct kvm_vcpu *vcpu)
5707{
5708 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5709 return handle_nop(vcpu);
5710}
5711
ff2f6fe9
NHE		 5712/*
5713 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5714 * We could reuse a single VMCS for all the L2 guests, but we also want the
5715 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5716 * allows keeping them loaded on the processor, and in the future will allow
5717 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5718 * every entry if they never change.
5719 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5720 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5721 *
5722 * The following functions allocate and free a vmcs02 in this pool.
5723 */
5724
5725/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5726static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5727{
5728 struct vmcs02_list *item;
5729 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5730 if (item->vmptr == vmx->nested.current_vmptr) {
5731 list_move(&item->list, &vmx->nested.vmcs02_pool);
5732 return &item->vmcs02;
5733 }
5734
5735 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5736 /* Recycle the least recently used VMCS. */
5737 item = list_entry(vmx->nested.vmcs02_pool.prev,
5738 struct vmcs02_list, list);
5739 item->vmptr = vmx->nested.current_vmptr;
5740 list_move(&item->list, &vmx->nested.vmcs02_pool);
5741 return &item->vmcs02;
5742 }
5743
5744 /* Create a new VMCS */
0fa24ce3 5745 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5746 if (!item)
5747 return NULL;
5748 item->vmcs02.vmcs = alloc_vmcs();
5749 if (!item->vmcs02.vmcs) {
5750 kfree(item);
5751 return NULL;
5752 }
5753 loaded_vmcs_init(&item->vmcs02);
5754 item->vmptr = vmx->nested.current_vmptr;
5755 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5756 vmx->nested.vmcs02_num++;
5757 return &item->vmcs02;
5758}
5759
5760/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5761static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5762{
5763 struct vmcs02_list *item;
5764 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5765 if (item->vmptr == vmptr) {
5766 free_loaded_vmcs(&item->vmcs02);
5767 list_del(&item->list);
5768 kfree(item);
5769 vmx->nested.vmcs02_num--;
5770 return;
5771 }
5772}
5773
5774/*
5775 * Free all VMCSs saved for this vcpu, except the one pointed by
5776 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5777 * currently used, if running L2), and vmcs01 when running L2.
5778 */
5779static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5780{
5781 struct vmcs02_list *item, *n;
5782 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5783 if (vmx->loaded_vmcs != &item->vmcs02)
5784 free_loaded_vmcs(&item->vmcs02);
5785 list_del(&item->list);
5786 kfree(item);
5787 }
5788 vmx->nested.vmcs02_num = 0;
5789
5790 if (vmx->loaded_vmcs != &vmx->vmcs01)
5791 free_loaded_vmcs(&vmx->vmcs01);
5792}
5793
0658fbaa
ACL		 5794/*
5795 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5796 * set the success or error code of an emulated VMX instruction, as specified
5797 * by Vol 2B, VMX Instruction Reference, "Conventions".
5798 */
5799static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5800{
5801 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5802 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5803 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5804}
5805
5806static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5807{
5808 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5809 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5810 X86_EFLAGS_SF | X86_EFLAGS_OF))
5811 | X86_EFLAGS_CF);
5812}
5813
145c28dd 5814static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
0658fbaa
ACL		 5815 u32 vm_instruction_error)
5816{
5817 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5818 /*
5819 * failValid writes the error number to the current VMCS, which
5820 * can't be done there isn't a current VMCS.
5821 */
5822 nested_vmx_failInvalid(vcpu);
5823 return;
5824 }
5825 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5826 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5827 X86_EFLAGS_SF | X86_EFLAGS_OF))
5828 | X86_EFLAGS_ZF);
5829 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5830 /*
5831 * We don't need to force a shadow sync because
5832 * VM_INSTRUCTION_ERROR is not shadowed
5833 */
5834}
145c28dd 5835
f4124500
JK		 5836static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
5837{
5838 struct vcpu_vmx *vmx =
5839 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
5840
5841 vmx->nested.preemption_timer_expired = true;
5842 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5843 kvm_vcpu_kick(&vmx->vcpu);
5844
5845 return HRTIMER_NORESTART;
5846}
5847
19677e32
BD		 5848/*
5849 * Decode the memory-address operand of a vmx instruction, as recorded on an
5850 * exit caused by such an instruction (run by a guest hypervisor).
5851 * On success, returns 0. When the operand is invalid, returns 1 and throws
5852 * #UD or #GP.
5853 */
5854static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5855 unsigned long exit_qualification,
5856 u32 vmx_instruction_info, gva_t *ret)
5857{
5858 /*
5859 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5860 * Execution", on an exit, vmx_instruction_info holds most of the
5861 * addressing components of the operand. Only the displacement part
5862 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5863 * For how an actual address is calculated from all these components,
5864 * refer to Vol. 1, "Operand Addressing".
5865 */
5866 int scaling = vmx_instruction_info & 3;
5867 int addr_size = (vmx_instruction_info >> 7) & 7;
5868 bool is_reg = vmx_instruction_info & (1u << 10);
5869 int seg_reg = (vmx_instruction_info >> 15) & 7;
5870 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5871 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5872 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5873 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5874
5875 if (is_reg) {
5876 kvm_queue_exception(vcpu, UD_VECTOR);
5877 return 1;
5878 }
5879
5880 /* Addr = segment_base + offset */
5881 /* offset = base + [index * scale] + displacement */
5882 *ret = vmx_get_segment_base(vcpu, seg_reg);
5883 if (base_is_valid)
5884 *ret += kvm_register_read(vcpu, base_reg);
5885 if (index_is_valid)
5886 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5887 *ret += exit_qualification; /* holds the displacement */
5888
5889 if (addr_size == 1) /* 32 bit */
5890 *ret &= 0xffffffff;
5891
5892 /*
5893 * TODO: throw #GP (and return 1) in various cases that the VM*
5894 * instructions require it - e.g., offset beyond segment limit,
5895 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5896 * address, and so on. Currently these are not checked.
5897 */
5898 return 0;
5899}
5900
3573e22c
BD		 5901/*
5902 * This function performs the various checks including
5903 * - if it's 4KB aligned
5904 * - No bits beyond the physical address width are set
5905 * - Returns 0 on success or else 1
4291b588 5906 * (Intel SDM Section 30.3)
3573e22c 5907 */
4291b588
BD		 5908static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
5909 gpa_t *vmpointer)
3573e22c
BD		 5910{
5911 gva_t gva;
5912 gpa_t vmptr;
5913 struct x86_exception e;
5914 struct page *page;
5915 struct vcpu_vmx *vmx = to_vmx(vcpu);
5916 int maxphyaddr = cpuid_maxphyaddr(vcpu);
5917
5918 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5919 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5920 return 1;
5921
5922 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5923 sizeof(vmptr), &e)) {
5924 kvm_inject_page_fault(vcpu, &e);
5925 return 1;
5926 }
5927
5928 switch (exit_reason) {
5929 case EXIT_REASON_VMON:
5930 /*
5931 * SDM 3: 24.11.5
5932 * The first 4 bytes of VMXON region contain the supported
5933 * VMCS revision identifier
5934 *
5935 * Note - IA32_VMX_BASIC[48] will never be 1
5936 * for the nested case;
5937 * which replaces physical address width with 32
5938 *
5939 */
bc39c4db 5940 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
3573e22c
BD		 5941 nested_vmx_failInvalid(vcpu);
5942 skip_emulated_instruction(vcpu);
5943 return 1;
5944 }
5945
5946 page = nested_get_page(vcpu, vmptr);
5947 if (page == NULL ||
5948 *(u32 *)kmap(page) != VMCS12_REVISION) {
5949 nested_vmx_failInvalid(vcpu);
5950 kunmap(page);
5951 skip_emulated_instruction(vcpu);
5952 return 1;
5953 }
5954 kunmap(page);
5955 vmx->nested.vmxon_ptr = vmptr;
5956 break;
4291b588 5957 case EXIT_REASON_VMCLEAR:
bc39c4db 5958 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 5959 nested_vmx_failValid(vcpu,
5960 VMXERR_VMCLEAR_INVALID_ADDRESS);
5961 skip_emulated_instruction(vcpu);
5962 return 1;
5963 }
5964
5965 if (vmptr == vmx->nested.vmxon_ptr) {
5966 nested_vmx_failValid(vcpu,
5967 VMXERR_VMCLEAR_VMXON_POINTER);
5968 skip_emulated_instruction(vcpu);
5969 return 1;
5970 }
5971 break;
5972 case EXIT_REASON_VMPTRLD:
bc39c4db 5973 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
4291b588
BD		 5974 nested_vmx_failValid(vcpu,
5975 VMXERR_VMPTRLD_INVALID_ADDRESS);
5976 skip_emulated_instruction(vcpu);
5977 return 1;
5978 }
3573e22c 5979
4291b588
BD		 5980 if (vmptr == vmx->nested.vmxon_ptr) {
5981 nested_vmx_failValid(vcpu,
5982 VMXERR_VMCLEAR_VMXON_POINTER);
5983 skip_emulated_instruction(vcpu);
5984 return 1;
5985 }
5986 break;
3573e22c
BD		 5987 default:
5988 return 1; /* shouldn't happen */
5989 }
5990
4291b588
BD		 5991 if (vmpointer)
5992 *vmpointer = vmptr;
3573e22c
BD		 5993 return 0;
5994}
5995
ec378aee
NHE		 5996/*
5997 * Emulate the VMXON instruction.
5998 * Currently, we just remember that VMX is active, and do not save or even
5999 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6000 * do not currently need to store anything in that guest-allocated memory
6001 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6002 * argument is different from the VMXON pointer (which the spec says they do).
6003 */
6004static int handle_vmon(struct kvm_vcpu *vcpu)
6005{
6006 struct kvm_segment cs;
6007 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 6008 struct vmcs *shadow_vmcs;
b3897a49
NHE		 6009 const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6010 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
ec378aee
NHE		 6011
6012 /* The Intel VMX Instruction Reference lists a bunch of bits that
6013 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6014 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6015 * Otherwise, we should fail with #UD. We test these now:
6016 */
6017 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6018 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6019 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6020 kvm_queue_exception(vcpu, UD_VECTOR);
6021 return 1;
6022 }
6023
6024 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6025 if (is_long_mode(vcpu) && !cs.l) {
6026 kvm_queue_exception(vcpu, UD_VECTOR);
6027 return 1;
6028 }
6029
6030 if (vmx_get_cpl(vcpu)) {
6031 kvm_inject_gp(vcpu, 0);
6032 return 1;
6033 }
3573e22c 6034
4291b588 6035 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
3573e22c
BD		 6036 return 1;
6037
145c28dd
AG		 6038 if (vmx->nested.vmxon) {
6039 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6040 skip_emulated_instruction(vcpu);
6041 return 1;
6042 }
b3897a49
NHE		 6043
6044 if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6045 != VMXON_NEEDED_FEATURES) {
6046 kvm_inject_gp(vcpu, 0);
6047 return 1;
6048 }
6049
8de48833
AG		 6050 if (enable_shadow_vmcs) {
6051 shadow_vmcs = alloc_vmcs();
6052 if (!shadow_vmcs)
6053 return -ENOMEM;
6054 /* mark vmcs as shadow */
6055 shadow_vmcs->revision_id |= (1u << 31);
6056 /* init shadow vmcs */
6057 vmcs_clear(shadow_vmcs);
6058 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6059 }
ec378aee 6060
ff2f6fe9
NHE		 6061 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6062 vmx->nested.vmcs02_num = 0;
6063
f4124500
JK		 6064 hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6065 HRTIMER_MODE_REL);
6066 vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6067
ec378aee
NHE		 6068 vmx->nested.vmxon = true;
6069
6070 skip_emulated_instruction(vcpu);
a25eb114 6071 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6072 return 1;
6073}
6074
6075/*
6076 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6077 * for running VMX instructions (except VMXON, whose prerequisites are
6078 * slightly different). It also specifies what exception to inject otherwise.
6079 */
6080static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6081{
6082 struct kvm_segment cs;
6083 struct vcpu_vmx *vmx = to_vmx(vcpu);
6084
6085 if (!vmx->nested.vmxon) {
6086 kvm_queue_exception(vcpu, UD_VECTOR);
6087 return 0;
6088 }
6089
6090 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6091 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6092 (is_long_mode(vcpu) && !cs.l)) {
6093 kvm_queue_exception(vcpu, UD_VECTOR);
6094 return 0;
6095 }
6096
6097 if (vmx_get_cpl(vcpu)) {
6098 kvm_inject_gp(vcpu, 0);
6099 return 0;
6100 }
6101
6102 return 1;
6103}
6104
e7953d7f
AG		 6105static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6106{
8a1b9dd0 6107 u32 exec_control;
012f83cb
AG		 6108 if (enable_shadow_vmcs) {
6109 if (vmx->nested.current_vmcs12 != NULL) {
6110 /* copy to memory all shadowed fields in case
6111 they were modified */
6112 copy_shadow_to_vmcs12(vmx);
6113 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 6114 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6115 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
6116 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6117 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 6118 }
6119 }
e7953d7f
AG		 6120 kunmap(vmx->nested.current_vmcs12_page);
6121 nested_release_page(vmx->nested.current_vmcs12_page);
6122}
6123
ec378aee
NHE		 6124/*
6125 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6126 * just stops using VMX.
6127 */
6128static void free_nested(struct vcpu_vmx *vmx)
6129{
6130 if (!vmx->nested.vmxon)
6131 return;
6132 vmx->nested.vmxon = false;
a9d30f33 6133 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 6134 nested_release_vmcs12(vmx);
a9d30f33
NHE		 6135 vmx->nested.current_vmptr = -1ull;
6136 vmx->nested.current_vmcs12 = NULL;
6137 }
e7953d7f
AG		 6138 if (enable_shadow_vmcs)
6139 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 6140 /* Unpin physical memory we referred to in current vmcs02 */
6141 if (vmx->nested.apic_access_page) {
6142 nested_release_page(vmx->nested.apic_access_page);
6143 vmx->nested.apic_access_page = 0;
6144 }
ff2f6fe9
NHE		 6145
6146 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 6147}
6148
6149/* Emulate the VMXOFF instruction */
6150static int handle_vmoff(struct kvm_vcpu *vcpu)
6151{
6152 if (!nested_vmx_check_permission(vcpu))
6153 return 1;
6154 free_nested(to_vmx(vcpu));
6155 skip_emulated_instruction(vcpu);
a25eb114 6156 nested_vmx_succeed(vcpu);
ec378aee
NHE		 6157 return 1;
6158}
6159
27d6c865
NHE		 6160/* Emulate the VMCLEAR instruction */
6161static int handle_vmclear(struct kvm_vcpu *vcpu)
6162{
6163 struct vcpu_vmx *vmx = to_vmx(vcpu);
27d6c865
NHE		 6164 gpa_t vmptr;
6165 struct vmcs12 *vmcs12;
6166 struct page *page;
27d6c865
NHE		 6167
6168 if (!nested_vmx_check_permission(vcpu))
6169 return 1;
6170
4291b588 6171 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
27d6c865 6172 return 1;
27d6c865
NHE		 6173
6174 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 6175 nested_release_vmcs12(vmx);
27d6c865
NHE		 6176 vmx->nested.current_vmptr = -1ull;
6177 vmx->nested.current_vmcs12 = NULL;
6178 }
6179
6180 page = nested_get_page(vcpu, vmptr);
6181 if (page == NULL) {
6182 /*
6183 * For accurate processor emulation, VMCLEAR beyond available
6184 * physical memory should do nothing at all. However, it is
6185 * possible that a nested vmx bug, not a guest hypervisor bug,
6186 * resulted in this case, so let's shut down before doing any
6187 * more damage:
6188 */
6189 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6190 return 1;
6191 }
6192 vmcs12 = kmap(page);
6193 vmcs12->launch_state = 0;
6194 kunmap(page);
6195 nested_release_page(page);
6196
6197 nested_free_vmcs02(vmx, vmptr);
6198
6199 skip_emulated_instruction(vcpu);
6200 nested_vmx_succeed(vcpu);
6201 return 1;
6202}
6203
cd232ad0
NHE		 6204static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6205
6206/* Emulate the VMLAUNCH instruction */
6207static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6208{
6209 return nested_vmx_run(vcpu, true);
6210}
6211
6212/* Emulate the VMRESUME instruction */
6213static int handle_vmresume(struct kvm_vcpu *vcpu)
6214{
6215
6216 return nested_vmx_run(vcpu, false);
6217}
6218
49f705c5
NHE		 6219enum vmcs_field_type {
6220 VMCS_FIELD_TYPE_U16 = 0,
6221 VMCS_FIELD_TYPE_U64 = 1,
6222 VMCS_FIELD_TYPE_U32 = 2,
6223 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6224};
6225
6226static inline int vmcs_field_type(unsigned long field)
6227{
6228 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
6229 return VMCS_FIELD_TYPE_U32;
6230 return (field >> 13) & 0x3 ;
6231}
6232
6233static inline int vmcs_field_readonly(unsigned long field)
6234{
6235 return (((field >> 10) & 0x3) == 1);
6236}
6237
6238/*
6239 * Read a vmcs12 field. Since these can have varying lengths and we return
6240 * one type, we chose the biggest type (u64) and zero-extend the return value
6241 * to that size. Note that the caller, handle_vmread, might need to use only
6242 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6243 * 64-bit fields are to be returned).
6244 */
6245static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
6246 unsigned long field, u64 *ret)
6247{
6248 short offset = vmcs_field_to_offset(field);
6249 char *p;
6250
6251 if (offset < 0)
6252 return 0;
6253
6254 p = ((char *)(get_vmcs12(vcpu))) + offset;
6255
6256 switch (vmcs_field_type(field)) {
6257 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6258 *ret = *((natural_width *)p);
6259 return 1;
6260 case VMCS_FIELD_TYPE_U16:
6261 *ret = *((u16 *)p);
6262 return 1;
6263 case VMCS_FIELD_TYPE_U32:
6264 *ret = *((u32 *)p);
6265 return 1;
6266 case VMCS_FIELD_TYPE_U64:
6267 *ret = *((u64 *)p);
6268 return 1;
6269 default:
6270 return 0; /* can never happen. */
6271 }
6272}
6273
20b97fea
AG		 6274
6275static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
6276 unsigned long field, u64 field_value){
6277 short offset = vmcs_field_to_offset(field);
6278 char *p = ((char *) get_vmcs12(vcpu)) + offset;
6279 if (offset < 0)
6280 return false;
6281
6282 switch (vmcs_field_type(field)) {
6283 case VMCS_FIELD_TYPE_U16:
6284 *(u16 *)p = field_value;
6285 return true;
6286 case VMCS_FIELD_TYPE_U32:
6287 *(u32 *)p = field_value;
6288 return true;
6289 case VMCS_FIELD_TYPE_U64:
6290 *(u64 *)p = field_value;
6291 return true;
6292 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6293 *(natural_width *)p = field_value;
6294 return true;
6295 default:
6296 return false; /* can never happen. */
6297 }
6298
6299}
6300
16f5b903
AG		 6301static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
6302{
6303 int i;
6304 unsigned long field;
6305 u64 field_value;
6306 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
c2bae893
MK		 6307 const unsigned long *fields = shadow_read_write_fields;
6308 const int num_fields = max_shadow_read_write_fields;
16f5b903
AG		 6309
6310 vmcs_load(shadow_vmcs);
6311
6312 for (i = 0; i < num_fields; i++) {
6313 field = fields[i];
6314 switch (vmcs_field_type(field)) {
6315 case VMCS_FIELD_TYPE_U16:
6316 field_value = vmcs_read16(field);
6317 break;
6318 case VMCS_FIELD_TYPE_U32:
6319 field_value = vmcs_read32(field);
6320 break;
6321 case VMCS_FIELD_TYPE_U64:
6322 field_value = vmcs_read64(field);
6323 break;
6324 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6325 field_value = vmcs_readl(field);
6326 break;
6327 }
6328 vmcs12_write_any(&vmx->vcpu, field, field_value);
6329 }
6330
6331 vmcs_clear(shadow_vmcs);
6332 vmcs_load(vmx->loaded_vmcs->vmcs);
6333}
6334
c3114420
AG		 6335static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
6336{
c2bae893
MK		 6337 const unsigned long *fields[] = {
6338 shadow_read_write_fields,
6339 shadow_read_only_fields
c3114420 6340 };
c2bae893 6341 const int max_fields[] = {
c3114420
AG		 6342 max_shadow_read_write_fields,
6343 max_shadow_read_only_fields
6344 };
6345 int i, q;
6346 unsigned long field;
6347 u64 field_value = 0;
6348 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6349
6350 vmcs_load(shadow_vmcs);
6351
c2bae893 6352 for (q = 0; q < ARRAY_SIZE(fields); q++) {
c3114420
AG		 6353 for (i = 0; i < max_fields[q]; i++) {
6354 field = fields[q][i];
6355 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6356
6357 switch (vmcs_field_type(field)) {
6358 case VMCS_FIELD_TYPE_U16:
6359 vmcs_write16(field, (u16)field_value);
6360 break;
6361 case VMCS_FIELD_TYPE_U32:
6362 vmcs_write32(field, (u32)field_value);
6363 break;
6364 case VMCS_FIELD_TYPE_U64:
6365 vmcs_write64(field, (u64)field_value);
6366 break;
6367 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6368 vmcs_writel(field, (long)field_value);
6369 break;
6370 }
6371 }
6372 }
6373
6374 vmcs_clear(shadow_vmcs);
6375 vmcs_load(vmx->loaded_vmcs->vmcs);
6376}
6377
49f705c5
NHE		 6378/*
6379 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6380 * used before) all generate the same failure when it is missing.
6381 */
6382static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6383{
6384 struct vcpu_vmx *vmx = to_vmx(vcpu);
6385 if (vmx->nested.current_vmptr == -1ull) {
6386 nested_vmx_failInvalid(vcpu);
6387 skip_emulated_instruction(vcpu);
6388 return 0;
6389 }
6390 return 1;
6391}
6392
6393static int handle_vmread(struct kvm_vcpu *vcpu)
6394{
6395 unsigned long field;
6396 u64 field_value;
6397 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6398 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6399 gva_t gva = 0;
6400
6401 if (!nested_vmx_check_permission(vcpu) ||
6402 !nested_vmx_check_vmcs12(vcpu))
6403 return 1;
6404
6405 /* Decode instruction info and find the field to read */
6406 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6407 /* Read the field, zero-extended to a u64 field_value */
6408 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6409 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6410 skip_emulated_instruction(vcpu);
6411 return 1;
6412 }
6413 /*
6414 * Now copy part of this value to register or memory, as requested.
6415 * Note that the number of bits actually copied is 32 or 64 depending
6416 * on the guest's mode (32 or 64 bit), not on the given field's length.
6417 */
6418 if (vmx_instruction_info & (1u << 10)) {
6419 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6420 field_value);
6421 } else {
6422 if (get_vmx_mem_address(vcpu, exit_qualification,
6423 vmx_instruction_info, &gva))
6424 return 1;
6425 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6426 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6427 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6428 }
6429
6430 nested_vmx_succeed(vcpu);
6431 skip_emulated_instruction(vcpu);
6432 return 1;
6433}
6434
6435
6436static int handle_vmwrite(struct kvm_vcpu *vcpu)
6437{
6438 unsigned long field;
6439 gva_t gva;
6440 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6441 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6442 /* The value to write might be 32 or 64 bits, depending on L1's long
6443 * mode, and eventually we need to write that into a field of several
6444 * possible lengths. The code below first zero-extends the value to 64
6445 * bit (field_value), and then copies only the approriate number of
6446 * bits into the vmcs12 field.
6447 */
6448 u64 field_value = 0;
6449 struct x86_exception e;
6450
6451 if (!nested_vmx_check_permission(vcpu) ||
6452 !nested_vmx_check_vmcs12(vcpu))
6453 return 1;
6454
6455 if (vmx_instruction_info & (1u << 10))
6456 field_value = kvm_register_read(vcpu,
6457 (((vmx_instruction_info) >> 3) & 0xf));
6458 else {
6459 if (get_vmx_mem_address(vcpu, exit_qualification,
6460 vmx_instruction_info, &gva))
6461 return 1;
6462 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6463 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6464 kvm_inject_page_fault(vcpu, &e);
6465 return 1;
6466 }
6467 }
6468
6469
6470 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6471 if (vmcs_field_readonly(field)) {
6472 nested_vmx_failValid(vcpu,
6473 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6474 skip_emulated_instruction(vcpu);
6475 return 1;
6476 }
6477
20b97fea 6478 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6479 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6480 skip_emulated_instruction(vcpu);
6481 return 1;
6482 }
6483
6484 nested_vmx_succeed(vcpu);
6485 skip_emulated_instruction(vcpu);
6486 return 1;
6487}
6488
63846663
NHE		 6489/* Emulate the VMPTRLD instruction */
6490static int handle_vmptrld(struct kvm_vcpu *vcpu)
6491{
6492 struct vcpu_vmx *vmx = to_vmx(vcpu);
63846663 6493 gpa_t vmptr;
8a1b9dd0 6494 u32 exec_control;
63846663
NHE		 6495
6496 if (!nested_vmx_check_permission(vcpu))
6497 return 1;
6498
4291b588 6499 if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
63846663 6500 return 1;
63846663
NHE		 6501
6502 if (vmx->nested.current_vmptr != vmptr) {
6503 struct vmcs12 *new_vmcs12;
6504 struct page *page;
6505 page = nested_get_page(vcpu, vmptr);
6506 if (page == NULL) {
6507 nested_vmx_failInvalid(vcpu);
6508 skip_emulated_instruction(vcpu);
6509 return 1;
6510 }
6511 new_vmcs12 = kmap(page);
6512 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6513 kunmap(page);
6514 nested_release_page_clean(page);
6515 nested_vmx_failValid(vcpu,
6516 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6517 skip_emulated_instruction(vcpu);
6518 return 1;
6519 }
e7953d7f
AG		 6520 if (vmx->nested.current_vmptr != -1ull)
6521 nested_release_vmcs12(vmx);
63846663
NHE		 6522
6523 vmx->nested.current_vmptr = vmptr;
6524 vmx->nested.current_vmcs12 = new_vmcs12;
6525 vmx->nested.current_vmcs12_page = page;
012f83cb 6526 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6527 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6528 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6529 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6530 vmcs_write64(VMCS_LINK_POINTER,
6531 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6532 vmx->nested.sync_shadow_vmcs = true;
6533 }
63846663
NHE		 6534 }
6535
6536 nested_vmx_succeed(vcpu);
6537 skip_emulated_instruction(vcpu);
6538 return 1;
6539}
6540
6a4d7550
NHE		 6541/* Emulate the VMPTRST instruction */
6542static int handle_vmptrst(struct kvm_vcpu *vcpu)
6543{
6544 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6545 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6546 gva_t vmcs_gva;
6547 struct x86_exception e;
6548
6549 if (!nested_vmx_check_permission(vcpu))
6550 return 1;
6551
6552 if (get_vmx_mem_address(vcpu, exit_qualification,
6553 vmx_instruction_info, &vmcs_gva))
6554 return 1;
6555 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6556 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6557 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6558 sizeof(u64), &e)) {
6559 kvm_inject_page_fault(vcpu, &e);
6560 return 1;
6561 }
6562 nested_vmx_succeed(vcpu);
6563 skip_emulated_instruction(vcpu);
6564 return 1;
6565}
6566
bfd0a56b
NHE		 6567/* Emulate the INVEPT instruction */
6568static int handle_invept(struct kvm_vcpu *vcpu)
6569{
6570 u32 vmx_instruction_info, types;
6571 unsigned long type;
6572 gva_t gva;
6573 struct x86_exception e;
6574 struct {
6575 u64 eptp, gpa;
6576 } operand;
bfd0a56b
NHE		 6577
6578 if (!(nested_vmx_secondary_ctls_high & SECONDARY_EXEC_ENABLE_EPT) ||
6579 !(nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
6580 kvm_queue_exception(vcpu, UD_VECTOR);
6581 return 1;
6582 }
6583
6584 if (!nested_vmx_check_permission(vcpu))
6585 return 1;
6586
6587 if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
6588 kvm_queue_exception(vcpu, UD_VECTOR);
6589 return 1;
6590 }
6591
6592 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6593 type = kvm_register_read(vcpu, (vmx_instruction_info >> 28) & 0xf);
6594
6595 types = (nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
6596
6597 if (!(types & (1UL << type))) {
6598 nested_vmx_failValid(vcpu,
6599 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
6600 return 1;
6601 }
6602
6603 /* According to the Intel VMX instruction reference, the memory
6604 * operand is read even if it isn't needed (e.g., for type==global)
6605 */
6606 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6607 vmx_instruction_info, &gva))
6608 return 1;
6609 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
6610 sizeof(operand), &e)) {
6611 kvm_inject_page_fault(vcpu, &e);
6612 return 1;
6613 }
6614
6615 switch (type) {
bfd0a56b
NHE		 6616 case VMX_EPT_EXTENT_GLOBAL:
6617 kvm_mmu_sync_roots(vcpu);
6618 kvm_mmu_flush_tlb(vcpu);
6619 nested_vmx_succeed(vcpu);
6620 break;
6621 default:
4b855078 6622 /* Trap single context invalidation invept calls */
bfd0a56b
NHE		 6623 BUG_ON(1);
6624 break;
6625 }
6626
6627 skip_emulated_instruction(vcpu);
6628 return 1;
6629}
6630
6aa8b732
AK		 6631/*
6632 * The exit handlers return 1 if the exit was handled fully and guest execution
6633 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6634 * to be done to userspace and return 0.
6635 */
772e0318 6636static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6637 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6638 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6639 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6640 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6641 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6642 [EXIT_REASON_CR_ACCESS] = handle_cr,
6643 [EXIT_REASON_DR_ACCESS] = handle_dr,
6644 [EXIT_REASON_CPUID] = handle_cpuid,
6645 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6646 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6647 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6648 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6649 [EXIT_REASON_INVD] = handle_invd,
a7052897 6650 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6651 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6652 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6653 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6654 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6655 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6656 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6657 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6658 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6659 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6660 [EXIT_REASON_VMOFF] = handle_vmoff,
6661 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6662 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6663 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6664 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6665 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6666 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6667 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6668 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6669 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6670 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6671 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6672 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
87c00572
GS		 6673 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
6674 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
bfd0a56b 6675 [EXIT_REASON_INVEPT] = handle_invept,
6aa8b732
AK		 6676};
6677
6678static const int kvm_vmx_max_exit_handlers =
50a3485c 6679 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6680
908a7bdd
JK		 6681static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6682 struct vmcs12 *vmcs12)
6683{
6684 unsigned long exit_qualification;
6685 gpa_t bitmap, last_bitmap;
6686 unsigned int port;
6687 int size;
6688 u8 b;
6689
908a7bdd 6690 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
2f0a6397 6691 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
908a7bdd
JK		 6692
6693 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6694
6695 port = exit_qualification >> 16;
6696 size = (exit_qualification & 7) + 1;
6697
6698 last_bitmap = (gpa_t)-1;
6699 b = -1;
6700
6701 while (size > 0) {
6702 if (port < 0x8000)
6703 bitmap = vmcs12->io_bitmap_a;
6704 else if (port < 0x10000)
6705 bitmap = vmcs12->io_bitmap_b;
6706 else
6707 return 1;
6708 bitmap += (port & 0x7fff) / 8;
6709
6710 if (last_bitmap != bitmap)
6711 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6712 return 1;
6713 if (b & (1 << (port & 7)))
6714 return 1;
6715
6716 port++;
6717 size--;
6718 last_bitmap = bitmap;
6719 }
6720
6721 return 0;
6722}
6723
644d711a
NHE		 6724/*
6725 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6726 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6727 * disinterest in the current event (read or write a specific MSR) by using an
6728 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6729 */
6730static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6731 struct vmcs12 *vmcs12, u32 exit_reason)
6732{
6733 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6734 gpa_t bitmap;
6735
cbd29cb6 6736 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6737 return 1;
6738
6739 /*
6740 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6741 * for the four combinations of read/write and low/high MSR numbers.
6742 * First we need to figure out which of the four to use:
6743 */
6744 bitmap = vmcs12->msr_bitmap;
6745 if (exit_reason == EXIT_REASON_MSR_WRITE)
6746 bitmap += 2048;
6747 if (msr_index >= 0xc0000000) {
6748 msr_index -= 0xc0000000;
6749 bitmap += 1024;
6750 }
6751
6752 /* Then read the msr_index'th bit from this bitmap: */
6753 if (msr_index < 1024*8) {
6754 unsigned char b;
bd31a7f5
JK		 6755 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6756 return 1;
644d711a
NHE		 6757 return 1 & (b >> (msr_index & 7));
6758 } else
6759 return 1; /* let L1 handle the wrong parameter */
6760}
6761
6762/*
6763 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6764 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6765 * intercept (via guest_host_mask etc.) the current event.
6766 */
6767static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6768 struct vmcs12 *vmcs12)
6769{
6770 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6771 int cr = exit_qualification & 15;
6772 int reg = (exit_qualification >> 8) & 15;
6773 unsigned long val = kvm_register_read(vcpu, reg);
6774
6775 switch ((exit_qualification >> 4) & 3) {
6776 case 0: /* mov to cr */
6777 switch (cr) {
6778 case 0:
6779 if (vmcs12->cr0_guest_host_mask &
6780 (val ^ vmcs12->cr0_read_shadow))
6781 return 1;
6782 break;
6783 case 3:
6784 if ((vmcs12->cr3_target_count >= 1 &&
6785 vmcs12->cr3_target_value0 == val) ||
6786 (vmcs12->cr3_target_count >= 2 &&
6787 vmcs12->cr3_target_value1 == val) ||
6788 (vmcs12->cr3_target_count >= 3 &&
6789 vmcs12->cr3_target_value2 == val) ||
6790 (vmcs12->cr3_target_count >= 4 &&
6791 vmcs12->cr3_target_value3 == val))
6792 return 0;
6793 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6794 return 1;
6795 break;
6796 case 4:
6797 if (vmcs12->cr4_guest_host_mask &
6798 (vmcs12->cr4_read_shadow ^ val))
6799 return 1;
6800 break;
6801 case 8:
6802 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6803 return 1;
6804 break;
6805 }
6806 break;
6807 case 2: /* clts */
6808 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6809 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6810 return 1;
6811 break;
6812 case 1: /* mov from cr */
6813 switch (cr) {
6814 case 3:
6815 if (vmcs12->cpu_based_vm_exec_control &
6816 CPU_BASED_CR3_STORE_EXITING)
6817 return 1;
6818 break;
6819 case 8:
6820 if (vmcs12->cpu_based_vm_exec_control &
6821 CPU_BASED_CR8_STORE_EXITING)
6822 return 1;
6823 break;
6824 }
6825 break;
6826 case 3: /* lmsw */
6827 /*
6828 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6829 * cr0. Other attempted changes are ignored, with no exit.
6830 */
6831 if (vmcs12->cr0_guest_host_mask & 0xe &
6832 (val ^ vmcs12->cr0_read_shadow))
6833 return 1;
6834 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6835 !(vmcs12->cr0_read_shadow & 0x1) &&
6836 (val & 0x1))
6837 return 1;
6838 break;
6839 }
6840 return 0;
6841}
6842
6843/*
6844 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6845 * should handle it ourselves in L0 (and then continue L2). Only call this
6846 * when in is_guest_mode (L2).
6847 */
6848static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6849{
644d711a
NHE		 6850 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6851 struct vcpu_vmx *vmx = to_vmx(vcpu);
6852 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6853 u32 exit_reason = vmx->exit_reason;
644d711a 6854
542060ea
JK		 6855 trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
6856 vmcs_readl(EXIT_QUALIFICATION),
6857 vmx->idt_vectoring_info,
6858 intr_info,
6859 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
6860 KVM_ISA_VMX);
6861
644d711a
NHE		 6862 if (vmx->nested.nested_run_pending)
6863 return 0;
6864
6865 if (unlikely(vmx->fail)) {
bd80158a
JK		 6866 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6867 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6868 return 1;
6869 }
6870
6871 switch (exit_reason) {
6872 case EXIT_REASON_EXCEPTION_NMI:
6873 if (!is_exception(intr_info))
6874 return 0;
6875 else if (is_page_fault(intr_info))
6876 return enable_ept;
e504c909 6877 else if (is_no_device(intr_info) &&
ccf9844e 6878 !(vmcs12->guest_cr0 & X86_CR0_TS))
e504c909 6879 return 0;
644d711a
NHE		 6880 return vmcs12->exception_bitmap &
6881 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6882 case EXIT_REASON_EXTERNAL_INTERRUPT:
6883 return 0;
6884 case EXIT_REASON_TRIPLE_FAULT:
6885 return 1;
6886 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6887 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6888 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6889 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6890 case EXIT_REASON_TASK_SWITCH:
6891 return 1;
6892 case EXIT_REASON_CPUID:
6893 return 1;
6894 case EXIT_REASON_HLT:
6895 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6896 case EXIT_REASON_INVD:
6897 return 1;
6898 case EXIT_REASON_INVLPG:
6899 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6900 case EXIT_REASON_RDPMC:
6901 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6902 case EXIT_REASON_RDTSC:
6903 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6904 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6905 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6906 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6907 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6908 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
bfd0a56b 6909 case EXIT_REASON_INVEPT:
644d711a
NHE		 6910 /*
6911 * VMX instructions trap unconditionally. This allows L1 to
6912 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6913 */
6914 return 1;
6915 case EXIT_REASON_CR_ACCESS:
6916 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6917 case EXIT_REASON_DR_ACCESS:
6918 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6919 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6920 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6921 case EXIT_REASON_MSR_READ:
6922 case EXIT_REASON_MSR_WRITE:
6923 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6924 case EXIT_REASON_INVALID_STATE:
6925 return 1;
6926 case EXIT_REASON_MWAIT_INSTRUCTION:
6927 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6928 case EXIT_REASON_MONITOR_INSTRUCTION:
6929 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6930 case EXIT_REASON_PAUSE_INSTRUCTION:
6931 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6932 nested_cpu_has2(vmcs12,
6933 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6934 case EXIT_REASON_MCE_DURING_VMENTRY:
6935 return 0;
6936 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6937 return 1;
6938 case EXIT_REASON_APIC_ACCESS:
6939 return nested_cpu_has2(vmcs12,
6940 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6941 case EXIT_REASON_EPT_VIOLATION:
2b1be677
NHE		 6942 /*
6943 * L0 always deals with the EPT violation. If nested EPT is
6944 * used, and the nested mmu code discovers that the address is
6945 * missing in the guest EPT table (EPT12), the EPT violation
6946 * will be injected with nested_ept_inject_page_fault()
6947 */
6948 return 0;
644d711a 6949 case EXIT_REASON_EPT_MISCONFIG:
2b1be677
NHE		 6950 /*
6951 * L2 never uses directly L1's EPT, but rather L0's own EPT
6952 * table (shadow on EPT) or a merged EPT table that L0 built
6953 * (EPT on EPT). So any problems with the structure of the
6954 * table is L0's fault.
6955 */
644d711a
NHE		 6956 return 0;
6957 case EXIT_REASON_WBINVD:
6958 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6959 case EXIT_REASON_XSETBV:
6960 return 1;
6961 default:
6962 return 1;
6963 }
6964}
6965
586f9607
AK		 6966static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6967{
6968 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6969 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6970}
6971
6aa8b732
AK		 6972/*
6973 * The guest has exited. See if we can fix it or if we need userspace
6974 * assistance.
6975 */
851ba692 6976static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6977{
29bd8a78 6978 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6979 u32 exit_reason = vmx->exit_reason;
1155f76a 6980 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6981
80ced186 6982 /* If guest state is invalid, start emulating */
14168786 6983 if (vmx->emulation_required)
80ced186 6984 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6985
644d711a 6986 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
533558bc
JK		 6987 nested_vmx_vmexit(vcpu, exit_reason,
6988 vmcs_read32(VM_EXIT_INTR_INFO),
6989 vmcs_readl(EXIT_QUALIFICATION));
644d711a
NHE		 6990 return 1;
6991 }
6992
5120702e
MG		 6993 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6994 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6995 vcpu->run->fail_entry.hardware_entry_failure_reason
6996 = exit_reason;
6997 return 0;
6998 }
6999
29bd8a78 7000 if (unlikely(vmx->fail)) {
851ba692
AK		 7001 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
7002 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 7003 = vmcs_read32(VM_INSTRUCTION_ERROR);
7004 return 0;
7005 }
6aa8b732 7006
b9bf6882
XG		 7007 /*
7008 * Note:
7009 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7010 * delivery event since it indicates guest is accessing MMIO.
7011 * The vm-exit can be triggered again after return to guest that
7012 * will cause infinite loop.
7013 */
d77c26fc 7014 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 7015 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 7016 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 7017 exit_reason != EXIT_REASON_TASK_SWITCH)) {
7018 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
7019 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
7020 vcpu->run->internal.ndata = 2;
7021 vcpu->run->internal.data[0] = vectoring_info;
7022 vcpu->run->internal.data[1] = exit_reason;
7023 return 0;
7024 }
3b86cd99 7025
644d711a
NHE		 7026 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
7027 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
f5c4368f 7028 get_vmcs12(vcpu))))) {
c4282df9 7029 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 7030 vmx->soft_vnmi_blocked = 0;
3b86cd99 7031 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 7032 vcpu->arch.nmi_pending) {
3b86cd99
JK		 7033 /*
7034 * This CPU don't support us in finding the end of an
7035 * NMI-blocked window if the guest runs with IRQs
7036 * disabled. So we pull the trigger after 1 s of
7037 * futile waiting, but inform the user about this.
7038 */
7039 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
7040 "state on VCPU %d after 1 s timeout\n",
7041 __func__, vcpu->vcpu_id);
7042 vmx->soft_vnmi_blocked = 0;
3b86cd99 7043 }
3b86cd99
JK		 7044 }
7045
6aa8b732
AK		 7046 if (exit_reason < kvm_vmx_max_exit_handlers
7047 && kvm_vmx_exit_handlers[exit_reason])
851ba692 7048 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 7049 else {
851ba692
AK		 7050 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
7051 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 7052 }
7053 return 0;
7054}
7055
95ba8273 7056static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 7057{
95ba8273 7058 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 7059 vmcs_write32(TPR_THRESHOLD, 0);
7060 return;
7061 }
7062
95ba8273 7063 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 7064}
7065
8d14695f
YZ		 7066static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
7067{
7068 u32 sec_exec_control;
7069
7070 /*
7071 * There is not point to enable virtualize x2apic without enable
7072 * apicv
7073 */
c7c9c56c
YZ		 7074 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7075 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 7076 return;
7077
7078 if (!vm_need_tpr_shadow(vcpu->kvm))
7079 return;
7080
7081 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7082
7083 if (set) {
7084 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7085 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7086 } else {
7087 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
7088 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7089 }
7090 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
7091
7092 vmx_set_msr_bitmap(vcpu);
7093}
7094
c7c9c56c
YZ		 7095static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
7096{
7097 u16 status;
7098 u8 old;
7099
7100 if (!vmx_vm_has_apicv(kvm))
7101 return;
7102
7103 if (isr == -1)
7104 isr = 0;
7105
7106 status = vmcs_read16(GUEST_INTR_STATUS);
7107 old = status >> 8;
7108 if (isr != old) {
7109 status &= 0xff;
7110 status |= isr << 8;
7111 vmcs_write16(GUEST_INTR_STATUS, status);
7112 }
7113}
7114
7115static void vmx_set_rvi(int vector)
7116{
7117 u16 status;
7118 u8 old;
7119
7120 status = vmcs_read16(GUEST_INTR_STATUS);
7121 old = (u8)status & 0xff;
7122 if ((u8)vector != old) {
7123 status &= ~0xff;
7124 status |= (u8)vector;
7125 vmcs_write16(GUEST_INTR_STATUS, status);
7126 }
7127}
7128
7129static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
7130{
7131 if (max_irr == -1)
7132 return;
7133
7134 vmx_set_rvi(max_irr);
7135}
7136
7137static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
7138{
3d81bc7e
YZ		 7139 if (!vmx_vm_has_apicv(vcpu->kvm))
7140 return;
7141
c7c9c56c
YZ		 7142 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
7143 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
7144 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
7145 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
7146}
7147
51aa01d1 7148static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 7149{
00eba012
AK		 7150 u32 exit_intr_info;
7151
7152 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
7153 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
7154 return;
7155
c5ca8e57 7156 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 7157 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 7158
7159 /* Handle machine checks before interrupts are enabled */
00eba012 7160 if (is_machine_check(exit_intr_info))
a0861c02
AK		 7161 kvm_machine_check();
7162
20f65983 7163 /* We need to handle NMIs before interrupts are enabled */
00eba012 7164 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 7165 (exit_intr_info & INTR_INFO_VALID_MASK)) {
7166 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 7167 asm("int $2");
ff9d07a0
ZY		 7168 kvm_after_handle_nmi(&vmx->vcpu);
7169 }
51aa01d1 7170}
20f65983 7171
a547c6db
YZ		 7172static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
7173{
7174 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7175
7176 /*
7177 * If external interrupt exists, IF bit is set in rflags/eflags on the
7178 * interrupt stack frame, and interrupt will be enabled on a return
7179 * from interrupt handler.
7180 */
7181 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
7182 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
7183 unsigned int vector;
7184 unsigned long entry;
7185 gate_desc *desc;
7186 struct vcpu_vmx *vmx = to_vmx(vcpu);
7187#ifdef CONFIG_X86_64
7188 unsigned long tmp;
7189#endif
7190
7191 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7192 desc = (gate_desc *)vmx->host_idt_base + vector;
7193 entry = gate_offset(*desc);
7194 asm volatile(
7195#ifdef CONFIG_X86_64
7196 "mov %%" _ASM_SP ", %[sp]\n\t"
7197 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
7198 "push $%c[ss]\n\t"
7199 "push %[sp]\n\t"
7200#endif
7201 "pushf\n\t"
7202 "orl $0x200, (%%" _ASM_SP ")\n\t"
7203 __ASM_SIZE(push) " $%c[cs]\n\t"
7204 "call *%[entry]\n\t"
7205 :
7206#ifdef CONFIG_X86_64
7207 [sp]"=&r"(tmp)
7208#endif
7209 :
7210 [entry]"r"(entry),
7211 [ss]"i"(__KERNEL_DS),
7212 [cs]"i"(__KERNEL_CS)
7213 );
7214 } else
7215 local_irq_enable();
7216}
7217
da8999d3
LJ		 7218static bool vmx_mpx_supported(void)
7219{
7220 return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
7221 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
7222}
7223
51aa01d1
AK		 7224static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
7225{
c5ca8e57 7226 u32 exit_intr_info;
51aa01d1
AK		 7227 bool unblock_nmi;
7228 u8 vector;
7229 bool idtv_info_valid;
7230
7231 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 7232
cf393f75 7233 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 7234 if (vmx->nmi_known_unmasked)
7235 return;
c5ca8e57
AK		 7236 /*
7237 * Can't use vmx->exit_intr_info since we're not sure what
7238 * the exit reason is.
7239 */
7240 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 7241 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
7242 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
7243 /*
7b4a25cb 7244 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 7245 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7246 * a guest IRET fault.
7b4a25cb
GN		 7247 * SDM 3: 23.2.2 (September 2008)
7248 * Bit 12 is undefined in any of the following cases:
7249 * If the VM exit sets the valid bit in the IDT-vectoring
7250 * information field.
7251 * If the VM exit is due to a double fault.
cf393f75 7252 */
7b4a25cb
GN		 7253 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
7254 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 7255 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7256 GUEST_INTR_STATE_NMI);
9d58b931
AK		 7257 else
7258 vmx->nmi_known_unmasked =
7259 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
7260 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 7261 } else if (unlikely(vmx->soft_vnmi_blocked))
7262 vmx->vnmi_blocked_time +=
7263 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 7264}
7265
3ab66e8a 7266static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 7267 u32 idt_vectoring_info,
7268 int instr_len_field,
7269 int error_code_field)
51aa01d1 7270{
51aa01d1
AK		 7271 u8 vector;
7272 int type;
7273 bool idtv_info_valid;
7274
7275 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 7276
3ab66e8a
JK		 7277 vcpu->arch.nmi_injected = false;
7278 kvm_clear_exception_queue(vcpu);
7279 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 7280
7281 if (!idtv_info_valid)
7282 return;
7283
3ab66e8a 7284 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 7285
668f612f
AK		 7286 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
7287 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 7288
64a7ec06 7289 switch (type) {
37b96e98 7290 case INTR_TYPE_NMI_INTR:
3ab66e8a 7291 vcpu->arch.nmi_injected = true;
668f612f 7292 /*
7b4a25cb 7293 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 7294 * Clear bit "block by NMI" before VM entry if a NMI
7295 * delivery faulted.
668f612f 7296 */
3ab66e8a 7297 vmx_set_nmi_mask(vcpu, false);
37b96e98 7298 break;
37b96e98 7299 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 7300 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 7301 /* fall through */
7302 case INTR_TYPE_HARD_EXCEPTION:
35920a35 7303 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 7304 u32 err = vmcs_read32(error_code_field);
851eb667 7305 kvm_requeue_exception_e(vcpu, vector, err);
35920a35 7306 } else
851eb667 7307 kvm_requeue_exception(vcpu, vector);
37b96e98 7308 break;
66fd3f7f 7309 case INTR_TYPE_SOFT_INTR:
3ab66e8a 7310 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 7311 /* fall through */
37b96e98 7312 case INTR_TYPE_EXT_INTR:
3ab66e8a 7313 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 7314 break;
7315 default:
7316 break;
f7d9238f 7317 }
cf393f75
AK		 7318}
7319
83422e17
AK		 7320static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
7321{
3ab66e8a 7322 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 7323 VM_EXIT_INSTRUCTION_LEN,
7324 IDT_VECTORING_ERROR_CODE);
7325}
7326
b463a6f7
AK		 7327static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
7328{
3ab66e8a 7329 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 7330 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
7331 VM_ENTRY_INSTRUCTION_LEN,
7332 VM_ENTRY_EXCEPTION_ERROR_CODE);
7333
7334 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
7335}
7336
d7cd9796
GN		 7337static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
7338{
7339 int i, nr_msrs;
7340 struct perf_guest_switch_msr *msrs;
7341
7342 msrs = perf_guest_get_msrs(&nr_msrs);
7343
7344 if (!msrs)
7345 return;
7346
7347 for (i = 0; i < nr_msrs; i++)
7348 if (msrs[i].host == msrs[i].guest)
7349 clear_atomic_switch_msr(vmx, msrs[i].msr);
7350 else
7351 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
7352 msrs[i].host);
7353}
7354
a3b5ba49 7355static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 7356{
a2fa3e9f 7357 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 7358 unsigned long debugctlmsr;
104f226b
AK		 7359
7360 /* Record the guest's net vcpu time for enforced NMI injections. */
7361 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
7362 vmx->entry_time = ktime_get();
7363
7364 /* Don't enter VMX if guest state is invalid, let the exit handler
7365 start emulation until we arrive back to a valid state */
14168786 7366 if (vmx->emulation_required)
104f226b
AK		 7367 return;
7368
012f83cb
AG		 7369 if (vmx->nested.sync_shadow_vmcs) {
7370 copy_vmcs12_to_shadow(vmx);
7371 vmx->nested.sync_shadow_vmcs = false;
7372 }
7373
104f226b
AK		 7374 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
7375 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
7376 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
7377 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
7378
7379 /* When single-stepping over STI and MOV SS, we must clear the
7380 * corresponding interruptibility bits in the guest state. Otherwise
7381 * vmentry fails as it then expects bit 14 (BS) in pending debug
7382 * exceptions being set, but that's not correct for the guest debugging
7383 * case. */
7384 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
7385 vmx_set_interrupt_shadow(vcpu, 0);
7386
d7cd9796 7387 atomic_switch_perf_msrs(vmx);
2a7921b7 7388 debugctlmsr = get_debugctlmsr();
d7cd9796 7389
d462b819 7390 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 7391 asm(
6aa8b732 7392 /* Store host registers */
b188c81f
AK		 7393 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
7394 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
7395 "push %%" _ASM_CX " \n\t"
7396 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 7397 "je 1f \n\t"
b188c81f 7398 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 7399 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 7400 "1: \n\t"
d3edefc0 7401 /* Reload cr2 if changed */
b188c81f
AK		 7402 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
7403 "mov %%cr2, %%" _ASM_DX " \n\t"
7404 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 7405 "je 2f \n\t"
b188c81f 7406 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 7407 "2: \n\t"
6aa8b732 7408 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7409 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7410 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7411 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7412 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7413 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7414 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7415 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7416 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7417#ifdef CONFIG_X86_64
e08aa78a
AK		 7418 "mov %c[r8](%0), %%r8 \n\t"
7419 "mov %c[r9](%0), %%r9 \n\t"
7420 "mov %c[r10](%0), %%r10 \n\t"
7421 "mov %c[r11](%0), %%r11 \n\t"
7422 "mov %c[r12](%0), %%r12 \n\t"
7423 "mov %c[r13](%0), %%r13 \n\t"
7424 "mov %c[r14](%0), %%r14 \n\t"
7425 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7426#endif
b188c81f 7427 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7428
6aa8b732 7429 /* Enter guest mode */
83287ea4 7430 "jne 1f \n\t"
4ecac3fd 7431 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7432 "jmp 2f \n\t"
7433 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7434 "2: "
6aa8b732 7435 /* Save guest registers, load host registers, keep flags */
b188c81f 7436 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7437 "pop %0 \n\t"
b188c81f
AK		 7438 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7439 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7440 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7441 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7442 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7443 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7444 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7445#ifdef CONFIG_X86_64
e08aa78a
AK		 7446 "mov %%r8, %c[r8](%0) \n\t"
7447 "mov %%r9, %c[r9](%0) \n\t"
7448 "mov %%r10, %c[r10](%0) \n\t"
7449 "mov %%r11, %c[r11](%0) \n\t"
7450 "mov %%r12, %c[r12](%0) \n\t"
7451 "mov %%r13, %c[r13](%0) \n\t"
7452 "mov %%r14, %c[r14](%0) \n\t"
7453 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7454#endif
b188c81f
AK		 7455 "mov %%cr2, %%" _ASM_AX " \n\t"
7456 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7457
b188c81f 7458 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7459 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7460 ".pushsection .rodata \n\t"
7461 ".global vmx_return \n\t"
7462 "vmx_return: " _ASM_PTR " 2b \n\t"
7463 ".popsection"
e08aa78a 7464 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7465 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7466 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7467 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7468 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7469 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7470 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7471 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7472 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7473 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7474 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7475#ifdef CONFIG_X86_64
ad312c7c
ZX		 7476 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7477 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7478 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7479 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7480 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7481 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7482 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7483 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7484#endif
40712fae
AK		 7485 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7486 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7487 : "cc", "memory"
7488#ifdef CONFIG_X86_64
b188c81f 7489 , "rax", "rbx", "rdi", "rsi"
c2036300 7490 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7491#else
7492 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7493#endif
7494 );
6aa8b732 7495
2a7921b7
GN		 7496 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7497 if (debugctlmsr)
7498 update_debugctlmsr(debugctlmsr);
7499
aa67f609
AK		 7500#ifndef CONFIG_X86_64
7501 /*
7502 * The sysexit path does not restore ds/es, so we must set them to
7503 * a reasonable value ourselves.
7504 *
7505 * We can't defer this to vmx_load_host_state() since that function
7506 * may be executed in interrupt context, which saves and restore segments
7507 * around it, nullifying its effect.
7508 */
7509 loadsegment(ds, __USER_DS);
7510 loadsegment(es, __USER_DS);
7511#endif
7512
6de4f3ad 7513 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7514 | (1 << VCPU_EXREG_RFLAGS)
aff48baa 7515 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7516 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7517 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7518 vcpu->arch.regs_dirty = 0;
7519
1155f76a
AK		 7520 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7521
d462b819 7522 vmx->loaded_vmcs->launched = 1;
1b6269db 7523
51aa01d1 7524 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7525 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1 7526
e0b890d3
GN		 7527 /*
7528 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7529 * we did not inject a still-pending event to L1 now because of
7530 * nested_run_pending, we need to re-enable this bit.
7531 */
7532 if (vmx->nested.nested_run_pending)
7533 kvm_make_request(KVM_REQ_EVENT, vcpu);
7534
7535 vmx->nested.nested_run_pending = 0;
7536
51aa01d1
AK		 7537 vmx_complete_atomic_exit(vmx);
7538 vmx_recover_nmi_blocking(vmx);
cf393f75 7539 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7540}
7541
6aa8b732
AK		 7542static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7543{
fb3f0f51
RR		 7544 struct vcpu_vmx *vmx = to_vmx(vcpu);
7545
cdbecfc3 7546 free_vpid(vmx);
d462b819 7547 free_loaded_vmcs(vmx->loaded_vmcs);
26a865f4 7548 free_nested(vmx);
fb3f0f51
RR		 7549 kfree(vmx->guest_msrs);
7550 kvm_vcpu_uninit(vcpu);
a4770347 7551 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7552}
7553
fb3f0f51 7554static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7555{
fb3f0f51 7556 int err;
c16f862d 7557 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7558 int cpu;
6aa8b732 7559
a2fa3e9f 7560 if (!vmx)
fb3f0f51
RR		 7561 return ERR_PTR(-ENOMEM);
7562
2384d2b3
SY		 7563 allocate_vpid(vmx);
7564
fb3f0f51
RR		 7565 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7566 if (err)
7567 goto free_vcpu;
965b58a5 7568
a2fa3e9f 7569 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7570 err = -ENOMEM;
fb3f0f51 7571 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7572 goto uninit_vcpu;
7573 }
965b58a5 7574
d462b819
NHE		 7575 vmx->loaded_vmcs = &vmx->vmcs01;
7576 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7577 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7578 goto free_msrs;
d462b819
NHE		 7579 if (!vmm_exclusive)
7580 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7581 loaded_vmcs_init(vmx->loaded_vmcs);
7582 if (!vmm_exclusive)
7583 kvm_cpu_vmxoff();
a2fa3e9f 7584
15ad7146
AK		 7585 cpu = get_cpu();
7586 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7587 vmx->vcpu.cpu = cpu;
8b9cf98c 7588 err = vmx_vcpu_setup(vmx);
fb3f0f51 7589 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7590 put_cpu();
fb3f0f51
RR		 7591 if (err)
7592 goto free_vmcs;
a63cb560 7593 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7594 err = alloc_apic_access_page(kvm);
7595 if (err)
5e4a0b3c 7596 goto free_vmcs;
a63cb560 7597 }
fb3f0f51 7598
b927a3ce
SY		 7599 if (enable_ept) {
7600 if (!kvm->arch.ept_identity_map_addr)
7601 kvm->arch.ept_identity_map_addr =
7602 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7603 err = -ENOMEM;
b7ebfb05
SY		 7604 if (alloc_identity_pagetable(kvm) != 0)
7605 goto free_vmcs;
93ea5388
GN		 7606 if (!init_rmode_identity_map(kvm))
7607 goto free_vmcs;
b927a3ce 7608 }
b7ebfb05 7609
a9d30f33
NHE		 7610 vmx->nested.current_vmptr = -1ull;
7611 vmx->nested.current_vmcs12 = NULL;
7612
fb3f0f51
RR		 7613 return &vmx->vcpu;
7614
7615free_vmcs:
5f3fbc34 7616 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7617free_msrs:
fb3f0f51
RR		 7618 kfree(vmx->guest_msrs);
7619uninit_vcpu:
7620 kvm_vcpu_uninit(&vmx->vcpu);
7621free_vcpu:
cdbecfc3 7622 free_vpid(vmx);
a4770347 7623 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7624 return ERR_PTR(err);
6aa8b732
AK		 7625}
7626
002c7f7c
YS		 7627static void __init vmx_check_processor_compat(void *rtn)
7628{
7629 struct vmcs_config vmcs_conf;
7630
7631 *(int *)rtn = 0;
7632 if (setup_vmcs_config(&vmcs_conf) < 0)
7633 *(int *)rtn = -EIO;
7634 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7635 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7636 smp_processor_id());
7637 *(int *)rtn = -EIO;
7638 }
7639}
7640
67253af5
SY		 7641static int get_ept_level(void)
7642{
7643 return VMX_EPT_DEFAULT_GAW + 1;
7644}
7645
4b12f0de 7646static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7647{
4b12f0de
SY		 7648 u64 ret;
7649
522c68c4
SY		 7650 /* For VT-d and EPT combination
7651 * 1. MMIO: always map as UC
7652 * 2. EPT with VT-d:
7653 * a. VT-d without snooping control feature: can't guarantee the
7654 * result, try to trust guest.
7655 * b. VT-d with snooping control feature: snooping control feature of
7656 * VT-d engine can guarantee the cache correctness. Just set it
7657 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7658 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7659 * consistent with host MTRR
7660 */
4b12f0de
SY		 7661 if (is_mmio)
7662 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
e0f0bbc5 7663 else if (kvm_arch_has_noncoherent_dma(vcpu->kvm))
522c68c4
SY		 7664 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7665 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7666 else
522c68c4 7667 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7668 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7669
7670 return ret;
64d4d521
SY		 7671}
7672
17cc3935 7673static int vmx_get_lpage_level(void)
344f414f 7674{
878403b7
SY		 7675 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7676 return PT_DIRECTORY_LEVEL;
7677 else
7678 /* For shadow and EPT supported 1GB page */
7679 return PT_PDPE_LEVEL;
344f414f
JR		 7680}
7681
0e851880
SY		 7682static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7683{
4e47c7a6
SY		 7684 struct kvm_cpuid_entry2 *best;
7685 struct vcpu_vmx *vmx = to_vmx(vcpu);
7686 u32 exec_control;
7687
7688 vmx->rdtscp_enabled = false;
7689 if (vmx_rdtscp_supported()) {
7690 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7691 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7692 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7693 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7694 vmx->rdtscp_enabled = true;
7695 else {
7696 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7697 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7698 exec_control);
7699 }
7700 }
7701 }
ad756a16 7702
ad756a16
MJ		 7703 /* Exposing INVPCID only when PCID is exposed */
7704 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7705 if (vmx_invpcid_supported() &&
4f977045 7706 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7707 guest_cpuid_has_pcid(vcpu)) {
29282fde 7708 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7709 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7710 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7711 exec_control);
7712 } else {
29282fde
TI		 7713 if (cpu_has_secondary_exec_ctrls()) {
7714 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7715 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7716 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7717 exec_control);
7718 }
ad756a16 7719 if (best)
4f977045 7720 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7721 }
0e851880
SY		 7722}
7723
d4330ef2
JR		 7724static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7725{
7b8050f5
NHE		 7726 if (func == 1 && nested)
7727 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7728}
7729
25d92081
YZ		 7730static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
7731 struct x86_exception *fault)
7732{
533558bc
JK		 7733 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7734 u32 exit_reason;
25d92081
YZ		 7735
7736 if (fault->error_code & PFERR_RSVD_MASK)
533558bc 7737 exit_reason = EXIT_REASON_EPT_MISCONFIG;
25d92081 7738 else
533558bc
JK		 7739 exit_reason = EXIT_REASON_EPT_VIOLATION;
7740 nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
25d92081
YZ		 7741 vmcs12->guest_physical_address = fault->address;
7742}
7743
155a97a3
NHE		 7744/* Callbacks for nested_ept_init_mmu_context: */
7745
7746static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
7747{
7748 /* return the page table to be shadowed - in our case, EPT12 */
7749 return get_vmcs12(vcpu)->ept_pointer;
7750}
7751
8a3c1a33 7752static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
155a97a3 7753{
8a3c1a33 7754 kvm_init_shadow_ept_mmu(vcpu, &vcpu->arch.mmu,
155a97a3
NHE		 7755 nested_vmx_ept_caps & VMX_EPT_EXECUTE_ONLY_BIT);
7756
7757 vcpu->arch.mmu.set_cr3 = vmx_set_cr3;
7758 vcpu->arch.mmu.get_cr3 = nested_ept_get_cr3;
7759 vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
7760
7761 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
155a97a3
NHE		 7762}
7763
7764static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
7765{
7766 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
7767}
7768
feaf0c7d
GN		 7769static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
7770 struct x86_exception *fault)
7771{
7772 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7773
7774 WARN_ON(!is_guest_mode(vcpu));
7775
7776 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7777 if (vmcs12->exception_bitmap & (1u << PF_VECTOR))
533558bc
JK		 7778 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
7779 vmcs_read32(VM_EXIT_INTR_INFO),
7780 vmcs_readl(EXIT_QUALIFICATION));
feaf0c7d
GN		 7781 else
7782 kvm_inject_page_fault(vcpu, fault);
7783}
7784
f4124500
JK		 7785static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
7786{
7787 u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
7788 struct vcpu_vmx *vmx = to_vmx(vcpu);
7789
7790 if (vcpu->arch.virtual_tsc_khz == 0)
7791 return;
7792
7793 /* Make sure short timeouts reliably trigger an immediate vmexit.
7794 * hrtimer_start does not guarantee this. */
7795 if (preemption_timeout <= 1) {
7796 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
7797 return;
7798 }
7799
7800 preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
7801 preemption_timeout *= 1000000;
7802 do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
7803 hrtimer_start(&vmx->nested.preemption_timer,
7804 ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
7805}
7806
fe3ef05c
NHE		 7807/*
7808 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7809 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7810 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7811 * guest in a way that will both be appropriate to L1's requests, and our
7812 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7813 * function also has additional necessary side-effects, like setting various
7814 * vcpu->arch fields.
7815 */
7816static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7817{
7818 struct vcpu_vmx *vmx = to_vmx(vcpu);
7819 u32 exec_control;
7820
7821 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7822 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7823 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7824 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7825 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7826 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7827 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7828 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7829 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7830 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7831 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7832 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7833 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7834 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7835 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7836 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7837 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7838 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7839 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7840 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7841 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7842 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7843 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7844 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7845 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7846 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7847 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7848 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7849 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7850 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7851 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7852 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7853 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7854 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7855 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7856 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7857
2996fca0
JK		 7858 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
7859 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
7860 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7861 } else {
7862 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
7863 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
7864 }
fe3ef05c
NHE		 7865 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7866 vmcs12->vm_entry_intr_info_field);
7867 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7868 vmcs12->vm_entry_exception_error_code);
7869 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7870 vmcs12->vm_entry_instruction_len);
7871 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7872 vmcs12->guest_interruptibility_info);
fe3ef05c 7873 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
63fbf59f 7874 vmx_set_rflags(vcpu, vmcs12->guest_rflags);
fe3ef05c
NHE		 7875 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7876 vmcs12->guest_pending_dbg_exceptions);
7877 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7878 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7879
7880 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7881
f4124500
JK		 7882 exec_control = vmcs12->pin_based_vm_exec_control;
7883 exec_control |= vmcs_config.pin_based_exec_ctrl;
696dfd95
PB		 7884 exec_control &= ~(PIN_BASED_VMX_PREEMPTION_TIMER |
7885 PIN_BASED_POSTED_INTR);
f4124500 7886 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
fe3ef05c 7887
f4124500
JK		 7888 vmx->nested.preemption_timer_expired = false;
7889 if (nested_cpu_has_preemption_timer(vmcs12))
7890 vmx_start_preemption_timer(vcpu);
0238ea91 7891
fe3ef05c
NHE		 7892 /*
7893 * Whether page-faults are trapped is determined by a combination of
7894 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7895 * If enable_ept, L0 doesn't care about page faults and we should
7896 * set all of these to L1's desires. However, if !enable_ept, L0 does
7897 * care about (at least some) page faults, and because it is not easy
7898 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7899 * to exit on each and every L2 page fault. This is done by setting
7900 * MASK=MATCH=0 and (see below) EB.PF=1.
7901 * Note that below we don't need special code to set EB.PF beyond the
7902 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7903 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7904 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7905 *
7906 * A problem with this approach (when !enable_ept) is that L1 may be
7907 * injected with more page faults than it asked for. This could have
7908 * caused problems, but in practice existing hypervisors don't care.
7909 * To fix this, we will need to emulate the PFEC checking (on the L1
7910 * page tables), using walk_addr(), when injecting PFs to L1.
7911 */
7912 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7913 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7914 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7915 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7916
7917 if (cpu_has_secondary_exec_ctrls()) {
f4124500 7918 exec_control = vmx_secondary_exec_control(vmx);
fe3ef05c
NHE		 7919 if (!vmx->rdtscp_enabled)
7920 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7921 /* Take the following fields only from vmcs12 */
696dfd95
PB		 7922 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
7923 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
7924 SECONDARY_EXEC_APIC_REGISTER_VIRT);
fe3ef05c
NHE		 7925 if (nested_cpu_has(vmcs12,
7926 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7927 exec_control |= vmcs12->secondary_vm_exec_control;
7928
7929 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7930 /*
7931 * Translate L1 physical address to host physical
7932 * address for vmcs02. Keep the page pinned, so this
7933 * physical address remains valid. We keep a reference
7934 * to it so we can release it later.
7935 */
7936 if (vmx->nested.apic_access_page) /* shouldn't happen */
7937 nested_release_page(vmx->nested.apic_access_page);
7938 vmx->nested.apic_access_page =
7939 nested_get_page(vcpu, vmcs12->apic_access_addr);
7940 /*
7941 * If translation failed, no matter: This feature asks
7942 * to exit when accessing the given address, and if it
7943 * can never be accessed, this feature won't do
7944 * anything anyway.
7945 */
7946 if (!vmx->nested.apic_access_page)
7947 exec_control &=
7948 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7949 else
7950 vmcs_write64(APIC_ACCESS_ADDR,
7951 page_to_phys(vmx->nested.apic_access_page));
ca3f257a
JK		 7952 } else if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) {
7953 exec_control |=
7954 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7955 vmcs_write64(APIC_ACCESS_ADDR,
7956 page_to_phys(vcpu->kvm->arch.apic_access_page));
fe3ef05c
NHE		 7957 }
7958
7959 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7960 }
7961
7962
7963 /*
7964 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7965 * Some constant fields are set here by vmx_set_constant_host_state().
7966 * Other fields are different per CPU, and will be set later when
7967 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7968 */
a547c6db 7969 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7970
7971 /*
7972 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7973 * entry, but only if the current (host) sp changed from the value
7974 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7975 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7976 * here we just force the write to happen on entry.
7977 */
7978 vmx->host_rsp = 0;
7979
7980 exec_control = vmx_exec_control(vmx); /* L0's desires */
7981 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7982 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7983 exec_control &= ~CPU_BASED_TPR_SHADOW;
7984 exec_control |= vmcs12->cpu_based_vm_exec_control;
7985 /*
7986 * Merging of IO and MSR bitmaps not currently supported.
7987 * Rather, exit every time.
7988 */
7989 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7990 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7991 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7992
7993 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7994
7995 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7996 * bitwise-or of what L1 wants to trap for L2, and what we want to
7997 * trap. Note that CR0.TS also needs updating - we do this later.
7998 */
7999 update_exception_bitmap(vcpu);
8000 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
8001 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8002
8049d651
NHE		 8003 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
8004 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
8005 * bits are further modified by vmx_set_efer() below.
8006 */
f4124500 8007 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
8049d651
NHE		 8008
8009 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
8010 * emulated by vmx_set_efer(), below.
8011 */
2961e876 8012 vm_entry_controls_init(vmx,
8049d651
NHE		 8013 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
8014 ~VM_ENTRY_IA32E_MODE) |
fe3ef05c
NHE		 8015 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
8016
44811c02 8017 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
fe3ef05c 8018 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
44811c02
JK		 8019 vcpu->arch.pat = vmcs12->guest_ia32_pat;
8020 } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
fe3ef05c
NHE		 8021 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
8022
8023
8024 set_cr4_guest_host_mask(vmx);
8025
36be0b9d
PB		 8026 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
8027 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
8028
27fc51b2
NHE		 8029 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
8030 vmcs_write64(TSC_OFFSET,
8031 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
8032 else
8033 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 8034
8035 if (enable_vpid) {
8036 /*
8037 * Trivially support vpid by letting L2s share their parent
8038 * L1's vpid. TODO: move to a more elaborate solution, giving
8039 * each L2 its own vpid and exposing the vpid feature to L1.
8040 */
8041 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
8042 vmx_flush_tlb(vcpu);
8043 }
8044
155a97a3
NHE		 8045 if (nested_cpu_has_ept(vmcs12)) {
8046 kvm_mmu_unload(vcpu);
8047 nested_ept_init_mmu_context(vcpu);
8048 }
8049
fe3ef05c
NHE		 8050 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
8051 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 8052 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 8053 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8054 else
8055 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8056 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8057 vmx_set_efer(vcpu, vcpu->arch.efer);
8058
8059 /*
8060 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8061 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8062 * The CR0_READ_SHADOW is what L2 should have expected to read given
8063 * the specifications by L1; It's not enough to take
8064 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8065 * have more bits than L1 expected.
8066 */
8067 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
8068 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
8069
8070 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
8071 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
8072
8073 /* shadow page tables on either EPT or shadow page tables */
8074 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
8075 kvm_mmu_reset_context(vcpu);
8076
feaf0c7d
GN		 8077 if (!enable_ept)
8078 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
8079
3633cfc3
NHE		 8080 /*
8081 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8082 */
8083 if (enable_ept) {
8084 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
8085 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
8086 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
8087 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
8088 }
8089
fe3ef05c
NHE		 8090 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
8091 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
8092}
8093
cd232ad0
NHE		 8094/*
8095 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8096 * for running an L2 nested guest.
8097 */
8098static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
8099{
8100 struct vmcs12 *vmcs12;
8101 struct vcpu_vmx *vmx = to_vmx(vcpu);
8102 int cpu;
8103 struct loaded_vmcs *vmcs02;
384bb783 8104 bool ia32e;
cd232ad0
NHE		 8105
8106 if (!nested_vmx_check_permission(vcpu) ||
8107 !nested_vmx_check_vmcs12(vcpu))
8108 return 1;
8109
8110 skip_emulated_instruction(vcpu);
8111 vmcs12 = get_vmcs12(vcpu);
8112
012f83cb
AG		 8113 if (enable_shadow_vmcs)
8114 copy_shadow_to_vmcs12(vmx);
8115
7c177938
NHE		 8116 /*
8117 * The nested entry process starts with enforcing various prerequisites
8118 * on vmcs12 as required by the Intel SDM, and act appropriately when
8119 * they fail: As the SDM explains, some conditions should cause the
8120 * instruction to fail, while others will cause the instruction to seem
8121 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8122 * To speed up the normal (success) code path, we should avoid checking
8123 * for misconfigurations which will anyway be caught by the processor
8124 * when using the merged vmcs02.
8125 */
8126 if (vmcs12->launch_state == launch) {
8127 nested_vmx_failValid(vcpu,
8128 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8129 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
8130 return 1;
8131 }
8132
6dfacadd
JK		 8133 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
8134 vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
26539bd0
PB		 8135 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8136 return 1;
8137 }
8138
7c177938 8139 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
bc39c4db 8140 !PAGE_ALIGNED(vmcs12->msr_bitmap)) {
7c177938
NHE		 8141 /*TODO: Also verify bits beyond physical address width are 0*/
8142 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8143 return 1;
8144 }
8145
8146 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
bc39c4db 8147 !PAGE_ALIGNED(vmcs12->apic_access_addr)) {
7c177938
NHE		 8148 /*TODO: Also verify bits beyond physical address width are 0*/
8149 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8150 return 1;
8151 }
8152
8153 if (vmcs12->vm_entry_msr_load_count > 0 ||
8154 vmcs12->vm_exit_msr_load_count > 0 ||
8155 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 8156 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8157 __func__);
7c177938
NHE		 8158 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8159 return 1;
8160 }
8161
8162 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
3dcdf3ec
JK		 8163 nested_vmx_true_procbased_ctls_low,
8164 nested_vmx_procbased_ctls_high) ||
7c177938
NHE		 8165 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
8166 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
8167 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
8168 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
8169 !vmx_control_verify(vmcs12->vm_exit_controls,
2996fca0
JK		 8170 nested_vmx_true_exit_ctls_low,
8171 nested_vmx_exit_ctls_high) ||
7c177938 8172 !vmx_control_verify(vmcs12->vm_entry_controls,
2996fca0
JK		 8173 nested_vmx_true_entry_ctls_low,
8174 nested_vmx_entry_ctls_high))
7c177938
NHE		 8175 {
8176 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
8177 return 1;
8178 }
8179
8180 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
8181 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8182 nested_vmx_failValid(vcpu,
8183 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
8184 return 1;
8185 }
8186
92fbc7b1 8187 if (!nested_cr0_valid(vmcs12, vmcs12->guest_cr0) ||
7c177938
NHE		 8188 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
8189 nested_vmx_entry_failure(vcpu, vmcs12,
8190 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8191 return 1;
8192 }
8193 if (vmcs12->vmcs_link_pointer != -1ull) {
8194 nested_vmx_entry_failure(vcpu, vmcs12,
8195 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
8196 return 1;
8197 }
8198
384bb783 8199 /*
cb0c8cda 8200 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 8201 * are performed on the field for the IA32_EFER MSR:
8202 * - Bits reserved in the IA32_EFER MSR must be 0.
8203 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8204 * the IA-32e mode guest VM-exit control. It must also be identical
8205 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8206 * CR0.PG) is 1.
8207 */
8208 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
8209 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
8210 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
8211 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
8212 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
8213 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
8214 nested_vmx_entry_failure(vcpu, vmcs12,
8215 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8216 return 1;
8217 }
8218 }
8219
8220 /*
8221 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8222 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8223 * the values of the LMA and LME bits in the field must each be that of
8224 * the host address-space size VM-exit control.
8225 */
8226 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
8227 ia32e = (vmcs12->vm_exit_controls &
8228 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
8229 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
8230 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
8231 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
8232 nested_vmx_entry_failure(vcpu, vmcs12,
8233 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
8234 return 1;
8235 }
8236 }
8237
7c177938
NHE		 8238 /*
8239 * We're finally done with prerequisite checking, and can start with
8240 * the nested entry.
8241 */
8242
cd232ad0
NHE		 8243 vmcs02 = nested_get_current_vmcs02(vmx);
8244 if (!vmcs02)
8245 return -ENOMEM;
8246
8247 enter_guest_mode(vcpu);
8248
8249 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
8250
2996fca0
JK		 8251 if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
8252 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8253
cd232ad0
NHE		 8254 cpu = get_cpu();
8255 vmx->loaded_vmcs = vmcs02;
8256 vmx_vcpu_put(vcpu);
8257 vmx_vcpu_load(vcpu, cpu);
8258 vcpu->cpu = cpu;
8259 put_cpu();
8260
36c3cc42
JK		 8261 vmx_segment_cache_clear(vmx);
8262
cd232ad0
NHE		 8263 vmcs12->launch_state = 1;
8264
8265 prepare_vmcs02(vcpu, vmcs12);
8266
6dfacadd
JK		 8267 if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
8268 return kvm_emulate_halt(vcpu);
8269
7af40ad3
JK		 8270 vmx->nested.nested_run_pending = 1;
8271
cd232ad0
NHE		 8272 /*
8273 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8274 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8275 * returned as far as L1 is concerned. It will only return (and set
8276 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8277 */
8278 return 1;
8279}
8280
4704d0be
NHE		 8281/*
8282 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8283 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8284 * This function returns the new value we should put in vmcs12.guest_cr0.
8285 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8286 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8287 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8288 * didn't trap the bit, because if L1 did, so would L0).
8289 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8290 * been modified by L2, and L1 knows it. So just leave the old value of
8291 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8292 * isn't relevant, because if L0 traps this bit it can set it to anything.
8293 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8294 * changed these bits, and therefore they need to be updated, but L0
8295 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8296 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8297 */
8298static inline unsigned long
8299vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8300{
8301 return
8302 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
8303 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
8304 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
8305 vcpu->arch.cr0_guest_owned_bits));
8306}
8307
8308static inline unsigned long
8309vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
8310{
8311 return
8312 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
8313 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
8314 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
8315 vcpu->arch.cr4_guest_owned_bits));
8316}
8317
5f3d5799
JK		 8318static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
8319 struct vmcs12 *vmcs12)
8320{
8321 u32 idt_vectoring;
8322 unsigned int nr;
8323
851eb667 8324 if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
5f3d5799
JK		 8325 nr = vcpu->arch.exception.nr;
8326 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8327
8328 if (kvm_exception_is_soft(nr)) {
8329 vmcs12->vm_exit_instruction_len =
8330 vcpu->arch.event_exit_inst_len;
8331 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
8332 } else
8333 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
8334
8335 if (vcpu->arch.exception.has_error_code) {
8336 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
8337 vmcs12->idt_vectoring_error_code =
8338 vcpu->arch.exception.error_code;
8339 }
8340
8341 vmcs12->idt_vectoring_info_field = idt_vectoring;
cd2633c5 8342 } else if (vcpu->arch.nmi_injected) {
5f3d5799
JK		 8343 vmcs12->idt_vectoring_info_field =
8344 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
8345 } else if (vcpu->arch.interrupt.pending) {
8346 nr = vcpu->arch.interrupt.nr;
8347 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
8348
8349 if (vcpu->arch.interrupt.soft) {
8350 idt_vectoring |= INTR_TYPE_SOFT_INTR;
8351 vmcs12->vm_entry_instruction_len =
8352 vcpu->arch.event_exit_inst_len;
8353 } else
8354 idt_vectoring |= INTR_TYPE_EXT_INTR;
8355
8356 vmcs12->idt_vectoring_info_field = idt_vectoring;
8357 }
8358}
8359
b6b8a145
JK		 8360static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
8361{
8362 struct vcpu_vmx *vmx = to_vmx(vcpu);
8363
f4124500
JK		 8364 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
8365 vmx->nested.preemption_timer_expired) {
8366 if (vmx->nested.nested_run_pending)
8367 return -EBUSY;
8368 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
8369 return 0;
8370 }
8371
b6b8a145 8372 if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
220c5672
JK		 8373 if (vmx->nested.nested_run_pending ||
8374 vcpu->arch.interrupt.pending)
b6b8a145
JK		 8375 return -EBUSY;
8376 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
8377 NMI_VECTOR | INTR_TYPE_NMI_INTR |
8378 INTR_INFO_VALID_MASK, 0);
8379 /*
8380 * The NMI-triggered VM exit counts as injection:
8381 * clear this one and block further NMIs.
8382 */
8383 vcpu->arch.nmi_pending = 0;
8384 vmx_set_nmi_mask(vcpu, true);
8385 return 0;
8386 }
8387
8388 if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
8389 nested_exit_on_intr(vcpu)) {
8390 if (vmx->nested.nested_run_pending)
8391 return -EBUSY;
8392 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
8393 }
8394
8395 return 0;
8396}
8397
f4124500
JK		 8398static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
8399{
8400 ktime_t remaining =
8401 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
8402 u64 value;
8403
8404 if (ktime_to_ns(remaining) <= 0)
8405 return 0;
8406
8407 value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
8408 do_div(value, 1000000);
8409 return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
8410}
8411
4704d0be
NHE		 8412/*
8413 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8414 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8415 * and this function updates it to reflect the changes to the guest state while
8416 * L2 was running (and perhaps made some exits which were handled directly by L0
8417 * without going back to L1), and to reflect the exit reason.
8418 * Note that we do not have to copy here all VMCS fields, just those that
8419 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8420 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8421 * which already writes to vmcs12 directly.
8422 */
533558bc
JK		 8423static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
8424 u32 exit_reason, u32 exit_intr_info,
8425 unsigned long exit_qualification)
4704d0be
NHE		 8426{
8427 /* update guest state fields: */
8428 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
8429 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
8430
4704d0be
NHE		 8431 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
8432 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
8433 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
8434
8435 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
8436 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
8437 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
8438 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
8439 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
8440 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
8441 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
8442 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
8443 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
8444 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
8445 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
8446 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
8447 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
8448 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
8449 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
8450 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
8451 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
8452 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
8453 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
8454 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
8455 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
8456 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
8457 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
8458 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
8459 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
8460 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
8461 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
8462 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
8463 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
8464 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
8465 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
8466 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
8467 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
8468 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
8469 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
8470 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
8471
4704d0be
NHE		 8472 vmcs12->guest_interruptibility_info =
8473 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
8474 vmcs12->guest_pending_dbg_exceptions =
8475 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
3edf1e69
JK		 8476 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
8477 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
8478 else
8479 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
4704d0be 8480
f4124500
JK		 8481 if (nested_cpu_has_preemption_timer(vmcs12)) {
8482 if (vmcs12->vm_exit_controls &
8483 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
8484 vmcs12->vmx_preemption_timer_value =
8485 vmx_get_preemption_timer_value(vcpu);
8486 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
8487 }
7854cbca 8488
3633cfc3
NHE		 8489 /*
8490 * In some cases (usually, nested EPT), L2 is allowed to change its
8491 * own CR3 without exiting. If it has changed it, we must keep it.
8492 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8493 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8494 *
8495 * Additionally, restore L2's PDPTR to vmcs12.
8496 */
8497 if (enable_ept) {
8498 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
8499 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
8500 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
8501 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
8502 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
8503 }
8504
c18911a2
JK		 8505 vmcs12->vm_entry_controls =
8506 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
2961e876 8507 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
c18911a2 8508
2996fca0
JK		 8509 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
8510 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
8511 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
8512 }
8513
4704d0be
NHE		 8514 /* TODO: These cannot have changed unless we have MSR bitmaps and
8515 * the relevant bit asks not to trap the change */
b8c07d55 8516 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be 8517 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10ba54a5
JK		 8518 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
8519 vmcs12->guest_ia32_efer = vcpu->arch.efer;
4704d0be
NHE		 8520 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
8521 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
8522 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
36be0b9d
PB		 8523 if (vmx_mpx_supported())
8524 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
4704d0be
NHE		 8525
8526 /* update exit information fields: */
8527
533558bc
JK		 8528 vmcs12->vm_exit_reason = exit_reason;
8529 vmcs12->exit_qualification = exit_qualification;
4704d0be 8530
533558bc 8531 vmcs12->vm_exit_intr_info = exit_intr_info;
c0d1c770
JK		 8532 if ((vmcs12->vm_exit_intr_info &
8533 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
8534 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
8535 vmcs12->vm_exit_intr_error_code =
8536 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 8537 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 8538 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
8539 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
8540
5f3d5799
JK		 8541 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
8542 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8543 * instead of reading the real value. */
4704d0be 8544 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 8545
8546 /*
8547 * Transfer the event that L0 or L1 may wanted to inject into
8548 * L2 to IDT_VECTORING_INFO_FIELD.
8549 */
8550 vmcs12_save_pending_event(vcpu, vmcs12);
8551 }
8552
8553 /*
8554 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8555 * preserved above and would only end up incorrectly in L1.
8556 */
8557 vcpu->arch.nmi_injected = false;
8558 kvm_clear_exception_queue(vcpu);
8559 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 8560}
8561
8562/*
8563 * A part of what we need to when the nested L2 guest exits and we want to
8564 * run its L1 parent, is to reset L1's guest state to the host state specified
8565 * in vmcs12.
8566 * This function is to be called not only on normal nested exit, but also on
8567 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8568 * Failures During or After Loading Guest State").
8569 * This function should be called when the active VMCS is L1's (vmcs01).
8570 */
733568f9
JK		 8571static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
8572 struct vmcs12 *vmcs12)
4704d0be 8573{
21feb4eb
ACL		 8574 struct kvm_segment seg;
8575
4704d0be
NHE		 8576 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
8577 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 8578 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 8579 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
8580 else
8581 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
8582 vmx_set_efer(vcpu, vcpu->arch.efer);
8583
8584 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
8585 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
1adfa76a 8586 vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
4704d0be
NHE		 8587 /*
8588 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8589 * actually changed, because it depends on the current state of
8590 * fpu_active (which may have changed).
8591 * Note that vmx_set_cr0 refers to efer set above.
8592 */
9e3e4dbf 8593 vmx_set_cr0(vcpu, vmcs12->host_cr0);
4704d0be
NHE		 8594 /*
8595 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8596 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8597 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8598 */
8599 update_exception_bitmap(vcpu);
8600 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
8601 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
8602
8603 /*
8604 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8605 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8606 */
8607 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
8608 kvm_set_cr4(vcpu, vmcs12->host_cr4);
8609
29bf08f1 8610 nested_ept_uninit_mmu_context(vcpu);
155a97a3 8611
4704d0be
NHE		 8612 kvm_set_cr3(vcpu, vmcs12->host_cr3);
8613 kvm_mmu_reset_context(vcpu);
8614
feaf0c7d
GN		 8615 if (!enable_ept)
8616 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
8617
4704d0be
NHE		 8618 if (enable_vpid) {
8619 /*
8620 * Trivially support vpid by letting L2s share their parent
8621 * L1's vpid. TODO: move to a more elaborate solution, giving
8622 * each L2 its own vpid and exposing the vpid feature to L1.
8623 */
8624 vmx_flush_tlb(vcpu);
8625 }
8626
8627
8628 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
8629 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
8630 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
8631 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
8632 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
4704d0be 8633
36be0b9d
PB		 8634 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8635 if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
8636 vmcs_write64(GUEST_BNDCFGS, 0);
8637
44811c02 8638 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
4704d0be 8639 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
44811c02
JK		 8640 vcpu->arch.pat = vmcs12->host_ia32_pat;
8641 }
4704d0be
NHE		 8642 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8643 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8644 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5 8645
21feb4eb
ACL		 8646 /* Set L1 segment info according to Intel SDM
8647 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8648 seg = (struct kvm_segment) {
8649 .base = 0,
8650 .limit = 0xFFFFFFFF,
8651 .selector = vmcs12->host_cs_selector,
8652 .type = 11,
8653 .present = 1,
8654 .s = 1,
8655 .g = 1
8656 };
8657 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
8658 seg.l = 1;
8659 else
8660 seg.db = 1;
8661 vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
8662 seg = (struct kvm_segment) {
8663 .base = 0,
8664 .limit = 0xFFFFFFFF,
8665 .type = 3,
8666 .present = 1,
8667 .s = 1,
8668 .db = 1,
8669 .g = 1
8670 };
8671 seg.selector = vmcs12->host_ds_selector;
8672 vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
8673 seg.selector = vmcs12->host_es_selector;
8674 vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
8675 seg.selector = vmcs12->host_ss_selector;
8676 vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
8677 seg.selector = vmcs12->host_fs_selector;
8678 seg.base = vmcs12->host_fs_base;
8679 vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
8680 seg.selector = vmcs12->host_gs_selector;
8681 seg.base = vmcs12->host_gs_base;
8682 vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
8683 seg = (struct kvm_segment) {
205befd9 8684 .base = vmcs12->host_tr_base,
21feb4eb
ACL		 8685 .limit = 0x67,
8686 .selector = vmcs12->host_tr_selector,
8687 .type = 11,
8688 .present = 1
8689 };
8690 vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
8691
503cd0c5
JK		 8692 kvm_set_dr(vcpu, 7, 0x400);
8693 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8694}
8695
8696/*
8697 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8698 * and modify vmcs12 to make it see what it would expect to see there if
8699 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8700 */
533558bc
JK		 8701static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
8702 u32 exit_intr_info,
8703 unsigned long exit_qualification)
4704d0be
NHE		 8704{
8705 struct vcpu_vmx *vmx = to_vmx(vcpu);
8706 int cpu;
8707 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8708
5f3d5799
JK		 8709 /* trying to cancel vmlaunch/vmresume is a bug */
8710 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8711
4704d0be 8712 leave_guest_mode(vcpu);
533558bc
JK		 8713 prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
8714 exit_qualification);
4704d0be 8715
77b0f5d6
BD		 8716 if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
8717 && nested_exit_intr_ack_set(vcpu)) {
8718 int irq = kvm_cpu_get_interrupt(vcpu);
8719 WARN_ON(irq < 0);
8720 vmcs12->vm_exit_intr_info = irq |
8721 INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
8722 }
8723
542060ea
JK		 8724 trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
8725 vmcs12->exit_qualification,
8726 vmcs12->idt_vectoring_info_field,
8727 vmcs12->vm_exit_intr_info,
8728 vmcs12->vm_exit_intr_error_code,
8729 KVM_ISA_VMX);
4704d0be
NHE		 8730
8731 cpu = get_cpu();
8732 vmx->loaded_vmcs = &vmx->vmcs01;
8733 vmx_vcpu_put(vcpu);
8734 vmx_vcpu_load(vcpu, cpu);
8735 vcpu->cpu = cpu;
8736 put_cpu();
8737
2961e876
GN		 8738 vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
8739 vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
36c3cc42
JK		 8740 vmx_segment_cache_clear(vmx);
8741
4704d0be
NHE		 8742 /* if no vmcs02 cache requested, remove the one we used */
8743 if (VMCS02_POOL_SIZE == 0)
8744 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8745
8746 load_vmcs12_host_state(vcpu, vmcs12);
8747
27fc51b2 8748 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8749 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8750
8751 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8752 vmx->host_rsp = 0;
8753
8754 /* Unpin physical memory we referred to in vmcs02 */
8755 if (vmx->nested.apic_access_page) {
8756 nested_release_page(vmx->nested.apic_access_page);
8757 vmx->nested.apic_access_page = 0;
8758 }
8759
8760 /*
8761 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8762 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8763 * success or failure flag accordingly.
8764 */
8765 if (unlikely(vmx->fail)) {
8766 vmx->fail = 0;
8767 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8768 } else
8769 nested_vmx_succeed(vcpu);
012f83cb
AG		 8770 if (enable_shadow_vmcs)
8771 vmx->nested.sync_shadow_vmcs = true;
b6b8a145
JK		 8772
8773 /* in case we halted in L2 */
8774 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4704d0be
NHE		 8775}
8776
42124925
JK		 8777/*
8778 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8779 */
8780static void vmx_leave_nested(struct kvm_vcpu *vcpu)
8781{
8782 if (is_guest_mode(vcpu))
533558bc 8783 nested_vmx_vmexit(vcpu, -1, 0, 0);
42124925
JK		 8784 free_nested(to_vmx(vcpu));
8785}
8786
7c177938
NHE		 8787/*
8788 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8789 * 23.7 "VM-entry failures during or after loading guest state" (this also
8790 * lists the acceptable exit-reason and exit-qualification parameters).
8791 * It should only be called before L2 actually succeeded to run, and when
8792 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8793 */
8794static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8795 struct vmcs12 *vmcs12,
8796 u32 reason, unsigned long qualification)
8797{
8798 load_vmcs12_host_state(vcpu, vmcs12);
8799 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8800 vmcs12->exit_qualification = qualification;
8801 nested_vmx_succeed(vcpu);
012f83cb
AG		 8802 if (enable_shadow_vmcs)
8803 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8804}
8805
8a76d7f2
JR		 8806static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8807 struct x86_instruction_info *info,
8808 enum x86_intercept_stage stage)
8809{
8810 return X86EMUL_CONTINUE;
8811}
8812
cbdd1bea 8813static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8814 .cpu_has_kvm_support = cpu_has_kvm_support,
8815 .disabled_by_bios = vmx_disabled_by_bios,
8816 .hardware_setup = hardware_setup,
8817 .hardware_unsetup = hardware_unsetup,
002c7f7c 8818 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8819 .hardware_enable = hardware_enable,
8820 .hardware_disable = hardware_disable,
04547156 8821 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8822
8823 .vcpu_create = vmx_create_vcpu,
8824 .vcpu_free = vmx_free_vcpu,
04d2cc77 8825 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8826
04d2cc77 8827 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8828 .vcpu_load = vmx_vcpu_load,
8829 .vcpu_put = vmx_vcpu_put,
8830
c8639010 8831 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8832 .get_msr = vmx_get_msr,
8833 .set_msr = vmx_set_msr,
8834 .get_segment_base = vmx_get_segment_base,
8835 .get_segment = vmx_get_segment,
8836 .set_segment = vmx_set_segment,
2e4d2653 8837 .get_cpl = vmx_get_cpl,
6aa8b732 8838 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8839 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8840 .decache_cr3 = vmx_decache_cr3,
25c4c276 8841 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8842 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8843 .set_cr3 = vmx_set_cr3,
8844 .set_cr4 = vmx_set_cr4,
6aa8b732 8845 .set_efer = vmx_set_efer,
6aa8b732
AK		 8846 .get_idt = vmx_get_idt,
8847 .set_idt = vmx_set_idt,
8848 .get_gdt = vmx_get_gdt,
8849 .set_gdt = vmx_set_gdt,
73aaf249
JK		 8850 .get_dr6 = vmx_get_dr6,
8851 .set_dr6 = vmx_set_dr6,
020df079 8852 .set_dr7 = vmx_set_dr7,
81908bf4 8853 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 8854 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8855 .get_rflags = vmx_get_rflags,
8856 .set_rflags = vmx_set_rflags,
ebcbab4c 8857 .fpu_activate = vmx_fpu_activate,
02daab21 8858 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8859
8860 .tlb_flush = vmx_flush_tlb,
6aa8b732 8861
6aa8b732 8862 .run = vmx_vcpu_run,
6062d012 8863 .handle_exit = vmx_handle_exit,
6aa8b732 8864 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8865 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8866 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8867 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8868 .set_irq = vmx_inject_irq,
95ba8273 8869 .set_nmi = vmx_inject_nmi,
298101da 8870 .queue_exception = vmx_queue_exception,
b463a6f7 8871 .cancel_injection = vmx_cancel_injection,
78646121 8872 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8873 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8874 .get_nmi_mask = vmx_get_nmi_mask,
8875 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8876 .enable_nmi_window = enable_nmi_window,
8877 .enable_irq_window = enable_irq_window,
8878 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8879 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8880 .vm_has_apicv = vmx_vm_has_apicv,
8881 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8882 .hwapic_irr_update = vmx_hwapic_irr_update,
8883 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8884 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8885 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8886
cbc94022 8887 .set_tss_addr = vmx_set_tss_addr,
67253af5 8888 .get_tdp_level = get_ept_level,
4b12f0de 8889 .get_mt_mask = vmx_get_mt_mask,
229456fc 8890
586f9607 8891 .get_exit_info = vmx_get_exit_info,
586f9607 8892
17cc3935 8893 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8894
8895 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8896
8897 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8898 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8899
8900 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8901
8902 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8903
4051b188 8904 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8905 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8906 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8907 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8908 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8909 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8910
8911 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8912
8913 .check_intercept = vmx_check_intercept,
a547c6db 8914 .handle_external_intr = vmx_handle_external_intr,
da8999d3 8915 .mpx_supported = vmx_mpx_supported,
b6b8a145
JK		 8916
8917 .check_nested_events = vmx_check_nested_events,
6aa8b732
AK		 8918};
8919
8920static int __init vmx_init(void)
8921{
8d14695f 8922 int r, i, msr;
26bb0981
AK		 8923
8924 rdmsrl_safe(MSR_EFER, &host_efer);
8925
8926 for (i = 0; i < NR_VMX_MSR; ++i)
8927 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8928
3e7c73e9 8929 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8930 if (!vmx_io_bitmap_a)
8931 return -ENOMEM;
8932
2106a548
GC		 8933 r = -ENOMEM;
8934
3e7c73e9 8935 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8936 if (!vmx_io_bitmap_b)
fdef3ad1 8937 goto out;
fdef3ad1 8938
5897297b 8939 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8940 if (!vmx_msr_bitmap_legacy)
25c5f225 8941 goto out1;
2106a548 8942
8d14695f
YZ		 8943 vmx_msr_bitmap_legacy_x2apic =
8944 (unsigned long *)__get_free_page(GFP_KERNEL);
8945 if (!vmx_msr_bitmap_legacy_x2apic)
8946 goto out2;
25c5f225 8947
5897297b 8948 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8949 if (!vmx_msr_bitmap_longmode)
8d14695f 8950 goto out3;
2106a548 8951
8d14695f
YZ		 8952 vmx_msr_bitmap_longmode_x2apic =
8953 (unsigned long *)__get_free_page(GFP_KERNEL);
8954 if (!vmx_msr_bitmap_longmode_x2apic)
8955 goto out4;
4607c2d7
AG		 8956 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8957 if (!vmx_vmread_bitmap)
8958 goto out5;
8959
8960 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8961 if (!vmx_vmwrite_bitmap)
8962 goto out6;
8963
8964 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8965 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
5897297b 8966
fdef3ad1
HQ		 8967 /*
8968 * Allow direct access to the PC debug port (it is often used for I/O
8969 * delays, but the vmexits simply slow things down).
8970 */
3e7c73e9
AK		 8971 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8972 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8973
3e7c73e9 8974 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8975
5897297b
AK		 8976 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8977 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8978
2384d2b3
SY		 8979 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8980
0ee75bea
AK		 8981 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8982 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8983 if (r)
4607c2d7 8984 goto out7;
25c5f225 8985
8f536b76
ZY		 8986#ifdef CONFIG_KEXEC
8987 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8988 crash_vmclear_local_loaded_vmcss);
8989#endif
8990
5897297b
AK		 8991 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8992 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8993 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8994 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8995 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8996 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
da8999d3
LJ		 8997 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
8998
8d14695f
YZ		 8999 memcpy(vmx_msr_bitmap_legacy_x2apic,
9000 vmx_msr_bitmap_legacy, PAGE_SIZE);
9001 memcpy(vmx_msr_bitmap_longmode_x2apic,
9002 vmx_msr_bitmap_longmode, PAGE_SIZE);
9003
01e439be 9004 if (enable_apicv) {
8d14695f
YZ		 9005 for (msr = 0x800; msr <= 0x8ff; msr++)
9006 vmx_disable_intercept_msr_read_x2apic(msr);
9007
9008 /* According SDM, in x2apic mode, the whole id reg is used.
9009 * But in KVM, it only use the highest eight bits. Need to
9010 * intercept it */
9011 vmx_enable_intercept_msr_read_x2apic(0x802);
9012 /* TMCCT */
9013 vmx_enable_intercept_msr_read_x2apic(0x839);
9014 /* TPR */
9015 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 9016 /* EOI */
9017 vmx_disable_intercept_msr_write_x2apic(0x80b);
9018 /* SELF-IPI */
9019 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 9020 }
fdef3ad1 9021
089d034e 9022 if (enable_ept) {
3f6d8c8a
XH		 9023 kvm_mmu_set_mask_ptes(0ull,
9024 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
9025 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
9026 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 9027 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 9028 kvm_enable_tdp();
9029 } else
9030 kvm_disable_tdp();
1439442c 9031
fdef3ad1
HQ		 9032 return 0;
9033
4607c2d7
AG		 9034out7:
9035 free_page((unsigned long)vmx_vmwrite_bitmap);
9036out6:
9037 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 9038out5:
9039 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 9040out4:
5897297b 9041 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 9042out3:
9043 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 9044out2:
5897297b 9045 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 9046out1:
3e7c73e9 9047 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 9048out:
3e7c73e9 9049 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 9050 return r;
6aa8b732
AK		 9051}
9052
9053static void __exit vmx_exit(void)
9054{
8d14695f
YZ		 9055 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
9056 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 9057 free_page((unsigned long)vmx_msr_bitmap_legacy);
9058 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 9059 free_page((unsigned long)vmx_io_bitmap_b);
9060 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 9061 free_page((unsigned long)vmx_vmwrite_bitmap);
9062 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 9063
8f536b76
ZY		 9064#ifdef CONFIG_KEXEC
9065 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
9066 synchronize_rcu();
9067#endif
9068
cb498ea2 9069 kvm_exit();
6aa8b732
AK		 9070}
9071
9072module_init(vmx_init)
9073module_exit(vmx_exit)
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