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KVM: MMU: make return value of mmio page fault handler more readable
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
5a71785d 87static bool __read_mostly enable_apicv = 1;
01e439be 88module_param(enable_apicv, bool, S_IRUGO);
83d4c286 89
abc4fc58
AG		 90static bool __read_mostly enable_shadow_vmcs = 1;
91module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
801d3424
NHE		 92/*
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
96 */
476bc001 97static bool __read_mostly nested = 0;
801d3424
NHE		 98module_param(nested, bool, S_IRUGO);
99
5037878e
GN		 100#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 102#define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 104#define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
107
cdc0e244
AK		 108#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
110
78ac8b47
AK		 111#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112
4b8d54f9
ZE		 113/*
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 117 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
123 */
00c25bce 124#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 125#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
127module_param(ple_gap, int, S_IRUGO);
128
129static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
130module_param(ple_window, int, S_IRUGO);
131
83287ea4
AK		 132extern const ulong vmx_return;
133
8bf00a52 134#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 135#define VMCS02_POOL_SIZE 1
61d2ef2c 136
a2fa3e9f
GH		 137struct vmcs {
138 u32 revision_id;
139 u32 abort;
140 char data[0];
141};
142
d462b819
NHE		 143/*
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
147 */
148struct loaded_vmcs {
149 struct vmcs *vmcs;
150 int cpu;
151 int launched;
152 struct list_head loaded_vmcss_on_cpu_link;
153};
154
26bb0981
AK		 155struct shared_msr_entry {
156 unsigned index;
157 u64 data;
d5696725 158 u64 mask;
26bb0981
AK		 159};
160
a9d30f33
NHE		 161/*
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
173 */
22bd0358 174typedef u64 natural_width;
a9d30f33
NHE		 175struct __packed vmcs12 {
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
178 */
179 u32 revision_id;
180 u32 abort;
22bd0358 181
27d6c865
NHE		 182 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding[7]; /* room for future expansion */
184
22bd0358
NHE		 185 u64 io_bitmap_a;
186 u64 io_bitmap_b;
187 u64 msr_bitmap;
188 u64 vm_exit_msr_store_addr;
189 u64 vm_exit_msr_load_addr;
190 u64 vm_entry_msr_load_addr;
191 u64 tsc_offset;
192 u64 virtual_apic_page_addr;
193 u64 apic_access_addr;
194 u64 ept_pointer;
195 u64 guest_physical_address;
196 u64 vmcs_link_pointer;
197 u64 guest_ia32_debugctl;
198 u64 guest_ia32_pat;
199 u64 guest_ia32_efer;
200 u64 guest_ia32_perf_global_ctrl;
201 u64 guest_pdptr0;
202 u64 guest_pdptr1;
203 u64 guest_pdptr2;
204 u64 guest_pdptr3;
205 u64 host_ia32_pat;
206 u64 host_ia32_efer;
207 u64 host_ia32_perf_global_ctrl;
208 u64 padding64[8]; /* room for future expansion */
209 /*
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
214 */
215 natural_width cr0_guest_host_mask;
216 natural_width cr4_guest_host_mask;
217 natural_width cr0_read_shadow;
218 natural_width cr4_read_shadow;
219 natural_width cr3_target_value0;
220 natural_width cr3_target_value1;
221 natural_width cr3_target_value2;
222 natural_width cr3_target_value3;
223 natural_width exit_qualification;
224 natural_width guest_linear_address;
225 natural_width guest_cr0;
226 natural_width guest_cr3;
227 natural_width guest_cr4;
228 natural_width guest_es_base;
229 natural_width guest_cs_base;
230 natural_width guest_ss_base;
231 natural_width guest_ds_base;
232 natural_width guest_fs_base;
233 natural_width guest_gs_base;
234 natural_width guest_ldtr_base;
235 natural_width guest_tr_base;
236 natural_width guest_gdtr_base;
237 natural_width guest_idtr_base;
238 natural_width guest_dr7;
239 natural_width guest_rsp;
240 natural_width guest_rip;
241 natural_width guest_rflags;
242 natural_width guest_pending_dbg_exceptions;
243 natural_width guest_sysenter_esp;
244 natural_width guest_sysenter_eip;
245 natural_width host_cr0;
246 natural_width host_cr3;
247 natural_width host_cr4;
248 natural_width host_fs_base;
249 natural_width host_gs_base;
250 natural_width host_tr_base;
251 natural_width host_gdtr_base;
252 natural_width host_idtr_base;
253 natural_width host_ia32_sysenter_esp;
254 natural_width host_ia32_sysenter_eip;
255 natural_width host_rsp;
256 natural_width host_rip;
257 natural_width paddingl[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control;
259 u32 cpu_based_vm_exec_control;
260 u32 exception_bitmap;
261 u32 page_fault_error_code_mask;
262 u32 page_fault_error_code_match;
263 u32 cr3_target_count;
264 u32 vm_exit_controls;
265 u32 vm_exit_msr_store_count;
266 u32 vm_exit_msr_load_count;
267 u32 vm_entry_controls;
268 u32 vm_entry_msr_load_count;
269 u32 vm_entry_intr_info_field;
270 u32 vm_entry_exception_error_code;
271 u32 vm_entry_instruction_len;
272 u32 tpr_threshold;
273 u32 secondary_vm_exec_control;
274 u32 vm_instruction_error;
275 u32 vm_exit_reason;
276 u32 vm_exit_intr_info;
277 u32 vm_exit_intr_error_code;
278 u32 idt_vectoring_info_field;
279 u32 idt_vectoring_error_code;
280 u32 vm_exit_instruction_len;
281 u32 vmx_instruction_info;
282 u32 guest_es_limit;
283 u32 guest_cs_limit;
284 u32 guest_ss_limit;
285 u32 guest_ds_limit;
286 u32 guest_fs_limit;
287 u32 guest_gs_limit;
288 u32 guest_ldtr_limit;
289 u32 guest_tr_limit;
290 u32 guest_gdtr_limit;
291 u32 guest_idtr_limit;
292 u32 guest_es_ar_bytes;
293 u32 guest_cs_ar_bytes;
294 u32 guest_ss_ar_bytes;
295 u32 guest_ds_ar_bytes;
296 u32 guest_fs_ar_bytes;
297 u32 guest_gs_ar_bytes;
298 u32 guest_ldtr_ar_bytes;
299 u32 guest_tr_ar_bytes;
300 u32 guest_interruptibility_info;
301 u32 guest_activity_state;
302 u32 guest_sysenter_cs;
303 u32 host_ia32_sysenter_cs;
0238ea91
JK		 304 u32 vmx_preemption_timer_value;
305 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 306 u16 virtual_processor_id;
307 u16 guest_es_selector;
308 u16 guest_cs_selector;
309 u16 guest_ss_selector;
310 u16 guest_ds_selector;
311 u16 guest_fs_selector;
312 u16 guest_gs_selector;
313 u16 guest_ldtr_selector;
314 u16 guest_tr_selector;
315 u16 host_es_selector;
316 u16 host_cs_selector;
317 u16 host_ss_selector;
318 u16 host_ds_selector;
319 u16 host_fs_selector;
320 u16 host_gs_selector;
321 u16 host_tr_selector;
a9d30f33
NHE		 322};
323
324/*
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
328 */
329#define VMCS12_REVISION 0x11e57ed0
330
331/*
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
335 */
336#define VMCS12_SIZE 0x1000
337
ff2f6fe9
NHE		 338/* Used to remember the last vmcs02 used for some recently used vmcs12s */
339struct vmcs02_list {
340 struct list_head list;
341 gpa_t vmptr;
342 struct loaded_vmcs vmcs02;
343};
344
ec378aee
NHE		 345/*
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
348 */
349struct nested_vmx {
350 /* Has the level1 guest done vmxon? */
351 bool vmxon;
a9d30f33
NHE		 352
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
354 gpa_t current_vmptr;
355 /* The host-usable pointer to the above */
356 struct page *current_vmcs12_page;
357 struct vmcs12 *current_vmcs12;
8de48833 358 struct vmcs *current_shadow_vmcs;
012f83cb
AG		 359 /*
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
362 */
363 bool sync_shadow_vmcs;
ff2f6fe9
NHE		 364
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool;
367 int vmcs02_num;
fe3ef05c 368 u64 vmcs01_tsc_offset;
644d711a
NHE		 369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending;
fe3ef05c
NHE		 371 /*
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
374 */
375 struct page *apic_access_page;
ec378aee
NHE		 376};
377
01e439be
YZ		 378#define POSTED_INTR_ON 0
379/* Posted-Interrupt Descriptor */
380struct pi_desc {
381 u32 pir[8]; /* Posted interrupt requested */
382 u32 control; /* bit 0 of control is outstanding notification bit */
383 u32 rsvd[7];
384} __aligned(64);
385
a20ed54d
YZ		 386static bool pi_test_and_set_on(struct pi_desc *pi_desc)
387{
388 return test_and_set_bit(POSTED_INTR_ON,
389 (unsigned long *)&pi_desc->control);
390}
391
392static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
393{
394 return test_and_clear_bit(POSTED_INTR_ON,
395 (unsigned long *)&pi_desc->control);
396}
397
398static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
399{
400 return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
401}
402
a2fa3e9f 403struct vcpu_vmx {
fb3f0f51 404 struct kvm_vcpu vcpu;
313dbd49 405 unsigned long host_rsp;
29bd8a78 406 u8 fail;
69c73028 407 u8 cpl;
9d58b931 408 bool nmi_known_unmasked;
51aa01d1 409 u32 exit_intr_info;
1155f76a 410 u32 idt_vectoring_info;
6de12732 411 ulong rflags;
26bb0981 412 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 413 int nmsrs;
414 int save_nmsrs;
a547c6db 415 unsigned long host_idt_base;
a2fa3e9f 416#ifdef CONFIG_X86_64
44ea2b17
AK		 417 u64 msr_host_kernel_gs_base;
418 u64 msr_guest_kernel_gs_base;
a2fa3e9f 419#endif
d462b819
NHE		 420 /*
421 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
422 * non-nested (L1) guest, it always points to vmcs01. For a nested
423 * guest (L2), it points to a different VMCS.
424 */
425 struct loaded_vmcs vmcs01;
426 struct loaded_vmcs *loaded_vmcs;
427 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 428 struct msr_autoload {
429 unsigned nr;
430 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
431 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
432 } msr_autoload;
a2fa3e9f
GH		 433 struct {
434 int loaded;
435 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 436#ifdef CONFIG_X86_64
437 u16 ds_sel, es_sel;
438#endif
152d3f2f
LV		 439 int gs_ldt_reload_needed;
440 int fs_reload_needed;
d77c26fc 441 } host_state;
9c8cba37 442 struct {
7ffd92c5 443 int vm86_active;
78ac8b47 444 ulong save_rflags;
f5f7b2fe
AK		 445 struct kvm_segment segs[8];
446 } rmode;
447 struct {
448 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 449 struct kvm_save_segment {
450 u16 selector;
451 unsigned long base;
452 u32 limit;
453 u32 ar;
f5f7b2fe 454 } seg[8];
2fb92db1 455 } segment_cache;
2384d2b3 456 int vpid;
04fa4d32 457 bool emulation_required;
3b86cd99
JK		 458
459 /* Support for vnmi-less CPUs */
460 int soft_vnmi_blocked;
461 ktime_t entry_time;
462 s64 vnmi_blocked_time;
a0861c02 463 u32 exit_reason;
4e47c7a6
SY		 464
465 bool rdtscp_enabled;
ec378aee 466
01e439be
YZ		 467 /* Posted interrupt descriptor */
468 struct pi_desc pi_desc;
469
ec378aee
NHE		 470 /* Support for a guest hypervisor (nested VMX) */
471 struct nested_vmx nested;
a2fa3e9f
GH		 472};
473
2fb92db1
AK		 474enum segment_cache_field {
475 SEG_FIELD_SEL = 0,
476 SEG_FIELD_BASE = 1,
477 SEG_FIELD_LIMIT = 2,
478 SEG_FIELD_AR = 3,
479
480 SEG_FIELD_NR = 4
481};
482
a2fa3e9f
GH		 483static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
484{
fb3f0f51 485 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 486}
487
22bd0358
NHE		 488#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
489#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
490#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
491 [number##_HIGH] = VMCS12_OFFSET(name)+4
492
4607c2d7
AG		 493
494static const unsigned long shadow_read_only_fields[] = {
495 /*
496 * We do NOT shadow fields that are modified when L0
497 * traps and emulates any vmx instruction (e.g. VMPTRLD,
498 * VMXON...) executed by L1.
499 * For example, VM_INSTRUCTION_ERROR is read
500 * by L1 if a vmx instruction fails (part of the error path).
501 * Note the code assumes this logic. If for some reason
502 * we start shadowing these fields then we need to
503 * force a shadow sync when L0 emulates vmx instructions
504 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
505 * by nested_vmx_failValid)
506 */
507 VM_EXIT_REASON,
508 VM_EXIT_INTR_INFO,
509 VM_EXIT_INSTRUCTION_LEN,
510 IDT_VECTORING_INFO_FIELD,
511 IDT_VECTORING_ERROR_CODE,
512 VM_EXIT_INTR_ERROR_CODE,
513 EXIT_QUALIFICATION,
514 GUEST_LINEAR_ADDRESS,
515 GUEST_PHYSICAL_ADDRESS
516};
517static const int max_shadow_read_only_fields =
518 ARRAY_SIZE(shadow_read_only_fields);
519
520static const unsigned long shadow_read_write_fields[] = {
521 GUEST_RIP,
522 GUEST_RSP,
523 GUEST_CR0,
524 GUEST_CR3,
525 GUEST_CR4,
526 GUEST_INTERRUPTIBILITY_INFO,
527 GUEST_RFLAGS,
528 GUEST_CS_SELECTOR,
529 GUEST_CS_AR_BYTES,
530 GUEST_CS_LIMIT,
531 GUEST_CS_BASE,
532 GUEST_ES_BASE,
533 CR0_GUEST_HOST_MASK,
534 CR0_READ_SHADOW,
535 CR4_READ_SHADOW,
536 TSC_OFFSET,
537 EXCEPTION_BITMAP,
538 CPU_BASED_VM_EXEC_CONTROL,
539 VM_ENTRY_EXCEPTION_ERROR_CODE,
540 VM_ENTRY_INTR_INFO_FIELD,
541 VM_ENTRY_INSTRUCTION_LEN,
542 VM_ENTRY_EXCEPTION_ERROR_CODE,
543 HOST_FS_BASE,
544 HOST_GS_BASE,
545 HOST_FS_SELECTOR,
546 HOST_GS_SELECTOR
547};
548static const int max_shadow_read_write_fields =
549 ARRAY_SIZE(shadow_read_write_fields);
550
772e0318 551static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 552 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
553 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
554 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
555 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
556 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
557 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
558 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
559 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
560 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
561 FIELD(HOST_ES_SELECTOR, host_es_selector),
562 FIELD(HOST_CS_SELECTOR, host_cs_selector),
563 FIELD(HOST_SS_SELECTOR, host_ss_selector),
564 FIELD(HOST_DS_SELECTOR, host_ds_selector),
565 FIELD(HOST_FS_SELECTOR, host_fs_selector),
566 FIELD(HOST_GS_SELECTOR, host_gs_selector),
567 FIELD(HOST_TR_SELECTOR, host_tr_selector),
568 FIELD64(IO_BITMAP_A, io_bitmap_a),
569 FIELD64(IO_BITMAP_B, io_bitmap_b),
570 FIELD64(MSR_BITMAP, msr_bitmap),
571 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
572 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
573 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
574 FIELD64(TSC_OFFSET, tsc_offset),
575 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
576 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
577 FIELD64(EPT_POINTER, ept_pointer),
578 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
579 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
580 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
581 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
582 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
583 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
584 FIELD64(GUEST_PDPTR0, guest_pdptr0),
585 FIELD64(GUEST_PDPTR1, guest_pdptr1),
586 FIELD64(GUEST_PDPTR2, guest_pdptr2),
587 FIELD64(GUEST_PDPTR3, guest_pdptr3),
588 FIELD64(HOST_IA32_PAT, host_ia32_pat),
589 FIELD64(HOST_IA32_EFER, host_ia32_efer),
590 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
591 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
592 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
593 FIELD(EXCEPTION_BITMAP, exception_bitmap),
594 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
595 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
596 FIELD(CR3_TARGET_COUNT, cr3_target_count),
597 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
598 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
599 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
600 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
601 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
602 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
603 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
604 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
605 FIELD(TPR_THRESHOLD, tpr_threshold),
606 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
607 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
608 FIELD(VM_EXIT_REASON, vm_exit_reason),
609 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
610 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
611 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
612 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
613 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
614 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
615 FIELD(GUEST_ES_LIMIT, guest_es_limit),
616 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
617 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
618 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
619 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
620 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
621 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
622 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
623 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
624 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
625 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
626 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
627 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
628 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
629 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
630 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
631 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
632 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
633 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
634 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
635 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
636 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 637 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 638 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
639 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
640 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
641 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
642 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
643 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
644 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
645 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
646 FIELD(EXIT_QUALIFICATION, exit_qualification),
647 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
648 FIELD(GUEST_CR0, guest_cr0),
649 FIELD(GUEST_CR3, guest_cr3),
650 FIELD(GUEST_CR4, guest_cr4),
651 FIELD(GUEST_ES_BASE, guest_es_base),
652 FIELD(GUEST_CS_BASE, guest_cs_base),
653 FIELD(GUEST_SS_BASE, guest_ss_base),
654 FIELD(GUEST_DS_BASE, guest_ds_base),
655 FIELD(GUEST_FS_BASE, guest_fs_base),
656 FIELD(GUEST_GS_BASE, guest_gs_base),
657 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
658 FIELD(GUEST_TR_BASE, guest_tr_base),
659 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
660 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
661 FIELD(GUEST_DR7, guest_dr7),
662 FIELD(GUEST_RSP, guest_rsp),
663 FIELD(GUEST_RIP, guest_rip),
664 FIELD(GUEST_RFLAGS, guest_rflags),
665 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
666 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
667 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
668 FIELD(HOST_CR0, host_cr0),
669 FIELD(HOST_CR3, host_cr3),
670 FIELD(HOST_CR4, host_cr4),
671 FIELD(HOST_FS_BASE, host_fs_base),
672 FIELD(HOST_GS_BASE, host_gs_base),
673 FIELD(HOST_TR_BASE, host_tr_base),
674 FIELD(HOST_GDTR_BASE, host_gdtr_base),
675 FIELD(HOST_IDTR_BASE, host_idtr_base),
676 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
677 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
678 FIELD(HOST_RSP, host_rsp),
679 FIELD(HOST_RIP, host_rip),
680};
681static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
682
683static inline short vmcs_field_to_offset(unsigned long field)
684{
685 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
686 return -1;
687 return vmcs_field_to_offset_table[field];
688}
689
a9d30f33
NHE		 690static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
691{
692 return to_vmx(vcpu)->nested.current_vmcs12;
693}
694
695static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
696{
697 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 698 if (is_error_page(page))
a9d30f33 699 return NULL;
32cad84f 700
a9d30f33
NHE		 701 return page;
702}
703
704static void nested_release_page(struct page *page)
705{
706 kvm_release_page_dirty(page);
707}
708
709static void nested_release_page_clean(struct page *page)
710{
711 kvm_release_page_clean(page);
712}
713
4e1096d2 714static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 715static void kvm_cpu_vmxon(u64 addr);
716static void kvm_cpu_vmxoff(void);
aff48baa 717static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 718static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 719static void vmx_set_segment(struct kvm_vcpu *vcpu,
720 struct kvm_segment *var, int seg);
721static void vmx_get_segment(struct kvm_vcpu *vcpu,
722 struct kvm_segment *var, int seg);
d99e4152
GN		 723static bool guest_state_valid(struct kvm_vcpu *vcpu);
724static u32 vmx_segment_access_rights(struct kvm_segment *var);
a20ed54d 725static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
c3114420 726static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
16f5b903 727static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
75880a01 728
6aa8b732
AK		 729static DEFINE_PER_CPU(struct vmcs *, vmxarea);
730static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 731/*
732 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
733 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
734 */
735static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 736static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 737
3e7c73e9
AK		 738static unsigned long *vmx_io_bitmap_a;
739static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 740static unsigned long *vmx_msr_bitmap_legacy;
741static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 742static unsigned long *vmx_msr_bitmap_legacy_x2apic;
743static unsigned long *vmx_msr_bitmap_longmode_x2apic;
4607c2d7
AG		 744static unsigned long *vmx_vmread_bitmap;
745static unsigned long *vmx_vmwrite_bitmap;
fdef3ad1 746
110312c8 747static bool cpu_has_load_ia32_efer;
8bf00a52 748static bool cpu_has_load_perf_global_ctrl;
110312c8 749
2384d2b3
SY		 750static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
751static DEFINE_SPINLOCK(vmx_vpid_lock);
752
1c3d14fe 753static struct vmcs_config {
6aa8b732
AK		 754 int size;
755 int order;
756 u32 revision_id;
1c3d14fe
YS		 757 u32 pin_based_exec_ctrl;
758 u32 cpu_based_exec_ctrl;
f78e0e2e 759 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 760 u32 vmexit_ctrl;
761 u32 vmentry_ctrl;
762} vmcs_config;
6aa8b732 763
efff9e53 764static struct vmx_capability {
d56f546d
SY		 765 u32 ept;
766 u32 vpid;
767} vmx_capability;
768
6aa8b732
AK		 769#define VMX_SEGMENT_FIELD(seg) \
770 [VCPU_SREG_##seg] = { \
771 .selector = GUEST_##seg##_SELECTOR, \
772 .base = GUEST_##seg##_BASE, \
773 .limit = GUEST_##seg##_LIMIT, \
774 .ar_bytes = GUEST_##seg##_AR_BYTES, \
775 }
776
772e0318 777static const struct kvm_vmx_segment_field {
6aa8b732
AK		 778 unsigned selector;
779 unsigned base;
780 unsigned limit;
781 unsigned ar_bytes;
782} kvm_vmx_segment_fields[] = {
783 VMX_SEGMENT_FIELD(CS),
784 VMX_SEGMENT_FIELD(DS),
785 VMX_SEGMENT_FIELD(ES),
786 VMX_SEGMENT_FIELD(FS),
787 VMX_SEGMENT_FIELD(GS),
788 VMX_SEGMENT_FIELD(SS),
789 VMX_SEGMENT_FIELD(TR),
790 VMX_SEGMENT_FIELD(LDTR),
791};
792
26bb0981
AK		 793static u64 host_efer;
794
6de4f3ad
AK		 795static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
796
4d56c8a7 797/*
8c06585d 798 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 799 * away by decrementing the array size.
800 */
6aa8b732 801static const u32 vmx_msr_index[] = {
05b3e0c2 802#ifdef CONFIG_X86_64
44ea2b17 803 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 804#endif
8c06585d 805 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 806};
9d8f549d 807#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 808
31299944 809static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 810{
811 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
812 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 813 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 814}
815
31299944 816static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 817{
818 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
819 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 820 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 821}
822
31299944 823static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 824{
825 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
826 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 827 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 828}
829
31299944 830static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 831{
832 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
833 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
834}
835
31299944 836static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 837{
838 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
839 INTR_INFO_VALID_MASK)) ==
840 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
841}
842
31299944 843static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 844{
04547156 845 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 846}
847
31299944 848static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 849{
04547156 850 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 851}
852
31299944 853static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 854{
04547156 855 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 856}
857
31299944 858static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 859{
04547156
SY		 860 return vmcs_config.cpu_based_exec_ctrl &
861 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 862}
863
774ead3a 864static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 865{
04547156
SY		 866 return vmcs_config.cpu_based_2nd_exec_ctrl &
867 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
868}
869
8d14695f
YZ		 870static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
871{
872 return vmcs_config.cpu_based_2nd_exec_ctrl &
873 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
874}
875
83d4c286
YZ		 876static inline bool cpu_has_vmx_apic_register_virt(void)
877{
878 return vmcs_config.cpu_based_2nd_exec_ctrl &
879 SECONDARY_EXEC_APIC_REGISTER_VIRT;
880}
881
c7c9c56c
YZ		 882static inline bool cpu_has_vmx_virtual_intr_delivery(void)
883{
884 return vmcs_config.cpu_based_2nd_exec_ctrl &
885 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
886}
887
01e439be
YZ		 888static inline bool cpu_has_vmx_posted_intr(void)
889{
890 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
891}
892
893static inline bool cpu_has_vmx_apicv(void)
894{
895 return cpu_has_vmx_apic_register_virt() &&
896 cpu_has_vmx_virtual_intr_delivery() &&
897 cpu_has_vmx_posted_intr();
898}
899
04547156
SY		 900static inline bool cpu_has_vmx_flexpriority(void)
901{
902 return cpu_has_vmx_tpr_shadow() &&
903 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 904}
905
e799794e
MT		 906static inline bool cpu_has_vmx_ept_execute_only(void)
907{
31299944 908 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 909}
910
911static inline bool cpu_has_vmx_eptp_uncacheable(void)
912{
31299944 913 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 914}
915
916static inline bool cpu_has_vmx_eptp_writeback(void)
917{
31299944 918 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 919}
920
921static inline bool cpu_has_vmx_ept_2m_page(void)
922{
31299944 923 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 924}
925
878403b7
SY		 926static inline bool cpu_has_vmx_ept_1g_page(void)
927{
31299944 928 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 929}
930
4bc9b982
SY		 931static inline bool cpu_has_vmx_ept_4levels(void)
932{
933 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
934}
935
83c3a331
XH		 936static inline bool cpu_has_vmx_ept_ad_bits(void)
937{
938 return vmx_capability.ept & VMX_EPT_AD_BIT;
939}
940
31299944 941static inline bool cpu_has_vmx_invept_context(void)
d56f546d 942{
31299944 943 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 944}
945
31299944 946static inline bool cpu_has_vmx_invept_global(void)
d56f546d 947{
31299944 948 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 949}
950
518c8aee
GJ		 951static inline bool cpu_has_vmx_invvpid_single(void)
952{
953 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
954}
955
b9d762fa
GJ		 956static inline bool cpu_has_vmx_invvpid_global(void)
957{
958 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
959}
960
31299944 961static inline bool cpu_has_vmx_ept(void)
d56f546d 962{
04547156
SY		 963 return vmcs_config.cpu_based_2nd_exec_ctrl &
964 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 965}
966
31299944 967static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 968{
969 return vmcs_config.cpu_based_2nd_exec_ctrl &
970 SECONDARY_EXEC_UNRESTRICTED_GUEST;
971}
972
31299944 973static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 974{
975 return vmcs_config.cpu_based_2nd_exec_ctrl &
976 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
977}
978
31299944 979static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 980{
6d3e435e 981 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 982}
983
31299944 984static inline bool cpu_has_vmx_vpid(void)
2384d2b3 985{
04547156
SY		 986 return vmcs_config.cpu_based_2nd_exec_ctrl &
987 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 988}
989
31299944 990static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 991{
992 return vmcs_config.cpu_based_2nd_exec_ctrl &
993 SECONDARY_EXEC_RDTSCP;
994}
995
ad756a16
MJ		 996static inline bool cpu_has_vmx_invpcid(void)
997{
998 return vmcs_config.cpu_based_2nd_exec_ctrl &
999 SECONDARY_EXEC_ENABLE_INVPCID;
1000}
1001
31299944 1002static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 1003{
1004 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1005}
1006
f5f48ee1
SY		 1007static inline bool cpu_has_vmx_wbinvd_exit(void)
1008{
1009 return vmcs_config.cpu_based_2nd_exec_ctrl &
1010 SECONDARY_EXEC_WBINVD_EXITING;
1011}
1012
abc4fc58
AG		 1013static inline bool cpu_has_vmx_shadow_vmcs(void)
1014{
1015 u64 vmx_msr;
1016 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1017 /* check if the cpu supports writing r/o exit information fields */
1018 if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1019 return false;
1020
1021 return vmcs_config.cpu_based_2nd_exec_ctrl &
1022 SECONDARY_EXEC_SHADOW_VMCS;
1023}
1024
04547156
SY		 1025static inline bool report_flexpriority(void)
1026{
1027 return flexpriority_enabled;
1028}
1029
fe3ef05c
NHE		 1030static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1031{
1032 return vmcs12->cpu_based_vm_exec_control & bit;
1033}
1034
1035static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1036{
1037 return (vmcs12->cpu_based_vm_exec_control &
1038 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1039 (vmcs12->secondary_vm_exec_control & bit);
1040}
1041
644d711a
NHE		 1042static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
1043 struct kvm_vcpu *vcpu)
1044{
1045 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1046}
1047
1048static inline bool is_exception(u32 intr_info)
1049{
1050 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1051 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1052}
1053
1054static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 1055static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1056 struct vmcs12 *vmcs12,
1057 u32 reason, unsigned long qualification);
1058
8b9cf98c 1059static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 1060{
1061 int i;
1062
a2fa3e9f 1063 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 1064 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 1065 return i;
1066 return -1;
1067}
1068
2384d2b3
SY		 1069static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1070{
1071 struct {
1072 u64 vpid : 16;
1073 u64 rsvd : 48;
1074 u64 gva;
1075 } operand = { vpid, 0, gva };
1076
4ecac3fd 1077 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 1078 /* CF==1 or ZF==1 --> rc = -1 */
1079 "; ja 1f ; ud2 ; 1:"
1080 : : "a"(&operand), "c"(ext) : "cc", "memory");
1081}
1082
1439442c
SY		 1083static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1084{
1085 struct {
1086 u64 eptp, gpa;
1087 } operand = {eptp, gpa};
1088
4ecac3fd 1089 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 1090 /* CF==1 or ZF==1 --> rc = -1 */
1091 "; ja 1f ; ud2 ; 1:\n"
1092 : : "a" (&operand), "c" (ext) : "cc", "memory");
1093}
1094
26bb0981 1095static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 1096{
1097 int i;
1098
8b9cf98c 1099 i = __find_msr_index(vmx, msr);
a75beee6 1100 if (i >= 0)
a2fa3e9f 1101 return &vmx->guest_msrs[i];
8b6d44c7 1102 return NULL;
7725f0ba
AK		 1103}
1104
6aa8b732
AK		 1105static void vmcs_clear(struct vmcs *vmcs)
1106{
1107 u64 phys_addr = __pa(vmcs);
1108 u8 error;
1109
4ecac3fd 1110 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 1111 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 1112 : "cc", "memory");
1113 if (error)
1114 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1115 vmcs, phys_addr);
1116}
1117
d462b819
NHE		 1118static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1119{
1120 vmcs_clear(loaded_vmcs->vmcs);
1121 loaded_vmcs->cpu = -1;
1122 loaded_vmcs->launched = 0;
1123}
1124
7725b894
DX		 1125static void vmcs_load(struct vmcs *vmcs)
1126{
1127 u64 phys_addr = __pa(vmcs);
1128 u8 error;
1129
1130 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1131 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1132 : "cc", "memory");
1133 if (error)
2844d849 1134 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1135 vmcs, phys_addr);
1136}
1137
8f536b76
ZY		 1138#ifdef CONFIG_KEXEC
1139/*
1140 * This bitmap is used to indicate whether the vmclear
1141 * operation is enabled on all cpus. All disabled by
1142 * default.
1143 */
1144static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1145
1146static inline void crash_enable_local_vmclear(int cpu)
1147{
1148 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1149}
1150
1151static inline void crash_disable_local_vmclear(int cpu)
1152{
1153 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1154}
1155
1156static inline int crash_local_vmclear_enabled(int cpu)
1157{
1158 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1159}
1160
1161static void crash_vmclear_local_loaded_vmcss(void)
1162{
1163 int cpu = raw_smp_processor_id();
1164 struct loaded_vmcs *v;
1165
1166 if (!crash_local_vmclear_enabled(cpu))
1167 return;
1168
1169 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1170 loaded_vmcss_on_cpu_link)
1171 vmcs_clear(v->vmcs);
1172}
1173#else
1174static inline void crash_enable_local_vmclear(int cpu) { }
1175static inline void crash_disable_local_vmclear(int cpu) { }
1176#endif /* CONFIG_KEXEC */
1177
d462b819 1178static void __loaded_vmcs_clear(void *arg)
6aa8b732 1179{
d462b819 1180 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1181 int cpu = raw_smp_processor_id();
6aa8b732 1182
d462b819
NHE		 1183 if (loaded_vmcs->cpu != cpu)
1184 return; /* vcpu migration can race with cpu offline */
1185 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1186 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1187 crash_disable_local_vmclear(cpu);
d462b819 1188 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1189
1190 /*
1191 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1192 * is before setting loaded_vmcs->vcpu to -1 which is done in
1193 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1194 * then adds the vmcs into percpu list before it is deleted.
1195 */
1196 smp_wmb();
1197
d462b819 1198 loaded_vmcs_init(loaded_vmcs);
8f536b76 1199 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1200}
1201
d462b819 1202static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1203{
e6c7d321
XG		 1204 int cpu = loaded_vmcs->cpu;
1205
1206 if (cpu != -1)
1207 smp_call_function_single(cpu,
1208 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1209}
1210
1760dd49 1211static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1212{
1213 if (vmx->vpid == 0)
1214 return;
1215
518c8aee
GJ		 1216 if (cpu_has_vmx_invvpid_single())
1217 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1218}
1219
b9d762fa
GJ		 1220static inline void vpid_sync_vcpu_global(void)
1221{
1222 if (cpu_has_vmx_invvpid_global())
1223 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1224}
1225
1226static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1227{
1228 if (cpu_has_vmx_invvpid_single())
1760dd49 1229 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1230 else
1231 vpid_sync_vcpu_global();
1232}
1233
1439442c
SY		 1234static inline void ept_sync_global(void)
1235{
1236 if (cpu_has_vmx_invept_global())
1237 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1238}
1239
1240static inline void ept_sync_context(u64 eptp)
1241{
089d034e 1242 if (enable_ept) {
1439442c
SY		 1243 if (cpu_has_vmx_invept_context())
1244 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1245 else
1246 ept_sync_global();
1247 }
1248}
1249
96304217 1250static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1251{
5e520e62 1252 unsigned long value;
6aa8b732 1253
5e520e62
AK		 1254 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1255 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1256 return value;
1257}
1258
96304217 1259static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1260{
1261 return vmcs_readl(field);
1262}
1263
96304217 1264static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1265{
1266 return vmcs_readl(field);
1267}
1268
96304217 1269static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1270{
05b3e0c2 1271#ifdef CONFIG_X86_64
6aa8b732
AK		 1272 return vmcs_readl(field);
1273#else
1274 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1275#endif
1276}
1277
e52de1b8
AK		 1278static noinline void vmwrite_error(unsigned long field, unsigned long value)
1279{
1280 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1281 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1282 dump_stack();
1283}
1284
6aa8b732
AK		 1285static void vmcs_writel(unsigned long field, unsigned long value)
1286{
1287 u8 error;
1288
4ecac3fd 1289 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1290 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1291 if (unlikely(error))
1292 vmwrite_error(field, value);
6aa8b732
AK		 1293}
1294
1295static void vmcs_write16(unsigned long field, u16 value)
1296{
1297 vmcs_writel(field, value);
1298}
1299
1300static void vmcs_write32(unsigned long field, u32 value)
1301{
1302 vmcs_writel(field, value);
1303}
1304
1305static void vmcs_write64(unsigned long field, u64 value)
1306{
6aa8b732 1307 vmcs_writel(field, value);
7682f2d0 1308#ifndef CONFIG_X86_64
6aa8b732
AK		 1309 asm volatile ("");
1310 vmcs_writel(field+1, value >> 32);
1311#endif
1312}
1313
2ab455cc
AL		 1314static void vmcs_clear_bits(unsigned long field, u32 mask)
1315{
1316 vmcs_writel(field, vmcs_readl(field) & ~mask);
1317}
1318
1319static void vmcs_set_bits(unsigned long field, u32 mask)
1320{
1321 vmcs_writel(field, vmcs_readl(field) | mask);
1322}
1323
2fb92db1
AK		 1324static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1325{
1326 vmx->segment_cache.bitmask = 0;
1327}
1328
1329static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1330 unsigned field)
1331{
1332 bool ret;
1333 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1334
1335 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1336 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1337 vmx->segment_cache.bitmask = 0;
1338 }
1339 ret = vmx->segment_cache.bitmask & mask;
1340 vmx->segment_cache.bitmask |= mask;
1341 return ret;
1342}
1343
1344static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1345{
1346 u16 *p = &vmx->segment_cache.seg[seg].selector;
1347
1348 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1349 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1350 return *p;
1351}
1352
1353static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1354{
1355 ulong *p = &vmx->segment_cache.seg[seg].base;
1356
1357 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1358 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1359 return *p;
1360}
1361
1362static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1363{
1364 u32 *p = &vmx->segment_cache.seg[seg].limit;
1365
1366 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1367 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1368 return *p;
1369}
1370
1371static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1372{
1373 u32 *p = &vmx->segment_cache.seg[seg].ar;
1374
1375 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1376 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1377 return *p;
1378}
1379
abd3f2d6
AK		 1380static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1381{
1382 u32 eb;
1383
fd7373cc
JK		 1384 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1385 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1386 if ((vcpu->guest_debug &
1387 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1388 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1389 eb |= 1u << BP_VECTOR;
7ffd92c5 1390 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1391 eb = ~0;
089d034e 1392 if (enable_ept)
1439442c 1393 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1394 if (vcpu->fpu_active)
1395 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1396
1397 /* When we are running a nested L2 guest and L1 specified for it a
1398 * certain exception bitmap, we must trap the same exceptions and pass
1399 * them to L1. When running L2, we will only handle the exceptions
1400 * specified above if L1 did not want them.
1401 */
1402 if (is_guest_mode(vcpu))
1403 eb |= get_vmcs12(vcpu)->exception_bitmap;
1404
abd3f2d6
AK		 1405 vmcs_write32(EXCEPTION_BITMAP, eb);
1406}
1407
8bf00a52
GN		 1408static void clear_atomic_switch_msr_special(unsigned long entry,
1409 unsigned long exit)
1410{
1411 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1412 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1413}
1414
61d2ef2c
AK		 1415static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1416{
1417 unsigned i;
1418 struct msr_autoload *m = &vmx->msr_autoload;
1419
8bf00a52
GN		 1420 switch (msr) {
1421 case MSR_EFER:
1422 if (cpu_has_load_ia32_efer) {
1423 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1424 VM_EXIT_LOAD_IA32_EFER);
1425 return;
1426 }
1427 break;
1428 case MSR_CORE_PERF_GLOBAL_CTRL:
1429 if (cpu_has_load_perf_global_ctrl) {
1430 clear_atomic_switch_msr_special(
1431 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1432 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1433 return;
1434 }
1435 break;
110312c8
AK		 1436 }
1437
61d2ef2c
AK		 1438 for (i = 0; i < m->nr; ++i)
1439 if (m->guest[i].index == msr)
1440 break;
1441
1442 if (i == m->nr)
1443 return;
1444 --m->nr;
1445 m->guest[i] = m->guest[m->nr];
1446 m->host[i] = m->host[m->nr];
1447 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1448 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1449}
1450
8bf00a52
GN		 1451static void add_atomic_switch_msr_special(unsigned long entry,
1452 unsigned long exit, unsigned long guest_val_vmcs,
1453 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1454{
1455 vmcs_write64(guest_val_vmcs, guest_val);
1456 vmcs_write64(host_val_vmcs, host_val);
1457 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1458 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1459}
1460
61d2ef2c
AK		 1461static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1462 u64 guest_val, u64 host_val)
1463{
1464 unsigned i;
1465 struct msr_autoload *m = &vmx->msr_autoload;
1466
8bf00a52
GN		 1467 switch (msr) {
1468 case MSR_EFER:
1469 if (cpu_has_load_ia32_efer) {
1470 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1471 VM_EXIT_LOAD_IA32_EFER,
1472 GUEST_IA32_EFER,
1473 HOST_IA32_EFER,
1474 guest_val, host_val);
1475 return;
1476 }
1477 break;
1478 case MSR_CORE_PERF_GLOBAL_CTRL:
1479 if (cpu_has_load_perf_global_ctrl) {
1480 add_atomic_switch_msr_special(
1481 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1482 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1483 GUEST_IA32_PERF_GLOBAL_CTRL,
1484 HOST_IA32_PERF_GLOBAL_CTRL,
1485 guest_val, host_val);
1486 return;
1487 }
1488 break;
110312c8
AK		 1489 }
1490
61d2ef2c
AK		 1491 for (i = 0; i < m->nr; ++i)
1492 if (m->guest[i].index == msr)
1493 break;
1494
e7fc6f93
GN		 1495 if (i == NR_AUTOLOAD_MSRS) {
1496 printk_once(KERN_WARNING"Not enough mst switch entries. "
1497 "Can't add msr %x\n", msr);
1498 return;
1499 } else if (i == m->nr) {
61d2ef2c
AK		 1500 ++m->nr;
1501 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1502 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1503 }
1504
1505 m->guest[i].index = msr;
1506 m->guest[i].value = guest_val;
1507 m->host[i].index = msr;
1508 m->host[i].value = host_val;
1509}
1510
33ed6329
AK		 1511static void reload_tss(void)
1512{
33ed6329
AK		 1513 /*
1514 * VT restores TR but not its size. Useless.
1515 */
d359192f 1516 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1517 struct desc_struct *descs;
33ed6329 1518
d359192f 1519 descs = (void *)gdt->address;
33ed6329
AK		 1520 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1521 load_TR_desc();
33ed6329
AK		 1522}
1523
92c0d900 1524static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1525{
3a34a881 1526 u64 guest_efer;
51c6cf66
AK		 1527 u64 ignore_bits;
1528
f6801dff 1529 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1530
51c6cf66 1531 /*
0fa06071 1532 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1533 * outside long mode
1534 */
1535 ignore_bits = EFER_NX | EFER_SCE;
1536#ifdef CONFIG_X86_64
1537 ignore_bits |= EFER_LMA | EFER_LME;
1538 /* SCE is meaningful only in long mode on Intel */
1539 if (guest_efer & EFER_LMA)
1540 ignore_bits &= ~(u64)EFER_SCE;
1541#endif
51c6cf66
AK		 1542 guest_efer &= ~ignore_bits;
1543 guest_efer |= host_efer & ignore_bits;
26bb0981 1544 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1545 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1546
1547 clear_atomic_switch_msr(vmx, MSR_EFER);
1548 /* On ept, can't emulate nx, and must switch nx atomically */
1549 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1550 guest_efer = vmx->vcpu.arch.efer;
1551 if (!(guest_efer & EFER_LMA))
1552 guest_efer &= ~EFER_LME;
1553 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1554 return false;
1555 }
1556
26bb0981 1557 return true;
51c6cf66
AK		 1558}
1559
2d49ec72
GN		 1560static unsigned long segment_base(u16 selector)
1561{
d359192f 1562 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1563 struct desc_struct *d;
1564 unsigned long table_base;
1565 unsigned long v;
1566
1567 if (!(selector & ~3))
1568 return 0;
1569
d359192f 1570 table_base = gdt->address;
2d49ec72
GN		 1571
1572 if (selector & 4) { /* from ldt */
1573 u16 ldt_selector = kvm_read_ldt();
1574
1575 if (!(ldt_selector & ~3))
1576 return 0;
1577
1578 table_base = segment_base(ldt_selector);
1579 }
1580 d = (struct desc_struct *)(table_base + (selector & ~7));
1581 v = get_desc_base(d);
1582#ifdef CONFIG_X86_64
1583 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1584 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1585#endif
1586 return v;
1587}
1588
1589static inline unsigned long kvm_read_tr_base(void)
1590{
1591 u16 tr;
1592 asm("str %0" : "=g"(tr));
1593 return segment_base(tr);
1594}
1595
04d2cc77 1596static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1597{
04d2cc77 1598 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1599 int i;
04d2cc77 1600
a2fa3e9f 1601 if (vmx->host_state.loaded)
33ed6329
AK		 1602 return;
1603
a2fa3e9f 1604 vmx->host_state.loaded = 1;
33ed6329
AK		 1605 /*
1606 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1607 * allow segment selectors with cpl > 0 or ti == 1.
1608 */
d6e88aec 1609 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1610 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1611 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1612 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1613 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1614 vmx->host_state.fs_reload_needed = 0;
1615 } else {
33ed6329 1616 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1617 vmx->host_state.fs_reload_needed = 1;
33ed6329 1618 }
9581d442 1619 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1620 if (!(vmx->host_state.gs_sel & 7))
1621 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1622 else {
1623 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1624 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1625 }
1626
b2da15ac
AK		 1627#ifdef CONFIG_X86_64
1628 savesegment(ds, vmx->host_state.ds_sel);
1629 savesegment(es, vmx->host_state.es_sel);
1630#endif
1631
33ed6329
AK		 1632#ifdef CONFIG_X86_64
1633 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1634 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1635#else
a2fa3e9f
GH		 1636 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1637 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1638#endif
707c0874
AK		 1639
1640#ifdef CONFIG_X86_64
c8770e7b
AK		 1641 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1642 if (is_long_mode(&vmx->vcpu))
44ea2b17 1643 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1644#endif
26bb0981
AK		 1645 for (i = 0; i < vmx->save_nmsrs; ++i)
1646 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1647 vmx->guest_msrs[i].data,
1648 vmx->guest_msrs[i].mask);
33ed6329
AK		 1649}
1650
a9b21b62 1651static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1652{
a2fa3e9f 1653 if (!vmx->host_state.loaded)
33ed6329
AK		 1654 return;
1655
e1beb1d3 1656 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1657 vmx->host_state.loaded = 0;
c8770e7b
AK		 1658#ifdef CONFIG_X86_64
1659 if (is_long_mode(&vmx->vcpu))
1660 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1661#endif
152d3f2f 1662 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1663 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1664#ifdef CONFIG_X86_64
9581d442 1665 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1666#else
1667 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1668#endif
33ed6329 1669 }
0a77fe4c
AK		 1670 if (vmx->host_state.fs_reload_needed)
1671 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1672#ifdef CONFIG_X86_64
1673 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1674 loadsegment(ds, vmx->host_state.ds_sel);
1675 loadsegment(es, vmx->host_state.es_sel);
1676 }
b2da15ac 1677#endif
152d3f2f 1678 reload_tss();
44ea2b17 1679#ifdef CONFIG_X86_64
c8770e7b 1680 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1681#endif
b1a74bf8
SS		 1682 /*
1683 * If the FPU is not active (through the host task or
1684 * the guest vcpu), then restore the cr0.TS bit.
1685 */
1686 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1687 stts();
3444d7da 1688 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1689}
1690
a9b21b62
AK		 1691static void vmx_load_host_state(struct vcpu_vmx *vmx)
1692{
1693 preempt_disable();
1694 __vmx_load_host_state(vmx);
1695 preempt_enable();
1696}
1697
6aa8b732
AK		 1698/*
1699 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1700 * vcpu mutex is already taken.
1701 */
15ad7146 1702static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1703{
a2fa3e9f 1704 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1705 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1706
4610c9cc
DX		 1707 if (!vmm_exclusive)
1708 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1709 else if (vmx->loaded_vmcs->cpu != cpu)
1710 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1711
d462b819
NHE		 1712 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1713 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1714 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1715 }
1716
d462b819 1717 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1718 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1719 unsigned long sysenter_esp;
1720
a8eeb04a 1721 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1722 local_irq_disable();
8f536b76 1723 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1724
1725 /*
1726 * Read loaded_vmcs->cpu should be before fetching
1727 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1728 * See the comments in __loaded_vmcs_clear().
1729 */
1730 smp_rmb();
1731
d462b819
NHE		 1732 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1733 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1734 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1735 local_irq_enable();
1736
6aa8b732
AK		 1737 /*
1738 * Linux uses per-cpu TSS and GDT, so set these when switching
1739 * processors.
1740 */
d6e88aec 1741 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1742 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1743
1744 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1745 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1746 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1747 }
6aa8b732
AK		 1748}
1749
1750static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1751{
a9b21b62 1752 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1753 if (!vmm_exclusive) {
d462b819
NHE		 1754 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1755 vcpu->cpu = -1;
4610c9cc
DX		 1756 kvm_cpu_vmxoff();
1757 }
6aa8b732
AK		 1758}
1759
5fd86fcf
AK		 1760static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1761{
81231c69
AK		 1762 ulong cr0;
1763
5fd86fcf
AK		 1764 if (vcpu->fpu_active)
1765 return;
1766 vcpu->fpu_active = 1;
81231c69
AK		 1767 cr0 = vmcs_readl(GUEST_CR0);
1768 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1769 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1770 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1771 update_exception_bitmap(vcpu);
edcafe3c 1772 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1773 if (is_guest_mode(vcpu))
1774 vcpu->arch.cr0_guest_owned_bits &=
1775 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1776 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1777}
1778
edcafe3c
AK		 1779static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1780
fe3ef05c
NHE		 1781/*
1782 * Return the cr0 value that a nested guest would read. This is a combination
1783 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1784 * its hypervisor (cr0_read_shadow).
1785 */
1786static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1787{
1788 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1789 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1790}
1791static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1792{
1793 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1794 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1795}
1796
5fd86fcf
AK		 1797static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1798{
36cf24e0
NHE		 1799 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1800 * set this *before* calling this function.
1801 */
edcafe3c 1802 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1803 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1804 update_exception_bitmap(vcpu);
edcafe3c
AK		 1805 vcpu->arch.cr0_guest_owned_bits = 0;
1806 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1807 if (is_guest_mode(vcpu)) {
1808 /*
1809 * L1's specified read shadow might not contain the TS bit,
1810 * so now that we turned on shadowing of this bit, we need to
1811 * set this bit of the shadow. Like in nested_vmx_run we need
1812 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1813 * up-to-date here because we just decached cr0.TS (and we'll
1814 * only update vmcs12->guest_cr0 on nested exit).
1815 */
1816 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1817 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1818 (vcpu->arch.cr0 & X86_CR0_TS);
1819 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1820 } else
1821 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1822}
1823
6aa8b732
AK		 1824static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1825{
78ac8b47 1826 unsigned long rflags, save_rflags;
345dcaa8 1827
6de12732
AK		 1828 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1829 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1830 rflags = vmcs_readl(GUEST_RFLAGS);
1831 if (to_vmx(vcpu)->rmode.vm86_active) {
1832 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1833 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1834 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1835 }
1836 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1837 }
6de12732 1838 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1839}
1840
1841static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1842{
6de12732
AK		 1843 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1844 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1845 if (to_vmx(vcpu)->rmode.vm86_active) {
1846 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1847 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1848 }
6aa8b732
AK		 1849 vmcs_writel(GUEST_RFLAGS, rflags);
1850}
1851
2809f5d2
GC		 1852static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1853{
1854 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1855 int ret = 0;
1856
1857 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1858 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1859 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1860 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1861
1862 return ret & mask;
1863}
1864
1865static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1866{
1867 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1868 u32 interruptibility = interruptibility_old;
1869
1870 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1871
48005f64 1872 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1873 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1874 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1875 interruptibility |= GUEST_INTR_STATE_STI;
1876
1877 if ((interruptibility != interruptibility_old))
1878 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1879}
1880
6aa8b732
AK		 1881static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1882{
1883 unsigned long rip;
6aa8b732 1884
5fdbf976 1885 rip = kvm_rip_read(vcpu);
6aa8b732 1886 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1887 kvm_rip_write(vcpu, rip);
6aa8b732 1888
2809f5d2
GC		 1889 /* skipping an emulated instruction also counts */
1890 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1891}
1892
0b6ac343
NHE		 1893/*
1894 * KVM wants to inject page-faults which it got to the guest. This function
1895 * checks whether in a nested guest, we need to inject them to L1 or L2.
1896 * This function assumes it is called with the exit reason in vmcs02 being
1897 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1898 * is running).
1899 */
1900static int nested_pf_handled(struct kvm_vcpu *vcpu)
1901{
1902 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1903
1904 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1905 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1906 return 0;
1907
1908 nested_vmx_vmexit(vcpu);
1909 return 1;
1910}
1911
298101da 1912static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1913 bool has_error_code, u32 error_code,
1914 bool reinject)
298101da 1915{
77ab6db0 1916 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1917 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1918
0b6ac343 1919 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
5a2892ce 1920 !vmx->nested.nested_run_pending && nested_pf_handled(vcpu))
0b6ac343
NHE		 1921 return;
1922
8ab2d2e2 1923 if (has_error_code) {
77ab6db0 1924 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1925 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1926 }
77ab6db0 1927
7ffd92c5 1928 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1929 int inc_eip = 0;
1930 if (kvm_exception_is_soft(nr))
1931 inc_eip = vcpu->arch.event_exit_inst_len;
1932 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1933 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1934 return;
1935 }
1936
66fd3f7f
GN		 1937 if (kvm_exception_is_soft(nr)) {
1938 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1939 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1940 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1941 } else
1942 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1943
1944 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1945}
1946
4e47c7a6
SY		 1947static bool vmx_rdtscp_supported(void)
1948{
1949 return cpu_has_vmx_rdtscp();
1950}
1951
ad756a16
MJ		 1952static bool vmx_invpcid_supported(void)
1953{
1954 return cpu_has_vmx_invpcid() && enable_ept;
1955}
1956
a75beee6
ED		 1957/*
1958 * Swap MSR entry in host/guest MSR entry array.
1959 */
8b9cf98c 1960static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1961{
26bb0981 1962 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1963
1964 tmp = vmx->guest_msrs[to];
1965 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1966 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1967}
1968
8d14695f
YZ		 1969static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1970{
1971 unsigned long *msr_bitmap;
1972
1973 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1974 if (is_long_mode(vcpu))
1975 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1976 else
1977 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1978 } else {
1979 if (is_long_mode(vcpu))
1980 msr_bitmap = vmx_msr_bitmap_longmode;
1981 else
1982 msr_bitmap = vmx_msr_bitmap_legacy;
1983 }
1984
1985 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1986}
1987
e38aea3e
AK		 1988/*
1989 * Set up the vmcs to automatically save and restore system
1990 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1991 * mode, as fiddling with msrs is very expensive.
1992 */
8b9cf98c 1993static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1994{
26bb0981 1995 int save_nmsrs, index;
e38aea3e 1996
a75beee6
ED		 1997 save_nmsrs = 0;
1998#ifdef CONFIG_X86_64
8b9cf98c 1999 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 2000 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 2001 if (index >= 0)
8b9cf98c
RR		 2002 move_msr_up(vmx, index, save_nmsrs++);
2003 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 2004 if (index >= 0)
8b9cf98c
RR		 2005 move_msr_up(vmx, index, save_nmsrs++);
2006 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 2007 if (index >= 0)
8b9cf98c 2008 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 2009 index = __find_msr_index(vmx, MSR_TSC_AUX);
2010 if (index >= 0 && vmx->rdtscp_enabled)
2011 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 2012 /*
8c06585d 2013 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 2014 * if efer.sce is enabled.
2015 */
8c06585d 2016 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 2017 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 2018 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 2019 }
2020#endif
92c0d900
AK		 2021 index = __find_msr_index(vmx, MSR_EFER);
2022 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 2023 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 2024
26bb0981 2025 vmx->save_nmsrs = save_nmsrs;
5897297b 2026
8d14695f
YZ		 2027 if (cpu_has_vmx_msr_bitmap())
2028 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 2029}
2030
6aa8b732
AK		 2031/*
2032 * reads and returns guest's timestamp counter "register"
2033 * guest_tsc = host_tsc + tsc_offset -- 21.3
2034 */
2035static u64 guest_read_tsc(void)
2036{
2037 u64 host_tsc, tsc_offset;
2038
2039 rdtscll(host_tsc);
2040 tsc_offset = vmcs_read64(TSC_OFFSET);
2041 return host_tsc + tsc_offset;
2042}
2043
d5c1785d
NHE		 2044/*
2045 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2046 * counter, even if a nested guest (L2) is currently running.
2047 */
886b470c 2048u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 2049{
886b470c 2050 u64 tsc_offset;
d5c1785d 2051
d5c1785d
NHE		 2052 tsc_offset = is_guest_mode(vcpu) ?
2053 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2054 vmcs_read64(TSC_OFFSET);
2055 return host_tsc + tsc_offset;
2056}
2057
4051b188 2058/*
cc578287
ZA		 2059 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2060 * software catchup for faster rates on slower CPUs.
4051b188 2061 */
cc578287 2062static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 2063{
cc578287
ZA		 2064 if (!scale)
2065 return;
2066
2067 if (user_tsc_khz > tsc_khz) {
2068 vcpu->arch.tsc_catchup = 1;
2069 vcpu->arch.tsc_always_catchup = 1;
2070 } else
2071 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 2072}
2073
ba904635
WA		 2074static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2075{
2076 return vmcs_read64(TSC_OFFSET);
2077}
2078
6aa8b732 2079/*
99e3e30a 2080 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 2081 */
99e3e30a 2082static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 2083{
27fc51b2 2084 if (is_guest_mode(vcpu)) {
7991825b 2085 /*
27fc51b2
NHE		 2086 * We're here if L1 chose not to trap WRMSR to TSC. According
2087 * to the spec, this should set L1's TSC; The offset that L1
2088 * set for L2 remains unchanged, and still needs to be added
2089 * to the newly set TSC to get L2's TSC.
7991825b 2090 */
27fc51b2
NHE		 2091 struct vmcs12 *vmcs12;
2092 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2093 /* recalculate vmcs02.TSC_OFFSET: */
2094 vmcs12 = get_vmcs12(vcpu);
2095 vmcs_write64(TSC_OFFSET, offset +
2096 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2097 vmcs12->tsc_offset : 0));
2098 } else {
2099 vmcs_write64(TSC_OFFSET, offset);
2100 }
6aa8b732
AK		 2101}
2102
f1e2b260 2103static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 2104{
2105 u64 offset = vmcs_read64(TSC_OFFSET);
2106 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 2107 if (is_guest_mode(vcpu)) {
2108 /* Even when running L2, the adjustment needs to apply to L1 */
2109 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2110 }
e48672fa
ZA		 2111}
2112
857e4099
JR		 2113static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
2114{
2115 return target_tsc - native_read_tsc();
2116}
2117
801d3424
NHE		 2118static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2119{
2120 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2121 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2122}
2123
2124/*
2125 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2126 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2127 * all guests if the "nested" module option is off, and can also be disabled
2128 * for a single guest by disabling its VMX cpuid bit.
2129 */
2130static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2131{
2132 return nested && guest_cpuid_has_vmx(vcpu);
2133}
2134
b87a51ae
NHE		 2135/*
2136 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2137 * returned for the various VMX controls MSRs when nested VMX is enabled.
2138 * The same values should also be used to verify that vmcs12 control fields are
2139 * valid during nested entry from L1 to L2.
2140 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2141 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2142 * bit in the high half is on if the corresponding bit in the control field
2143 * may be on. See also vmx_control_verify().
2144 * TODO: allow these variables to be modified (downgraded) by module options
2145 * or other means.
2146 */
2147static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2148static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2149static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2150static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2151static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2152static u32 nested_vmx_misc_low, nested_vmx_misc_high;
b87a51ae
NHE		 2153static __init void nested_vmx_setup_ctls_msrs(void)
2154{
2155 /*
2156 * Note that as a general rule, the high half of the MSRs (bits in
2157 * the control fields which may be 1) should be initialized by the
2158 * intersection of the underlying hardware's MSR (i.e., features which
2159 * can be supported) and the list of features we want to expose -
2160 * because they are known to be properly supported in our code.
2161 * Also, usually, the low half of the MSRs (bits which must be 1) can
2162 * be set to 0, meaning that L1 may turn off any of these bits. The
2163 * reason is that if one of these bits is necessary, it will appear
2164 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2165 * fields of vmcs01 and vmcs02, will turn these bits off - and
2166 * nested_vmx_exit_handled() will not pass related exits to L1.
2167 * These rules have exceptions below.
2168 */
2169
2170 /* pin-based controls */
eabeaacc
JK		 2171 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2172 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2173 /*
2174 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2175 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2176 */
eabeaacc
JK		 2177 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2178 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2179 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2180 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2181 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2182
33fb20c3
JK		 2183 /*
2184 * Exit controls
2185 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2186 * 17 must be 1.
2187 */
2188 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2189 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2190#ifdef CONFIG_X86_64
2191 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2192#else
2193 nested_vmx_exit_ctls_high = 0;
2194#endif
33fb20c3 2195 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2196
2197 /* entry controls */
2198 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2199 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2200 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2201 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2202 nested_vmx_entry_ctls_high &=
2203 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
33fb20c3 2204 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2205
2206 /* cpu-based controls */
2207 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2208 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2209 nested_vmx_procbased_ctls_low = 0;
2210 nested_vmx_procbased_ctls_high &=
2211 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2212 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2213 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2214 CPU_BASED_CR3_STORE_EXITING |
2215#ifdef CONFIG_X86_64
2216 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2217#endif
2218 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2219 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2220 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2221 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2222 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2223 /*
2224 * We can allow some features even when not supported by the
2225 * hardware. For example, L1 can specify an MSR bitmap - and we
2226 * can use it to avoid exits to L1 - even when L0 runs L2
2227 * without MSR bitmaps.
2228 */
2229 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2230
2231 /* secondary cpu-based controls */
2232 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2233 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2234 nested_vmx_secondary_ctls_low = 0;
2235 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2236 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2237 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2
JK		 2238
2239 /* miscellaneous data */
2240 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2241 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2242 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2243 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2244}
2245
2246static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2247{
2248 /*
2249 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2250 */
2251 return ((control & high) | low) == control;
2252}
2253
2254static inline u64 vmx_control_msr(u32 low, u32 high)
2255{
2256 return low | ((u64)high << 32);
2257}
2258
2259/*
2260 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2261 * also let it use VMX-specific MSRs.
2262 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2263 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2264 * like all other MSRs).
2265 */
2266static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2267{
2268 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2269 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2270 /*
2271 * According to the spec, processors which do not support VMX
2272 * should throw a #GP(0) when VMX capability MSRs are read.
2273 */
2274 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2275 return 1;
2276 }
2277
2278 switch (msr_index) {
2279 case MSR_IA32_FEATURE_CONTROL:
2280 *pdata = 0;
2281 break;
2282 case MSR_IA32_VMX_BASIC:
2283 /*
2284 * This MSR reports some information about VMX support. We
2285 * should return information about the VMX we emulate for the
2286 * guest, and the VMCS structure we give it - not about the
2287 * VMX support of the underlying hardware.
2288 */
2289 *pdata = VMCS12_REVISION |
2290 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2291 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2292 break;
2293 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2294 case MSR_IA32_VMX_PINBASED_CTLS:
2295 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2296 nested_vmx_pinbased_ctls_high);
2297 break;
2298 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2299 case MSR_IA32_VMX_PROCBASED_CTLS:
2300 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2301 nested_vmx_procbased_ctls_high);
2302 break;
2303 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2304 case MSR_IA32_VMX_EXIT_CTLS:
2305 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2306 nested_vmx_exit_ctls_high);
2307 break;
2308 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2309 case MSR_IA32_VMX_ENTRY_CTLS:
2310 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2311 nested_vmx_entry_ctls_high);
2312 break;
2313 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2314 *pdata = vmx_control_msr(nested_vmx_misc_low,
2315 nested_vmx_misc_high);
b87a51ae
NHE		 2316 break;
2317 /*
2318 * These MSRs specify bits which the guest must keep fixed (on or off)
2319 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2320 * We picked the standard core2 setting.
2321 */
2322#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2323#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2324 case MSR_IA32_VMX_CR0_FIXED0:
2325 *pdata = VMXON_CR0_ALWAYSON;
2326 break;
2327 case MSR_IA32_VMX_CR0_FIXED1:
2328 *pdata = -1ULL;
2329 break;
2330 case MSR_IA32_VMX_CR4_FIXED0:
2331 *pdata = VMXON_CR4_ALWAYSON;
2332 break;
2333 case MSR_IA32_VMX_CR4_FIXED1:
2334 *pdata = -1ULL;
2335 break;
2336 case MSR_IA32_VMX_VMCS_ENUM:
2337 *pdata = 0x1f;
2338 break;
2339 case MSR_IA32_VMX_PROCBASED_CTLS2:
2340 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2341 nested_vmx_secondary_ctls_high);
2342 break;
2343 case MSR_IA32_VMX_EPT_VPID_CAP:
2344 /* Currently, no nested ept or nested vpid */
2345 *pdata = 0;
2346 break;
2347 default:
2348 return 0;
2349 }
2350
2351 return 1;
2352}
2353
2354static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2355{
2356 if (!nested_vmx_allowed(vcpu))
2357 return 0;
2358
2359 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2360 /* TODO: the right thing. */
2361 return 1;
2362 /*
2363 * No need to treat VMX capability MSRs specially: If we don't handle
2364 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2365 */
2366 return 0;
2367}
2368
6aa8b732
AK		 2369/*
2370 * Reads an msr value (of 'msr_index') into 'pdata'.
2371 * Returns 0 on success, non-0 otherwise.
2372 * Assumes vcpu_load() was already called.
2373 */
2374static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2375{
2376 u64 data;
26bb0981 2377 struct shared_msr_entry *msr;
6aa8b732
AK		 2378
2379 if (!pdata) {
2380 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2381 return -EINVAL;
2382 }
2383
2384 switch (msr_index) {
05b3e0c2 2385#ifdef CONFIG_X86_64
6aa8b732
AK		 2386 case MSR_FS_BASE:
2387 data = vmcs_readl(GUEST_FS_BASE);
2388 break;
2389 case MSR_GS_BASE:
2390 data = vmcs_readl(GUEST_GS_BASE);
2391 break;
44ea2b17
AK		 2392 case MSR_KERNEL_GS_BASE:
2393 vmx_load_host_state(to_vmx(vcpu));
2394 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2395 break;
26bb0981 2396#endif
6aa8b732 2397 case MSR_EFER:
3bab1f5d 2398 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2399 case MSR_IA32_TSC:
6aa8b732
AK		 2400 data = guest_read_tsc();
2401 break;
2402 case MSR_IA32_SYSENTER_CS:
2403 data = vmcs_read32(GUEST_SYSENTER_CS);
2404 break;
2405 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2406 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2407 break;
2408 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2409 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2410 break;
4e47c7a6
SY		 2411 case MSR_TSC_AUX:
2412 if (!to_vmx(vcpu)->rdtscp_enabled)
2413 return 1;
2414 /* Otherwise falls through */
6aa8b732 2415 default:
b87a51ae
NHE		 2416 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2417 return 0;
8b9cf98c 2418 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2419 if (msr) {
2420 data = msr->data;
2421 break;
6aa8b732 2422 }
3bab1f5d 2423 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2424 }
2425
2426 *pdata = data;
2427 return 0;
2428}
2429
2430/*
2431 * Writes msr value into into the appropriate "register".
2432 * Returns 0 on success, non-0 otherwise.
2433 * Assumes vcpu_load() was already called.
2434 */
8fe8ab46 2435static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2436{
a2fa3e9f 2437 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2438 struct shared_msr_entry *msr;
2cc51560 2439 int ret = 0;
8fe8ab46
WA		 2440 u32 msr_index = msr_info->index;
2441 u64 data = msr_info->data;
2cc51560 2442
6aa8b732 2443 switch (msr_index) {
3bab1f5d 2444 case MSR_EFER:
8fe8ab46 2445 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2446 break;
16175a79 2447#ifdef CONFIG_X86_64
6aa8b732 2448 case MSR_FS_BASE:
2fb92db1 2449 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2450 vmcs_writel(GUEST_FS_BASE, data);
2451 break;
2452 case MSR_GS_BASE:
2fb92db1 2453 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2454 vmcs_writel(GUEST_GS_BASE, data);
2455 break;
44ea2b17
AK		 2456 case MSR_KERNEL_GS_BASE:
2457 vmx_load_host_state(vmx);
2458 vmx->msr_guest_kernel_gs_base = data;
2459 break;
6aa8b732
AK		 2460#endif
2461 case MSR_IA32_SYSENTER_CS:
2462 vmcs_write32(GUEST_SYSENTER_CS, data);
2463 break;
2464 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2465 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2466 break;
2467 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2468 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2469 break;
af24a4e4 2470 case MSR_IA32_TSC:
8fe8ab46 2471 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2472 break;
468d472f
SY		 2473 case MSR_IA32_CR_PAT:
2474 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2475 vmcs_write64(GUEST_IA32_PAT, data);
2476 vcpu->arch.pat = data;
2477 break;
2478 }
8fe8ab46 2479 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2480 break;
ba904635
WA		 2481 case MSR_IA32_TSC_ADJUST:
2482 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2483 break;
2484 case MSR_TSC_AUX:
2485 if (!vmx->rdtscp_enabled)
2486 return 1;
2487 /* Check reserved bit, higher 32 bits should be zero */
2488 if ((data >> 32) != 0)
2489 return 1;
2490 /* Otherwise falls through */
6aa8b732 2491 default:
b87a51ae
NHE		 2492 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2493 break;
8b9cf98c 2494 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2495 if (msr) {
2496 msr->data = data;
2225fd56
AK		 2497 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2498 preempt_disable();
9ee73970
AK		 2499 kvm_set_shared_msr(msr->index, msr->data,
2500 msr->mask);
2225fd56
AK		 2501 preempt_enable();
2502 }
3bab1f5d 2503 break;
6aa8b732 2504 }
8fe8ab46 2505 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2506 }
2507
2cc51560 2508 return ret;
6aa8b732
AK		 2509}
2510
5fdbf976 2511static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2512{
5fdbf976
MT		 2513 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2514 switch (reg) {
2515 case VCPU_REGS_RSP:
2516 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2517 break;
2518 case VCPU_REGS_RIP:
2519 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2520 break;
6de4f3ad
AK		 2521 case VCPU_EXREG_PDPTR:
2522 if (enable_ept)
2523 ept_save_pdptrs(vcpu);
2524 break;
5fdbf976
MT		 2525 default:
2526 break;
2527 }
6aa8b732
AK		 2528}
2529
6aa8b732
AK		 2530static __init int cpu_has_kvm_support(void)
2531{
6210e37b 2532 return cpu_has_vmx();
6aa8b732
AK		 2533}
2534
2535static __init int vmx_disabled_by_bios(void)
2536{
2537 u64 msr;
2538
2539 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2540 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2541 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2542 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2543 && tboot_enabled())
2544 return 1;
23f3e991 2545 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2546 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2547 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2548 && !tboot_enabled()) {
2549 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2550 "activate TXT before enabling KVM\n");
cafd6659 2551 return 1;
f9335afe 2552 }
23f3e991
JC		 2553 /* launched w/o TXT and VMX disabled */
2554 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2555 && !tboot_enabled())
2556 return 1;
cafd6659
SW		 2557 }
2558
2559 return 0;
6aa8b732
AK		 2560}
2561
7725b894
DX		 2562static void kvm_cpu_vmxon(u64 addr)
2563{
2564 asm volatile (ASM_VMX_VMXON_RAX
2565 : : "a"(&addr), "m"(addr)
2566 : "memory", "cc");
2567}
2568
10474ae8 2569static int hardware_enable(void *garbage)
6aa8b732
AK		 2570{
2571 int cpu = raw_smp_processor_id();
2572 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2573 u64 old, test_bits;
6aa8b732 2574
10474ae8
AG		 2575 if (read_cr4() & X86_CR4_VMXE)
2576 return -EBUSY;
2577
d462b819 2578 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2579
2580 /*
2581 * Now we can enable the vmclear operation in kdump
2582 * since the loaded_vmcss_on_cpu list on this cpu
2583 * has been initialized.
2584 *
2585 * Though the cpu is not in VMX operation now, there
2586 * is no problem to enable the vmclear operation
2587 * for the loaded_vmcss_on_cpu list is empty!
2588 */
2589 crash_enable_local_vmclear(cpu);
2590
6aa8b732 2591 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2592
2593 test_bits = FEATURE_CONTROL_LOCKED;
2594 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2595 if (tboot_enabled())
2596 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2597
2598 if ((old & test_bits) != test_bits) {
6aa8b732 2599 /* enable and lock */
cafd6659
SW		 2600 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2601 }
66aee91a 2602 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2603
4610c9cc
DX		 2604 if (vmm_exclusive) {
2605 kvm_cpu_vmxon(phys_addr);
2606 ept_sync_global();
2607 }
10474ae8 2608
357d1226 2609 native_store_gdt(&__get_cpu_var(host_gdt));
3444d7da 2610
10474ae8 2611 return 0;
6aa8b732
AK		 2612}
2613
d462b819 2614static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2615{
2616 int cpu = raw_smp_processor_id();
d462b819 2617 struct loaded_vmcs *v, *n;
543e4243 2618
d462b819
NHE		 2619 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2620 loaded_vmcss_on_cpu_link)
2621 __loaded_vmcs_clear(v);
543e4243
AK		 2622}
2623
710ff4a8
EH		 2624
2625/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2626 * tricks.
2627 */
2628static void kvm_cpu_vmxoff(void)
6aa8b732 2629{
4ecac3fd 2630 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2631}
2632
710ff4a8
EH		 2633static void hardware_disable(void *garbage)
2634{
4610c9cc 2635 if (vmm_exclusive) {
d462b819 2636 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2637 kvm_cpu_vmxoff();
2638 }
7725b894 2639 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2640}
2641
1c3d14fe 2642static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2643 u32 msr, u32 *result)
1c3d14fe
YS		 2644{
2645 u32 vmx_msr_low, vmx_msr_high;
2646 u32 ctl = ctl_min | ctl_opt;
2647
2648 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2649
2650 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2651 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2652
2653 /* Ensure minimum (required) set of control bits are supported. */
2654 if (ctl_min & ~ctl)
002c7f7c 2655 return -EIO;
1c3d14fe
YS		 2656
2657 *result = ctl;
2658 return 0;
2659}
2660
110312c8
AK		 2661static __init bool allow_1_setting(u32 msr, u32 ctl)
2662{
2663 u32 vmx_msr_low, vmx_msr_high;
2664
2665 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2666 return vmx_msr_high & ctl;
2667}
2668
002c7f7c 2669static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2670{
2671 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2672 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2673 u32 _pin_based_exec_control = 0;
2674 u32 _cpu_based_exec_control = 0;
f78e0e2e 2675 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2676 u32 _vmexit_control = 0;
2677 u32 _vmentry_control = 0;
2678
10166744 2679 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2680#ifdef CONFIG_X86_64
2681 CPU_BASED_CR8_LOAD_EXITING |
2682 CPU_BASED_CR8_STORE_EXITING |
2683#endif
d56f546d
SY		 2684 CPU_BASED_CR3_LOAD_EXITING |
2685 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2686 CPU_BASED_USE_IO_BITMAPS |
2687 CPU_BASED_MOV_DR_EXITING |
a7052897 2688 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2689 CPU_BASED_MWAIT_EXITING |
2690 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2691 CPU_BASED_INVLPG_EXITING |
2692 CPU_BASED_RDPMC_EXITING;
443381a8 2693
f78e0e2e 2694 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2695 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2696 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2697 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2698 &_cpu_based_exec_control) < 0)
002c7f7c 2699 return -EIO;
6e5d865c
YS		 2700#ifdef CONFIG_X86_64
2701 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2702 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2703 ~CPU_BASED_CR8_STORE_EXITING;
2704#endif
f78e0e2e 2705 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2706 min2 = 0;
2707 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2708 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2709 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2710 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2711 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2712 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2713 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2714 SECONDARY_EXEC_RDTSCP |
83d4c286 2715 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 2716 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58
AG		 2717 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2718 SECONDARY_EXEC_SHADOW_VMCS;
d56f546d
SY		 2719 if (adjust_vmx_controls(min2, opt2,
2720 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2721 &_cpu_based_2nd_exec_control) < 0)
2722 return -EIO;
2723 }
2724#ifndef CONFIG_X86_64
2725 if (!(_cpu_based_2nd_exec_control &
2726 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2727 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2728#endif
83d4c286
YZ		 2729
2730 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2731 _cpu_based_2nd_exec_control &= ~(
8d14695f 2732 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2733 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2734 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2735
d56f546d 2736 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2737 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2738 enabled */
5fff7d27
GN		 2739 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2740 CPU_BASED_CR3_STORE_EXITING |
2741 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2742 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2743 vmx_capability.ept, vmx_capability.vpid);
2744 }
1c3d14fe
YS		 2745
2746 min = 0;
2747#ifdef CONFIG_X86_64
2748 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2749#endif
a547c6db
YZ		 2750 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2751 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2752 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2753 &_vmexit_control) < 0)
002c7f7c 2754 return -EIO;
1c3d14fe 2755
01e439be
YZ		 2756 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2757 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
2758 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2759 &_pin_based_exec_control) < 0)
2760 return -EIO;
2761
2762 if (!(_cpu_based_2nd_exec_control &
2763 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
2764 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
2765 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2766
468d472f
SY		 2767 min = 0;
2768 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2769 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2770 &_vmentry_control) < 0)
002c7f7c 2771 return -EIO;
6aa8b732 2772
c68876fd 2773 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2774
2775 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2776 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2777 return -EIO;
1c3d14fe
YS		 2778
2779#ifdef CONFIG_X86_64
2780 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2781 if (vmx_msr_high & (1u<<16))
002c7f7c 2782 return -EIO;
1c3d14fe
YS		 2783#endif
2784
2785 /* Require Write-Back (WB) memory type for VMCS accesses. */
2786 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2787 return -EIO;
1c3d14fe 2788
002c7f7c
YS		 2789 vmcs_conf->size = vmx_msr_high & 0x1fff;
2790 vmcs_conf->order = get_order(vmcs_config.size);
2791 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2792
002c7f7c
YS		 2793 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2794 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2795 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2796 vmcs_conf->vmexit_ctrl = _vmexit_control;
2797 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2798
110312c8
AK		 2799 cpu_has_load_ia32_efer =
2800 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2801 VM_ENTRY_LOAD_IA32_EFER)
2802 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2803 VM_EXIT_LOAD_IA32_EFER);
2804
8bf00a52
GN		 2805 cpu_has_load_perf_global_ctrl =
2806 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2807 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2808 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2809 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2810
2811 /*
2812 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2813 * but due to arrata below it can't be used. Workaround is to use
2814 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2815 *
2816 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2817 *
2818 * AAK155 (model 26)
2819 * AAP115 (model 30)
2820 * AAT100 (model 37)
2821 * BC86,AAY89,BD102 (model 44)
2822 * BA97 (model 46)
2823 *
2824 */
2825 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2826 switch (boot_cpu_data.x86_model) {
2827 case 26:
2828 case 30:
2829 case 37:
2830 case 44:
2831 case 46:
2832 cpu_has_load_perf_global_ctrl = false;
2833 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2834 "does not work properly. Using workaround\n");
2835 break;
2836 default:
2837 break;
2838 }
2839 }
2840
1c3d14fe 2841 return 0;
c68876fd 2842}
6aa8b732
AK		 2843
2844static struct vmcs *alloc_vmcs_cpu(int cpu)
2845{
2846 int node = cpu_to_node(cpu);
2847 struct page *pages;
2848 struct vmcs *vmcs;
2849
6484eb3e 2850 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2851 if (!pages)
2852 return NULL;
2853 vmcs = page_address(pages);
1c3d14fe
YS		 2854 memset(vmcs, 0, vmcs_config.size);
2855 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2856 return vmcs;
2857}
2858
2859static struct vmcs *alloc_vmcs(void)
2860{
d3b2c338 2861 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2862}
2863
2864static void free_vmcs(struct vmcs *vmcs)
2865{
1c3d14fe 2866 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2867}
2868
d462b819
NHE		 2869/*
2870 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2871 */
2872static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2873{
2874 if (!loaded_vmcs->vmcs)
2875 return;
2876 loaded_vmcs_clear(loaded_vmcs);
2877 free_vmcs(loaded_vmcs->vmcs);
2878 loaded_vmcs->vmcs = NULL;
2879}
2880
39959588 2881static void free_kvm_area(void)
6aa8b732
AK		 2882{
2883 int cpu;
2884
3230bb47 2885 for_each_possible_cpu(cpu) {
6aa8b732 2886 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2887 per_cpu(vmxarea, cpu) = NULL;
2888 }
6aa8b732
AK		 2889}
2890
6aa8b732
AK		 2891static __init int alloc_kvm_area(void)
2892{
2893 int cpu;
2894
3230bb47 2895 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2896 struct vmcs *vmcs;
2897
2898 vmcs = alloc_vmcs_cpu(cpu);
2899 if (!vmcs) {
2900 free_kvm_area();
2901 return -ENOMEM;
2902 }
2903
2904 per_cpu(vmxarea, cpu) = vmcs;
2905 }
2906 return 0;
2907}
2908
2909static __init int hardware_setup(void)
2910{
002c7f7c
YS		 2911 if (setup_vmcs_config(&vmcs_config) < 0)
2912 return -EIO;
50a37eb4
JR		 2913
2914 if (boot_cpu_has(X86_FEATURE_NX))
2915 kvm_enable_efer_bits(EFER_NX);
2916
93ba03c2
SY		 2917 if (!cpu_has_vmx_vpid())
2918 enable_vpid = 0;
abc4fc58
AG		 2919 if (!cpu_has_vmx_shadow_vmcs())
2920 enable_shadow_vmcs = 0;
93ba03c2 2921
4bc9b982
SY		 2922 if (!cpu_has_vmx_ept() ||
2923 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2924 enable_ept = 0;
3a624e29 2925 enable_unrestricted_guest = 0;
83c3a331 2926 enable_ept_ad_bits = 0;
3a624e29
NK		 2927 }
2928
83c3a331
XH		 2929 if (!cpu_has_vmx_ept_ad_bits())
2930 enable_ept_ad_bits = 0;
2931
3a624e29
NK		 2932 if (!cpu_has_vmx_unrestricted_guest())
2933 enable_unrestricted_guest = 0;
93ba03c2
SY		 2934
2935 if (!cpu_has_vmx_flexpriority())
2936 flexpriority_enabled = 0;
2937
95ba8273
GN		 2938 if (!cpu_has_vmx_tpr_shadow())
2939 kvm_x86_ops->update_cr8_intercept = NULL;
2940
54dee993
MT		 2941 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2942 kvm_disable_largepages();
2943
4b8d54f9
ZE		 2944 if (!cpu_has_vmx_ple())
2945 ple_gap = 0;
2946
01e439be
YZ		 2947 if (!cpu_has_vmx_apicv())
2948 enable_apicv = 0;
c7c9c56c 2949
01e439be 2950 if (enable_apicv)
c7c9c56c 2951 kvm_x86_ops->update_cr8_intercept = NULL;
a20ed54d 2952 else {
c7c9c56c 2953 kvm_x86_ops->hwapic_irr_update = NULL;
a20ed54d
YZ		 2954 kvm_x86_ops->deliver_posted_interrupt = NULL;
2955 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
2956 }
83d4c286 2957
b87a51ae
NHE		 2958 if (nested)
2959 nested_vmx_setup_ctls_msrs();
2960
6aa8b732
AK		 2961 return alloc_kvm_area();
2962}
2963
2964static __exit void hardware_unsetup(void)
2965{
2966 free_kvm_area();
2967}
2968
14168786
GN		 2969static bool emulation_required(struct kvm_vcpu *vcpu)
2970{
2971 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2972}
2973
91b0aa2c 2974static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2975 struct kvm_segment *save)
6aa8b732 2976{
d99e4152
GN		 2977 if (!emulate_invalid_guest_state) {
2978 /*
2979 * CS and SS RPL should be equal during guest entry according
2980 * to VMX spec, but in reality it is not always so. Since vcpu
2981 * is in the middle of the transition from real mode to
2982 * protected mode it is safe to assume that RPL 0 is a good
2983 * default value.
2984 */
2985 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2986 save->selector &= ~SELECTOR_RPL_MASK;
2987 save->dpl = save->selector & SELECTOR_RPL_MASK;
2988 save->s = 1;
6aa8b732 2989 }
d99e4152 2990 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2991}
2992
2993static void enter_pmode(struct kvm_vcpu *vcpu)
2994{
2995 unsigned long flags;
a89a8fb9 2996 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2997
d99e4152
GN		 2998 /*
2999 * Update real mode segment cache. It may be not up-to-date if sement
3000 * register was written while vcpu was in a guest mode.
3001 */
3002 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3003 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3004 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3005 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3006 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3007 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3008
7ffd92c5 3009 vmx->rmode.vm86_active = 0;
6aa8b732 3010
2fb92db1
AK		 3011 vmx_segment_cache_clear(vmx);
3012
f5f7b2fe 3013 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 3014
3015 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 3016 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3017 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 3018 vmcs_writel(GUEST_RFLAGS, flags);
3019
66aee91a
RR		 3020 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3021 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 3022
3023 update_exception_bitmap(vcpu);
3024
91b0aa2c
GN		 3025 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3026 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3027 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3028 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3029 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3030 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 3031
3032 /* CPL is always 0 when CPU enters protected mode */
3033 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3034 vmx->cpl = 0;
6aa8b732
AK		 3035}
3036
f5f7b2fe 3037static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 3038{
772e0318 3039 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 3040 struct kvm_segment var = *save;
3041
3042 var.dpl = 0x3;
3043 if (seg == VCPU_SREG_CS)
3044 var.type = 0x3;
3045
3046 if (!emulate_invalid_guest_state) {
3047 var.selector = var.base >> 4;
3048 var.base = var.base & 0xffff0;
3049 var.limit = 0xffff;
3050 var.g = 0;
3051 var.db = 0;
3052 var.present = 1;
3053 var.s = 1;
3054 var.l = 0;
3055 var.unusable = 0;
3056 var.type = 0x3;
3057 var.avl = 0;
3058 if (save->base & 0xf)
3059 printk_once(KERN_WARNING "kvm: segment base is not "
3060 "paragraph aligned when entering "
3061 "protected mode (seg=%d)", seg);
3062 }
6aa8b732 3063
d99e4152
GN		 3064 vmcs_write16(sf->selector, var.selector);
3065 vmcs_write32(sf->base, var.base);
3066 vmcs_write32(sf->limit, var.limit);
3067 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 3068}
3069
3070static void enter_rmode(struct kvm_vcpu *vcpu)
3071{
3072 unsigned long flags;
a89a8fb9 3073 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 3074
f5f7b2fe
AK		 3075 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3076 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3077 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3078 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3079 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 3080 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3081 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 3082
7ffd92c5 3083 vmx->rmode.vm86_active = 1;
6aa8b732 3084
776e58ea
GN		 3085 /*
3086 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 3087 * vcpu. Warn the user that an update is overdue.
776e58ea 3088 */
4918c6ca 3089 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 3090 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3091 "called before entering vcpu\n");
776e58ea 3092
2fb92db1
AK		 3093 vmx_segment_cache_clear(vmx);
3094
4918c6ca 3095 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 3096 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 3097 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3098
3099 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 3100 vmx->rmode.save_rflags = flags;
6aa8b732 3101
053de044 3102 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 3103
3104 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 3105 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 3106 update_exception_bitmap(vcpu);
3107
d99e4152
GN		 3108 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3109 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3110 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3111 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3112 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3113 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 3114
8668a3c4 3115 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 3116}
3117
401d10de
AS		 3118static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3119{
3120 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 3121 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3122
3123 if (!msr)
3124 return;
401d10de 3125
44ea2b17
AK		 3126 /*
3127 * Force kernel_gs_base reloading before EFER changes, as control
3128 * of this msr depends on is_long_mode().
3129 */
3130 vmx_load_host_state(to_vmx(vcpu));
f6801dff 3131 vcpu->arch.efer = efer;
401d10de
AS		 3132 if (efer & EFER_LMA) {
3133 vmcs_write32(VM_ENTRY_CONTROLS,
3134 vmcs_read32(VM_ENTRY_CONTROLS) |
3135 VM_ENTRY_IA32E_MODE);
3136 msr->data = efer;
3137 } else {
3138 vmcs_write32(VM_ENTRY_CONTROLS,
3139 vmcs_read32(VM_ENTRY_CONTROLS) &
3140 ~VM_ENTRY_IA32E_MODE);
3141
3142 msr->data = efer & ~EFER_LME;
3143 }
3144 setup_msrs(vmx);
3145}
3146
05b3e0c2 3147#ifdef CONFIG_X86_64
6aa8b732
AK		 3148
3149static void enter_lmode(struct kvm_vcpu *vcpu)
3150{
3151 u32 guest_tr_ar;
3152
2fb92db1
AK		 3153 vmx_segment_cache_clear(to_vmx(vcpu));
3154
6aa8b732
AK		 3155 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3156 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3157 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3158 __func__);
6aa8b732
AK		 3159 vmcs_write32(GUEST_TR_AR_BYTES,
3160 (guest_tr_ar & ~AR_TYPE_MASK)
3161 | AR_TYPE_BUSY_64_TSS);
3162 }
da38f438 3163 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3164}
3165
3166static void exit_lmode(struct kvm_vcpu *vcpu)
3167{
6aa8b732
AK		 3168 vmcs_write32(VM_ENTRY_CONTROLS,
3169 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3170 & ~VM_ENTRY_IA32E_MODE);
da38f438 3171 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3172}
3173
3174#endif
3175
2384d2b3
SY		 3176static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3177{
b9d762fa 3178 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3179 if (enable_ept) {
3180 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3181 return;
4e1096d2 3182 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3183 }
2384d2b3
SY		 3184}
3185
e8467fda
AK		 3186static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3187{
3188 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3189
3190 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3191 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3192}
3193
aff48baa
AK		 3194static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3195{
3196 if (enable_ept && is_paging(vcpu))
3197 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3198 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3199}
3200
25c4c276 3201static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3202{
fc78f519
AK		 3203 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3204
3205 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3206 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3207}
3208
1439442c
SY		 3209static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3210{
6de4f3ad
AK		 3211 if (!test_bit(VCPU_EXREG_PDPTR,
3212 (unsigned long *)&vcpu->arch.regs_dirty))
3213 return;
3214
1439442c 3215 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3216 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3217 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3218 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3219 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3220 }
3221}
3222
8f5d549f
AK		 3223static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3224{
3225 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3226 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3227 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3228 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3229 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3230 }
6de4f3ad
AK		 3231
3232 __set_bit(VCPU_EXREG_PDPTR,
3233 (unsigned long *)&vcpu->arch.regs_avail);
3234 __set_bit(VCPU_EXREG_PDPTR,
3235 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3236}
3237
5e1746d6 3238static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3239
3240static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3241 unsigned long cr0,
3242 struct kvm_vcpu *vcpu)
3243{
5233dd51
MT		 3244 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3245 vmx_decache_cr3(vcpu);
1439442c
SY		 3246 if (!(cr0 & X86_CR0_PG)) {
3247 /* From paging/starting to nonpaging */
3248 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3249 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3250 (CPU_BASED_CR3_LOAD_EXITING |
3251 CPU_BASED_CR3_STORE_EXITING));
3252 vcpu->arch.cr0 = cr0;
fc78f519 3253 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3254 } else if (!is_paging(vcpu)) {
3255 /* From nonpaging to paging */
3256 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3257 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3258 ~(CPU_BASED_CR3_LOAD_EXITING |
3259 CPU_BASED_CR3_STORE_EXITING));
3260 vcpu->arch.cr0 = cr0;
fc78f519 3261 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3262 }
95eb84a7
SY		 3263
3264 if (!(cr0 & X86_CR0_WP))
3265 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3266}
3267
6aa8b732
AK		 3268static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3269{
7ffd92c5 3270 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3271 unsigned long hw_cr0;
3272
5037878e 3273 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3274 if (enable_unrestricted_guest)
5037878e 3275 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3276 else {
5037878e 3277 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3278
218e763f
GN		 3279 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3280 enter_pmode(vcpu);
6aa8b732 3281
218e763f
GN		 3282 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3283 enter_rmode(vcpu);
3284 }
6aa8b732 3285
05b3e0c2 3286#ifdef CONFIG_X86_64
f6801dff 3287 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3288 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3289 enter_lmode(vcpu);
707d92fa 3290 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3291 exit_lmode(vcpu);
3292 }
3293#endif
3294
089d034e 3295 if (enable_ept)
1439442c
SY		 3296 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3297
02daab21 3298 if (!vcpu->fpu_active)
81231c69 3299 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3300
6aa8b732 3301 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3302 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3303 vcpu->arch.cr0 = cr0;
14168786
GN		 3304
3305 /* depends on vcpu->arch.cr0 to be set to a new value */
3306 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3307}
3308
1439442c
SY		 3309static u64 construct_eptp(unsigned long root_hpa)
3310{
3311 u64 eptp;
3312
3313 /* TODO write the value reading from MSR */
3314 eptp = VMX_EPT_DEFAULT_MT |
3315 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3316 if (enable_ept_ad_bits)
3317 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3318 eptp |= (root_hpa & PAGE_MASK);
3319
3320 return eptp;
3321}
3322
6aa8b732
AK		 3323static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3324{
1439442c
SY		 3325 unsigned long guest_cr3;
3326 u64 eptp;
3327
3328 guest_cr3 = cr3;
089d034e 3329 if (enable_ept) {
1439442c
SY		 3330 eptp = construct_eptp(cr3);
3331 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3332 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3333 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3334 ept_load_pdptrs(vcpu);
1439442c
SY		 3335 }
3336
2384d2b3 3337 vmx_flush_tlb(vcpu);
1439442c 3338 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3339}
3340
5e1746d6 3341static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3342{
7ffd92c5 3343 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3344 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3345
5e1746d6
NHE		 3346 if (cr4 & X86_CR4_VMXE) {
3347 /*
3348 * To use VMXON (and later other VMX instructions), a guest
3349 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3350 * So basically the check on whether to allow nested VMX
3351 * is here.
3352 */
3353 if (!nested_vmx_allowed(vcpu))
3354 return 1;
1a0d74e6
JK		 3355 }
3356 if (to_vmx(vcpu)->nested.vmxon &&
3357 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3358 return 1;
3359
ad312c7c 3360 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3361 if (enable_ept) {
3362 if (!is_paging(vcpu)) {
3363 hw_cr4 &= ~X86_CR4_PAE;
3364 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3365 /*
3366 * SMEP is disabled if CPU is in non-paging mode in
3367 * hardware. However KVM always uses paging mode to
3368 * emulate guest non-paging mode with TDP.
3369 * To emulate this behavior, SMEP needs to be manually
3370 * disabled when guest switches to non-paging mode.
3371 */
3372 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3373 } else if (!(cr4 & X86_CR4_PAE)) {
3374 hw_cr4 &= ~X86_CR4_PAE;
3375 }
3376 }
1439442c
SY		 3377
3378 vmcs_writel(CR4_READ_SHADOW, cr4);
3379 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3380 return 0;
6aa8b732
AK		 3381}
3382
6aa8b732
AK		 3383static void vmx_get_segment(struct kvm_vcpu *vcpu,
3384 struct kvm_segment *var, int seg)
3385{
a9179499 3386 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3387 u32 ar;
3388
c6ad1153 3389 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3390 *var = vmx->rmode.segs[seg];
a9179499 3391 if (seg == VCPU_SREG_TR
2fb92db1 3392 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3393 return;
1390a28b
AK		 3394 var->base = vmx_read_guest_seg_base(vmx, seg);
3395 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3396 return;
a9179499 3397 }
2fb92db1
AK		 3398 var->base = vmx_read_guest_seg_base(vmx, seg);
3399 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3400 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3401 ar = vmx_read_guest_seg_ar(vmx, seg);
6aa8b732
AK		 3402 var->type = ar & 15;
3403 var->s = (ar >> 4) & 1;
3404 var->dpl = (ar >> 5) & 3;
3405 var->present = (ar >> 7) & 1;
3406 var->avl = (ar >> 12) & 1;
3407 var->l = (ar >> 13) & 1;
3408 var->db = (ar >> 14) & 1;
3409 var->g = (ar >> 15) & 1;
3410 var->unusable = (ar >> 16) & 1;
3411}
3412
a9179499
AK		 3413static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3414{
a9179499
AK		 3415 struct kvm_segment s;
3416
3417 if (to_vmx(vcpu)->rmode.vm86_active) {
3418 vmx_get_segment(vcpu, &s, seg);
3419 return s.base;
3420 }
2fb92db1 3421 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3422}
3423
b09408d0 3424static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3425{
b09408d0
MT		 3426 struct vcpu_vmx *vmx = to_vmx(vcpu);
3427
3eeb3288 3428 if (!is_protmode(vcpu))
2e4d2653
IE		 3429 return 0;
3430
f4c63e5d
AK		 3431 if (!is_long_mode(vcpu)
3432 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3433 return 3;
3434
69c73028
AK		 3435 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3436 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3437 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3438 }
d881e6f6
AK		 3439
3440 return vmx->cpl;
69c73028
AK		 3441}
3442
3443
653e3108 3444static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3445{
6aa8b732
AK		 3446 u32 ar;
3447
f0495f9b 3448 if (var->unusable || !var->present)
6aa8b732
AK		 3449 ar = 1 << 16;
3450 else {
3451 ar = var->type & 15;
3452 ar |= (var->s & 1) << 4;
3453 ar |= (var->dpl & 3) << 5;
3454 ar |= (var->present & 1) << 7;
3455 ar |= (var->avl & 1) << 12;
3456 ar |= (var->l & 1) << 13;
3457 ar |= (var->db & 1) << 14;
3458 ar |= (var->g & 1) << 15;
3459 }
653e3108
AK		 3460
3461 return ar;
3462}
3463
3464static void vmx_set_segment(struct kvm_vcpu *vcpu,
3465 struct kvm_segment *var, int seg)
3466{
7ffd92c5 3467 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3468 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3469
2fb92db1 3470 vmx_segment_cache_clear(vmx);
2f143240
GN		 3471 if (seg == VCPU_SREG_CS)
3472 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3473
1ecd50a9
GN		 3474 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3475 vmx->rmode.segs[seg] = *var;
3476 if (seg == VCPU_SREG_TR)
3477 vmcs_write16(sf->selector, var->selector);
3478 else if (var->s)
3479 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3480 goto out;
653e3108 3481 }
1ecd50a9 3482
653e3108
AK		 3483 vmcs_writel(sf->base, var->base);
3484 vmcs_write32(sf->limit, var->limit);
3485 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3486
3487 /*
3488 * Fix the "Accessed" bit in AR field of segment registers for older
3489 * qemu binaries.
3490 * IA32 arch specifies that at the time of processor reset the
3491 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3492 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3493 * state vmexit when "unrestricted guest" mode is turned on.
3494 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3495 * tree. Newer qemu binaries with that qemu fix would not need this
3496 * kvm hack.
3497 */
3498 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3499 var->type |= 0x1; /* Accessed */
3a624e29 3500
f924d66d 3501 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3502
3503out:
14168786 3504 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3505}
3506
6aa8b732
AK		 3507static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3508{
2fb92db1 3509 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3510
3511 *db = (ar >> 14) & 1;
3512 *l = (ar >> 13) & 1;
3513}
3514
89a27f4d 3515static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3516{
89a27f4d
GN		 3517 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3518 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3519}
3520
89a27f4d 3521static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3522{
89a27f4d
GN		 3523 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3524 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3525}
3526
89a27f4d 3527static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3528{
89a27f4d
GN		 3529 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3530 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3531}
3532
89a27f4d 3533static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3534{
89a27f4d
GN		 3535 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3536 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3537}
3538
648dfaa7
MG		 3539static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3540{
3541 struct kvm_segment var;
3542 u32 ar;
3543
3544 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3545 var.dpl = 0x3;
0647f4aa
GN		 3546 if (seg == VCPU_SREG_CS)
3547 var.type = 0x3;
648dfaa7
MG		 3548 ar = vmx_segment_access_rights(&var);
3549
3550 if (var.base != (var.selector << 4))
3551 return false;
89efbed0 3552 if (var.limit != 0xffff)
648dfaa7 3553 return false;
07f42f5f 3554 if (ar != 0xf3)
648dfaa7
MG		 3555 return false;
3556
3557 return true;
3558}
3559
3560static bool code_segment_valid(struct kvm_vcpu *vcpu)
3561{
3562 struct kvm_segment cs;
3563 unsigned int cs_rpl;
3564
3565 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3566 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3567
1872a3f4
AK		 3568 if (cs.unusable)
3569 return false;
648dfaa7
MG		 3570 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3571 return false;
3572 if (!cs.s)
3573 return false;
1872a3f4 3574 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3575 if (cs.dpl > cs_rpl)
3576 return false;
1872a3f4 3577 } else {
648dfaa7
MG		 3578 if (cs.dpl != cs_rpl)
3579 return false;
3580 }
3581 if (!cs.present)
3582 return false;
3583
3584 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3585 return true;
3586}
3587
3588static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3589{
3590 struct kvm_segment ss;
3591 unsigned int ss_rpl;
3592
3593 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3594 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3595
1872a3f4
AK		 3596 if (ss.unusable)
3597 return true;
3598 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3599 return false;
3600 if (!ss.s)
3601 return false;
3602 if (ss.dpl != ss_rpl) /* DPL != RPL */
3603 return false;
3604 if (!ss.present)
3605 return false;
3606
3607 return true;
3608}
3609
3610static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3611{
3612 struct kvm_segment var;
3613 unsigned int rpl;
3614
3615 vmx_get_segment(vcpu, &var, seg);
3616 rpl = var.selector & SELECTOR_RPL_MASK;
3617
1872a3f4
AK		 3618 if (var.unusable)
3619 return true;
648dfaa7
MG		 3620 if (!var.s)
3621 return false;
3622 if (!var.present)
3623 return false;
3624 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3625 if (var.dpl < rpl) /* DPL < RPL */
3626 return false;
3627 }
3628
3629 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3630 * rights flags
3631 */
3632 return true;
3633}
3634
3635static bool tr_valid(struct kvm_vcpu *vcpu)
3636{
3637 struct kvm_segment tr;
3638
3639 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3640
1872a3f4
AK		 3641 if (tr.unusable)
3642 return false;
648dfaa7
MG		 3643 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3644 return false;
1872a3f4 3645 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3646 return false;
3647 if (!tr.present)
3648 return false;
3649
3650 return true;
3651}
3652
3653static bool ldtr_valid(struct kvm_vcpu *vcpu)
3654{
3655 struct kvm_segment ldtr;
3656
3657 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3658
1872a3f4
AK		 3659 if (ldtr.unusable)
3660 return true;
648dfaa7
MG		 3661 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3662 return false;
3663 if (ldtr.type != 2)
3664 return false;
3665 if (!ldtr.present)
3666 return false;
3667
3668 return true;
3669}
3670
3671static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3672{
3673 struct kvm_segment cs, ss;
3674
3675 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3676 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3677
3678 return ((cs.selector & SELECTOR_RPL_MASK) ==
3679 (ss.selector & SELECTOR_RPL_MASK));
3680}
3681
3682/*
3683 * Check if guest state is valid. Returns true if valid, false if
3684 * not.
3685 * We assume that registers are always usable
3686 */
3687static bool guest_state_valid(struct kvm_vcpu *vcpu)
3688{
c5e97c80
GN		 3689 if (enable_unrestricted_guest)
3690 return true;
3691
648dfaa7 3692 /* real mode guest state checks */
f13882d8 3693 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 3694 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3695 return false;
3696 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3697 return false;
3698 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3699 return false;
3700 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3701 return false;
3702 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3703 return false;
3704 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3705 return false;
3706 } else {
3707 /* protected mode guest state checks */
3708 if (!cs_ss_rpl_check(vcpu))
3709 return false;
3710 if (!code_segment_valid(vcpu))
3711 return false;
3712 if (!stack_segment_valid(vcpu))
3713 return false;
3714 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3715 return false;
3716 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3717 return false;
3718 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3719 return false;
3720 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3721 return false;
3722 if (!tr_valid(vcpu))
3723 return false;
3724 if (!ldtr_valid(vcpu))
3725 return false;
3726 }
3727 /* TODO:
3728 * - Add checks on RIP
3729 * - Add checks on RFLAGS
3730 */
3731
3732 return true;
3733}
3734
d77c26fc 3735static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3736{
40dcaa9f 3737 gfn_t fn;
195aefde 3738 u16 data = 0;
40dcaa9f 3739 int r, idx, ret = 0;
6aa8b732 3740
40dcaa9f 3741 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3742 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3743 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3744 if (r < 0)
10589a46 3745 goto out;
195aefde 3746 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3747 r = kvm_write_guest_page(kvm, fn++, &data,
3748 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3749 if (r < 0)
10589a46 3750 goto out;
195aefde
IE		 3751 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3752 if (r < 0)
10589a46 3753 goto out;
195aefde
IE		 3754 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3755 if (r < 0)
10589a46 3756 goto out;
195aefde 3757 data = ~0;
10589a46
MT		 3758 r = kvm_write_guest_page(kvm, fn, &data,
3759 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3760 sizeof(u8));
195aefde 3761 if (r < 0)
10589a46
MT		 3762 goto out;
3763
3764 ret = 1;
3765out:
40dcaa9f 3766 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3767 return ret;
6aa8b732
AK		 3768}
3769
b7ebfb05
SY		 3770static int init_rmode_identity_map(struct kvm *kvm)
3771{
40dcaa9f 3772 int i, idx, r, ret;
b7ebfb05
SY		 3773 pfn_t identity_map_pfn;
3774 u32 tmp;
3775
089d034e 3776 if (!enable_ept)
b7ebfb05
SY		 3777 return 1;
3778 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3779 printk(KERN_ERR "EPT: identity-mapping pagetable "
3780 "haven't been allocated!\n");
3781 return 0;
3782 }
3783 if (likely(kvm->arch.ept_identity_pagetable_done))
3784 return 1;
3785 ret = 0;
b927a3ce 3786 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3787 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3788 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3789 if (r < 0)
3790 goto out;
3791 /* Set up identity-mapping pagetable for EPT in real mode */
3792 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3793 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3794 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3795 r = kvm_write_guest_page(kvm, identity_map_pfn,
3796 &tmp, i * sizeof(tmp), sizeof(tmp));
3797 if (r < 0)
3798 goto out;
3799 }
3800 kvm->arch.ept_identity_pagetable_done = true;
3801 ret = 1;
3802out:
40dcaa9f 3803 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3804 return ret;
3805}
3806
6aa8b732
AK		 3807static void seg_setup(int seg)
3808{
772e0318 3809 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3810 unsigned int ar;
6aa8b732
AK		 3811
3812 vmcs_write16(sf->selector, 0);
3813 vmcs_writel(sf->base, 0);
3814 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3815 ar = 0x93;
3816 if (seg == VCPU_SREG_CS)
3817 ar |= 0x08; /* code segment */
3a624e29
NK		 3818
3819 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3820}
3821
f78e0e2e
SY		 3822static int alloc_apic_access_page(struct kvm *kvm)
3823{
4484141a 3824 struct page *page;
f78e0e2e
SY		 3825 struct kvm_userspace_memory_region kvm_userspace_mem;
3826 int r = 0;
3827
79fac95e 3828 mutex_lock(&kvm->slots_lock);
bfc6d222 3829 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3830 goto out;
3831 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3832 kvm_userspace_mem.flags = 0;
3833 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3834 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3835 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3836 if (r)
3837 goto out;
72dc67a6 3838
4484141a
XG		 3839 page = gfn_to_page(kvm, 0xfee00);
3840 if (is_error_page(page)) {
3841 r = -EFAULT;
3842 goto out;
3843 }
3844
3845 kvm->arch.apic_access_page = page;
f78e0e2e 3846out:
79fac95e 3847 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3848 return r;
3849}
3850
b7ebfb05
SY		 3851static int alloc_identity_pagetable(struct kvm *kvm)
3852{
4484141a 3853 struct page *page;
b7ebfb05
SY		 3854 struct kvm_userspace_memory_region kvm_userspace_mem;
3855 int r = 0;
3856
79fac95e 3857 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3858 if (kvm->arch.ept_identity_pagetable)
3859 goto out;
3860 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3861 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3862 kvm_userspace_mem.guest_phys_addr =
3863 kvm->arch.ept_identity_map_addr;
b7ebfb05 3864 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3865 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3866 if (r)
3867 goto out;
3868
4484141a
XG		 3869 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3870 if (is_error_page(page)) {
3871 r = -EFAULT;
3872 goto out;
3873 }
3874
3875 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3876out:
79fac95e 3877 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3878 return r;
3879}
3880
2384d2b3
SY		 3881static void allocate_vpid(struct vcpu_vmx *vmx)
3882{
3883 int vpid;
3884
3885 vmx->vpid = 0;
919818ab 3886 if (!enable_vpid)
2384d2b3
SY		 3887 return;
3888 spin_lock(&vmx_vpid_lock);
3889 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3890 if (vpid < VMX_NR_VPIDS) {
3891 vmx->vpid = vpid;
3892 __set_bit(vpid, vmx_vpid_bitmap);
3893 }
3894 spin_unlock(&vmx_vpid_lock);
3895}
3896
cdbecfc3
LJ		 3897static void free_vpid(struct vcpu_vmx *vmx)
3898{
3899 if (!enable_vpid)
3900 return;
3901 spin_lock(&vmx_vpid_lock);
3902 if (vmx->vpid != 0)
3903 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3904 spin_unlock(&vmx_vpid_lock);
3905}
3906
8d14695f
YZ		 3907#define MSR_TYPE_R 1
3908#define MSR_TYPE_W 2
3909static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3910 u32 msr, int type)
25c5f225 3911{
3e7c73e9 3912 int f = sizeof(unsigned long);
25c5f225
SY		 3913
3914 if (!cpu_has_vmx_msr_bitmap())
3915 return;
3916
3917 /*
3918 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3919 * have the write-low and read-high bitmap offsets the wrong way round.
3920 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3921 */
25c5f225 3922 if (msr <= 0x1fff) {
8d14695f
YZ		 3923 if (type & MSR_TYPE_R)
3924 /* read-low */
3925 __clear_bit(msr, msr_bitmap + 0x000 / f);
3926
3927 if (type & MSR_TYPE_W)
3928 /* write-low */
3929 __clear_bit(msr, msr_bitmap + 0x800 / f);
3930
25c5f225
SY		 3931 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3932 msr &= 0x1fff;
8d14695f
YZ		 3933 if (type & MSR_TYPE_R)
3934 /* read-high */
3935 __clear_bit(msr, msr_bitmap + 0x400 / f);
3936
3937 if (type & MSR_TYPE_W)
3938 /* write-high */
3939 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3940
3941 }
3942}
3943
3944static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3945 u32 msr, int type)
3946{
3947 int f = sizeof(unsigned long);
3948
3949 if (!cpu_has_vmx_msr_bitmap())
3950 return;
3951
3952 /*
3953 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3954 * have the write-low and read-high bitmap offsets the wrong way round.
3955 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3956 */
3957 if (msr <= 0x1fff) {
3958 if (type & MSR_TYPE_R)
3959 /* read-low */
3960 __set_bit(msr, msr_bitmap + 0x000 / f);
3961
3962 if (type & MSR_TYPE_W)
3963 /* write-low */
3964 __set_bit(msr, msr_bitmap + 0x800 / f);
3965
3966 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3967 msr &= 0x1fff;
3968 if (type & MSR_TYPE_R)
3969 /* read-high */
3970 __set_bit(msr, msr_bitmap + 0x400 / f);
3971
3972 if (type & MSR_TYPE_W)
3973 /* write-high */
3974 __set_bit(msr, msr_bitmap + 0xc00 / f);
3975
25c5f225 3976 }
25c5f225
SY		 3977}
3978
5897297b
AK		 3979static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3980{
3981 if (!longmode_only)
8d14695f
YZ		 3982 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3983 msr, MSR_TYPE_R | MSR_TYPE_W);
3984 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3985 msr, MSR_TYPE_R | MSR_TYPE_W);
3986}
3987
3988static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3989{
3990 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3991 msr, MSR_TYPE_R);
3992 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3993 msr, MSR_TYPE_R);
3994}
3995
3996static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3997{
3998 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3999 msr, MSR_TYPE_R);
4000 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4001 msr, MSR_TYPE_R);
4002}
4003
4004static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4005{
4006 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4007 msr, MSR_TYPE_W);
4008 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4009 msr, MSR_TYPE_W);
5897297b
AK		 4010}
4011
01e439be
YZ		 4012static int vmx_vm_has_apicv(struct kvm *kvm)
4013{
4014 return enable_apicv && irqchip_in_kernel(kvm);
4015}
4016
a20ed54d
YZ		 4017/*
4018 * Send interrupt to vcpu via posted interrupt way.
4019 * 1. If target vcpu is running(non-root mode), send posted interrupt
4020 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4021 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4022 * interrupt from PIR in next vmentry.
4023 */
4024static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4025{
4026 struct vcpu_vmx *vmx = to_vmx(vcpu);
4027 int r;
4028
4029 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4030 return;
4031
4032 r = pi_test_and_set_on(&vmx->pi_desc);
4033 kvm_make_request(KVM_REQ_EVENT, vcpu);
6ffbbbba 4034#ifdef CONFIG_SMP
a20ed54d
YZ		 4035 if (!r && (vcpu->mode == IN_GUEST_MODE))
4036 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4037 POSTED_INTR_VECTOR);
4038 else
6ffbbbba 4039#endif
a20ed54d
YZ		 4040 kvm_vcpu_kick(vcpu);
4041}
4042
4043static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4044{
4045 struct vcpu_vmx *vmx = to_vmx(vcpu);
4046
4047 if (!pi_test_and_clear_on(&vmx->pi_desc))
4048 return;
4049
4050 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4051}
4052
4053static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4054{
4055 return;
4056}
4057
a3a8ff8e
NHE		 4058/*
4059 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4060 * will not change in the lifetime of the guest.
4061 * Note that host-state that does change is set elsewhere. E.g., host-state
4062 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4063 */
a547c6db 4064static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 4065{
4066 u32 low32, high32;
4067 unsigned long tmpl;
4068 struct desc_ptr dt;
4069
b1a74bf8 4070 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 4071 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
4072 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4073
4074 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 4075#ifdef CONFIG_X86_64
4076 /*
4077 * Load null selectors, so we can avoid reloading them in
4078 * __vmx_load_host_state(), in case userspace uses the null selectors
4079 * too (the expected case).
4080 */
4081 vmcs_write16(HOST_DS_SELECTOR, 0);
4082 vmcs_write16(HOST_ES_SELECTOR, 0);
4083#else
a3a8ff8e
NHE		 4084 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4085 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 4086#endif
a3a8ff8e
NHE		 4087 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
4088 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
4089
4090 native_store_idt(&dt);
4091 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 4092 vmx->host_idt_base = dt.address;
a3a8ff8e 4093
83287ea4 4094 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 4095
4096 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4097 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4098 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4099 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
4100
4101 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4102 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4103 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4104 }
4105}
4106
bf8179a0
NHE		 4107static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4108{
4109 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4110 if (enable_ept)
4111 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 4112 if (is_guest_mode(&vmx->vcpu))
4113 vmx->vcpu.arch.cr4_guest_owned_bits &=
4114 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 4115 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4116}
4117
01e439be
YZ		 4118static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4119{
4120 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4121
4122 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4123 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4124 return pin_based_exec_ctrl;
4125}
4126
bf8179a0
NHE		 4127static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4128{
4129 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4130 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
4131 exec_control &= ~CPU_BASED_TPR_SHADOW;
4132#ifdef CONFIG_X86_64
4133 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4134 CPU_BASED_CR8_LOAD_EXITING;
4135#endif
4136 }
4137 if (!enable_ept)
4138 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4139 CPU_BASED_CR3_LOAD_EXITING |
4140 CPU_BASED_INVLPG_EXITING;
4141 return exec_control;
4142}
4143
4144static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4145{
4146 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4147 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4148 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4149 if (vmx->vpid == 0)
4150 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4151 if (!enable_ept) {
4152 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4153 enable_unrestricted_guest = 0;
ad756a16
MJ		 4154 /* Enable INVPCID for non-ept guests may cause performance regression. */
4155 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 4156 }
4157 if (!enable_unrestricted_guest)
4158 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4159 if (!ple_gap)
4160 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 4161 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
4162 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4163 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 4164 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
abc4fc58
AG		 4165 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4166 (handle_vmptrld).
4167 We can NOT enable shadow_vmcs here because we don't have yet
4168 a current VMCS12
4169 */
4170 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
bf8179a0
NHE		 4171 return exec_control;
4172}
4173
ce88decf
XG		 4174static void ept_set_mmio_spte_mask(void)
4175{
4176 /*
4177 * EPT Misconfigurations can be generated if the value of bits 2:0
4178 * of an EPT paging-structure entry is 110b (write/execute).
885032b9 4179 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
ce88decf
XG		 4180 * spte.
4181 */
885032b9 4182 kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
ce88decf
XG		 4183}
4184
6aa8b732
AK		 4185/*
4186 * Sets up the vmcs for emulated real mode.
4187 */
8b9cf98c 4188static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 4189{
2e4ce7f5 4190#ifdef CONFIG_X86_64
6aa8b732 4191 unsigned long a;
2e4ce7f5 4192#endif
6aa8b732 4193 int i;
6aa8b732 4194
6aa8b732 4195 /* I/O */
3e7c73e9
AK		 4196 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4197 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4198
4607c2d7
AG		 4199 if (enable_shadow_vmcs) {
4200 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4201 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4202 }
25c5f225 4203 if (cpu_has_vmx_msr_bitmap())
5897297b 4204 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4205
6aa8b732
AK		 4206 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4207
6aa8b732 4208 /* Control */
01e439be 4209 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
6e5d865c 4210
bf8179a0 4211 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4212
83ff3b9d 4213 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4214 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4215 vmx_secondary_exec_control(vmx));
83ff3b9d 4216 }
f78e0e2e 4217
01e439be 4218 if (vmx_vm_has_apicv(vmx->vcpu.kvm)) {
c7c9c56c
YZ		 4219 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4220 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4221 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4222 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4223
4224 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be
YZ		 4225
4226 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4227 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 4228 }
4229
4b8d54f9
ZE		 4230 if (ple_gap) {
4231 vmcs_write32(PLE_GAP, ple_gap);
4232 vmcs_write32(PLE_WINDOW, ple_window);
4233 }
4234
c3707958
XG		 4235 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4236 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4237 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4238
9581d442
AK		 4239 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4240 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4241 vmx_set_constant_host_state(vmx);
05b3e0c2 4242#ifdef CONFIG_X86_64
6aa8b732
AK		 4243 rdmsrl(MSR_FS_BASE, a);
4244 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4245 rdmsrl(MSR_GS_BASE, a);
4246 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4247#else
4248 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4249 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4250#endif
4251
2cc51560
ED		 4252 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4253 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4254 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4255 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4256 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4257
468d472f 4258 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4259 u32 msr_low, msr_high;
4260 u64 host_pat;
468d472f
SY		 4261 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4262 host_pat = msr_low | ((u64) msr_high << 32);
4263 /* Write the default value follow host pat */
4264 vmcs_write64(GUEST_IA32_PAT, host_pat);
4265 /* Keep arch.pat sync with GUEST_IA32_PAT */
4266 vmx->vcpu.arch.pat = host_pat;
4267 }
4268
6aa8b732
AK		 4269 for (i = 0; i < NR_VMX_MSR; ++i) {
4270 u32 index = vmx_msr_index[i];
4271 u32 data_low, data_high;
a2fa3e9f 4272 int j = vmx->nmsrs;
6aa8b732
AK		 4273
4274 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4275 continue;
432bd6cb
AK		 4276 if (wrmsr_safe(index, data_low, data_high) < 0)
4277 continue;
26bb0981
AK		 4278 vmx->guest_msrs[j].index = i;
4279 vmx->guest_msrs[j].data = 0;
d5696725 4280 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4281 ++vmx->nmsrs;
6aa8b732 4282 }
6aa8b732 4283
1c3d14fe 4284 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4285
4286 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4287 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4288
e00c8cf2 4289 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4290 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4291
4292 return 0;
4293}
4294
57f252f2 4295static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4296{
4297 struct vcpu_vmx *vmx = to_vmx(vcpu);
4298 u64 msr;
e00c8cf2 4299
7ffd92c5 4300 vmx->rmode.vm86_active = 0;
e00c8cf2 4301
3b86cd99
JK		 4302 vmx->soft_vnmi_blocked = 0;
4303
ad312c7c 4304 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4305 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4306 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4307 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4308 msr |= MSR_IA32_APICBASE_BSP;
4309 kvm_set_apic_base(&vmx->vcpu, msr);
4310
2fb92db1
AK		 4311 vmx_segment_cache_clear(vmx);
4312
5706be0d 4313 seg_setup(VCPU_SREG_CS);
66450a21 4314 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4315 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4316
4317 seg_setup(VCPU_SREG_DS);
4318 seg_setup(VCPU_SREG_ES);
4319 seg_setup(VCPU_SREG_FS);
4320 seg_setup(VCPU_SREG_GS);
4321 seg_setup(VCPU_SREG_SS);
4322
4323 vmcs_write16(GUEST_TR_SELECTOR, 0);
4324 vmcs_writel(GUEST_TR_BASE, 0);
4325 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4326 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4327
4328 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4329 vmcs_writel(GUEST_LDTR_BASE, 0);
4330 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4331 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4332
4333 vmcs_write32(GUEST_SYSENTER_CS, 0);
4334 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4335 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4336
4337 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4338 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4339
e00c8cf2
AK		 4340 vmcs_writel(GUEST_GDTR_BASE, 0);
4341 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4342
4343 vmcs_writel(GUEST_IDTR_BASE, 0);
4344 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4345
443381a8 4346 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4347 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4348 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4349
e00c8cf2
AK		 4350 /* Special registers */
4351 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4352
4353 setup_msrs(vmx);
4354
6aa8b732
AK		 4355 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4356
f78e0e2e
SY		 4357 if (cpu_has_vmx_tpr_shadow()) {
4358 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4359 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4360 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4361 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4362 vmcs_write32(TPR_THRESHOLD, 0);
4363 }
4364
4365 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4366 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4367 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4368
01e439be
YZ		 4369 if (vmx_vm_has_apicv(vcpu->kvm))
4370 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4371
2384d2b3
SY		 4372 if (vmx->vpid != 0)
4373 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4374
fa40052c 4375 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4376 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4377 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4378 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4379 vmx_fpu_activate(&vmx->vcpu);
4380 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4381
b9d762fa 4382 vpid_sync_context(vmx);
6aa8b732
AK		 4383}
4384
b6f1250e
NHE		 4385/*
4386 * In nested virtualization, check if L1 asked to exit on external interrupts.
4387 * For most existing hypervisors, this will always return true.
4388 */
4389static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4390{
4391 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4392 PIN_BASED_EXT_INTR_MASK;
4393}
4394
ea8ceb83
JK		 4395static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4396{
4397 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4398 PIN_BASED_NMI_EXITING;
4399}
4400
730dca42 4401static int enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4402{
4403 u32 cpu_based_vm_exec_control;
730dca42
JK		 4404
4405 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
d6185f20
NHE		 4406 /*
4407 * We get here if vmx_interrupt_allowed() said we can't
730dca42
JK		 4408 * inject to L1 now because L2 must run. The caller will have
4409 * to make L2 exit right after entry, so we can inject to L1
4410 * more promptly.
b6f1250e 4411 */
730dca42 4412 return -EBUSY;
3b86cd99
JK		 4413
4414 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4415 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4416 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
730dca42 4417 return 0;
3b86cd99
JK		 4418}
4419
03b28f81 4420static int enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99
JK		 4421{
4422 u32 cpu_based_vm_exec_control;
4423
03b28f81
JK		 4424 if (!cpu_has_virtual_nmis())
4425 return enable_irq_window(vcpu);
4426
4427 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI)
4428 return enable_irq_window(vcpu);
3b86cd99
JK		 4429
4430 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4431 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4432 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
03b28f81 4433 return 0;
3b86cd99
JK		 4434}
4435
66fd3f7f 4436static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4437{
9c8cba37 4438 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4439 uint32_t intr;
4440 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4441
229456fc 4442 trace_kvm_inj_virq(irq);
2714d1d3 4443
fa89a817 4444 ++vcpu->stat.irq_injections;
7ffd92c5 4445 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4446 int inc_eip = 0;
4447 if (vcpu->arch.interrupt.soft)
4448 inc_eip = vcpu->arch.event_exit_inst_len;
4449 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4450 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4451 return;
4452 }
66fd3f7f
GN		 4453 intr = irq | INTR_INFO_VALID_MASK;
4454 if (vcpu->arch.interrupt.soft) {
4455 intr |= INTR_TYPE_SOFT_INTR;
4456 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4457 vmx->vcpu.arch.event_exit_inst_len);
4458 } else
4459 intr |= INTR_TYPE_EXT_INTR;
4460 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4461}
4462
f08864b4
SY		 4463static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4464{
66a5a347
JK		 4465 struct vcpu_vmx *vmx = to_vmx(vcpu);
4466
0b6ac343
NHE		 4467 if (is_guest_mode(vcpu))
4468 return;
4469
3b86cd99
JK		 4470 if (!cpu_has_virtual_nmis()) {
4471 /*
4472 * Tracking the NMI-blocked state in software is built upon
4473 * finding the next open IRQ window. This, in turn, depends on
4474 * well-behaving guests: They have to keep IRQs disabled at
4475 * least as long as the NMI handler runs. Otherwise we may
4476 * cause NMI nesting, maybe breaking the guest. But as this is
4477 * highly unlikely, we can live with the residual risk.
4478 */
4479 vmx->soft_vnmi_blocked = 1;
4480 vmx->vnmi_blocked_time = 0;
4481 }
4482
487b391d 4483 ++vcpu->stat.nmi_injections;
9d58b931 4484 vmx->nmi_known_unmasked = false;
7ffd92c5 4485 if (vmx->rmode.vm86_active) {
71f9833b 4486 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4487 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4488 return;
4489 }
f08864b4
SY		 4490 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4491 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4492}
4493
3cfc3092
JK		 4494static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4495{
4496 if (!cpu_has_virtual_nmis())
4497 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4498 if (to_vmx(vcpu)->nmi_known_unmasked)
4499 return false;
c332c83a 4500 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4501}
4502
4503static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4504{
4505 struct vcpu_vmx *vmx = to_vmx(vcpu);
4506
4507 if (!cpu_has_virtual_nmis()) {
4508 if (vmx->soft_vnmi_blocked != masked) {
4509 vmx->soft_vnmi_blocked = masked;
4510 vmx->vnmi_blocked_time = 0;
4511 }
4512 } else {
9d58b931 4513 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4514 if (masked)
4515 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4516 GUEST_INTR_STATE_NMI);
4517 else
4518 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4519 GUEST_INTR_STATE_NMI);
4520 }
4521}
4522
2505dc9f
JK		 4523static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4524{
ea8ceb83
JK		 4525 if (is_guest_mode(vcpu)) {
4526 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4527
4528 if (to_vmx(vcpu)->nested.nested_run_pending)
4529 return 0;
4530 if (nested_exit_on_nmi(vcpu)) {
4531 nested_vmx_vmexit(vcpu);
4532 vmcs12->vm_exit_reason = EXIT_REASON_EXCEPTION_NMI;
4533 vmcs12->vm_exit_intr_info = NMI_VECTOR |
4534 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK;
4535 /*
4536 * The NMI-triggered VM exit counts as injection:
4537 * clear this one and block further NMIs.
4538 */
4539 vcpu->arch.nmi_pending = 0;
4540 vmx_set_nmi_mask(vcpu, true);
4541 return 0;
4542 }
4543 }
4544
2505dc9f
JK		 4545 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4546 return 0;
4547
4548 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4549 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4550 | GUEST_INTR_STATE_NMI));
4551}
4552
78646121
GN		 4553static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4554{
e8457c67 4555 if (is_guest_mode(vcpu)) {
51cfe38e 4556 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4557
4558 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4559 return 0;
e8457c67
JK		 4560 if (nested_exit_on_intr(vcpu)) {
4561 nested_vmx_vmexit(vcpu);
4562 vmcs12->vm_exit_reason =
4563 EXIT_REASON_EXTERNAL_INTERRUPT;
4564 vmcs12->vm_exit_intr_info = 0;
4565 /*
4566 * fall through to normal code, but now in L1, not L2
4567 */
4568 }
b6f1250e
NHE		 4569 }
4570
c4282df9
GN		 4571 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4572 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4573 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4574}
4575
cbc94022
IE		 4576static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4577{
4578 int ret;
4579 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4580 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4581 .guest_phys_addr = addr,
4582 .memory_size = PAGE_SIZE * 3,
4583 .flags = 0,
4584 };
4585
47ae31e2 4586 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4587 if (ret)
4588 return ret;
bfc6d222 4589 kvm->arch.tss_addr = addr;
93ea5388
GN		 4590 if (!init_rmode_tss(kvm))
4591 return -ENOMEM;
4592
cbc94022
IE		 4593 return 0;
4594}
4595
0ca1b4f4 4596static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4597{
77ab6db0 4598 switch (vec) {
77ab6db0 4599 case BP_VECTOR:
c573cd22
JK		 4600 /*
4601 * Update instruction length as we may reinject the exception
4602 * from user space while in guest debugging mode.
4603 */
4604 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4605 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4606 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4607 return false;
4608 /* fall through */
4609 case DB_VECTOR:
4610 if (vcpu->guest_debug &
4611 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4612 return false;
d0bfb940
JK		 4613 /* fall through */
4614 case DE_VECTOR:
77ab6db0
JK		 4615 case OF_VECTOR:
4616 case BR_VECTOR:
4617 case UD_VECTOR:
4618 case DF_VECTOR:
4619 case SS_VECTOR:
4620 case GP_VECTOR:
4621 case MF_VECTOR:
0ca1b4f4
GN		 4622 return true;
4623 break;
77ab6db0 4624 }
0ca1b4f4
GN		 4625 return false;
4626}
4627
4628static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4629 int vec, u32 err_code)
4630{
4631 /*
4632 * Instruction with address size override prefix opcode 0x67
4633 * Cause the #SS fault with 0 error code in VM86 mode.
4634 */
4635 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4636 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4637 if (vcpu->arch.halt_request) {
4638 vcpu->arch.halt_request = 0;
4639 return kvm_emulate_halt(vcpu);
4640 }
4641 return 1;
4642 }
4643 return 0;
4644 }
4645
4646 /*
4647 * Forward all other exceptions that are valid in real mode.
4648 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4649 * the required debugging infrastructure rework.
4650 */
4651 kvm_queue_exception(vcpu, vec);
4652 return 1;
6aa8b732
AK		 4653}
4654
a0861c02
AK		 4655/*
4656 * Trigger machine check on the host. We assume all the MSRs are already set up
4657 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4658 * We pass a fake environment to the machine check handler because we want
4659 * the guest to be always treated like user space, no matter what context
4660 * it used internally.
4661 */
4662static void kvm_machine_check(void)
4663{
4664#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4665 struct pt_regs regs = {
4666 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4667 .flags = X86_EFLAGS_IF,
4668 };
4669
4670 do_machine_check(&regs, 0);
4671#endif
4672}
4673
851ba692 4674static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4675{
4676 /* already handled by vcpu_run */
4677 return 1;
4678}
4679
851ba692 4680static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4681{
1155f76a 4682 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4683 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4684 u32 intr_info, ex_no, error_code;
42dbaa5a 4685 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4686 u32 vect_info;
4687 enum emulation_result er;
4688
1155f76a 4689 vect_info = vmx->idt_vectoring_info;
88786475 4690 intr_info = vmx->exit_intr_info;
6aa8b732 4691
a0861c02 4692 if (is_machine_check(intr_info))
851ba692 4693 return handle_machine_check(vcpu);
a0861c02 4694
e4a41889 4695 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4696 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4697
4698 if (is_no_device(intr_info)) {
5fd86fcf 4699 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4700 return 1;
4701 }
4702
7aa81cc0 4703 if (is_invalid_opcode(intr_info)) {
51d8b661 4704 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4705 if (er != EMULATE_DONE)
7ee5d940 4706 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4707 return 1;
4708 }
4709
6aa8b732 4710 error_code = 0;
2e11384c 4711 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4712 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4713
4714 /*
4715 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4716 * MMIO, it is better to report an internal error.
4717 * See the comments in vmx_handle_exit.
4718 */
4719 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4720 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4721 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4722 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4723 vcpu->run->internal.ndata = 2;
4724 vcpu->run->internal.data[0] = vect_info;
4725 vcpu->run->internal.data[1] = intr_info;
4726 return 0;
4727 }
4728
6aa8b732 4729 if (is_page_fault(intr_info)) {
1439442c 4730 /* EPT won't cause page fault directly */
cf3ace79 4731 BUG_ON(enable_ept);
6aa8b732 4732 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4733 trace_kvm_page_fault(cr2, error_code);
4734
3298b75c 4735 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4736 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4737 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4738 }
4739
d0bfb940 4740 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4741
4742 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4743 return handle_rmode_exception(vcpu, ex_no, error_code);
4744
42dbaa5a
JK		 4745 switch (ex_no) {
4746 case DB_VECTOR:
4747 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4748 if (!(vcpu->guest_debug &
4749 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4750 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4751 kvm_queue_exception(vcpu, DB_VECTOR);
4752 return 1;
4753 }
4754 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4755 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4756 /* fall through */
4757 case BP_VECTOR:
c573cd22
JK		 4758 /*
4759 * Update instruction length as we may reinject #BP from
4760 * user space while in guest debugging mode. Reading it for
4761 * #DB as well causes no harm, it is not used in that case.
4762 */
4763 vmx->vcpu.arch.event_exit_inst_len =
4764 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4765 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4766 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4767 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4768 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4769 break;
4770 default:
d0bfb940
JK		 4771 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4772 kvm_run->ex.exception = ex_no;
4773 kvm_run->ex.error_code = error_code;
42dbaa5a 4774 break;
6aa8b732 4775 }
6aa8b732
AK		 4776 return 0;
4777}
4778
851ba692 4779static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4780{
1165f5fe 4781 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4782 return 1;
4783}
4784
851ba692 4785static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4786{
851ba692 4787 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4788 return 0;
4789}
6aa8b732 4790
851ba692 4791static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4792{
bfdaab09 4793 unsigned long exit_qualification;
34c33d16 4794 int size, in, string;
039576c0 4795 unsigned port;
6aa8b732 4796
bfdaab09 4797 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4798 string = (exit_qualification & 16) != 0;
cf8f70bf 4799 in = (exit_qualification & 8) != 0;
e70669ab 4800
cf8f70bf 4801 ++vcpu->stat.io_exits;
e70669ab 4802
cf8f70bf 4803 if (string || in)
51d8b661 4804 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4805
cf8f70bf
GN		 4806 port = exit_qualification >> 16;
4807 size = (exit_qualification & 7) + 1;
e93f36bc 4808 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4809
4810 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4811}
4812
102d8325
IM		 4813static void
4814vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4815{
4816 /*
4817 * Patch in the VMCALL instruction:
4818 */
4819 hypercall[0] = 0x0f;
4820 hypercall[1] = 0x01;
4821 hypercall[2] = 0xc1;
102d8325
IM		 4822}
4823
0fa06071 4824/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4825static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4826{
eeadf9e7 4827 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4828 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4829 unsigned long orig_val = val;
4830
eeadf9e7
NHE		 4831 /*
4832 * We get here when L2 changed cr0 in a way that did not change
4833 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4834 * but did change L0 shadowed bits. So we first calculate the
4835 * effective cr0 value that L1 would like to write into the
4836 * hardware. It consists of the L2-owned bits from the new
4837 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4838 */
1a0d74e6
JK		 4839 val = (val & ~vmcs12->cr0_guest_host_mask) |
4840 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4841
4842 /* TODO: will have to take unrestricted guest mode into
4843 * account */
4844 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4845 return 1;
1a0d74e6
JK		 4846
4847 if (kvm_set_cr0(vcpu, val))
4848 return 1;
4849 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4850 return 0;
1a0d74e6
JK		 4851 } else {
4852 if (to_vmx(vcpu)->nested.vmxon &&
4853 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4854 return 1;
eeadf9e7 4855 return kvm_set_cr0(vcpu, val);
1a0d74e6 4856 }
eeadf9e7
NHE		 4857}
4858
4859static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4860{
4861 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4862 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4863 unsigned long orig_val = val;
4864
4865 /* analogously to handle_set_cr0 */
4866 val = (val & ~vmcs12->cr4_guest_host_mask) |
4867 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4868 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4869 return 1;
1a0d74e6 4870 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4871 return 0;
4872 } else
4873 return kvm_set_cr4(vcpu, val);
4874}
4875
4876/* called to set cr0 as approriate for clts instruction exit. */
4877static void handle_clts(struct kvm_vcpu *vcpu)
4878{
4879 if (is_guest_mode(vcpu)) {
4880 /*
4881 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4882 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4883 * just pretend it's off (also in arch.cr0 for fpu_activate).
4884 */
4885 vmcs_writel(CR0_READ_SHADOW,
4886 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4887 vcpu->arch.cr0 &= ~X86_CR0_TS;
4888 } else
4889 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4890}
4891
851ba692 4892static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4893{
229456fc 4894 unsigned long exit_qualification, val;
6aa8b732
AK		 4895 int cr;
4896 int reg;
49a9b07e 4897 int err;
6aa8b732 4898
bfdaab09 4899 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4900 cr = exit_qualification & 15;
4901 reg = (exit_qualification >> 8) & 15;
4902 switch ((exit_qualification >> 4) & 3) {
4903 case 0: /* mov to cr */
229456fc
MT		 4904 val = kvm_register_read(vcpu, reg);
4905 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4906 switch (cr) {
4907 case 0:
eeadf9e7 4908 err = handle_set_cr0(vcpu, val);
db8fcefa 4909 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4910 return 1;
4911 case 3:
2390218b 4912 err = kvm_set_cr3(vcpu, val);
db8fcefa 4913 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4914 return 1;
4915 case 4:
eeadf9e7 4916 err = handle_set_cr4(vcpu, val);
db8fcefa 4917 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4918 return 1;
0a5fff19
GN		 4919 case 8: {
4920 u8 cr8_prev = kvm_get_cr8(vcpu);
4921 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4922 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4923 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4924 if (irqchip_in_kernel(vcpu->kvm))
4925 return 1;
4926 if (cr8_prev <= cr8)
4927 return 1;
851ba692 4928 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4929 return 0;
4930 }
4b8073e4 4931 }
6aa8b732 4932 break;
25c4c276 4933 case 2: /* clts */
eeadf9e7 4934 handle_clts(vcpu);
4d4ec087 4935 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4936 skip_emulated_instruction(vcpu);
6b52d186 4937 vmx_fpu_activate(vcpu);
25c4c276 4938 return 1;
6aa8b732
AK		 4939 case 1: /*mov from cr*/
4940 switch (cr) {
4941 case 3:
9f8fe504
AK		 4942 val = kvm_read_cr3(vcpu);
4943 kvm_register_write(vcpu, reg, val);
4944 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4945 skip_emulated_instruction(vcpu);
4946 return 1;
4947 case 8:
229456fc
MT		 4948 val = kvm_get_cr8(vcpu);
4949 kvm_register_write(vcpu, reg, val);
4950 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4951 skip_emulated_instruction(vcpu);
4952 return 1;
4953 }
4954 break;
4955 case 3: /* lmsw */
a1f83a74 4956 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4957 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4958 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4959
4960 skip_emulated_instruction(vcpu);
4961 return 1;
4962 default:
4963 break;
4964 }
851ba692 4965 vcpu->run->exit_reason = 0;
a737f256 4966 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4967 (int)(exit_qualification >> 4) & 3, cr);
4968 return 0;
4969}
4970
851ba692 4971static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4972{
bfdaab09 4973 unsigned long exit_qualification;
6aa8b732
AK		 4974 int dr, reg;
4975
f2483415 4976 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4977 if (!kvm_require_cpl(vcpu, 0))
4978 return 1;
42dbaa5a
JK		 4979 dr = vmcs_readl(GUEST_DR7);
4980 if (dr & DR7_GD) {
4981 /*
4982 * As the vm-exit takes precedence over the debug trap, we
4983 * need to emulate the latter, either for the host or the
4984 * guest debugging itself.
4985 */
4986 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4987 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4988 vcpu->run->debug.arch.dr7 = dr;
4989 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4990 vmcs_readl(GUEST_CS_BASE) +
4991 vmcs_readl(GUEST_RIP);
851ba692
AK		 4992 vcpu->run->debug.arch.exception = DB_VECTOR;
4993 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4994 return 0;
4995 } else {
4996 vcpu->arch.dr7 &= ~DR7_GD;
4997 vcpu->arch.dr6 |= DR6_BD;
4998 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4999 kvm_queue_exception(vcpu, DB_VECTOR);
5000 return 1;
5001 }
5002 }
5003
bfdaab09 5004 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 5005 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5006 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5007 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 5008 unsigned long val;
5009 if (!kvm_get_dr(vcpu, dr, &val))
5010 kvm_register_write(vcpu, reg, val);
5011 } else
5012 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 5013 skip_emulated_instruction(vcpu);
5014 return 1;
5015}
5016
020df079
GN		 5017static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5018{
5019 vmcs_writel(GUEST_DR7, val);
5020}
5021
851ba692 5022static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 5023{
06465c5a
AK		 5024 kvm_emulate_cpuid(vcpu);
5025 return 1;
6aa8b732
AK		 5026}
5027
851ba692 5028static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 5029{
ad312c7c 5030 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 5031 u64 data;
5032
5033 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 5034 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 5035 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5036 return 1;
5037 }
5038
229456fc 5039 trace_kvm_msr_read(ecx, data);
2714d1d3 5040
6aa8b732 5041 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 5042 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
5043 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 5044 skip_emulated_instruction(vcpu);
5045 return 1;
5046}
5047
851ba692 5048static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 5049{
8fe8ab46 5050 struct msr_data msr;
ad312c7c
ZX		 5051 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5052 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5053 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 5054
8fe8ab46
WA		 5055 msr.data = data;
5056 msr.index = ecx;
5057 msr.host_initiated = false;
5058 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 5059 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 5060 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 5061 return 1;
5062 }
5063
59200273 5064 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 5065 skip_emulated_instruction(vcpu);
5066 return 1;
5067}
5068
851ba692 5069static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 5070{
3842d135 5071 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 5072 return 1;
5073}
5074
851ba692 5075static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 5076{
85f455f7
ED		 5077 u32 cpu_based_vm_exec_control;
5078
5079 /* clear pending irq */
5080 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5081 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5082 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 5083
3842d135
AK		 5084 kvm_make_request(KVM_REQ_EVENT, vcpu);
5085
a26bf12a 5086 ++vcpu->stat.irq_window_exits;
2714d1d3 5087
c1150d8c
DL		 5088 /*
5089 * If the user space waits to inject interrupts, exit as soon as
5090 * possible
5091 */
8061823a 5092 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 5093 vcpu->run->request_interrupt_window &&
8061823a 5094 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 5095 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 5096 return 0;
5097 }
6aa8b732
AK		 5098 return 1;
5099}
5100
851ba692 5101static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 5102{
5103 skip_emulated_instruction(vcpu);
d3bef15f 5104 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 5105}
5106
851ba692 5107static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 5108{
510043da 5109 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 5110 kvm_emulate_hypercall(vcpu);
5111 return 1;
c21415e8
IM		 5112}
5113
ec25d5e6
GN		 5114static int handle_invd(struct kvm_vcpu *vcpu)
5115{
51d8b661 5116 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 5117}
5118
851ba692 5119static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 5120{
f9c617f6 5121 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 5122
5123 kvm_mmu_invlpg(vcpu, exit_qualification);
5124 skip_emulated_instruction(vcpu);
5125 return 1;
5126}
5127
fee84b07
AK		 5128static int handle_rdpmc(struct kvm_vcpu *vcpu)
5129{
5130 int err;
5131
5132 err = kvm_rdpmc(vcpu);
5133 kvm_complete_insn_gp(vcpu, err);
5134
5135 return 1;
5136}
5137
851ba692 5138static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 5139{
5140 skip_emulated_instruction(vcpu);
f5f48ee1 5141 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 5142 return 1;
5143}
5144
2acf923e
DC		 5145static int handle_xsetbv(struct kvm_vcpu *vcpu)
5146{
5147 u64 new_bv = kvm_read_edx_eax(vcpu);
5148 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5149
5150 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5151 skip_emulated_instruction(vcpu);
5152 return 1;
5153}
5154
851ba692 5155static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 5156{
58fbbf26
KT		 5157 if (likely(fasteoi)) {
5158 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5159 int access_type, offset;
5160
5161 access_type = exit_qualification & APIC_ACCESS_TYPE;
5162 offset = exit_qualification & APIC_ACCESS_OFFSET;
5163 /*
5164 * Sane guest uses MOV to write EOI, with written value
5165 * not cared. So make a short-circuit here by avoiding
5166 * heavy instruction emulation.
5167 */
5168 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5169 (offset == APIC_EOI)) {
5170 kvm_lapic_set_eoi(vcpu);
5171 skip_emulated_instruction(vcpu);
5172 return 1;
5173 }
5174 }
51d8b661 5175 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 5176}
5177
c7c9c56c
YZ		 5178static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5179{
5180 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5181 int vector = exit_qualification & 0xff;
5182
5183 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5184 kvm_apic_set_eoi_accelerated(vcpu, vector);
5185 return 1;
5186}
5187
83d4c286
YZ		 5188static int handle_apic_write(struct kvm_vcpu *vcpu)
5189{
5190 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5191 u32 offset = exit_qualification & 0xfff;
5192
5193 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5194 kvm_apic_write_nodecode(vcpu, offset);
5195 return 1;
5196}
5197
851ba692 5198static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 5199{
60637aac 5200 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 5201 unsigned long exit_qualification;
e269fb21
JK		 5202 bool has_error_code = false;
5203 u32 error_code = 0;
37817f29 5204 u16 tss_selector;
7f3d35fd 5205 int reason, type, idt_v, idt_index;
64a7ec06
GN		 5206
5207 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 5208 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 5209 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 5210
5211 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5212
5213 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 5214 if (reason == TASK_SWITCH_GATE && idt_v) {
5215 switch (type) {
5216 case INTR_TYPE_NMI_INTR:
5217 vcpu->arch.nmi_injected = false;
654f06fc 5218 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 5219 break;
5220 case INTR_TYPE_EXT_INTR:
66fd3f7f 5221 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 5222 kvm_clear_interrupt_queue(vcpu);
5223 break;
5224 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5225 if (vmx->idt_vectoring_info &
5226 VECTORING_INFO_DELIVER_CODE_MASK) {
5227 has_error_code = true;
5228 error_code =
5229 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5230 }
5231 /* fall through */
64a7ec06
GN		 5232 case INTR_TYPE_SOFT_EXCEPTION:
5233 kvm_clear_exception_queue(vcpu);
5234 break;
5235 default:
5236 break;
5237 }
60637aac 5238 }
37817f29
IE		 5239 tss_selector = exit_qualification;
5240
64a7ec06
GN		 5241 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5242 type != INTR_TYPE_EXT_INTR &&
5243 type != INTR_TYPE_NMI_INTR))
5244 skip_emulated_instruction(vcpu);
5245
7f3d35fd
KW		 5246 if (kvm_task_switch(vcpu, tss_selector,
5247 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5248 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5249 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5250 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5251 vcpu->run->internal.ndata = 0;
42dbaa5a 5252 return 0;
acb54517 5253 }
42dbaa5a
JK		 5254
5255 /* clear all local breakpoint enable flags */
5256 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5257
5258 /*
5259 * TODO: What about debug traps on tss switch?
5260 * Are we supposed to inject them and update dr6?
5261 */
5262
5263 return 1;
37817f29
IE		 5264}
5265
851ba692 5266static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5267{
f9c617f6 5268 unsigned long exit_qualification;
1439442c 5269 gpa_t gpa;
4f5982a5 5270 u32 error_code;
1439442c 5271 int gla_validity;
1439442c 5272
f9c617f6 5273 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5274
1439442c
SY		 5275 gla_validity = (exit_qualification >> 7) & 0x3;
5276 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5277 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5278 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5279 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5280 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5281 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5282 (long unsigned int)exit_qualification);
851ba692
AK		 5283 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5284 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5285 return 0;
1439442c
SY		 5286 }
5287
5288 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5289 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5290
5291 /* It is a write fault? */
5292 error_code = exit_qualification & (1U << 1);
5293 /* ept page table is present? */
5294 error_code |= (exit_qualification >> 3) & 0x1;
5295
5296 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5297}
5298
68f89400
MT		 5299static u64 ept_rsvd_mask(u64 spte, int level)
5300{
5301 int i;
5302 u64 mask = 0;
5303
5304 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5305 mask |= (1ULL << i);
5306
5307 if (level > 2)
5308 /* bits 7:3 reserved */
5309 mask |= 0xf8;
5310 else if (level == 2) {
5311 if (spte & (1ULL << 7))
5312 /* 2MB ref, bits 20:12 reserved */
5313 mask |= 0x1ff000;
5314 else
5315 /* bits 6:3 reserved */
5316 mask |= 0x78;
5317 }
5318
5319 return mask;
5320}
5321
5322static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5323 int level)
5324{
5325 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5326
5327 /* 010b (write-only) */
5328 WARN_ON((spte & 0x7) == 0x2);
5329
5330 /* 110b (write/execute) */
5331 WARN_ON((spte & 0x7) == 0x6);
5332
5333 /* 100b (execute-only) and value not supported by logical processor */
5334 if (!cpu_has_vmx_ept_execute_only())
5335 WARN_ON((spte & 0x7) == 0x4);
5336
5337 /* not 000b */
5338 if ((spte & 0x7)) {
5339 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5340
5341 if (rsvd_bits != 0) {
5342 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5343 __func__, rsvd_bits);
5344 WARN_ON(1);
5345 }
5346
5347 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5348 u64 ept_mem_type = (spte & 0x38) >> 3;
5349
5350 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5351 ept_mem_type == 7) {
5352 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5353 __func__, ept_mem_type);
5354 WARN_ON(1);
5355 }
5356 }
5357 }
5358}
5359
851ba692 5360static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5361{
5362 u64 sptes[4];
ce88decf 5363 int nr_sptes, i, ret;
68f89400
MT		 5364 gpa_t gpa;
5365
5366 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5367
ce88decf 5368 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
b37fbea6 5369 if (likely(ret == RET_MMIO_PF_EMULATE))
ce88decf
XG		 5370 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5371 EMULATE_DONE;
b37fbea6 5372 if (unlikely(ret == RET_MMIO_PF_RETRY))
ce88decf
XG		 5373 return 1;
5374
5375 /* It is the real ept misconfig */
68f89400
MT		 5376 printk(KERN_ERR "EPT: Misconfiguration.\n");
5377 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5378
5379 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5380
5381 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5382 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5383
851ba692
AK		 5384 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5385 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5386
5387 return 0;
5388}
5389
851ba692 5390static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5391{
5392 u32 cpu_based_vm_exec_control;
5393
5394 /* clear pending NMI */
5395 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5396 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5397 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5398 ++vcpu->stat.nmi_window_exits;
3842d135 5399 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5400
5401 return 1;
5402}
5403
80ced186 5404static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5405{
8b3079a5
AK		 5406 struct vcpu_vmx *vmx = to_vmx(vcpu);
5407 enum emulation_result err = EMULATE_DONE;
80ced186 5408 int ret = 1;
49e9d557
AK		 5409 u32 cpu_exec_ctrl;
5410 bool intr_window_requested;
b8405c18 5411 unsigned count = 130;
49e9d557
AK		 5412
5413 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5414 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5415
b8405c18 5416 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5417 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5418 return handle_interrupt_window(&vmx->vcpu);
5419
de87dcdd
AK		 5420 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5421 return 1;
5422
991eebf9 5423 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5424
80ced186
MG		 5425 if (err == EMULATE_DO_MMIO) {
5426 ret = 0;
5427 goto out;
5428 }
1d5a4d9b 5429
de5f70e0
AK		 5430 if (err != EMULATE_DONE) {
5431 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5432 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5433 vcpu->run->internal.ndata = 0;
6d77dbfc 5434 return 0;
de5f70e0 5435 }
ea953ef0 5436
8d76c49e
GN		 5437 if (vcpu->arch.halt_request) {
5438 vcpu->arch.halt_request = 0;
5439 ret = kvm_emulate_halt(vcpu);
5440 goto out;
5441 }
5442
ea953ef0 5443 if (signal_pending(current))
80ced186 5444 goto out;
ea953ef0
MG		 5445 if (need_resched())
5446 schedule();
5447 }
5448
14168786 5449 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5450out:
5451 return ret;
ea953ef0
MG		 5452}
5453
4b8d54f9
ZE		 5454/*
5455 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5456 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5457 */
9fb41ba8 5458static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5459{
5460 skip_emulated_instruction(vcpu);
5461 kvm_vcpu_on_spin(vcpu);
5462
5463 return 1;
5464}
5465
59708670
SY		 5466static int handle_invalid_op(struct kvm_vcpu *vcpu)
5467{
5468 kvm_queue_exception(vcpu, UD_VECTOR);
5469 return 1;
5470}
5471
ff2f6fe9
NHE		 5472/*
5473 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5474 * We could reuse a single VMCS for all the L2 guests, but we also want the
5475 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5476 * allows keeping them loaded on the processor, and in the future will allow
5477 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5478 * every entry if they never change.
5479 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5480 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5481 *
5482 * The following functions allocate and free a vmcs02 in this pool.
5483 */
5484
5485/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5486static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5487{
5488 struct vmcs02_list *item;
5489 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5490 if (item->vmptr == vmx->nested.current_vmptr) {
5491 list_move(&item->list, &vmx->nested.vmcs02_pool);
5492 return &item->vmcs02;
5493 }
5494
5495 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5496 /* Recycle the least recently used VMCS. */
5497 item = list_entry(vmx->nested.vmcs02_pool.prev,
5498 struct vmcs02_list, list);
5499 item->vmptr = vmx->nested.current_vmptr;
5500 list_move(&item->list, &vmx->nested.vmcs02_pool);
5501 return &item->vmcs02;
5502 }
5503
5504 /* Create a new VMCS */
0fa24ce3 5505 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5506 if (!item)
5507 return NULL;
5508 item->vmcs02.vmcs = alloc_vmcs();
5509 if (!item->vmcs02.vmcs) {
5510 kfree(item);
5511 return NULL;
5512 }
5513 loaded_vmcs_init(&item->vmcs02);
5514 item->vmptr = vmx->nested.current_vmptr;
5515 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5516 vmx->nested.vmcs02_num++;
5517 return &item->vmcs02;
5518}
5519
5520/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5521static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5522{
5523 struct vmcs02_list *item;
5524 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5525 if (item->vmptr == vmptr) {
5526 free_loaded_vmcs(&item->vmcs02);
5527 list_del(&item->list);
5528 kfree(item);
5529 vmx->nested.vmcs02_num--;
5530 return;
5531 }
5532}
5533
5534/*
5535 * Free all VMCSs saved for this vcpu, except the one pointed by
5536 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5537 * currently used, if running L2), and vmcs01 when running L2.
5538 */
5539static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5540{
5541 struct vmcs02_list *item, *n;
5542 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5543 if (vmx->loaded_vmcs != &item->vmcs02)
5544 free_loaded_vmcs(&item->vmcs02);
5545 list_del(&item->list);
5546 kfree(item);
5547 }
5548 vmx->nested.vmcs02_num = 0;
5549
5550 if (vmx->loaded_vmcs != &vmx->vmcs01)
5551 free_loaded_vmcs(&vmx->vmcs01);
5552}
5553
145c28dd
AG		 5554static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5555 u32 vm_instruction_error);
5556
ec378aee
NHE		 5557/*
5558 * Emulate the VMXON instruction.
5559 * Currently, we just remember that VMX is active, and do not save or even
5560 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5561 * do not currently need to store anything in that guest-allocated memory
5562 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5563 * argument is different from the VMXON pointer (which the spec says they do).
5564 */
5565static int handle_vmon(struct kvm_vcpu *vcpu)
5566{
5567 struct kvm_segment cs;
5568 struct vcpu_vmx *vmx = to_vmx(vcpu);
8de48833 5569 struct vmcs *shadow_vmcs;
ec378aee
NHE		 5570
5571 /* The Intel VMX Instruction Reference lists a bunch of bits that
5572 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5573 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5574 * Otherwise, we should fail with #UD. We test these now:
5575 */
5576 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5577 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5578 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5579 kvm_queue_exception(vcpu, UD_VECTOR);
5580 return 1;
5581 }
5582
5583 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5584 if (is_long_mode(vcpu) && !cs.l) {
5585 kvm_queue_exception(vcpu, UD_VECTOR);
5586 return 1;
5587 }
5588
5589 if (vmx_get_cpl(vcpu)) {
5590 kvm_inject_gp(vcpu, 0);
5591 return 1;
5592 }
145c28dd
AG		 5593 if (vmx->nested.vmxon) {
5594 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
5595 skip_emulated_instruction(vcpu);
5596 return 1;
5597 }
8de48833
AG		 5598 if (enable_shadow_vmcs) {
5599 shadow_vmcs = alloc_vmcs();
5600 if (!shadow_vmcs)
5601 return -ENOMEM;
5602 /* mark vmcs as shadow */
5603 shadow_vmcs->revision_id |= (1u << 31);
5604 /* init shadow vmcs */
5605 vmcs_clear(shadow_vmcs);
5606 vmx->nested.current_shadow_vmcs = shadow_vmcs;
5607 }
ec378aee 5608
ff2f6fe9
NHE		 5609 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5610 vmx->nested.vmcs02_num = 0;
5611
ec378aee
NHE		 5612 vmx->nested.vmxon = true;
5613
5614 skip_emulated_instruction(vcpu);
5615 return 1;
5616}
5617
5618/*
5619 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5620 * for running VMX instructions (except VMXON, whose prerequisites are
5621 * slightly different). It also specifies what exception to inject otherwise.
5622 */
5623static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5624{
5625 struct kvm_segment cs;
5626 struct vcpu_vmx *vmx = to_vmx(vcpu);
5627
5628 if (!vmx->nested.vmxon) {
5629 kvm_queue_exception(vcpu, UD_VECTOR);
5630 return 0;
5631 }
5632
5633 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5634 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5635 (is_long_mode(vcpu) && !cs.l)) {
5636 kvm_queue_exception(vcpu, UD_VECTOR);
5637 return 0;
5638 }
5639
5640 if (vmx_get_cpl(vcpu)) {
5641 kvm_inject_gp(vcpu, 0);
5642 return 0;
5643 }
5644
5645 return 1;
5646}
5647
e7953d7f
AG		 5648static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
5649{
8a1b9dd0 5650 u32 exec_control;
012f83cb
AG		 5651 if (enable_shadow_vmcs) {
5652 if (vmx->nested.current_vmcs12 != NULL) {
5653 /* copy to memory all shadowed fields in case
5654 they were modified */
5655 copy_shadow_to_vmcs12(vmx);
5656 vmx->nested.sync_shadow_vmcs = false;
8a1b9dd0
AG		 5657 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5658 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
5659 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
5660 vmcs_write64(VMCS_LINK_POINTER, -1ull);
012f83cb
AG		 5661 }
5662 }
e7953d7f
AG		 5663 kunmap(vmx->nested.current_vmcs12_page);
5664 nested_release_page(vmx->nested.current_vmcs12_page);
5665}
5666
ec378aee
NHE		 5667/*
5668 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5669 * just stops using VMX.
5670 */
5671static void free_nested(struct vcpu_vmx *vmx)
5672{
5673 if (!vmx->nested.vmxon)
5674 return;
5675 vmx->nested.vmxon = false;
a9d30f33 5676 if (vmx->nested.current_vmptr != -1ull) {
e7953d7f 5677 nested_release_vmcs12(vmx);
a9d30f33
NHE		 5678 vmx->nested.current_vmptr = -1ull;
5679 vmx->nested.current_vmcs12 = NULL;
5680 }
e7953d7f
AG		 5681 if (enable_shadow_vmcs)
5682 free_vmcs(vmx->nested.current_shadow_vmcs);
fe3ef05c
NHE		 5683 /* Unpin physical memory we referred to in current vmcs02 */
5684 if (vmx->nested.apic_access_page) {
5685 nested_release_page(vmx->nested.apic_access_page);
5686 vmx->nested.apic_access_page = 0;
5687 }
ff2f6fe9
NHE		 5688
5689 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5690}
5691
5692/* Emulate the VMXOFF instruction */
5693static int handle_vmoff(struct kvm_vcpu *vcpu)
5694{
5695 if (!nested_vmx_check_permission(vcpu))
5696 return 1;
5697 free_nested(to_vmx(vcpu));
5698 skip_emulated_instruction(vcpu);
5699 return 1;
5700}
5701
064aea77
NHE		 5702/*
5703 * Decode the memory-address operand of a vmx instruction, as recorded on an
5704 * exit caused by such an instruction (run by a guest hypervisor).
5705 * On success, returns 0. When the operand is invalid, returns 1 and throws
5706 * #UD or #GP.
5707 */
5708static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5709 unsigned long exit_qualification,
5710 u32 vmx_instruction_info, gva_t *ret)
5711{
5712 /*
5713 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5714 * Execution", on an exit, vmx_instruction_info holds most of the
5715 * addressing components of the operand. Only the displacement part
5716 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5717 * For how an actual address is calculated from all these components,
5718 * refer to Vol. 1, "Operand Addressing".
5719 */
5720 int scaling = vmx_instruction_info & 3;
5721 int addr_size = (vmx_instruction_info >> 7) & 7;
5722 bool is_reg = vmx_instruction_info & (1u << 10);
5723 int seg_reg = (vmx_instruction_info >> 15) & 7;
5724 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5725 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5726 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5727 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5728
5729 if (is_reg) {
5730 kvm_queue_exception(vcpu, UD_VECTOR);
5731 return 1;
5732 }
5733
5734 /* Addr = segment_base + offset */
5735 /* offset = base + [index * scale] + displacement */
5736 *ret = vmx_get_segment_base(vcpu, seg_reg);
5737 if (base_is_valid)
5738 *ret += kvm_register_read(vcpu, base_reg);
5739 if (index_is_valid)
5740 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5741 *ret += exit_qualification; /* holds the displacement */
5742
5743 if (addr_size == 1) /* 32 bit */
5744 *ret &= 0xffffffff;
5745
5746 /*
5747 * TODO: throw #GP (and return 1) in various cases that the VM*
5748 * instructions require it - e.g., offset beyond segment limit,
5749 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5750 * address, and so on. Currently these are not checked.
5751 */
5752 return 0;
5753}
5754
0140caea
NHE		 5755/*
5756 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5757 * set the success or error code of an emulated VMX instruction, as specified
5758 * by Vol 2B, VMX Instruction Reference, "Conventions".
5759 */
5760static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5761{
5762 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5763 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5764 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5765}
5766
5767static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5768{
5769 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5770 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5771 X86_EFLAGS_SF | X86_EFLAGS_OF))
5772 | X86_EFLAGS_CF);
5773}
5774
5775static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5776 u32 vm_instruction_error)
5777{
5778 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5779 /*
5780 * failValid writes the error number to the current VMCS, which
5781 * can't be done there isn't a current VMCS.
5782 */
5783 nested_vmx_failInvalid(vcpu);
5784 return;
5785 }
5786 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5787 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5788 X86_EFLAGS_SF | X86_EFLAGS_OF))
5789 | X86_EFLAGS_ZF);
5790 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
012f83cb
AG		 5791 /*
5792 * We don't need to force a shadow sync because
5793 * VM_INSTRUCTION_ERROR is not shadowed
5794 */
0140caea
NHE		 5795}
5796
27d6c865
NHE		 5797/* Emulate the VMCLEAR instruction */
5798static int handle_vmclear(struct kvm_vcpu *vcpu)
5799{
5800 struct vcpu_vmx *vmx = to_vmx(vcpu);
5801 gva_t gva;
5802 gpa_t vmptr;
5803 struct vmcs12 *vmcs12;
5804 struct page *page;
5805 struct x86_exception e;
5806
5807 if (!nested_vmx_check_permission(vcpu))
5808 return 1;
5809
5810 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5811 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5812 return 1;
5813
5814 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5815 sizeof(vmptr), &e)) {
5816 kvm_inject_page_fault(vcpu, &e);
5817 return 1;
5818 }
5819
5820 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5821 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5822 skip_emulated_instruction(vcpu);
5823 return 1;
5824 }
5825
5826 if (vmptr == vmx->nested.current_vmptr) {
e7953d7f 5827 nested_release_vmcs12(vmx);
27d6c865
NHE		 5828 vmx->nested.current_vmptr = -1ull;
5829 vmx->nested.current_vmcs12 = NULL;
5830 }
5831
5832 page = nested_get_page(vcpu, vmptr);
5833 if (page == NULL) {
5834 /*
5835 * For accurate processor emulation, VMCLEAR beyond available
5836 * physical memory should do nothing at all. However, it is
5837 * possible that a nested vmx bug, not a guest hypervisor bug,
5838 * resulted in this case, so let's shut down before doing any
5839 * more damage:
5840 */
5841 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5842 return 1;
5843 }
5844 vmcs12 = kmap(page);
5845 vmcs12->launch_state = 0;
5846 kunmap(page);
5847 nested_release_page(page);
5848
5849 nested_free_vmcs02(vmx, vmptr);
5850
5851 skip_emulated_instruction(vcpu);
5852 nested_vmx_succeed(vcpu);
5853 return 1;
5854}
5855
cd232ad0
NHE		 5856static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5857
5858/* Emulate the VMLAUNCH instruction */
5859static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5860{
5861 return nested_vmx_run(vcpu, true);
5862}
5863
5864/* Emulate the VMRESUME instruction */
5865static int handle_vmresume(struct kvm_vcpu *vcpu)
5866{
5867
5868 return nested_vmx_run(vcpu, false);
5869}
5870
49f705c5
NHE		 5871enum vmcs_field_type {
5872 VMCS_FIELD_TYPE_U16 = 0,
5873 VMCS_FIELD_TYPE_U64 = 1,
5874 VMCS_FIELD_TYPE_U32 = 2,
5875 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5876};
5877
5878static inline int vmcs_field_type(unsigned long field)
5879{
5880 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5881 return VMCS_FIELD_TYPE_U32;
5882 return (field >> 13) & 0x3 ;
5883}
5884
5885static inline int vmcs_field_readonly(unsigned long field)
5886{
5887 return (((field >> 10) & 0x3) == 1);
5888}
5889
5890/*
5891 * Read a vmcs12 field. Since these can have varying lengths and we return
5892 * one type, we chose the biggest type (u64) and zero-extend the return value
5893 * to that size. Note that the caller, handle_vmread, might need to use only
5894 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5895 * 64-bit fields are to be returned).
5896 */
5897static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5898 unsigned long field, u64 *ret)
5899{
5900 short offset = vmcs_field_to_offset(field);
5901 char *p;
5902
5903 if (offset < 0)
5904 return 0;
5905
5906 p = ((char *)(get_vmcs12(vcpu))) + offset;
5907
5908 switch (vmcs_field_type(field)) {
5909 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5910 *ret = *((natural_width *)p);
5911 return 1;
5912 case VMCS_FIELD_TYPE_U16:
5913 *ret = *((u16 *)p);
5914 return 1;
5915 case VMCS_FIELD_TYPE_U32:
5916 *ret = *((u32 *)p);
5917 return 1;
5918 case VMCS_FIELD_TYPE_U64:
5919 *ret = *((u64 *)p);
5920 return 1;
5921 default:
5922 return 0; /* can never happen. */
5923 }
5924}
5925
20b97fea
AG		 5926
5927static inline bool vmcs12_write_any(struct kvm_vcpu *vcpu,
5928 unsigned long field, u64 field_value){
5929 short offset = vmcs_field_to_offset(field);
5930 char *p = ((char *) get_vmcs12(vcpu)) + offset;
5931 if (offset < 0)
5932 return false;
5933
5934 switch (vmcs_field_type(field)) {
5935 case VMCS_FIELD_TYPE_U16:
5936 *(u16 *)p = field_value;
5937 return true;
5938 case VMCS_FIELD_TYPE_U32:
5939 *(u32 *)p = field_value;
5940 return true;
5941 case VMCS_FIELD_TYPE_U64:
5942 *(u64 *)p = field_value;
5943 return true;
5944 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5945 *(natural_width *)p = field_value;
5946 return true;
5947 default:
5948 return false; /* can never happen. */
5949 }
5950
5951}
5952
16f5b903
AG		 5953static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
5954{
5955 int i;
5956 unsigned long field;
5957 u64 field_value;
5958 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
5959 unsigned long *fields = (unsigned long *)shadow_read_write_fields;
5960 int num_fields = max_shadow_read_write_fields;
5961
5962 vmcs_load(shadow_vmcs);
5963
5964 for (i = 0; i < num_fields; i++) {
5965 field = fields[i];
5966 switch (vmcs_field_type(field)) {
5967 case VMCS_FIELD_TYPE_U16:
5968 field_value = vmcs_read16(field);
5969 break;
5970 case VMCS_FIELD_TYPE_U32:
5971 field_value = vmcs_read32(field);
5972 break;
5973 case VMCS_FIELD_TYPE_U64:
5974 field_value = vmcs_read64(field);
5975 break;
5976 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5977 field_value = vmcs_readl(field);
5978 break;
5979 }
5980 vmcs12_write_any(&vmx->vcpu, field, field_value);
5981 }
5982
5983 vmcs_clear(shadow_vmcs);
5984 vmcs_load(vmx->loaded_vmcs->vmcs);
5985}
5986
c3114420
AG		 5987static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
5988{
5989 unsigned long *fields[] = {
5990 (unsigned long *)shadow_read_write_fields,
5991 (unsigned long *)shadow_read_only_fields
5992 };
5993 int num_lists = ARRAY_SIZE(fields);
5994 int max_fields[] = {
5995 max_shadow_read_write_fields,
5996 max_shadow_read_only_fields
5997 };
5998 int i, q;
5999 unsigned long field;
6000 u64 field_value = 0;
6001 struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
6002
6003 vmcs_load(shadow_vmcs);
6004
6005 for (q = 0; q < num_lists; q++) {
6006 for (i = 0; i < max_fields[q]; i++) {
6007 field = fields[q][i];
6008 vmcs12_read_any(&vmx->vcpu, field, &field_value);
6009
6010 switch (vmcs_field_type(field)) {
6011 case VMCS_FIELD_TYPE_U16:
6012 vmcs_write16(field, (u16)field_value);
6013 break;
6014 case VMCS_FIELD_TYPE_U32:
6015 vmcs_write32(field, (u32)field_value);
6016 break;
6017 case VMCS_FIELD_TYPE_U64:
6018 vmcs_write64(field, (u64)field_value);
6019 break;
6020 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6021 vmcs_writel(field, (long)field_value);
6022 break;
6023 }
6024 }
6025 }
6026
6027 vmcs_clear(shadow_vmcs);
6028 vmcs_load(vmx->loaded_vmcs->vmcs);
6029}
6030
49f705c5
NHE		 6031/*
6032 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6033 * used before) all generate the same failure when it is missing.
6034 */
6035static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
6036{
6037 struct vcpu_vmx *vmx = to_vmx(vcpu);
6038 if (vmx->nested.current_vmptr == -1ull) {
6039 nested_vmx_failInvalid(vcpu);
6040 skip_emulated_instruction(vcpu);
6041 return 0;
6042 }
6043 return 1;
6044}
6045
6046static int handle_vmread(struct kvm_vcpu *vcpu)
6047{
6048 unsigned long field;
6049 u64 field_value;
6050 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6051 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6052 gva_t gva = 0;
6053
6054 if (!nested_vmx_check_permission(vcpu) ||
6055 !nested_vmx_check_vmcs12(vcpu))
6056 return 1;
6057
6058 /* Decode instruction info and find the field to read */
6059 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6060 /* Read the field, zero-extended to a u64 field_value */
6061 if (!vmcs12_read_any(vcpu, field, &field_value)) {
6062 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6063 skip_emulated_instruction(vcpu);
6064 return 1;
6065 }
6066 /*
6067 * Now copy part of this value to register or memory, as requested.
6068 * Note that the number of bits actually copied is 32 or 64 depending
6069 * on the guest's mode (32 or 64 bit), not on the given field's length.
6070 */
6071 if (vmx_instruction_info & (1u << 10)) {
6072 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
6073 field_value);
6074 } else {
6075 if (get_vmx_mem_address(vcpu, exit_qualification,
6076 vmx_instruction_info, &gva))
6077 return 1;
6078 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6079 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
6080 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
6081 }
6082
6083 nested_vmx_succeed(vcpu);
6084 skip_emulated_instruction(vcpu);
6085 return 1;
6086}
6087
6088
6089static int handle_vmwrite(struct kvm_vcpu *vcpu)
6090{
6091 unsigned long field;
6092 gva_t gva;
6093 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6094 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
49f705c5
NHE		 6095 /* The value to write might be 32 or 64 bits, depending on L1's long
6096 * mode, and eventually we need to write that into a field of several
6097 * possible lengths. The code below first zero-extends the value to 64
6098 * bit (field_value), and then copies only the approriate number of
6099 * bits into the vmcs12 field.
6100 */
6101 u64 field_value = 0;
6102 struct x86_exception e;
6103
6104 if (!nested_vmx_check_permission(vcpu) ||
6105 !nested_vmx_check_vmcs12(vcpu))
6106 return 1;
6107
6108 if (vmx_instruction_info & (1u << 10))
6109 field_value = kvm_register_read(vcpu,
6110 (((vmx_instruction_info) >> 3) & 0xf));
6111 else {
6112 if (get_vmx_mem_address(vcpu, exit_qualification,
6113 vmx_instruction_info, &gva))
6114 return 1;
6115 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
6116 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
6117 kvm_inject_page_fault(vcpu, &e);
6118 return 1;
6119 }
6120 }
6121
6122
6123 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
6124 if (vmcs_field_readonly(field)) {
6125 nested_vmx_failValid(vcpu,
6126 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
6127 skip_emulated_instruction(vcpu);
6128 return 1;
6129 }
6130
20b97fea 6131 if (!vmcs12_write_any(vcpu, field, field_value)) {
49f705c5
NHE		 6132 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
6133 skip_emulated_instruction(vcpu);
6134 return 1;
6135 }
6136
6137 nested_vmx_succeed(vcpu);
6138 skip_emulated_instruction(vcpu);
6139 return 1;
6140}
6141
63846663
NHE		 6142/* Emulate the VMPTRLD instruction */
6143static int handle_vmptrld(struct kvm_vcpu *vcpu)
6144{
6145 struct vcpu_vmx *vmx = to_vmx(vcpu);
6146 gva_t gva;
6147 gpa_t vmptr;
6148 struct x86_exception e;
8a1b9dd0 6149 u32 exec_control;
63846663
NHE		 6150
6151 if (!nested_vmx_check_permission(vcpu))
6152 return 1;
6153
6154 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6155 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
6156 return 1;
6157
6158 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6159 sizeof(vmptr), &e)) {
6160 kvm_inject_page_fault(vcpu, &e);
6161 return 1;
6162 }
6163
6164 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
6165 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
6166 skip_emulated_instruction(vcpu);
6167 return 1;
6168 }
6169
6170 if (vmx->nested.current_vmptr != vmptr) {
6171 struct vmcs12 *new_vmcs12;
6172 struct page *page;
6173 page = nested_get_page(vcpu, vmptr);
6174 if (page == NULL) {
6175 nested_vmx_failInvalid(vcpu);
6176 skip_emulated_instruction(vcpu);
6177 return 1;
6178 }
6179 new_vmcs12 = kmap(page);
6180 if (new_vmcs12->revision_id != VMCS12_REVISION) {
6181 kunmap(page);
6182 nested_release_page_clean(page);
6183 nested_vmx_failValid(vcpu,
6184 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
6185 skip_emulated_instruction(vcpu);
6186 return 1;
6187 }
e7953d7f
AG		 6188 if (vmx->nested.current_vmptr != -1ull)
6189 nested_release_vmcs12(vmx);
63846663
NHE		 6190
6191 vmx->nested.current_vmptr = vmptr;
6192 vmx->nested.current_vmcs12 = new_vmcs12;
6193 vmx->nested.current_vmcs12_page = page;
012f83cb 6194 if (enable_shadow_vmcs) {
8a1b9dd0
AG		 6195 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6196 exec_control |= SECONDARY_EXEC_SHADOW_VMCS;
6197 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6198 vmcs_write64(VMCS_LINK_POINTER,
6199 __pa(vmx->nested.current_shadow_vmcs));
012f83cb
AG		 6200 vmx->nested.sync_shadow_vmcs = true;
6201 }
63846663
NHE		 6202 }
6203
6204 nested_vmx_succeed(vcpu);
6205 skip_emulated_instruction(vcpu);
6206 return 1;
6207}
6208
6a4d7550
NHE		 6209/* Emulate the VMPTRST instruction */
6210static int handle_vmptrst(struct kvm_vcpu *vcpu)
6211{
6212 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6213 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6214 gva_t vmcs_gva;
6215 struct x86_exception e;
6216
6217 if (!nested_vmx_check_permission(vcpu))
6218 return 1;
6219
6220 if (get_vmx_mem_address(vcpu, exit_qualification,
6221 vmx_instruction_info, &vmcs_gva))
6222 return 1;
6223 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6224 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
6225 (void *)&to_vmx(vcpu)->nested.current_vmptr,
6226 sizeof(u64), &e)) {
6227 kvm_inject_page_fault(vcpu, &e);
6228 return 1;
6229 }
6230 nested_vmx_succeed(vcpu);
6231 skip_emulated_instruction(vcpu);
6232 return 1;
6233}
6234
6aa8b732
AK		 6235/*
6236 * The exit handlers return 1 if the exit was handled fully and guest execution
6237 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6238 * to be done to userspace and return 0.
6239 */
772e0318 6240static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 6241 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
6242 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 6243 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 6244 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 6245 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 6246 [EXIT_REASON_CR_ACCESS] = handle_cr,
6247 [EXIT_REASON_DR_ACCESS] = handle_dr,
6248 [EXIT_REASON_CPUID] = handle_cpuid,
6249 [EXIT_REASON_MSR_READ] = handle_rdmsr,
6250 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
6251 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
6252 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 6253 [EXIT_REASON_INVD] = handle_invd,
a7052897 6254 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 6255 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 6256 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 6257 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 6258 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 6259 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 6260 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 6261 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 6262 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 6263 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 6264 [EXIT_REASON_VMOFF] = handle_vmoff,
6265 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 6266 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
6267 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 6268 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 6269 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 6270 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 6271 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 6272 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 6273 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 6274 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
6275 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 6276 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 6277 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
6278 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 6279};
6280
6281static const int kvm_vmx_max_exit_handlers =
50a3485c 6282 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 6283
908a7bdd
JK		 6284static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
6285 struct vmcs12 *vmcs12)
6286{
6287 unsigned long exit_qualification;
6288 gpa_t bitmap, last_bitmap;
6289 unsigned int port;
6290 int size;
6291 u8 b;
6292
6293 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
6294 return 1;
6295
6296 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
6297 return 0;
6298
6299 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6300
6301 port = exit_qualification >> 16;
6302 size = (exit_qualification & 7) + 1;
6303
6304 last_bitmap = (gpa_t)-1;
6305 b = -1;
6306
6307 while (size > 0) {
6308 if (port < 0x8000)
6309 bitmap = vmcs12->io_bitmap_a;
6310 else if (port < 0x10000)
6311 bitmap = vmcs12->io_bitmap_b;
6312 else
6313 return 1;
6314 bitmap += (port & 0x7fff) / 8;
6315
6316 if (last_bitmap != bitmap)
6317 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
6318 return 1;
6319 if (b & (1 << (port & 7)))
6320 return 1;
6321
6322 port++;
6323 size--;
6324 last_bitmap = bitmap;
6325 }
6326
6327 return 0;
6328}
6329
644d711a
NHE		 6330/*
6331 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6332 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6333 * disinterest in the current event (read or write a specific MSR) by using an
6334 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6335 */
6336static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
6337 struct vmcs12 *vmcs12, u32 exit_reason)
6338{
6339 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
6340 gpa_t bitmap;
6341
cbd29cb6 6342 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 6343 return 1;
6344
6345 /*
6346 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6347 * for the four combinations of read/write and low/high MSR numbers.
6348 * First we need to figure out which of the four to use:
6349 */
6350 bitmap = vmcs12->msr_bitmap;
6351 if (exit_reason == EXIT_REASON_MSR_WRITE)
6352 bitmap += 2048;
6353 if (msr_index >= 0xc0000000) {
6354 msr_index -= 0xc0000000;
6355 bitmap += 1024;
6356 }
6357
6358 /* Then read the msr_index'th bit from this bitmap: */
6359 if (msr_index < 1024*8) {
6360 unsigned char b;
bd31a7f5
JK		 6361 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6362 return 1;
644d711a
NHE		 6363 return 1 & (b >> (msr_index & 7));
6364 } else
6365 return 1; /* let L1 handle the wrong parameter */
6366}
6367
6368/*
6369 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6370 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6371 * intercept (via guest_host_mask etc.) the current event.
6372 */
6373static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6374 struct vmcs12 *vmcs12)
6375{
6376 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6377 int cr = exit_qualification & 15;
6378 int reg = (exit_qualification >> 8) & 15;
6379 unsigned long val = kvm_register_read(vcpu, reg);
6380
6381 switch ((exit_qualification >> 4) & 3) {
6382 case 0: /* mov to cr */
6383 switch (cr) {
6384 case 0:
6385 if (vmcs12->cr0_guest_host_mask &
6386 (val ^ vmcs12->cr0_read_shadow))
6387 return 1;
6388 break;
6389 case 3:
6390 if ((vmcs12->cr3_target_count >= 1 &&
6391 vmcs12->cr3_target_value0 == val) ||
6392 (vmcs12->cr3_target_count >= 2 &&
6393 vmcs12->cr3_target_value1 == val) ||
6394 (vmcs12->cr3_target_count >= 3 &&
6395 vmcs12->cr3_target_value2 == val) ||
6396 (vmcs12->cr3_target_count >= 4 &&
6397 vmcs12->cr3_target_value3 == val))
6398 return 0;
6399 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6400 return 1;
6401 break;
6402 case 4:
6403 if (vmcs12->cr4_guest_host_mask &
6404 (vmcs12->cr4_read_shadow ^ val))
6405 return 1;
6406 break;
6407 case 8:
6408 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6409 return 1;
6410 break;
6411 }
6412 break;
6413 case 2: /* clts */
6414 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6415 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6416 return 1;
6417 break;
6418 case 1: /* mov from cr */
6419 switch (cr) {
6420 case 3:
6421 if (vmcs12->cpu_based_vm_exec_control &
6422 CPU_BASED_CR3_STORE_EXITING)
6423 return 1;
6424 break;
6425 case 8:
6426 if (vmcs12->cpu_based_vm_exec_control &
6427 CPU_BASED_CR8_STORE_EXITING)
6428 return 1;
6429 break;
6430 }
6431 break;
6432 case 3: /* lmsw */
6433 /*
6434 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6435 * cr0. Other attempted changes are ignored, with no exit.
6436 */
6437 if (vmcs12->cr0_guest_host_mask & 0xe &
6438 (val ^ vmcs12->cr0_read_shadow))
6439 return 1;
6440 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6441 !(vmcs12->cr0_read_shadow & 0x1) &&
6442 (val & 0x1))
6443 return 1;
6444 break;
6445 }
6446 return 0;
6447}
6448
6449/*
6450 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6451 * should handle it ourselves in L0 (and then continue L2). Only call this
6452 * when in is_guest_mode (L2).
6453 */
6454static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6455{
644d711a
NHE		 6456 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6457 struct vcpu_vmx *vmx = to_vmx(vcpu);
6458 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6459 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6460
6461 if (vmx->nested.nested_run_pending)
6462 return 0;
6463
6464 if (unlikely(vmx->fail)) {
bd80158a
JK		 6465 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6466 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6467 return 1;
6468 }
6469
6470 switch (exit_reason) {
6471 case EXIT_REASON_EXCEPTION_NMI:
6472 if (!is_exception(intr_info))
6473 return 0;
6474 else if (is_page_fault(intr_info))
6475 return enable_ept;
6476 return vmcs12->exception_bitmap &
6477 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6478 case EXIT_REASON_EXTERNAL_INTERRUPT:
6479 return 0;
6480 case EXIT_REASON_TRIPLE_FAULT:
6481 return 1;
6482 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6483 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6484 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6485 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6486 case EXIT_REASON_TASK_SWITCH:
6487 return 1;
6488 case EXIT_REASON_CPUID:
6489 return 1;
6490 case EXIT_REASON_HLT:
6491 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6492 case EXIT_REASON_INVD:
6493 return 1;
6494 case EXIT_REASON_INVLPG:
6495 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6496 case EXIT_REASON_RDPMC:
6497 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6498 case EXIT_REASON_RDTSC:
6499 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6500 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6501 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6502 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6503 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6504 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6505 /*
6506 * VMX instructions trap unconditionally. This allows L1 to
6507 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6508 */
6509 return 1;
6510 case EXIT_REASON_CR_ACCESS:
6511 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6512 case EXIT_REASON_DR_ACCESS:
6513 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6514 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6515 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6516 case EXIT_REASON_MSR_READ:
6517 case EXIT_REASON_MSR_WRITE:
6518 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6519 case EXIT_REASON_INVALID_STATE:
6520 return 1;
6521 case EXIT_REASON_MWAIT_INSTRUCTION:
6522 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6523 case EXIT_REASON_MONITOR_INSTRUCTION:
6524 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6525 case EXIT_REASON_PAUSE_INSTRUCTION:
6526 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6527 nested_cpu_has2(vmcs12,
6528 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6529 case EXIT_REASON_MCE_DURING_VMENTRY:
6530 return 0;
6531 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6532 return 1;
6533 case EXIT_REASON_APIC_ACCESS:
6534 return nested_cpu_has2(vmcs12,
6535 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6536 case EXIT_REASON_EPT_VIOLATION:
6537 case EXIT_REASON_EPT_MISCONFIG:
6538 return 0;
0238ea91
JK		 6539 case EXIT_REASON_PREEMPTION_TIMER:
6540 return vmcs12->pin_based_vm_exec_control &
6541 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6542 case EXIT_REASON_WBINVD:
6543 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6544 case EXIT_REASON_XSETBV:
6545 return 1;
6546 default:
6547 return 1;
6548 }
6549}
6550
586f9607
AK		 6551static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6552{
6553 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6554 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6555}
6556
6aa8b732
AK		 6557/*
6558 * The guest has exited. See if we can fix it or if we need userspace
6559 * assistance.
6560 */
851ba692 6561static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6562{
29bd8a78 6563 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6564 u32 exit_reason = vmx->exit_reason;
1155f76a 6565 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6566
80ced186 6567 /* If guest state is invalid, start emulating */
14168786 6568 if (vmx->emulation_required)
80ced186 6569 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6570
b6f1250e
NHE		 6571 /*
6572 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6573 * we did not inject a still-pending event to L1 now because of
6574 * nested_run_pending, we need to re-enable this bit.
6575 */
6576 if (vmx->nested.nested_run_pending)
6577 kvm_make_request(KVM_REQ_EVENT, vcpu);
6578
509c75ea
NHE		 6579 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6580 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6581 vmx->nested.nested_run_pending = 1;
6582 else
6583 vmx->nested.nested_run_pending = 0;
6584
6585 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6586 nested_vmx_vmexit(vcpu);
6587 return 1;
6588 }
6589
5120702e
MG		 6590 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6591 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6592 vcpu->run->fail_entry.hardware_entry_failure_reason
6593 = exit_reason;
6594 return 0;
6595 }
6596
29bd8a78 6597 if (unlikely(vmx->fail)) {
851ba692
AK		 6598 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6599 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6600 = vmcs_read32(VM_INSTRUCTION_ERROR);
6601 return 0;
6602 }
6aa8b732 6603
b9bf6882
XG		 6604 /*
6605 * Note:
6606 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6607 * delivery event since it indicates guest is accessing MMIO.
6608 * The vm-exit can be triggered again after return to guest that
6609 * will cause infinite loop.
6610 */
d77c26fc 6611 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6612 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6613 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6614 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6615 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6616 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6617 vcpu->run->internal.ndata = 2;
6618 vcpu->run->internal.data[0] = vectoring_info;
6619 vcpu->run->internal.data[1] = exit_reason;
6620 return 0;
6621 }
3b86cd99 6622
644d711a
NHE		 6623 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6624 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6625 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6626 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6627 vmx->soft_vnmi_blocked = 0;
3b86cd99 6628 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6629 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6630 /*
6631 * This CPU don't support us in finding the end of an
6632 * NMI-blocked window if the guest runs with IRQs
6633 * disabled. So we pull the trigger after 1 s of
6634 * futile waiting, but inform the user about this.
6635 */
6636 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6637 "state on VCPU %d after 1 s timeout\n",
6638 __func__, vcpu->vcpu_id);
6639 vmx->soft_vnmi_blocked = 0;
3b86cd99 6640 }
3b86cd99
JK		 6641 }
6642
6aa8b732
AK		 6643 if (exit_reason < kvm_vmx_max_exit_handlers
6644 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6645 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6646 else {
851ba692
AK		 6647 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6648 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6649 }
6650 return 0;
6651}
6652
95ba8273 6653static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6654{
95ba8273 6655 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6656 vmcs_write32(TPR_THRESHOLD, 0);
6657 return;
6658 }
6659
95ba8273 6660 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6661}
6662
8d14695f
YZ		 6663static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6664{
6665 u32 sec_exec_control;
6666
6667 /*
6668 * There is not point to enable virtualize x2apic without enable
6669 * apicv
6670 */
c7c9c56c
YZ		 6671 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6672 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6673 return;
6674
6675 if (!vm_need_tpr_shadow(vcpu->kvm))
6676 return;
6677
6678 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6679
6680 if (set) {
6681 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6682 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6683 } else {
6684 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6685 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6686 }
6687 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6688
6689 vmx_set_msr_bitmap(vcpu);
6690}
6691
c7c9c56c
YZ		 6692static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6693{
6694 u16 status;
6695 u8 old;
6696
6697 if (!vmx_vm_has_apicv(kvm))
6698 return;
6699
6700 if (isr == -1)
6701 isr = 0;
6702
6703 status = vmcs_read16(GUEST_INTR_STATUS);
6704 old = status >> 8;
6705 if (isr != old) {
6706 status &= 0xff;
6707 status |= isr << 8;
6708 vmcs_write16(GUEST_INTR_STATUS, status);
6709 }
6710}
6711
6712static void vmx_set_rvi(int vector)
6713{
6714 u16 status;
6715 u8 old;
6716
6717 status = vmcs_read16(GUEST_INTR_STATUS);
6718 old = (u8)status & 0xff;
6719 if ((u8)vector != old) {
6720 status &= ~0xff;
6721 status |= (u8)vector;
6722 vmcs_write16(GUEST_INTR_STATUS, status);
6723 }
6724}
6725
6726static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6727{
6728 if (max_irr == -1)
6729 return;
6730
6731 vmx_set_rvi(max_irr);
6732}
6733
6734static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6735{
3d81bc7e
YZ		 6736 if (!vmx_vm_has_apicv(vcpu->kvm))
6737 return;
6738
c7c9c56c
YZ		 6739 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6740 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6741 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6742 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6743}
6744
51aa01d1 6745static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6746{
00eba012
AK		 6747 u32 exit_intr_info;
6748
6749 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6750 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6751 return;
6752
c5ca8e57 6753 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6754 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6755
6756 /* Handle machine checks before interrupts are enabled */
00eba012 6757 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6758 kvm_machine_check();
6759
20f65983 6760 /* We need to handle NMIs before interrupts are enabled */
00eba012 6761 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6762 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6763 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6764 asm("int $2");
ff9d07a0
ZY		 6765 kvm_after_handle_nmi(&vmx->vcpu);
6766 }
51aa01d1 6767}
20f65983 6768
a547c6db
YZ		 6769static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6770{
6771 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6772
6773 /*
6774 * If external interrupt exists, IF bit is set in rflags/eflags on the
6775 * interrupt stack frame, and interrupt will be enabled on a return
6776 * from interrupt handler.
6777 */
6778 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6779 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6780 unsigned int vector;
6781 unsigned long entry;
6782 gate_desc *desc;
6783 struct vcpu_vmx *vmx = to_vmx(vcpu);
6784#ifdef CONFIG_X86_64
6785 unsigned long tmp;
6786#endif
6787
6788 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6789 desc = (gate_desc *)vmx->host_idt_base + vector;
6790 entry = gate_offset(*desc);
6791 asm volatile(
6792#ifdef CONFIG_X86_64
6793 "mov %%" _ASM_SP ", %[sp]\n\t"
6794 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6795 "push $%c[ss]\n\t"
6796 "push %[sp]\n\t"
6797#endif
6798 "pushf\n\t"
6799 "orl $0x200, (%%" _ASM_SP ")\n\t"
6800 __ASM_SIZE(push) " $%c[cs]\n\t"
6801 "call *%[entry]\n\t"
6802 :
6803#ifdef CONFIG_X86_64
6804 [sp]"=&r"(tmp)
6805#endif
6806 :
6807 [entry]"r"(entry),
6808 [ss]"i"(__KERNEL_DS),
6809 [cs]"i"(__KERNEL_CS)
6810 );
6811 } else
6812 local_irq_enable();
6813}
6814
51aa01d1
AK		 6815static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6816{
c5ca8e57 6817 u32 exit_intr_info;
51aa01d1
AK		 6818 bool unblock_nmi;
6819 u8 vector;
6820 bool idtv_info_valid;
6821
6822 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6823
cf393f75 6824 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6825 if (vmx->nmi_known_unmasked)
6826 return;
c5ca8e57
AK		 6827 /*
6828 * Can't use vmx->exit_intr_info since we're not sure what
6829 * the exit reason is.
6830 */
6831 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6832 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6833 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6834 /*
7b4a25cb 6835 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6836 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6837 * a guest IRET fault.
7b4a25cb
GN		 6838 * SDM 3: 23.2.2 (September 2008)
6839 * Bit 12 is undefined in any of the following cases:
6840 * If the VM exit sets the valid bit in the IDT-vectoring
6841 * information field.
6842 * If the VM exit is due to a double fault.
cf393f75 6843 */
7b4a25cb
GN		 6844 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6845 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6846 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6847 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6848 else
6849 vmx->nmi_known_unmasked =
6850 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6851 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6852 } else if (unlikely(vmx->soft_vnmi_blocked))
6853 vmx->vnmi_blocked_time +=
6854 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6855}
6856
3ab66e8a 6857static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6858 u32 idt_vectoring_info,
6859 int instr_len_field,
6860 int error_code_field)
51aa01d1 6861{
51aa01d1
AK		 6862 u8 vector;
6863 int type;
6864 bool idtv_info_valid;
6865
6866 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6867
3ab66e8a
JK		 6868 vcpu->arch.nmi_injected = false;
6869 kvm_clear_exception_queue(vcpu);
6870 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6871
6872 if (!idtv_info_valid)
6873 return;
6874
3ab66e8a 6875 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6876
668f612f
AK		 6877 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6878 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6879
64a7ec06 6880 switch (type) {
37b96e98 6881 case INTR_TYPE_NMI_INTR:
3ab66e8a 6882 vcpu->arch.nmi_injected = true;
668f612f 6883 /*
7b4a25cb 6884 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6885 * Clear bit "block by NMI" before VM entry if a NMI
6886 * delivery faulted.
668f612f 6887 */
3ab66e8a 6888 vmx_set_nmi_mask(vcpu, false);
37b96e98 6889 break;
37b96e98 6890 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6891 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6892 /* fall through */
6893 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6894 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6895 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6896 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6897 } else
3ab66e8a 6898 kvm_queue_exception(vcpu, vector);
37b96e98 6899 break;
66fd3f7f 6900 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6901 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6902 /* fall through */
37b96e98 6903 case INTR_TYPE_EXT_INTR:
3ab66e8a 6904 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6905 break;
6906 default:
6907 break;
f7d9238f 6908 }
cf393f75
AK		 6909}
6910
83422e17
AK		 6911static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6912{
3ab66e8a 6913 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6914 VM_EXIT_INSTRUCTION_LEN,
6915 IDT_VECTORING_ERROR_CODE);
6916}
6917
b463a6f7
AK		 6918static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6919{
3ab66e8a 6920 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6921 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6922 VM_ENTRY_INSTRUCTION_LEN,
6923 VM_ENTRY_EXCEPTION_ERROR_CODE);
6924
6925 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6926}
6927
d7cd9796
GN		 6928static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6929{
6930 int i, nr_msrs;
6931 struct perf_guest_switch_msr *msrs;
6932
6933 msrs = perf_guest_get_msrs(&nr_msrs);
6934
6935 if (!msrs)
6936 return;
6937
6938 for (i = 0; i < nr_msrs; i++)
6939 if (msrs[i].host == msrs[i].guest)
6940 clear_atomic_switch_msr(vmx, msrs[i].msr);
6941 else
6942 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6943 msrs[i].host);
6944}
6945
a3b5ba49 6946static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6947{
a2fa3e9f 6948 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6949 unsigned long debugctlmsr;
104f226b
AK		 6950
6951 /* Record the guest's net vcpu time for enforced NMI injections. */
6952 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6953 vmx->entry_time = ktime_get();
6954
6955 /* Don't enter VMX if guest state is invalid, let the exit handler
6956 start emulation until we arrive back to a valid state */
14168786 6957 if (vmx->emulation_required)
104f226b
AK		 6958 return;
6959
012f83cb
AG		 6960 if (vmx->nested.sync_shadow_vmcs) {
6961 copy_vmcs12_to_shadow(vmx);
6962 vmx->nested.sync_shadow_vmcs = false;
6963 }
6964
104f226b
AK		 6965 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6966 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6967 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6968 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6969
6970 /* When single-stepping over STI and MOV SS, we must clear the
6971 * corresponding interruptibility bits in the guest state. Otherwise
6972 * vmentry fails as it then expects bit 14 (BS) in pending debug
6973 * exceptions being set, but that's not correct for the guest debugging
6974 * case. */
6975 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6976 vmx_set_interrupt_shadow(vcpu, 0);
6977
d7cd9796 6978 atomic_switch_perf_msrs(vmx);
2a7921b7 6979 debugctlmsr = get_debugctlmsr();
d7cd9796 6980
d462b819 6981 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6982 asm(
6aa8b732 6983 /* Store host registers */
b188c81f
AK		 6984 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6985 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6986 "push %%" _ASM_CX " \n\t"
6987 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6988 "je 1f \n\t"
b188c81f 6989 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6990 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6991 "1: \n\t"
d3edefc0 6992 /* Reload cr2 if changed */
b188c81f
AK		 6993 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6994 "mov %%cr2, %%" _ASM_DX " \n\t"
6995 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6996 "je 2f \n\t"
b188c81f 6997 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6998 "2: \n\t"
6aa8b732 6999 /* Check if vmlaunch of vmresume is needed */
e08aa78a 7000 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 7001 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 7002 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
7003 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
7004 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
7005 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
7006 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
7007 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 7008#ifdef CONFIG_X86_64
e08aa78a
AK		 7009 "mov %c[r8](%0), %%r8 \n\t"
7010 "mov %c[r9](%0), %%r9 \n\t"
7011 "mov %c[r10](%0), %%r10 \n\t"
7012 "mov %c[r11](%0), %%r11 \n\t"
7013 "mov %c[r12](%0), %%r12 \n\t"
7014 "mov %c[r13](%0), %%r13 \n\t"
7015 "mov %c[r14](%0), %%r14 \n\t"
7016 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 7017#endif
b188c81f 7018 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 7019
6aa8b732 7020 /* Enter guest mode */
83287ea4 7021 "jne 1f \n\t"
4ecac3fd 7022 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 7023 "jmp 2f \n\t"
7024 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
7025 "2: "
6aa8b732 7026 /* Save guest registers, load host registers, keep flags */
b188c81f 7027 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 7028 "pop %0 \n\t"
b188c81f
AK		 7029 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
7030 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
7031 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
7032 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
7033 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
7034 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
7035 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 7036#ifdef CONFIG_X86_64
e08aa78a
AK		 7037 "mov %%r8, %c[r8](%0) \n\t"
7038 "mov %%r9, %c[r9](%0) \n\t"
7039 "mov %%r10, %c[r10](%0) \n\t"
7040 "mov %%r11, %c[r11](%0) \n\t"
7041 "mov %%r12, %c[r12](%0) \n\t"
7042 "mov %%r13, %c[r13](%0) \n\t"
7043 "mov %%r14, %c[r14](%0) \n\t"
7044 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 7045#endif
b188c81f
AK		 7046 "mov %%cr2, %%" _ASM_AX " \n\t"
7047 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 7048
b188c81f 7049 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 7050 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 7051 ".pushsection .rodata \n\t"
7052 ".global vmx_return \n\t"
7053 "vmx_return: " _ASM_PTR " 2b \n\t"
7054 ".popsection"
e08aa78a 7055 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 7056 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 7057 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 7058 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 7059 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
7060 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
7061 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
7062 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
7063 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
7064 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
7065 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 7066#ifdef CONFIG_X86_64
ad312c7c
ZX		 7067 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
7068 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
7069 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
7070 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
7071 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
7072 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
7073 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
7074 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 7075#endif
40712fae
AK		 7076 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
7077 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 7078 : "cc", "memory"
7079#ifdef CONFIG_X86_64
b188c81f 7080 , "rax", "rbx", "rdi", "rsi"
c2036300 7081 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 7082#else
7083 , "eax", "ebx", "edi", "esi"
c2036300
LV		 7084#endif
7085 );
6aa8b732 7086
2a7921b7
GN		 7087 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7088 if (debugctlmsr)
7089 update_debugctlmsr(debugctlmsr);
7090
aa67f609
AK		 7091#ifndef CONFIG_X86_64
7092 /*
7093 * The sysexit path does not restore ds/es, so we must set them to
7094 * a reasonable value ourselves.
7095 *
7096 * We can't defer this to vmx_load_host_state() since that function
7097 * may be executed in interrupt context, which saves and restore segments
7098 * around it, nullifying its effect.
7099 */
7100 loadsegment(ds, __USER_DS);
7101 loadsegment(es, __USER_DS);
7102#endif
7103
6de4f3ad 7104 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 7105 | (1 << VCPU_EXREG_RFLAGS)
69c73028 7106 | (1 << VCPU_EXREG_CPL)
aff48baa 7107 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 7108 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 7109 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 7110 vcpu->arch.regs_dirty = 0;
7111
1155f76a
AK		 7112 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
7113
d462b819 7114 vmx->loaded_vmcs->launched = 1;
1b6269db 7115
51aa01d1 7116 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 7117 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 7118
7119 vmx_complete_atomic_exit(vmx);
7120 vmx_recover_nmi_blocking(vmx);
cf393f75 7121 vmx_complete_interrupts(vmx);
6aa8b732
AK		 7122}
7123
6aa8b732
AK		 7124static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
7125{
fb3f0f51
RR		 7126 struct vcpu_vmx *vmx = to_vmx(vcpu);
7127
cdbecfc3 7128 free_vpid(vmx);
ec378aee 7129 free_nested(vmx);
d462b819 7130 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 7131 kfree(vmx->guest_msrs);
7132 kvm_vcpu_uninit(vcpu);
a4770347 7133 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 7134}
7135
fb3f0f51 7136static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 7137{
fb3f0f51 7138 int err;
c16f862d 7139 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 7140 int cpu;
6aa8b732 7141
a2fa3e9f 7142 if (!vmx)
fb3f0f51
RR		 7143 return ERR_PTR(-ENOMEM);
7144
2384d2b3
SY		 7145 allocate_vpid(vmx);
7146
fb3f0f51
RR		 7147 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
7148 if (err)
7149 goto free_vcpu;
965b58a5 7150
a2fa3e9f 7151 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 7152 err = -ENOMEM;
fb3f0f51 7153 if (!vmx->guest_msrs) {
fb3f0f51
RR		 7154 goto uninit_vcpu;
7155 }
965b58a5 7156
d462b819
NHE		 7157 vmx->loaded_vmcs = &vmx->vmcs01;
7158 vmx->loaded_vmcs->vmcs = alloc_vmcs();
7159 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 7160 goto free_msrs;
d462b819
NHE		 7161 if (!vmm_exclusive)
7162 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
7163 loaded_vmcs_init(vmx->loaded_vmcs);
7164 if (!vmm_exclusive)
7165 kvm_cpu_vmxoff();
a2fa3e9f 7166
15ad7146
AK		 7167 cpu = get_cpu();
7168 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 7169 vmx->vcpu.cpu = cpu;
8b9cf98c 7170 err = vmx_vcpu_setup(vmx);
fb3f0f51 7171 vmx_vcpu_put(&vmx->vcpu);
15ad7146 7172 put_cpu();
fb3f0f51
RR		 7173 if (err)
7174 goto free_vmcs;
a63cb560 7175 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 7176 err = alloc_apic_access_page(kvm);
7177 if (err)
5e4a0b3c 7178 goto free_vmcs;
a63cb560 7179 }
fb3f0f51 7180
b927a3ce
SY		 7181 if (enable_ept) {
7182 if (!kvm->arch.ept_identity_map_addr)
7183 kvm->arch.ept_identity_map_addr =
7184 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 7185 err = -ENOMEM;
b7ebfb05
SY		 7186 if (alloc_identity_pagetable(kvm) != 0)
7187 goto free_vmcs;
93ea5388
GN		 7188 if (!init_rmode_identity_map(kvm))
7189 goto free_vmcs;
b927a3ce 7190 }
b7ebfb05 7191
a9d30f33
NHE		 7192 vmx->nested.current_vmptr = -1ull;
7193 vmx->nested.current_vmcs12 = NULL;
7194
fb3f0f51
RR		 7195 return &vmx->vcpu;
7196
7197free_vmcs:
5f3fbc34 7198 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 7199free_msrs:
fb3f0f51
RR		 7200 kfree(vmx->guest_msrs);
7201uninit_vcpu:
7202 kvm_vcpu_uninit(&vmx->vcpu);
7203free_vcpu:
cdbecfc3 7204 free_vpid(vmx);
a4770347 7205 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 7206 return ERR_PTR(err);
6aa8b732
AK		 7207}
7208
002c7f7c
YS		 7209static void __init vmx_check_processor_compat(void *rtn)
7210{
7211 struct vmcs_config vmcs_conf;
7212
7213 *(int *)rtn = 0;
7214 if (setup_vmcs_config(&vmcs_conf) < 0)
7215 *(int *)rtn = -EIO;
7216 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
7217 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
7218 smp_processor_id());
7219 *(int *)rtn = -EIO;
7220 }
7221}
7222
67253af5
SY		 7223static int get_ept_level(void)
7224{
7225 return VMX_EPT_DEFAULT_GAW + 1;
7226}
7227
4b12f0de 7228static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 7229{
4b12f0de
SY		 7230 u64 ret;
7231
522c68c4
SY		 7232 /* For VT-d and EPT combination
7233 * 1. MMIO: always map as UC
7234 * 2. EPT with VT-d:
7235 * a. VT-d without snooping control feature: can't guarantee the
7236 * result, try to trust guest.
7237 * b. VT-d with snooping control feature: snooping control feature of
7238 * VT-d engine can guarantee the cache correctness. Just set it
7239 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 7240 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 7241 * consistent with host MTRR
7242 */
4b12f0de
SY		 7243 if (is_mmio)
7244 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 7245 else if (vcpu->kvm->arch.iommu_domain &&
7246 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
7247 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
7248 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 7249 else
522c68c4 7250 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 7251 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 7252
7253 return ret;
64d4d521
SY		 7254}
7255
17cc3935 7256static int vmx_get_lpage_level(void)
344f414f 7257{
878403b7
SY		 7258 if (enable_ept && !cpu_has_vmx_ept_1g_page())
7259 return PT_DIRECTORY_LEVEL;
7260 else
7261 /* For shadow and EPT supported 1GB page */
7262 return PT_PDPE_LEVEL;
344f414f
JR		 7263}
7264
0e851880
SY		 7265static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
7266{
4e47c7a6
SY		 7267 struct kvm_cpuid_entry2 *best;
7268 struct vcpu_vmx *vmx = to_vmx(vcpu);
7269 u32 exec_control;
7270
7271 vmx->rdtscp_enabled = false;
7272 if (vmx_rdtscp_supported()) {
7273 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7274 if (exec_control & SECONDARY_EXEC_RDTSCP) {
7275 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
7276 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
7277 vmx->rdtscp_enabled = true;
7278 else {
7279 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7280 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7281 exec_control);
7282 }
7283 }
7284 }
ad756a16 7285
ad756a16
MJ		 7286 /* Exposing INVPCID only when PCID is exposed */
7287 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
7288 if (vmx_invpcid_supported() &&
4f977045 7289 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 7290 guest_cpuid_has_pcid(vcpu)) {
29282fde 7291 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 7292 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
7293 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7294 exec_control);
7295 } else {
29282fde
TI		 7296 if (cpu_has_secondary_exec_ctrls()) {
7297 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7298 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
7299 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
7300 exec_control);
7301 }
ad756a16 7302 if (best)
4f977045 7303 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 7304 }
0e851880
SY		 7305}
7306
d4330ef2
JR		 7307static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
7308{
7b8050f5
NHE		 7309 if (func == 1 && nested)
7310 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 7311}
7312
fe3ef05c
NHE		 7313/*
7314 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7315 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7316 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7317 * guest in a way that will both be appropriate to L1's requests, and our
7318 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7319 * function also has additional necessary side-effects, like setting various
7320 * vcpu->arch fields.
7321 */
7322static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7323{
7324 struct vcpu_vmx *vmx = to_vmx(vcpu);
7325 u32 exec_control;
7326
7327 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
7328 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
7329 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
7330 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
7331 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
7332 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
7333 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
7334 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
7335 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
7336 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
7337 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
7338 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
7339 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
7340 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
7341 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
7342 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
7343 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
7344 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
7345 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
7346 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
7347 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
7348 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
7349 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
7350 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
7351 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
7352 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
7353 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
7354 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
7355 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
7356 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
7357 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
7358 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
7359 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
7360 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
7361 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
7362 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
7363
7364 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
7365 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
7366 vmcs12->vm_entry_intr_info_field);
7367 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
7368 vmcs12->vm_entry_exception_error_code);
7369 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7370 vmcs12->vm_entry_instruction_len);
7371 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7372 vmcs12->guest_interruptibility_info);
fe3ef05c 7373 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7374 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
fe3ef05c
NHE		 7375 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7376 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7377 vmcs12->guest_pending_dbg_exceptions);
7378 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7379 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7380
7381 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7382
7383 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7384 (vmcs_config.pin_based_exec_ctrl |
7385 vmcs12->pin_based_vm_exec_control));
7386
0238ea91
JK		 7387 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7388 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7389 vmcs12->vmx_preemption_timer_value);
7390
fe3ef05c
NHE		 7391 /*
7392 * Whether page-faults are trapped is determined by a combination of
7393 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7394 * If enable_ept, L0 doesn't care about page faults and we should
7395 * set all of these to L1's desires. However, if !enable_ept, L0 does
7396 * care about (at least some) page faults, and because it is not easy
7397 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7398 * to exit on each and every L2 page fault. This is done by setting
7399 * MASK=MATCH=0 and (see below) EB.PF=1.
7400 * Note that below we don't need special code to set EB.PF beyond the
7401 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7402 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7403 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7404 *
7405 * A problem with this approach (when !enable_ept) is that L1 may be
7406 * injected with more page faults than it asked for. This could have
7407 * caused problems, but in practice existing hypervisors don't care.
7408 * To fix this, we will need to emulate the PFEC checking (on the L1
7409 * page tables), using walk_addr(), when injecting PFs to L1.
7410 */
7411 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7412 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7413 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7414 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7415
7416 if (cpu_has_secondary_exec_ctrls()) {
7417 u32 exec_control = vmx_secondary_exec_control(vmx);
7418 if (!vmx->rdtscp_enabled)
7419 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7420 /* Take the following fields only from vmcs12 */
7421 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7422 if (nested_cpu_has(vmcs12,
7423 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7424 exec_control |= vmcs12->secondary_vm_exec_control;
7425
7426 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7427 /*
7428 * Translate L1 physical address to host physical
7429 * address for vmcs02. Keep the page pinned, so this
7430 * physical address remains valid. We keep a reference
7431 * to it so we can release it later.
7432 */
7433 if (vmx->nested.apic_access_page) /* shouldn't happen */
7434 nested_release_page(vmx->nested.apic_access_page);
7435 vmx->nested.apic_access_page =
7436 nested_get_page(vcpu, vmcs12->apic_access_addr);
7437 /*
7438 * If translation failed, no matter: This feature asks
7439 * to exit when accessing the given address, and if it
7440 * can never be accessed, this feature won't do
7441 * anything anyway.
7442 */
7443 if (!vmx->nested.apic_access_page)
7444 exec_control &=
7445 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7446 else
7447 vmcs_write64(APIC_ACCESS_ADDR,
7448 page_to_phys(vmx->nested.apic_access_page));
7449 }
7450
7451 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7452 }
7453
7454
7455 /*
7456 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7457 * Some constant fields are set here by vmx_set_constant_host_state().
7458 * Other fields are different per CPU, and will be set later when
7459 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7460 */
a547c6db 7461 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7462
7463 /*
7464 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7465 * entry, but only if the current (host) sp changed from the value
7466 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7467 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7468 * here we just force the write to happen on entry.
7469 */
7470 vmx->host_rsp = 0;
7471
7472 exec_control = vmx_exec_control(vmx); /* L0's desires */
7473 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7474 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7475 exec_control &= ~CPU_BASED_TPR_SHADOW;
7476 exec_control |= vmcs12->cpu_based_vm_exec_control;
7477 /*
7478 * Merging of IO and MSR bitmaps not currently supported.
7479 * Rather, exit every time.
7480 */
7481 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7482 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7483 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7484
7485 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7486
7487 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7488 * bitwise-or of what L1 wants to trap for L2, and what we want to
7489 * trap. Note that CR0.TS also needs updating - we do this later.
7490 */
7491 update_exception_bitmap(vcpu);
7492 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7493 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7494
7495 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7496 vmcs_write32(VM_EXIT_CONTROLS,
7497 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7498 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7499 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7500
7501 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7502 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7503 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7504 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7505
7506
7507 set_cr4_guest_host_mask(vmx);
7508
27fc51b2
NHE		 7509 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7510 vmcs_write64(TSC_OFFSET,
7511 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7512 else
7513 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7514
7515 if (enable_vpid) {
7516 /*
7517 * Trivially support vpid by letting L2s share their parent
7518 * L1's vpid. TODO: move to a more elaborate solution, giving
7519 * each L2 its own vpid and exposing the vpid feature to L1.
7520 */
7521 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7522 vmx_flush_tlb(vcpu);
7523 }
7524
7525 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7526 vcpu->arch.efer = vmcs12->guest_ia32_efer;
d1fa0352 7527 else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
fe3ef05c
NHE		 7528 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7529 else
7530 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7531 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7532 vmx_set_efer(vcpu, vcpu->arch.efer);
7533
7534 /*
7535 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7536 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7537 * The CR0_READ_SHADOW is what L2 should have expected to read given
7538 * the specifications by L1; It's not enough to take
7539 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7540 * have more bits than L1 expected.
7541 */
7542 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7543 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7544
7545 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7546 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7547
7548 /* shadow page tables on either EPT or shadow page tables */
7549 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7550 kvm_mmu_reset_context(vcpu);
7551
7552 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7553 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7554}
7555
cd232ad0
NHE		 7556/*
7557 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7558 * for running an L2 nested guest.
7559 */
7560static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7561{
7562 struct vmcs12 *vmcs12;
7563 struct vcpu_vmx *vmx = to_vmx(vcpu);
7564 int cpu;
7565 struct loaded_vmcs *vmcs02;
384bb783 7566 bool ia32e;
cd232ad0
NHE		 7567
7568 if (!nested_vmx_check_permission(vcpu) ||
7569 !nested_vmx_check_vmcs12(vcpu))
7570 return 1;
7571
7572 skip_emulated_instruction(vcpu);
7573 vmcs12 = get_vmcs12(vcpu);
7574
012f83cb
AG		 7575 if (enable_shadow_vmcs)
7576 copy_shadow_to_vmcs12(vmx);
7577
7c177938
NHE		 7578 /*
7579 * The nested entry process starts with enforcing various prerequisites
7580 * on vmcs12 as required by the Intel SDM, and act appropriately when
7581 * they fail: As the SDM explains, some conditions should cause the
7582 * instruction to fail, while others will cause the instruction to seem
7583 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7584 * To speed up the normal (success) code path, we should avoid checking
7585 * for misconfigurations which will anyway be caught by the processor
7586 * when using the merged vmcs02.
7587 */
7588 if (vmcs12->launch_state == launch) {
7589 nested_vmx_failValid(vcpu,
7590 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7591 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7592 return 1;
7593 }
7594
26539bd0
PB		 7595 if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE) {
7596 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7597 return 1;
7598 }
7599
7c177938
NHE		 7600 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7601 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7602 /*TODO: Also verify bits beyond physical address width are 0*/
7603 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7604 return 1;
7605 }
7606
7607 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7608 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7609 /*TODO: Also verify bits beyond physical address width are 0*/
7610 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7611 return 1;
7612 }
7613
7614 if (vmcs12->vm_entry_msr_load_count > 0 ||
7615 vmcs12->vm_exit_msr_load_count > 0 ||
7616 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7617 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7618 __func__);
7c177938
NHE		 7619 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7620 return 1;
7621 }
7622
7623 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7624 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7625 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7626 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7627 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7628 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7629 !vmx_control_verify(vmcs12->vm_exit_controls,
7630 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7631 !vmx_control_verify(vmcs12->vm_entry_controls,
7632 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7633 {
7634 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7635 return 1;
7636 }
7637
7638 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7639 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7640 nested_vmx_failValid(vcpu,
7641 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7642 return 1;
7643 }
7644
7645 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7646 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7647 nested_vmx_entry_failure(vcpu, vmcs12,
7648 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7649 return 1;
7650 }
7651 if (vmcs12->vmcs_link_pointer != -1ull) {
7652 nested_vmx_entry_failure(vcpu, vmcs12,
7653 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7654 return 1;
7655 }
7656
384bb783 7657 /*
cb0c8cda 7658 * If the load IA32_EFER VM-entry control is 1, the following checks
384bb783
JK		 7659 * are performed on the field for the IA32_EFER MSR:
7660 * - Bits reserved in the IA32_EFER MSR must be 0.
7661 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7662 * the IA-32e mode guest VM-exit control. It must also be identical
7663 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7664 * CR0.PG) is 1.
7665 */
7666 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
7667 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
7668 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
7669 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
7670 ((vmcs12->guest_cr0 & X86_CR0_PG) &&
7671 ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
7672 nested_vmx_entry_failure(vcpu, vmcs12,
7673 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7674 return 1;
7675 }
7676 }
7677
7678 /*
7679 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7680 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7681 * the values of the LMA and LME bits in the field must each be that of
7682 * the host address-space size VM-exit control.
7683 */
7684 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
7685 ia32e = (vmcs12->vm_exit_controls &
7686 VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
7687 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
7688 ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
7689 ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
7690 nested_vmx_entry_failure(vcpu, vmcs12,
7691 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7692 return 1;
7693 }
7694 }
7695
7c177938
NHE		 7696 /*
7697 * We're finally done with prerequisite checking, and can start with
7698 * the nested entry.
7699 */
7700
cd232ad0
NHE		 7701 vmcs02 = nested_get_current_vmcs02(vmx);
7702 if (!vmcs02)
7703 return -ENOMEM;
7704
7705 enter_guest_mode(vcpu);
7706
7707 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7708
7709 cpu = get_cpu();
7710 vmx->loaded_vmcs = vmcs02;
7711 vmx_vcpu_put(vcpu);
7712 vmx_vcpu_load(vcpu, cpu);
7713 vcpu->cpu = cpu;
7714 put_cpu();
7715
36c3cc42
JK		 7716 vmx_segment_cache_clear(vmx);
7717
cd232ad0
NHE		 7718 vmcs12->launch_state = 1;
7719
7720 prepare_vmcs02(vcpu, vmcs12);
7721
7722 /*
7723 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7724 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7725 * returned as far as L1 is concerned. It will only return (and set
7726 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7727 */
7728 return 1;
7729}
7730
4704d0be
NHE		 7731/*
7732 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7733 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7734 * This function returns the new value we should put in vmcs12.guest_cr0.
7735 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7736 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7737 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7738 * didn't trap the bit, because if L1 did, so would L0).
7739 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7740 * been modified by L2, and L1 knows it. So just leave the old value of
7741 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7742 * isn't relevant, because if L0 traps this bit it can set it to anything.
7743 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7744 * changed these bits, and therefore they need to be updated, but L0
7745 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7746 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7747 */
7748static inline unsigned long
7749vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7750{
7751 return
7752 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7753 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7754 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7755 vcpu->arch.cr0_guest_owned_bits));
7756}
7757
7758static inline unsigned long
7759vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7760{
7761 return
7762 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7763 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7764 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7765 vcpu->arch.cr4_guest_owned_bits));
7766}
7767
5f3d5799
JK		 7768static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7769 struct vmcs12 *vmcs12)
7770{
7771 u32 idt_vectoring;
7772 unsigned int nr;
7773
7774 if (vcpu->arch.exception.pending) {
7775 nr = vcpu->arch.exception.nr;
7776 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7777
7778 if (kvm_exception_is_soft(nr)) {
7779 vmcs12->vm_exit_instruction_len =
7780 vcpu->arch.event_exit_inst_len;
7781 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7782 } else
7783 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7784
7785 if (vcpu->arch.exception.has_error_code) {
7786 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7787 vmcs12->idt_vectoring_error_code =
7788 vcpu->arch.exception.error_code;
7789 }
7790
7791 vmcs12->idt_vectoring_info_field = idt_vectoring;
7792 } else if (vcpu->arch.nmi_pending) {
7793 vmcs12->idt_vectoring_info_field =
7794 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7795 } else if (vcpu->arch.interrupt.pending) {
7796 nr = vcpu->arch.interrupt.nr;
7797 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7798
7799 if (vcpu->arch.interrupt.soft) {
7800 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7801 vmcs12->vm_entry_instruction_len =
7802 vcpu->arch.event_exit_inst_len;
7803 } else
7804 idt_vectoring |= INTR_TYPE_EXT_INTR;
7805
7806 vmcs12->idt_vectoring_info_field = idt_vectoring;
7807 }
7808}
7809
4704d0be
NHE		 7810/*
7811 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7812 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7813 * and this function updates it to reflect the changes to the guest state while
7814 * L2 was running (and perhaps made some exits which were handled directly by L0
7815 * without going back to L1), and to reflect the exit reason.
7816 * Note that we do not have to copy here all VMCS fields, just those that
7817 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7818 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7819 * which already writes to vmcs12 directly.
7820 */
733568f9 7821static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7822{
7823 /* update guest state fields: */
7824 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7825 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7826
7827 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7828 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7829 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7830 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7831
7832 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7833 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7834 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7835 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7836 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7837 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7838 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7839 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7840 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7841 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7842 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7843 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7844 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7845 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7846 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7847 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7848 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7849 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7850 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7851 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7852 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7853 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7854 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7855 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7856 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7857 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7858 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7859 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7860 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7861 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7862 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7863 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7864 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7865 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7866 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7867 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7868
4704d0be
NHE		 7869 vmcs12->guest_interruptibility_info =
7870 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7871 vmcs12->guest_pending_dbg_exceptions =
7872 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7873
c18911a2
JK		 7874 vmcs12->vm_entry_controls =
7875 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7876 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7877
4704d0be
NHE		 7878 /* TODO: These cannot have changed unless we have MSR bitmaps and
7879 * the relevant bit asks not to trap the change */
7880 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 7881 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 7882 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7883 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7884 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7885 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7886
7887 /* update exit information fields: */
7888
957c897e 7889 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7890 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7891
7892 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 7893 if ((vmcs12->vm_exit_intr_info &
7894 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7895 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7896 vmcs12->vm_exit_intr_error_code =
7897 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 7898 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 7899 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7900 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7901
5f3d5799
JK		 7902 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7903 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7904 * instead of reading the real value. */
4704d0be 7905 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 7906
7907 /*
7908 * Transfer the event that L0 or L1 may wanted to inject into
7909 * L2 to IDT_VECTORING_INFO_FIELD.
7910 */
7911 vmcs12_save_pending_event(vcpu, vmcs12);
7912 }
7913
7914 /*
7915 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7916 * preserved above and would only end up incorrectly in L1.
7917 */
7918 vcpu->arch.nmi_injected = false;
7919 kvm_clear_exception_queue(vcpu);
7920 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 7921}
7922
7923/*
7924 * A part of what we need to when the nested L2 guest exits and we want to
7925 * run its L1 parent, is to reset L1's guest state to the host state specified
7926 * in vmcs12.
7927 * This function is to be called not only on normal nested exit, but also on
7928 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7929 * Failures During or After Loading Guest State").
7930 * This function should be called when the active VMCS is L1's (vmcs01).
7931 */
733568f9
JK		 7932static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7933 struct vmcs12 *vmcs12)
4704d0be
NHE		 7934{
7935 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7936 vcpu->arch.efer = vmcs12->host_ia32_efer;
d1fa0352 7937 else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
4704d0be
NHE		 7938 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7939 else
7940 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7941 vmx_set_efer(vcpu, vcpu->arch.efer);
7942
7943 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7944 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
c4627c72 7945 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
4704d0be
NHE		 7946 /*
7947 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7948 * actually changed, because it depends on the current state of
7949 * fpu_active (which may have changed).
7950 * Note that vmx_set_cr0 refers to efer set above.
7951 */
7952 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7953 /*
7954 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7955 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7956 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7957 */
7958 update_exception_bitmap(vcpu);
7959 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7960 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7961
7962 /*
7963 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7964 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7965 */
7966 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7967 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7968
7969 /* shadow page tables on either EPT or shadow page tables */
7970 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7971 kvm_mmu_reset_context(vcpu);
7972
7973 if (enable_vpid) {
7974 /*
7975 * Trivially support vpid by letting L2s share their parent
7976 * L1's vpid. TODO: move to a more elaborate solution, giving
7977 * each L2 its own vpid and exposing the vpid feature to L1.
7978 */
7979 vmx_flush_tlb(vcpu);
7980 }
7981
7982
7983 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7984 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7985 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7986 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7987 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7988 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7989 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7990 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7991 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7992 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7993 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7994 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7995 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7996 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7997 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7998
7999 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
8000 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
8001 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8002 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
8003 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5
JK		 8004
8005 kvm_set_dr(vcpu, 7, 0x400);
8006 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 8007}
8008
8009/*
8010 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8011 * and modify vmcs12 to make it see what it would expect to see there if
8012 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8013 */
8014static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
8015{
8016 struct vcpu_vmx *vmx = to_vmx(vcpu);
8017 int cpu;
8018 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8019
5f3d5799
JK		 8020 /* trying to cancel vmlaunch/vmresume is a bug */
8021 WARN_ON_ONCE(vmx->nested.nested_run_pending);
8022
4704d0be
NHE		 8023 leave_guest_mode(vcpu);
8024 prepare_vmcs12(vcpu, vmcs12);
8025
8026 cpu = get_cpu();
8027 vmx->loaded_vmcs = &vmx->vmcs01;
8028 vmx_vcpu_put(vcpu);
8029 vmx_vcpu_load(vcpu, cpu);
8030 vcpu->cpu = cpu;
8031 put_cpu();
8032
36c3cc42
JK		 8033 vmx_segment_cache_clear(vmx);
8034
4704d0be
NHE		 8035 /* if no vmcs02 cache requested, remove the one we used */
8036 if (VMCS02_POOL_SIZE == 0)
8037 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
8038
8039 load_vmcs12_host_state(vcpu, vmcs12);
8040
27fc51b2 8041 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 8042 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
8043
8044 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8045 vmx->host_rsp = 0;
8046
8047 /* Unpin physical memory we referred to in vmcs02 */
8048 if (vmx->nested.apic_access_page) {
8049 nested_release_page(vmx->nested.apic_access_page);
8050 vmx->nested.apic_access_page = 0;
8051 }
8052
8053 /*
8054 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8055 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8056 * success or failure flag accordingly.
8057 */
8058 if (unlikely(vmx->fail)) {
8059 vmx->fail = 0;
8060 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
8061 } else
8062 nested_vmx_succeed(vcpu);
012f83cb
AG		 8063 if (enable_shadow_vmcs)
8064 vmx->nested.sync_shadow_vmcs = true;
4704d0be
NHE		 8065}
8066
7c177938
NHE		 8067/*
8068 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8069 * 23.7 "VM-entry failures during or after loading guest state" (this also
8070 * lists the acceptable exit-reason and exit-qualification parameters).
8071 * It should only be called before L2 actually succeeded to run, and when
8072 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8073 */
8074static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
8075 struct vmcs12 *vmcs12,
8076 u32 reason, unsigned long qualification)
8077{
8078 load_vmcs12_host_state(vcpu, vmcs12);
8079 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
8080 vmcs12->exit_qualification = qualification;
8081 nested_vmx_succeed(vcpu);
012f83cb
AG		 8082 if (enable_shadow_vmcs)
8083 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
7c177938
NHE		 8084}
8085
8a76d7f2
JR		 8086static int vmx_check_intercept(struct kvm_vcpu *vcpu,
8087 struct x86_instruction_info *info,
8088 enum x86_intercept_stage stage)
8089{
8090 return X86EMUL_CONTINUE;
8091}
8092
cbdd1bea 8093static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 8094 .cpu_has_kvm_support = cpu_has_kvm_support,
8095 .disabled_by_bios = vmx_disabled_by_bios,
8096 .hardware_setup = hardware_setup,
8097 .hardware_unsetup = hardware_unsetup,
002c7f7c 8098 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 8099 .hardware_enable = hardware_enable,
8100 .hardware_disable = hardware_disable,
04547156 8101 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 8102
8103 .vcpu_create = vmx_create_vcpu,
8104 .vcpu_free = vmx_free_vcpu,
04d2cc77 8105 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 8106
04d2cc77 8107 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 8108 .vcpu_load = vmx_vcpu_load,
8109 .vcpu_put = vmx_vcpu_put,
8110
c8639010 8111 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 8112 .get_msr = vmx_get_msr,
8113 .set_msr = vmx_set_msr,
8114 .get_segment_base = vmx_get_segment_base,
8115 .get_segment = vmx_get_segment,
8116 .set_segment = vmx_set_segment,
2e4d2653 8117 .get_cpl = vmx_get_cpl,
6aa8b732 8118 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 8119 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 8120 .decache_cr3 = vmx_decache_cr3,
25c4c276 8121 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 8122 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 8123 .set_cr3 = vmx_set_cr3,
8124 .set_cr4 = vmx_set_cr4,
6aa8b732 8125 .set_efer = vmx_set_efer,
6aa8b732
AK		 8126 .get_idt = vmx_get_idt,
8127 .set_idt = vmx_set_idt,
8128 .get_gdt = vmx_get_gdt,
8129 .set_gdt = vmx_set_gdt,
020df079 8130 .set_dr7 = vmx_set_dr7,
5fdbf976 8131 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 8132 .get_rflags = vmx_get_rflags,
8133 .set_rflags = vmx_set_rflags,
ebcbab4c 8134 .fpu_activate = vmx_fpu_activate,
02daab21 8135 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 8136
8137 .tlb_flush = vmx_flush_tlb,
6aa8b732 8138
6aa8b732 8139 .run = vmx_vcpu_run,
6062d012 8140 .handle_exit = vmx_handle_exit,
6aa8b732 8141 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 8142 .set_interrupt_shadow = vmx_set_interrupt_shadow,
8143 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 8144 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 8145 .set_irq = vmx_inject_irq,
95ba8273 8146 .set_nmi = vmx_inject_nmi,
298101da 8147 .queue_exception = vmx_queue_exception,
b463a6f7 8148 .cancel_injection = vmx_cancel_injection,
78646121 8149 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 8150 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 8151 .get_nmi_mask = vmx_get_nmi_mask,
8152 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 8153 .enable_nmi_window = enable_nmi_window,
8154 .enable_irq_window = enable_irq_window,
8155 .update_cr8_intercept = update_cr8_intercept,
8d14695f 8156 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 8157 .vm_has_apicv = vmx_vm_has_apicv,
8158 .load_eoi_exitmap = vmx_load_eoi_exitmap,
8159 .hwapic_irr_update = vmx_hwapic_irr_update,
8160 .hwapic_isr_update = vmx_hwapic_isr_update,
a20ed54d
YZ		 8161 .sync_pir_to_irr = vmx_sync_pir_to_irr,
8162 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 8163
cbc94022 8164 .set_tss_addr = vmx_set_tss_addr,
67253af5 8165 .get_tdp_level = get_ept_level,
4b12f0de 8166 .get_mt_mask = vmx_get_mt_mask,
229456fc 8167
586f9607 8168 .get_exit_info = vmx_get_exit_info,
586f9607 8169
17cc3935 8170 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 8171
8172 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 8173
8174 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 8175 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 8176
8177 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 8178
8179 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 8180
4051b188 8181 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 8182 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 8183 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 8184 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 8185 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 8186 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 8187
8188 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 8189
8190 .check_intercept = vmx_check_intercept,
a547c6db 8191 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 8192};
8193
8194static int __init vmx_init(void)
8195{
8d14695f 8196 int r, i, msr;
26bb0981
AK		 8197
8198 rdmsrl_safe(MSR_EFER, &host_efer);
8199
8200 for (i = 0; i < NR_VMX_MSR; ++i)
8201 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 8202
3e7c73e9 8203 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 8204 if (!vmx_io_bitmap_a)
8205 return -ENOMEM;
8206
2106a548
GC		 8207 r = -ENOMEM;
8208
3e7c73e9 8209 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8210 if (!vmx_io_bitmap_b)
fdef3ad1 8211 goto out;
fdef3ad1 8212
5897297b 8213 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8214 if (!vmx_msr_bitmap_legacy)
25c5f225 8215 goto out1;
2106a548 8216
8d14695f
YZ		 8217 vmx_msr_bitmap_legacy_x2apic =
8218 (unsigned long *)__get_free_page(GFP_KERNEL);
8219 if (!vmx_msr_bitmap_legacy_x2apic)
8220 goto out2;
25c5f225 8221
5897297b 8222 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 8223 if (!vmx_msr_bitmap_longmode)
8d14695f 8224 goto out3;
2106a548 8225
8d14695f
YZ		 8226 vmx_msr_bitmap_longmode_x2apic =
8227 (unsigned long *)__get_free_page(GFP_KERNEL);
8228 if (!vmx_msr_bitmap_longmode_x2apic)
8229 goto out4;
4607c2d7
AG		 8230 vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8231 if (!vmx_vmread_bitmap)
8232 goto out5;
8233
8234 vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
8235 if (!vmx_vmwrite_bitmap)
8236 goto out6;
8237
8238 memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
8239 memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
8240 /* shadowed read/write fields */
8241 for (i = 0; i < max_shadow_read_write_fields; i++) {
8242 clear_bit(shadow_read_write_fields[i], vmx_vmwrite_bitmap);
8243 clear_bit(shadow_read_write_fields[i], vmx_vmread_bitmap);
8244 }
8245 /* shadowed read only fields */
8246 for (i = 0; i < max_shadow_read_only_fields; i++)
8247 clear_bit(shadow_read_only_fields[i], vmx_vmread_bitmap);
5897297b 8248
fdef3ad1
HQ		 8249 /*
8250 * Allow direct access to the PC debug port (it is often used for I/O
8251 * delays, but the vmexits simply slow things down).
8252 */
3e7c73e9
AK		 8253 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
8254 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 8255
3e7c73e9 8256 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 8257
5897297b
AK		 8258 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
8259 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 8260
2384d2b3
SY		 8261 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
8262
0ee75bea
AK		 8263 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
8264 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 8265 if (r)
4607c2d7 8266 goto out7;
25c5f225 8267
8f536b76
ZY		 8268#ifdef CONFIG_KEXEC
8269 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
8270 crash_vmclear_local_loaded_vmcss);
8271#endif
8272
5897297b
AK		 8273 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
8274 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
8275 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
8276 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
8277 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
8278 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 8279 memcpy(vmx_msr_bitmap_legacy_x2apic,
8280 vmx_msr_bitmap_legacy, PAGE_SIZE);
8281 memcpy(vmx_msr_bitmap_longmode_x2apic,
8282 vmx_msr_bitmap_longmode, PAGE_SIZE);
8283
01e439be 8284 if (enable_apicv) {
8d14695f
YZ		 8285 for (msr = 0x800; msr <= 0x8ff; msr++)
8286 vmx_disable_intercept_msr_read_x2apic(msr);
8287
8288 /* According SDM, in x2apic mode, the whole id reg is used.
8289 * But in KVM, it only use the highest eight bits. Need to
8290 * intercept it */
8291 vmx_enable_intercept_msr_read_x2apic(0x802);
8292 /* TMCCT */
8293 vmx_enable_intercept_msr_read_x2apic(0x839);
8294 /* TPR */
8295 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 8296 /* EOI */
8297 vmx_disable_intercept_msr_write_x2apic(0x80b);
8298 /* SELF-IPI */
8299 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 8300 }
fdef3ad1 8301
089d034e 8302 if (enable_ept) {
3f6d8c8a
XH		 8303 kvm_mmu_set_mask_ptes(0ull,
8304 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
8305 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
8306 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 8307 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 8308 kvm_enable_tdp();
8309 } else
8310 kvm_disable_tdp();
1439442c 8311
fdef3ad1
HQ		 8312 return 0;
8313
4607c2d7
AG		 8314out7:
8315 free_page((unsigned long)vmx_vmwrite_bitmap);
8316out6:
8317 free_page((unsigned long)vmx_vmread_bitmap);
458f212e
YZ		 8318out5:
8319 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 8320out4:
5897297b 8321 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 8322out3:
8323 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 8324out2:
5897297b 8325 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 8326out1:
3e7c73e9 8327 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 8328out:
3e7c73e9 8329 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 8330 return r;
6aa8b732
AK		 8331}
8332
8333static void __exit vmx_exit(void)
8334{
8d14695f
YZ		 8335 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
8336 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 8337 free_page((unsigned long)vmx_msr_bitmap_legacy);
8338 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 8339 free_page((unsigned long)vmx_io_bitmap_b);
8340 free_page((unsigned long)vmx_io_bitmap_a);
4607c2d7
AG		 8341 free_page((unsigned long)vmx_vmwrite_bitmap);
8342 free_page((unsigned long)vmx_vmread_bitmap);
fdef3ad1 8343
8f536b76
ZY		 8344#ifdef CONFIG_KEXEC
8345 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
8346 synchronize_rcu();
8347#endif
8348
cb498ea2 8349 kvm_exit();
6aa8b732
AK		 8350}
8351
8352module_init(vmx_init)
8353module_exit(vmx_exit)
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