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KVM: VMX: Register a new IPI for posted interrupt
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
00b27a3e 21#include "cpuid.h"
e495606d 22
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
9d8f549d 25#include <linux/kernel.h>
6aa8b732
AK		 26#include <linux/mm.h>
27#include <linux/highmem.h>
e8edc6e0 28#include <linux/sched.h>
c7addb90 29#include <linux/moduleparam.h>
e9bda3b3 30#include <linux/mod_devicetable.h>
229456fc 31#include <linux/ftrace_event.h>
5a0e3ad6 32#include <linux/slab.h>
cafd6659 33#include <linux/tboot.h>
5fdbf976 34#include "kvm_cache_regs.h"
35920a35 35#include "x86.h"
e495606d 36
6aa8b732 37#include <asm/io.h>
3b3be0d1 38#include <asm/desc.h>
13673a90 39#include <asm/vmx.h>
6210e37b 40#include <asm/virtext.h>
a0861c02 41#include <asm/mce.h>
2acf923e
DC		 42#include <asm/i387.h>
43#include <asm/xcr.h>
d7cd9796 44#include <asm/perf_event.h>
8f536b76 45#include <asm/kexec.h>
6aa8b732 46
229456fc
MT		 47#include "trace.h"
48
4ecac3fd 49#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 50#define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 52
6aa8b732
AK		 53MODULE_AUTHOR("Qumranet");
54MODULE_LICENSE("GPL");
55
e9bda3b3
JT		 56static const struct x86_cpu_id vmx_cpu_id[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX),
58 {}
59};
60MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
61
476bc001 62static bool __read_mostly enable_vpid = 1;
736caefe 63module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 64
476bc001 65static bool __read_mostly flexpriority_enabled = 1;
736caefe 66module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 67
476bc001 68static bool __read_mostly enable_ept = 1;
736caefe 69module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 70
476bc001 71static bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 72module_param_named(unrestricted_guest,
73 enable_unrestricted_guest, bool, S_IRUGO);
74
83c3a331
XH		 75static bool __read_mostly enable_ept_ad_bits = 1;
76module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
77
a27685c3 78static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 79module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 80
476bc001 81static bool __read_mostly vmm_exclusive = 1;
b923e62e
DX		 82module_param(vmm_exclusive, bool, S_IRUGO);
83
476bc001 84static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 85module_param(fasteoi, bool, S_IRUGO);
86
257090f7 87static bool __read_mostly enable_apicv_reg_vid;
83d4c286 88
801d3424
NHE		 89/*
90 * If nested=1, nested virtualization is supported, i.e., guests may use
91 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
92 * use VMX instructions.
93 */
476bc001 94static bool __read_mostly nested = 0;
801d3424
NHE		 95module_param(nested, bool, S_IRUGO);
96
5037878e
GN		 97#define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
98#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 99#define KVM_VM_CR0_ALWAYS_ON \
100 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 101#define KVM_CR4_GUEST_OWNED_BITS \
102 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
103 | X86_CR4_OSXMMEXCPT)
104
cdc0e244
AK		 105#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
106#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
107
78ac8b47
AK		 108#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
109
4b8d54f9
ZE		 110/*
111 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
112 * ple_gap: upper bound on the amount of time between two successive
113 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 114 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 115 * ple_window: upper bound on the amount of time a guest is allowed to execute
116 * in a PAUSE loop. Tests indicate that most spinlocks are held for
117 * less than 2^12 cycles
118 * Time is measured based on a counter that runs at the same rate as the TSC,
119 * refer SDM volume 3b section 21.6.13 & 22.1.3.
120 */
00c25bce 121#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 122#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
123static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
124module_param(ple_gap, int, S_IRUGO);
125
126static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
127module_param(ple_window, int, S_IRUGO);
128
83287ea4
AK		 129extern const ulong vmx_return;
130
8bf00a52 131#define NR_AUTOLOAD_MSRS 8
ff2f6fe9 132#define VMCS02_POOL_SIZE 1
61d2ef2c 133
a2fa3e9f
GH		 134struct vmcs {
135 u32 revision_id;
136 u32 abort;
137 char data[0];
138};
139
d462b819
NHE		 140/*
141 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
142 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
143 * loaded on this CPU (so we can clear them if the CPU goes down).
144 */
145struct loaded_vmcs {
146 struct vmcs *vmcs;
147 int cpu;
148 int launched;
149 struct list_head loaded_vmcss_on_cpu_link;
150};
151
26bb0981
AK		 152struct shared_msr_entry {
153 unsigned index;
154 u64 data;
d5696725 155 u64 mask;
26bb0981
AK		 156};
157
a9d30f33
NHE		 158/*
159 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
160 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
161 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
162 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
163 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
164 * More than one of these structures may exist, if L1 runs multiple L2 guests.
165 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
166 * underlying hardware which will be used to run L2.
167 * This structure is packed to ensure that its layout is identical across
168 * machines (necessary for live migration).
169 * If there are changes in this struct, VMCS12_REVISION must be changed.
170 */
22bd0358 171typedef u64 natural_width;
a9d30f33
NHE		 172struct __packed vmcs12 {
173 /* According to the Intel spec, a VMCS region must start with the
174 * following two fields. Then follow implementation-specific data.
175 */
176 u32 revision_id;
177 u32 abort;
22bd0358 178
27d6c865
NHE		 179 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
180 u32 padding[7]; /* room for future expansion */
181
22bd0358
NHE		 182 u64 io_bitmap_a;
183 u64 io_bitmap_b;
184 u64 msr_bitmap;
185 u64 vm_exit_msr_store_addr;
186 u64 vm_exit_msr_load_addr;
187 u64 vm_entry_msr_load_addr;
188 u64 tsc_offset;
189 u64 virtual_apic_page_addr;
190 u64 apic_access_addr;
191 u64 ept_pointer;
192 u64 guest_physical_address;
193 u64 vmcs_link_pointer;
194 u64 guest_ia32_debugctl;
195 u64 guest_ia32_pat;
196 u64 guest_ia32_efer;
197 u64 guest_ia32_perf_global_ctrl;
198 u64 guest_pdptr0;
199 u64 guest_pdptr1;
200 u64 guest_pdptr2;
201 u64 guest_pdptr3;
202 u64 host_ia32_pat;
203 u64 host_ia32_efer;
204 u64 host_ia32_perf_global_ctrl;
205 u64 padding64[8]; /* room for future expansion */
206 /*
207 * To allow migration of L1 (complete with its L2 guests) between
208 * machines of different natural widths (32 or 64 bit), we cannot have
209 * unsigned long fields with no explict size. We use u64 (aliased
210 * natural_width) instead. Luckily, x86 is little-endian.
211 */
212 natural_width cr0_guest_host_mask;
213 natural_width cr4_guest_host_mask;
214 natural_width cr0_read_shadow;
215 natural_width cr4_read_shadow;
216 natural_width cr3_target_value0;
217 natural_width cr3_target_value1;
218 natural_width cr3_target_value2;
219 natural_width cr3_target_value3;
220 natural_width exit_qualification;
221 natural_width guest_linear_address;
222 natural_width guest_cr0;
223 natural_width guest_cr3;
224 natural_width guest_cr4;
225 natural_width guest_es_base;
226 natural_width guest_cs_base;
227 natural_width guest_ss_base;
228 natural_width guest_ds_base;
229 natural_width guest_fs_base;
230 natural_width guest_gs_base;
231 natural_width guest_ldtr_base;
232 natural_width guest_tr_base;
233 natural_width guest_gdtr_base;
234 natural_width guest_idtr_base;
235 natural_width guest_dr7;
236 natural_width guest_rsp;
237 natural_width guest_rip;
238 natural_width guest_rflags;
239 natural_width guest_pending_dbg_exceptions;
240 natural_width guest_sysenter_esp;
241 natural_width guest_sysenter_eip;
242 natural_width host_cr0;
243 natural_width host_cr3;
244 natural_width host_cr4;
245 natural_width host_fs_base;
246 natural_width host_gs_base;
247 natural_width host_tr_base;
248 natural_width host_gdtr_base;
249 natural_width host_idtr_base;
250 natural_width host_ia32_sysenter_esp;
251 natural_width host_ia32_sysenter_eip;
252 natural_width host_rsp;
253 natural_width host_rip;
254 natural_width paddingl[8]; /* room for future expansion */
255 u32 pin_based_vm_exec_control;
256 u32 cpu_based_vm_exec_control;
257 u32 exception_bitmap;
258 u32 page_fault_error_code_mask;
259 u32 page_fault_error_code_match;
260 u32 cr3_target_count;
261 u32 vm_exit_controls;
262 u32 vm_exit_msr_store_count;
263 u32 vm_exit_msr_load_count;
264 u32 vm_entry_controls;
265 u32 vm_entry_msr_load_count;
266 u32 vm_entry_intr_info_field;
267 u32 vm_entry_exception_error_code;
268 u32 vm_entry_instruction_len;
269 u32 tpr_threshold;
270 u32 secondary_vm_exec_control;
271 u32 vm_instruction_error;
272 u32 vm_exit_reason;
273 u32 vm_exit_intr_info;
274 u32 vm_exit_intr_error_code;
275 u32 idt_vectoring_info_field;
276 u32 idt_vectoring_error_code;
277 u32 vm_exit_instruction_len;
278 u32 vmx_instruction_info;
279 u32 guest_es_limit;
280 u32 guest_cs_limit;
281 u32 guest_ss_limit;
282 u32 guest_ds_limit;
283 u32 guest_fs_limit;
284 u32 guest_gs_limit;
285 u32 guest_ldtr_limit;
286 u32 guest_tr_limit;
287 u32 guest_gdtr_limit;
288 u32 guest_idtr_limit;
289 u32 guest_es_ar_bytes;
290 u32 guest_cs_ar_bytes;
291 u32 guest_ss_ar_bytes;
292 u32 guest_ds_ar_bytes;
293 u32 guest_fs_ar_bytes;
294 u32 guest_gs_ar_bytes;
295 u32 guest_ldtr_ar_bytes;
296 u32 guest_tr_ar_bytes;
297 u32 guest_interruptibility_info;
298 u32 guest_activity_state;
299 u32 guest_sysenter_cs;
300 u32 host_ia32_sysenter_cs;
0238ea91
JK		 301 u32 vmx_preemption_timer_value;
302 u32 padding32[7]; /* room for future expansion */
22bd0358
NHE		 303 u16 virtual_processor_id;
304 u16 guest_es_selector;
305 u16 guest_cs_selector;
306 u16 guest_ss_selector;
307 u16 guest_ds_selector;
308 u16 guest_fs_selector;
309 u16 guest_gs_selector;
310 u16 guest_ldtr_selector;
311 u16 guest_tr_selector;
312 u16 host_es_selector;
313 u16 host_cs_selector;
314 u16 host_ss_selector;
315 u16 host_ds_selector;
316 u16 host_fs_selector;
317 u16 host_gs_selector;
318 u16 host_tr_selector;
a9d30f33
NHE		 319};
320
321/*
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 */
326#define VMCS12_REVISION 0x11e57ed0
327
328/*
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
332 */
333#define VMCS12_SIZE 0x1000
334
ff2f6fe9
NHE		 335/* Used to remember the last vmcs02 used for some recently used vmcs12s */
336struct vmcs02_list {
337 struct list_head list;
338 gpa_t vmptr;
339 struct loaded_vmcs vmcs02;
340};
341
ec378aee
NHE		 342/*
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 */
346struct nested_vmx {
347 /* Has the level1 guest done vmxon? */
348 bool vmxon;
a9d30f33
NHE		 349
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 gpa_t current_vmptr;
352 /* The host-usable pointer to the above */
353 struct page *current_vmcs12_page;
354 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 355
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool;
358 int vmcs02_num;
fe3ef05c 359 u64 vmcs01_tsc_offset;
644d711a
NHE		 360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending;
fe3ef05c
NHE		 362 /*
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
365 */
366 struct page *apic_access_page;
ec378aee
NHE		 367};
368
a2fa3e9f 369struct vcpu_vmx {
fb3f0f51 370 struct kvm_vcpu vcpu;
313dbd49 371 unsigned long host_rsp;
29bd8a78 372 u8 fail;
69c73028 373 u8 cpl;
9d58b931 374 bool nmi_known_unmasked;
51aa01d1 375 u32 exit_intr_info;
1155f76a 376 u32 idt_vectoring_info;
6de12732 377 ulong rflags;
26bb0981 378 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 379 int nmsrs;
380 int save_nmsrs;
a547c6db 381 unsigned long host_idt_base;
a2fa3e9f 382#ifdef CONFIG_X86_64
44ea2b17
AK		 383 u64 msr_host_kernel_gs_base;
384 u64 msr_guest_kernel_gs_base;
a2fa3e9f 385#endif
d462b819
NHE		 386 /*
387 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
388 * non-nested (L1) guest, it always points to vmcs01. For a nested
389 * guest (L2), it points to a different VMCS.
390 */
391 struct loaded_vmcs vmcs01;
392 struct loaded_vmcs *loaded_vmcs;
393 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 394 struct msr_autoload {
395 unsigned nr;
396 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
397 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
398 } msr_autoload;
a2fa3e9f
GH		 399 struct {
400 int loaded;
401 u16 fs_sel, gs_sel, ldt_sel;
b2da15ac
AK		 402#ifdef CONFIG_X86_64
403 u16 ds_sel, es_sel;
404#endif
152d3f2f
LV		 405 int gs_ldt_reload_needed;
406 int fs_reload_needed;
d77c26fc 407 } host_state;
9c8cba37 408 struct {
7ffd92c5 409 int vm86_active;
78ac8b47 410 ulong save_rflags;
f5f7b2fe
AK		 411 struct kvm_segment segs[8];
412 } rmode;
413 struct {
414 u32 bitmask; /* 4 bits per segment (1 bit per field) */
7ffd92c5
AK		 415 struct kvm_save_segment {
416 u16 selector;
417 unsigned long base;
418 u32 limit;
419 u32 ar;
f5f7b2fe 420 } seg[8];
2fb92db1 421 } segment_cache;
2384d2b3 422 int vpid;
04fa4d32 423 bool emulation_required;
3b86cd99
JK		 424
425 /* Support for vnmi-less CPUs */
426 int soft_vnmi_blocked;
427 ktime_t entry_time;
428 s64 vnmi_blocked_time;
a0861c02 429 u32 exit_reason;
4e47c7a6
SY		 430
431 bool rdtscp_enabled;
ec378aee
NHE		 432
433 /* Support for a guest hypervisor (nested VMX) */
434 struct nested_vmx nested;
a2fa3e9f
GH		 435};
436
2fb92db1
AK		 437enum segment_cache_field {
438 SEG_FIELD_SEL = 0,
439 SEG_FIELD_BASE = 1,
440 SEG_FIELD_LIMIT = 2,
441 SEG_FIELD_AR = 3,
442
443 SEG_FIELD_NR = 4
444};
445
a2fa3e9f
GH		 446static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
447{
fb3f0f51 448 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 449}
450
22bd0358
NHE		 451#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
452#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
453#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
454 [number##_HIGH] = VMCS12_OFFSET(name)+4
455
772e0318 456static const unsigned short vmcs_field_to_offset_table[] = {
22bd0358
NHE		 457 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
458 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
459 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
460 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
461 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
462 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
463 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
464 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
465 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
466 FIELD(HOST_ES_SELECTOR, host_es_selector),
467 FIELD(HOST_CS_SELECTOR, host_cs_selector),
468 FIELD(HOST_SS_SELECTOR, host_ss_selector),
469 FIELD(HOST_DS_SELECTOR, host_ds_selector),
470 FIELD(HOST_FS_SELECTOR, host_fs_selector),
471 FIELD(HOST_GS_SELECTOR, host_gs_selector),
472 FIELD(HOST_TR_SELECTOR, host_tr_selector),
473 FIELD64(IO_BITMAP_A, io_bitmap_a),
474 FIELD64(IO_BITMAP_B, io_bitmap_b),
475 FIELD64(MSR_BITMAP, msr_bitmap),
476 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
477 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
478 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
479 FIELD64(TSC_OFFSET, tsc_offset),
480 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
481 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
482 FIELD64(EPT_POINTER, ept_pointer),
483 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
484 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
485 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
486 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
487 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
488 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
489 FIELD64(GUEST_PDPTR0, guest_pdptr0),
490 FIELD64(GUEST_PDPTR1, guest_pdptr1),
491 FIELD64(GUEST_PDPTR2, guest_pdptr2),
492 FIELD64(GUEST_PDPTR3, guest_pdptr3),
493 FIELD64(HOST_IA32_PAT, host_ia32_pat),
494 FIELD64(HOST_IA32_EFER, host_ia32_efer),
495 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
496 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
497 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
498 FIELD(EXCEPTION_BITMAP, exception_bitmap),
499 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
500 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
501 FIELD(CR3_TARGET_COUNT, cr3_target_count),
502 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
503 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
504 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
505 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
506 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
507 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
508 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
509 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
510 FIELD(TPR_THRESHOLD, tpr_threshold),
511 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
512 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
513 FIELD(VM_EXIT_REASON, vm_exit_reason),
514 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
515 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
516 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
517 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
518 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
519 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
520 FIELD(GUEST_ES_LIMIT, guest_es_limit),
521 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
522 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
523 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
524 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
525 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
526 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
527 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
528 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
529 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
530 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
531 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
532 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
533 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
534 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
535 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
536 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
537 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
538 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
539 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
540 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
541 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
0238ea91 542 FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
22bd0358
NHE		 543 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
544 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
545 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
546 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
547 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
548 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
549 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
550 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
551 FIELD(EXIT_QUALIFICATION, exit_qualification),
552 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
553 FIELD(GUEST_CR0, guest_cr0),
554 FIELD(GUEST_CR3, guest_cr3),
555 FIELD(GUEST_CR4, guest_cr4),
556 FIELD(GUEST_ES_BASE, guest_es_base),
557 FIELD(GUEST_CS_BASE, guest_cs_base),
558 FIELD(GUEST_SS_BASE, guest_ss_base),
559 FIELD(GUEST_DS_BASE, guest_ds_base),
560 FIELD(GUEST_FS_BASE, guest_fs_base),
561 FIELD(GUEST_GS_BASE, guest_gs_base),
562 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
563 FIELD(GUEST_TR_BASE, guest_tr_base),
564 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
565 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
566 FIELD(GUEST_DR7, guest_dr7),
567 FIELD(GUEST_RSP, guest_rsp),
568 FIELD(GUEST_RIP, guest_rip),
569 FIELD(GUEST_RFLAGS, guest_rflags),
570 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
571 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
572 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
573 FIELD(HOST_CR0, host_cr0),
574 FIELD(HOST_CR3, host_cr3),
575 FIELD(HOST_CR4, host_cr4),
576 FIELD(HOST_FS_BASE, host_fs_base),
577 FIELD(HOST_GS_BASE, host_gs_base),
578 FIELD(HOST_TR_BASE, host_tr_base),
579 FIELD(HOST_GDTR_BASE, host_gdtr_base),
580 FIELD(HOST_IDTR_BASE, host_idtr_base),
581 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
582 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
583 FIELD(HOST_RSP, host_rsp),
584 FIELD(HOST_RIP, host_rip),
585};
586static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
587
588static inline short vmcs_field_to_offset(unsigned long field)
589{
590 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
591 return -1;
592 return vmcs_field_to_offset_table[field];
593}
594
a9d30f33
NHE		 595static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
596{
597 return to_vmx(vcpu)->nested.current_vmcs12;
598}
599
600static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
601{
602 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
32cad84f 603 if (is_error_page(page))
a9d30f33 604 return NULL;
32cad84f 605
a9d30f33
NHE		 606 return page;
607}
608
609static void nested_release_page(struct page *page)
610{
611 kvm_release_page_dirty(page);
612}
613
614static void nested_release_page_clean(struct page *page)
615{
616 kvm_release_page_clean(page);
617}
618
4e1096d2 619static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 620static void kvm_cpu_vmxon(u64 addr);
621static void kvm_cpu_vmxoff(void);
aff48baa 622static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 623static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
b246dd5d
OW		 624static void vmx_set_segment(struct kvm_vcpu *vcpu,
625 struct kvm_segment *var, int seg);
626static void vmx_get_segment(struct kvm_vcpu *vcpu,
627 struct kvm_segment *var, int seg);
d99e4152
GN		 628static bool guest_state_valid(struct kvm_vcpu *vcpu);
629static u32 vmx_segment_access_rights(struct kvm_segment *var);
75880a01 630
6aa8b732
AK		 631static DEFINE_PER_CPU(struct vmcs *, vmxarea);
632static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 633/*
634 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
635 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
636 */
637static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 638static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 639
3e7c73e9
AK		 640static unsigned long *vmx_io_bitmap_a;
641static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 642static unsigned long *vmx_msr_bitmap_legacy;
643static unsigned long *vmx_msr_bitmap_longmode;
8d14695f
YZ		 644static unsigned long *vmx_msr_bitmap_legacy_x2apic;
645static unsigned long *vmx_msr_bitmap_longmode_x2apic;
fdef3ad1 646
110312c8 647static bool cpu_has_load_ia32_efer;
8bf00a52 648static bool cpu_has_load_perf_global_ctrl;
110312c8 649
2384d2b3
SY		 650static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
651static DEFINE_SPINLOCK(vmx_vpid_lock);
652
1c3d14fe 653static struct vmcs_config {
6aa8b732
AK		 654 int size;
655 int order;
656 u32 revision_id;
1c3d14fe
YS		 657 u32 pin_based_exec_ctrl;
658 u32 cpu_based_exec_ctrl;
f78e0e2e 659 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 660 u32 vmexit_ctrl;
661 u32 vmentry_ctrl;
662} vmcs_config;
6aa8b732 663
efff9e53 664static struct vmx_capability {
d56f546d
SY		 665 u32 ept;
666 u32 vpid;
667} vmx_capability;
668
6aa8b732
AK		 669#define VMX_SEGMENT_FIELD(seg) \
670 [VCPU_SREG_##seg] = { \
671 .selector = GUEST_##seg##_SELECTOR, \
672 .base = GUEST_##seg##_BASE, \
673 .limit = GUEST_##seg##_LIMIT, \
674 .ar_bytes = GUEST_##seg##_AR_BYTES, \
675 }
676
772e0318 677static const struct kvm_vmx_segment_field {
6aa8b732
AK		 678 unsigned selector;
679 unsigned base;
680 unsigned limit;
681 unsigned ar_bytes;
682} kvm_vmx_segment_fields[] = {
683 VMX_SEGMENT_FIELD(CS),
684 VMX_SEGMENT_FIELD(DS),
685 VMX_SEGMENT_FIELD(ES),
686 VMX_SEGMENT_FIELD(FS),
687 VMX_SEGMENT_FIELD(GS),
688 VMX_SEGMENT_FIELD(SS),
689 VMX_SEGMENT_FIELD(TR),
690 VMX_SEGMENT_FIELD(LDTR),
691};
692
26bb0981
AK		 693static u64 host_efer;
694
6de4f3ad
AK		 695static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
696
4d56c8a7 697/*
8c06585d 698 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 699 * away by decrementing the array size.
700 */
6aa8b732 701static const u32 vmx_msr_index[] = {
05b3e0c2 702#ifdef CONFIG_X86_64
44ea2b17 703 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 704#endif
8c06585d 705 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 706};
9d8f549d 707#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 708
31299944 709static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 710{
711 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
712 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 713 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 714}
715
31299944 716static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 717{
718 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
719 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 720 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 721}
722
31299944 723static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 724{
725 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
726 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 727 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 728}
729
31299944 730static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 731{
732 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
733 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
734}
735
31299944 736static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 737{
738 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
739 INTR_INFO_VALID_MASK)) ==
740 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
741}
742
31299944 743static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 744{
04547156 745 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 746}
747
31299944 748static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 749{
04547156 750 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 751}
752
31299944 753static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 754{
04547156 755 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 756}
757
31299944 758static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 759{
04547156
SY		 760 return vmcs_config.cpu_based_exec_ctrl &
761 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 762}
763
774ead3a 764static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 765{
04547156
SY		 766 return vmcs_config.cpu_based_2nd_exec_ctrl &
767 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
768}
769
8d14695f
YZ		 770static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
771{
772 return vmcs_config.cpu_based_2nd_exec_ctrl &
773 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
774}
775
83d4c286
YZ		 776static inline bool cpu_has_vmx_apic_register_virt(void)
777{
778 return vmcs_config.cpu_based_2nd_exec_ctrl &
779 SECONDARY_EXEC_APIC_REGISTER_VIRT;
780}
781
c7c9c56c
YZ		 782static inline bool cpu_has_vmx_virtual_intr_delivery(void)
783{
784 return vmcs_config.cpu_based_2nd_exec_ctrl &
785 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
786}
787
04547156
SY		 788static inline bool cpu_has_vmx_flexpriority(void)
789{
790 return cpu_has_vmx_tpr_shadow() &&
791 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 792}
793
e799794e
MT		 794static inline bool cpu_has_vmx_ept_execute_only(void)
795{
31299944 796 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 797}
798
799static inline bool cpu_has_vmx_eptp_uncacheable(void)
800{
31299944 801 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 802}
803
804static inline bool cpu_has_vmx_eptp_writeback(void)
805{
31299944 806 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 807}
808
809static inline bool cpu_has_vmx_ept_2m_page(void)
810{
31299944 811 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 812}
813
878403b7
SY		 814static inline bool cpu_has_vmx_ept_1g_page(void)
815{
31299944 816 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 817}
818
4bc9b982
SY		 819static inline bool cpu_has_vmx_ept_4levels(void)
820{
821 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
822}
823
83c3a331
XH		 824static inline bool cpu_has_vmx_ept_ad_bits(void)
825{
826 return vmx_capability.ept & VMX_EPT_AD_BIT;
827}
828
31299944 829static inline bool cpu_has_vmx_invept_context(void)
d56f546d 830{
31299944 831 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 832}
833
31299944 834static inline bool cpu_has_vmx_invept_global(void)
d56f546d 835{
31299944 836 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 837}
838
518c8aee
GJ		 839static inline bool cpu_has_vmx_invvpid_single(void)
840{
841 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
842}
843
b9d762fa
GJ		 844static inline bool cpu_has_vmx_invvpid_global(void)
845{
846 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
847}
848
31299944 849static inline bool cpu_has_vmx_ept(void)
d56f546d 850{
04547156
SY		 851 return vmcs_config.cpu_based_2nd_exec_ctrl &
852 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 853}
854
31299944 855static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 856{
857 return vmcs_config.cpu_based_2nd_exec_ctrl &
858 SECONDARY_EXEC_UNRESTRICTED_GUEST;
859}
860
31299944 861static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 862{
863 return vmcs_config.cpu_based_2nd_exec_ctrl &
864 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
865}
866
31299944 867static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 868{
6d3e435e 869 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 870}
871
31299944 872static inline bool cpu_has_vmx_vpid(void)
2384d2b3 873{
04547156
SY		 874 return vmcs_config.cpu_based_2nd_exec_ctrl &
875 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 876}
877
31299944 878static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 879{
880 return vmcs_config.cpu_based_2nd_exec_ctrl &
881 SECONDARY_EXEC_RDTSCP;
882}
883
ad756a16
MJ		 884static inline bool cpu_has_vmx_invpcid(void)
885{
886 return vmcs_config.cpu_based_2nd_exec_ctrl &
887 SECONDARY_EXEC_ENABLE_INVPCID;
888}
889
31299944 890static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 891{
892 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
893}
894
f5f48ee1
SY		 895static inline bool cpu_has_vmx_wbinvd_exit(void)
896{
897 return vmcs_config.cpu_based_2nd_exec_ctrl &
898 SECONDARY_EXEC_WBINVD_EXITING;
899}
900
04547156
SY		 901static inline bool report_flexpriority(void)
902{
903 return flexpriority_enabled;
904}
905
fe3ef05c
NHE		 906static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
907{
908 return vmcs12->cpu_based_vm_exec_control & bit;
909}
910
911static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
912{
913 return (vmcs12->cpu_based_vm_exec_control &
914 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
915 (vmcs12->secondary_vm_exec_control & bit);
916}
917
644d711a
NHE		 918static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
919 struct kvm_vcpu *vcpu)
920{
921 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
922}
923
924static inline bool is_exception(u32 intr_info)
925{
926 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
927 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
928}
929
930static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 931static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
932 struct vmcs12 *vmcs12,
933 u32 reason, unsigned long qualification);
934
8b9cf98c 935static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 936{
937 int i;
938
a2fa3e9f 939 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 940 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 941 return i;
942 return -1;
943}
944
2384d2b3
SY		 945static inline void __invvpid(int ext, u16 vpid, gva_t gva)
946{
947 struct {
948 u64 vpid : 16;
949 u64 rsvd : 48;
950 u64 gva;
951 } operand = { vpid, 0, gva };
952
4ecac3fd 953 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 954 /* CF==1 or ZF==1 --> rc = -1 */
955 "; ja 1f ; ud2 ; 1:"
956 : : "a"(&operand), "c"(ext) : "cc", "memory");
957}
958
1439442c
SY		 959static inline void __invept(int ext, u64 eptp, gpa_t gpa)
960{
961 struct {
962 u64 eptp, gpa;
963 } operand = {eptp, gpa};
964
4ecac3fd 965 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 966 /* CF==1 or ZF==1 --> rc = -1 */
967 "; ja 1f ; ud2 ; 1:\n"
968 : : "a" (&operand), "c" (ext) : "cc", "memory");
969}
970
26bb0981 971static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 972{
973 int i;
974
8b9cf98c 975 i = __find_msr_index(vmx, msr);
a75beee6 976 if (i >= 0)
a2fa3e9f 977 return &vmx->guest_msrs[i];
8b6d44c7 978 return NULL;
7725f0ba
AK		 979}
980
6aa8b732
AK		 981static void vmcs_clear(struct vmcs *vmcs)
982{
983 u64 phys_addr = __pa(vmcs);
984 u8 error;
985
4ecac3fd 986 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 987 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 988 : "cc", "memory");
989 if (error)
990 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
991 vmcs, phys_addr);
992}
993
d462b819
NHE		 994static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
995{
996 vmcs_clear(loaded_vmcs->vmcs);
997 loaded_vmcs->cpu = -1;
998 loaded_vmcs->launched = 0;
999}
1000
7725b894
DX		 1001static void vmcs_load(struct vmcs *vmcs)
1002{
1003 u64 phys_addr = __pa(vmcs);
1004 u8 error;
1005
1006 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 1007 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 1008 : "cc", "memory");
1009 if (error)
2844d849 1010 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 1011 vmcs, phys_addr);
1012}
1013
8f536b76
ZY		 1014#ifdef CONFIG_KEXEC
1015/*
1016 * This bitmap is used to indicate whether the vmclear
1017 * operation is enabled on all cpus. All disabled by
1018 * default.
1019 */
1020static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1021
1022static inline void crash_enable_local_vmclear(int cpu)
1023{
1024 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1025}
1026
1027static inline void crash_disable_local_vmclear(int cpu)
1028{
1029 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1030}
1031
1032static inline int crash_local_vmclear_enabled(int cpu)
1033{
1034 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1035}
1036
1037static void crash_vmclear_local_loaded_vmcss(void)
1038{
1039 int cpu = raw_smp_processor_id();
1040 struct loaded_vmcs *v;
1041
1042 if (!crash_local_vmclear_enabled(cpu))
1043 return;
1044
1045 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1046 loaded_vmcss_on_cpu_link)
1047 vmcs_clear(v->vmcs);
1048}
1049#else
1050static inline void crash_enable_local_vmclear(int cpu) { }
1051static inline void crash_disable_local_vmclear(int cpu) { }
1052#endif /* CONFIG_KEXEC */
1053
d462b819 1054static void __loaded_vmcs_clear(void *arg)
6aa8b732 1055{
d462b819 1056 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 1057 int cpu = raw_smp_processor_id();
6aa8b732 1058
d462b819
NHE		 1059 if (loaded_vmcs->cpu != cpu)
1060 return; /* vcpu migration can race with cpu offline */
1061 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 1062 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 1063 crash_disable_local_vmclear(cpu);
d462b819 1064 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 1065
1066 /*
1067 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1068 * is before setting loaded_vmcs->vcpu to -1 which is done in
1069 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1070 * then adds the vmcs into percpu list before it is deleted.
1071 */
1072 smp_wmb();
1073
d462b819 1074 loaded_vmcs_init(loaded_vmcs);
8f536b76 1075 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 1076}
1077
d462b819 1078static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 1079{
e6c7d321
XG		 1080 int cpu = loaded_vmcs->cpu;
1081
1082 if (cpu != -1)
1083 smp_call_function_single(cpu,
1084 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 1085}
1086
1760dd49 1087static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 1088{
1089 if (vmx->vpid == 0)
1090 return;
1091
518c8aee
GJ		 1092 if (cpu_has_vmx_invvpid_single())
1093 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 1094}
1095
b9d762fa
GJ		 1096static inline void vpid_sync_vcpu_global(void)
1097{
1098 if (cpu_has_vmx_invvpid_global())
1099 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1100}
1101
1102static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1103{
1104 if (cpu_has_vmx_invvpid_single())
1760dd49 1105 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1106 else
1107 vpid_sync_vcpu_global();
1108}
1109
1439442c
SY		 1110static inline void ept_sync_global(void)
1111{
1112 if (cpu_has_vmx_invept_global())
1113 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1114}
1115
1116static inline void ept_sync_context(u64 eptp)
1117{
089d034e 1118 if (enable_ept) {
1439442c
SY		 1119 if (cpu_has_vmx_invept_context())
1120 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1121 else
1122 ept_sync_global();
1123 }
1124}
1125
96304217 1126static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1127{
5e520e62 1128 unsigned long value;
6aa8b732 1129
5e520e62
AK		 1130 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1131 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1132 return value;
1133}
1134
96304217 1135static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1136{
1137 return vmcs_readl(field);
1138}
1139
96304217 1140static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1141{
1142 return vmcs_readl(field);
1143}
1144
96304217 1145static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1146{
05b3e0c2 1147#ifdef CONFIG_X86_64
6aa8b732
AK		 1148 return vmcs_readl(field);
1149#else
1150 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1151#endif
1152}
1153
e52de1b8
AK		 1154static noinline void vmwrite_error(unsigned long field, unsigned long value)
1155{
1156 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1157 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1158 dump_stack();
1159}
1160
6aa8b732
AK		 1161static void vmcs_writel(unsigned long field, unsigned long value)
1162{
1163 u8 error;
1164
4ecac3fd 1165 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1166 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1167 if (unlikely(error))
1168 vmwrite_error(field, value);
6aa8b732
AK		 1169}
1170
1171static void vmcs_write16(unsigned long field, u16 value)
1172{
1173 vmcs_writel(field, value);
1174}
1175
1176static void vmcs_write32(unsigned long field, u32 value)
1177{
1178 vmcs_writel(field, value);
1179}
1180
1181static void vmcs_write64(unsigned long field, u64 value)
1182{
6aa8b732 1183 vmcs_writel(field, value);
7682f2d0 1184#ifndef CONFIG_X86_64
6aa8b732
AK		 1185 asm volatile ("");
1186 vmcs_writel(field+1, value >> 32);
1187#endif
1188}
1189
2ab455cc
AL		 1190static void vmcs_clear_bits(unsigned long field, u32 mask)
1191{
1192 vmcs_writel(field, vmcs_readl(field) & ~mask);
1193}
1194
1195static void vmcs_set_bits(unsigned long field, u32 mask)
1196{
1197 vmcs_writel(field, vmcs_readl(field) | mask);
1198}
1199
2fb92db1
AK		 1200static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1201{
1202 vmx->segment_cache.bitmask = 0;
1203}
1204
1205static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1206 unsigned field)
1207{
1208 bool ret;
1209 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1210
1211 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1212 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1213 vmx->segment_cache.bitmask = 0;
1214 }
1215 ret = vmx->segment_cache.bitmask & mask;
1216 vmx->segment_cache.bitmask |= mask;
1217 return ret;
1218}
1219
1220static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1221{
1222 u16 *p = &vmx->segment_cache.seg[seg].selector;
1223
1224 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1225 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1226 return *p;
1227}
1228
1229static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1230{
1231 ulong *p = &vmx->segment_cache.seg[seg].base;
1232
1233 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1234 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1235 return *p;
1236}
1237
1238static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1239{
1240 u32 *p = &vmx->segment_cache.seg[seg].limit;
1241
1242 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1243 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1244 return *p;
1245}
1246
1247static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1248{
1249 u32 *p = &vmx->segment_cache.seg[seg].ar;
1250
1251 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1252 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1253 return *p;
1254}
1255
abd3f2d6
AK		 1256static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1257{
1258 u32 eb;
1259
fd7373cc
JK		 1260 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1261 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1262 if ((vcpu->guest_debug &
1263 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1264 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1265 eb |= 1u << BP_VECTOR;
7ffd92c5 1266 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1267 eb = ~0;
089d034e 1268 if (enable_ept)
1439442c 1269 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1270 if (vcpu->fpu_active)
1271 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1272
1273 /* When we are running a nested L2 guest and L1 specified for it a
1274 * certain exception bitmap, we must trap the same exceptions and pass
1275 * them to L1. When running L2, we will only handle the exceptions
1276 * specified above if L1 did not want them.
1277 */
1278 if (is_guest_mode(vcpu))
1279 eb |= get_vmcs12(vcpu)->exception_bitmap;
1280
abd3f2d6
AK		 1281 vmcs_write32(EXCEPTION_BITMAP, eb);
1282}
1283
8bf00a52
GN		 1284static void clear_atomic_switch_msr_special(unsigned long entry,
1285 unsigned long exit)
1286{
1287 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1288 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1289}
1290
61d2ef2c
AK		 1291static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1292{
1293 unsigned i;
1294 struct msr_autoload *m = &vmx->msr_autoload;
1295
8bf00a52
GN		 1296 switch (msr) {
1297 case MSR_EFER:
1298 if (cpu_has_load_ia32_efer) {
1299 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1300 VM_EXIT_LOAD_IA32_EFER);
1301 return;
1302 }
1303 break;
1304 case MSR_CORE_PERF_GLOBAL_CTRL:
1305 if (cpu_has_load_perf_global_ctrl) {
1306 clear_atomic_switch_msr_special(
1307 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1308 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1309 return;
1310 }
1311 break;
110312c8
AK		 1312 }
1313
61d2ef2c
AK		 1314 for (i = 0; i < m->nr; ++i)
1315 if (m->guest[i].index == msr)
1316 break;
1317
1318 if (i == m->nr)
1319 return;
1320 --m->nr;
1321 m->guest[i] = m->guest[m->nr];
1322 m->host[i] = m->host[m->nr];
1323 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1324 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1325}
1326
8bf00a52
GN		 1327static void add_atomic_switch_msr_special(unsigned long entry,
1328 unsigned long exit, unsigned long guest_val_vmcs,
1329 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1330{
1331 vmcs_write64(guest_val_vmcs, guest_val);
1332 vmcs_write64(host_val_vmcs, host_val);
1333 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1334 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1335}
1336
61d2ef2c
AK		 1337static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1338 u64 guest_val, u64 host_val)
1339{
1340 unsigned i;
1341 struct msr_autoload *m = &vmx->msr_autoload;
1342
8bf00a52
GN		 1343 switch (msr) {
1344 case MSR_EFER:
1345 if (cpu_has_load_ia32_efer) {
1346 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1347 VM_EXIT_LOAD_IA32_EFER,
1348 GUEST_IA32_EFER,
1349 HOST_IA32_EFER,
1350 guest_val, host_val);
1351 return;
1352 }
1353 break;
1354 case MSR_CORE_PERF_GLOBAL_CTRL:
1355 if (cpu_has_load_perf_global_ctrl) {
1356 add_atomic_switch_msr_special(
1357 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1358 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1359 GUEST_IA32_PERF_GLOBAL_CTRL,
1360 HOST_IA32_PERF_GLOBAL_CTRL,
1361 guest_val, host_val);
1362 return;
1363 }
1364 break;
110312c8
AK		 1365 }
1366
61d2ef2c
AK		 1367 for (i = 0; i < m->nr; ++i)
1368 if (m->guest[i].index == msr)
1369 break;
1370
e7fc6f93
GN		 1371 if (i == NR_AUTOLOAD_MSRS) {
1372 printk_once(KERN_WARNING"Not enough mst switch entries. "
1373 "Can't add msr %x\n", msr);
1374 return;
1375 } else if (i == m->nr) {
61d2ef2c
AK		 1376 ++m->nr;
1377 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1378 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1379 }
1380
1381 m->guest[i].index = msr;
1382 m->guest[i].value = guest_val;
1383 m->host[i].index = msr;
1384 m->host[i].value = host_val;
1385}
1386
33ed6329
AK		 1387static void reload_tss(void)
1388{
33ed6329
AK		 1389 /*
1390 * VT restores TR but not its size. Useless.
1391 */
d359192f 1392 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1393 struct desc_struct *descs;
33ed6329 1394
d359192f 1395 descs = (void *)gdt->address;
33ed6329
AK		 1396 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1397 load_TR_desc();
33ed6329
AK		 1398}
1399
92c0d900 1400static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1401{
3a34a881 1402 u64 guest_efer;
51c6cf66
AK		 1403 u64 ignore_bits;
1404
f6801dff 1405 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1406
51c6cf66 1407 /*
0fa06071 1408 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
51c6cf66
AK		 1409 * outside long mode
1410 */
1411 ignore_bits = EFER_NX | EFER_SCE;
1412#ifdef CONFIG_X86_64
1413 ignore_bits |= EFER_LMA | EFER_LME;
1414 /* SCE is meaningful only in long mode on Intel */
1415 if (guest_efer & EFER_LMA)
1416 ignore_bits &= ~(u64)EFER_SCE;
1417#endif
51c6cf66
AK		 1418 guest_efer &= ~ignore_bits;
1419 guest_efer |= host_efer & ignore_bits;
26bb0981 1420 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1421 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1422
1423 clear_atomic_switch_msr(vmx, MSR_EFER);
1424 /* On ept, can't emulate nx, and must switch nx atomically */
1425 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1426 guest_efer = vmx->vcpu.arch.efer;
1427 if (!(guest_efer & EFER_LMA))
1428 guest_efer &= ~EFER_LME;
1429 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1430 return false;
1431 }
1432
26bb0981 1433 return true;
51c6cf66
AK		 1434}
1435
2d49ec72
GN		 1436static unsigned long segment_base(u16 selector)
1437{
d359192f 1438 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1439 struct desc_struct *d;
1440 unsigned long table_base;
1441 unsigned long v;
1442
1443 if (!(selector & ~3))
1444 return 0;
1445
d359192f 1446 table_base = gdt->address;
2d49ec72
GN		 1447
1448 if (selector & 4) { /* from ldt */
1449 u16 ldt_selector = kvm_read_ldt();
1450
1451 if (!(ldt_selector & ~3))
1452 return 0;
1453
1454 table_base = segment_base(ldt_selector);
1455 }
1456 d = (struct desc_struct *)(table_base + (selector & ~7));
1457 v = get_desc_base(d);
1458#ifdef CONFIG_X86_64
1459 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1460 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1461#endif
1462 return v;
1463}
1464
1465static inline unsigned long kvm_read_tr_base(void)
1466{
1467 u16 tr;
1468 asm("str %0" : "=g"(tr));
1469 return segment_base(tr);
1470}
1471
04d2cc77 1472static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1473{
04d2cc77 1474 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1475 int i;
04d2cc77 1476
a2fa3e9f 1477 if (vmx->host_state.loaded)
33ed6329
AK		 1478 return;
1479
a2fa3e9f 1480 vmx->host_state.loaded = 1;
33ed6329
AK		 1481 /*
1482 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1483 * allow segment selectors with cpl > 0 or ti == 1.
1484 */
d6e88aec 1485 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1486 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1487 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1488 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1489 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1490 vmx->host_state.fs_reload_needed = 0;
1491 } else {
33ed6329 1492 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1493 vmx->host_state.fs_reload_needed = 1;
33ed6329 1494 }
9581d442 1495 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1496 if (!(vmx->host_state.gs_sel & 7))
1497 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1498 else {
1499 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1500 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1501 }
1502
b2da15ac
AK		 1503#ifdef CONFIG_X86_64
1504 savesegment(ds, vmx->host_state.ds_sel);
1505 savesegment(es, vmx->host_state.es_sel);
1506#endif
1507
33ed6329
AK		 1508#ifdef CONFIG_X86_64
1509 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1510 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1511#else
a2fa3e9f
GH		 1512 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1513 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1514#endif
707c0874
AK		 1515
1516#ifdef CONFIG_X86_64
c8770e7b
AK		 1517 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1518 if (is_long_mode(&vmx->vcpu))
44ea2b17 1519 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1520#endif
26bb0981
AK		 1521 for (i = 0; i < vmx->save_nmsrs; ++i)
1522 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1523 vmx->guest_msrs[i].data,
1524 vmx->guest_msrs[i].mask);
33ed6329
AK		 1525}
1526
a9b21b62 1527static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1528{
a2fa3e9f 1529 if (!vmx->host_state.loaded)
33ed6329
AK		 1530 return;
1531
e1beb1d3 1532 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1533 vmx->host_state.loaded = 0;
c8770e7b
AK		 1534#ifdef CONFIG_X86_64
1535 if (is_long_mode(&vmx->vcpu))
1536 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1537#endif
152d3f2f 1538 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1539 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1540#ifdef CONFIG_X86_64
9581d442 1541 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1542#else
1543 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1544#endif
33ed6329 1545 }
0a77fe4c
AK		 1546 if (vmx->host_state.fs_reload_needed)
1547 loadsegment(fs, vmx->host_state.fs_sel);
b2da15ac
AK		 1548#ifdef CONFIG_X86_64
1549 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1550 loadsegment(ds, vmx->host_state.ds_sel);
1551 loadsegment(es, vmx->host_state.es_sel);
1552 }
b2da15ac 1553#endif
152d3f2f 1554 reload_tss();
44ea2b17 1555#ifdef CONFIG_X86_64
c8770e7b 1556 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1557#endif
b1a74bf8
SS		 1558 /*
1559 * If the FPU is not active (through the host task or
1560 * the guest vcpu), then restore the cr0.TS bit.
1561 */
1562 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1563 stts();
3444d7da 1564 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1565}
1566
a9b21b62
AK		 1567static void vmx_load_host_state(struct vcpu_vmx *vmx)
1568{
1569 preempt_disable();
1570 __vmx_load_host_state(vmx);
1571 preempt_enable();
1572}
1573
6aa8b732
AK		 1574/*
1575 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1576 * vcpu mutex is already taken.
1577 */
15ad7146 1578static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1579{
a2fa3e9f 1580 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1581 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1582
4610c9cc
DX		 1583 if (!vmm_exclusive)
1584 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1585 else if (vmx->loaded_vmcs->cpu != cpu)
1586 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1587
d462b819
NHE		 1588 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1589 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1590 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1591 }
1592
d462b819 1593 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1594 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1595 unsigned long sysenter_esp;
1596
a8eeb04a 1597 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1598 local_irq_disable();
8f536b76 1599 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1600
1601 /*
1602 * Read loaded_vmcs->cpu should be before fetching
1603 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1604 * See the comments in __loaded_vmcs_clear().
1605 */
1606 smp_rmb();
1607
d462b819
NHE		 1608 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1609 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1610 crash_enable_local_vmclear(cpu);
92fe13be
DX		 1611 local_irq_enable();
1612
6aa8b732
AK		 1613 /*
1614 * Linux uses per-cpu TSS and GDT, so set these when switching
1615 * processors.
1616 */
d6e88aec 1617 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1618 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1619
1620 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1621 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1622 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1623 }
6aa8b732
AK		 1624}
1625
1626static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1627{
a9b21b62 1628 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1629 if (!vmm_exclusive) {
d462b819
NHE		 1630 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1631 vcpu->cpu = -1;
4610c9cc
DX		 1632 kvm_cpu_vmxoff();
1633 }
6aa8b732
AK		 1634}
1635
5fd86fcf
AK		 1636static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1637{
81231c69
AK		 1638 ulong cr0;
1639
5fd86fcf
AK		 1640 if (vcpu->fpu_active)
1641 return;
1642 vcpu->fpu_active = 1;
81231c69
AK		 1643 cr0 = vmcs_readl(GUEST_CR0);
1644 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1645 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1646 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1647 update_exception_bitmap(vcpu);
edcafe3c 1648 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1649 if (is_guest_mode(vcpu))
1650 vcpu->arch.cr0_guest_owned_bits &=
1651 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1652 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1653}
1654
edcafe3c
AK		 1655static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1656
fe3ef05c
NHE		 1657/*
1658 * Return the cr0 value that a nested guest would read. This is a combination
1659 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1660 * its hypervisor (cr0_read_shadow).
1661 */
1662static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1663{
1664 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1665 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1666}
1667static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1668{
1669 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1670 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1671}
1672
5fd86fcf
AK		 1673static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1674{
36cf24e0
NHE		 1675 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1676 * set this *before* calling this function.
1677 */
edcafe3c 1678 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1679 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1680 update_exception_bitmap(vcpu);
edcafe3c
AK		 1681 vcpu->arch.cr0_guest_owned_bits = 0;
1682 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1683 if (is_guest_mode(vcpu)) {
1684 /*
1685 * L1's specified read shadow might not contain the TS bit,
1686 * so now that we turned on shadowing of this bit, we need to
1687 * set this bit of the shadow. Like in nested_vmx_run we need
1688 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1689 * up-to-date here because we just decached cr0.TS (and we'll
1690 * only update vmcs12->guest_cr0 on nested exit).
1691 */
1692 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1693 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1694 (vcpu->arch.cr0 & X86_CR0_TS);
1695 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1696 } else
1697 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1698}
1699
6aa8b732
AK		 1700static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1701{
78ac8b47 1702 unsigned long rflags, save_rflags;
345dcaa8 1703
6de12732
AK		 1704 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1705 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1706 rflags = vmcs_readl(GUEST_RFLAGS);
1707 if (to_vmx(vcpu)->rmode.vm86_active) {
1708 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1709 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1710 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1711 }
1712 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1713 }
6de12732 1714 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1715}
1716
1717static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1718{
6de12732
AK		 1719 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1720 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1721 if (to_vmx(vcpu)->rmode.vm86_active) {
1722 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1723 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1724 }
6aa8b732
AK		 1725 vmcs_writel(GUEST_RFLAGS, rflags);
1726}
1727
2809f5d2
GC		 1728static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1729{
1730 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1731 int ret = 0;
1732
1733 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1734 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1735 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1736 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1737
1738 return ret & mask;
1739}
1740
1741static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1742{
1743 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1744 u32 interruptibility = interruptibility_old;
1745
1746 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1747
48005f64 1748 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1749 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1750 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1751 interruptibility |= GUEST_INTR_STATE_STI;
1752
1753 if ((interruptibility != interruptibility_old))
1754 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1755}
1756
6aa8b732
AK		 1757static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1758{
1759 unsigned long rip;
6aa8b732 1760
5fdbf976 1761 rip = kvm_rip_read(vcpu);
6aa8b732 1762 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1763 kvm_rip_write(vcpu, rip);
6aa8b732 1764
2809f5d2
GC		 1765 /* skipping an emulated instruction also counts */
1766 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1767}
1768
0b6ac343
NHE		 1769/*
1770 * KVM wants to inject page-faults which it got to the guest. This function
1771 * checks whether in a nested guest, we need to inject them to L1 or L2.
1772 * This function assumes it is called with the exit reason in vmcs02 being
1773 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1774 * is running).
1775 */
1776static int nested_pf_handled(struct kvm_vcpu *vcpu)
1777{
1778 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1779
1780 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
95871901 1781 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
0b6ac343
NHE		 1782 return 0;
1783
1784 nested_vmx_vmexit(vcpu);
1785 return 1;
1786}
1787
298101da 1788static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1789 bool has_error_code, u32 error_code,
1790 bool reinject)
298101da 1791{
77ab6db0 1792 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1793 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1794
0b6ac343
NHE		 1795 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1796 nested_pf_handled(vcpu))
1797 return;
1798
8ab2d2e2 1799 if (has_error_code) {
77ab6db0 1800 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1801 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1802 }
77ab6db0 1803
7ffd92c5 1804 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1805 int inc_eip = 0;
1806 if (kvm_exception_is_soft(nr))
1807 inc_eip = vcpu->arch.event_exit_inst_len;
1808 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1809 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1810 return;
1811 }
1812
66fd3f7f
GN		 1813 if (kvm_exception_is_soft(nr)) {
1814 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1815 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1816 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1817 } else
1818 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1819
1820 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1821}
1822
4e47c7a6
SY		 1823static bool vmx_rdtscp_supported(void)
1824{
1825 return cpu_has_vmx_rdtscp();
1826}
1827
ad756a16
MJ		 1828static bool vmx_invpcid_supported(void)
1829{
1830 return cpu_has_vmx_invpcid() && enable_ept;
1831}
1832
a75beee6
ED		 1833/*
1834 * Swap MSR entry in host/guest MSR entry array.
1835 */
8b9cf98c 1836static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1837{
26bb0981 1838 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1839
1840 tmp = vmx->guest_msrs[to];
1841 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1842 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1843}
1844
8d14695f
YZ		 1845static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
1846{
1847 unsigned long *msr_bitmap;
1848
1849 if (irqchip_in_kernel(vcpu->kvm) && apic_x2apic_mode(vcpu->arch.apic)) {
1850 if (is_long_mode(vcpu))
1851 msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
1852 else
1853 msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
1854 } else {
1855 if (is_long_mode(vcpu))
1856 msr_bitmap = vmx_msr_bitmap_longmode;
1857 else
1858 msr_bitmap = vmx_msr_bitmap_legacy;
1859 }
1860
1861 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1862}
1863
e38aea3e
AK		 1864/*
1865 * Set up the vmcs to automatically save and restore system
1866 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1867 * mode, as fiddling with msrs is very expensive.
1868 */
8b9cf98c 1869static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1870{
26bb0981 1871 int save_nmsrs, index;
e38aea3e 1872
a75beee6
ED		 1873 save_nmsrs = 0;
1874#ifdef CONFIG_X86_64
8b9cf98c 1875 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1876 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1877 if (index >= 0)
8b9cf98c
RR		 1878 move_msr_up(vmx, index, save_nmsrs++);
1879 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1880 if (index >= 0)
8b9cf98c
RR		 1881 move_msr_up(vmx, index, save_nmsrs++);
1882 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1883 if (index >= 0)
8b9cf98c 1884 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1885 index = __find_msr_index(vmx, MSR_TSC_AUX);
1886 if (index >= 0 && vmx->rdtscp_enabled)
1887 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1888 /*
8c06585d 1889 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1890 * if efer.sce is enabled.
1891 */
8c06585d 1892 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1893 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1894 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1895 }
1896#endif
92c0d900
AK		 1897 index = __find_msr_index(vmx, MSR_EFER);
1898 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1899 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1900
26bb0981 1901 vmx->save_nmsrs = save_nmsrs;
5897297b 1902
8d14695f
YZ		 1903 if (cpu_has_vmx_msr_bitmap())
1904 vmx_set_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1905}
1906
6aa8b732
AK		 1907/*
1908 * reads and returns guest's timestamp counter "register"
1909 * guest_tsc = host_tsc + tsc_offset -- 21.3
1910 */
1911static u64 guest_read_tsc(void)
1912{
1913 u64 host_tsc, tsc_offset;
1914
1915 rdtscll(host_tsc);
1916 tsc_offset = vmcs_read64(TSC_OFFSET);
1917 return host_tsc + tsc_offset;
1918}
1919
d5c1785d
NHE		 1920/*
1921 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1922 * counter, even if a nested guest (L2) is currently running.
1923 */
886b470c 1924u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
d5c1785d 1925{
886b470c 1926 u64 tsc_offset;
d5c1785d 1927
d5c1785d
NHE		 1928 tsc_offset = is_guest_mode(vcpu) ?
1929 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1930 vmcs_read64(TSC_OFFSET);
1931 return host_tsc + tsc_offset;
1932}
1933
4051b188 1934/*
cc578287
ZA		 1935 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1936 * software catchup for faster rates on slower CPUs.
4051b188 1937 */
cc578287 1938static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
4051b188 1939{
cc578287
ZA		 1940 if (!scale)
1941 return;
1942
1943 if (user_tsc_khz > tsc_khz) {
1944 vcpu->arch.tsc_catchup = 1;
1945 vcpu->arch.tsc_always_catchup = 1;
1946 } else
1947 WARN(1, "user requested TSC rate below hardware speed\n");
4051b188
JR		 1948}
1949
ba904635
WA		 1950static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1951{
1952 return vmcs_read64(TSC_OFFSET);
1953}
1954
6aa8b732 1955/*
99e3e30a 1956 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1957 */
99e3e30a 1958static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1959{
27fc51b2 1960 if (is_guest_mode(vcpu)) {
7991825b 1961 /*
27fc51b2
NHE		 1962 * We're here if L1 chose not to trap WRMSR to TSC. According
1963 * to the spec, this should set L1's TSC; The offset that L1
1964 * set for L2 remains unchanged, and still needs to be added
1965 * to the newly set TSC to get L2's TSC.
7991825b 1966 */
27fc51b2
NHE		 1967 struct vmcs12 *vmcs12;
1968 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1969 /* recalculate vmcs02.TSC_OFFSET: */
1970 vmcs12 = get_vmcs12(vcpu);
1971 vmcs_write64(TSC_OFFSET, offset +
1972 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1973 vmcs12->tsc_offset : 0));
1974 } else {
1975 vmcs_write64(TSC_OFFSET, offset);
1976 }
6aa8b732
AK		 1977}
1978
f1e2b260 1979static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
e48672fa
ZA		 1980{
1981 u64 offset = vmcs_read64(TSC_OFFSET);
1982 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1983 if (is_guest_mode(vcpu)) {
1984 /* Even when running L2, the adjustment needs to apply to L1 */
1985 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1986 }
e48672fa
ZA		 1987}
1988
857e4099
JR		 1989static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1990{
1991 return target_tsc - native_read_tsc();
1992}
1993
801d3424
NHE		 1994static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1995{
1996 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1997 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1998}
1999
2000/*
2001 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2002 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2003 * all guests if the "nested" module option is off, and can also be disabled
2004 * for a single guest by disabling its VMX cpuid bit.
2005 */
2006static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2007{
2008 return nested && guest_cpuid_has_vmx(vcpu);
2009}
2010
b87a51ae
NHE		 2011/*
2012 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2013 * returned for the various VMX controls MSRs when nested VMX is enabled.
2014 * The same values should also be used to verify that vmcs12 control fields are
2015 * valid during nested entry from L1 to L2.
2016 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2017 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2018 * bit in the high half is on if the corresponding bit in the control field
2019 * may be on. See also vmx_control_verify().
2020 * TODO: allow these variables to be modified (downgraded) by module options
2021 * or other means.
2022 */
2023static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
2024static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
2025static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
2026static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
2027static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
c18911a2 2028static u32 nested_vmx_misc_low, nested_vmx_misc_high;
b87a51ae
NHE		 2029static __init void nested_vmx_setup_ctls_msrs(void)
2030{
2031 /*
2032 * Note that as a general rule, the high half of the MSRs (bits in
2033 * the control fields which may be 1) should be initialized by the
2034 * intersection of the underlying hardware's MSR (i.e., features which
2035 * can be supported) and the list of features we want to expose -
2036 * because they are known to be properly supported in our code.
2037 * Also, usually, the low half of the MSRs (bits which must be 1) can
2038 * be set to 0, meaning that L1 may turn off any of these bits. The
2039 * reason is that if one of these bits is necessary, it will appear
2040 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2041 * fields of vmcs01 and vmcs02, will turn these bits off - and
2042 * nested_vmx_exit_handled() will not pass related exits to L1.
2043 * These rules have exceptions below.
2044 */
2045
2046 /* pin-based controls */
eabeaacc
JK		 2047 rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2048 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high);
b87a51ae
NHE		 2049 /*
2050 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2051 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2052 */
eabeaacc
JK		 2053 nested_vmx_pinbased_ctls_low |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2054 nested_vmx_pinbased_ctls_high &= PIN_BASED_EXT_INTR_MASK |
0238ea91
JK		 2055 PIN_BASED_NMI_EXITING | PIN_BASED_VIRTUAL_NMIS |
2056 PIN_BASED_VMX_PREEMPTION_TIMER;
eabeaacc 2057 nested_vmx_pinbased_ctls_high |= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae 2058
33fb20c3
JK		 2059 /*
2060 * Exit controls
2061 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2062 * 17 must be 1.
2063 */
2064 nested_vmx_exit_ctls_low = VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b6f1250e 2065 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 2066#ifdef CONFIG_X86_64
2067 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
2068#else
2069 nested_vmx_exit_ctls_high = 0;
2070#endif
33fb20c3 2071 nested_vmx_exit_ctls_high |= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2072
2073 /* entry controls */
2074 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2075 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
33fb20c3
JK		 2076 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2077 nested_vmx_entry_ctls_low = VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2078 nested_vmx_entry_ctls_high &=
2079 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
33fb20c3 2080 nested_vmx_entry_ctls_high |= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
b87a51ae
NHE		 2081
2082 /* cpu-based controls */
2083 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2084 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2085 nested_vmx_procbased_ctls_low = 0;
2086 nested_vmx_procbased_ctls_high &=
2087 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2088 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2089 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2090 CPU_BASED_CR3_STORE_EXITING |
2091#ifdef CONFIG_X86_64
2092 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2093#endif
2094 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2095 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
dbcb4e79 2096 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
d6851fbe 2097 CPU_BASED_PAUSE_EXITING |
b87a51ae
NHE		 2098 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2099 /*
2100 * We can allow some features even when not supported by the
2101 * hardware. For example, L1 can specify an MSR bitmap - and we
2102 * can use it to avoid exits to L1 - even when L0 runs L2
2103 * without MSR bitmaps.
2104 */
2105 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2106
2107 /* secondary cpu-based controls */
2108 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2109 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2110 nested_vmx_secondary_ctls_low = 0;
2111 nested_vmx_secondary_ctls_high &=
d6851fbe
JK		 2112 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2113 SECONDARY_EXEC_WBINVD_EXITING;
c18911a2
JK		 2114
2115 /* miscellaneous data */
2116 rdmsr(MSR_IA32_VMX_MISC, nested_vmx_misc_low, nested_vmx_misc_high);
0238ea91
JK		 2117 nested_vmx_misc_low &= VMX_MISC_PREEMPTION_TIMER_RATE_MASK |
2118 VMX_MISC_SAVE_EFER_LMA;
c18911a2 2119 nested_vmx_misc_high = 0;
b87a51ae
NHE		 2120}
2121
2122static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2123{
2124 /*
2125 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2126 */
2127 return ((control & high) | low) == control;
2128}
2129
2130static inline u64 vmx_control_msr(u32 low, u32 high)
2131{
2132 return low | ((u64)high << 32);
2133}
2134
2135/*
2136 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2137 * also let it use VMX-specific MSRs.
2138 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2139 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2140 * like all other MSRs).
2141 */
2142static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2143{
2144 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2145 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2146 /*
2147 * According to the spec, processors which do not support VMX
2148 * should throw a #GP(0) when VMX capability MSRs are read.
2149 */
2150 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2151 return 1;
2152 }
2153
2154 switch (msr_index) {
2155 case MSR_IA32_FEATURE_CONTROL:
2156 *pdata = 0;
2157 break;
2158 case MSR_IA32_VMX_BASIC:
2159 /*
2160 * This MSR reports some information about VMX support. We
2161 * should return information about the VMX we emulate for the
2162 * guest, and the VMCS structure we give it - not about the
2163 * VMX support of the underlying hardware.
2164 */
2165 *pdata = VMCS12_REVISION |
2166 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2167 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2168 break;
2169 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2170 case MSR_IA32_VMX_PINBASED_CTLS:
2171 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2172 nested_vmx_pinbased_ctls_high);
2173 break;
2174 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2175 case MSR_IA32_VMX_PROCBASED_CTLS:
2176 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2177 nested_vmx_procbased_ctls_high);
2178 break;
2179 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2180 case MSR_IA32_VMX_EXIT_CTLS:
2181 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2182 nested_vmx_exit_ctls_high);
2183 break;
2184 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2185 case MSR_IA32_VMX_ENTRY_CTLS:
2186 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2187 nested_vmx_entry_ctls_high);
2188 break;
2189 case MSR_IA32_VMX_MISC:
c18911a2
JK		 2190 *pdata = vmx_control_msr(nested_vmx_misc_low,
2191 nested_vmx_misc_high);
b87a51ae
NHE		 2192 break;
2193 /*
2194 * These MSRs specify bits which the guest must keep fixed (on or off)
2195 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2196 * We picked the standard core2 setting.
2197 */
2198#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2199#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2200 case MSR_IA32_VMX_CR0_FIXED0:
2201 *pdata = VMXON_CR0_ALWAYSON;
2202 break;
2203 case MSR_IA32_VMX_CR0_FIXED1:
2204 *pdata = -1ULL;
2205 break;
2206 case MSR_IA32_VMX_CR4_FIXED0:
2207 *pdata = VMXON_CR4_ALWAYSON;
2208 break;
2209 case MSR_IA32_VMX_CR4_FIXED1:
2210 *pdata = -1ULL;
2211 break;
2212 case MSR_IA32_VMX_VMCS_ENUM:
2213 *pdata = 0x1f;
2214 break;
2215 case MSR_IA32_VMX_PROCBASED_CTLS2:
2216 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2217 nested_vmx_secondary_ctls_high);
2218 break;
2219 case MSR_IA32_VMX_EPT_VPID_CAP:
2220 /* Currently, no nested ept or nested vpid */
2221 *pdata = 0;
2222 break;
2223 default:
2224 return 0;
2225 }
2226
2227 return 1;
2228}
2229
2230static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2231{
2232 if (!nested_vmx_allowed(vcpu))
2233 return 0;
2234
2235 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2236 /* TODO: the right thing. */
2237 return 1;
2238 /*
2239 * No need to treat VMX capability MSRs specially: If we don't handle
2240 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2241 */
2242 return 0;
2243}
2244
6aa8b732
AK		 2245/*
2246 * Reads an msr value (of 'msr_index') into 'pdata'.
2247 * Returns 0 on success, non-0 otherwise.
2248 * Assumes vcpu_load() was already called.
2249 */
2250static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2251{
2252 u64 data;
26bb0981 2253 struct shared_msr_entry *msr;
6aa8b732
AK		 2254
2255 if (!pdata) {
2256 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2257 return -EINVAL;
2258 }
2259
2260 switch (msr_index) {
05b3e0c2 2261#ifdef CONFIG_X86_64
6aa8b732
AK		 2262 case MSR_FS_BASE:
2263 data = vmcs_readl(GUEST_FS_BASE);
2264 break;
2265 case MSR_GS_BASE:
2266 data = vmcs_readl(GUEST_GS_BASE);
2267 break;
44ea2b17
AK		 2268 case MSR_KERNEL_GS_BASE:
2269 vmx_load_host_state(to_vmx(vcpu));
2270 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2271 break;
26bb0981 2272#endif
6aa8b732 2273 case MSR_EFER:
3bab1f5d 2274 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2275 case MSR_IA32_TSC:
6aa8b732
AK		 2276 data = guest_read_tsc();
2277 break;
2278 case MSR_IA32_SYSENTER_CS:
2279 data = vmcs_read32(GUEST_SYSENTER_CS);
2280 break;
2281 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2282 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2283 break;
2284 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2285 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2286 break;
4e47c7a6
SY		 2287 case MSR_TSC_AUX:
2288 if (!to_vmx(vcpu)->rdtscp_enabled)
2289 return 1;
2290 /* Otherwise falls through */
6aa8b732 2291 default:
b87a51ae
NHE		 2292 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2293 return 0;
8b9cf98c 2294 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d
AK		 2295 if (msr) {
2296 data = msr->data;
2297 break;
6aa8b732 2298 }
3bab1f5d 2299 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2300 }
2301
2302 *pdata = data;
2303 return 0;
2304}
2305
2306/*
2307 * Writes msr value into into the appropriate "register".
2308 * Returns 0 on success, non-0 otherwise.
2309 * Assumes vcpu_load() was already called.
2310 */
8fe8ab46 2311static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 2312{
a2fa3e9f 2313 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2314 struct shared_msr_entry *msr;
2cc51560 2315 int ret = 0;
8fe8ab46
WA		 2316 u32 msr_index = msr_info->index;
2317 u64 data = msr_info->data;
2cc51560 2318
6aa8b732 2319 switch (msr_index) {
3bab1f5d 2320 case MSR_EFER:
8fe8ab46 2321 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 2322 break;
16175a79 2323#ifdef CONFIG_X86_64
6aa8b732 2324 case MSR_FS_BASE:
2fb92db1 2325 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2326 vmcs_writel(GUEST_FS_BASE, data);
2327 break;
2328 case MSR_GS_BASE:
2fb92db1 2329 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2330 vmcs_writel(GUEST_GS_BASE, data);
2331 break;
44ea2b17
AK		 2332 case MSR_KERNEL_GS_BASE:
2333 vmx_load_host_state(vmx);
2334 vmx->msr_guest_kernel_gs_base = data;
2335 break;
6aa8b732
AK		 2336#endif
2337 case MSR_IA32_SYSENTER_CS:
2338 vmcs_write32(GUEST_SYSENTER_CS, data);
2339 break;
2340 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2341 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2342 break;
2343 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2344 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2345 break;
af24a4e4 2346 case MSR_IA32_TSC:
8fe8ab46 2347 kvm_write_tsc(vcpu, msr_info);
6aa8b732 2348 break;
468d472f
SY		 2349 case MSR_IA32_CR_PAT:
2350 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2351 vmcs_write64(GUEST_IA32_PAT, data);
2352 vcpu->arch.pat = data;
2353 break;
2354 }
8fe8ab46 2355 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 2356 break;
ba904635
WA		 2357 case MSR_IA32_TSC_ADJUST:
2358 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6
SY		 2359 break;
2360 case MSR_TSC_AUX:
2361 if (!vmx->rdtscp_enabled)
2362 return 1;
2363 /* Check reserved bit, higher 32 bits should be zero */
2364 if ((data >> 32) != 0)
2365 return 1;
2366 /* Otherwise falls through */
6aa8b732 2367 default:
b87a51ae
NHE		 2368 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2369 break;
8b9cf98c 2370 msr = find_msr_entry(vmx, msr_index);
3bab1f5d
AK		 2371 if (msr) {
2372 msr->data = data;
2225fd56
AK		 2373 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2374 preempt_disable();
9ee73970
AK		 2375 kvm_set_shared_msr(msr->index, msr->data,
2376 msr->mask);
2225fd56
AK		 2377 preempt_enable();
2378 }
3bab1f5d 2379 break;
6aa8b732 2380 }
8fe8ab46 2381 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 2382 }
2383
2cc51560 2384 return ret;
6aa8b732
AK		 2385}
2386
5fdbf976 2387static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2388{
5fdbf976
MT		 2389 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2390 switch (reg) {
2391 case VCPU_REGS_RSP:
2392 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2393 break;
2394 case VCPU_REGS_RIP:
2395 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2396 break;
6de4f3ad
AK		 2397 case VCPU_EXREG_PDPTR:
2398 if (enable_ept)
2399 ept_save_pdptrs(vcpu);
2400 break;
5fdbf976
MT		 2401 default:
2402 break;
2403 }
6aa8b732
AK		 2404}
2405
6aa8b732
AK		 2406static __init int cpu_has_kvm_support(void)
2407{
6210e37b 2408 return cpu_has_vmx();
6aa8b732
AK		 2409}
2410
2411static __init int vmx_disabled_by_bios(void)
2412{
2413 u64 msr;
2414
2415 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2416 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2417 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2418 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2419 && tboot_enabled())
2420 return 1;
23f3e991 2421 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2422 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2423 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2424 && !tboot_enabled()) {
2425 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2426 "activate TXT before enabling KVM\n");
cafd6659 2427 return 1;
f9335afe 2428 }
23f3e991
JC		 2429 /* launched w/o TXT and VMX disabled */
2430 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2431 && !tboot_enabled())
2432 return 1;
cafd6659
SW		 2433 }
2434
2435 return 0;
6aa8b732
AK		 2436}
2437
7725b894
DX		 2438static void kvm_cpu_vmxon(u64 addr)
2439{
2440 asm volatile (ASM_VMX_VMXON_RAX
2441 : : "a"(&addr), "m"(addr)
2442 : "memory", "cc");
2443}
2444
10474ae8 2445static int hardware_enable(void *garbage)
6aa8b732
AK		 2446{
2447 int cpu = raw_smp_processor_id();
2448 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2449 u64 old, test_bits;
6aa8b732 2450
10474ae8
AG		 2451 if (read_cr4() & X86_CR4_VMXE)
2452 return -EBUSY;
2453
d462b819 2454 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76
ZY		 2455
2456 /*
2457 * Now we can enable the vmclear operation in kdump
2458 * since the loaded_vmcss_on_cpu list on this cpu
2459 * has been initialized.
2460 *
2461 * Though the cpu is not in VMX operation now, there
2462 * is no problem to enable the vmclear operation
2463 * for the loaded_vmcss_on_cpu list is empty!
2464 */
2465 crash_enable_local_vmclear(cpu);
2466
6aa8b732 2467 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2468
2469 test_bits = FEATURE_CONTROL_LOCKED;
2470 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2471 if (tboot_enabled())
2472 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2473
2474 if ((old & test_bits) != test_bits) {
6aa8b732 2475 /* enable and lock */
cafd6659
SW		 2476 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2477 }
66aee91a 2478 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2479
4610c9cc
DX		 2480 if (vmm_exclusive) {
2481 kvm_cpu_vmxon(phys_addr);
2482 ept_sync_global();
2483 }
10474ae8 2484
3444d7da
AK		 2485 store_gdt(&__get_cpu_var(host_gdt));
2486
10474ae8 2487 return 0;
6aa8b732
AK		 2488}
2489
d462b819 2490static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2491{
2492 int cpu = raw_smp_processor_id();
d462b819 2493 struct loaded_vmcs *v, *n;
543e4243 2494
d462b819
NHE		 2495 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2496 loaded_vmcss_on_cpu_link)
2497 __loaded_vmcs_clear(v);
543e4243
AK		 2498}
2499
710ff4a8
EH		 2500
2501/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2502 * tricks.
2503 */
2504static void kvm_cpu_vmxoff(void)
6aa8b732 2505{
4ecac3fd 2506 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2507}
2508
710ff4a8
EH		 2509static void hardware_disable(void *garbage)
2510{
4610c9cc 2511 if (vmm_exclusive) {
d462b819 2512 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2513 kvm_cpu_vmxoff();
2514 }
7725b894 2515 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2516}
2517
1c3d14fe 2518static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2519 u32 msr, u32 *result)
1c3d14fe
YS		 2520{
2521 u32 vmx_msr_low, vmx_msr_high;
2522 u32 ctl = ctl_min | ctl_opt;
2523
2524 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2525
2526 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2527 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2528
2529 /* Ensure minimum (required) set of control bits are supported. */
2530 if (ctl_min & ~ctl)
002c7f7c 2531 return -EIO;
1c3d14fe
YS		 2532
2533 *result = ctl;
2534 return 0;
2535}
2536
110312c8
AK		 2537static __init bool allow_1_setting(u32 msr, u32 ctl)
2538{
2539 u32 vmx_msr_low, vmx_msr_high;
2540
2541 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2542 return vmx_msr_high & ctl;
2543}
2544
002c7f7c 2545static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2546{
2547 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2548 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2549 u32 _pin_based_exec_control = 0;
2550 u32 _cpu_based_exec_control = 0;
f78e0e2e 2551 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2552 u32 _vmexit_control = 0;
2553 u32 _vmentry_control = 0;
2554
2555 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2556 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2557 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2558 &_pin_based_exec_control) < 0)
002c7f7c 2559 return -EIO;
1c3d14fe 2560
10166744 2561 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 2562#ifdef CONFIG_X86_64
2563 CPU_BASED_CR8_LOAD_EXITING |
2564 CPU_BASED_CR8_STORE_EXITING |
2565#endif
d56f546d
SY		 2566 CPU_BASED_CR3_LOAD_EXITING |
2567 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2568 CPU_BASED_USE_IO_BITMAPS |
2569 CPU_BASED_MOV_DR_EXITING |
a7052897 2570 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2571 CPU_BASED_MWAIT_EXITING |
2572 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 2573 CPU_BASED_INVLPG_EXITING |
2574 CPU_BASED_RDPMC_EXITING;
443381a8 2575
f78e0e2e 2576 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2577 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2578 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2579 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2580 &_cpu_based_exec_control) < 0)
002c7f7c 2581 return -EIO;
6e5d865c
YS		 2582#ifdef CONFIG_X86_64
2583 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2584 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2585 ~CPU_BASED_CR8_STORE_EXITING;
2586#endif
f78e0e2e 2587 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2588 min2 = 0;
2589 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 2590 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 2591 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2592 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2593 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2594 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 2595 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
ad756a16 2596 SECONDARY_EXEC_RDTSCP |
83d4c286 2597 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c
YZ		 2598 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2599 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
d56f546d
SY		 2600 if (adjust_vmx_controls(min2, opt2,
2601 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2602 &_cpu_based_2nd_exec_control) < 0)
2603 return -EIO;
2604 }
2605#ifndef CONFIG_X86_64
2606 if (!(_cpu_based_2nd_exec_control &
2607 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2608 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2609#endif
83d4c286
YZ		 2610
2611 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2612 _cpu_based_2nd_exec_control &= ~(
8d14695f 2613 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 2614 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2615 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 2616
d56f546d 2617 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2618 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2619 enabled */
5fff7d27
GN		 2620 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2621 CPU_BASED_CR3_STORE_EXITING |
2622 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2623 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2624 vmx_capability.ept, vmx_capability.vpid);
2625 }
1c3d14fe
YS		 2626
2627 min = 0;
2628#ifdef CONFIG_X86_64
2629 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2630#endif
a547c6db
YZ		 2631 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
2632 VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2633 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2634 &_vmexit_control) < 0)
002c7f7c 2635 return -EIO;
1c3d14fe 2636
468d472f
SY		 2637 min = 0;
2638 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2639 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2640 &_vmentry_control) < 0)
002c7f7c 2641 return -EIO;
6aa8b732 2642
c68876fd 2643 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2644
2645 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2646 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2647 return -EIO;
1c3d14fe
YS		 2648
2649#ifdef CONFIG_X86_64
2650 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2651 if (vmx_msr_high & (1u<<16))
002c7f7c 2652 return -EIO;
1c3d14fe
YS		 2653#endif
2654
2655 /* Require Write-Back (WB) memory type for VMCS accesses. */
2656 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2657 return -EIO;
1c3d14fe 2658
002c7f7c
YS		 2659 vmcs_conf->size = vmx_msr_high & 0x1fff;
2660 vmcs_conf->order = get_order(vmcs_config.size);
2661 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2662
002c7f7c
YS		 2663 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2664 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2665 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2666 vmcs_conf->vmexit_ctrl = _vmexit_control;
2667 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2668
110312c8
AK		 2669 cpu_has_load_ia32_efer =
2670 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2671 VM_ENTRY_LOAD_IA32_EFER)
2672 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2673 VM_EXIT_LOAD_IA32_EFER);
2674
8bf00a52
GN		 2675 cpu_has_load_perf_global_ctrl =
2676 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2677 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2678 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2679 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2680
2681 /*
2682 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2683 * but due to arrata below it can't be used. Workaround is to use
2684 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2685 *
2686 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2687 *
2688 * AAK155 (model 26)
2689 * AAP115 (model 30)
2690 * AAT100 (model 37)
2691 * BC86,AAY89,BD102 (model 44)
2692 * BA97 (model 46)
2693 *
2694 */
2695 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2696 switch (boot_cpu_data.x86_model) {
2697 case 26:
2698 case 30:
2699 case 37:
2700 case 44:
2701 case 46:
2702 cpu_has_load_perf_global_ctrl = false;
2703 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2704 "does not work properly. Using workaround\n");
2705 break;
2706 default:
2707 break;
2708 }
2709 }
2710
1c3d14fe 2711 return 0;
c68876fd 2712}
6aa8b732
AK		 2713
2714static struct vmcs *alloc_vmcs_cpu(int cpu)
2715{
2716 int node = cpu_to_node(cpu);
2717 struct page *pages;
2718 struct vmcs *vmcs;
2719
6484eb3e 2720 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2721 if (!pages)
2722 return NULL;
2723 vmcs = page_address(pages);
1c3d14fe
YS		 2724 memset(vmcs, 0, vmcs_config.size);
2725 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2726 return vmcs;
2727}
2728
2729static struct vmcs *alloc_vmcs(void)
2730{
d3b2c338 2731 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2732}
2733
2734static void free_vmcs(struct vmcs *vmcs)
2735{
1c3d14fe 2736 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2737}
2738
d462b819
NHE		 2739/*
2740 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2741 */
2742static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2743{
2744 if (!loaded_vmcs->vmcs)
2745 return;
2746 loaded_vmcs_clear(loaded_vmcs);
2747 free_vmcs(loaded_vmcs->vmcs);
2748 loaded_vmcs->vmcs = NULL;
2749}
2750
39959588 2751static void free_kvm_area(void)
6aa8b732
AK		 2752{
2753 int cpu;
2754
3230bb47 2755 for_each_possible_cpu(cpu) {
6aa8b732 2756 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2757 per_cpu(vmxarea, cpu) = NULL;
2758 }
6aa8b732
AK		 2759}
2760
6aa8b732
AK		 2761static __init int alloc_kvm_area(void)
2762{
2763 int cpu;
2764
3230bb47 2765 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2766 struct vmcs *vmcs;
2767
2768 vmcs = alloc_vmcs_cpu(cpu);
2769 if (!vmcs) {
2770 free_kvm_area();
2771 return -ENOMEM;
2772 }
2773
2774 per_cpu(vmxarea, cpu) = vmcs;
2775 }
2776 return 0;
2777}
2778
2779static __init int hardware_setup(void)
2780{
002c7f7c
YS		 2781 if (setup_vmcs_config(&vmcs_config) < 0)
2782 return -EIO;
50a37eb4
JR		 2783
2784 if (boot_cpu_has(X86_FEATURE_NX))
2785 kvm_enable_efer_bits(EFER_NX);
2786
93ba03c2
SY		 2787 if (!cpu_has_vmx_vpid())
2788 enable_vpid = 0;
2789
4bc9b982
SY		 2790 if (!cpu_has_vmx_ept() ||
2791 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2792 enable_ept = 0;
3a624e29 2793 enable_unrestricted_guest = 0;
83c3a331 2794 enable_ept_ad_bits = 0;
3a624e29
NK		 2795 }
2796
83c3a331
XH		 2797 if (!cpu_has_vmx_ept_ad_bits())
2798 enable_ept_ad_bits = 0;
2799
3a624e29
NK		 2800 if (!cpu_has_vmx_unrestricted_guest())
2801 enable_unrestricted_guest = 0;
93ba03c2
SY		 2802
2803 if (!cpu_has_vmx_flexpriority())
2804 flexpriority_enabled = 0;
2805
95ba8273
GN		 2806 if (!cpu_has_vmx_tpr_shadow())
2807 kvm_x86_ops->update_cr8_intercept = NULL;
2808
54dee993
MT		 2809 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2810 kvm_disable_largepages();
2811
4b8d54f9
ZE		 2812 if (!cpu_has_vmx_ple())
2813 ple_gap = 0;
2814
c7c9c56c
YZ		 2815 if (!cpu_has_vmx_apic_register_virt() ||
2816 !cpu_has_vmx_virtual_intr_delivery())
2817 enable_apicv_reg_vid = 0;
2818
2819 if (enable_apicv_reg_vid)
2820 kvm_x86_ops->update_cr8_intercept = NULL;
2821 else
2822 kvm_x86_ops->hwapic_irr_update = NULL;
83d4c286 2823
b87a51ae
NHE		 2824 if (nested)
2825 nested_vmx_setup_ctls_msrs();
2826
6aa8b732
AK		 2827 return alloc_kvm_area();
2828}
2829
2830static __exit void hardware_unsetup(void)
2831{
2832 free_kvm_area();
2833}
2834
14168786
GN		 2835static bool emulation_required(struct kvm_vcpu *vcpu)
2836{
2837 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
2838}
2839
91b0aa2c 2840static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2841 struct kvm_segment *save)
6aa8b732 2842{
d99e4152
GN		 2843 if (!emulate_invalid_guest_state) {
2844 /*
2845 * CS and SS RPL should be equal during guest entry according
2846 * to VMX spec, but in reality it is not always so. Since vcpu
2847 * is in the middle of the transition from real mode to
2848 * protected mode it is safe to assume that RPL 0 is a good
2849 * default value.
2850 */
2851 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
2852 save->selector &= ~SELECTOR_RPL_MASK;
2853 save->dpl = save->selector & SELECTOR_RPL_MASK;
2854 save->s = 1;
6aa8b732 2855 }
d99e4152 2856 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2857}
2858
2859static void enter_pmode(struct kvm_vcpu *vcpu)
2860{
2861 unsigned long flags;
a89a8fb9 2862 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2863
d99e4152
GN		 2864 /*
2865 * Update real mode segment cache. It may be not up-to-date if sement
2866 * register was written while vcpu was in a guest mode.
2867 */
2868 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2869 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2870 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2871 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2872 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2873 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2874
7ffd92c5 2875 vmx->rmode.vm86_active = 0;
6aa8b732 2876
2fb92db1
AK		 2877 vmx_segment_cache_clear(vmx);
2878
f5f7b2fe 2879 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2880
2881 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2882 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2883 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2884 vmcs_writel(GUEST_RFLAGS, flags);
2885
66aee91a
RR		 2886 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2887 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2888
2889 update_exception_bitmap(vcpu);
2890
91b0aa2c
GN		 2891 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2892 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2893 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2894 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2895 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2896 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
1f3141e8
GN		 2897
2898 /* CPL is always 0 when CPU enters protected mode */
2899 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2900 vmx->cpl = 0;
6aa8b732
AK		 2901}
2902
f5f7b2fe 2903static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2904{
772e0318 2905 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2906 struct kvm_segment var = *save;
2907
2908 var.dpl = 0x3;
2909 if (seg == VCPU_SREG_CS)
2910 var.type = 0x3;
2911
2912 if (!emulate_invalid_guest_state) {
2913 var.selector = var.base >> 4;
2914 var.base = var.base & 0xffff0;
2915 var.limit = 0xffff;
2916 var.g = 0;
2917 var.db = 0;
2918 var.present = 1;
2919 var.s = 1;
2920 var.l = 0;
2921 var.unusable = 0;
2922 var.type = 0x3;
2923 var.avl = 0;
2924 if (save->base & 0xf)
2925 printk_once(KERN_WARNING "kvm: segment base is not "
2926 "paragraph aligned when entering "
2927 "protected mode (seg=%d)", seg);
2928 }
6aa8b732 2929
d99e4152
GN		 2930 vmcs_write16(sf->selector, var.selector);
2931 vmcs_write32(sf->base, var.base);
2932 vmcs_write32(sf->limit, var.limit);
2933 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2934}
2935
2936static void enter_rmode(struct kvm_vcpu *vcpu)
2937{
2938 unsigned long flags;
a89a8fb9 2939 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2940
f5f7b2fe
AK		 2941 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2942 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2943 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2944 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2945 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2946 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2947 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2948
7ffd92c5 2949 vmx->rmode.vm86_active = 1;
6aa8b732 2950
776e58ea
GN		 2951 /*
2952 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2953 * vcpu. Warn the user that an update is overdue.
776e58ea 2954 */
4918c6ca 2955 if (!vcpu->kvm->arch.tss_addr)
776e58ea
GN		 2956 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2957 "called before entering vcpu\n");
776e58ea 2958
2fb92db1
AK		 2959 vmx_segment_cache_clear(vmx);
2960
4918c6ca 2961 vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
6aa8b732 2962 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2963 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2964
2965 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2966 vmx->rmode.save_rflags = flags;
6aa8b732 2967
053de044 2968 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2969
2970 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2971 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2972 update_exception_bitmap(vcpu);
2973
d99e4152
GN		 2974 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2975 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2976 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2977 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2978 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2979 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2980
8668a3c4 2981 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2982}
2983
401d10de
AS		 2984static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2985{
2986 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2987 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2988
2989 if (!msr)
2990 return;
401d10de 2991
44ea2b17
AK		 2992 /*
2993 * Force kernel_gs_base reloading before EFER changes, as control
2994 * of this msr depends on is_long_mode().
2995 */
2996 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2997 vcpu->arch.efer = efer;
401d10de
AS		 2998 if (efer & EFER_LMA) {
2999 vmcs_write32(VM_ENTRY_CONTROLS,
3000 vmcs_read32(VM_ENTRY_CONTROLS) |
3001 VM_ENTRY_IA32E_MODE);
3002 msr->data = efer;
3003 } else {
3004 vmcs_write32(VM_ENTRY_CONTROLS,
3005 vmcs_read32(VM_ENTRY_CONTROLS) &
3006 ~VM_ENTRY_IA32E_MODE);
3007
3008 msr->data = efer & ~EFER_LME;
3009 }
3010 setup_msrs(vmx);
3011}
3012
05b3e0c2 3013#ifdef CONFIG_X86_64
6aa8b732
AK		 3014
3015static void enter_lmode(struct kvm_vcpu *vcpu)
3016{
3017 u32 guest_tr_ar;
3018
2fb92db1
AK		 3019 vmx_segment_cache_clear(to_vmx(vcpu));
3020
6aa8b732
AK		 3021 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3022 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 3023 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3024 __func__);
6aa8b732
AK		 3025 vmcs_write32(GUEST_TR_AR_BYTES,
3026 (guest_tr_ar & ~AR_TYPE_MASK)
3027 | AR_TYPE_BUSY_64_TSS);
3028 }
da38f438 3029 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 3030}
3031
3032static void exit_lmode(struct kvm_vcpu *vcpu)
3033{
6aa8b732
AK		 3034 vmcs_write32(VM_ENTRY_CONTROLS,
3035 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 3036 & ~VM_ENTRY_IA32E_MODE);
da38f438 3037 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 3038}
3039
3040#endif
3041
2384d2b3
SY		 3042static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3043{
b9d762fa 3044 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 3045 if (enable_ept) {
3046 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3047 return;
4e1096d2 3048 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 3049 }
2384d2b3
SY		 3050}
3051
e8467fda
AK		 3052static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3053{
3054 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3055
3056 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3057 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3058}
3059
aff48baa
AK		 3060static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3061{
3062 if (enable_ept && is_paging(vcpu))
3063 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3064 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3065}
3066
25c4c276 3067static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 3068{
fc78f519
AK		 3069 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3070
3071 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3072 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 3073}
3074
1439442c
SY		 3075static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3076{
6de4f3ad
AK		 3077 if (!test_bit(VCPU_EXREG_PDPTR,
3078 (unsigned long *)&vcpu->arch.regs_dirty))
3079 return;
3080
1439442c 3081 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3082 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
3083 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
3084 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
3085 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 3086 }
3087}
3088
8f5d549f
AK		 3089static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3090{
3091 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 3092 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3093 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3094 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3095 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 3096 }
6de4f3ad
AK		 3097
3098 __set_bit(VCPU_EXREG_PDPTR,
3099 (unsigned long *)&vcpu->arch.regs_avail);
3100 __set_bit(VCPU_EXREG_PDPTR,
3101 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 3102}
3103
5e1746d6 3104static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 3105
3106static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3107 unsigned long cr0,
3108 struct kvm_vcpu *vcpu)
3109{
5233dd51
MT		 3110 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3111 vmx_decache_cr3(vcpu);
1439442c
SY		 3112 if (!(cr0 & X86_CR0_PG)) {
3113 /* From paging/starting to nonpaging */
3114 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3115 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 3116 (CPU_BASED_CR3_LOAD_EXITING |
3117 CPU_BASED_CR3_STORE_EXITING));
3118 vcpu->arch.cr0 = cr0;
fc78f519 3119 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 3120 } else if (!is_paging(vcpu)) {
3121 /* From nonpaging to paging */
3122 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 3123 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 3124 ~(CPU_BASED_CR3_LOAD_EXITING |
3125 CPU_BASED_CR3_STORE_EXITING));
3126 vcpu->arch.cr0 = cr0;
fc78f519 3127 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 3128 }
95eb84a7
SY		 3129
3130 if (!(cr0 & X86_CR0_WP))
3131 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 3132}
3133
6aa8b732
AK		 3134static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3135{
7ffd92c5 3136 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 3137 unsigned long hw_cr0;
3138
5037878e 3139 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3a624e29 3140 if (enable_unrestricted_guest)
5037878e 3141 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 3142 else {
5037878e 3143 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 3144
218e763f
GN		 3145 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3146 enter_pmode(vcpu);
6aa8b732 3147
218e763f
GN		 3148 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3149 enter_rmode(vcpu);
3150 }
6aa8b732 3151
05b3e0c2 3152#ifdef CONFIG_X86_64
f6801dff 3153 if (vcpu->arch.efer & EFER_LME) {
707d92fa 3154 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 3155 enter_lmode(vcpu);
707d92fa 3156 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 3157 exit_lmode(vcpu);
3158 }
3159#endif
3160
089d034e 3161 if (enable_ept)
1439442c
SY		 3162 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3163
02daab21 3164 if (!vcpu->fpu_active)
81231c69 3165 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 3166
6aa8b732 3167 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 3168 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 3169 vcpu->arch.cr0 = cr0;
14168786
GN		 3170
3171 /* depends on vcpu->arch.cr0 to be set to a new value */
3172 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 3173}
3174
1439442c
SY		 3175static u64 construct_eptp(unsigned long root_hpa)
3176{
3177 u64 eptp;
3178
3179 /* TODO write the value reading from MSR */
3180 eptp = VMX_EPT_DEFAULT_MT |
3181 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
b38f9934
XH		 3182 if (enable_ept_ad_bits)
3183 eptp |= VMX_EPT_AD_ENABLE_BIT;
1439442c
SY		 3184 eptp |= (root_hpa & PAGE_MASK);
3185
3186 return eptp;
3187}
3188
6aa8b732
AK		 3189static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3190{
1439442c
SY		 3191 unsigned long guest_cr3;
3192 u64 eptp;
3193
3194 guest_cr3 = cr3;
089d034e 3195 if (enable_ept) {
1439442c
SY		 3196 eptp = construct_eptp(cr3);
3197 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 3198 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 3199 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 3200 ept_load_pdptrs(vcpu);
1439442c
SY		 3201 }
3202
2384d2b3 3203 vmx_flush_tlb(vcpu);
1439442c 3204 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 3205}
3206
5e1746d6 3207static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 3208{
7ffd92c5 3209 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 3210 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3211
5e1746d6
NHE		 3212 if (cr4 & X86_CR4_VMXE) {
3213 /*
3214 * To use VMXON (and later other VMX instructions), a guest
3215 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3216 * So basically the check on whether to allow nested VMX
3217 * is here.
3218 */
3219 if (!nested_vmx_allowed(vcpu))
3220 return 1;
1a0d74e6
JK		 3221 }
3222 if (to_vmx(vcpu)->nested.vmxon &&
3223 ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
5e1746d6
NHE		 3224 return 1;
3225
ad312c7c 3226 vcpu->arch.cr4 = cr4;
bc23008b
AK		 3227 if (enable_ept) {
3228 if (!is_paging(vcpu)) {
3229 hw_cr4 &= ~X86_CR4_PAE;
3230 hw_cr4 |= X86_CR4_PSE;
c08800a5
DX		 3231 /*
3232 * SMEP is disabled if CPU is in non-paging mode in
3233 * hardware. However KVM always uses paging mode to
3234 * emulate guest non-paging mode with TDP.
3235 * To emulate this behavior, SMEP needs to be manually
3236 * disabled when guest switches to non-paging mode.
3237 */
3238 hw_cr4 &= ~X86_CR4_SMEP;
bc23008b
AK		 3239 } else if (!(cr4 & X86_CR4_PAE)) {
3240 hw_cr4 &= ~X86_CR4_PAE;
3241 }
3242 }
1439442c
SY		 3243
3244 vmcs_writel(CR4_READ_SHADOW, cr4);
3245 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 3246 return 0;
6aa8b732
AK		 3247}
3248
6aa8b732
AK		 3249static void vmx_get_segment(struct kvm_vcpu *vcpu,
3250 struct kvm_segment *var, int seg)
3251{
a9179499 3252 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 3253 u32 ar;
3254
c6ad1153 3255 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 3256 *var = vmx->rmode.segs[seg];
a9179499 3257 if (seg == VCPU_SREG_TR
2fb92db1 3258 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 3259 return;
1390a28b
AK		 3260 var->base = vmx_read_guest_seg_base(vmx, seg);
3261 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3262 return;
a9179499 3263 }
2fb92db1
AK		 3264 var->base = vmx_read_guest_seg_base(vmx, seg);
3265 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3266 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3267 ar = vmx_read_guest_seg_ar(vmx, seg);
6aa8b732
AK		 3268 var->type = ar & 15;
3269 var->s = (ar >> 4) & 1;
3270 var->dpl = (ar >> 5) & 3;
3271 var->present = (ar >> 7) & 1;
3272 var->avl = (ar >> 12) & 1;
3273 var->l = (ar >> 13) & 1;
3274 var->db = (ar >> 14) & 1;
3275 var->g = (ar >> 15) & 1;
3276 var->unusable = (ar >> 16) & 1;
3277}
3278
a9179499
AK		 3279static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3280{
a9179499
AK		 3281 struct kvm_segment s;
3282
3283 if (to_vmx(vcpu)->rmode.vm86_active) {
3284 vmx_get_segment(vcpu, &s, seg);
3285 return s.base;
3286 }
2fb92db1 3287 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3288}
3289
b09408d0 3290static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3291{
b09408d0
MT		 3292 struct vcpu_vmx *vmx = to_vmx(vcpu);
3293
3eeb3288 3294 if (!is_protmode(vcpu))
2e4d2653
IE		 3295 return 0;
3296
f4c63e5d
AK		 3297 if (!is_long_mode(vcpu)
3298 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3299 return 3;
3300
69c73028
AK		 3301 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3302 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
b09408d0 3303 vmx->cpl = vmx_read_guest_seg_selector(vmx, VCPU_SREG_CS) & 3;
69c73028 3304 }
d881e6f6
AK		 3305
3306 return vmx->cpl;
69c73028
AK		 3307}
3308
3309
653e3108 3310static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3311{
6aa8b732
AK		 3312 u32 ar;
3313
f0495f9b 3314 if (var->unusable || !var->present)
6aa8b732
AK		 3315 ar = 1 << 16;
3316 else {
3317 ar = var->type & 15;
3318 ar |= (var->s & 1) << 4;
3319 ar |= (var->dpl & 3) << 5;
3320 ar |= (var->present & 1) << 7;
3321 ar |= (var->avl & 1) << 12;
3322 ar |= (var->l & 1) << 13;
3323 ar |= (var->db & 1) << 14;
3324 ar |= (var->g & 1) << 15;
3325 }
653e3108
AK		 3326
3327 return ar;
3328}
3329
3330static void vmx_set_segment(struct kvm_vcpu *vcpu,
3331 struct kvm_segment *var, int seg)
3332{
7ffd92c5 3333 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 3334 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 3335
2fb92db1 3336 vmx_segment_cache_clear(vmx);
2f143240
GN		 3337 if (seg == VCPU_SREG_CS)
3338 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2fb92db1 3339
1ecd50a9
GN		 3340 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3341 vmx->rmode.segs[seg] = *var;
3342 if (seg == VCPU_SREG_TR)
3343 vmcs_write16(sf->selector, var->selector);
3344 else if (var->s)
3345 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 3346 goto out;
653e3108 3347 }
1ecd50a9 3348
653e3108
AK		 3349 vmcs_writel(sf->base, var->base);
3350 vmcs_write32(sf->limit, var->limit);
3351 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 3352
3353 /*
3354 * Fix the "Accessed" bit in AR field of segment registers for older
3355 * qemu binaries.
3356 * IA32 arch specifies that at the time of processor reset the
3357 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 3358 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 3359 * state vmexit when "unrestricted guest" mode is turned on.
3360 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3361 * tree. Newer qemu binaries with that qemu fix would not need this
3362 * kvm hack.
3363 */
3364 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 3365 var->type |= 0x1; /* Accessed */
3a624e29 3366
f924d66d 3367 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 3368
3369out:
14168786 3370 vmx->emulation_required |= emulation_required(vcpu);
6aa8b732
AK		 3371}
3372
6aa8b732
AK		 3373static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3374{
2fb92db1 3375 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3376
3377 *db = (ar >> 14) & 1;
3378 *l = (ar >> 13) & 1;
3379}
3380
89a27f4d 3381static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3382{
89a27f4d
GN		 3383 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3384 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3385}
3386
89a27f4d 3387static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3388{
89a27f4d
GN		 3389 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3390 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3391}
3392
89a27f4d 3393static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3394{
89a27f4d
GN		 3395 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3396 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3397}
3398
89a27f4d 3399static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3400{
89a27f4d
GN		 3401 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3402 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3403}
3404
648dfaa7
MG		 3405static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3406{
3407 struct kvm_segment var;
3408 u32 ar;
3409
3410 vmx_get_segment(vcpu, &var, seg);
07f42f5f 3411 var.dpl = 0x3;
0647f4aa
GN		 3412 if (seg == VCPU_SREG_CS)
3413 var.type = 0x3;
648dfaa7
MG		 3414 ar = vmx_segment_access_rights(&var);
3415
3416 if (var.base != (var.selector << 4))
3417 return false;
89efbed0 3418 if (var.limit != 0xffff)
648dfaa7 3419 return false;
07f42f5f 3420 if (ar != 0xf3)
648dfaa7
MG		 3421 return false;
3422
3423 return true;
3424}
3425
3426static bool code_segment_valid(struct kvm_vcpu *vcpu)
3427{
3428 struct kvm_segment cs;
3429 unsigned int cs_rpl;
3430
3431 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3432 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3433
1872a3f4
AK		 3434 if (cs.unusable)
3435 return false;
648dfaa7
MG		 3436 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3437 return false;
3438 if (!cs.s)
3439 return false;
1872a3f4 3440 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3441 if (cs.dpl > cs_rpl)
3442 return false;
1872a3f4 3443 } else {
648dfaa7
MG		 3444 if (cs.dpl != cs_rpl)
3445 return false;
3446 }
3447 if (!cs.present)
3448 return false;
3449
3450 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3451 return true;
3452}
3453
3454static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3455{
3456 struct kvm_segment ss;
3457 unsigned int ss_rpl;
3458
3459 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3460 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3461
1872a3f4
AK		 3462 if (ss.unusable)
3463 return true;
3464 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3465 return false;
3466 if (!ss.s)
3467 return false;
3468 if (ss.dpl != ss_rpl) /* DPL != RPL */
3469 return false;
3470 if (!ss.present)
3471 return false;
3472
3473 return true;
3474}
3475
3476static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3477{
3478 struct kvm_segment var;
3479 unsigned int rpl;
3480
3481 vmx_get_segment(vcpu, &var, seg);
3482 rpl = var.selector & SELECTOR_RPL_MASK;
3483
1872a3f4
AK		 3484 if (var.unusable)
3485 return true;
648dfaa7
MG		 3486 if (!var.s)
3487 return false;
3488 if (!var.present)
3489 return false;
3490 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3491 if (var.dpl < rpl) /* DPL < RPL */
3492 return false;
3493 }
3494
3495 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3496 * rights flags
3497 */
3498 return true;
3499}
3500
3501static bool tr_valid(struct kvm_vcpu *vcpu)
3502{
3503 struct kvm_segment tr;
3504
3505 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3506
1872a3f4
AK		 3507 if (tr.unusable)
3508 return false;
648dfaa7
MG		 3509 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3510 return false;
1872a3f4 3511 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3512 return false;
3513 if (!tr.present)
3514 return false;
3515
3516 return true;
3517}
3518
3519static bool ldtr_valid(struct kvm_vcpu *vcpu)
3520{
3521 struct kvm_segment ldtr;
3522
3523 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3524
1872a3f4
AK		 3525 if (ldtr.unusable)
3526 return true;
648dfaa7
MG		 3527 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3528 return false;
3529 if (ldtr.type != 2)
3530 return false;
3531 if (!ldtr.present)
3532 return false;
3533
3534 return true;
3535}
3536
3537static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3538{
3539 struct kvm_segment cs, ss;
3540
3541 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3542 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3543
3544 return ((cs.selector & SELECTOR_RPL_MASK) ==
3545 (ss.selector & SELECTOR_RPL_MASK));
3546}
3547
3548/*
3549 * Check if guest state is valid. Returns true if valid, false if
3550 * not.
3551 * We assume that registers are always usable
3552 */
3553static bool guest_state_valid(struct kvm_vcpu *vcpu)
3554{
c5e97c80
GN		 3555 if (enable_unrestricted_guest)
3556 return true;
3557
648dfaa7 3558 /* real mode guest state checks */
3eeb3288 3559 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3560 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3561 return false;
3562 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3563 return false;
3564 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3565 return false;
3566 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3567 return false;
3568 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3569 return false;
3570 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3571 return false;
3572 } else {
3573 /* protected mode guest state checks */
3574 if (!cs_ss_rpl_check(vcpu))
3575 return false;
3576 if (!code_segment_valid(vcpu))
3577 return false;
3578 if (!stack_segment_valid(vcpu))
3579 return false;
3580 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3581 return false;
3582 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3583 return false;
3584 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3585 return false;
3586 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3587 return false;
3588 if (!tr_valid(vcpu))
3589 return false;
3590 if (!ldtr_valid(vcpu))
3591 return false;
3592 }
3593 /* TODO:
3594 * - Add checks on RIP
3595 * - Add checks on RFLAGS
3596 */
3597
3598 return true;
3599}
3600
d77c26fc 3601static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3602{
40dcaa9f 3603 gfn_t fn;
195aefde 3604 u16 data = 0;
40dcaa9f 3605 int r, idx, ret = 0;
6aa8b732 3606
40dcaa9f 3607 idx = srcu_read_lock(&kvm->srcu);
4918c6ca 3608 fn = kvm->arch.tss_addr >> PAGE_SHIFT;
195aefde
IE		 3609 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3610 if (r < 0)
10589a46 3611 goto out;
195aefde 3612 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3613 r = kvm_write_guest_page(kvm, fn++, &data,
3614 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3615 if (r < 0)
10589a46 3616 goto out;
195aefde
IE		 3617 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3618 if (r < 0)
10589a46 3619 goto out;
195aefde
IE		 3620 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3621 if (r < 0)
10589a46 3622 goto out;
195aefde 3623 data = ~0;
10589a46
MT		 3624 r = kvm_write_guest_page(kvm, fn, &data,
3625 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3626 sizeof(u8));
195aefde 3627 if (r < 0)
10589a46
MT		 3628 goto out;
3629
3630 ret = 1;
3631out:
40dcaa9f 3632 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3633 return ret;
6aa8b732
AK		 3634}
3635
b7ebfb05
SY		 3636static int init_rmode_identity_map(struct kvm *kvm)
3637{
40dcaa9f 3638 int i, idx, r, ret;
b7ebfb05
SY		 3639 pfn_t identity_map_pfn;
3640 u32 tmp;
3641
089d034e 3642 if (!enable_ept)
b7ebfb05
SY		 3643 return 1;
3644 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3645 printk(KERN_ERR "EPT: identity-mapping pagetable "
3646 "haven't been allocated!\n");
3647 return 0;
3648 }
3649 if (likely(kvm->arch.ept_identity_pagetable_done))
3650 return 1;
3651 ret = 0;
b927a3ce 3652 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3653 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3654 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3655 if (r < 0)
3656 goto out;
3657 /* Set up identity-mapping pagetable for EPT in real mode */
3658 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3659 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3660 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3661 r = kvm_write_guest_page(kvm, identity_map_pfn,
3662 &tmp, i * sizeof(tmp), sizeof(tmp));
3663 if (r < 0)
3664 goto out;
3665 }
3666 kvm->arch.ept_identity_pagetable_done = true;
3667 ret = 1;
3668out:
40dcaa9f 3669 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3670 return ret;
3671}
3672
6aa8b732
AK		 3673static void seg_setup(int seg)
3674{
772e0318 3675 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3676 unsigned int ar;
6aa8b732
AK		 3677
3678 vmcs_write16(sf->selector, 0);
3679 vmcs_writel(sf->base, 0);
3680 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3681 ar = 0x93;
3682 if (seg == VCPU_SREG_CS)
3683 ar |= 0x08; /* code segment */
3a624e29
NK		 3684
3685 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3686}
3687
f78e0e2e
SY		 3688static int alloc_apic_access_page(struct kvm *kvm)
3689{
4484141a 3690 struct page *page;
f78e0e2e
SY		 3691 struct kvm_userspace_memory_region kvm_userspace_mem;
3692 int r = 0;
3693
79fac95e 3694 mutex_lock(&kvm->slots_lock);
bfc6d222 3695 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3696 goto out;
3697 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3698 kvm_userspace_mem.flags = 0;
3699 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3700 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3701 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
f78e0e2e
SY		 3702 if (r)
3703 goto out;
72dc67a6 3704
4484141a
XG		 3705 page = gfn_to_page(kvm, 0xfee00);
3706 if (is_error_page(page)) {
3707 r = -EFAULT;
3708 goto out;
3709 }
3710
3711 kvm->arch.apic_access_page = page;
f78e0e2e 3712out:
79fac95e 3713 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3714 return r;
3715}
3716
b7ebfb05
SY		 3717static int alloc_identity_pagetable(struct kvm *kvm)
3718{
4484141a 3719 struct page *page;
b7ebfb05
SY		 3720 struct kvm_userspace_memory_region kvm_userspace_mem;
3721 int r = 0;
3722
79fac95e 3723 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3724 if (kvm->arch.ept_identity_pagetable)
3725 goto out;
3726 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3727 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3728 kvm_userspace_mem.guest_phys_addr =
3729 kvm->arch.ept_identity_map_addr;
b7ebfb05 3730 kvm_userspace_mem.memory_size = PAGE_SIZE;
47ae31e2 3731 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem);
b7ebfb05
SY		 3732 if (r)
3733 goto out;
3734
4484141a
XG		 3735 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3736 if (is_error_page(page)) {
3737 r = -EFAULT;
3738 goto out;
3739 }
3740
3741 kvm->arch.ept_identity_pagetable = page;
b7ebfb05 3742out:
79fac95e 3743 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3744 return r;
3745}
3746
2384d2b3
SY		 3747static void allocate_vpid(struct vcpu_vmx *vmx)
3748{
3749 int vpid;
3750
3751 vmx->vpid = 0;
919818ab 3752 if (!enable_vpid)
2384d2b3
SY		 3753 return;
3754 spin_lock(&vmx_vpid_lock);
3755 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3756 if (vpid < VMX_NR_VPIDS) {
3757 vmx->vpid = vpid;
3758 __set_bit(vpid, vmx_vpid_bitmap);
3759 }
3760 spin_unlock(&vmx_vpid_lock);
3761}
3762
cdbecfc3
LJ		 3763static void free_vpid(struct vcpu_vmx *vmx)
3764{
3765 if (!enable_vpid)
3766 return;
3767 spin_lock(&vmx_vpid_lock);
3768 if (vmx->vpid != 0)
3769 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3770 spin_unlock(&vmx_vpid_lock);
3771}
3772
8d14695f
YZ		 3773#define MSR_TYPE_R 1
3774#define MSR_TYPE_W 2
3775static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
3776 u32 msr, int type)
25c5f225 3777{
3e7c73e9 3778 int f = sizeof(unsigned long);
25c5f225
SY		 3779
3780 if (!cpu_has_vmx_msr_bitmap())
3781 return;
3782
3783 /*
3784 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3785 * have the write-low and read-high bitmap offsets the wrong way round.
3786 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3787 */
25c5f225 3788 if (msr <= 0x1fff) {
8d14695f
YZ		 3789 if (type & MSR_TYPE_R)
3790 /* read-low */
3791 __clear_bit(msr, msr_bitmap + 0x000 / f);
3792
3793 if (type & MSR_TYPE_W)
3794 /* write-low */
3795 __clear_bit(msr, msr_bitmap + 0x800 / f);
3796
25c5f225
SY		 3797 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3798 msr &= 0x1fff;
8d14695f
YZ		 3799 if (type & MSR_TYPE_R)
3800 /* read-high */
3801 __clear_bit(msr, msr_bitmap + 0x400 / f);
3802
3803 if (type & MSR_TYPE_W)
3804 /* write-high */
3805 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3806
3807 }
3808}
3809
3810static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
3811 u32 msr, int type)
3812{
3813 int f = sizeof(unsigned long);
3814
3815 if (!cpu_has_vmx_msr_bitmap())
3816 return;
3817
3818 /*
3819 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3820 * have the write-low and read-high bitmap offsets the wrong way round.
3821 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3822 */
3823 if (msr <= 0x1fff) {
3824 if (type & MSR_TYPE_R)
3825 /* read-low */
3826 __set_bit(msr, msr_bitmap + 0x000 / f);
3827
3828 if (type & MSR_TYPE_W)
3829 /* write-low */
3830 __set_bit(msr, msr_bitmap + 0x800 / f);
3831
3832 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3833 msr &= 0x1fff;
3834 if (type & MSR_TYPE_R)
3835 /* read-high */
3836 __set_bit(msr, msr_bitmap + 0x400 / f);
3837
3838 if (type & MSR_TYPE_W)
3839 /* write-high */
3840 __set_bit(msr, msr_bitmap + 0xc00 / f);
3841
25c5f225 3842 }
25c5f225
SY		 3843}
3844
5897297b
AK		 3845static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3846{
3847 if (!longmode_only)
8d14695f
YZ		 3848 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
3849 msr, MSR_TYPE_R | MSR_TYPE_W);
3850 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
3851 msr, MSR_TYPE_R | MSR_TYPE_W);
3852}
3853
3854static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
3855{
3856 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3857 msr, MSR_TYPE_R);
3858 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3859 msr, MSR_TYPE_R);
3860}
3861
3862static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
3863{
3864 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3865 msr, MSR_TYPE_R);
3866 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3867 msr, MSR_TYPE_R);
3868}
3869
3870static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
3871{
3872 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
3873 msr, MSR_TYPE_W);
3874 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
3875 msr, MSR_TYPE_W);
5897297b
AK		 3876}
3877
a3a8ff8e
NHE		 3878/*
3879 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3880 * will not change in the lifetime of the guest.
3881 * Note that host-state that does change is set elsewhere. E.g., host-state
3882 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3883 */
a547c6db 3884static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3885{
3886 u32 low32, high32;
3887 unsigned long tmpl;
3888 struct desc_ptr dt;
3889
b1a74bf8 3890 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
a3a8ff8e
NHE		 3891 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3892 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3893
3894 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3895#ifdef CONFIG_X86_64
3896 /*
3897 * Load null selectors, so we can avoid reloading them in
3898 * __vmx_load_host_state(), in case userspace uses the null selectors
3899 * too (the expected case).
3900 */
3901 vmcs_write16(HOST_DS_SELECTOR, 0);
3902 vmcs_write16(HOST_ES_SELECTOR, 0);
3903#else
a3a8ff8e
NHE		 3904 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3905 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3906#endif
a3a8ff8e
NHE		 3907 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3908 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3909
3910 native_store_idt(&dt);
3911 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 3912 vmx->host_idt_base = dt.address;
a3a8ff8e 3913
83287ea4 3914 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3915
3916 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3917 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3918 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3919 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3920
3921 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3922 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3923 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3924 }
3925}
3926
bf8179a0
NHE		 3927static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3928{
3929 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3930 if (enable_ept)
3931 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3932 if (is_guest_mode(&vmx->vcpu))
3933 vmx->vcpu.arch.cr4_guest_owned_bits &=
3934 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3935 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3936}
3937
3938static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3939{
3940 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3941 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3942 exec_control &= ~CPU_BASED_TPR_SHADOW;
3943#ifdef CONFIG_X86_64
3944 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3945 CPU_BASED_CR8_LOAD_EXITING;
3946#endif
3947 }
3948 if (!enable_ept)
3949 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3950 CPU_BASED_CR3_LOAD_EXITING |
3951 CPU_BASED_INVLPG_EXITING;
3952 return exec_control;
3953}
3954
c7c9c56c
YZ		 3955static int vmx_vm_has_apicv(struct kvm *kvm)
3956{
3957 return enable_apicv_reg_vid && irqchip_in_kernel(kvm);
3958}
3959
bf8179a0
NHE		 3960static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3961{
3962 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3963 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3964 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3965 if (vmx->vpid == 0)
3966 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3967 if (!enable_ept) {
3968 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3969 enable_unrestricted_guest = 0;
ad756a16
MJ		 3970 /* Enable INVPCID for non-ept guests may cause performance regression. */
3971 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
bf8179a0
NHE		 3972 }
3973 if (!enable_unrestricted_guest)
3974 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3975 if (!ple_gap)
3976 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
c7c9c56c
YZ		 3977 if (!vmx_vm_has_apicv(vmx->vcpu.kvm))
3978 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3979 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 3980 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
bf8179a0
NHE		 3981 return exec_control;
3982}
3983
ce88decf
XG		 3984static void ept_set_mmio_spte_mask(void)
3985{
3986 /*
3987 * EPT Misconfigurations can be generated if the value of bits 2:0
3988 * of an EPT paging-structure entry is 110b (write/execute).
3989 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3990 * spte.
3991 */
3992 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3993}
3994
6aa8b732
AK		 3995/*
3996 * Sets up the vmcs for emulated real mode.
3997 */
8b9cf98c 3998static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3999{
2e4ce7f5 4000#ifdef CONFIG_X86_64
6aa8b732 4001 unsigned long a;
2e4ce7f5 4002#endif
6aa8b732 4003 int i;
6aa8b732 4004
6aa8b732 4005 /* I/O */
3e7c73e9
AK		 4006 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4007 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 4008
25c5f225 4009 if (cpu_has_vmx_msr_bitmap())
5897297b 4010 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 4011
6aa8b732
AK		 4012 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4013
6aa8b732 4014 /* Control */
1c3d14fe
YS		 4015 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
4016 vmcs_config.pin_based_exec_ctrl);
6e5d865c 4017
bf8179a0 4018 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 4019
83ff3b9d 4020 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 4021 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4022 vmx_secondary_exec_control(vmx));
83ff3b9d 4023 }
f78e0e2e 4024
c7c9c56c
YZ		 4025 if (enable_apicv_reg_vid) {
4026 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4027 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4028 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4029 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4030
4031 vmcs_write16(GUEST_INTR_STATUS, 0);
4032 }
4033
4b8d54f9
ZE		 4034 if (ple_gap) {
4035 vmcs_write32(PLE_GAP, ple_gap);
4036 vmcs_write32(PLE_WINDOW, ple_window);
4037 }
4038
c3707958
XG		 4039 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4040 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 4041 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
4042
9581d442
AK		 4043 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
4044 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 4045 vmx_set_constant_host_state(vmx);
05b3e0c2 4046#ifdef CONFIG_X86_64
6aa8b732
AK		 4047 rdmsrl(MSR_FS_BASE, a);
4048 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4049 rdmsrl(MSR_GS_BASE, a);
4050 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4051#else
4052 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4053 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4054#endif
4055
2cc51560
ED		 4056 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4057 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 4058 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 4059 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 4060 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 4061
468d472f 4062 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 4063 u32 msr_low, msr_high;
4064 u64 host_pat;
468d472f
SY		 4065 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
4066 host_pat = msr_low | ((u64) msr_high << 32);
4067 /* Write the default value follow host pat */
4068 vmcs_write64(GUEST_IA32_PAT, host_pat);
4069 /* Keep arch.pat sync with GUEST_IA32_PAT */
4070 vmx->vcpu.arch.pat = host_pat;
4071 }
4072
6aa8b732
AK		 4073 for (i = 0; i < NR_VMX_MSR; ++i) {
4074 u32 index = vmx_msr_index[i];
4075 u32 data_low, data_high;
a2fa3e9f 4076 int j = vmx->nmsrs;
6aa8b732
AK		 4077
4078 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4079 continue;
432bd6cb
AK		 4080 if (wrmsr_safe(index, data_low, data_high) < 0)
4081 continue;
26bb0981
AK		 4082 vmx->guest_msrs[j].index = i;
4083 vmx->guest_msrs[j].data = 0;
d5696725 4084 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 4085 ++vmx->nmsrs;
6aa8b732 4086 }
6aa8b732 4087
1c3d14fe 4088 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 4089
4090 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 4091 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
4092
e00c8cf2 4093 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 4094 set_cr4_guest_host_mask(vmx);
e00c8cf2
AK		 4095
4096 return 0;
4097}
4098
57f252f2 4099static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
e00c8cf2
AK		 4100{
4101 struct vcpu_vmx *vmx = to_vmx(vcpu);
4102 u64 msr;
e00c8cf2 4103
7ffd92c5 4104 vmx->rmode.vm86_active = 0;
e00c8cf2 4105
3b86cd99
JK		 4106 vmx->soft_vnmi_blocked = 0;
4107
ad312c7c 4108 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 4109 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 4110 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 4111 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 4112 msr |= MSR_IA32_APICBASE_BSP;
4113 kvm_set_apic_base(&vmx->vcpu, msr);
4114
2fb92db1
AK		 4115 vmx_segment_cache_clear(vmx);
4116
5706be0d 4117 seg_setup(VCPU_SREG_CS);
66450a21 4118 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
04b66839 4119 vmcs_write32(GUEST_CS_BASE, 0xffff0000);
e00c8cf2
AK		 4120
4121 seg_setup(VCPU_SREG_DS);
4122 seg_setup(VCPU_SREG_ES);
4123 seg_setup(VCPU_SREG_FS);
4124 seg_setup(VCPU_SREG_GS);
4125 seg_setup(VCPU_SREG_SS);
4126
4127 vmcs_write16(GUEST_TR_SELECTOR, 0);
4128 vmcs_writel(GUEST_TR_BASE, 0);
4129 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4130 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4131
4132 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4133 vmcs_writel(GUEST_LDTR_BASE, 0);
4134 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4135 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4136
4137 vmcs_write32(GUEST_SYSENTER_CS, 0);
4138 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4139 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4140
4141 vmcs_writel(GUEST_RFLAGS, 0x02);
66450a21 4142 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 4143
e00c8cf2
AK		 4144 vmcs_writel(GUEST_GDTR_BASE, 0);
4145 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4146
4147 vmcs_writel(GUEST_IDTR_BASE, 0);
4148 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4149
443381a8 4150 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 4151 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4152 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4153
e00c8cf2
AK		 4154 /* Special registers */
4155 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4156
4157 setup_msrs(vmx);
4158
6aa8b732
AK		 4159 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4160
f78e0e2e
SY		 4161 if (cpu_has_vmx_tpr_shadow()) {
4162 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4163 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4164 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 4165 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 4166 vmcs_write32(TPR_THRESHOLD, 0);
4167 }
4168
4169 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4170 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 4171 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 4172
2384d2b3
SY		 4173 if (vmx->vpid != 0)
4174 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4175
fa40052c 4176 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 4177 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 4178 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 4179 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 4180 vmx_fpu_activate(&vmx->vcpu);
4181 update_exception_bitmap(&vmx->vcpu);
6aa8b732 4182
b9d762fa 4183 vpid_sync_context(vmx);
6aa8b732
AK		 4184}
4185
b6f1250e
NHE		 4186/*
4187 * In nested virtualization, check if L1 asked to exit on external interrupts.
4188 * For most existing hypervisors, this will always return true.
4189 */
4190static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4191{
4192 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4193 PIN_BASED_EXT_INTR_MASK;
4194}
4195
3b86cd99
JK		 4196static void enable_irq_window(struct kvm_vcpu *vcpu)
4197{
4198 u32 cpu_based_vm_exec_control;
d6185f20
NHE		 4199 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4200 /*
4201 * We get here if vmx_interrupt_allowed() said we can't
4202 * inject to L1 now because L2 must run. Ask L2 to exit
4203 * right after entry, so we can inject to L1 more promptly.
b6f1250e 4204 */
d6185f20 4205 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
b6f1250e 4206 return;
d6185f20 4207 }
3b86cd99
JK		 4208
4209 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4210 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4211 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4212}
4213
4214static void enable_nmi_window(struct kvm_vcpu *vcpu)
4215{
4216 u32 cpu_based_vm_exec_control;
4217
4218 if (!cpu_has_virtual_nmis()) {
4219 enable_irq_window(vcpu);
4220 return;
4221 }
4222
30bd0c4c
AK		 4223 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4224 enable_irq_window(vcpu);
4225 return;
4226 }
3b86cd99
JK		 4227 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4228 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4229 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4230}
4231
66fd3f7f 4232static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 4233{
9c8cba37 4234 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 4235 uint32_t intr;
4236 int irq = vcpu->arch.interrupt.nr;
9c8cba37 4237
229456fc 4238 trace_kvm_inj_virq(irq);
2714d1d3 4239
fa89a817 4240 ++vcpu->stat.irq_injections;
7ffd92c5 4241 if (vmx->rmode.vm86_active) {
71f9833b
SH		 4242 int inc_eip = 0;
4243 if (vcpu->arch.interrupt.soft)
4244 inc_eip = vcpu->arch.event_exit_inst_len;
4245 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 4246 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 4247 return;
4248 }
66fd3f7f
GN		 4249 intr = irq | INTR_INFO_VALID_MASK;
4250 if (vcpu->arch.interrupt.soft) {
4251 intr |= INTR_TYPE_SOFT_INTR;
4252 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4253 vmx->vcpu.arch.event_exit_inst_len);
4254 } else
4255 intr |= INTR_TYPE_EXT_INTR;
4256 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 4257}
4258
f08864b4
SY		 4259static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4260{
66a5a347
JK		 4261 struct vcpu_vmx *vmx = to_vmx(vcpu);
4262
0b6ac343
NHE		 4263 if (is_guest_mode(vcpu))
4264 return;
4265
3b86cd99
JK		 4266 if (!cpu_has_virtual_nmis()) {
4267 /*
4268 * Tracking the NMI-blocked state in software is built upon
4269 * finding the next open IRQ window. This, in turn, depends on
4270 * well-behaving guests: They have to keep IRQs disabled at
4271 * least as long as the NMI handler runs. Otherwise we may
4272 * cause NMI nesting, maybe breaking the guest. But as this is
4273 * highly unlikely, we can live with the residual risk.
4274 */
4275 vmx->soft_vnmi_blocked = 1;
4276 vmx->vnmi_blocked_time = 0;
4277 }
4278
487b391d 4279 ++vcpu->stat.nmi_injections;
9d58b931 4280 vmx->nmi_known_unmasked = false;
7ffd92c5 4281 if (vmx->rmode.vm86_active) {
71f9833b 4282 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 4283 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 4284 return;
4285 }
f08864b4
SY		 4286 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4287 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 4288}
4289
c4282df9 4290static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 4291{
3b86cd99 4292 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 4293 return 0;
33f089ca 4294
c4282df9 4295 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 4296 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4297 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 4298}
4299
3cfc3092
JK		 4300static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4301{
4302 if (!cpu_has_virtual_nmis())
4303 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 4304 if (to_vmx(vcpu)->nmi_known_unmasked)
4305 return false;
c332c83a 4306 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 4307}
4308
4309static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4310{
4311 struct vcpu_vmx *vmx = to_vmx(vcpu);
4312
4313 if (!cpu_has_virtual_nmis()) {
4314 if (vmx->soft_vnmi_blocked != masked) {
4315 vmx->soft_vnmi_blocked = masked;
4316 vmx->vnmi_blocked_time = 0;
4317 }
4318 } else {
9d58b931 4319 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 4320 if (masked)
4321 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4322 GUEST_INTR_STATE_NMI);
4323 else
4324 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4325 GUEST_INTR_STATE_NMI);
4326 }
4327}
4328
78646121
GN		 4329static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4330{
e8457c67 4331 if (is_guest_mode(vcpu)) {
51cfe38e 4332 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
e8457c67
JK		 4333
4334 if (to_vmx(vcpu)->nested.nested_run_pending)
b6f1250e 4335 return 0;
e8457c67
JK		 4336 if (nested_exit_on_intr(vcpu)) {
4337 nested_vmx_vmexit(vcpu);
4338 vmcs12->vm_exit_reason =
4339 EXIT_REASON_EXTERNAL_INTERRUPT;
4340 vmcs12->vm_exit_intr_info = 0;
4341 /*
4342 * fall through to normal code, but now in L1, not L2
4343 */
4344 }
b6f1250e
NHE		 4345 }
4346
c4282df9
GN		 4347 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4348 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4349 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4350}
4351
cbc94022
IE		 4352static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4353{
4354 int ret;
4355 struct kvm_userspace_memory_region tss_mem = {
6fe63979 4356 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 4357 .guest_phys_addr = addr,
4358 .memory_size = PAGE_SIZE * 3,
4359 .flags = 0,
4360 };
4361
47ae31e2 4362 ret = kvm_set_memory_region(kvm, &tss_mem);
cbc94022
IE		 4363 if (ret)
4364 return ret;
bfc6d222 4365 kvm->arch.tss_addr = addr;
93ea5388
GN		 4366 if (!init_rmode_tss(kvm))
4367 return -ENOMEM;
4368
cbc94022
IE		 4369 return 0;
4370}
4371
0ca1b4f4 4372static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4373{
77ab6db0 4374 switch (vec) {
77ab6db0 4375 case BP_VECTOR:
c573cd22
JK		 4376 /*
4377 * Update instruction length as we may reinject the exception
4378 * from user space while in guest debugging mode.
4379 */
4380 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4381 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4382 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4383 return false;
4384 /* fall through */
4385 case DB_VECTOR:
4386 if (vcpu->guest_debug &
4387 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4388 return false;
d0bfb940
JK		 4389 /* fall through */
4390 case DE_VECTOR:
77ab6db0
JK		 4391 case OF_VECTOR:
4392 case BR_VECTOR:
4393 case UD_VECTOR:
4394 case DF_VECTOR:
4395 case SS_VECTOR:
4396 case GP_VECTOR:
4397 case MF_VECTOR:
0ca1b4f4
GN		 4398 return true;
4399 break;
77ab6db0 4400 }
0ca1b4f4
GN		 4401 return false;
4402}
4403
4404static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4405 int vec, u32 err_code)
4406{
4407 /*
4408 * Instruction with address size override prefix opcode 0x67
4409 * Cause the #SS fault with 0 error code in VM86 mode.
4410 */
4411 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
4412 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
4413 if (vcpu->arch.halt_request) {
4414 vcpu->arch.halt_request = 0;
4415 return kvm_emulate_halt(vcpu);
4416 }
4417 return 1;
4418 }
4419 return 0;
4420 }
4421
4422 /*
4423 * Forward all other exceptions that are valid in real mode.
4424 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4425 * the required debugging infrastructure rework.
4426 */
4427 kvm_queue_exception(vcpu, vec);
4428 return 1;
6aa8b732
AK		 4429}
4430
a0861c02
AK		 4431/*
4432 * Trigger machine check on the host. We assume all the MSRs are already set up
4433 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4434 * We pass a fake environment to the machine check handler because we want
4435 * the guest to be always treated like user space, no matter what context
4436 * it used internally.
4437 */
4438static void kvm_machine_check(void)
4439{
4440#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4441 struct pt_regs regs = {
4442 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4443 .flags = X86_EFLAGS_IF,
4444 };
4445
4446 do_machine_check(&regs, 0);
4447#endif
4448}
4449
851ba692 4450static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4451{
4452 /* already handled by vcpu_run */
4453 return 1;
4454}
4455
851ba692 4456static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4457{
1155f76a 4458 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4459 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4460 u32 intr_info, ex_no, error_code;
42dbaa5a 4461 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4462 u32 vect_info;
4463 enum emulation_result er;
4464
1155f76a 4465 vect_info = vmx->idt_vectoring_info;
88786475 4466 intr_info = vmx->exit_intr_info;
6aa8b732 4467
a0861c02 4468 if (is_machine_check(intr_info))
851ba692 4469 return handle_machine_check(vcpu);
a0861c02 4470
e4a41889 4471 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4472 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4473
4474 if (is_no_device(intr_info)) {
5fd86fcf 4475 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4476 return 1;
4477 }
4478
7aa81cc0 4479 if (is_invalid_opcode(intr_info)) {
51d8b661 4480 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4481 if (er != EMULATE_DONE)
7ee5d940 4482 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4483 return 1;
4484 }
4485
6aa8b732 4486 error_code = 0;
2e11384c 4487 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4488 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e
XG		 4489
4490 /*
4491 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4492 * MMIO, it is better to report an internal error.
4493 * See the comments in vmx_handle_exit.
4494 */
4495 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4496 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4497 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4498 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4499 vcpu->run->internal.ndata = 2;
4500 vcpu->run->internal.data[0] = vect_info;
4501 vcpu->run->internal.data[1] = intr_info;
4502 return 0;
4503 }
4504
6aa8b732 4505 if (is_page_fault(intr_info)) {
1439442c 4506 /* EPT won't cause page fault directly */
cf3ace79 4507 BUG_ON(enable_ept);
6aa8b732 4508 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4509 trace_kvm_page_fault(cr2, error_code);
4510
3298b75c 4511 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4512 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4513 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4514 }
4515
d0bfb940 4516 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4517
4518 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4519 return handle_rmode_exception(vcpu, ex_no, error_code);
4520
42dbaa5a
JK		 4521 switch (ex_no) {
4522 case DB_VECTOR:
4523 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4524 if (!(vcpu->guest_debug &
4525 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4526 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4527 kvm_queue_exception(vcpu, DB_VECTOR);
4528 return 1;
4529 }
4530 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4531 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4532 /* fall through */
4533 case BP_VECTOR:
c573cd22
JK		 4534 /*
4535 * Update instruction length as we may reinject #BP from
4536 * user space while in guest debugging mode. Reading it for
4537 * #DB as well causes no harm, it is not used in that case.
4538 */
4539 vmx->vcpu.arch.event_exit_inst_len =
4540 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4541 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4542 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4543 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4544 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4545 break;
4546 default:
d0bfb940
JK		 4547 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4548 kvm_run->ex.exception = ex_no;
4549 kvm_run->ex.error_code = error_code;
42dbaa5a 4550 break;
6aa8b732 4551 }
6aa8b732
AK		 4552 return 0;
4553}
4554
851ba692 4555static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4556{
1165f5fe 4557 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4558 return 1;
4559}
4560
851ba692 4561static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4562{
851ba692 4563 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4564 return 0;
4565}
6aa8b732 4566
851ba692 4567static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4568{
bfdaab09 4569 unsigned long exit_qualification;
34c33d16 4570 int size, in, string;
039576c0 4571 unsigned port;
6aa8b732 4572
bfdaab09 4573 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4574 string = (exit_qualification & 16) != 0;
cf8f70bf 4575 in = (exit_qualification & 8) != 0;
e70669ab 4576
cf8f70bf 4577 ++vcpu->stat.io_exits;
e70669ab 4578
cf8f70bf 4579 if (string || in)
51d8b661 4580 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4581
cf8f70bf
GN		 4582 port = exit_qualification >> 16;
4583 size = (exit_qualification & 7) + 1;
e93f36bc 4584 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4585
4586 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4587}
4588
102d8325
IM		 4589static void
4590vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4591{
4592 /*
4593 * Patch in the VMCALL instruction:
4594 */
4595 hypercall[0] = 0x0f;
4596 hypercall[1] = 0x01;
4597 hypercall[2] = 0xc1;
102d8325
IM		 4598}
4599
0fa06071 4600/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4601static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4602{
eeadf9e7 4603 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4604 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4605 unsigned long orig_val = val;
4606
eeadf9e7
NHE		 4607 /*
4608 * We get here when L2 changed cr0 in a way that did not change
4609 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4610 * but did change L0 shadowed bits. So we first calculate the
4611 * effective cr0 value that L1 would like to write into the
4612 * hardware. It consists of the L2-owned bits from the new
4613 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4614 */
1a0d74e6
JK		 4615 val = (val & ~vmcs12->cr0_guest_host_mask) |
4616 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4617
4618 /* TODO: will have to take unrestricted guest mode into
4619 * account */
4620 if ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON)
eeadf9e7 4621 return 1;
1a0d74e6
JK		 4622
4623 if (kvm_set_cr0(vcpu, val))
4624 return 1;
4625 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4626 return 0;
1a0d74e6
JK		 4627 } else {
4628 if (to_vmx(vcpu)->nested.vmxon &&
4629 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4630 return 1;
eeadf9e7 4631 return kvm_set_cr0(vcpu, val);
1a0d74e6 4632 }
eeadf9e7
NHE		 4633}
4634
4635static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4636{
4637 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4638 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4639 unsigned long orig_val = val;
4640
4641 /* analogously to handle_set_cr0 */
4642 val = (val & ~vmcs12->cr4_guest_host_mask) |
4643 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4644 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4645 return 1;
1a0d74e6 4646 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4647 return 0;
4648 } else
4649 return kvm_set_cr4(vcpu, val);
4650}
4651
4652/* called to set cr0 as approriate for clts instruction exit. */
4653static void handle_clts(struct kvm_vcpu *vcpu)
4654{
4655 if (is_guest_mode(vcpu)) {
4656 /*
4657 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4658 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4659 * just pretend it's off (also in arch.cr0 for fpu_activate).
4660 */
4661 vmcs_writel(CR0_READ_SHADOW,
4662 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4663 vcpu->arch.cr0 &= ~X86_CR0_TS;
4664 } else
4665 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4666}
4667
851ba692 4668static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4669{
229456fc 4670 unsigned long exit_qualification, val;
6aa8b732
AK		 4671 int cr;
4672 int reg;
49a9b07e 4673 int err;
6aa8b732 4674
bfdaab09 4675 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4676 cr = exit_qualification & 15;
4677 reg = (exit_qualification >> 8) & 15;
4678 switch ((exit_qualification >> 4) & 3) {
4679 case 0: /* mov to cr */
229456fc
MT		 4680 val = kvm_register_read(vcpu, reg);
4681 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4682 switch (cr) {
4683 case 0:
eeadf9e7 4684 err = handle_set_cr0(vcpu, val);
db8fcefa 4685 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4686 return 1;
4687 case 3:
2390218b 4688 err = kvm_set_cr3(vcpu, val);
db8fcefa 4689 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4690 return 1;
4691 case 4:
eeadf9e7 4692 err = handle_set_cr4(vcpu, val);
db8fcefa 4693 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4694 return 1;
0a5fff19
GN		 4695 case 8: {
4696 u8 cr8_prev = kvm_get_cr8(vcpu);
4697 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4698 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4699 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4700 if (irqchip_in_kernel(vcpu->kvm))
4701 return 1;
4702 if (cr8_prev <= cr8)
4703 return 1;
851ba692 4704 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4705 return 0;
4706 }
4b8073e4 4707 }
6aa8b732 4708 break;
25c4c276 4709 case 2: /* clts */
eeadf9e7 4710 handle_clts(vcpu);
4d4ec087 4711 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4712 skip_emulated_instruction(vcpu);
6b52d186 4713 vmx_fpu_activate(vcpu);
25c4c276 4714 return 1;
6aa8b732
AK		 4715 case 1: /*mov from cr*/
4716 switch (cr) {
4717 case 3:
9f8fe504
AK		 4718 val = kvm_read_cr3(vcpu);
4719 kvm_register_write(vcpu, reg, val);
4720 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4721 skip_emulated_instruction(vcpu);
4722 return 1;
4723 case 8:
229456fc
MT		 4724 val = kvm_get_cr8(vcpu);
4725 kvm_register_write(vcpu, reg, val);
4726 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4727 skip_emulated_instruction(vcpu);
4728 return 1;
4729 }
4730 break;
4731 case 3: /* lmsw */
a1f83a74 4732 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4733 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4734 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4735
4736 skip_emulated_instruction(vcpu);
4737 return 1;
4738 default:
4739 break;
4740 }
851ba692 4741 vcpu->run->exit_reason = 0;
a737f256 4742 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4743 (int)(exit_qualification >> 4) & 3, cr);
4744 return 0;
4745}
4746
851ba692 4747static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4748{
bfdaab09 4749 unsigned long exit_qualification;
6aa8b732
AK		 4750 int dr, reg;
4751
f2483415 4752 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4753 if (!kvm_require_cpl(vcpu, 0))
4754 return 1;
42dbaa5a
JK		 4755 dr = vmcs_readl(GUEST_DR7);
4756 if (dr & DR7_GD) {
4757 /*
4758 * As the vm-exit takes precedence over the debug trap, we
4759 * need to emulate the latter, either for the host or the
4760 * guest debugging itself.
4761 */
4762 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4763 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4764 vcpu->run->debug.arch.dr7 = dr;
4765 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4766 vmcs_readl(GUEST_CS_BASE) +
4767 vmcs_readl(GUEST_RIP);
851ba692
AK		 4768 vcpu->run->debug.arch.exception = DB_VECTOR;
4769 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4770 return 0;
4771 } else {
4772 vcpu->arch.dr7 &= ~DR7_GD;
4773 vcpu->arch.dr6 |= DR6_BD;
4774 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4775 kvm_queue_exception(vcpu, DB_VECTOR);
4776 return 1;
4777 }
4778 }
4779
bfdaab09 4780 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4781 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4782 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4783 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4784 unsigned long val;
4785 if (!kvm_get_dr(vcpu, dr, &val))
4786 kvm_register_write(vcpu, reg, val);
4787 } else
4788 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4789 skip_emulated_instruction(vcpu);
4790 return 1;
4791}
4792
020df079
GN		 4793static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4794{
4795 vmcs_writel(GUEST_DR7, val);
4796}
4797
851ba692 4798static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4799{
06465c5a
AK		 4800 kvm_emulate_cpuid(vcpu);
4801 return 1;
6aa8b732
AK		 4802}
4803
851ba692 4804static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4805{
ad312c7c 4806 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4807 u64 data;
4808
4809 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4810 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4811 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4812 return 1;
4813 }
4814
229456fc 4815 trace_kvm_msr_read(ecx, data);
2714d1d3 4816
6aa8b732 4817 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4818 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4819 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4820 skip_emulated_instruction(vcpu);
4821 return 1;
4822}
4823
851ba692 4824static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4825{
8fe8ab46 4826 struct msr_data msr;
ad312c7c
ZX		 4827 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4828 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4829 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4830
8fe8ab46
WA		 4831 msr.data = data;
4832 msr.index = ecx;
4833 msr.host_initiated = false;
4834 if (vmx_set_msr(vcpu, &msr) != 0) {
59200273 4835 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4836 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4837 return 1;
4838 }
4839
59200273 4840 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4841 skip_emulated_instruction(vcpu);
4842 return 1;
4843}
4844
851ba692 4845static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4846{
3842d135 4847 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4848 return 1;
4849}
4850
851ba692 4851static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4852{
85f455f7
ED		 4853 u32 cpu_based_vm_exec_control;
4854
4855 /* clear pending irq */
4856 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4857 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4858 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4859
3842d135
AK		 4860 kvm_make_request(KVM_REQ_EVENT, vcpu);
4861
a26bf12a 4862 ++vcpu->stat.irq_window_exits;
2714d1d3 4863
c1150d8c
DL		 4864 /*
4865 * If the user space waits to inject interrupts, exit as soon as
4866 * possible
4867 */
8061823a 4868 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4869 vcpu->run->request_interrupt_window &&
8061823a 4870 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4871 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4872 return 0;
4873 }
6aa8b732
AK		 4874 return 1;
4875}
4876
851ba692 4877static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4878{
4879 skip_emulated_instruction(vcpu);
d3bef15f 4880 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4881}
4882
851ba692 4883static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4884{
510043da 4885 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4886 kvm_emulate_hypercall(vcpu);
4887 return 1;
c21415e8
IM		 4888}
4889
ec25d5e6
GN		 4890static int handle_invd(struct kvm_vcpu *vcpu)
4891{
51d8b661 4892 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4893}
4894
851ba692 4895static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4896{
f9c617f6 4897 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4898
4899 kvm_mmu_invlpg(vcpu, exit_qualification);
4900 skip_emulated_instruction(vcpu);
4901 return 1;
4902}
4903
fee84b07
AK		 4904static int handle_rdpmc(struct kvm_vcpu *vcpu)
4905{
4906 int err;
4907
4908 err = kvm_rdpmc(vcpu);
4909 kvm_complete_insn_gp(vcpu, err);
4910
4911 return 1;
4912}
4913
851ba692 4914static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4915{
4916 skip_emulated_instruction(vcpu);
f5f48ee1 4917 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4918 return 1;
4919}
4920
2acf923e
DC		 4921static int handle_xsetbv(struct kvm_vcpu *vcpu)
4922{
4923 u64 new_bv = kvm_read_edx_eax(vcpu);
4924 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4925
4926 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4927 skip_emulated_instruction(vcpu);
4928 return 1;
4929}
4930
851ba692 4931static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4932{
58fbbf26
KT		 4933 if (likely(fasteoi)) {
4934 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4935 int access_type, offset;
4936
4937 access_type = exit_qualification & APIC_ACCESS_TYPE;
4938 offset = exit_qualification & APIC_ACCESS_OFFSET;
4939 /*
4940 * Sane guest uses MOV to write EOI, with written value
4941 * not cared. So make a short-circuit here by avoiding
4942 * heavy instruction emulation.
4943 */
4944 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4945 (offset == APIC_EOI)) {
4946 kvm_lapic_set_eoi(vcpu);
4947 skip_emulated_instruction(vcpu);
4948 return 1;
4949 }
4950 }
51d8b661 4951 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4952}
4953
c7c9c56c
YZ		 4954static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4955{
4956 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4957 int vector = exit_qualification & 0xff;
4958
4959 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4960 kvm_apic_set_eoi_accelerated(vcpu, vector);
4961 return 1;
4962}
4963
83d4c286
YZ		 4964static int handle_apic_write(struct kvm_vcpu *vcpu)
4965{
4966 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4967 u32 offset = exit_qualification & 0xfff;
4968
4969 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4970 kvm_apic_write_nodecode(vcpu, offset);
4971 return 1;
4972}
4973
851ba692 4974static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4975{
60637aac 4976 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4977 unsigned long exit_qualification;
e269fb21
JK		 4978 bool has_error_code = false;
4979 u32 error_code = 0;
37817f29 4980 u16 tss_selector;
7f3d35fd 4981 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4982
4983 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4984 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4985 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4986
4987 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4988
4989 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4990 if (reason == TASK_SWITCH_GATE && idt_v) {
4991 switch (type) {
4992 case INTR_TYPE_NMI_INTR:
4993 vcpu->arch.nmi_injected = false;
654f06fc 4994 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4995 break;
4996 case INTR_TYPE_EXT_INTR:
66fd3f7f 4997 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4998 kvm_clear_interrupt_queue(vcpu);
4999 break;
5000 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 5001 if (vmx->idt_vectoring_info &
5002 VECTORING_INFO_DELIVER_CODE_MASK) {
5003 has_error_code = true;
5004 error_code =
5005 vmcs_read32(IDT_VECTORING_ERROR_CODE);
5006 }
5007 /* fall through */
64a7ec06
GN		 5008 case INTR_TYPE_SOFT_EXCEPTION:
5009 kvm_clear_exception_queue(vcpu);
5010 break;
5011 default:
5012 break;
5013 }
60637aac 5014 }
37817f29
IE		 5015 tss_selector = exit_qualification;
5016
64a7ec06
GN		 5017 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5018 type != INTR_TYPE_EXT_INTR &&
5019 type != INTR_TYPE_NMI_INTR))
5020 skip_emulated_instruction(vcpu);
5021
7f3d35fd
KW		 5022 if (kvm_task_switch(vcpu, tss_selector,
5023 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5024 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 5025 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5026 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5027 vcpu->run->internal.ndata = 0;
42dbaa5a 5028 return 0;
acb54517 5029 }
42dbaa5a
JK		 5030
5031 /* clear all local breakpoint enable flags */
5032 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
5033
5034 /*
5035 * TODO: What about debug traps on tss switch?
5036 * Are we supposed to inject them and update dr6?
5037 */
5038
5039 return 1;
37817f29
IE		 5040}
5041
851ba692 5042static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 5043{
f9c617f6 5044 unsigned long exit_qualification;
1439442c 5045 gpa_t gpa;
4f5982a5 5046 u32 error_code;
1439442c 5047 int gla_validity;
1439442c 5048
f9c617f6 5049 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 5050
1439442c
SY		 5051 gla_validity = (exit_qualification >> 7) & 0x3;
5052 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5053 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5054 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5055 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 5056 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 5057 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5058 (long unsigned int)exit_qualification);
851ba692
AK		 5059 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5060 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 5061 return 0;
1439442c
SY		 5062 }
5063
5064 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 5065 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5
XG		 5066
5067 /* It is a write fault? */
5068 error_code = exit_qualification & (1U << 1);
5069 /* ept page table is present? */
5070 error_code |= (exit_qualification >> 3) & 0x1;
5071
5072 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 5073}
5074
68f89400
MT		 5075static u64 ept_rsvd_mask(u64 spte, int level)
5076{
5077 int i;
5078 u64 mask = 0;
5079
5080 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
5081 mask |= (1ULL << i);
5082
5083 if (level > 2)
5084 /* bits 7:3 reserved */
5085 mask |= 0xf8;
5086 else if (level == 2) {
5087 if (spte & (1ULL << 7))
5088 /* 2MB ref, bits 20:12 reserved */
5089 mask |= 0x1ff000;
5090 else
5091 /* bits 6:3 reserved */
5092 mask |= 0x78;
5093 }
5094
5095 return mask;
5096}
5097
5098static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
5099 int level)
5100{
5101 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
5102
5103 /* 010b (write-only) */
5104 WARN_ON((spte & 0x7) == 0x2);
5105
5106 /* 110b (write/execute) */
5107 WARN_ON((spte & 0x7) == 0x6);
5108
5109 /* 100b (execute-only) and value not supported by logical processor */
5110 if (!cpu_has_vmx_ept_execute_only())
5111 WARN_ON((spte & 0x7) == 0x4);
5112
5113 /* not 000b */
5114 if ((spte & 0x7)) {
5115 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
5116
5117 if (rsvd_bits != 0) {
5118 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
5119 __func__, rsvd_bits);
5120 WARN_ON(1);
5121 }
5122
5123 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
5124 u64 ept_mem_type = (spte & 0x38) >> 3;
5125
5126 if (ept_mem_type == 2 || ept_mem_type == 3 ||
5127 ept_mem_type == 7) {
5128 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
5129 __func__, ept_mem_type);
5130 WARN_ON(1);
5131 }
5132 }
5133 }
5134}
5135
851ba692 5136static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 5137{
5138 u64 sptes[4];
ce88decf 5139 int nr_sptes, i, ret;
68f89400
MT		 5140 gpa_t gpa;
5141
5142 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5143
ce88decf
XG		 5144 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
5145 if (likely(ret == 1))
5146 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5147 EMULATE_DONE;
5148 if (unlikely(!ret))
5149 return 1;
5150
5151 /* It is the real ept misconfig */
68f89400
MT		 5152 printk(KERN_ERR "EPT: Misconfiguration.\n");
5153 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
5154
5155 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
5156
5157 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
5158 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
5159
851ba692
AK		 5160 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5161 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 5162
5163 return 0;
5164}
5165
851ba692 5166static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 5167{
5168 u32 cpu_based_vm_exec_control;
5169
5170 /* clear pending NMI */
5171 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5172 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5173 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5174 ++vcpu->stat.nmi_window_exits;
3842d135 5175 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 5176
5177 return 1;
5178}
5179
80ced186 5180static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 5181{
8b3079a5
AK		 5182 struct vcpu_vmx *vmx = to_vmx(vcpu);
5183 enum emulation_result err = EMULATE_DONE;
80ced186 5184 int ret = 1;
49e9d557
AK		 5185 u32 cpu_exec_ctrl;
5186 bool intr_window_requested;
b8405c18 5187 unsigned count = 130;
49e9d557
AK		 5188
5189 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5190 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 5191
b8405c18 5192 while (!guest_state_valid(vcpu) && count-- != 0) {
bdea48e3 5193 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 5194 return handle_interrupt_window(&vmx->vcpu);
5195
de87dcdd
AK		 5196 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5197 return 1;
5198
991eebf9 5199 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
ea953ef0 5200
80ced186
MG		 5201 if (err == EMULATE_DO_MMIO) {
5202 ret = 0;
5203 goto out;
5204 }
1d5a4d9b 5205
de5f70e0
AK		 5206 if (err != EMULATE_DONE) {
5207 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5208 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5209 vcpu->run->internal.ndata = 0;
6d77dbfc 5210 return 0;
de5f70e0 5211 }
ea953ef0
MG		 5212
5213 if (signal_pending(current))
80ced186 5214 goto out;
ea953ef0
MG		 5215 if (need_resched())
5216 schedule();
5217 }
5218
14168786 5219 vmx->emulation_required = emulation_required(vcpu);
80ced186
MG		 5220out:
5221 return ret;
ea953ef0
MG		 5222}
5223
4b8d54f9
ZE		 5224/*
5225 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5226 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5227 */
9fb41ba8 5228static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 5229{
5230 skip_emulated_instruction(vcpu);
5231 kvm_vcpu_on_spin(vcpu);
5232
5233 return 1;
5234}
5235
59708670
SY		 5236static int handle_invalid_op(struct kvm_vcpu *vcpu)
5237{
5238 kvm_queue_exception(vcpu, UD_VECTOR);
5239 return 1;
5240}
5241
ff2f6fe9
NHE		 5242/*
5243 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5244 * We could reuse a single VMCS for all the L2 guests, but we also want the
5245 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5246 * allows keeping them loaded on the processor, and in the future will allow
5247 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5248 * every entry if they never change.
5249 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5250 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5251 *
5252 * The following functions allocate and free a vmcs02 in this pool.
5253 */
5254
5255/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5256static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5257{
5258 struct vmcs02_list *item;
5259 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5260 if (item->vmptr == vmx->nested.current_vmptr) {
5261 list_move(&item->list, &vmx->nested.vmcs02_pool);
5262 return &item->vmcs02;
5263 }
5264
5265 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5266 /* Recycle the least recently used VMCS. */
5267 item = list_entry(vmx->nested.vmcs02_pool.prev,
5268 struct vmcs02_list, list);
5269 item->vmptr = vmx->nested.current_vmptr;
5270 list_move(&item->list, &vmx->nested.vmcs02_pool);
5271 return &item->vmcs02;
5272 }
5273
5274 /* Create a new VMCS */
0fa24ce3 5275 item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
ff2f6fe9
NHE		 5276 if (!item)
5277 return NULL;
5278 item->vmcs02.vmcs = alloc_vmcs();
5279 if (!item->vmcs02.vmcs) {
5280 kfree(item);
5281 return NULL;
5282 }
5283 loaded_vmcs_init(&item->vmcs02);
5284 item->vmptr = vmx->nested.current_vmptr;
5285 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5286 vmx->nested.vmcs02_num++;
5287 return &item->vmcs02;
5288}
5289
5290/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5291static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5292{
5293 struct vmcs02_list *item;
5294 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5295 if (item->vmptr == vmptr) {
5296 free_loaded_vmcs(&item->vmcs02);
5297 list_del(&item->list);
5298 kfree(item);
5299 vmx->nested.vmcs02_num--;
5300 return;
5301 }
5302}
5303
5304/*
5305 * Free all VMCSs saved for this vcpu, except the one pointed by
5306 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5307 * currently used, if running L2), and vmcs01 when running L2.
5308 */
5309static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5310{
5311 struct vmcs02_list *item, *n;
5312 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5313 if (vmx->loaded_vmcs != &item->vmcs02)
5314 free_loaded_vmcs(&item->vmcs02);
5315 list_del(&item->list);
5316 kfree(item);
5317 }
5318 vmx->nested.vmcs02_num = 0;
5319
5320 if (vmx->loaded_vmcs != &vmx->vmcs01)
5321 free_loaded_vmcs(&vmx->vmcs01);
5322}
5323
ec378aee
NHE		 5324/*
5325 * Emulate the VMXON instruction.
5326 * Currently, we just remember that VMX is active, and do not save or even
5327 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5328 * do not currently need to store anything in that guest-allocated memory
5329 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5330 * argument is different from the VMXON pointer (which the spec says they do).
5331 */
5332static int handle_vmon(struct kvm_vcpu *vcpu)
5333{
5334 struct kvm_segment cs;
5335 struct vcpu_vmx *vmx = to_vmx(vcpu);
5336
5337 /* The Intel VMX Instruction Reference lists a bunch of bits that
5338 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5339 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5340 * Otherwise, we should fail with #UD. We test these now:
5341 */
5342 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5343 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5344 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5345 kvm_queue_exception(vcpu, UD_VECTOR);
5346 return 1;
5347 }
5348
5349 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5350 if (is_long_mode(vcpu) && !cs.l) {
5351 kvm_queue_exception(vcpu, UD_VECTOR);
5352 return 1;
5353 }
5354
5355 if (vmx_get_cpl(vcpu)) {
5356 kvm_inject_gp(vcpu, 0);
5357 return 1;
5358 }
5359
ff2f6fe9
NHE		 5360 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5361 vmx->nested.vmcs02_num = 0;
5362
ec378aee
NHE		 5363 vmx->nested.vmxon = true;
5364
5365 skip_emulated_instruction(vcpu);
5366 return 1;
5367}
5368
5369/*
5370 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5371 * for running VMX instructions (except VMXON, whose prerequisites are
5372 * slightly different). It also specifies what exception to inject otherwise.
5373 */
5374static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5375{
5376 struct kvm_segment cs;
5377 struct vcpu_vmx *vmx = to_vmx(vcpu);
5378
5379 if (!vmx->nested.vmxon) {
5380 kvm_queue_exception(vcpu, UD_VECTOR);
5381 return 0;
5382 }
5383
5384 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5385 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5386 (is_long_mode(vcpu) && !cs.l)) {
5387 kvm_queue_exception(vcpu, UD_VECTOR);
5388 return 0;
5389 }
5390
5391 if (vmx_get_cpl(vcpu)) {
5392 kvm_inject_gp(vcpu, 0);
5393 return 0;
5394 }
5395
5396 return 1;
5397}
5398
5399/*
5400 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5401 * just stops using VMX.
5402 */
5403static void free_nested(struct vcpu_vmx *vmx)
5404{
5405 if (!vmx->nested.vmxon)
5406 return;
5407 vmx->nested.vmxon = false;
a9d30f33
NHE		 5408 if (vmx->nested.current_vmptr != -1ull) {
5409 kunmap(vmx->nested.current_vmcs12_page);
5410 nested_release_page(vmx->nested.current_vmcs12_page);
5411 vmx->nested.current_vmptr = -1ull;
5412 vmx->nested.current_vmcs12 = NULL;
5413 }
fe3ef05c
NHE		 5414 /* Unpin physical memory we referred to in current vmcs02 */
5415 if (vmx->nested.apic_access_page) {
5416 nested_release_page(vmx->nested.apic_access_page);
5417 vmx->nested.apic_access_page = 0;
5418 }
ff2f6fe9
NHE		 5419
5420 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 5421}
5422
5423/* Emulate the VMXOFF instruction */
5424static int handle_vmoff(struct kvm_vcpu *vcpu)
5425{
5426 if (!nested_vmx_check_permission(vcpu))
5427 return 1;
5428 free_nested(to_vmx(vcpu));
5429 skip_emulated_instruction(vcpu);
5430 return 1;
5431}
5432
064aea77
NHE		 5433/*
5434 * Decode the memory-address operand of a vmx instruction, as recorded on an
5435 * exit caused by such an instruction (run by a guest hypervisor).
5436 * On success, returns 0. When the operand is invalid, returns 1 and throws
5437 * #UD or #GP.
5438 */
5439static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5440 unsigned long exit_qualification,
5441 u32 vmx_instruction_info, gva_t *ret)
5442{
5443 /*
5444 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5445 * Execution", on an exit, vmx_instruction_info holds most of the
5446 * addressing components of the operand. Only the displacement part
5447 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5448 * For how an actual address is calculated from all these components,
5449 * refer to Vol. 1, "Operand Addressing".
5450 */
5451 int scaling = vmx_instruction_info & 3;
5452 int addr_size = (vmx_instruction_info >> 7) & 7;
5453 bool is_reg = vmx_instruction_info & (1u << 10);
5454 int seg_reg = (vmx_instruction_info >> 15) & 7;
5455 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5456 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5457 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5458 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5459
5460 if (is_reg) {
5461 kvm_queue_exception(vcpu, UD_VECTOR);
5462 return 1;
5463 }
5464
5465 /* Addr = segment_base + offset */
5466 /* offset = base + [index * scale] + displacement */
5467 *ret = vmx_get_segment_base(vcpu, seg_reg);
5468 if (base_is_valid)
5469 *ret += kvm_register_read(vcpu, base_reg);
5470 if (index_is_valid)
5471 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5472 *ret += exit_qualification; /* holds the displacement */
5473
5474 if (addr_size == 1) /* 32 bit */
5475 *ret &= 0xffffffff;
5476
5477 /*
5478 * TODO: throw #GP (and return 1) in various cases that the VM*
5479 * instructions require it - e.g., offset beyond segment limit,
5480 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5481 * address, and so on. Currently these are not checked.
5482 */
5483 return 0;
5484}
5485
0140caea
NHE		 5486/*
5487 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5488 * set the success or error code of an emulated VMX instruction, as specified
5489 * by Vol 2B, VMX Instruction Reference, "Conventions".
5490 */
5491static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5492{
5493 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5494 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5495 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5496}
5497
5498static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5499{
5500 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5501 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5502 X86_EFLAGS_SF | X86_EFLAGS_OF))
5503 | X86_EFLAGS_CF);
5504}
5505
5506static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5507 u32 vm_instruction_error)
5508{
5509 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5510 /*
5511 * failValid writes the error number to the current VMCS, which
5512 * can't be done there isn't a current VMCS.
5513 */
5514 nested_vmx_failInvalid(vcpu);
5515 return;
5516 }
5517 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5518 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5519 X86_EFLAGS_SF | X86_EFLAGS_OF))
5520 | X86_EFLAGS_ZF);
5521 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5522}
5523
27d6c865
NHE		 5524/* Emulate the VMCLEAR instruction */
5525static int handle_vmclear(struct kvm_vcpu *vcpu)
5526{
5527 struct vcpu_vmx *vmx = to_vmx(vcpu);
5528 gva_t gva;
5529 gpa_t vmptr;
5530 struct vmcs12 *vmcs12;
5531 struct page *page;
5532 struct x86_exception e;
5533
5534 if (!nested_vmx_check_permission(vcpu))
5535 return 1;
5536
5537 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5538 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5539 return 1;
5540
5541 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5542 sizeof(vmptr), &e)) {
5543 kvm_inject_page_fault(vcpu, &e);
5544 return 1;
5545 }
5546
5547 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5548 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5549 skip_emulated_instruction(vcpu);
5550 return 1;
5551 }
5552
5553 if (vmptr == vmx->nested.current_vmptr) {
5554 kunmap(vmx->nested.current_vmcs12_page);
5555 nested_release_page(vmx->nested.current_vmcs12_page);
5556 vmx->nested.current_vmptr = -1ull;
5557 vmx->nested.current_vmcs12 = NULL;
5558 }
5559
5560 page = nested_get_page(vcpu, vmptr);
5561 if (page == NULL) {
5562 /*
5563 * For accurate processor emulation, VMCLEAR beyond available
5564 * physical memory should do nothing at all. However, it is
5565 * possible that a nested vmx bug, not a guest hypervisor bug,
5566 * resulted in this case, so let's shut down before doing any
5567 * more damage:
5568 */
5569 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5570 return 1;
5571 }
5572 vmcs12 = kmap(page);
5573 vmcs12->launch_state = 0;
5574 kunmap(page);
5575 nested_release_page(page);
5576
5577 nested_free_vmcs02(vmx, vmptr);
5578
5579 skip_emulated_instruction(vcpu);
5580 nested_vmx_succeed(vcpu);
5581 return 1;
5582}
5583
cd232ad0
NHE		 5584static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5585
5586/* Emulate the VMLAUNCH instruction */
5587static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5588{
5589 return nested_vmx_run(vcpu, true);
5590}
5591
5592/* Emulate the VMRESUME instruction */
5593static int handle_vmresume(struct kvm_vcpu *vcpu)
5594{
5595
5596 return nested_vmx_run(vcpu, false);
5597}
5598
49f705c5
NHE		 5599enum vmcs_field_type {
5600 VMCS_FIELD_TYPE_U16 = 0,
5601 VMCS_FIELD_TYPE_U64 = 1,
5602 VMCS_FIELD_TYPE_U32 = 2,
5603 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5604};
5605
5606static inline int vmcs_field_type(unsigned long field)
5607{
5608 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5609 return VMCS_FIELD_TYPE_U32;
5610 return (field >> 13) & 0x3 ;
5611}
5612
5613static inline int vmcs_field_readonly(unsigned long field)
5614{
5615 return (((field >> 10) & 0x3) == 1);
5616}
5617
5618/*
5619 * Read a vmcs12 field. Since these can have varying lengths and we return
5620 * one type, we chose the biggest type (u64) and zero-extend the return value
5621 * to that size. Note that the caller, handle_vmread, might need to use only
5622 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5623 * 64-bit fields are to be returned).
5624 */
5625static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5626 unsigned long field, u64 *ret)
5627{
5628 short offset = vmcs_field_to_offset(field);
5629 char *p;
5630
5631 if (offset < 0)
5632 return 0;
5633
5634 p = ((char *)(get_vmcs12(vcpu))) + offset;
5635
5636 switch (vmcs_field_type(field)) {
5637 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5638 *ret = *((natural_width *)p);
5639 return 1;
5640 case VMCS_FIELD_TYPE_U16:
5641 *ret = *((u16 *)p);
5642 return 1;
5643 case VMCS_FIELD_TYPE_U32:
5644 *ret = *((u32 *)p);
5645 return 1;
5646 case VMCS_FIELD_TYPE_U64:
5647 *ret = *((u64 *)p);
5648 return 1;
5649 default:
5650 return 0; /* can never happen. */
5651 }
5652}
5653
5654/*
5655 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5656 * used before) all generate the same failure when it is missing.
5657 */
5658static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5659{
5660 struct vcpu_vmx *vmx = to_vmx(vcpu);
5661 if (vmx->nested.current_vmptr == -1ull) {
5662 nested_vmx_failInvalid(vcpu);
5663 skip_emulated_instruction(vcpu);
5664 return 0;
5665 }
5666 return 1;
5667}
5668
5669static int handle_vmread(struct kvm_vcpu *vcpu)
5670{
5671 unsigned long field;
5672 u64 field_value;
5673 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5674 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5675 gva_t gva = 0;
5676
5677 if (!nested_vmx_check_permission(vcpu) ||
5678 !nested_vmx_check_vmcs12(vcpu))
5679 return 1;
5680
5681 /* Decode instruction info and find the field to read */
5682 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5683 /* Read the field, zero-extended to a u64 field_value */
5684 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5685 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5686 skip_emulated_instruction(vcpu);
5687 return 1;
5688 }
5689 /*
5690 * Now copy part of this value to register or memory, as requested.
5691 * Note that the number of bits actually copied is 32 or 64 depending
5692 * on the guest's mode (32 or 64 bit), not on the given field's length.
5693 */
5694 if (vmx_instruction_info & (1u << 10)) {
5695 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5696 field_value);
5697 } else {
5698 if (get_vmx_mem_address(vcpu, exit_qualification,
5699 vmx_instruction_info, &gva))
5700 return 1;
5701 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5702 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5703 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5704 }
5705
5706 nested_vmx_succeed(vcpu);
5707 skip_emulated_instruction(vcpu);
5708 return 1;
5709}
5710
5711
5712static int handle_vmwrite(struct kvm_vcpu *vcpu)
5713{
5714 unsigned long field;
5715 gva_t gva;
5716 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5717 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5718 char *p;
5719 short offset;
5720 /* The value to write might be 32 or 64 bits, depending on L1's long
5721 * mode, and eventually we need to write that into a field of several
5722 * possible lengths. The code below first zero-extends the value to 64
5723 * bit (field_value), and then copies only the approriate number of
5724 * bits into the vmcs12 field.
5725 */
5726 u64 field_value = 0;
5727 struct x86_exception e;
5728
5729 if (!nested_vmx_check_permission(vcpu) ||
5730 !nested_vmx_check_vmcs12(vcpu))
5731 return 1;
5732
5733 if (vmx_instruction_info & (1u << 10))
5734 field_value = kvm_register_read(vcpu,
5735 (((vmx_instruction_info) >> 3) & 0xf));
5736 else {
5737 if (get_vmx_mem_address(vcpu, exit_qualification,
5738 vmx_instruction_info, &gva))
5739 return 1;
5740 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5741 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5742 kvm_inject_page_fault(vcpu, &e);
5743 return 1;
5744 }
5745 }
5746
5747
5748 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5749 if (vmcs_field_readonly(field)) {
5750 nested_vmx_failValid(vcpu,
5751 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5752 skip_emulated_instruction(vcpu);
5753 return 1;
5754 }
5755
5756 offset = vmcs_field_to_offset(field);
5757 if (offset < 0) {
5758 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5759 skip_emulated_instruction(vcpu);
5760 return 1;
5761 }
5762 p = ((char *) get_vmcs12(vcpu)) + offset;
5763
5764 switch (vmcs_field_type(field)) {
5765 case VMCS_FIELD_TYPE_U16:
5766 *(u16 *)p = field_value;
5767 break;
5768 case VMCS_FIELD_TYPE_U32:
5769 *(u32 *)p = field_value;
5770 break;
5771 case VMCS_FIELD_TYPE_U64:
5772 *(u64 *)p = field_value;
5773 break;
5774 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5775 *(natural_width *)p = field_value;
5776 break;
5777 default:
5778 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5779 skip_emulated_instruction(vcpu);
5780 return 1;
5781 }
5782
5783 nested_vmx_succeed(vcpu);
5784 skip_emulated_instruction(vcpu);
5785 return 1;
5786}
5787
63846663
NHE		 5788/* Emulate the VMPTRLD instruction */
5789static int handle_vmptrld(struct kvm_vcpu *vcpu)
5790{
5791 struct vcpu_vmx *vmx = to_vmx(vcpu);
5792 gva_t gva;
5793 gpa_t vmptr;
5794 struct x86_exception e;
5795
5796 if (!nested_vmx_check_permission(vcpu))
5797 return 1;
5798
5799 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5800 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5801 return 1;
5802
5803 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5804 sizeof(vmptr), &e)) {
5805 kvm_inject_page_fault(vcpu, &e);
5806 return 1;
5807 }
5808
5809 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5810 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5811 skip_emulated_instruction(vcpu);
5812 return 1;
5813 }
5814
5815 if (vmx->nested.current_vmptr != vmptr) {
5816 struct vmcs12 *new_vmcs12;
5817 struct page *page;
5818 page = nested_get_page(vcpu, vmptr);
5819 if (page == NULL) {
5820 nested_vmx_failInvalid(vcpu);
5821 skip_emulated_instruction(vcpu);
5822 return 1;
5823 }
5824 new_vmcs12 = kmap(page);
5825 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5826 kunmap(page);
5827 nested_release_page_clean(page);
5828 nested_vmx_failValid(vcpu,
5829 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5830 skip_emulated_instruction(vcpu);
5831 return 1;
5832 }
5833 if (vmx->nested.current_vmptr != -1ull) {
5834 kunmap(vmx->nested.current_vmcs12_page);
5835 nested_release_page(vmx->nested.current_vmcs12_page);
5836 }
5837
5838 vmx->nested.current_vmptr = vmptr;
5839 vmx->nested.current_vmcs12 = new_vmcs12;
5840 vmx->nested.current_vmcs12_page = page;
5841 }
5842
5843 nested_vmx_succeed(vcpu);
5844 skip_emulated_instruction(vcpu);
5845 return 1;
5846}
5847
6a4d7550
NHE		 5848/* Emulate the VMPTRST instruction */
5849static int handle_vmptrst(struct kvm_vcpu *vcpu)
5850{
5851 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5852 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5853 gva_t vmcs_gva;
5854 struct x86_exception e;
5855
5856 if (!nested_vmx_check_permission(vcpu))
5857 return 1;
5858
5859 if (get_vmx_mem_address(vcpu, exit_qualification,
5860 vmx_instruction_info, &vmcs_gva))
5861 return 1;
5862 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5863 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5864 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5865 sizeof(u64), &e)) {
5866 kvm_inject_page_fault(vcpu, &e);
5867 return 1;
5868 }
5869 nested_vmx_succeed(vcpu);
5870 skip_emulated_instruction(vcpu);
5871 return 1;
5872}
5873
6aa8b732
AK		 5874/*
5875 * The exit handlers return 1 if the exit was handled fully and guest execution
5876 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5877 * to be done to userspace and return 0.
5878 */
772e0318 5879static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5880 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5881 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5882 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5883 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5884 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5885 [EXIT_REASON_CR_ACCESS] = handle_cr,
5886 [EXIT_REASON_DR_ACCESS] = handle_dr,
5887 [EXIT_REASON_CPUID] = handle_cpuid,
5888 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5889 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5890 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5891 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5892 [EXIT_REASON_INVD] = handle_invd,
a7052897 5893 [EXIT_REASON_INVLPG] = handle_invlpg,
fee84b07 5894 [EXIT_REASON_RDPMC] = handle_rdpmc,
c21415e8 5895 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5896 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5897 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5898 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5899 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5900 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5901 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5902 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5903 [EXIT_REASON_VMOFF] = handle_vmoff,
5904 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5905 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5906 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
83d4c286 5907 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
c7c9c56c 5908 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
e5edaa01 5909 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5910 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5911 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5912 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5913 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5914 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5915 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5916 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5917 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5918};
5919
5920static const int kvm_vmx_max_exit_handlers =
50a3485c 5921 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5922
908a7bdd
JK		 5923static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
5924 struct vmcs12 *vmcs12)
5925{
5926 unsigned long exit_qualification;
5927 gpa_t bitmap, last_bitmap;
5928 unsigned int port;
5929 int size;
5930 u8 b;
5931
5932 if (nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING))
5933 return 1;
5934
5935 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
5936 return 0;
5937
5938 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5939
5940 port = exit_qualification >> 16;
5941 size = (exit_qualification & 7) + 1;
5942
5943 last_bitmap = (gpa_t)-1;
5944 b = -1;
5945
5946 while (size > 0) {
5947 if (port < 0x8000)
5948 bitmap = vmcs12->io_bitmap_a;
5949 else if (port < 0x10000)
5950 bitmap = vmcs12->io_bitmap_b;
5951 else
5952 return 1;
5953 bitmap += (port & 0x7fff) / 8;
5954
5955 if (last_bitmap != bitmap)
5956 if (kvm_read_guest(vcpu->kvm, bitmap, &b, 1))
5957 return 1;
5958 if (b & (1 << (port & 7)))
5959 return 1;
5960
5961 port++;
5962 size--;
5963 last_bitmap = bitmap;
5964 }
5965
5966 return 0;
5967}
5968
644d711a
NHE		 5969/*
5970 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5971 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5972 * disinterest in the current event (read or write a specific MSR) by using an
5973 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5974 */
5975static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5976 struct vmcs12 *vmcs12, u32 exit_reason)
5977{
5978 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5979 gpa_t bitmap;
5980
cbd29cb6 5981 if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
644d711a
NHE		 5982 return 1;
5983
5984 /*
5985 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5986 * for the four combinations of read/write and low/high MSR numbers.
5987 * First we need to figure out which of the four to use:
5988 */
5989 bitmap = vmcs12->msr_bitmap;
5990 if (exit_reason == EXIT_REASON_MSR_WRITE)
5991 bitmap += 2048;
5992 if (msr_index >= 0xc0000000) {
5993 msr_index -= 0xc0000000;
5994 bitmap += 1024;
5995 }
5996
5997 /* Then read the msr_index'th bit from this bitmap: */
5998 if (msr_index < 1024*8) {
5999 unsigned char b;
bd31a7f5
JK		 6000 if (kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1))
6001 return 1;
644d711a
NHE		 6002 return 1 & (b >> (msr_index & 7));
6003 } else
6004 return 1; /* let L1 handle the wrong parameter */
6005}
6006
6007/*
6008 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6009 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6010 * intercept (via guest_host_mask etc.) the current event.
6011 */
6012static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
6013 struct vmcs12 *vmcs12)
6014{
6015 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6016 int cr = exit_qualification & 15;
6017 int reg = (exit_qualification >> 8) & 15;
6018 unsigned long val = kvm_register_read(vcpu, reg);
6019
6020 switch ((exit_qualification >> 4) & 3) {
6021 case 0: /* mov to cr */
6022 switch (cr) {
6023 case 0:
6024 if (vmcs12->cr0_guest_host_mask &
6025 (val ^ vmcs12->cr0_read_shadow))
6026 return 1;
6027 break;
6028 case 3:
6029 if ((vmcs12->cr3_target_count >= 1 &&
6030 vmcs12->cr3_target_value0 == val) ||
6031 (vmcs12->cr3_target_count >= 2 &&
6032 vmcs12->cr3_target_value1 == val) ||
6033 (vmcs12->cr3_target_count >= 3 &&
6034 vmcs12->cr3_target_value2 == val) ||
6035 (vmcs12->cr3_target_count >= 4 &&
6036 vmcs12->cr3_target_value3 == val))
6037 return 0;
6038 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
6039 return 1;
6040 break;
6041 case 4:
6042 if (vmcs12->cr4_guest_host_mask &
6043 (vmcs12->cr4_read_shadow ^ val))
6044 return 1;
6045 break;
6046 case 8:
6047 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
6048 return 1;
6049 break;
6050 }
6051 break;
6052 case 2: /* clts */
6053 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
6054 (vmcs12->cr0_read_shadow & X86_CR0_TS))
6055 return 1;
6056 break;
6057 case 1: /* mov from cr */
6058 switch (cr) {
6059 case 3:
6060 if (vmcs12->cpu_based_vm_exec_control &
6061 CPU_BASED_CR3_STORE_EXITING)
6062 return 1;
6063 break;
6064 case 8:
6065 if (vmcs12->cpu_based_vm_exec_control &
6066 CPU_BASED_CR8_STORE_EXITING)
6067 return 1;
6068 break;
6069 }
6070 break;
6071 case 3: /* lmsw */
6072 /*
6073 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6074 * cr0. Other attempted changes are ignored, with no exit.
6075 */
6076 if (vmcs12->cr0_guest_host_mask & 0xe &
6077 (val ^ vmcs12->cr0_read_shadow))
6078 return 1;
6079 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
6080 !(vmcs12->cr0_read_shadow & 0x1) &&
6081 (val & 0x1))
6082 return 1;
6083 break;
6084 }
6085 return 0;
6086}
6087
6088/*
6089 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6090 * should handle it ourselves in L0 (and then continue L2). Only call this
6091 * when in is_guest_mode (L2).
6092 */
6093static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
6094{
644d711a
NHE		 6095 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6096 struct vcpu_vmx *vmx = to_vmx(vcpu);
6097 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
957c897e 6098 u32 exit_reason = vmx->exit_reason;
644d711a
NHE		 6099
6100 if (vmx->nested.nested_run_pending)
6101 return 0;
6102
6103 if (unlikely(vmx->fail)) {
bd80158a
JK		 6104 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
6105 vmcs_read32(VM_INSTRUCTION_ERROR));
644d711a
NHE		 6106 return 1;
6107 }
6108
6109 switch (exit_reason) {
6110 case EXIT_REASON_EXCEPTION_NMI:
6111 if (!is_exception(intr_info))
6112 return 0;
6113 else if (is_page_fault(intr_info))
6114 return enable_ept;
6115 return vmcs12->exception_bitmap &
6116 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
6117 case EXIT_REASON_EXTERNAL_INTERRUPT:
6118 return 0;
6119 case EXIT_REASON_TRIPLE_FAULT:
6120 return 1;
6121 case EXIT_REASON_PENDING_INTERRUPT:
3b656cf7 6122 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
644d711a 6123 case EXIT_REASON_NMI_WINDOW:
3b656cf7 6124 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
644d711a
NHE		 6125 case EXIT_REASON_TASK_SWITCH:
6126 return 1;
6127 case EXIT_REASON_CPUID:
6128 return 1;
6129 case EXIT_REASON_HLT:
6130 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
6131 case EXIT_REASON_INVD:
6132 return 1;
6133 case EXIT_REASON_INVLPG:
6134 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
6135 case EXIT_REASON_RDPMC:
6136 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
6137 case EXIT_REASON_RDTSC:
6138 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
6139 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
6140 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
6141 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
6142 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
6143 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
6144 /*
6145 * VMX instructions trap unconditionally. This allows L1 to
6146 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6147 */
6148 return 1;
6149 case EXIT_REASON_CR_ACCESS:
6150 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
6151 case EXIT_REASON_DR_ACCESS:
6152 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
6153 case EXIT_REASON_IO_INSTRUCTION:
908a7bdd 6154 return nested_vmx_exit_handled_io(vcpu, vmcs12);
644d711a
NHE		 6155 case EXIT_REASON_MSR_READ:
6156 case EXIT_REASON_MSR_WRITE:
6157 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
6158 case EXIT_REASON_INVALID_STATE:
6159 return 1;
6160 case EXIT_REASON_MWAIT_INSTRUCTION:
6161 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
6162 case EXIT_REASON_MONITOR_INSTRUCTION:
6163 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
6164 case EXIT_REASON_PAUSE_INSTRUCTION:
6165 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
6166 nested_cpu_has2(vmcs12,
6167 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
6168 case EXIT_REASON_MCE_DURING_VMENTRY:
6169 return 0;
6170 case EXIT_REASON_TPR_BELOW_THRESHOLD:
6171 return 1;
6172 case EXIT_REASON_APIC_ACCESS:
6173 return nested_cpu_has2(vmcs12,
6174 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
6175 case EXIT_REASON_EPT_VIOLATION:
6176 case EXIT_REASON_EPT_MISCONFIG:
6177 return 0;
0238ea91
JK		 6178 case EXIT_REASON_PREEMPTION_TIMER:
6179 return vmcs12->pin_based_vm_exec_control &
6180 PIN_BASED_VMX_PREEMPTION_TIMER;
644d711a
NHE		 6181 case EXIT_REASON_WBINVD:
6182 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
6183 case EXIT_REASON_XSETBV:
6184 return 1;
6185 default:
6186 return 1;
6187 }
6188}
6189
586f9607
AK		 6190static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
6191{
6192 *info1 = vmcs_readl(EXIT_QUALIFICATION);
6193 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
6194}
6195
6aa8b732
AK		 6196/*
6197 * The guest has exited. See if we can fix it or if we need userspace
6198 * assistance.
6199 */
851ba692 6200static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 6201{
29bd8a78 6202 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 6203 u32 exit_reason = vmx->exit_reason;
1155f76a 6204 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 6205
80ced186 6206 /* If guest state is invalid, start emulating */
14168786 6207 if (vmx->emulation_required)
80ced186 6208 return handle_invalid_guest_state(vcpu);
1d5a4d9b 6209
b6f1250e
NHE		 6210 /*
6211 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6212 * we did not inject a still-pending event to L1 now because of
6213 * nested_run_pending, we need to re-enable this bit.
6214 */
6215 if (vmx->nested.nested_run_pending)
6216 kvm_make_request(KVM_REQ_EVENT, vcpu);
6217
509c75ea
NHE		 6218 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
6219 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 6220 vmx->nested.nested_run_pending = 1;
6221 else
6222 vmx->nested.nested_run_pending = 0;
6223
6224 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
6225 nested_vmx_vmexit(vcpu);
6226 return 1;
6227 }
6228
5120702e
MG		 6229 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6230 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6231 vcpu->run->fail_entry.hardware_entry_failure_reason
6232 = exit_reason;
6233 return 0;
6234 }
6235
29bd8a78 6236 if (unlikely(vmx->fail)) {
851ba692
AK		 6237 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6238 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 6239 = vmcs_read32(VM_INSTRUCTION_ERROR);
6240 return 0;
6241 }
6aa8b732 6242
b9bf6882
XG		 6243 /*
6244 * Note:
6245 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6246 * delivery event since it indicates guest is accessing MMIO.
6247 * The vm-exit can be triggered again after return to guest that
6248 * will cause infinite loop.
6249 */
d77c26fc 6250 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 6251 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac 6252 exit_reason != EXIT_REASON_EPT_VIOLATION &&
b9bf6882
XG		 6253 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6254 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6255 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6256 vcpu->run->internal.ndata = 2;
6257 vcpu->run->internal.data[0] = vectoring_info;
6258 vcpu->run->internal.data[1] = exit_reason;
6259 return 0;
6260 }
3b86cd99 6261
644d711a
NHE		 6262 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6263 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6264 get_vmcs12(vcpu), vcpu)))) {
c4282df9 6265 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 6266 vmx->soft_vnmi_blocked = 0;
3b86cd99 6267 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 6268 vcpu->arch.nmi_pending) {
3b86cd99
JK		 6269 /*
6270 * This CPU don't support us in finding the end of an
6271 * NMI-blocked window if the guest runs with IRQs
6272 * disabled. So we pull the trigger after 1 s of
6273 * futile waiting, but inform the user about this.
6274 */
6275 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6276 "state on VCPU %d after 1 s timeout\n",
6277 __func__, vcpu->vcpu_id);
6278 vmx->soft_vnmi_blocked = 0;
3b86cd99 6279 }
3b86cd99
JK		 6280 }
6281
6aa8b732
AK		 6282 if (exit_reason < kvm_vmx_max_exit_handlers
6283 && kvm_vmx_exit_handlers[exit_reason])
851ba692 6284 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 6285 else {
851ba692
AK		 6286 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6287 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 6288 }
6289 return 0;
6290}
6291
95ba8273 6292static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 6293{
95ba8273 6294 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 6295 vmcs_write32(TPR_THRESHOLD, 0);
6296 return;
6297 }
6298
95ba8273 6299 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 6300}
6301
8d14695f
YZ		 6302static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
6303{
6304 u32 sec_exec_control;
6305
6306 /*
6307 * There is not point to enable virtualize x2apic without enable
6308 * apicv
6309 */
c7c9c56c
YZ		 6310 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6311 !vmx_vm_has_apicv(vcpu->kvm))
8d14695f
YZ		 6312 return;
6313
6314 if (!vm_need_tpr_shadow(vcpu->kvm))
6315 return;
6316
6317 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6318
6319 if (set) {
6320 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6321 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6322 } else {
6323 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
6324 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6325 }
6326 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
6327
6328 vmx_set_msr_bitmap(vcpu);
6329}
6330
c7c9c56c
YZ		 6331static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
6332{
6333 u16 status;
6334 u8 old;
6335
6336 if (!vmx_vm_has_apicv(kvm))
6337 return;
6338
6339 if (isr == -1)
6340 isr = 0;
6341
6342 status = vmcs_read16(GUEST_INTR_STATUS);
6343 old = status >> 8;
6344 if (isr != old) {
6345 status &= 0xff;
6346 status |= isr << 8;
6347 vmcs_write16(GUEST_INTR_STATUS, status);
6348 }
6349}
6350
6351static void vmx_set_rvi(int vector)
6352{
6353 u16 status;
6354 u8 old;
6355
6356 status = vmcs_read16(GUEST_INTR_STATUS);
6357 old = (u8)status & 0xff;
6358 if ((u8)vector != old) {
6359 status &= ~0xff;
6360 status |= (u8)vector;
6361 vmcs_write16(GUEST_INTR_STATUS, status);
6362 }
6363}
6364
6365static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
6366{
6367 if (max_irr == -1)
6368 return;
6369
6370 vmx_set_rvi(max_irr);
6371}
6372
6373static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
6374{
6375 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
6376 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
6377 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
6378 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
6379}
6380
51aa01d1 6381static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 6382{
00eba012
AK		 6383 u32 exit_intr_info;
6384
6385 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6386 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6387 return;
6388
c5ca8e57 6389 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 6390 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 6391
6392 /* Handle machine checks before interrupts are enabled */
00eba012 6393 if (is_machine_check(exit_intr_info))
a0861c02
AK		 6394 kvm_machine_check();
6395
20f65983 6396 /* We need to handle NMIs before interrupts are enabled */
00eba012 6397 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 6398 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6399 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 6400 asm("int $2");
ff9d07a0
ZY		 6401 kvm_after_handle_nmi(&vmx->vcpu);
6402 }
51aa01d1 6403}
20f65983 6404
a547c6db
YZ		 6405static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
6406{
6407 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6408
6409 /*
6410 * If external interrupt exists, IF bit is set in rflags/eflags on the
6411 * interrupt stack frame, and interrupt will be enabled on a return
6412 * from interrupt handler.
6413 */
6414 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
6415 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
6416 unsigned int vector;
6417 unsigned long entry;
6418 gate_desc *desc;
6419 struct vcpu_vmx *vmx = to_vmx(vcpu);
6420#ifdef CONFIG_X86_64
6421 unsigned long tmp;
6422#endif
6423
6424 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6425 desc = (gate_desc *)vmx->host_idt_base + vector;
6426 entry = gate_offset(*desc);
6427 asm volatile(
6428#ifdef CONFIG_X86_64
6429 "mov %%" _ASM_SP ", %[sp]\n\t"
6430 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
6431 "push $%c[ss]\n\t"
6432 "push %[sp]\n\t"
6433#endif
6434 "pushf\n\t"
6435 "orl $0x200, (%%" _ASM_SP ")\n\t"
6436 __ASM_SIZE(push) " $%c[cs]\n\t"
6437 "call *%[entry]\n\t"
6438 :
6439#ifdef CONFIG_X86_64
6440 [sp]"=&r"(tmp)
6441#endif
6442 :
6443 [entry]"r"(entry),
6444 [ss]"i"(__KERNEL_DS),
6445 [cs]"i"(__KERNEL_CS)
6446 );
6447 } else
6448 local_irq_enable();
6449}
6450
51aa01d1
AK		 6451static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6452{
c5ca8e57 6453 u32 exit_intr_info;
51aa01d1
AK		 6454 bool unblock_nmi;
6455 u8 vector;
6456 bool idtv_info_valid;
6457
6458 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 6459
cf393f75 6460 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 6461 if (vmx->nmi_known_unmasked)
6462 return;
c5ca8e57
AK		 6463 /*
6464 * Can't use vmx->exit_intr_info since we're not sure what
6465 * the exit reason is.
6466 */
6467 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 6468 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6469 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6470 /*
7b4a25cb 6471 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 6472 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6473 * a guest IRET fault.
7b4a25cb
GN		 6474 * SDM 3: 23.2.2 (September 2008)
6475 * Bit 12 is undefined in any of the following cases:
6476 * If the VM exit sets the valid bit in the IDT-vectoring
6477 * information field.
6478 * If the VM exit is due to a double fault.
cf393f75 6479 */
7b4a25cb
GN		 6480 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6481 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 6482 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6483 GUEST_INTR_STATE_NMI);
9d58b931
AK		 6484 else
6485 vmx->nmi_known_unmasked =
6486 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6487 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 6488 } else if (unlikely(vmx->soft_vnmi_blocked))
6489 vmx->vnmi_blocked_time +=
6490 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 6491}
6492
3ab66e8a 6493static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
83422e17
AK		 6494 u32 idt_vectoring_info,
6495 int instr_len_field,
6496 int error_code_field)
51aa01d1 6497{
51aa01d1
AK		 6498 u8 vector;
6499 int type;
6500 bool idtv_info_valid;
6501
6502 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 6503
3ab66e8a
JK		 6504 vcpu->arch.nmi_injected = false;
6505 kvm_clear_exception_queue(vcpu);
6506 kvm_clear_interrupt_queue(vcpu);
37b96e98
GN		 6507
6508 if (!idtv_info_valid)
6509 return;
6510
3ab66e8a 6511 kvm_make_request(KVM_REQ_EVENT, vcpu);
3842d135 6512
668f612f
AK		 6513 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6514 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 6515
64a7ec06 6516 switch (type) {
37b96e98 6517 case INTR_TYPE_NMI_INTR:
3ab66e8a 6518 vcpu->arch.nmi_injected = true;
668f612f 6519 /*
7b4a25cb 6520 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 6521 * Clear bit "block by NMI" before VM entry if a NMI
6522 * delivery faulted.
668f612f 6523 */
3ab66e8a 6524 vmx_set_nmi_mask(vcpu, false);
37b96e98 6525 break;
37b96e98 6526 case INTR_TYPE_SOFT_EXCEPTION:
3ab66e8a 6527 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f
GN		 6528 /* fall through */
6529 case INTR_TYPE_HARD_EXCEPTION:
35920a35 6530 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 6531 u32 err = vmcs_read32(error_code_field);
3ab66e8a 6532 kvm_queue_exception_e(vcpu, vector, err);
35920a35 6533 } else
3ab66e8a 6534 kvm_queue_exception(vcpu, vector);
37b96e98 6535 break;
66fd3f7f 6536 case INTR_TYPE_SOFT_INTR:
3ab66e8a 6537 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
66fd3f7f 6538 /* fall through */
37b96e98 6539 case INTR_TYPE_EXT_INTR:
3ab66e8a 6540 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 6541 break;
6542 default:
6543 break;
f7d9238f 6544 }
cf393f75
AK		 6545}
6546
83422e17
AK		 6547static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6548{
3ab66e8a 6549 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
83422e17
AK		 6550 VM_EXIT_INSTRUCTION_LEN,
6551 IDT_VECTORING_ERROR_CODE);
6552}
6553
b463a6f7
AK		 6554static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6555{
3ab66e8a 6556 __vmx_complete_interrupts(vcpu,
b463a6f7
AK		 6557 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6558 VM_ENTRY_INSTRUCTION_LEN,
6559 VM_ENTRY_EXCEPTION_ERROR_CODE);
6560
6561 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6562}
6563
d7cd9796
GN		 6564static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6565{
6566 int i, nr_msrs;
6567 struct perf_guest_switch_msr *msrs;
6568
6569 msrs = perf_guest_get_msrs(&nr_msrs);
6570
6571 if (!msrs)
6572 return;
6573
6574 for (i = 0; i < nr_msrs; i++)
6575 if (msrs[i].host == msrs[i].guest)
6576 clear_atomic_switch_msr(vmx, msrs[i].msr);
6577 else
6578 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6579 msrs[i].host);
6580}
6581
a3b5ba49 6582static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 6583{
a2fa3e9f 6584 struct vcpu_vmx *vmx = to_vmx(vcpu);
2a7921b7 6585 unsigned long debugctlmsr;
104f226b
AK		 6586
6587 /* Record the guest's net vcpu time for enforced NMI injections. */
6588 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6589 vmx->entry_time = ktime_get();
6590
6591 /* Don't enter VMX if guest state is invalid, let the exit handler
6592 start emulation until we arrive back to a valid state */
14168786 6593 if (vmx->emulation_required)
104f226b
AK		 6594 return;
6595
6596 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6597 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6598 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6599 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6600
6601 /* When single-stepping over STI and MOV SS, we must clear the
6602 * corresponding interruptibility bits in the guest state. Otherwise
6603 * vmentry fails as it then expects bit 14 (BS) in pending debug
6604 * exceptions being set, but that's not correct for the guest debugging
6605 * case. */
6606 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6607 vmx_set_interrupt_shadow(vcpu, 0);
6608
d7cd9796 6609 atomic_switch_perf_msrs(vmx);
2a7921b7 6610 debugctlmsr = get_debugctlmsr();
d7cd9796 6611
d462b819 6612 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 6613 asm(
6aa8b732 6614 /* Store host registers */
b188c81f
AK		 6615 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6616 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6617 "push %%" _ASM_CX " \n\t"
6618 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
313dbd49 6619 "je 1f \n\t"
b188c81f 6620 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
4ecac3fd 6621 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 6622 "1: \n\t"
d3edefc0 6623 /* Reload cr2 if changed */
b188c81f
AK		 6624 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6625 "mov %%cr2, %%" _ASM_DX " \n\t"
6626 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
d3edefc0 6627 "je 2f \n\t"
b188c81f 6628 "mov %%" _ASM_AX", %%cr2 \n\t"
d3edefc0 6629 "2: \n\t"
6aa8b732 6630 /* Check if vmlaunch of vmresume is needed */
e08aa78a 6631 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 6632 /* Load guest registers. Don't clobber flags. */
b188c81f
AK		 6633 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6634 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6635 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6636 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6637 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6638 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
05b3e0c2 6639#ifdef CONFIG_X86_64
e08aa78a
AK		 6640 "mov %c[r8](%0), %%r8 \n\t"
6641 "mov %c[r9](%0), %%r9 \n\t"
6642 "mov %c[r10](%0), %%r10 \n\t"
6643 "mov %c[r11](%0), %%r11 \n\t"
6644 "mov %c[r12](%0), %%r12 \n\t"
6645 "mov %c[r13](%0), %%r13 \n\t"
6646 "mov %c[r14](%0), %%r14 \n\t"
6647 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6648#endif
b188c81f 6649 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
c801949d 6650
6aa8b732 6651 /* Enter guest mode */
83287ea4 6652 "jne 1f \n\t"
4ecac3fd 6653 __ex(ASM_VMX_VMLAUNCH) "\n\t"
83287ea4
AK		 6654 "jmp 2f \n\t"
6655 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6656 "2: "
6aa8b732 6657 /* Save guest registers, load host registers, keep flags */
b188c81f 6658 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
40712fae 6659 "pop %0 \n\t"
b188c81f
AK		 6660 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6661 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6662 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6663 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6664 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6665 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6666 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
05b3e0c2 6667#ifdef CONFIG_X86_64
e08aa78a
AK		 6668 "mov %%r8, %c[r8](%0) \n\t"
6669 "mov %%r9, %c[r9](%0) \n\t"
6670 "mov %%r10, %c[r10](%0) \n\t"
6671 "mov %%r11, %c[r11](%0) \n\t"
6672 "mov %%r12, %c[r12](%0) \n\t"
6673 "mov %%r13, %c[r13](%0) \n\t"
6674 "mov %%r14, %c[r14](%0) \n\t"
6675 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6676#endif
b188c81f
AK		 6677 "mov %%cr2, %%" _ASM_AX " \n\t"
6678 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
c801949d 6679
b188c81f 6680 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
e08aa78a 6681 "setbe %c[fail](%0) \n\t"
83287ea4
AK		 6682 ".pushsection .rodata \n\t"
6683 ".global vmx_return \n\t"
6684 "vmx_return: " _ASM_PTR " 2b \n\t"
6685 ".popsection"
e08aa78a 6686 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6687 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6688 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6689 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6690 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6691 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6692 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6693 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6694 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6695 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6696 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6697#ifdef CONFIG_X86_64
ad312c7c
ZX		 6698 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6699 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6700 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6701 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6702 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6703 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6704 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6705 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6706#endif
40712fae
AK		 6707 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6708 [wordsize]"i"(sizeof(ulong))
c2036300
LV		 6709 : "cc", "memory"
6710#ifdef CONFIG_X86_64
b188c81f 6711 , "rax", "rbx", "rdi", "rsi"
c2036300 6712 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
b188c81f
AK		 6713#else
6714 , "eax", "ebx", "edi", "esi"
c2036300
LV		 6715#endif
6716 );
6aa8b732 6717
2a7921b7
GN		 6718 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6719 if (debugctlmsr)
6720 update_debugctlmsr(debugctlmsr);
6721
aa67f609
AK		 6722#ifndef CONFIG_X86_64
6723 /*
6724 * The sysexit path does not restore ds/es, so we must set them to
6725 * a reasonable value ourselves.
6726 *
6727 * We can't defer this to vmx_load_host_state() since that function
6728 * may be executed in interrupt context, which saves and restore segments
6729 * around it, nullifying its effect.
6730 */
6731 loadsegment(ds, __USER_DS);
6732 loadsegment(es, __USER_DS);
6733#endif
6734
6de4f3ad 6735 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6736 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6737 | (1 << VCPU_EXREG_CPL)
aff48baa 6738 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6739 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6740 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6741 vcpu->arch.regs_dirty = 0;
6742
1155f76a
AK		 6743 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6744
d462b819 6745 vmx->loaded_vmcs->launched = 1;
1b6269db 6746
51aa01d1 6747 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
1e2b1dd7 6748 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
51aa01d1
AK		 6749
6750 vmx_complete_atomic_exit(vmx);
6751 vmx_recover_nmi_blocking(vmx);
cf393f75 6752 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6753}
6754
6aa8b732
AK		 6755static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6756{
fb3f0f51
RR		 6757 struct vcpu_vmx *vmx = to_vmx(vcpu);
6758
cdbecfc3 6759 free_vpid(vmx);
ec378aee 6760 free_nested(vmx);
d462b819 6761 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6762 kfree(vmx->guest_msrs);
6763 kvm_vcpu_uninit(vcpu);
a4770347 6764 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6765}
6766
fb3f0f51 6767static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6768{
fb3f0f51 6769 int err;
c16f862d 6770 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6771 int cpu;
6aa8b732 6772
a2fa3e9f 6773 if (!vmx)
fb3f0f51
RR		 6774 return ERR_PTR(-ENOMEM);
6775
2384d2b3
SY		 6776 allocate_vpid(vmx);
6777
fb3f0f51
RR		 6778 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6779 if (err)
6780 goto free_vcpu;
965b58a5 6781
a2fa3e9f 6782 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6783 err = -ENOMEM;
fb3f0f51 6784 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6785 goto uninit_vcpu;
6786 }
965b58a5 6787
d462b819
NHE		 6788 vmx->loaded_vmcs = &vmx->vmcs01;
6789 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6790 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6791 goto free_msrs;
d462b819
NHE		 6792 if (!vmm_exclusive)
6793 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6794 loaded_vmcs_init(vmx->loaded_vmcs);
6795 if (!vmm_exclusive)
6796 kvm_cpu_vmxoff();
a2fa3e9f 6797
15ad7146
AK		 6798 cpu = get_cpu();
6799 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6800 vmx->vcpu.cpu = cpu;
8b9cf98c 6801 err = vmx_vcpu_setup(vmx);
fb3f0f51 6802 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6803 put_cpu();
fb3f0f51
RR		 6804 if (err)
6805 goto free_vmcs;
a63cb560 6806 if (vm_need_virtualize_apic_accesses(kvm)) {
be6d05cf
JK		 6807 err = alloc_apic_access_page(kvm);
6808 if (err)
5e4a0b3c 6809 goto free_vmcs;
a63cb560 6810 }
fb3f0f51 6811
b927a3ce
SY		 6812 if (enable_ept) {
6813 if (!kvm->arch.ept_identity_map_addr)
6814 kvm->arch.ept_identity_map_addr =
6815 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6816 err = -ENOMEM;
b7ebfb05
SY		 6817 if (alloc_identity_pagetable(kvm) != 0)
6818 goto free_vmcs;
93ea5388
GN		 6819 if (!init_rmode_identity_map(kvm))
6820 goto free_vmcs;
b927a3ce 6821 }
b7ebfb05 6822
a9d30f33
NHE		 6823 vmx->nested.current_vmptr = -1ull;
6824 vmx->nested.current_vmcs12 = NULL;
6825
fb3f0f51
RR		 6826 return &vmx->vcpu;
6827
6828free_vmcs:
5f3fbc34 6829 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51 6830free_msrs:
fb3f0f51
RR		 6831 kfree(vmx->guest_msrs);
6832uninit_vcpu:
6833 kvm_vcpu_uninit(&vmx->vcpu);
6834free_vcpu:
cdbecfc3 6835 free_vpid(vmx);
a4770347 6836 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6837 return ERR_PTR(err);
6aa8b732
AK		 6838}
6839
002c7f7c
YS		 6840static void __init vmx_check_processor_compat(void *rtn)
6841{
6842 struct vmcs_config vmcs_conf;
6843
6844 *(int *)rtn = 0;
6845 if (setup_vmcs_config(&vmcs_conf) < 0)
6846 *(int *)rtn = -EIO;
6847 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6848 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6849 smp_processor_id());
6850 *(int *)rtn = -EIO;
6851 }
6852}
6853
67253af5
SY		 6854static int get_ept_level(void)
6855{
6856 return VMX_EPT_DEFAULT_GAW + 1;
6857}
6858
4b12f0de 6859static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6860{
4b12f0de
SY		 6861 u64 ret;
6862
522c68c4
SY		 6863 /* For VT-d and EPT combination
6864 * 1. MMIO: always map as UC
6865 * 2. EPT with VT-d:
6866 * a. VT-d without snooping control feature: can't guarantee the
6867 * result, try to trust guest.
6868 * b. VT-d with snooping control feature: snooping control feature of
6869 * VT-d engine can guarantee the cache correctness. Just set it
6870 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6871 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6872 * consistent with host MTRR
6873 */
4b12f0de
SY		 6874 if (is_mmio)
6875 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6876 else if (vcpu->kvm->arch.iommu_domain &&
6877 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6878 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6879 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6880 else
522c68c4 6881 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6882 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6883
6884 return ret;
64d4d521
SY		 6885}
6886
17cc3935 6887static int vmx_get_lpage_level(void)
344f414f 6888{
878403b7
SY		 6889 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6890 return PT_DIRECTORY_LEVEL;
6891 else
6892 /* For shadow and EPT supported 1GB page */
6893 return PT_PDPE_LEVEL;
344f414f
JR		 6894}
6895
0e851880
SY		 6896static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6897{
4e47c7a6
SY		 6898 struct kvm_cpuid_entry2 *best;
6899 struct vcpu_vmx *vmx = to_vmx(vcpu);
6900 u32 exec_control;
6901
6902 vmx->rdtscp_enabled = false;
6903 if (vmx_rdtscp_supported()) {
6904 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6905 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6906 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6907 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6908 vmx->rdtscp_enabled = true;
6909 else {
6910 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6911 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6912 exec_control);
6913 }
6914 }
6915 }
ad756a16 6916
ad756a16
MJ		 6917 /* Exposing INVPCID only when PCID is exposed */
6918 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6919 if (vmx_invpcid_supported() &&
4f977045 6920 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
ad756a16 6921 guest_cpuid_has_pcid(vcpu)) {
29282fde 6922 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
ad756a16
MJ		 6923 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6924 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6925 exec_control);
6926 } else {
29282fde
TI		 6927 if (cpu_has_secondary_exec_ctrls()) {
6928 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6929 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6930 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6931 exec_control);
6932 }
ad756a16 6933 if (best)
4f977045 6934 best->ebx &= ~bit(X86_FEATURE_INVPCID);
ad756a16 6935 }
0e851880
SY		 6936}
6937
d4330ef2
JR		 6938static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6939{
7b8050f5
NHE		 6940 if (func == 1 && nested)
6941 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6942}
6943
fe3ef05c
NHE		 6944/*
6945 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6946 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6947 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6948 * guest in a way that will both be appropriate to L1's requests, and our
6949 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6950 * function also has additional necessary side-effects, like setting various
6951 * vcpu->arch fields.
6952 */
6953static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6954{
6955 struct vcpu_vmx *vmx = to_vmx(vcpu);
6956 u32 exec_control;
6957
6958 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6959 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6960 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6961 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6962 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6963 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6964 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6965 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6966 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6967 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6968 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6969 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6970 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6971 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6972 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6973 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6974 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6975 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6976 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6977 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6978 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6979 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6980 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6981 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6982 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6983 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6984 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6985 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6986 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6987 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6988 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6989 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6990 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6991 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6992 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6993 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6994
6995 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6996 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6997 vmcs12->vm_entry_intr_info_field);
6998 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6999 vmcs12->vm_entry_exception_error_code);
7000 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
7001 vmcs12->vm_entry_instruction_len);
7002 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
7003 vmcs12->guest_interruptibility_info);
7004 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
7005 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
503cd0c5 7006 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
fe3ef05c
NHE		 7007 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
7008 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
7009 vmcs12->guest_pending_dbg_exceptions);
7010 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
7011 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
7012
7013 vmcs_write64(VMCS_LINK_POINTER, -1ull);
7014
7015 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
7016 (vmcs_config.pin_based_exec_ctrl |
7017 vmcs12->pin_based_vm_exec_control));
7018
0238ea91
JK		 7019 if (vmcs12->pin_based_vm_exec_control & PIN_BASED_VMX_PREEMPTION_TIMER)
7020 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE,
7021 vmcs12->vmx_preemption_timer_value);
7022
fe3ef05c
NHE		 7023 /*
7024 * Whether page-faults are trapped is determined by a combination of
7025 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7026 * If enable_ept, L0 doesn't care about page faults and we should
7027 * set all of these to L1's desires. However, if !enable_ept, L0 does
7028 * care about (at least some) page faults, and because it is not easy
7029 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7030 * to exit on each and every L2 page fault. This is done by setting
7031 * MASK=MATCH=0 and (see below) EB.PF=1.
7032 * Note that below we don't need special code to set EB.PF beyond the
7033 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7034 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7035 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7036 *
7037 * A problem with this approach (when !enable_ept) is that L1 may be
7038 * injected with more page faults than it asked for. This could have
7039 * caused problems, but in practice existing hypervisors don't care.
7040 * To fix this, we will need to emulate the PFEC checking (on the L1
7041 * page tables), using walk_addr(), when injecting PFs to L1.
7042 */
7043 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
7044 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
7045 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
7046 enable_ept ? vmcs12->page_fault_error_code_match : 0);
7047
7048 if (cpu_has_secondary_exec_ctrls()) {
7049 u32 exec_control = vmx_secondary_exec_control(vmx);
7050 if (!vmx->rdtscp_enabled)
7051 exec_control &= ~SECONDARY_EXEC_RDTSCP;
7052 /* Take the following fields only from vmcs12 */
7053 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7054 if (nested_cpu_has(vmcs12,
7055 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
7056 exec_control |= vmcs12->secondary_vm_exec_control;
7057
7058 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
7059 /*
7060 * Translate L1 physical address to host physical
7061 * address for vmcs02. Keep the page pinned, so this
7062 * physical address remains valid. We keep a reference
7063 * to it so we can release it later.
7064 */
7065 if (vmx->nested.apic_access_page) /* shouldn't happen */
7066 nested_release_page(vmx->nested.apic_access_page);
7067 vmx->nested.apic_access_page =
7068 nested_get_page(vcpu, vmcs12->apic_access_addr);
7069 /*
7070 * If translation failed, no matter: This feature asks
7071 * to exit when accessing the given address, and if it
7072 * can never be accessed, this feature won't do
7073 * anything anyway.
7074 */
7075 if (!vmx->nested.apic_access_page)
7076 exec_control &=
7077 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
7078 else
7079 vmcs_write64(APIC_ACCESS_ADDR,
7080 page_to_phys(vmx->nested.apic_access_page));
7081 }
7082
7083 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
7084 }
7085
7086
7087 /*
7088 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7089 * Some constant fields are set here by vmx_set_constant_host_state().
7090 * Other fields are different per CPU, and will be set later when
7091 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7092 */
a547c6db 7093 vmx_set_constant_host_state(vmx);
fe3ef05c
NHE		 7094
7095 /*
7096 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7097 * entry, but only if the current (host) sp changed from the value
7098 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7099 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7100 * here we just force the write to happen on entry.
7101 */
7102 vmx->host_rsp = 0;
7103
7104 exec_control = vmx_exec_control(vmx); /* L0's desires */
7105 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
7106 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
7107 exec_control &= ~CPU_BASED_TPR_SHADOW;
7108 exec_control |= vmcs12->cpu_based_vm_exec_control;
7109 /*
7110 * Merging of IO and MSR bitmaps not currently supported.
7111 * Rather, exit every time.
7112 */
7113 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
7114 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
7115 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
7116
7117 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
7118
7119 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7120 * bitwise-or of what L1 wants to trap for L2, and what we want to
7121 * trap. Note that CR0.TS also needs updating - we do this later.
7122 */
7123 update_exception_bitmap(vcpu);
7124 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
7125 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7126
7127 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7128 vmcs_write32(VM_EXIT_CONTROLS,
7129 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
7130 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
7131 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
7132
7133 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
7134 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
7135 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
7136 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
7137
7138
7139 set_cr4_guest_host_mask(vmx);
7140
27fc51b2
NHE		 7141 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
7142 vmcs_write64(TSC_OFFSET,
7143 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
7144 else
7145 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
fe3ef05c
NHE		 7146
7147 if (enable_vpid) {
7148 /*
7149 * Trivially support vpid by letting L2s share their parent
7150 * L1's vpid. TODO: move to a more elaborate solution, giving
7151 * each L2 its own vpid and exposing the vpid feature to L1.
7152 */
7153 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
7154 vmx_flush_tlb(vcpu);
7155 }
7156
7157 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
7158 vcpu->arch.efer = vmcs12->guest_ia32_efer;
7159 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
7160 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7161 else
7162 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7163 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7164 vmx_set_efer(vcpu, vcpu->arch.efer);
7165
7166 /*
7167 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7168 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7169 * The CR0_READ_SHADOW is what L2 should have expected to read given
7170 * the specifications by L1; It's not enough to take
7171 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7172 * have more bits than L1 expected.
7173 */
7174 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
7175 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
7176
7177 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
7178 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
7179
7180 /* shadow page tables on either EPT or shadow page tables */
7181 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
7182 kvm_mmu_reset_context(vcpu);
7183
7184 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
7185 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
7186}
7187
cd232ad0
NHE		 7188/*
7189 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7190 * for running an L2 nested guest.
7191 */
7192static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
7193{
7194 struct vmcs12 *vmcs12;
7195 struct vcpu_vmx *vmx = to_vmx(vcpu);
7196 int cpu;
7197 struct loaded_vmcs *vmcs02;
7198
7199 if (!nested_vmx_check_permission(vcpu) ||
7200 !nested_vmx_check_vmcs12(vcpu))
7201 return 1;
7202
7203 skip_emulated_instruction(vcpu);
7204 vmcs12 = get_vmcs12(vcpu);
7205
7c177938
NHE		 7206 /*
7207 * The nested entry process starts with enforcing various prerequisites
7208 * on vmcs12 as required by the Intel SDM, and act appropriately when
7209 * they fail: As the SDM explains, some conditions should cause the
7210 * instruction to fail, while others will cause the instruction to seem
7211 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7212 * To speed up the normal (success) code path, we should avoid checking
7213 * for misconfigurations which will anyway be caught by the processor
7214 * when using the merged vmcs02.
7215 */
7216 if (vmcs12->launch_state == launch) {
7217 nested_vmx_failValid(vcpu,
7218 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7219 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
7220 return 1;
7221 }
7222
7223 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
7224 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
7225 /*TODO: Also verify bits beyond physical address width are 0*/
7226 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7227 return 1;
7228 }
7229
7230 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
7231 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
7232 /*TODO: Also verify bits beyond physical address width are 0*/
7233 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7234 return 1;
7235 }
7236
7237 if (vmcs12->vm_entry_msr_load_count > 0 ||
7238 vmcs12->vm_exit_msr_load_count > 0 ||
7239 vmcs12->vm_exit_msr_store_count > 0) {
bd80158a
JK		 7240 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7241 __func__);
7c177938
NHE		 7242 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7243 return 1;
7244 }
7245
7246 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
7247 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
7248 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
7249 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
7250 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
7251 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
7252 !vmx_control_verify(vmcs12->vm_exit_controls,
7253 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
7254 !vmx_control_verify(vmcs12->vm_entry_controls,
7255 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
7256 {
7257 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
7258 return 1;
7259 }
7260
7261 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7262 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7263 nested_vmx_failValid(vcpu,
7264 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
7265 return 1;
7266 }
7267
7268 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
7269 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
7270 nested_vmx_entry_failure(vcpu, vmcs12,
7271 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
7272 return 1;
7273 }
7274 if (vmcs12->vmcs_link_pointer != -1ull) {
7275 nested_vmx_entry_failure(vcpu, vmcs12,
7276 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
7277 return 1;
7278 }
7279
7280 /*
7281 * We're finally done with prerequisite checking, and can start with
7282 * the nested entry.
7283 */
7284
cd232ad0
NHE		 7285 vmcs02 = nested_get_current_vmcs02(vmx);
7286 if (!vmcs02)
7287 return -ENOMEM;
7288
7289 enter_guest_mode(vcpu);
7290
7291 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
7292
7293 cpu = get_cpu();
7294 vmx->loaded_vmcs = vmcs02;
7295 vmx_vcpu_put(vcpu);
7296 vmx_vcpu_load(vcpu, cpu);
7297 vcpu->cpu = cpu;
7298 put_cpu();
7299
36c3cc42
JK		 7300 vmx_segment_cache_clear(vmx);
7301
cd232ad0
NHE		 7302 vmcs12->launch_state = 1;
7303
7304 prepare_vmcs02(vcpu, vmcs12);
7305
7306 /*
7307 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7308 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7309 * returned as far as L1 is concerned. It will only return (and set
7310 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7311 */
7312 return 1;
7313}
7314
4704d0be
NHE		 7315/*
7316 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7317 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7318 * This function returns the new value we should put in vmcs12.guest_cr0.
7319 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7320 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7321 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7322 * didn't trap the bit, because if L1 did, so would L0).
7323 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7324 * been modified by L2, and L1 knows it. So just leave the old value of
7325 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7326 * isn't relevant, because if L0 traps this bit it can set it to anything.
7327 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7328 * changed these bits, and therefore they need to be updated, but L0
7329 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7330 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7331 */
7332static inline unsigned long
7333vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7334{
7335 return
7336 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7337 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7338 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7339 vcpu->arch.cr0_guest_owned_bits));
7340}
7341
7342static inline unsigned long
7343vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7344{
7345 return
7346 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7347 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7348 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7349 vcpu->arch.cr4_guest_owned_bits));
7350}
7351
5f3d5799
JK		 7352static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
7353 struct vmcs12 *vmcs12)
7354{
7355 u32 idt_vectoring;
7356 unsigned int nr;
7357
7358 if (vcpu->arch.exception.pending) {
7359 nr = vcpu->arch.exception.nr;
7360 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7361
7362 if (kvm_exception_is_soft(nr)) {
7363 vmcs12->vm_exit_instruction_len =
7364 vcpu->arch.event_exit_inst_len;
7365 idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
7366 } else
7367 idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
7368
7369 if (vcpu->arch.exception.has_error_code) {
7370 idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
7371 vmcs12->idt_vectoring_error_code =
7372 vcpu->arch.exception.error_code;
7373 }
7374
7375 vmcs12->idt_vectoring_info_field = idt_vectoring;
7376 } else if (vcpu->arch.nmi_pending) {
7377 vmcs12->idt_vectoring_info_field =
7378 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
7379 } else if (vcpu->arch.interrupt.pending) {
7380 nr = vcpu->arch.interrupt.nr;
7381 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
7382
7383 if (vcpu->arch.interrupt.soft) {
7384 idt_vectoring |= INTR_TYPE_SOFT_INTR;
7385 vmcs12->vm_entry_instruction_len =
7386 vcpu->arch.event_exit_inst_len;
7387 } else
7388 idt_vectoring |= INTR_TYPE_EXT_INTR;
7389
7390 vmcs12->idt_vectoring_info_field = idt_vectoring;
7391 }
7392}
7393
4704d0be
NHE		 7394/*
7395 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7396 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7397 * and this function updates it to reflect the changes to the guest state while
7398 * L2 was running (and perhaps made some exits which were handled directly by L0
7399 * without going back to L1), and to reflect the exit reason.
7400 * Note that we do not have to copy here all VMCS fields, just those that
7401 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7402 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7403 * which already writes to vmcs12 directly.
7404 */
733568f9 7405static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
4704d0be
NHE		 7406{
7407 /* update guest state fields: */
7408 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7409 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7410
7411 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7412 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7413 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7414 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7415
7416 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7417 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7418 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7419 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7420 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7421 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7422 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7423 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7424 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7425 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7426 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7427 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7428 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7429 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7430 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7431 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7432 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7433 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7434 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7435 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7436 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7437 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7438 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7439 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7440 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7441 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7442 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7443 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7444 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7445 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7446 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7447 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7448 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7449 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7450 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7451 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7452
7453 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7454 vmcs12->guest_interruptibility_info =
7455 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7456 vmcs12->guest_pending_dbg_exceptions =
7457 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7458
c18911a2
JK		 7459 vmcs12->vm_entry_controls =
7460 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
7461 (vmcs_read32(VM_ENTRY_CONTROLS) & VM_ENTRY_IA32E_MODE);
7462
4704d0be
NHE		 7463 /* TODO: These cannot have changed unless we have MSR bitmaps and
7464 * the relevant bit asks not to trap the change */
7465 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
b8c07d55 7466 if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
4704d0be
NHE		 7467 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7468 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7469 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7470 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7471
7472 /* update exit information fields: */
7473
957c897e 7474 vmcs12->vm_exit_reason = to_vmx(vcpu)->exit_reason;
4704d0be
NHE		 7475 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7476
7477 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
c0d1c770
JK		 7478 if ((vmcs12->vm_exit_intr_info &
7479 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
7480 (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
7481 vmcs12->vm_exit_intr_error_code =
7482 vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5f3d5799 7483 vmcs12->idt_vectoring_info_field = 0;
4704d0be
NHE		 7484 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7485 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7486
5f3d5799
JK		 7487 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
7488 /* vm_entry_intr_info_field is cleared on exit. Emulate this
7489 * instead of reading the real value. */
4704d0be 7490 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
5f3d5799
JK		 7491
7492 /*
7493 * Transfer the event that L0 or L1 may wanted to inject into
7494 * L2 to IDT_VECTORING_INFO_FIELD.
7495 */
7496 vmcs12_save_pending_event(vcpu, vmcs12);
7497 }
7498
7499 /*
7500 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
7501 * preserved above and would only end up incorrectly in L1.
7502 */
7503 vcpu->arch.nmi_injected = false;
7504 kvm_clear_exception_queue(vcpu);
7505 kvm_clear_interrupt_queue(vcpu);
4704d0be
NHE		 7506}
7507
7508/*
7509 * A part of what we need to when the nested L2 guest exits and we want to
7510 * run its L1 parent, is to reset L1's guest state to the host state specified
7511 * in vmcs12.
7512 * This function is to be called not only on normal nested exit, but also on
7513 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7514 * Failures During or After Loading Guest State").
7515 * This function should be called when the active VMCS is L1's (vmcs01).
7516 */
733568f9
JK		 7517static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
7518 struct vmcs12 *vmcs12)
4704d0be
NHE		 7519{
7520 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7521 vcpu->arch.efer = vmcs12->host_ia32_efer;
7522 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7523 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7524 else
7525 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7526 vmx_set_efer(vcpu, vcpu->arch.efer);
7527
7528 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7529 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
c4627c72 7530 vmx_set_rflags(vcpu, X86_EFLAGS_BIT1);
4704d0be
NHE		 7531 /*
7532 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7533 * actually changed, because it depends on the current state of
7534 * fpu_active (which may have changed).
7535 * Note that vmx_set_cr0 refers to efer set above.
7536 */
7537 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7538 /*
7539 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7540 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7541 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7542 */
7543 update_exception_bitmap(vcpu);
7544 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7545 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7546
7547 /*
7548 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7549 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7550 */
7551 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7552 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7553
7554 /* shadow page tables on either EPT or shadow page tables */
7555 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7556 kvm_mmu_reset_context(vcpu);
7557
7558 if (enable_vpid) {
7559 /*
7560 * Trivially support vpid by letting L2s share their parent
7561 * L1's vpid. TODO: move to a more elaborate solution, giving
7562 * each L2 its own vpid and exposing the vpid feature to L1.
7563 */
7564 vmx_flush_tlb(vcpu);
7565 }
7566
7567
7568 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7569 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7570 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7571 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7572 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7573 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7574 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7575 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7576 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7577 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7578 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7579 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7580 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7581 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7582 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7583
7584 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7585 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7586 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7587 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7588 vmcs12->host_ia32_perf_global_ctrl);
503cd0c5
JK		 7589
7590 kvm_set_dr(vcpu, 7, 0x400);
7591 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4704d0be
NHE		 7592}
7593
7594/*
7595 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7596 * and modify vmcs12 to make it see what it would expect to see there if
7597 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7598 */
7599static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7600{
7601 struct vcpu_vmx *vmx = to_vmx(vcpu);
7602 int cpu;
7603 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7604
5f3d5799
JK		 7605 /* trying to cancel vmlaunch/vmresume is a bug */
7606 WARN_ON_ONCE(vmx->nested.nested_run_pending);
7607
4704d0be
NHE		 7608 leave_guest_mode(vcpu);
7609 prepare_vmcs12(vcpu, vmcs12);
7610
7611 cpu = get_cpu();
7612 vmx->loaded_vmcs = &vmx->vmcs01;
7613 vmx_vcpu_put(vcpu);
7614 vmx_vcpu_load(vcpu, cpu);
7615 vcpu->cpu = cpu;
7616 put_cpu();
7617
36c3cc42
JK		 7618 vmx_segment_cache_clear(vmx);
7619
4704d0be
NHE		 7620 /* if no vmcs02 cache requested, remove the one we used */
7621 if (VMCS02_POOL_SIZE == 0)
7622 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7623
7624 load_vmcs12_host_state(vcpu, vmcs12);
7625
27fc51b2 7626 /* Update TSC_OFFSET if TSC was changed while L2 ran */
4704d0be
NHE		 7627 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7628
7629 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7630 vmx->host_rsp = 0;
7631
7632 /* Unpin physical memory we referred to in vmcs02 */
7633 if (vmx->nested.apic_access_page) {
7634 nested_release_page(vmx->nested.apic_access_page);
7635 vmx->nested.apic_access_page = 0;
7636 }
7637
7638 /*
7639 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7640 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7641 * success or failure flag accordingly.
7642 */
7643 if (unlikely(vmx->fail)) {
7644 vmx->fail = 0;
7645 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7646 } else
7647 nested_vmx_succeed(vcpu);
7648}
7649
7c177938
NHE		 7650/*
7651 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7652 * 23.7 "VM-entry failures during or after loading guest state" (this also
7653 * lists the acceptable exit-reason and exit-qualification parameters).
7654 * It should only be called before L2 actually succeeded to run, and when
7655 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7656 */
7657static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7658 struct vmcs12 *vmcs12,
7659 u32 reason, unsigned long qualification)
7660{
7661 load_vmcs12_host_state(vcpu, vmcs12);
7662 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7663 vmcs12->exit_qualification = qualification;
7664 nested_vmx_succeed(vcpu);
7665}
7666
8a76d7f2
JR		 7667static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7668 struct x86_instruction_info *info,
7669 enum x86_intercept_stage stage)
7670{
7671 return X86EMUL_CONTINUE;
7672}
7673
cbdd1bea 7674static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 7675 .cpu_has_kvm_support = cpu_has_kvm_support,
7676 .disabled_by_bios = vmx_disabled_by_bios,
7677 .hardware_setup = hardware_setup,
7678 .hardware_unsetup = hardware_unsetup,
002c7f7c 7679 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7680 .hardware_enable = hardware_enable,
7681 .hardware_disable = hardware_disable,
04547156 7682 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 7683
7684 .vcpu_create = vmx_create_vcpu,
7685 .vcpu_free = vmx_free_vcpu,
04d2cc77 7686 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7687
04d2cc77 7688 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 7689 .vcpu_load = vmx_vcpu_load,
7690 .vcpu_put = vmx_vcpu_put,
7691
c8639010 7692 .update_db_bp_intercept = update_exception_bitmap,
6aa8b732
AK		 7693 .get_msr = vmx_get_msr,
7694 .set_msr = vmx_set_msr,
7695 .get_segment_base = vmx_get_segment_base,
7696 .get_segment = vmx_get_segment,
7697 .set_segment = vmx_set_segment,
2e4d2653 7698 .get_cpl = vmx_get_cpl,
6aa8b732 7699 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7700 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7701 .decache_cr3 = vmx_decache_cr3,
25c4c276 7702 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7703 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7704 .set_cr3 = vmx_set_cr3,
7705 .set_cr4 = vmx_set_cr4,
6aa8b732 7706 .set_efer = vmx_set_efer,
6aa8b732
AK		 7707 .get_idt = vmx_get_idt,
7708 .set_idt = vmx_set_idt,
7709 .get_gdt = vmx_get_gdt,
7710 .set_gdt = vmx_set_gdt,
020df079 7711 .set_dr7 = vmx_set_dr7,
5fdbf976 7712 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7713 .get_rflags = vmx_get_rflags,
7714 .set_rflags = vmx_set_rflags,
ebcbab4c 7715 .fpu_activate = vmx_fpu_activate,
02daab21 7716 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 7717
7718 .tlb_flush = vmx_flush_tlb,
6aa8b732 7719
6aa8b732 7720 .run = vmx_vcpu_run,
6062d012 7721 .handle_exit = vmx_handle_exit,
6aa8b732 7722 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7723 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7724 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7725 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7726 .set_irq = vmx_inject_irq,
95ba8273 7727 .set_nmi = vmx_inject_nmi,
298101da 7728 .queue_exception = vmx_queue_exception,
b463a6f7 7729 .cancel_injection = vmx_cancel_injection,
78646121 7730 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7731 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7732 .get_nmi_mask = vmx_get_nmi_mask,
7733 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7734 .enable_nmi_window = enable_nmi_window,
7735 .enable_irq_window = enable_irq_window,
7736 .update_cr8_intercept = update_cr8_intercept,
8d14695f 7737 .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
c7c9c56c
YZ		 7738 .vm_has_apicv = vmx_vm_has_apicv,
7739 .load_eoi_exitmap = vmx_load_eoi_exitmap,
7740 .hwapic_irr_update = vmx_hwapic_irr_update,
7741 .hwapic_isr_update = vmx_hwapic_isr_update,
95ba8273 7742
cbc94022 7743 .set_tss_addr = vmx_set_tss_addr,
67253af5 7744 .get_tdp_level = get_ept_level,
4b12f0de 7745 .get_mt_mask = vmx_get_mt_mask,
229456fc 7746
586f9607 7747 .get_exit_info = vmx_get_exit_info,
586f9607 7748
17cc3935 7749 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7750
7751 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7752
7753 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7754 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7755
7756 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7757
7758 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7759
4051b188 7760 .set_tsc_khz = vmx_set_tsc_khz,
ba904635 7761 .read_tsc_offset = vmx_read_tsc_offset,
99e3e30a 7762 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7763 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7764 .compute_tsc_offset = vmx_compute_tsc_offset,
d5c1785d 7765 .read_l1_tsc = vmx_read_l1_tsc,
1c97f0a0
JR		 7766
7767 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7768
7769 .check_intercept = vmx_check_intercept,
a547c6db 7770 .handle_external_intr = vmx_handle_external_intr,
6aa8b732
AK		 7771};
7772
7773static int __init vmx_init(void)
7774{
8d14695f 7775 int r, i, msr;
26bb0981
AK		 7776
7777 rdmsrl_safe(MSR_EFER, &host_efer);
7778
7779 for (i = 0; i < NR_VMX_MSR; ++i)
7780 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7781
3e7c73e9 7782 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7783 if (!vmx_io_bitmap_a)
7784 return -ENOMEM;
7785
2106a548
GC		 7786 r = -ENOMEM;
7787
3e7c73e9 7788 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7789 if (!vmx_io_bitmap_b)
fdef3ad1 7790 goto out;
fdef3ad1 7791
5897297b 7792 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7793 if (!vmx_msr_bitmap_legacy)
25c5f225 7794 goto out1;
2106a548 7795
8d14695f
YZ		 7796 vmx_msr_bitmap_legacy_x2apic =
7797 (unsigned long *)__get_free_page(GFP_KERNEL);
7798 if (!vmx_msr_bitmap_legacy_x2apic)
7799 goto out2;
25c5f225 7800
5897297b 7801 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
2106a548 7802 if (!vmx_msr_bitmap_longmode)
8d14695f 7803 goto out3;
2106a548 7804
8d14695f
YZ		 7805 vmx_msr_bitmap_longmode_x2apic =
7806 (unsigned long *)__get_free_page(GFP_KERNEL);
7807 if (!vmx_msr_bitmap_longmode_x2apic)
7808 goto out4;
5897297b 7809
fdef3ad1
HQ		 7810 /*
7811 * Allow direct access to the PC debug port (it is often used for I/O
7812 * delays, but the vmexits simply slow things down).
7813 */
3e7c73e9
AK		 7814 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7815 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7816
3e7c73e9 7817 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7818
5897297b
AK		 7819 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7820 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7821
2384d2b3
SY		 7822 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7823
0ee75bea
AK		 7824 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7825 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7826 if (r)
458f212e 7827 goto out5;
25c5f225 7828
8f536b76
ZY		 7829#ifdef CONFIG_KEXEC
7830 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7831 crash_vmclear_local_loaded_vmcss);
7832#endif
7833
5897297b
AK		 7834 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7835 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7836 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7837 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7838 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7839 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
8d14695f
YZ		 7840 memcpy(vmx_msr_bitmap_legacy_x2apic,
7841 vmx_msr_bitmap_legacy, PAGE_SIZE);
7842 memcpy(vmx_msr_bitmap_longmode_x2apic,
7843 vmx_msr_bitmap_longmode, PAGE_SIZE);
7844
c7c9c56c 7845 if (enable_apicv_reg_vid) {
8d14695f
YZ		 7846 for (msr = 0x800; msr <= 0x8ff; msr++)
7847 vmx_disable_intercept_msr_read_x2apic(msr);
7848
7849 /* According SDM, in x2apic mode, the whole id reg is used.
7850 * But in KVM, it only use the highest eight bits. Need to
7851 * intercept it */
7852 vmx_enable_intercept_msr_read_x2apic(0x802);
7853 /* TMCCT */
7854 vmx_enable_intercept_msr_read_x2apic(0x839);
7855 /* TPR */
7856 vmx_disable_intercept_msr_write_x2apic(0x808);
c7c9c56c
YZ		 7857 /* EOI */
7858 vmx_disable_intercept_msr_write_x2apic(0x80b);
7859 /* SELF-IPI */
7860 vmx_disable_intercept_msr_write_x2apic(0x83f);
8d14695f 7861 }
fdef3ad1 7862
089d034e 7863 if (enable_ept) {
3f6d8c8a
XH		 7864 kvm_mmu_set_mask_ptes(0ull,
7865 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7866 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7867 0ull, VMX_EPT_EXECUTABLE_MASK);
ce88decf 7868 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7869 kvm_enable_tdp();
7870 } else
7871 kvm_disable_tdp();
1439442c 7872
fdef3ad1
HQ		 7873 return 0;
7874
458f212e
YZ		 7875out5:
7876 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
8d14695f 7877out4:
5897297b 7878 free_page((unsigned long)vmx_msr_bitmap_longmode);
8d14695f
YZ		 7879out3:
7880 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
25c5f225 7881out2:
5897297b 7882 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7883out1:
3e7c73e9 7884 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7885out:
3e7c73e9 7886 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7887 return r;
6aa8b732
AK		 7888}
7889
7890static void __exit vmx_exit(void)
7891{
8d14695f
YZ		 7892 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
7893 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
5897297b
AK		 7894 free_page((unsigned long)vmx_msr_bitmap_legacy);
7895 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7896 free_page((unsigned long)vmx_io_bitmap_b);
7897 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7898
8f536b76
ZY		 7899#ifdef CONFIG_KEXEC
7900 rcu_assign_pointer(crash_vmclear_loaded_vmcss, NULL);
7901 synchronize_rcu();
7902#endif
7903
cb498ea2 7904 kvm_exit();
6aa8b732
AK		 7905}
7906
7907module_init(vmx_init)
7908module_exit(vmx_exit)
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