]>
Commit | Line | Data |
---|---|---|
6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * Copyright (C) 2006 Qumranet, Inc. | |
8 | * | |
9 | * Authors: | |
10 | * Avi Kivity <avi@qumranet.com> | |
11 | * Yaniv Kamay <yaniv@qumranet.com> | |
12 | * | |
13 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
14 | * the COPYING file in the top-level directory. | |
15 | * | |
16 | */ | |
17 | ||
85f455f7 | 18 | #include "irq.h" |
6aa8b732 | 19 | #include "vmx.h" |
1d737c8a | 20 | #include "mmu.h" |
e495606d | 21 | |
edf88417 | 22 | #include <linux/kvm_host.h> |
6aa8b732 | 23 | #include <linux/module.h> |
9d8f549d | 24 | #include <linux/kernel.h> |
6aa8b732 AK |
25 | #include <linux/mm.h> |
26 | #include <linux/highmem.h> | |
e8edc6e0 | 27 | #include <linux/sched.h> |
c7addb90 | 28 | #include <linux/moduleparam.h> |
5fdbf976 | 29 | #include "kvm_cache_regs.h" |
35920a35 | 30 | #include "x86.h" |
e495606d | 31 | |
6aa8b732 | 32 | #include <asm/io.h> |
3b3be0d1 | 33 | #include <asm/desc.h> |
6aa8b732 | 34 | |
4ecac3fd AK |
35 | #define __ex(x) __kvm_handle_fault_on_reboot(x) |
36 | ||
6aa8b732 AK |
37 | MODULE_AUTHOR("Qumranet"); |
38 | MODULE_LICENSE("GPL"); | |
39 | ||
c7addb90 AK |
40 | static int bypass_guest_pf = 1; |
41 | module_param(bypass_guest_pf, bool, 0); | |
42 | ||
2384d2b3 SY |
43 | static int enable_vpid = 1; |
44 | module_param(enable_vpid, bool, 0); | |
45 | ||
4c9fc8ef AK |
46 | static int flexpriority_enabled = 1; |
47 | module_param(flexpriority_enabled, bool, 0); | |
48 | ||
1439442c | 49 | static int enable_ept = 1; |
d56f546d SY |
50 | module_param(enable_ept, bool, 0); |
51 | ||
a2fa3e9f GH |
52 | struct vmcs { |
53 | u32 revision_id; | |
54 | u32 abort; | |
55 | char data[0]; | |
56 | }; | |
57 | ||
58 | struct vcpu_vmx { | |
fb3f0f51 | 59 | struct kvm_vcpu vcpu; |
543e4243 | 60 | struct list_head local_vcpus_link; |
313dbd49 | 61 | unsigned long host_rsp; |
a2fa3e9f | 62 | int launched; |
29bd8a78 | 63 | u8 fail; |
1155f76a | 64 | u32 idt_vectoring_info; |
a2fa3e9f GH |
65 | struct kvm_msr_entry *guest_msrs; |
66 | struct kvm_msr_entry *host_msrs; | |
67 | int nmsrs; | |
68 | int save_nmsrs; | |
69 | int msr_offset_efer; | |
70 | #ifdef CONFIG_X86_64 | |
71 | int msr_offset_kernel_gs_base; | |
72 | #endif | |
73 | struct vmcs *vmcs; | |
74 | struct { | |
75 | int loaded; | |
76 | u16 fs_sel, gs_sel, ldt_sel; | |
152d3f2f LV |
77 | int gs_ldt_reload_needed; |
78 | int fs_reload_needed; | |
51c6cf66 | 79 | int guest_efer_loaded; |
d77c26fc | 80 | } host_state; |
9c8cba37 AK |
81 | struct { |
82 | struct { | |
83 | bool pending; | |
84 | u8 vector; | |
85 | unsigned rip; | |
86 | } irq; | |
87 | } rmode; | |
2384d2b3 | 88 | int vpid; |
a2fa3e9f GH |
89 | }; |
90 | ||
91 | static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu) | |
92 | { | |
fb3f0f51 | 93 | return container_of(vcpu, struct vcpu_vmx, vcpu); |
a2fa3e9f GH |
94 | } |
95 | ||
b7ebfb05 | 96 | static int init_rmode(struct kvm *kvm); |
4e1096d2 | 97 | static u64 construct_eptp(unsigned long root_hpa); |
75880a01 | 98 | |
6aa8b732 AK |
99 | static DEFINE_PER_CPU(struct vmcs *, vmxarea); |
100 | static DEFINE_PER_CPU(struct vmcs *, current_vmcs); | |
543e4243 | 101 | static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu); |
6aa8b732 | 102 | |
fdef3ad1 HQ |
103 | static struct page *vmx_io_bitmap_a; |
104 | static struct page *vmx_io_bitmap_b; | |
25c5f225 | 105 | static struct page *vmx_msr_bitmap; |
fdef3ad1 | 106 | |
2384d2b3 SY |
107 | static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); |
108 | static DEFINE_SPINLOCK(vmx_vpid_lock); | |
109 | ||
1c3d14fe | 110 | static struct vmcs_config { |
6aa8b732 AK |
111 | int size; |
112 | int order; | |
113 | u32 revision_id; | |
1c3d14fe YS |
114 | u32 pin_based_exec_ctrl; |
115 | u32 cpu_based_exec_ctrl; | |
f78e0e2e | 116 | u32 cpu_based_2nd_exec_ctrl; |
1c3d14fe YS |
117 | u32 vmexit_ctrl; |
118 | u32 vmentry_ctrl; | |
119 | } vmcs_config; | |
6aa8b732 | 120 | |
d56f546d SY |
121 | struct vmx_capability { |
122 | u32 ept; | |
123 | u32 vpid; | |
124 | } vmx_capability; | |
125 | ||
6aa8b732 AK |
126 | #define VMX_SEGMENT_FIELD(seg) \ |
127 | [VCPU_SREG_##seg] = { \ | |
128 | .selector = GUEST_##seg##_SELECTOR, \ | |
129 | .base = GUEST_##seg##_BASE, \ | |
130 | .limit = GUEST_##seg##_LIMIT, \ | |
131 | .ar_bytes = GUEST_##seg##_AR_BYTES, \ | |
132 | } | |
133 | ||
134 | static struct kvm_vmx_segment_field { | |
135 | unsigned selector; | |
136 | unsigned base; | |
137 | unsigned limit; | |
138 | unsigned ar_bytes; | |
139 | } kvm_vmx_segment_fields[] = { | |
140 | VMX_SEGMENT_FIELD(CS), | |
141 | VMX_SEGMENT_FIELD(DS), | |
142 | VMX_SEGMENT_FIELD(ES), | |
143 | VMX_SEGMENT_FIELD(FS), | |
144 | VMX_SEGMENT_FIELD(GS), | |
145 | VMX_SEGMENT_FIELD(SS), | |
146 | VMX_SEGMENT_FIELD(TR), | |
147 | VMX_SEGMENT_FIELD(LDTR), | |
148 | }; | |
149 | ||
4d56c8a7 AK |
150 | /* |
151 | * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it | |
152 | * away by decrementing the array size. | |
153 | */ | |
6aa8b732 | 154 | static const u32 vmx_msr_index[] = { |
05b3e0c2 | 155 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
156 | MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE, |
157 | #endif | |
158 | MSR_EFER, MSR_K6_STAR, | |
159 | }; | |
9d8f549d | 160 | #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index) |
6aa8b732 | 161 | |
a2fa3e9f GH |
162 | static void load_msrs(struct kvm_msr_entry *e, int n) |
163 | { | |
164 | int i; | |
165 | ||
166 | for (i = 0; i < n; ++i) | |
167 | wrmsrl(e[i].index, e[i].data); | |
168 | } | |
169 | ||
170 | static void save_msrs(struct kvm_msr_entry *e, int n) | |
171 | { | |
172 | int i; | |
173 | ||
174 | for (i = 0; i < n; ++i) | |
175 | rdmsrl(e[i].index, e[i].data); | |
176 | } | |
177 | ||
6aa8b732 AK |
178 | static inline int is_page_fault(u32 intr_info) |
179 | { | |
180 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
181 | INTR_INFO_VALID_MASK)) == | |
182 | (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK); | |
183 | } | |
184 | ||
2ab455cc AL |
185 | static inline int is_no_device(u32 intr_info) |
186 | { | |
187 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
188 | INTR_INFO_VALID_MASK)) == | |
189 | (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK); | |
190 | } | |
191 | ||
7aa81cc0 AL |
192 | static inline int is_invalid_opcode(u32 intr_info) |
193 | { | |
194 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK | | |
195 | INTR_INFO_VALID_MASK)) == | |
196 | (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK); | |
197 | } | |
198 | ||
6aa8b732 AK |
199 | static inline int is_external_interrupt(u32 intr_info) |
200 | { | |
201 | return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK)) | |
202 | == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
203 | } | |
204 | ||
25c5f225 SY |
205 | static inline int cpu_has_vmx_msr_bitmap(void) |
206 | { | |
207 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS); | |
208 | } | |
209 | ||
6e5d865c YS |
210 | static inline int cpu_has_vmx_tpr_shadow(void) |
211 | { | |
212 | return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW); | |
213 | } | |
214 | ||
215 | static inline int vm_need_tpr_shadow(struct kvm *kvm) | |
216 | { | |
217 | return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm))); | |
218 | } | |
219 | ||
f78e0e2e SY |
220 | static inline int cpu_has_secondary_exec_ctrls(void) |
221 | { | |
222 | return (vmcs_config.cpu_based_exec_ctrl & | |
223 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); | |
224 | } | |
225 | ||
774ead3a | 226 | static inline bool cpu_has_vmx_virtualize_apic_accesses(void) |
f78e0e2e | 227 | { |
4c9fc8ef AK |
228 | return flexpriority_enabled |
229 | && (vmcs_config.cpu_based_2nd_exec_ctrl & | |
230 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES); | |
f78e0e2e SY |
231 | } |
232 | ||
d56f546d SY |
233 | static inline int cpu_has_vmx_invept_individual_addr(void) |
234 | { | |
235 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT)); | |
236 | } | |
237 | ||
238 | static inline int cpu_has_vmx_invept_context(void) | |
239 | { | |
240 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT)); | |
241 | } | |
242 | ||
243 | static inline int cpu_has_vmx_invept_global(void) | |
244 | { | |
245 | return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT)); | |
246 | } | |
247 | ||
248 | static inline int cpu_has_vmx_ept(void) | |
249 | { | |
250 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
251 | SECONDARY_EXEC_ENABLE_EPT); | |
252 | } | |
253 | ||
254 | static inline int vm_need_ept(void) | |
255 | { | |
256 | return (cpu_has_vmx_ept() && enable_ept); | |
257 | } | |
258 | ||
f78e0e2e SY |
259 | static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm) |
260 | { | |
261 | return ((cpu_has_vmx_virtualize_apic_accesses()) && | |
262 | (irqchip_in_kernel(kvm))); | |
263 | } | |
264 | ||
2384d2b3 SY |
265 | static inline int cpu_has_vmx_vpid(void) |
266 | { | |
267 | return (vmcs_config.cpu_based_2nd_exec_ctrl & | |
268 | SECONDARY_EXEC_ENABLE_VPID); | |
269 | } | |
270 | ||
f08864b4 SY |
271 | static inline int cpu_has_virtual_nmis(void) |
272 | { | |
273 | return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS; | |
274 | } | |
275 | ||
8b9cf98c | 276 | static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) |
7725f0ba AK |
277 | { |
278 | int i; | |
279 | ||
a2fa3e9f GH |
280 | for (i = 0; i < vmx->nmsrs; ++i) |
281 | if (vmx->guest_msrs[i].index == msr) | |
a75beee6 ED |
282 | return i; |
283 | return -1; | |
284 | } | |
285 | ||
2384d2b3 SY |
286 | static inline void __invvpid(int ext, u16 vpid, gva_t gva) |
287 | { | |
288 | struct { | |
289 | u64 vpid : 16; | |
290 | u64 rsvd : 48; | |
291 | u64 gva; | |
292 | } operand = { vpid, 0, gva }; | |
293 | ||
4ecac3fd | 294 | asm volatile (__ex(ASM_VMX_INVVPID) |
2384d2b3 SY |
295 | /* CF==1 or ZF==1 --> rc = -1 */ |
296 | "; ja 1f ; ud2 ; 1:" | |
297 | : : "a"(&operand), "c"(ext) : "cc", "memory"); | |
298 | } | |
299 | ||
1439442c SY |
300 | static inline void __invept(int ext, u64 eptp, gpa_t gpa) |
301 | { | |
302 | struct { | |
303 | u64 eptp, gpa; | |
304 | } operand = {eptp, gpa}; | |
305 | ||
4ecac3fd | 306 | asm volatile (__ex(ASM_VMX_INVEPT) |
1439442c SY |
307 | /* CF==1 or ZF==1 --> rc = -1 */ |
308 | "; ja 1f ; ud2 ; 1:\n" | |
309 | : : "a" (&operand), "c" (ext) : "cc", "memory"); | |
310 | } | |
311 | ||
8b9cf98c | 312 | static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) |
a75beee6 ED |
313 | { |
314 | int i; | |
315 | ||
8b9cf98c | 316 | i = __find_msr_index(vmx, msr); |
a75beee6 | 317 | if (i >= 0) |
a2fa3e9f | 318 | return &vmx->guest_msrs[i]; |
8b6d44c7 | 319 | return NULL; |
7725f0ba AK |
320 | } |
321 | ||
6aa8b732 AK |
322 | static void vmcs_clear(struct vmcs *vmcs) |
323 | { | |
324 | u64 phys_addr = __pa(vmcs); | |
325 | u8 error; | |
326 | ||
4ecac3fd | 327 | asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0" |
6aa8b732 AK |
328 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
329 | : "cc", "memory"); | |
330 | if (error) | |
331 | printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n", | |
332 | vmcs, phys_addr); | |
333 | } | |
334 | ||
335 | static void __vcpu_clear(void *arg) | |
336 | { | |
8b9cf98c | 337 | struct vcpu_vmx *vmx = arg; |
d3b2c338 | 338 | int cpu = raw_smp_processor_id(); |
6aa8b732 | 339 | |
8b9cf98c | 340 | if (vmx->vcpu.cpu == cpu) |
a2fa3e9f GH |
341 | vmcs_clear(vmx->vmcs); |
342 | if (per_cpu(current_vmcs, cpu) == vmx->vmcs) | |
6aa8b732 | 343 | per_cpu(current_vmcs, cpu) = NULL; |
ad312c7c | 344 | rdtscll(vmx->vcpu.arch.host_tsc); |
543e4243 AK |
345 | list_del(&vmx->local_vcpus_link); |
346 | vmx->vcpu.cpu = -1; | |
347 | vmx->launched = 0; | |
6aa8b732 AK |
348 | } |
349 | ||
8b9cf98c | 350 | static void vcpu_clear(struct vcpu_vmx *vmx) |
8d0be2b3 | 351 | { |
eae5ecb5 AK |
352 | if (vmx->vcpu.cpu == -1) |
353 | return; | |
8691e5a8 | 354 | smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1); |
8d0be2b3 AK |
355 | } |
356 | ||
2384d2b3 SY |
357 | static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx) |
358 | { | |
359 | if (vmx->vpid == 0) | |
360 | return; | |
361 | ||
362 | __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0); | |
363 | } | |
364 | ||
1439442c SY |
365 | static inline void ept_sync_global(void) |
366 | { | |
367 | if (cpu_has_vmx_invept_global()) | |
368 | __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0); | |
369 | } | |
370 | ||
371 | static inline void ept_sync_context(u64 eptp) | |
372 | { | |
373 | if (vm_need_ept()) { | |
374 | if (cpu_has_vmx_invept_context()) | |
375 | __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0); | |
376 | else | |
377 | ept_sync_global(); | |
378 | } | |
379 | } | |
380 | ||
381 | static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa) | |
382 | { | |
383 | if (vm_need_ept()) { | |
384 | if (cpu_has_vmx_invept_individual_addr()) | |
385 | __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR, | |
386 | eptp, gpa); | |
387 | else | |
388 | ept_sync_context(eptp); | |
389 | } | |
390 | } | |
391 | ||
6aa8b732 AK |
392 | static unsigned long vmcs_readl(unsigned long field) |
393 | { | |
394 | unsigned long value; | |
395 | ||
4ecac3fd | 396 | asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX) |
6aa8b732 AK |
397 | : "=a"(value) : "d"(field) : "cc"); |
398 | return value; | |
399 | } | |
400 | ||
401 | static u16 vmcs_read16(unsigned long field) | |
402 | { | |
403 | return vmcs_readl(field); | |
404 | } | |
405 | ||
406 | static u32 vmcs_read32(unsigned long field) | |
407 | { | |
408 | return vmcs_readl(field); | |
409 | } | |
410 | ||
411 | static u64 vmcs_read64(unsigned long field) | |
412 | { | |
05b3e0c2 | 413 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
414 | return vmcs_readl(field); |
415 | #else | |
416 | return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32); | |
417 | #endif | |
418 | } | |
419 | ||
e52de1b8 AK |
420 | static noinline void vmwrite_error(unsigned long field, unsigned long value) |
421 | { | |
422 | printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n", | |
423 | field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); | |
424 | dump_stack(); | |
425 | } | |
426 | ||
6aa8b732 AK |
427 | static void vmcs_writel(unsigned long field, unsigned long value) |
428 | { | |
429 | u8 error; | |
430 | ||
4ecac3fd | 431 | asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0" |
d77c26fc | 432 | : "=q"(error) : "a"(value), "d"(field) : "cc"); |
e52de1b8 AK |
433 | if (unlikely(error)) |
434 | vmwrite_error(field, value); | |
6aa8b732 AK |
435 | } |
436 | ||
437 | static void vmcs_write16(unsigned long field, u16 value) | |
438 | { | |
439 | vmcs_writel(field, value); | |
440 | } | |
441 | ||
442 | static void vmcs_write32(unsigned long field, u32 value) | |
443 | { | |
444 | vmcs_writel(field, value); | |
445 | } | |
446 | ||
447 | static void vmcs_write64(unsigned long field, u64 value) | |
448 | { | |
6aa8b732 | 449 | vmcs_writel(field, value); |
7682f2d0 | 450 | #ifndef CONFIG_X86_64 |
6aa8b732 AK |
451 | asm volatile (""); |
452 | vmcs_writel(field+1, value >> 32); | |
453 | #endif | |
454 | } | |
455 | ||
2ab455cc AL |
456 | static void vmcs_clear_bits(unsigned long field, u32 mask) |
457 | { | |
458 | vmcs_writel(field, vmcs_readl(field) & ~mask); | |
459 | } | |
460 | ||
461 | static void vmcs_set_bits(unsigned long field, u32 mask) | |
462 | { | |
463 | vmcs_writel(field, vmcs_readl(field) | mask); | |
464 | } | |
465 | ||
abd3f2d6 AK |
466 | static void update_exception_bitmap(struct kvm_vcpu *vcpu) |
467 | { | |
468 | u32 eb; | |
469 | ||
7aa81cc0 | 470 | eb = (1u << PF_VECTOR) | (1u << UD_VECTOR); |
abd3f2d6 AK |
471 | if (!vcpu->fpu_active) |
472 | eb |= 1u << NM_VECTOR; | |
473 | if (vcpu->guest_debug.enabled) | |
19bd8afd | 474 | eb |= 1u << DB_VECTOR; |
ad312c7c | 475 | if (vcpu->arch.rmode.active) |
abd3f2d6 | 476 | eb = ~0; |
1439442c SY |
477 | if (vm_need_ept()) |
478 | eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ | |
abd3f2d6 AK |
479 | vmcs_write32(EXCEPTION_BITMAP, eb); |
480 | } | |
481 | ||
33ed6329 AK |
482 | static void reload_tss(void) |
483 | { | |
33ed6329 AK |
484 | /* |
485 | * VT restores TR but not its size. Useless. | |
486 | */ | |
487 | struct descriptor_table gdt; | |
a5f61300 | 488 | struct desc_struct *descs; |
33ed6329 | 489 | |
d6e88aec | 490 | kvm_get_gdt(&gdt); |
33ed6329 AK |
491 | descs = (void *)gdt.base; |
492 | descs[GDT_ENTRY_TSS].type = 9; /* available TSS */ | |
493 | load_TR_desc(); | |
33ed6329 AK |
494 | } |
495 | ||
8b9cf98c | 496 | static void load_transition_efer(struct vcpu_vmx *vmx) |
2cc51560 | 497 | { |
a2fa3e9f | 498 | int efer_offset = vmx->msr_offset_efer; |
51c6cf66 AK |
499 | u64 host_efer = vmx->host_msrs[efer_offset].data; |
500 | u64 guest_efer = vmx->guest_msrs[efer_offset].data; | |
501 | u64 ignore_bits; | |
502 | ||
503 | if (efer_offset < 0) | |
504 | return; | |
505 | /* | |
506 | * NX is emulated; LMA and LME handled by hardware; SCE meaninless | |
507 | * outside long mode | |
508 | */ | |
509 | ignore_bits = EFER_NX | EFER_SCE; | |
510 | #ifdef CONFIG_X86_64 | |
511 | ignore_bits |= EFER_LMA | EFER_LME; | |
512 | /* SCE is meaningful only in long mode on Intel */ | |
513 | if (guest_efer & EFER_LMA) | |
514 | ignore_bits &= ~(u64)EFER_SCE; | |
515 | #endif | |
516 | if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits)) | |
517 | return; | |
2cc51560 | 518 | |
51c6cf66 AK |
519 | vmx->host_state.guest_efer_loaded = 1; |
520 | guest_efer &= ~ignore_bits; | |
521 | guest_efer |= host_efer & ignore_bits; | |
522 | wrmsrl(MSR_EFER, guest_efer); | |
8b9cf98c | 523 | vmx->vcpu.stat.efer_reload++; |
2cc51560 ED |
524 | } |
525 | ||
51c6cf66 AK |
526 | static void reload_host_efer(struct vcpu_vmx *vmx) |
527 | { | |
528 | if (vmx->host_state.guest_efer_loaded) { | |
529 | vmx->host_state.guest_efer_loaded = 0; | |
530 | load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1); | |
531 | } | |
532 | } | |
533 | ||
04d2cc77 | 534 | static void vmx_save_host_state(struct kvm_vcpu *vcpu) |
33ed6329 | 535 | { |
04d2cc77 AK |
536 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
537 | ||
a2fa3e9f | 538 | if (vmx->host_state.loaded) |
33ed6329 AK |
539 | return; |
540 | ||
a2fa3e9f | 541 | vmx->host_state.loaded = 1; |
33ed6329 AK |
542 | /* |
543 | * Set host fs and gs selectors. Unfortunately, 22.2.3 does not | |
544 | * allow segment selectors with cpl > 0 or ti == 1. | |
545 | */ | |
d6e88aec | 546 | vmx->host_state.ldt_sel = kvm_read_ldt(); |
152d3f2f | 547 | vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel; |
d6e88aec | 548 | vmx->host_state.fs_sel = kvm_read_fs(); |
152d3f2f | 549 | if (!(vmx->host_state.fs_sel & 7)) { |
a2fa3e9f | 550 | vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel); |
152d3f2f LV |
551 | vmx->host_state.fs_reload_needed = 0; |
552 | } else { | |
33ed6329 | 553 | vmcs_write16(HOST_FS_SELECTOR, 0); |
152d3f2f | 554 | vmx->host_state.fs_reload_needed = 1; |
33ed6329 | 555 | } |
d6e88aec | 556 | vmx->host_state.gs_sel = kvm_read_gs(); |
a2fa3e9f GH |
557 | if (!(vmx->host_state.gs_sel & 7)) |
558 | vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel); | |
33ed6329 AK |
559 | else { |
560 | vmcs_write16(HOST_GS_SELECTOR, 0); | |
152d3f2f | 561 | vmx->host_state.gs_ldt_reload_needed = 1; |
33ed6329 AK |
562 | } |
563 | ||
564 | #ifdef CONFIG_X86_64 | |
565 | vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE)); | |
566 | vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE)); | |
567 | #else | |
a2fa3e9f GH |
568 | vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel)); |
569 | vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel)); | |
33ed6329 | 570 | #endif |
707c0874 AK |
571 | |
572 | #ifdef CONFIG_X86_64 | |
d77c26fc | 573 | if (is_long_mode(&vmx->vcpu)) |
a2fa3e9f GH |
574 | save_msrs(vmx->host_msrs + |
575 | vmx->msr_offset_kernel_gs_base, 1); | |
d77c26fc | 576 | |
707c0874 | 577 | #endif |
a2fa3e9f | 578 | load_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
51c6cf66 | 579 | load_transition_efer(vmx); |
33ed6329 AK |
580 | } |
581 | ||
a9b21b62 | 582 | static void __vmx_load_host_state(struct vcpu_vmx *vmx) |
33ed6329 | 583 | { |
15ad7146 | 584 | unsigned long flags; |
33ed6329 | 585 | |
a2fa3e9f | 586 | if (!vmx->host_state.loaded) |
33ed6329 AK |
587 | return; |
588 | ||
e1beb1d3 | 589 | ++vmx->vcpu.stat.host_state_reload; |
a2fa3e9f | 590 | vmx->host_state.loaded = 0; |
152d3f2f | 591 | if (vmx->host_state.fs_reload_needed) |
d6e88aec | 592 | kvm_load_fs(vmx->host_state.fs_sel); |
152d3f2f | 593 | if (vmx->host_state.gs_ldt_reload_needed) { |
d6e88aec | 594 | kvm_load_ldt(vmx->host_state.ldt_sel); |
33ed6329 AK |
595 | /* |
596 | * If we have to reload gs, we must take care to | |
597 | * preserve our gs base. | |
598 | */ | |
15ad7146 | 599 | local_irq_save(flags); |
d6e88aec | 600 | kvm_load_gs(vmx->host_state.gs_sel); |
33ed6329 AK |
601 | #ifdef CONFIG_X86_64 |
602 | wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE)); | |
603 | #endif | |
15ad7146 | 604 | local_irq_restore(flags); |
33ed6329 | 605 | } |
152d3f2f | 606 | reload_tss(); |
a2fa3e9f GH |
607 | save_msrs(vmx->guest_msrs, vmx->save_nmsrs); |
608 | load_msrs(vmx->host_msrs, vmx->save_nmsrs); | |
51c6cf66 | 609 | reload_host_efer(vmx); |
33ed6329 AK |
610 | } |
611 | ||
a9b21b62 AK |
612 | static void vmx_load_host_state(struct vcpu_vmx *vmx) |
613 | { | |
614 | preempt_disable(); | |
615 | __vmx_load_host_state(vmx); | |
616 | preempt_enable(); | |
617 | } | |
618 | ||
6aa8b732 AK |
619 | /* |
620 | * Switches to specified vcpu, until a matching vcpu_put(), but assumes | |
621 | * vcpu mutex is already taken. | |
622 | */ | |
15ad7146 | 623 | static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) |
6aa8b732 | 624 | { |
a2fa3e9f GH |
625 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
626 | u64 phys_addr = __pa(vmx->vmcs); | |
019960ae | 627 | u64 tsc_this, delta, new_offset; |
6aa8b732 | 628 | |
a3d7f85f | 629 | if (vcpu->cpu != cpu) { |
8b9cf98c | 630 | vcpu_clear(vmx); |
2f599714 | 631 | kvm_migrate_timers(vcpu); |
2384d2b3 | 632 | vpid_sync_vcpu_all(vmx); |
543e4243 AK |
633 | local_irq_disable(); |
634 | list_add(&vmx->local_vcpus_link, | |
635 | &per_cpu(vcpus_on_cpu, cpu)); | |
636 | local_irq_enable(); | |
a3d7f85f | 637 | } |
6aa8b732 | 638 | |
a2fa3e9f | 639 | if (per_cpu(current_vmcs, cpu) != vmx->vmcs) { |
6aa8b732 AK |
640 | u8 error; |
641 | ||
a2fa3e9f | 642 | per_cpu(current_vmcs, cpu) = vmx->vmcs; |
4ecac3fd | 643 | asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0" |
6aa8b732 AK |
644 | : "=g"(error) : "a"(&phys_addr), "m"(phys_addr) |
645 | : "cc"); | |
646 | if (error) | |
647 | printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n", | |
a2fa3e9f | 648 | vmx->vmcs, phys_addr); |
6aa8b732 AK |
649 | } |
650 | ||
651 | if (vcpu->cpu != cpu) { | |
652 | struct descriptor_table dt; | |
653 | unsigned long sysenter_esp; | |
654 | ||
655 | vcpu->cpu = cpu; | |
656 | /* | |
657 | * Linux uses per-cpu TSS and GDT, so set these when switching | |
658 | * processors. | |
659 | */ | |
d6e88aec AK |
660 | vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */ |
661 | kvm_get_gdt(&dt); | |
6aa8b732 AK |
662 | vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */ |
663 | ||
664 | rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); | |
665 | vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ | |
7700270e AK |
666 | |
667 | /* | |
668 | * Make sure the time stamp counter is monotonous. | |
669 | */ | |
670 | rdtscll(tsc_this); | |
019960ae AK |
671 | if (tsc_this < vcpu->arch.host_tsc) { |
672 | delta = vcpu->arch.host_tsc - tsc_this; | |
673 | new_offset = vmcs_read64(TSC_OFFSET) + delta; | |
674 | vmcs_write64(TSC_OFFSET, new_offset); | |
675 | } | |
6aa8b732 | 676 | } |
6aa8b732 AK |
677 | } |
678 | ||
679 | static void vmx_vcpu_put(struct kvm_vcpu *vcpu) | |
680 | { | |
a9b21b62 | 681 | __vmx_load_host_state(to_vmx(vcpu)); |
6aa8b732 AK |
682 | } |
683 | ||
5fd86fcf AK |
684 | static void vmx_fpu_activate(struct kvm_vcpu *vcpu) |
685 | { | |
686 | if (vcpu->fpu_active) | |
687 | return; | |
688 | vcpu->fpu_active = 1; | |
707d92fa | 689 | vmcs_clear_bits(GUEST_CR0, X86_CR0_TS); |
ad312c7c | 690 | if (vcpu->arch.cr0 & X86_CR0_TS) |
707d92fa | 691 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
692 | update_exception_bitmap(vcpu); |
693 | } | |
694 | ||
695 | static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu) | |
696 | { | |
697 | if (!vcpu->fpu_active) | |
698 | return; | |
699 | vcpu->fpu_active = 0; | |
707d92fa | 700 | vmcs_set_bits(GUEST_CR0, X86_CR0_TS); |
5fd86fcf AK |
701 | update_exception_bitmap(vcpu); |
702 | } | |
703 | ||
6aa8b732 AK |
704 | static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) |
705 | { | |
706 | return vmcs_readl(GUEST_RFLAGS); | |
707 | } | |
708 | ||
709 | static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) | |
710 | { | |
ad312c7c | 711 | if (vcpu->arch.rmode.active) |
053de044 | 712 | rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
713 | vmcs_writel(GUEST_RFLAGS, rflags); |
714 | } | |
715 | ||
716 | static void skip_emulated_instruction(struct kvm_vcpu *vcpu) | |
717 | { | |
718 | unsigned long rip; | |
719 | u32 interruptibility; | |
720 | ||
5fdbf976 | 721 | rip = kvm_rip_read(vcpu); |
6aa8b732 | 722 | rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); |
5fdbf976 | 723 | kvm_rip_write(vcpu, rip); |
6aa8b732 AK |
724 | |
725 | /* | |
726 | * We emulated an instruction, so temporary interrupt blocking | |
727 | * should be removed, if set. | |
728 | */ | |
729 | interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
730 | if (interruptibility & 3) | |
731 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, | |
732 | interruptibility & ~3); | |
ad312c7c | 733 | vcpu->arch.interrupt_window_open = 1; |
6aa8b732 AK |
734 | } |
735 | ||
298101da AK |
736 | static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr, |
737 | bool has_error_code, u32 error_code) | |
738 | { | |
77ab6db0 JK |
739 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
740 | ||
741 | if (has_error_code) | |
742 | vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); | |
743 | ||
744 | if (vcpu->arch.rmode.active) { | |
745 | vmx->rmode.irq.pending = true; | |
746 | vmx->rmode.irq.vector = nr; | |
747 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); | |
748 | if (nr == BP_VECTOR) | |
749 | vmx->rmode.irq.rip++; | |
750 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
751 | nr | INTR_TYPE_SOFT_INTR | |
752 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) | |
753 | | INTR_INFO_VALID_MASK); | |
754 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
755 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); | |
756 | return; | |
757 | } | |
758 | ||
298101da AK |
759 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
760 | nr | INTR_TYPE_EXCEPTION | |
2e11384c | 761 | | (has_error_code ? INTR_INFO_DELIVER_CODE_MASK : 0) |
298101da | 762 | | INTR_INFO_VALID_MASK); |
298101da AK |
763 | } |
764 | ||
765 | static bool vmx_exception_injected(struct kvm_vcpu *vcpu) | |
766 | { | |
35920a35 | 767 | return false; |
298101da AK |
768 | } |
769 | ||
a75beee6 ED |
770 | /* |
771 | * Swap MSR entry in host/guest MSR entry array. | |
772 | */ | |
54e11fa1 | 773 | #ifdef CONFIG_X86_64 |
8b9cf98c | 774 | static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) |
a75beee6 | 775 | { |
a2fa3e9f GH |
776 | struct kvm_msr_entry tmp; |
777 | ||
778 | tmp = vmx->guest_msrs[to]; | |
779 | vmx->guest_msrs[to] = vmx->guest_msrs[from]; | |
780 | vmx->guest_msrs[from] = tmp; | |
781 | tmp = vmx->host_msrs[to]; | |
782 | vmx->host_msrs[to] = vmx->host_msrs[from]; | |
783 | vmx->host_msrs[from] = tmp; | |
a75beee6 | 784 | } |
54e11fa1 | 785 | #endif |
a75beee6 | 786 | |
e38aea3e AK |
787 | /* |
788 | * Set up the vmcs to automatically save and restore system | |
789 | * msrs. Don't touch the 64-bit msrs if the guest is in legacy | |
790 | * mode, as fiddling with msrs is very expensive. | |
791 | */ | |
8b9cf98c | 792 | static void setup_msrs(struct vcpu_vmx *vmx) |
e38aea3e | 793 | { |
2cc51560 | 794 | int save_nmsrs; |
e38aea3e | 795 | |
33f9c505 | 796 | vmx_load_host_state(vmx); |
a75beee6 ED |
797 | save_nmsrs = 0; |
798 | #ifdef CONFIG_X86_64 | |
8b9cf98c | 799 | if (is_long_mode(&vmx->vcpu)) { |
2cc51560 ED |
800 | int index; |
801 | ||
8b9cf98c | 802 | index = __find_msr_index(vmx, MSR_SYSCALL_MASK); |
a75beee6 | 803 | if (index >= 0) |
8b9cf98c RR |
804 | move_msr_up(vmx, index, save_nmsrs++); |
805 | index = __find_msr_index(vmx, MSR_LSTAR); | |
a75beee6 | 806 | if (index >= 0) |
8b9cf98c RR |
807 | move_msr_up(vmx, index, save_nmsrs++); |
808 | index = __find_msr_index(vmx, MSR_CSTAR); | |
a75beee6 | 809 | if (index >= 0) |
8b9cf98c RR |
810 | move_msr_up(vmx, index, save_nmsrs++); |
811 | index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE); | |
a75beee6 | 812 | if (index >= 0) |
8b9cf98c | 813 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
814 | /* |
815 | * MSR_K6_STAR is only needed on long mode guests, and only | |
816 | * if efer.sce is enabled. | |
817 | */ | |
8b9cf98c | 818 | index = __find_msr_index(vmx, MSR_K6_STAR); |
ad312c7c | 819 | if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE)) |
8b9cf98c | 820 | move_msr_up(vmx, index, save_nmsrs++); |
a75beee6 ED |
821 | } |
822 | #endif | |
a2fa3e9f | 823 | vmx->save_nmsrs = save_nmsrs; |
e38aea3e | 824 | |
4d56c8a7 | 825 | #ifdef CONFIG_X86_64 |
a2fa3e9f | 826 | vmx->msr_offset_kernel_gs_base = |
8b9cf98c | 827 | __find_msr_index(vmx, MSR_KERNEL_GS_BASE); |
4d56c8a7 | 828 | #endif |
8b9cf98c | 829 | vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER); |
e38aea3e AK |
830 | } |
831 | ||
6aa8b732 AK |
832 | /* |
833 | * reads and returns guest's timestamp counter "register" | |
834 | * guest_tsc = host_tsc + tsc_offset -- 21.3 | |
835 | */ | |
836 | static u64 guest_read_tsc(void) | |
837 | { | |
838 | u64 host_tsc, tsc_offset; | |
839 | ||
840 | rdtscll(host_tsc); | |
841 | tsc_offset = vmcs_read64(TSC_OFFSET); | |
842 | return host_tsc + tsc_offset; | |
843 | } | |
844 | ||
845 | /* | |
846 | * writes 'guest_tsc' into guest's timestamp counter "register" | |
847 | * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc | |
848 | */ | |
849 | static void guest_write_tsc(u64 guest_tsc) | |
850 | { | |
851 | u64 host_tsc; | |
852 | ||
853 | rdtscll(host_tsc); | |
854 | vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc); | |
855 | } | |
856 | ||
6aa8b732 AK |
857 | /* |
858 | * Reads an msr value (of 'msr_index') into 'pdata'. | |
859 | * Returns 0 on success, non-0 otherwise. | |
860 | * Assumes vcpu_load() was already called. | |
861 | */ | |
862 | static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata) | |
863 | { | |
864 | u64 data; | |
a2fa3e9f | 865 | struct kvm_msr_entry *msr; |
6aa8b732 AK |
866 | |
867 | if (!pdata) { | |
868 | printk(KERN_ERR "BUG: get_msr called with NULL pdata\n"); | |
869 | return -EINVAL; | |
870 | } | |
871 | ||
872 | switch (msr_index) { | |
05b3e0c2 | 873 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
874 | case MSR_FS_BASE: |
875 | data = vmcs_readl(GUEST_FS_BASE); | |
876 | break; | |
877 | case MSR_GS_BASE: | |
878 | data = vmcs_readl(GUEST_GS_BASE); | |
879 | break; | |
880 | case MSR_EFER: | |
3bab1f5d | 881 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
882 | #endif |
883 | case MSR_IA32_TIME_STAMP_COUNTER: | |
884 | data = guest_read_tsc(); | |
885 | break; | |
886 | case MSR_IA32_SYSENTER_CS: | |
887 | data = vmcs_read32(GUEST_SYSENTER_CS); | |
888 | break; | |
889 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 890 | data = vmcs_readl(GUEST_SYSENTER_EIP); |
6aa8b732 AK |
891 | break; |
892 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 893 | data = vmcs_readl(GUEST_SYSENTER_ESP); |
6aa8b732 | 894 | break; |
6aa8b732 | 895 | default: |
8b9cf98c | 896 | msr = find_msr_entry(to_vmx(vcpu), msr_index); |
3bab1f5d AK |
897 | if (msr) { |
898 | data = msr->data; | |
899 | break; | |
6aa8b732 | 900 | } |
3bab1f5d | 901 | return kvm_get_msr_common(vcpu, msr_index, pdata); |
6aa8b732 AK |
902 | } |
903 | ||
904 | *pdata = data; | |
905 | return 0; | |
906 | } | |
907 | ||
908 | /* | |
909 | * Writes msr value into into the appropriate "register". | |
910 | * Returns 0 on success, non-0 otherwise. | |
911 | * Assumes vcpu_load() was already called. | |
912 | */ | |
913 | static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data) | |
914 | { | |
a2fa3e9f GH |
915 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
916 | struct kvm_msr_entry *msr; | |
2cc51560 ED |
917 | int ret = 0; |
918 | ||
6aa8b732 | 919 | switch (msr_index) { |
05b3e0c2 | 920 | #ifdef CONFIG_X86_64 |
3bab1f5d | 921 | case MSR_EFER: |
a9b21b62 | 922 | vmx_load_host_state(vmx); |
2cc51560 | 923 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
2cc51560 | 924 | break; |
6aa8b732 AK |
925 | case MSR_FS_BASE: |
926 | vmcs_writel(GUEST_FS_BASE, data); | |
927 | break; | |
928 | case MSR_GS_BASE: | |
929 | vmcs_writel(GUEST_GS_BASE, data); | |
930 | break; | |
931 | #endif | |
932 | case MSR_IA32_SYSENTER_CS: | |
933 | vmcs_write32(GUEST_SYSENTER_CS, data); | |
934 | break; | |
935 | case MSR_IA32_SYSENTER_EIP: | |
f5b42c33 | 936 | vmcs_writel(GUEST_SYSENTER_EIP, data); |
6aa8b732 AK |
937 | break; |
938 | case MSR_IA32_SYSENTER_ESP: | |
f5b42c33 | 939 | vmcs_writel(GUEST_SYSENTER_ESP, data); |
6aa8b732 | 940 | break; |
d27d4aca | 941 | case MSR_IA32_TIME_STAMP_COUNTER: |
6aa8b732 | 942 | guest_write_tsc(data); |
efa67e0d CL |
943 | break; |
944 | case MSR_P6_PERFCTR0: | |
945 | case MSR_P6_PERFCTR1: | |
946 | case MSR_P6_EVNTSEL0: | |
947 | case MSR_P6_EVNTSEL1: | |
948 | /* | |
949 | * Just discard all writes to the performance counters; this | |
950 | * should keep both older linux and windows 64-bit guests | |
951 | * happy | |
952 | */ | |
953 | pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data); | |
954 | ||
6aa8b732 | 955 | break; |
6aa8b732 | 956 | default: |
a9b21b62 | 957 | vmx_load_host_state(vmx); |
8b9cf98c | 958 | msr = find_msr_entry(vmx, msr_index); |
3bab1f5d AK |
959 | if (msr) { |
960 | msr->data = data; | |
961 | break; | |
6aa8b732 | 962 | } |
2cc51560 | 963 | ret = kvm_set_msr_common(vcpu, msr_index, data); |
6aa8b732 AK |
964 | } |
965 | ||
2cc51560 | 966 | return ret; |
6aa8b732 AK |
967 | } |
968 | ||
5fdbf976 | 969 | static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) |
6aa8b732 | 970 | { |
5fdbf976 MT |
971 | __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail); |
972 | switch (reg) { | |
973 | case VCPU_REGS_RSP: | |
974 | vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); | |
975 | break; | |
976 | case VCPU_REGS_RIP: | |
977 | vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); | |
978 | break; | |
979 | default: | |
980 | break; | |
981 | } | |
6aa8b732 AK |
982 | } |
983 | ||
984 | static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg) | |
985 | { | |
986 | unsigned long dr7 = 0x400; | |
6aa8b732 AK |
987 | int old_singlestep; |
988 | ||
6aa8b732 AK |
989 | old_singlestep = vcpu->guest_debug.singlestep; |
990 | ||
991 | vcpu->guest_debug.enabled = dbg->enabled; | |
992 | if (vcpu->guest_debug.enabled) { | |
993 | int i; | |
994 | ||
995 | dr7 |= 0x200; /* exact */ | |
996 | for (i = 0; i < 4; ++i) { | |
997 | if (!dbg->breakpoints[i].enabled) | |
998 | continue; | |
999 | vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address; | |
1000 | dr7 |= 2 << (i*2); /* global enable */ | |
1001 | dr7 |= 0 << (i*4+16); /* execution breakpoint */ | |
1002 | } | |
1003 | ||
6aa8b732 | 1004 | vcpu->guest_debug.singlestep = dbg->singlestep; |
abd3f2d6 | 1005 | } else |
6aa8b732 | 1006 | vcpu->guest_debug.singlestep = 0; |
6aa8b732 AK |
1007 | |
1008 | if (old_singlestep && !vcpu->guest_debug.singlestep) { | |
1009 | unsigned long flags; | |
1010 | ||
1011 | flags = vmcs_readl(GUEST_RFLAGS); | |
1012 | flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF); | |
1013 | vmcs_writel(GUEST_RFLAGS, flags); | |
1014 | } | |
1015 | ||
abd3f2d6 | 1016 | update_exception_bitmap(vcpu); |
6aa8b732 AK |
1017 | vmcs_writel(GUEST_DR7, dr7); |
1018 | ||
1019 | return 0; | |
1020 | } | |
1021 | ||
2a8067f1 ED |
1022 | static int vmx_get_irq(struct kvm_vcpu *vcpu) |
1023 | { | |
f7d9238f AK |
1024 | if (!vcpu->arch.interrupt.pending) |
1025 | return -1; | |
1026 | return vcpu->arch.interrupt.nr; | |
2a8067f1 ED |
1027 | } |
1028 | ||
6aa8b732 AK |
1029 | static __init int cpu_has_kvm_support(void) |
1030 | { | |
1031 | unsigned long ecx = cpuid_ecx(1); | |
1032 | return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */ | |
1033 | } | |
1034 | ||
1035 | static __init int vmx_disabled_by_bios(void) | |
1036 | { | |
1037 | u64 msr; | |
1038 | ||
1039 | rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); | |
ca60dfbb SY |
1040 | return (msr & (IA32_FEATURE_CONTROL_LOCKED_BIT | |
1041 | IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT)) | |
1042 | == IA32_FEATURE_CONTROL_LOCKED_BIT; | |
62b3ffb8 | 1043 | /* locked but not enabled */ |
6aa8b732 AK |
1044 | } |
1045 | ||
774c47f1 | 1046 | static void hardware_enable(void *garbage) |
6aa8b732 AK |
1047 | { |
1048 | int cpu = raw_smp_processor_id(); | |
1049 | u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); | |
1050 | u64 old; | |
1051 | ||
543e4243 | 1052 | INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu)); |
6aa8b732 | 1053 | rdmsrl(MSR_IA32_FEATURE_CONTROL, old); |
ca60dfbb SY |
1054 | if ((old & (IA32_FEATURE_CONTROL_LOCKED_BIT | |
1055 | IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT)) | |
1056 | != (IA32_FEATURE_CONTROL_LOCKED_BIT | | |
1057 | IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT)) | |
6aa8b732 | 1058 | /* enable and lock */ |
62b3ffb8 | 1059 | wrmsrl(MSR_IA32_FEATURE_CONTROL, old | |
ca60dfbb SY |
1060 | IA32_FEATURE_CONTROL_LOCKED_BIT | |
1061 | IA32_FEATURE_CONTROL_VMXON_ENABLED_BIT); | |
66aee91a | 1062 | write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */ |
4ecac3fd AK |
1063 | asm volatile (ASM_VMX_VMXON_RAX |
1064 | : : "a"(&phys_addr), "m"(phys_addr) | |
6aa8b732 AK |
1065 | : "memory", "cc"); |
1066 | } | |
1067 | ||
543e4243 AK |
1068 | static void vmclear_local_vcpus(void) |
1069 | { | |
1070 | int cpu = raw_smp_processor_id(); | |
1071 | struct vcpu_vmx *vmx, *n; | |
1072 | ||
1073 | list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu), | |
1074 | local_vcpus_link) | |
1075 | __vcpu_clear(vmx); | |
1076 | } | |
1077 | ||
6aa8b732 AK |
1078 | static void hardware_disable(void *garbage) |
1079 | { | |
543e4243 | 1080 | vmclear_local_vcpus(); |
4ecac3fd | 1081 | asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc"); |
e693d71b | 1082 | write_cr4(read_cr4() & ~X86_CR4_VMXE); |
6aa8b732 AK |
1083 | } |
1084 | ||
1c3d14fe | 1085 | static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, |
d77c26fc | 1086 | u32 msr, u32 *result) |
1c3d14fe YS |
1087 | { |
1088 | u32 vmx_msr_low, vmx_msr_high; | |
1089 | u32 ctl = ctl_min | ctl_opt; | |
1090 | ||
1091 | rdmsr(msr, vmx_msr_low, vmx_msr_high); | |
1092 | ||
1093 | ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ | |
1094 | ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ | |
1095 | ||
1096 | /* Ensure minimum (required) set of control bits are supported. */ | |
1097 | if (ctl_min & ~ctl) | |
002c7f7c | 1098 | return -EIO; |
1c3d14fe YS |
1099 | |
1100 | *result = ctl; | |
1101 | return 0; | |
1102 | } | |
1103 | ||
002c7f7c | 1104 | static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf) |
6aa8b732 AK |
1105 | { |
1106 | u32 vmx_msr_low, vmx_msr_high; | |
d56f546d | 1107 | u32 min, opt, min2, opt2; |
1c3d14fe YS |
1108 | u32 _pin_based_exec_control = 0; |
1109 | u32 _cpu_based_exec_control = 0; | |
f78e0e2e | 1110 | u32 _cpu_based_2nd_exec_control = 0; |
1c3d14fe YS |
1111 | u32 _vmexit_control = 0; |
1112 | u32 _vmentry_control = 0; | |
1113 | ||
1114 | min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; | |
f08864b4 | 1115 | opt = PIN_BASED_VIRTUAL_NMIS; |
1c3d14fe YS |
1116 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, |
1117 | &_pin_based_exec_control) < 0) | |
002c7f7c | 1118 | return -EIO; |
1c3d14fe YS |
1119 | |
1120 | min = CPU_BASED_HLT_EXITING | | |
1121 | #ifdef CONFIG_X86_64 | |
1122 | CPU_BASED_CR8_LOAD_EXITING | | |
1123 | CPU_BASED_CR8_STORE_EXITING | | |
1124 | #endif | |
d56f546d SY |
1125 | CPU_BASED_CR3_LOAD_EXITING | |
1126 | CPU_BASED_CR3_STORE_EXITING | | |
1c3d14fe YS |
1127 | CPU_BASED_USE_IO_BITMAPS | |
1128 | CPU_BASED_MOV_DR_EXITING | | |
1129 | CPU_BASED_USE_TSC_OFFSETING; | |
f78e0e2e | 1130 | opt = CPU_BASED_TPR_SHADOW | |
25c5f225 | 1131 | CPU_BASED_USE_MSR_BITMAPS | |
f78e0e2e | 1132 | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; |
1c3d14fe YS |
1133 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, |
1134 | &_cpu_based_exec_control) < 0) | |
002c7f7c | 1135 | return -EIO; |
6e5d865c YS |
1136 | #ifdef CONFIG_X86_64 |
1137 | if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) | |
1138 | _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & | |
1139 | ~CPU_BASED_CR8_STORE_EXITING; | |
1140 | #endif | |
f78e0e2e | 1141 | if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { |
d56f546d SY |
1142 | min2 = 0; |
1143 | opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | | |
2384d2b3 | 1144 | SECONDARY_EXEC_WBINVD_EXITING | |
d56f546d SY |
1145 | SECONDARY_EXEC_ENABLE_VPID | |
1146 | SECONDARY_EXEC_ENABLE_EPT; | |
1147 | if (adjust_vmx_controls(min2, opt2, | |
1148 | MSR_IA32_VMX_PROCBASED_CTLS2, | |
f78e0e2e SY |
1149 | &_cpu_based_2nd_exec_control) < 0) |
1150 | return -EIO; | |
1151 | } | |
1152 | #ifndef CONFIG_X86_64 | |
1153 | if (!(_cpu_based_2nd_exec_control & | |
1154 | SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) | |
1155 | _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1156 | #endif | |
d56f546d SY |
1157 | if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { |
1158 | /* CR3 accesses don't need to cause VM Exits when EPT enabled */ | |
1159 | min &= ~(CPU_BASED_CR3_LOAD_EXITING | | |
1160 | CPU_BASED_CR3_STORE_EXITING); | |
1161 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, | |
1162 | &_cpu_based_exec_control) < 0) | |
1163 | return -EIO; | |
1164 | rdmsr(MSR_IA32_VMX_EPT_VPID_CAP, | |
1165 | vmx_capability.ept, vmx_capability.vpid); | |
1166 | } | |
1c3d14fe YS |
1167 | |
1168 | min = 0; | |
1169 | #ifdef CONFIG_X86_64 | |
1170 | min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; | |
1171 | #endif | |
1172 | opt = 0; | |
1173 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, | |
1174 | &_vmexit_control) < 0) | |
002c7f7c | 1175 | return -EIO; |
1c3d14fe YS |
1176 | |
1177 | min = opt = 0; | |
1178 | if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, | |
1179 | &_vmentry_control) < 0) | |
002c7f7c | 1180 | return -EIO; |
6aa8b732 | 1181 | |
c68876fd | 1182 | rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); |
1c3d14fe YS |
1183 | |
1184 | /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ | |
1185 | if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) | |
002c7f7c | 1186 | return -EIO; |
1c3d14fe YS |
1187 | |
1188 | #ifdef CONFIG_X86_64 | |
1189 | /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ | |
1190 | if (vmx_msr_high & (1u<<16)) | |
002c7f7c | 1191 | return -EIO; |
1c3d14fe YS |
1192 | #endif |
1193 | ||
1194 | /* Require Write-Back (WB) memory type for VMCS accesses. */ | |
1195 | if (((vmx_msr_high >> 18) & 15) != 6) | |
002c7f7c | 1196 | return -EIO; |
1c3d14fe | 1197 | |
002c7f7c YS |
1198 | vmcs_conf->size = vmx_msr_high & 0x1fff; |
1199 | vmcs_conf->order = get_order(vmcs_config.size); | |
1200 | vmcs_conf->revision_id = vmx_msr_low; | |
1c3d14fe | 1201 | |
002c7f7c YS |
1202 | vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; |
1203 | vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; | |
f78e0e2e | 1204 | vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; |
002c7f7c YS |
1205 | vmcs_conf->vmexit_ctrl = _vmexit_control; |
1206 | vmcs_conf->vmentry_ctrl = _vmentry_control; | |
1c3d14fe YS |
1207 | |
1208 | return 0; | |
c68876fd | 1209 | } |
6aa8b732 AK |
1210 | |
1211 | static struct vmcs *alloc_vmcs_cpu(int cpu) | |
1212 | { | |
1213 | int node = cpu_to_node(cpu); | |
1214 | struct page *pages; | |
1215 | struct vmcs *vmcs; | |
1216 | ||
1c3d14fe | 1217 | pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order); |
6aa8b732 AK |
1218 | if (!pages) |
1219 | return NULL; | |
1220 | vmcs = page_address(pages); | |
1c3d14fe YS |
1221 | memset(vmcs, 0, vmcs_config.size); |
1222 | vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */ | |
6aa8b732 AK |
1223 | return vmcs; |
1224 | } | |
1225 | ||
1226 | static struct vmcs *alloc_vmcs(void) | |
1227 | { | |
d3b2c338 | 1228 | return alloc_vmcs_cpu(raw_smp_processor_id()); |
6aa8b732 AK |
1229 | } |
1230 | ||
1231 | static void free_vmcs(struct vmcs *vmcs) | |
1232 | { | |
1c3d14fe | 1233 | free_pages((unsigned long)vmcs, vmcs_config.order); |
6aa8b732 AK |
1234 | } |
1235 | ||
39959588 | 1236 | static void free_kvm_area(void) |
6aa8b732 AK |
1237 | { |
1238 | int cpu; | |
1239 | ||
1240 | for_each_online_cpu(cpu) | |
1241 | free_vmcs(per_cpu(vmxarea, cpu)); | |
1242 | } | |
1243 | ||
6aa8b732 AK |
1244 | static __init int alloc_kvm_area(void) |
1245 | { | |
1246 | int cpu; | |
1247 | ||
1248 | for_each_online_cpu(cpu) { | |
1249 | struct vmcs *vmcs; | |
1250 | ||
1251 | vmcs = alloc_vmcs_cpu(cpu); | |
1252 | if (!vmcs) { | |
1253 | free_kvm_area(); | |
1254 | return -ENOMEM; | |
1255 | } | |
1256 | ||
1257 | per_cpu(vmxarea, cpu) = vmcs; | |
1258 | } | |
1259 | return 0; | |
1260 | } | |
1261 | ||
1262 | static __init int hardware_setup(void) | |
1263 | { | |
002c7f7c YS |
1264 | if (setup_vmcs_config(&vmcs_config) < 0) |
1265 | return -EIO; | |
50a37eb4 JR |
1266 | |
1267 | if (boot_cpu_has(X86_FEATURE_NX)) | |
1268 | kvm_enable_efer_bits(EFER_NX); | |
1269 | ||
6aa8b732 AK |
1270 | return alloc_kvm_area(); |
1271 | } | |
1272 | ||
1273 | static __exit void hardware_unsetup(void) | |
1274 | { | |
1275 | free_kvm_area(); | |
1276 | } | |
1277 | ||
6aa8b732 AK |
1278 | static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save) |
1279 | { | |
1280 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1281 | ||
6af11b9e | 1282 | if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) { |
6aa8b732 AK |
1283 | vmcs_write16(sf->selector, save->selector); |
1284 | vmcs_writel(sf->base, save->base); | |
1285 | vmcs_write32(sf->limit, save->limit); | |
1286 | vmcs_write32(sf->ar_bytes, save->ar); | |
1287 | } else { | |
1288 | u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK) | |
1289 | << AR_DPL_SHIFT; | |
1290 | vmcs_write32(sf->ar_bytes, 0x93 | dpl); | |
1291 | } | |
1292 | } | |
1293 | ||
1294 | static void enter_pmode(struct kvm_vcpu *vcpu) | |
1295 | { | |
1296 | unsigned long flags; | |
1297 | ||
ad312c7c | 1298 | vcpu->arch.rmode.active = 0; |
6aa8b732 | 1299 | |
ad312c7c ZX |
1300 | vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base); |
1301 | vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit); | |
1302 | vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar); | |
6aa8b732 AK |
1303 | |
1304 | flags = vmcs_readl(GUEST_RFLAGS); | |
053de044 | 1305 | flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM); |
ad312c7c | 1306 | flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT); |
6aa8b732 AK |
1307 | vmcs_writel(GUEST_RFLAGS, flags); |
1308 | ||
66aee91a RR |
1309 | vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | |
1310 | (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); | |
6aa8b732 AK |
1311 | |
1312 | update_exception_bitmap(vcpu); | |
1313 | ||
ad312c7c ZX |
1314 | fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1315 | fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1316 | fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1317 | fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
6aa8b732 AK |
1318 | |
1319 | vmcs_write16(GUEST_SS_SELECTOR, 0); | |
1320 | vmcs_write32(GUEST_SS_AR_BYTES, 0x93); | |
1321 | ||
1322 | vmcs_write16(GUEST_CS_SELECTOR, | |
1323 | vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK); | |
1324 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
1325 | } | |
1326 | ||
d77c26fc | 1327 | static gva_t rmode_tss_base(struct kvm *kvm) |
6aa8b732 | 1328 | { |
bfc6d222 | 1329 | if (!kvm->arch.tss_addr) { |
cbc94022 IE |
1330 | gfn_t base_gfn = kvm->memslots[0].base_gfn + |
1331 | kvm->memslots[0].npages - 3; | |
1332 | return base_gfn << PAGE_SHIFT; | |
1333 | } | |
bfc6d222 | 1334 | return kvm->arch.tss_addr; |
6aa8b732 AK |
1335 | } |
1336 | ||
1337 | static void fix_rmode_seg(int seg, struct kvm_save_segment *save) | |
1338 | { | |
1339 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1340 | ||
1341 | save->selector = vmcs_read16(sf->selector); | |
1342 | save->base = vmcs_readl(sf->base); | |
1343 | save->limit = vmcs_read32(sf->limit); | |
1344 | save->ar = vmcs_read32(sf->ar_bytes); | |
15b00f32 JK |
1345 | vmcs_write16(sf->selector, save->base >> 4); |
1346 | vmcs_write32(sf->base, save->base & 0xfffff); | |
6aa8b732 AK |
1347 | vmcs_write32(sf->limit, 0xffff); |
1348 | vmcs_write32(sf->ar_bytes, 0xf3); | |
1349 | } | |
1350 | ||
1351 | static void enter_rmode(struct kvm_vcpu *vcpu) | |
1352 | { | |
1353 | unsigned long flags; | |
1354 | ||
ad312c7c | 1355 | vcpu->arch.rmode.active = 1; |
6aa8b732 | 1356 | |
ad312c7c | 1357 | vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE); |
6aa8b732 AK |
1358 | vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm)); |
1359 | ||
ad312c7c | 1360 | vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT); |
6aa8b732 AK |
1361 | vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); |
1362 | ||
ad312c7c | 1363 | vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES); |
6aa8b732 AK |
1364 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); |
1365 | ||
1366 | flags = vmcs_readl(GUEST_RFLAGS); | |
ad312c7c ZX |
1367 | vcpu->arch.rmode.save_iopl |
1368 | = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT; | |
6aa8b732 | 1369 | |
053de044 | 1370 | flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; |
6aa8b732 AK |
1371 | |
1372 | vmcs_writel(GUEST_RFLAGS, flags); | |
66aee91a | 1373 | vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); |
6aa8b732 AK |
1374 | update_exception_bitmap(vcpu); |
1375 | ||
1376 | vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4); | |
1377 | vmcs_write32(GUEST_SS_LIMIT, 0xffff); | |
1378 | vmcs_write32(GUEST_SS_AR_BYTES, 0xf3); | |
1379 | ||
1380 | vmcs_write32(GUEST_CS_AR_BYTES, 0xf3); | |
abacf8df | 1381 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); |
8cb5b033 AK |
1382 | if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000) |
1383 | vmcs_writel(GUEST_CS_BASE, 0xf0000); | |
6aa8b732 AK |
1384 | vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4); |
1385 | ||
ad312c7c ZX |
1386 | fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es); |
1387 | fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds); | |
1388 | fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs); | |
1389 | fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs); | |
75880a01 | 1390 | |
8668a3c4 | 1391 | kvm_mmu_reset_context(vcpu); |
b7ebfb05 | 1392 | init_rmode(vcpu->kvm); |
6aa8b732 AK |
1393 | } |
1394 | ||
05b3e0c2 | 1395 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1396 | |
1397 | static void enter_lmode(struct kvm_vcpu *vcpu) | |
1398 | { | |
1399 | u32 guest_tr_ar; | |
1400 | ||
1401 | guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); | |
1402 | if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) { | |
1403 | printk(KERN_DEBUG "%s: tss fixup for long mode. \n", | |
b8688d51 | 1404 | __func__); |
6aa8b732 AK |
1405 | vmcs_write32(GUEST_TR_AR_BYTES, |
1406 | (guest_tr_ar & ~AR_TYPE_MASK) | |
1407 | | AR_TYPE_BUSY_64_TSS); | |
1408 | } | |
1409 | ||
ad312c7c | 1410 | vcpu->arch.shadow_efer |= EFER_LMA; |
6aa8b732 | 1411 | |
8b9cf98c | 1412 | find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME; |
6aa8b732 AK |
1413 | vmcs_write32(VM_ENTRY_CONTROLS, |
1414 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1415 | | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1416 | } |
1417 | ||
1418 | static void exit_lmode(struct kvm_vcpu *vcpu) | |
1419 | { | |
ad312c7c | 1420 | vcpu->arch.shadow_efer &= ~EFER_LMA; |
6aa8b732 AK |
1421 | |
1422 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1423 | vmcs_read32(VM_ENTRY_CONTROLS) | |
1e4e6e00 | 1424 | & ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1425 | } |
1426 | ||
1427 | #endif | |
1428 | ||
2384d2b3 SY |
1429 | static void vmx_flush_tlb(struct kvm_vcpu *vcpu) |
1430 | { | |
1431 | vpid_sync_vcpu_all(to_vmx(vcpu)); | |
4e1096d2 SY |
1432 | if (vm_need_ept()) |
1433 | ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa)); | |
2384d2b3 SY |
1434 | } |
1435 | ||
25c4c276 | 1436 | static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) |
399badf3 | 1437 | { |
ad312c7c ZX |
1438 | vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK; |
1439 | vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK; | |
399badf3 AK |
1440 | } |
1441 | ||
1439442c SY |
1442 | static void ept_load_pdptrs(struct kvm_vcpu *vcpu) |
1443 | { | |
1444 | if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) { | |
1445 | if (!load_pdptrs(vcpu, vcpu->arch.cr3)) { | |
1446 | printk(KERN_ERR "EPT: Fail to load pdptrs!\n"); | |
1447 | return; | |
1448 | } | |
1449 | vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]); | |
1450 | vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]); | |
1451 | vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]); | |
1452 | vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]); | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); | |
1457 | ||
1458 | static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, | |
1459 | unsigned long cr0, | |
1460 | struct kvm_vcpu *vcpu) | |
1461 | { | |
1462 | if (!(cr0 & X86_CR0_PG)) { | |
1463 | /* From paging/starting to nonpaging */ | |
1464 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1465 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) | |
1439442c SY |
1466 | (CPU_BASED_CR3_LOAD_EXITING | |
1467 | CPU_BASED_CR3_STORE_EXITING)); | |
1468 | vcpu->arch.cr0 = cr0; | |
1469 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1470 | *hw_cr0 |= X86_CR0_PE | X86_CR0_PG; | |
1471 | *hw_cr0 &= ~X86_CR0_WP; | |
1472 | } else if (!is_paging(vcpu)) { | |
1473 | /* From nonpaging to paging */ | |
1474 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, | |
65267ea1 | 1475 | vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) & |
1439442c SY |
1476 | ~(CPU_BASED_CR3_LOAD_EXITING | |
1477 | CPU_BASED_CR3_STORE_EXITING)); | |
1478 | vcpu->arch.cr0 = cr0; | |
1479 | vmx_set_cr4(vcpu, vcpu->arch.cr4); | |
1480 | if (!(vcpu->arch.cr0 & X86_CR0_WP)) | |
1481 | *hw_cr0 &= ~X86_CR0_WP; | |
1482 | } | |
1483 | } | |
1484 | ||
1485 | static void ept_update_paging_mode_cr4(unsigned long *hw_cr4, | |
1486 | struct kvm_vcpu *vcpu) | |
1487 | { | |
1488 | if (!is_paging(vcpu)) { | |
1489 | *hw_cr4 &= ~X86_CR4_PAE; | |
1490 | *hw_cr4 |= X86_CR4_PSE; | |
1491 | } else if (!(vcpu->arch.cr4 & X86_CR4_PAE)) | |
1492 | *hw_cr4 &= ~X86_CR4_PAE; | |
1493 | } | |
1494 | ||
6aa8b732 AK |
1495 | static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) |
1496 | { | |
1439442c SY |
1497 | unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | |
1498 | KVM_VM_CR0_ALWAYS_ON; | |
1499 | ||
5fd86fcf AK |
1500 | vmx_fpu_deactivate(vcpu); |
1501 | ||
ad312c7c | 1502 | if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1503 | enter_pmode(vcpu); |
1504 | ||
ad312c7c | 1505 | if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE)) |
6aa8b732 AK |
1506 | enter_rmode(vcpu); |
1507 | ||
05b3e0c2 | 1508 | #ifdef CONFIG_X86_64 |
ad312c7c | 1509 | if (vcpu->arch.shadow_efer & EFER_LME) { |
707d92fa | 1510 | if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) |
6aa8b732 | 1511 | enter_lmode(vcpu); |
707d92fa | 1512 | if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) |
6aa8b732 AK |
1513 | exit_lmode(vcpu); |
1514 | } | |
1515 | #endif | |
1516 | ||
1439442c SY |
1517 | if (vm_need_ept()) |
1518 | ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); | |
1519 | ||
6aa8b732 | 1520 | vmcs_writel(CR0_READ_SHADOW, cr0); |
1439442c | 1521 | vmcs_writel(GUEST_CR0, hw_cr0); |
ad312c7c | 1522 | vcpu->arch.cr0 = cr0; |
5fd86fcf | 1523 | |
707d92fa | 1524 | if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE)) |
5fd86fcf | 1525 | vmx_fpu_activate(vcpu); |
6aa8b732 AK |
1526 | } |
1527 | ||
1439442c SY |
1528 | static u64 construct_eptp(unsigned long root_hpa) |
1529 | { | |
1530 | u64 eptp; | |
1531 | ||
1532 | /* TODO write the value reading from MSR */ | |
1533 | eptp = VMX_EPT_DEFAULT_MT | | |
1534 | VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT; | |
1535 | eptp |= (root_hpa & PAGE_MASK); | |
1536 | ||
1537 | return eptp; | |
1538 | } | |
1539 | ||
6aa8b732 AK |
1540 | static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) |
1541 | { | |
1439442c SY |
1542 | unsigned long guest_cr3; |
1543 | u64 eptp; | |
1544 | ||
1545 | guest_cr3 = cr3; | |
1546 | if (vm_need_ept()) { | |
1547 | eptp = construct_eptp(cr3); | |
1548 | vmcs_write64(EPT_POINTER, eptp); | |
1549 | ept_sync_context(eptp); | |
1550 | ept_load_pdptrs(vcpu); | |
1551 | guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 : | |
1552 | VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
1553 | } | |
1554 | ||
2384d2b3 | 1555 | vmx_flush_tlb(vcpu); |
1439442c | 1556 | vmcs_writel(GUEST_CR3, guest_cr3); |
ad312c7c | 1557 | if (vcpu->arch.cr0 & X86_CR0_PE) |
5fd86fcf | 1558 | vmx_fpu_deactivate(vcpu); |
6aa8b732 AK |
1559 | } |
1560 | ||
1561 | static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) | |
1562 | { | |
1439442c SY |
1563 | unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ? |
1564 | KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON); | |
1565 | ||
ad312c7c | 1566 | vcpu->arch.cr4 = cr4; |
1439442c SY |
1567 | if (vm_need_ept()) |
1568 | ept_update_paging_mode_cr4(&hw_cr4, vcpu); | |
1569 | ||
1570 | vmcs_writel(CR4_READ_SHADOW, cr4); | |
1571 | vmcs_writel(GUEST_CR4, hw_cr4); | |
6aa8b732 AK |
1572 | } |
1573 | ||
6aa8b732 AK |
1574 | static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) |
1575 | { | |
8b9cf98c RR |
1576 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1577 | struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); | |
6aa8b732 | 1578 | |
ad312c7c | 1579 | vcpu->arch.shadow_efer = efer; |
9f62e19a JR |
1580 | if (!msr) |
1581 | return; | |
6aa8b732 AK |
1582 | if (efer & EFER_LMA) { |
1583 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1584 | vmcs_read32(VM_ENTRY_CONTROLS) | | |
1e4e6e00 | 1585 | VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1586 | msr->data = efer; |
1587 | ||
1588 | } else { | |
1589 | vmcs_write32(VM_ENTRY_CONTROLS, | |
1590 | vmcs_read32(VM_ENTRY_CONTROLS) & | |
1e4e6e00 | 1591 | ~VM_ENTRY_IA32E_MODE); |
6aa8b732 AK |
1592 | |
1593 | msr->data = efer & ~EFER_LME; | |
1594 | } | |
8b9cf98c | 1595 | setup_msrs(vmx); |
6aa8b732 AK |
1596 | } |
1597 | ||
6aa8b732 AK |
1598 | static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) |
1599 | { | |
1600 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1601 | ||
1602 | return vmcs_readl(sf->base); | |
1603 | } | |
1604 | ||
1605 | static void vmx_get_segment(struct kvm_vcpu *vcpu, | |
1606 | struct kvm_segment *var, int seg) | |
1607 | { | |
1608 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1609 | u32 ar; | |
1610 | ||
1611 | var->base = vmcs_readl(sf->base); | |
1612 | var->limit = vmcs_read32(sf->limit); | |
1613 | var->selector = vmcs_read16(sf->selector); | |
1614 | ar = vmcs_read32(sf->ar_bytes); | |
1615 | if (ar & AR_UNUSABLE_MASK) | |
1616 | ar = 0; | |
1617 | var->type = ar & 15; | |
1618 | var->s = (ar >> 4) & 1; | |
1619 | var->dpl = (ar >> 5) & 3; | |
1620 | var->present = (ar >> 7) & 1; | |
1621 | var->avl = (ar >> 12) & 1; | |
1622 | var->l = (ar >> 13) & 1; | |
1623 | var->db = (ar >> 14) & 1; | |
1624 | var->g = (ar >> 15) & 1; | |
1625 | var->unusable = (ar >> 16) & 1; | |
1626 | } | |
1627 | ||
2e4d2653 IE |
1628 | static int vmx_get_cpl(struct kvm_vcpu *vcpu) |
1629 | { | |
1630 | struct kvm_segment kvm_seg; | |
1631 | ||
1632 | if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */ | |
1633 | return 0; | |
1634 | ||
1635 | if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */ | |
1636 | return 3; | |
1637 | ||
1638 | vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS); | |
1639 | return kvm_seg.selector & 3; | |
1640 | } | |
1641 | ||
653e3108 | 1642 | static u32 vmx_segment_access_rights(struct kvm_segment *var) |
6aa8b732 | 1643 | { |
6aa8b732 AK |
1644 | u32 ar; |
1645 | ||
653e3108 | 1646 | if (var->unusable) |
6aa8b732 AK |
1647 | ar = 1 << 16; |
1648 | else { | |
1649 | ar = var->type & 15; | |
1650 | ar |= (var->s & 1) << 4; | |
1651 | ar |= (var->dpl & 3) << 5; | |
1652 | ar |= (var->present & 1) << 7; | |
1653 | ar |= (var->avl & 1) << 12; | |
1654 | ar |= (var->l & 1) << 13; | |
1655 | ar |= (var->db & 1) << 14; | |
1656 | ar |= (var->g & 1) << 15; | |
1657 | } | |
f7fbf1fd UL |
1658 | if (ar == 0) /* a 0 value means unusable */ |
1659 | ar = AR_UNUSABLE_MASK; | |
653e3108 AK |
1660 | |
1661 | return ar; | |
1662 | } | |
1663 | ||
1664 | static void vmx_set_segment(struct kvm_vcpu *vcpu, | |
1665 | struct kvm_segment *var, int seg) | |
1666 | { | |
1667 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1668 | u32 ar; | |
1669 | ||
ad312c7c ZX |
1670 | if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) { |
1671 | vcpu->arch.rmode.tr.selector = var->selector; | |
1672 | vcpu->arch.rmode.tr.base = var->base; | |
1673 | vcpu->arch.rmode.tr.limit = var->limit; | |
1674 | vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var); | |
653e3108 AK |
1675 | return; |
1676 | } | |
1677 | vmcs_writel(sf->base, var->base); | |
1678 | vmcs_write32(sf->limit, var->limit); | |
1679 | vmcs_write16(sf->selector, var->selector); | |
ad312c7c | 1680 | if (vcpu->arch.rmode.active && var->s) { |
653e3108 AK |
1681 | /* |
1682 | * Hack real-mode segments into vm86 compatibility. | |
1683 | */ | |
1684 | if (var->base == 0xffff0000 && var->selector == 0xf000) | |
1685 | vmcs_writel(sf->base, 0xf0000); | |
1686 | ar = 0xf3; | |
1687 | } else | |
1688 | ar = vmx_segment_access_rights(var); | |
6aa8b732 AK |
1689 | vmcs_write32(sf->ar_bytes, ar); |
1690 | } | |
1691 | ||
6aa8b732 AK |
1692 | static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) |
1693 | { | |
1694 | u32 ar = vmcs_read32(GUEST_CS_AR_BYTES); | |
1695 | ||
1696 | *db = (ar >> 14) & 1; | |
1697 | *l = (ar >> 13) & 1; | |
1698 | } | |
1699 | ||
1700 | static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1701 | { | |
1702 | dt->limit = vmcs_read32(GUEST_IDTR_LIMIT); | |
1703 | dt->base = vmcs_readl(GUEST_IDTR_BASE); | |
1704 | } | |
1705 | ||
1706 | static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1707 | { | |
1708 | vmcs_write32(GUEST_IDTR_LIMIT, dt->limit); | |
1709 | vmcs_writel(GUEST_IDTR_BASE, dt->base); | |
1710 | } | |
1711 | ||
1712 | static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1713 | { | |
1714 | dt->limit = vmcs_read32(GUEST_GDTR_LIMIT); | |
1715 | dt->base = vmcs_readl(GUEST_GDTR_BASE); | |
1716 | } | |
1717 | ||
1718 | static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt) | |
1719 | { | |
1720 | vmcs_write32(GUEST_GDTR_LIMIT, dt->limit); | |
1721 | vmcs_writel(GUEST_GDTR_BASE, dt->base); | |
1722 | } | |
1723 | ||
d77c26fc | 1724 | static int init_rmode_tss(struct kvm *kvm) |
6aa8b732 | 1725 | { |
6aa8b732 | 1726 | gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT; |
195aefde | 1727 | u16 data = 0; |
10589a46 | 1728 | int ret = 0; |
195aefde | 1729 | int r; |
6aa8b732 | 1730 | |
195aefde IE |
1731 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1732 | if (r < 0) | |
10589a46 | 1733 | goto out; |
195aefde | 1734 | data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; |
464d17c8 SY |
1735 | r = kvm_write_guest_page(kvm, fn++, &data, |
1736 | TSS_IOPB_BASE_OFFSET, sizeof(u16)); | |
195aefde | 1737 | if (r < 0) |
10589a46 | 1738 | goto out; |
195aefde IE |
1739 | r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); |
1740 | if (r < 0) | |
10589a46 | 1741 | goto out; |
195aefde IE |
1742 | r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); |
1743 | if (r < 0) | |
10589a46 | 1744 | goto out; |
195aefde | 1745 | data = ~0; |
10589a46 MT |
1746 | r = kvm_write_guest_page(kvm, fn, &data, |
1747 | RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, | |
1748 | sizeof(u8)); | |
195aefde | 1749 | if (r < 0) |
10589a46 MT |
1750 | goto out; |
1751 | ||
1752 | ret = 1; | |
1753 | out: | |
10589a46 | 1754 | return ret; |
6aa8b732 AK |
1755 | } |
1756 | ||
b7ebfb05 SY |
1757 | static int init_rmode_identity_map(struct kvm *kvm) |
1758 | { | |
1759 | int i, r, ret; | |
1760 | pfn_t identity_map_pfn; | |
1761 | u32 tmp; | |
1762 | ||
1763 | if (!vm_need_ept()) | |
1764 | return 1; | |
1765 | if (unlikely(!kvm->arch.ept_identity_pagetable)) { | |
1766 | printk(KERN_ERR "EPT: identity-mapping pagetable " | |
1767 | "haven't been allocated!\n"); | |
1768 | return 0; | |
1769 | } | |
1770 | if (likely(kvm->arch.ept_identity_pagetable_done)) | |
1771 | return 1; | |
1772 | ret = 0; | |
1773 | identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT; | |
1774 | r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); | |
1775 | if (r < 0) | |
1776 | goto out; | |
1777 | /* Set up identity-mapping pagetable for EPT in real mode */ | |
1778 | for (i = 0; i < PT32_ENT_PER_PAGE; i++) { | |
1779 | tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | | |
1780 | _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); | |
1781 | r = kvm_write_guest_page(kvm, identity_map_pfn, | |
1782 | &tmp, i * sizeof(tmp), sizeof(tmp)); | |
1783 | if (r < 0) | |
1784 | goto out; | |
1785 | } | |
1786 | kvm->arch.ept_identity_pagetable_done = true; | |
1787 | ret = 1; | |
1788 | out: | |
1789 | return ret; | |
1790 | } | |
1791 | ||
6aa8b732 AK |
1792 | static void seg_setup(int seg) |
1793 | { | |
1794 | struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; | |
1795 | ||
1796 | vmcs_write16(sf->selector, 0); | |
1797 | vmcs_writel(sf->base, 0); | |
1798 | vmcs_write32(sf->limit, 0xffff); | |
1799 | vmcs_write32(sf->ar_bytes, 0x93); | |
1800 | } | |
1801 | ||
f78e0e2e SY |
1802 | static int alloc_apic_access_page(struct kvm *kvm) |
1803 | { | |
1804 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1805 | int r = 0; | |
1806 | ||
72dc67a6 | 1807 | down_write(&kvm->slots_lock); |
bfc6d222 | 1808 | if (kvm->arch.apic_access_page) |
f78e0e2e SY |
1809 | goto out; |
1810 | kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT; | |
1811 | kvm_userspace_mem.flags = 0; | |
1812 | kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL; | |
1813 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
1814 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1815 | if (r) | |
1816 | goto out; | |
72dc67a6 IE |
1817 | |
1818 | down_read(¤t->mm->mmap_sem); | |
bfc6d222 | 1819 | kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00); |
72dc67a6 | 1820 | up_read(¤t->mm->mmap_sem); |
f78e0e2e | 1821 | out: |
72dc67a6 | 1822 | up_write(&kvm->slots_lock); |
f78e0e2e SY |
1823 | return r; |
1824 | } | |
1825 | ||
b7ebfb05 SY |
1826 | static int alloc_identity_pagetable(struct kvm *kvm) |
1827 | { | |
1828 | struct kvm_userspace_memory_region kvm_userspace_mem; | |
1829 | int r = 0; | |
1830 | ||
1831 | down_write(&kvm->slots_lock); | |
1832 | if (kvm->arch.ept_identity_pagetable) | |
1833 | goto out; | |
1834 | kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT; | |
1835 | kvm_userspace_mem.flags = 0; | |
1836 | kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; | |
1837 | kvm_userspace_mem.memory_size = PAGE_SIZE; | |
1838 | r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0); | |
1839 | if (r) | |
1840 | goto out; | |
1841 | ||
1842 | down_read(¤t->mm->mmap_sem); | |
1843 | kvm->arch.ept_identity_pagetable = gfn_to_page(kvm, | |
1844 | VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT); | |
1845 | up_read(¤t->mm->mmap_sem); | |
1846 | out: | |
1847 | up_write(&kvm->slots_lock); | |
1848 | return r; | |
1849 | } | |
1850 | ||
2384d2b3 SY |
1851 | static void allocate_vpid(struct vcpu_vmx *vmx) |
1852 | { | |
1853 | int vpid; | |
1854 | ||
1855 | vmx->vpid = 0; | |
1856 | if (!enable_vpid || !cpu_has_vmx_vpid()) | |
1857 | return; | |
1858 | spin_lock(&vmx_vpid_lock); | |
1859 | vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); | |
1860 | if (vpid < VMX_NR_VPIDS) { | |
1861 | vmx->vpid = vpid; | |
1862 | __set_bit(vpid, vmx_vpid_bitmap); | |
1863 | } | |
1864 | spin_unlock(&vmx_vpid_lock); | |
1865 | } | |
1866 | ||
8b2cf73c | 1867 | static void vmx_disable_intercept_for_msr(struct page *msr_bitmap, u32 msr) |
25c5f225 SY |
1868 | { |
1869 | void *va; | |
1870 | ||
1871 | if (!cpu_has_vmx_msr_bitmap()) | |
1872 | return; | |
1873 | ||
1874 | /* | |
1875 | * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals | |
1876 | * have the write-low and read-high bitmap offsets the wrong way round. | |
1877 | * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. | |
1878 | */ | |
1879 | va = kmap(msr_bitmap); | |
1880 | if (msr <= 0x1fff) { | |
1881 | __clear_bit(msr, va + 0x000); /* read-low */ | |
1882 | __clear_bit(msr, va + 0x800); /* write-low */ | |
1883 | } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { | |
1884 | msr &= 0x1fff; | |
1885 | __clear_bit(msr, va + 0x400); /* read-high */ | |
1886 | __clear_bit(msr, va + 0xc00); /* write-high */ | |
1887 | } | |
1888 | kunmap(msr_bitmap); | |
1889 | } | |
1890 | ||
6aa8b732 AK |
1891 | /* |
1892 | * Sets up the vmcs for emulated real mode. | |
1893 | */ | |
8b9cf98c | 1894 | static int vmx_vcpu_setup(struct vcpu_vmx *vmx) |
6aa8b732 AK |
1895 | { |
1896 | u32 host_sysenter_cs; | |
1897 | u32 junk; | |
1898 | unsigned long a; | |
1899 | struct descriptor_table dt; | |
1900 | int i; | |
cd2276a7 | 1901 | unsigned long kvm_vmx_return; |
6e5d865c | 1902 | u32 exec_control; |
6aa8b732 | 1903 | |
6aa8b732 | 1904 | /* I/O */ |
fdef3ad1 HQ |
1905 | vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a)); |
1906 | vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b)); | |
6aa8b732 | 1907 | |
25c5f225 SY |
1908 | if (cpu_has_vmx_msr_bitmap()) |
1909 | vmcs_write64(MSR_BITMAP, page_to_phys(vmx_msr_bitmap)); | |
1910 | ||
6aa8b732 AK |
1911 | vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ |
1912 | ||
6aa8b732 | 1913 | /* Control */ |
1c3d14fe YS |
1914 | vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, |
1915 | vmcs_config.pin_based_exec_ctrl); | |
6e5d865c YS |
1916 | |
1917 | exec_control = vmcs_config.cpu_based_exec_ctrl; | |
1918 | if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) { | |
1919 | exec_control &= ~CPU_BASED_TPR_SHADOW; | |
1920 | #ifdef CONFIG_X86_64 | |
1921 | exec_control |= CPU_BASED_CR8_STORE_EXITING | | |
1922 | CPU_BASED_CR8_LOAD_EXITING; | |
1923 | #endif | |
1924 | } | |
d56f546d SY |
1925 | if (!vm_need_ept()) |
1926 | exec_control |= CPU_BASED_CR3_STORE_EXITING | | |
1927 | CPU_BASED_CR3_LOAD_EXITING; | |
6e5d865c | 1928 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control); |
6aa8b732 | 1929 | |
83ff3b9d SY |
1930 | if (cpu_has_secondary_exec_ctrls()) { |
1931 | exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; | |
1932 | if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
1933 | exec_control &= | |
1934 | ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; | |
2384d2b3 SY |
1935 | if (vmx->vpid == 0) |
1936 | exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; | |
d56f546d SY |
1937 | if (!vm_need_ept()) |
1938 | exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; | |
83ff3b9d SY |
1939 | vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control); |
1940 | } | |
f78e0e2e | 1941 | |
c7addb90 AK |
1942 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf); |
1943 | vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf); | |
6aa8b732 AK |
1944 | vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ |
1945 | ||
1946 | vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */ | |
1947 | vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */ | |
1948 | vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */ | |
1949 | ||
1950 | vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ | |
1951 | vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
1952 | vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ | |
d6e88aec AK |
1953 | vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */ |
1954 | vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */ | |
6aa8b732 | 1955 | vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ |
05b3e0c2 | 1956 | #ifdef CONFIG_X86_64 |
6aa8b732 AK |
1957 | rdmsrl(MSR_FS_BASE, a); |
1958 | vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */ | |
1959 | rdmsrl(MSR_GS_BASE, a); | |
1960 | vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */ | |
1961 | #else | |
1962 | vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ | |
1963 | vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ | |
1964 | #endif | |
1965 | ||
1966 | vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ | |
1967 | ||
d6e88aec | 1968 | kvm_get_idt(&dt); |
6aa8b732 AK |
1969 | vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */ |
1970 | ||
d77c26fc | 1971 | asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return)); |
cd2276a7 | 1972 | vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */ |
2cc51560 ED |
1973 | vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); |
1974 | vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); | |
1975 | vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); | |
6aa8b732 AK |
1976 | |
1977 | rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk); | |
1978 | vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs); | |
1979 | rdmsrl(MSR_IA32_SYSENTER_ESP, a); | |
1980 | vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */ | |
1981 | rdmsrl(MSR_IA32_SYSENTER_EIP, a); | |
1982 | vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */ | |
1983 | ||
6aa8b732 AK |
1984 | for (i = 0; i < NR_VMX_MSR; ++i) { |
1985 | u32 index = vmx_msr_index[i]; | |
1986 | u32 data_low, data_high; | |
1987 | u64 data; | |
a2fa3e9f | 1988 | int j = vmx->nmsrs; |
6aa8b732 AK |
1989 | |
1990 | if (rdmsr_safe(index, &data_low, &data_high) < 0) | |
1991 | continue; | |
432bd6cb AK |
1992 | if (wrmsr_safe(index, data_low, data_high) < 0) |
1993 | continue; | |
6aa8b732 | 1994 | data = data_low | ((u64)data_high << 32); |
a2fa3e9f GH |
1995 | vmx->host_msrs[j].index = index; |
1996 | vmx->host_msrs[j].reserved = 0; | |
1997 | vmx->host_msrs[j].data = data; | |
1998 | vmx->guest_msrs[j] = vmx->host_msrs[j]; | |
1999 | ++vmx->nmsrs; | |
6aa8b732 | 2000 | } |
6aa8b732 | 2001 | |
1c3d14fe | 2002 | vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl); |
6aa8b732 AK |
2003 | |
2004 | /* 22.2.1, 20.8.1 */ | |
1c3d14fe YS |
2005 | vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl); |
2006 | ||
e00c8cf2 AK |
2007 | vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL); |
2008 | vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK); | |
2009 | ||
f78e0e2e | 2010 | |
e00c8cf2 AK |
2011 | return 0; |
2012 | } | |
2013 | ||
b7ebfb05 SY |
2014 | static int init_rmode(struct kvm *kvm) |
2015 | { | |
2016 | if (!init_rmode_tss(kvm)) | |
2017 | return 0; | |
2018 | if (!init_rmode_identity_map(kvm)) | |
2019 | return 0; | |
2020 | return 1; | |
2021 | } | |
2022 | ||
e00c8cf2 AK |
2023 | static int vmx_vcpu_reset(struct kvm_vcpu *vcpu) |
2024 | { | |
2025 | struct vcpu_vmx *vmx = to_vmx(vcpu); | |
2026 | u64 msr; | |
2027 | int ret; | |
2028 | ||
5fdbf976 | 2029 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
3200f405 | 2030 | down_read(&vcpu->kvm->slots_lock); |
b7ebfb05 | 2031 | if (!init_rmode(vmx->vcpu.kvm)) { |
e00c8cf2 AK |
2032 | ret = -ENOMEM; |
2033 | goto out; | |
2034 | } | |
2035 | ||
ad312c7c | 2036 | vmx->vcpu.arch.rmode.active = 0; |
e00c8cf2 | 2037 | |
ad312c7c | 2038 | vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); |
2d3ad1f4 | 2039 | kvm_set_cr8(&vmx->vcpu, 0); |
e00c8cf2 AK |
2040 | msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE; |
2041 | if (vmx->vcpu.vcpu_id == 0) | |
2042 | msr |= MSR_IA32_APICBASE_BSP; | |
2043 | kvm_set_apic_base(&vmx->vcpu, msr); | |
2044 | ||
2045 | fx_init(&vmx->vcpu); | |
2046 | ||
2047 | /* | |
2048 | * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode | |
2049 | * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh. | |
2050 | */ | |
2051 | if (vmx->vcpu.vcpu_id == 0) { | |
2052 | vmcs_write16(GUEST_CS_SELECTOR, 0xf000); | |
2053 | vmcs_writel(GUEST_CS_BASE, 0x000f0000); | |
2054 | } else { | |
ad312c7c ZX |
2055 | vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8); |
2056 | vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12); | |
e00c8cf2 AK |
2057 | } |
2058 | vmcs_write32(GUEST_CS_LIMIT, 0xffff); | |
2059 | vmcs_write32(GUEST_CS_AR_BYTES, 0x9b); | |
2060 | ||
2061 | seg_setup(VCPU_SREG_DS); | |
2062 | seg_setup(VCPU_SREG_ES); | |
2063 | seg_setup(VCPU_SREG_FS); | |
2064 | seg_setup(VCPU_SREG_GS); | |
2065 | seg_setup(VCPU_SREG_SS); | |
2066 | ||
2067 | vmcs_write16(GUEST_TR_SELECTOR, 0); | |
2068 | vmcs_writel(GUEST_TR_BASE, 0); | |
2069 | vmcs_write32(GUEST_TR_LIMIT, 0xffff); | |
2070 | vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); | |
2071 | ||
2072 | vmcs_write16(GUEST_LDTR_SELECTOR, 0); | |
2073 | vmcs_writel(GUEST_LDTR_BASE, 0); | |
2074 | vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); | |
2075 | vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); | |
2076 | ||
2077 | vmcs_write32(GUEST_SYSENTER_CS, 0); | |
2078 | vmcs_writel(GUEST_SYSENTER_ESP, 0); | |
2079 | vmcs_writel(GUEST_SYSENTER_EIP, 0); | |
2080 | ||
2081 | vmcs_writel(GUEST_RFLAGS, 0x02); | |
2082 | if (vmx->vcpu.vcpu_id == 0) | |
5fdbf976 | 2083 | kvm_rip_write(vcpu, 0xfff0); |
e00c8cf2 | 2084 | else |
5fdbf976 MT |
2085 | kvm_rip_write(vcpu, 0); |
2086 | kvm_register_write(vcpu, VCPU_REGS_RSP, 0); | |
e00c8cf2 AK |
2087 | |
2088 | /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */ | |
2089 | vmcs_writel(GUEST_DR7, 0x400); | |
2090 | ||
2091 | vmcs_writel(GUEST_GDTR_BASE, 0); | |
2092 | vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); | |
2093 | ||
2094 | vmcs_writel(GUEST_IDTR_BASE, 0); | |
2095 | vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); | |
2096 | ||
2097 | vmcs_write32(GUEST_ACTIVITY_STATE, 0); | |
2098 | vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); | |
2099 | vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0); | |
2100 | ||
2101 | guest_write_tsc(0); | |
2102 | ||
2103 | /* Special registers */ | |
2104 | vmcs_write64(GUEST_IA32_DEBUGCTL, 0); | |
2105 | ||
2106 | setup_msrs(vmx); | |
2107 | ||
6aa8b732 AK |
2108 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ |
2109 | ||
f78e0e2e SY |
2110 | if (cpu_has_vmx_tpr_shadow()) { |
2111 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); | |
2112 | if (vm_need_tpr_shadow(vmx->vcpu.kvm)) | |
2113 | vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, | |
ad312c7c | 2114 | page_to_phys(vmx->vcpu.arch.apic->regs_page)); |
f78e0e2e SY |
2115 | vmcs_write32(TPR_THRESHOLD, 0); |
2116 | } | |
2117 | ||
2118 | if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm)) | |
2119 | vmcs_write64(APIC_ACCESS_ADDR, | |
bfc6d222 | 2120 | page_to_phys(vmx->vcpu.kvm->arch.apic_access_page)); |
6aa8b732 | 2121 | |
2384d2b3 SY |
2122 | if (vmx->vpid != 0) |
2123 | vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); | |
2124 | ||
ad312c7c ZX |
2125 | vmx->vcpu.arch.cr0 = 0x60000010; |
2126 | vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */ | |
8b9cf98c | 2127 | vmx_set_cr4(&vmx->vcpu, 0); |
8b9cf98c | 2128 | vmx_set_efer(&vmx->vcpu, 0); |
8b9cf98c RR |
2129 | vmx_fpu_activate(&vmx->vcpu); |
2130 | update_exception_bitmap(&vmx->vcpu); | |
6aa8b732 | 2131 | |
2384d2b3 SY |
2132 | vpid_sync_vcpu_all(vmx); |
2133 | ||
3200f405 | 2134 | ret = 0; |
6aa8b732 | 2135 | |
6aa8b732 | 2136 | out: |
3200f405 | 2137 | up_read(&vcpu->kvm->slots_lock); |
6aa8b732 AK |
2138 | return ret; |
2139 | } | |
2140 | ||
85f455f7 ED |
2141 | static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq) |
2142 | { | |
9c8cba37 AK |
2143 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
2144 | ||
2714d1d3 FEL |
2145 | KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler); |
2146 | ||
ad312c7c | 2147 | if (vcpu->arch.rmode.active) { |
9c8cba37 AK |
2148 | vmx->rmode.irq.pending = true; |
2149 | vmx->rmode.irq.vector = irq; | |
5fdbf976 | 2150 | vmx->rmode.irq.rip = kvm_rip_read(vcpu); |
9c5623e3 AK |
2151 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, |
2152 | irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK); | |
2153 | vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1); | |
5fdbf976 | 2154 | kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1); |
85f455f7 ED |
2155 | return; |
2156 | } | |
2157 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2158 | irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK); | |
2159 | } | |
2160 | ||
f08864b4 SY |
2161 | static void vmx_inject_nmi(struct kvm_vcpu *vcpu) |
2162 | { | |
2163 | vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, | |
2164 | INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); | |
f08864b4 SY |
2165 | } |
2166 | ||
6aa8b732 AK |
2167 | static void kvm_do_inject_irq(struct kvm_vcpu *vcpu) |
2168 | { | |
ad312c7c ZX |
2169 | int word_index = __ffs(vcpu->arch.irq_summary); |
2170 | int bit_index = __ffs(vcpu->arch.irq_pending[word_index]); | |
6aa8b732 AK |
2171 | int irq = word_index * BITS_PER_LONG + bit_index; |
2172 | ||
ad312c7c ZX |
2173 | clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]); |
2174 | if (!vcpu->arch.irq_pending[word_index]) | |
2175 | clear_bit(word_index, &vcpu->arch.irq_summary); | |
ecfc79c7 | 2176 | kvm_queue_interrupt(vcpu, irq); |
6aa8b732 AK |
2177 | } |
2178 | ||
c1150d8c DL |
2179 | |
2180 | static void do_interrupt_requests(struct kvm_vcpu *vcpu, | |
2181 | struct kvm_run *kvm_run) | |
6aa8b732 | 2182 | { |
c1150d8c DL |
2183 | u32 cpu_based_vm_exec_control; |
2184 | ||
ad312c7c | 2185 | vcpu->arch.interrupt_window_open = |
c1150d8c DL |
2186 | ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && |
2187 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0); | |
2188 | ||
ad312c7c | 2189 | if (vcpu->arch.interrupt_window_open && |
ecfc79c7 | 2190 | vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending) |
6aa8b732 | 2191 | kvm_do_inject_irq(vcpu); |
c1150d8c | 2192 | |
ecfc79c7 AK |
2193 | if (vcpu->arch.interrupt_window_open && vcpu->arch.interrupt.pending) |
2194 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | |
2195 | ||
c1150d8c | 2196 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); |
ad312c7c ZX |
2197 | if (!vcpu->arch.interrupt_window_open && |
2198 | (vcpu->arch.irq_summary || kvm_run->request_interrupt_window)) | |
6aa8b732 AK |
2199 | /* |
2200 | * Interrupts blocked. Wait for unblock. | |
2201 | */ | |
c1150d8c DL |
2202 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; |
2203 | else | |
2204 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2205 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
6aa8b732 AK |
2206 | } |
2207 | ||
cbc94022 IE |
2208 | static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) |
2209 | { | |
2210 | int ret; | |
2211 | struct kvm_userspace_memory_region tss_mem = { | |
2212 | .slot = 8, | |
2213 | .guest_phys_addr = addr, | |
2214 | .memory_size = PAGE_SIZE * 3, | |
2215 | .flags = 0, | |
2216 | }; | |
2217 | ||
2218 | ret = kvm_set_memory_region(kvm, &tss_mem, 0); | |
2219 | if (ret) | |
2220 | return ret; | |
bfc6d222 | 2221 | kvm->arch.tss_addr = addr; |
cbc94022 IE |
2222 | return 0; |
2223 | } | |
2224 | ||
6aa8b732 AK |
2225 | static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu) |
2226 | { | |
2227 | struct kvm_guest_debug *dbg = &vcpu->guest_debug; | |
2228 | ||
2229 | set_debugreg(dbg->bp[0], 0); | |
2230 | set_debugreg(dbg->bp[1], 1); | |
2231 | set_debugreg(dbg->bp[2], 2); | |
2232 | set_debugreg(dbg->bp[3], 3); | |
2233 | ||
2234 | if (dbg->singlestep) { | |
2235 | unsigned long flags; | |
2236 | ||
2237 | flags = vmcs_readl(GUEST_RFLAGS); | |
2238 | flags |= X86_EFLAGS_TF | X86_EFLAGS_RF; | |
2239 | vmcs_writel(GUEST_RFLAGS, flags); | |
2240 | } | |
2241 | } | |
2242 | ||
2243 | static int handle_rmode_exception(struct kvm_vcpu *vcpu, | |
2244 | int vec, u32 err_code) | |
2245 | { | |
b3f37707 NK |
2246 | /* |
2247 | * Instruction with address size override prefix opcode 0x67 | |
2248 | * Cause the #SS fault with 0 error code in VM86 mode. | |
2249 | */ | |
2250 | if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) | |
3427318f | 2251 | if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE) |
6aa8b732 | 2252 | return 1; |
77ab6db0 JK |
2253 | /* |
2254 | * Forward all other exceptions that are valid in real mode. | |
2255 | * FIXME: Breaks guest debugging in real mode, needs to be fixed with | |
2256 | * the required debugging infrastructure rework. | |
2257 | */ | |
2258 | switch (vec) { | |
2259 | case DE_VECTOR: | |
2260 | case DB_VECTOR: | |
2261 | case BP_VECTOR: | |
2262 | case OF_VECTOR: | |
2263 | case BR_VECTOR: | |
2264 | case UD_VECTOR: | |
2265 | case DF_VECTOR: | |
2266 | case SS_VECTOR: | |
2267 | case GP_VECTOR: | |
2268 | case MF_VECTOR: | |
2269 | kvm_queue_exception(vcpu, vec); | |
2270 | return 1; | |
2271 | } | |
6aa8b732 AK |
2272 | return 0; |
2273 | } | |
2274 | ||
2275 | static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2276 | { | |
1155f76a | 2277 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
6aa8b732 AK |
2278 | u32 intr_info, error_code; |
2279 | unsigned long cr2, rip; | |
2280 | u32 vect_info; | |
2281 | enum emulation_result er; | |
2282 | ||
1155f76a | 2283 | vect_info = vmx->idt_vectoring_info; |
6aa8b732 AK |
2284 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); |
2285 | ||
2286 | if ((vect_info & VECTORING_INFO_VALID_MASK) && | |
d77c26fc | 2287 | !is_page_fault(intr_info)) |
6aa8b732 | 2288 | printk(KERN_ERR "%s: unexpected, vectoring info 0x%x " |
b8688d51 | 2289 | "intr info 0x%x\n", __func__, vect_info, intr_info); |
6aa8b732 | 2290 | |
85f455f7 | 2291 | if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) { |
6aa8b732 | 2292 | int irq = vect_info & VECTORING_INFO_VECTOR_MASK; |
ad312c7c ZX |
2293 | set_bit(irq, vcpu->arch.irq_pending); |
2294 | set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary); | |
6aa8b732 AK |
2295 | } |
2296 | ||
1b6269db AK |
2297 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */ |
2298 | return 1; /* already handled by vmx_vcpu_run() */ | |
2ab455cc AL |
2299 | |
2300 | if (is_no_device(intr_info)) { | |
5fd86fcf | 2301 | vmx_fpu_activate(vcpu); |
2ab455cc AL |
2302 | return 1; |
2303 | } | |
2304 | ||
7aa81cc0 | 2305 | if (is_invalid_opcode(intr_info)) { |
571008da | 2306 | er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD); |
7aa81cc0 | 2307 | if (er != EMULATE_DONE) |
7ee5d940 | 2308 | kvm_queue_exception(vcpu, UD_VECTOR); |
7aa81cc0 AL |
2309 | return 1; |
2310 | } | |
2311 | ||
6aa8b732 | 2312 | error_code = 0; |
5fdbf976 | 2313 | rip = kvm_rip_read(vcpu); |
2e11384c | 2314 | if (intr_info & INTR_INFO_DELIVER_CODE_MASK) |
6aa8b732 AK |
2315 | error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); |
2316 | if (is_page_fault(intr_info)) { | |
1439442c SY |
2317 | /* EPT won't cause page fault directly */ |
2318 | if (vm_need_ept()) | |
2319 | BUG(); | |
6aa8b732 | 2320 | cr2 = vmcs_readl(EXIT_QUALIFICATION); |
2714d1d3 FEL |
2321 | KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2, |
2322 | (u32)((u64)cr2 >> 32), handler); | |
f7d9238f | 2323 | if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending) |
577bdc49 | 2324 | kvm_mmu_unprotect_page_virt(vcpu, cr2); |
3067714c | 2325 | return kvm_mmu_page_fault(vcpu, cr2, error_code); |
6aa8b732 AK |
2326 | } |
2327 | ||
ad312c7c | 2328 | if (vcpu->arch.rmode.active && |
6aa8b732 | 2329 | handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK, |
72d6e5a0 | 2330 | error_code)) { |
ad312c7c ZX |
2331 | if (vcpu->arch.halt_request) { |
2332 | vcpu->arch.halt_request = 0; | |
72d6e5a0 AK |
2333 | return kvm_emulate_halt(vcpu); |
2334 | } | |
6aa8b732 | 2335 | return 1; |
72d6e5a0 | 2336 | } |
6aa8b732 | 2337 | |
d77c26fc MD |
2338 | if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == |
2339 | (INTR_TYPE_EXCEPTION | 1)) { | |
6aa8b732 AK |
2340 | kvm_run->exit_reason = KVM_EXIT_DEBUG; |
2341 | return 0; | |
2342 | } | |
2343 | kvm_run->exit_reason = KVM_EXIT_EXCEPTION; | |
2344 | kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK; | |
2345 | kvm_run->ex.error_code = error_code; | |
2346 | return 0; | |
2347 | } | |
2348 | ||
2349 | static int handle_external_interrupt(struct kvm_vcpu *vcpu, | |
2350 | struct kvm_run *kvm_run) | |
2351 | { | |
1165f5fe | 2352 | ++vcpu->stat.irq_exits; |
2714d1d3 | 2353 | KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler); |
6aa8b732 AK |
2354 | return 1; |
2355 | } | |
2356 | ||
988ad74f AK |
2357 | static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2358 | { | |
2359 | kvm_run->exit_reason = KVM_EXIT_SHUTDOWN; | |
2360 | return 0; | |
2361 | } | |
6aa8b732 | 2362 | |
6aa8b732 AK |
2363 | static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2364 | { | |
bfdaab09 | 2365 | unsigned long exit_qualification; |
039576c0 AK |
2366 | int size, down, in, string, rep; |
2367 | unsigned port; | |
6aa8b732 | 2368 | |
1165f5fe | 2369 | ++vcpu->stat.io_exits; |
bfdaab09 | 2370 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
039576c0 | 2371 | string = (exit_qualification & 16) != 0; |
e70669ab LV |
2372 | |
2373 | if (string) { | |
3427318f LV |
2374 | if (emulate_instruction(vcpu, |
2375 | kvm_run, 0, 0, 0) == EMULATE_DO_MMIO) | |
e70669ab LV |
2376 | return 0; |
2377 | return 1; | |
2378 | } | |
2379 | ||
2380 | size = (exit_qualification & 7) + 1; | |
2381 | in = (exit_qualification & 8) != 0; | |
039576c0 | 2382 | down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0; |
039576c0 AK |
2383 | rep = (exit_qualification & 32) != 0; |
2384 | port = exit_qualification >> 16; | |
e70669ab | 2385 | |
3090dd73 | 2386 | return kvm_emulate_pio(vcpu, kvm_run, in, size, port); |
6aa8b732 AK |
2387 | } |
2388 | ||
102d8325 IM |
2389 | static void |
2390 | vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) | |
2391 | { | |
2392 | /* | |
2393 | * Patch in the VMCALL instruction: | |
2394 | */ | |
2395 | hypercall[0] = 0x0f; | |
2396 | hypercall[1] = 0x01; | |
2397 | hypercall[2] = 0xc1; | |
102d8325 IM |
2398 | } |
2399 | ||
6aa8b732 AK |
2400 | static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2401 | { | |
bfdaab09 | 2402 | unsigned long exit_qualification; |
6aa8b732 AK |
2403 | int cr; |
2404 | int reg; | |
2405 | ||
bfdaab09 | 2406 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2407 | cr = exit_qualification & 15; |
2408 | reg = (exit_qualification >> 8) & 15; | |
2409 | switch ((exit_qualification >> 4) & 3) { | |
2410 | case 0: /* mov to cr */ | |
5fdbf976 MT |
2411 | KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, |
2412 | (u32)kvm_register_read(vcpu, reg), | |
2413 | (u32)((u64)kvm_register_read(vcpu, reg) >> 32), | |
2414 | handler); | |
6aa8b732 AK |
2415 | switch (cr) { |
2416 | case 0: | |
5fdbf976 | 2417 | kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2418 | skip_emulated_instruction(vcpu); |
2419 | return 1; | |
2420 | case 3: | |
5fdbf976 | 2421 | kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2422 | skip_emulated_instruction(vcpu); |
2423 | return 1; | |
2424 | case 4: | |
5fdbf976 | 2425 | kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 AK |
2426 | skip_emulated_instruction(vcpu); |
2427 | return 1; | |
2428 | case 8: | |
5fdbf976 | 2429 | kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg)); |
6aa8b732 | 2430 | skip_emulated_instruction(vcpu); |
e5314067 AK |
2431 | if (irqchip_in_kernel(vcpu->kvm)) |
2432 | return 1; | |
253abdee YS |
2433 | kvm_run->exit_reason = KVM_EXIT_SET_TPR; |
2434 | return 0; | |
6aa8b732 AK |
2435 | }; |
2436 | break; | |
25c4c276 | 2437 | case 2: /* clts */ |
5fd86fcf | 2438 | vmx_fpu_deactivate(vcpu); |
ad312c7c ZX |
2439 | vcpu->arch.cr0 &= ~X86_CR0_TS; |
2440 | vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0); | |
5fd86fcf | 2441 | vmx_fpu_activate(vcpu); |
2714d1d3 | 2442 | KVMTRACE_0D(CLTS, vcpu, handler); |
25c4c276 AL |
2443 | skip_emulated_instruction(vcpu); |
2444 | return 1; | |
6aa8b732 AK |
2445 | case 1: /*mov from cr*/ |
2446 | switch (cr) { | |
2447 | case 3: | |
5fdbf976 | 2448 | kvm_register_write(vcpu, reg, vcpu->arch.cr3); |
2714d1d3 | 2449 | KVMTRACE_3D(CR_READ, vcpu, (u32)cr, |
5fdbf976 MT |
2450 | (u32)kvm_register_read(vcpu, reg), |
2451 | (u32)((u64)kvm_register_read(vcpu, reg) >> 32), | |
2714d1d3 | 2452 | handler); |
6aa8b732 AK |
2453 | skip_emulated_instruction(vcpu); |
2454 | return 1; | |
2455 | case 8: | |
5fdbf976 | 2456 | kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu)); |
2714d1d3 | 2457 | KVMTRACE_2D(CR_READ, vcpu, (u32)cr, |
5fdbf976 | 2458 | (u32)kvm_register_read(vcpu, reg), handler); |
6aa8b732 AK |
2459 | skip_emulated_instruction(vcpu); |
2460 | return 1; | |
2461 | } | |
2462 | break; | |
2463 | case 3: /* lmsw */ | |
2d3ad1f4 | 2464 | kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f); |
6aa8b732 AK |
2465 | |
2466 | skip_emulated_instruction(vcpu); | |
2467 | return 1; | |
2468 | default: | |
2469 | break; | |
2470 | } | |
2471 | kvm_run->exit_reason = 0; | |
f0242478 | 2472 | pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n", |
6aa8b732 AK |
2473 | (int)(exit_qualification >> 4) & 3, cr); |
2474 | return 0; | |
2475 | } | |
2476 | ||
2477 | static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2478 | { | |
bfdaab09 | 2479 | unsigned long exit_qualification; |
6aa8b732 AK |
2480 | unsigned long val; |
2481 | int dr, reg; | |
2482 | ||
2483 | /* | |
2484 | * FIXME: this code assumes the host is debugging the guest. | |
2485 | * need to deal with guest debugging itself too. | |
2486 | */ | |
bfdaab09 | 2487 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); |
6aa8b732 AK |
2488 | dr = exit_qualification & 7; |
2489 | reg = (exit_qualification >> 8) & 15; | |
6aa8b732 AK |
2490 | if (exit_qualification & 16) { |
2491 | /* mov from dr */ | |
2492 | switch (dr) { | |
2493 | case 6: | |
2494 | val = 0xffff0ff0; | |
2495 | break; | |
2496 | case 7: | |
2497 | val = 0x400; | |
2498 | break; | |
2499 | default: | |
2500 | val = 0; | |
2501 | } | |
5fdbf976 | 2502 | kvm_register_write(vcpu, reg, val); |
2714d1d3 | 2503 | KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler); |
6aa8b732 AK |
2504 | } else { |
2505 | /* mov to dr */ | |
2506 | } | |
6aa8b732 AK |
2507 | skip_emulated_instruction(vcpu); |
2508 | return 1; | |
2509 | } | |
2510 | ||
2511 | static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2512 | { | |
06465c5a AK |
2513 | kvm_emulate_cpuid(vcpu); |
2514 | return 1; | |
6aa8b732 AK |
2515 | } |
2516 | ||
2517 | static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2518 | { | |
ad312c7c | 2519 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
6aa8b732 AK |
2520 | u64 data; |
2521 | ||
2522 | if (vmx_get_msr(vcpu, ecx, &data)) { | |
c1a5d4f9 | 2523 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2524 | return 1; |
2525 | } | |
2526 | ||
2714d1d3 FEL |
2527 | KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2528 | handler); | |
2529 | ||
6aa8b732 | 2530 | /* FIXME: handling of bits 32:63 of rax, rdx */ |
ad312c7c ZX |
2531 | vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u; |
2532 | vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u; | |
6aa8b732 AK |
2533 | skip_emulated_instruction(vcpu); |
2534 | return 1; | |
2535 | } | |
2536 | ||
2537 | static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2538 | { | |
ad312c7c ZX |
2539 | u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX]; |
2540 | u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u) | |
2541 | | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32); | |
6aa8b732 | 2542 | |
2714d1d3 FEL |
2543 | KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32), |
2544 | handler); | |
2545 | ||
6aa8b732 | 2546 | if (vmx_set_msr(vcpu, ecx, data) != 0) { |
c1a5d4f9 | 2547 | kvm_inject_gp(vcpu, 0); |
6aa8b732 AK |
2548 | return 1; |
2549 | } | |
2550 | ||
2551 | skip_emulated_instruction(vcpu); | |
2552 | return 1; | |
2553 | } | |
2554 | ||
6e5d865c YS |
2555 | static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu, |
2556 | struct kvm_run *kvm_run) | |
2557 | { | |
2558 | return 1; | |
2559 | } | |
2560 | ||
6aa8b732 AK |
2561 | static int handle_interrupt_window(struct kvm_vcpu *vcpu, |
2562 | struct kvm_run *kvm_run) | |
2563 | { | |
85f455f7 ED |
2564 | u32 cpu_based_vm_exec_control; |
2565 | ||
2566 | /* clear pending irq */ | |
2567 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2568 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING; | |
2569 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2714d1d3 FEL |
2570 | |
2571 | KVMTRACE_0D(PEND_INTR, vcpu, handler); | |
2572 | ||
c1150d8c DL |
2573 | /* |
2574 | * If the user space waits to inject interrupts, exit as soon as | |
2575 | * possible | |
2576 | */ | |
2577 | if (kvm_run->request_interrupt_window && | |
ad312c7c | 2578 | !vcpu->arch.irq_summary) { |
c1150d8c | 2579 | kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN; |
1165f5fe | 2580 | ++vcpu->stat.irq_window_exits; |
c1150d8c DL |
2581 | return 0; |
2582 | } | |
6aa8b732 AK |
2583 | return 1; |
2584 | } | |
2585 | ||
2586 | static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) | |
2587 | { | |
2588 | skip_emulated_instruction(vcpu); | |
d3bef15f | 2589 | return kvm_emulate_halt(vcpu); |
6aa8b732 AK |
2590 | } |
2591 | ||
c21415e8 IM |
2592 | static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2593 | { | |
510043da | 2594 | skip_emulated_instruction(vcpu); |
7aa81cc0 AL |
2595 | kvm_emulate_hypercall(vcpu); |
2596 | return 1; | |
c21415e8 IM |
2597 | } |
2598 | ||
e5edaa01 ED |
2599 | static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2600 | { | |
2601 | skip_emulated_instruction(vcpu); | |
2602 | /* TODO: Add support for VT-d/pass-through device */ | |
2603 | return 1; | |
2604 | } | |
2605 | ||
f78e0e2e SY |
2606 | static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2607 | { | |
2608 | u64 exit_qualification; | |
2609 | enum emulation_result er; | |
2610 | unsigned long offset; | |
2611 | ||
2612 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2613 | offset = exit_qualification & 0xffful; | |
2614 | ||
2615 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2616 | ||
2617 | if (er != EMULATE_DONE) { | |
2618 | printk(KERN_ERR | |
2619 | "Fail to handle apic access vmexit! Offset is 0x%lx\n", | |
2620 | offset); | |
2621 | return -ENOTSUPP; | |
2622 | } | |
2623 | return 1; | |
2624 | } | |
2625 | ||
37817f29 IE |
2626 | static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2627 | { | |
2628 | unsigned long exit_qualification; | |
2629 | u16 tss_selector; | |
2630 | int reason; | |
2631 | ||
2632 | exit_qualification = vmcs_readl(EXIT_QUALIFICATION); | |
2633 | ||
2634 | reason = (u32)exit_qualification >> 30; | |
2635 | tss_selector = exit_qualification; | |
2636 | ||
2637 | return kvm_task_switch(vcpu, tss_selector, reason); | |
2638 | } | |
2639 | ||
1439442c SY |
2640 | static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2641 | { | |
2642 | u64 exit_qualification; | |
2643 | enum emulation_result er; | |
2644 | gpa_t gpa; | |
2645 | unsigned long hva; | |
2646 | int gla_validity; | |
2647 | int r; | |
2648 | ||
2649 | exit_qualification = vmcs_read64(EXIT_QUALIFICATION); | |
2650 | ||
2651 | if (exit_qualification & (1 << 6)) { | |
2652 | printk(KERN_ERR "EPT: GPA exceeds GAW!\n"); | |
2653 | return -ENOTSUPP; | |
2654 | } | |
2655 | ||
2656 | gla_validity = (exit_qualification >> 7) & 0x3; | |
2657 | if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) { | |
2658 | printk(KERN_ERR "EPT: Handling EPT violation failed!\n"); | |
2659 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
2660 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
2661 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
2662 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
2663 | (long unsigned int)exit_qualification); | |
2664 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2665 | kvm_run->hw.hardware_exit_reason = 0; | |
2666 | return -ENOTSUPP; | |
2667 | } | |
2668 | ||
2669 | gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); | |
2670 | hva = gfn_to_hva(vcpu->kvm, gpa >> PAGE_SHIFT); | |
2671 | if (!kvm_is_error_hva(hva)) { | |
2672 | r = kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0); | |
2673 | if (r < 0) { | |
2674 | printk(KERN_ERR "EPT: Not enough memory!\n"); | |
2675 | return -ENOMEM; | |
2676 | } | |
2677 | return 1; | |
2678 | } else { | |
2679 | /* must be MMIO */ | |
2680 | er = emulate_instruction(vcpu, kvm_run, 0, 0, 0); | |
2681 | ||
2682 | if (er == EMULATE_FAIL) { | |
2683 | printk(KERN_ERR | |
2684 | "EPT: Fail to handle EPT violation vmexit!er is %d\n", | |
2685 | er); | |
2686 | printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n", | |
2687 | (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS), | |
2688 | (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS)); | |
2689 | printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n", | |
2690 | (long unsigned int)exit_qualification); | |
2691 | return -ENOTSUPP; | |
2692 | } else if (er == EMULATE_DO_MMIO) | |
2693 | return 0; | |
2694 | } | |
2695 | return 1; | |
2696 | } | |
2697 | ||
f08864b4 SY |
2698 | static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
2699 | { | |
2700 | u32 cpu_based_vm_exec_control; | |
2701 | ||
2702 | /* clear pending NMI */ | |
2703 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2704 | cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING; | |
2705 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2706 | ++vcpu->stat.nmi_window_exits; | |
2707 | ||
2708 | return 1; | |
2709 | } | |
2710 | ||
6aa8b732 AK |
2711 | /* |
2712 | * The exit handlers return 1 if the exit was handled fully and guest execution | |
2713 | * may resume. Otherwise they set the kvm_run parameter to indicate what needs | |
2714 | * to be done to userspace and return 0. | |
2715 | */ | |
2716 | static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu, | |
2717 | struct kvm_run *kvm_run) = { | |
2718 | [EXIT_REASON_EXCEPTION_NMI] = handle_exception, | |
2719 | [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, | |
988ad74f | 2720 | [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, |
f08864b4 | 2721 | [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, |
6aa8b732 | 2722 | [EXIT_REASON_IO_INSTRUCTION] = handle_io, |
6aa8b732 AK |
2723 | [EXIT_REASON_CR_ACCESS] = handle_cr, |
2724 | [EXIT_REASON_DR_ACCESS] = handle_dr, | |
2725 | [EXIT_REASON_CPUID] = handle_cpuid, | |
2726 | [EXIT_REASON_MSR_READ] = handle_rdmsr, | |
2727 | [EXIT_REASON_MSR_WRITE] = handle_wrmsr, | |
2728 | [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window, | |
2729 | [EXIT_REASON_HLT] = handle_halt, | |
c21415e8 | 2730 | [EXIT_REASON_VMCALL] = handle_vmcall, |
f78e0e2e SY |
2731 | [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, |
2732 | [EXIT_REASON_APIC_ACCESS] = handle_apic_access, | |
e5edaa01 | 2733 | [EXIT_REASON_WBINVD] = handle_wbinvd, |
37817f29 | 2734 | [EXIT_REASON_TASK_SWITCH] = handle_task_switch, |
1439442c | 2735 | [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, |
6aa8b732 AK |
2736 | }; |
2737 | ||
2738 | static const int kvm_vmx_max_exit_handlers = | |
50a3485c | 2739 | ARRAY_SIZE(kvm_vmx_exit_handlers); |
6aa8b732 AK |
2740 | |
2741 | /* | |
2742 | * The guest has exited. See if we can fix it or if we need userspace | |
2743 | * assistance. | |
2744 | */ | |
2745 | static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu) | |
2746 | { | |
6aa8b732 | 2747 | u32 exit_reason = vmcs_read32(VM_EXIT_REASON); |
29bd8a78 | 2748 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1155f76a | 2749 | u32 vectoring_info = vmx->idt_vectoring_info; |
29bd8a78 | 2750 | |
5fdbf976 MT |
2751 | KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu), |
2752 | (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit); | |
2714d1d3 | 2753 | |
1439442c SY |
2754 | /* Access CR3 don't cause VMExit in paging mode, so we need |
2755 | * to sync with guest real CR3. */ | |
2756 | if (vm_need_ept() && is_paging(vcpu)) { | |
2757 | vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); | |
2758 | ept_load_pdptrs(vcpu); | |
2759 | } | |
2760 | ||
29bd8a78 AK |
2761 | if (unlikely(vmx->fail)) { |
2762 | kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY; | |
2763 | kvm_run->fail_entry.hardware_entry_failure_reason | |
2764 | = vmcs_read32(VM_INSTRUCTION_ERROR); | |
2765 | return 0; | |
2766 | } | |
6aa8b732 | 2767 | |
d77c26fc | 2768 | if ((vectoring_info & VECTORING_INFO_VALID_MASK) && |
1439442c SY |
2769 | (exit_reason != EXIT_REASON_EXCEPTION_NMI && |
2770 | exit_reason != EXIT_REASON_EPT_VIOLATION)) | |
6aa8b732 | 2771 | printk(KERN_WARNING "%s: unexpected, valid vectoring info and " |
b8688d51 | 2772 | "exit reason is 0x%x\n", __func__, exit_reason); |
6aa8b732 AK |
2773 | if (exit_reason < kvm_vmx_max_exit_handlers |
2774 | && kvm_vmx_exit_handlers[exit_reason]) | |
2775 | return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run); | |
2776 | else { | |
2777 | kvm_run->exit_reason = KVM_EXIT_UNKNOWN; | |
2778 | kvm_run->hw.hardware_exit_reason = exit_reason; | |
2779 | } | |
2780 | return 0; | |
2781 | } | |
2782 | ||
6e5d865c YS |
2783 | static void update_tpr_threshold(struct kvm_vcpu *vcpu) |
2784 | { | |
2785 | int max_irr, tpr; | |
2786 | ||
2787 | if (!vm_need_tpr_shadow(vcpu->kvm)) | |
2788 | return; | |
2789 | ||
2790 | if (!kvm_lapic_enabled(vcpu) || | |
2791 | ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) { | |
2792 | vmcs_write32(TPR_THRESHOLD, 0); | |
2793 | return; | |
2794 | } | |
2795 | ||
2796 | tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4; | |
2797 | vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4); | |
2798 | } | |
2799 | ||
85f455f7 ED |
2800 | static void enable_irq_window(struct kvm_vcpu *vcpu) |
2801 | { | |
2802 | u32 cpu_based_vm_exec_control; | |
2803 | ||
2804 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2805 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; | |
2806 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2807 | } | |
2808 | ||
f08864b4 SY |
2809 | static void enable_nmi_window(struct kvm_vcpu *vcpu) |
2810 | { | |
2811 | u32 cpu_based_vm_exec_control; | |
2812 | ||
2813 | if (!cpu_has_virtual_nmis()) | |
2814 | return; | |
2815 | ||
2816 | cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); | |
2817 | cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING; | |
2818 | vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control); | |
2819 | } | |
2820 | ||
2821 | static int vmx_nmi_enabled(struct kvm_vcpu *vcpu) | |
2822 | { | |
2823 | u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2824 | return !(guest_intr & (GUEST_INTR_STATE_NMI | | |
2825 | GUEST_INTR_STATE_MOV_SS | | |
2826 | GUEST_INTR_STATE_STI)); | |
2827 | } | |
2828 | ||
2829 | static int vmx_irq_enabled(struct kvm_vcpu *vcpu) | |
2830 | { | |
2831 | u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); | |
2832 | return (!(guest_intr & (GUEST_INTR_STATE_MOV_SS | | |
2833 | GUEST_INTR_STATE_STI)) && | |
2834 | (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)); | |
2835 | } | |
2836 | ||
2837 | static void enable_intr_window(struct kvm_vcpu *vcpu) | |
2838 | { | |
2839 | if (vcpu->arch.nmi_pending) | |
2840 | enable_nmi_window(vcpu); | |
2841 | else if (kvm_cpu_has_interrupt(vcpu)) | |
2842 | enable_irq_window(vcpu); | |
2843 | } | |
2844 | ||
cf393f75 AK |
2845 | static void vmx_complete_interrupts(struct vcpu_vmx *vmx) |
2846 | { | |
2847 | u32 exit_intr_info; | |
668f612f | 2848 | u32 idt_vectoring_info; |
cf393f75 AK |
2849 | bool unblock_nmi; |
2850 | u8 vector; | |
668f612f AK |
2851 | int type; |
2852 | bool idtv_info_valid; | |
35920a35 | 2853 | u32 error; |
cf393f75 AK |
2854 | |
2855 | exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
2856 | if (cpu_has_virtual_nmis()) { | |
2857 | unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; | |
2858 | vector = exit_intr_info & INTR_INFO_VECTOR_MASK; | |
2859 | /* | |
2860 | * SDM 3: 25.7.1.2 | |
2861 | * Re-set bit "block by NMI" before VM entry if vmexit caused by | |
2862 | * a guest IRET fault. | |
2863 | */ | |
2864 | if (unblock_nmi && vector != DF_VECTOR) | |
2865 | vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2866 | GUEST_INTR_STATE_NMI); | |
2867 | } | |
668f612f AK |
2868 | |
2869 | idt_vectoring_info = vmx->idt_vectoring_info; | |
2870 | idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; | |
2871 | vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; | |
2872 | type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; | |
2873 | if (vmx->vcpu.arch.nmi_injected) { | |
2874 | /* | |
2875 | * SDM 3: 25.7.1.2 | |
2876 | * Clear bit "block by NMI" before VM entry if a NMI delivery | |
2877 | * faulted. | |
2878 | */ | |
2879 | if (idtv_info_valid && type == INTR_TYPE_NMI_INTR) | |
2880 | vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, | |
2881 | GUEST_INTR_STATE_NMI); | |
2882 | else | |
2883 | vmx->vcpu.arch.nmi_injected = false; | |
2884 | } | |
35920a35 AK |
2885 | kvm_clear_exception_queue(&vmx->vcpu); |
2886 | if (idtv_info_valid && type == INTR_TYPE_EXCEPTION) { | |
2887 | if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { | |
2888 | error = vmcs_read32(IDT_VECTORING_ERROR_CODE); | |
2889 | kvm_queue_exception_e(&vmx->vcpu, vector, error); | |
2890 | } else | |
2891 | kvm_queue_exception(&vmx->vcpu, vector); | |
2892 | vmx->idt_vectoring_info = 0; | |
2893 | } | |
f7d9238f AK |
2894 | kvm_clear_interrupt_queue(&vmx->vcpu); |
2895 | if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) { | |
2896 | kvm_queue_interrupt(&vmx->vcpu, vector); | |
2897 | vmx->idt_vectoring_info = 0; | |
2898 | } | |
cf393f75 AK |
2899 | } |
2900 | ||
85f455f7 ED |
2901 | static void vmx_intr_assist(struct kvm_vcpu *vcpu) |
2902 | { | |
f7d9238f | 2903 | u32 intr_info_field; |
85f455f7 | 2904 | |
6e5d865c YS |
2905 | update_tpr_threshold(vcpu); |
2906 | ||
85f455f7 | 2907 | intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD); |
f08864b4 | 2908 | if (cpu_has_virtual_nmis()) { |
668f612f AK |
2909 | if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) { |
2910 | if (vmx_nmi_enabled(vcpu)) { | |
2911 | vcpu->arch.nmi_pending = false; | |
2912 | vcpu->arch.nmi_injected = true; | |
2913 | } else { | |
2914 | enable_intr_window(vcpu); | |
2915 | return; | |
2916 | } | |
2917 | } | |
2918 | if (vcpu->arch.nmi_injected) { | |
2919 | vmx_inject_nmi(vcpu); | |
f08864b4 SY |
2920 | enable_intr_window(vcpu); |
2921 | return; | |
2922 | } | |
f08864b4 | 2923 | } |
f7d9238f AK |
2924 | if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) { |
2925 | if (vmx_irq_enabled(vcpu)) | |
2926 | kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu)); | |
2927 | else | |
2928 | enable_irq_window(vcpu); | |
2929 | } | |
2930 | if (vcpu->arch.interrupt.pending) { | |
2931 | vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr); | |
2932 | kvm_timer_intr_post(vcpu, vcpu->arch.interrupt.nr); | |
2933 | } | |
85f455f7 ED |
2934 | } |
2935 | ||
9c8cba37 AK |
2936 | /* |
2937 | * Failure to inject an interrupt should give us the information | |
2938 | * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs | |
2939 | * when fetching the interrupt redirection bitmap in the real-mode | |
2940 | * tss, this doesn't happen. So we do it ourselves. | |
2941 | */ | |
2942 | static void fixup_rmode_irq(struct vcpu_vmx *vmx) | |
2943 | { | |
2944 | vmx->rmode.irq.pending = 0; | |
5fdbf976 | 2945 | if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip) |
9c8cba37 | 2946 | return; |
5fdbf976 | 2947 | kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip); |
9c8cba37 AK |
2948 | if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) { |
2949 | vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK; | |
2950 | vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR; | |
2951 | return; | |
2952 | } | |
2953 | vmx->idt_vectoring_info = | |
2954 | VECTORING_INFO_VALID_MASK | |
2955 | | INTR_TYPE_EXT_INTR | |
2956 | | vmx->rmode.irq.vector; | |
2957 | } | |
2958 | ||
c801949d AK |
2959 | #ifdef CONFIG_X86_64 |
2960 | #define R "r" | |
2961 | #define Q "q" | |
2962 | #else | |
2963 | #define R "e" | |
2964 | #define Q "l" | |
2965 | #endif | |
2966 | ||
04d2cc77 | 2967 | static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run) |
6aa8b732 | 2968 | { |
a2fa3e9f | 2969 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
1b6269db | 2970 | u32 intr_info; |
e6adf283 | 2971 | |
5fdbf976 MT |
2972 | if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty)) |
2973 | vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); | |
2974 | if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty)) | |
2975 | vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); | |
2976 | ||
e6adf283 AK |
2977 | /* |
2978 | * Loading guest fpu may have cleared host cr0.ts | |
2979 | */ | |
2980 | vmcs_writel(HOST_CR0, read_cr0()); | |
2981 | ||
d77c26fc | 2982 | asm( |
6aa8b732 | 2983 | /* Store host registers */ |
c801949d AK |
2984 | "push %%"R"dx; push %%"R"bp;" |
2985 | "push %%"R"cx \n\t" | |
313dbd49 AK |
2986 | "cmp %%"R"sp, %c[host_rsp](%0) \n\t" |
2987 | "je 1f \n\t" | |
2988 | "mov %%"R"sp, %c[host_rsp](%0) \n\t" | |
4ecac3fd | 2989 | __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t" |
313dbd49 | 2990 | "1: \n\t" |
6aa8b732 | 2991 | /* Check if vmlaunch of vmresume is needed */ |
e08aa78a | 2992 | "cmpl $0, %c[launched](%0) \n\t" |
6aa8b732 | 2993 | /* Load guest registers. Don't clobber flags. */ |
c801949d AK |
2994 | "mov %c[cr2](%0), %%"R"ax \n\t" |
2995 | "mov %%"R"ax, %%cr2 \n\t" | |
2996 | "mov %c[rax](%0), %%"R"ax \n\t" | |
2997 | "mov %c[rbx](%0), %%"R"bx \n\t" | |
2998 | "mov %c[rdx](%0), %%"R"dx \n\t" | |
2999 | "mov %c[rsi](%0), %%"R"si \n\t" | |
3000 | "mov %c[rdi](%0), %%"R"di \n\t" | |
3001 | "mov %c[rbp](%0), %%"R"bp \n\t" | |
05b3e0c2 | 3002 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3003 | "mov %c[r8](%0), %%r8 \n\t" |
3004 | "mov %c[r9](%0), %%r9 \n\t" | |
3005 | "mov %c[r10](%0), %%r10 \n\t" | |
3006 | "mov %c[r11](%0), %%r11 \n\t" | |
3007 | "mov %c[r12](%0), %%r12 \n\t" | |
3008 | "mov %c[r13](%0), %%r13 \n\t" | |
3009 | "mov %c[r14](%0), %%r14 \n\t" | |
3010 | "mov %c[r15](%0), %%r15 \n\t" | |
6aa8b732 | 3011 | #endif |
c801949d AK |
3012 | "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */ |
3013 | ||
6aa8b732 | 3014 | /* Enter guest mode */ |
cd2276a7 | 3015 | "jne .Llaunched \n\t" |
4ecac3fd | 3016 | __ex(ASM_VMX_VMLAUNCH) "\n\t" |
cd2276a7 | 3017 | "jmp .Lkvm_vmx_return \n\t" |
4ecac3fd | 3018 | ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t" |
cd2276a7 | 3019 | ".Lkvm_vmx_return: " |
6aa8b732 | 3020 | /* Save guest registers, load host registers, keep flags */ |
c801949d AK |
3021 | "xchg %0, (%%"R"sp) \n\t" |
3022 | "mov %%"R"ax, %c[rax](%0) \n\t" | |
3023 | "mov %%"R"bx, %c[rbx](%0) \n\t" | |
3024 | "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t" | |
3025 | "mov %%"R"dx, %c[rdx](%0) \n\t" | |
3026 | "mov %%"R"si, %c[rsi](%0) \n\t" | |
3027 | "mov %%"R"di, %c[rdi](%0) \n\t" | |
3028 | "mov %%"R"bp, %c[rbp](%0) \n\t" | |
05b3e0c2 | 3029 | #ifdef CONFIG_X86_64 |
e08aa78a AK |
3030 | "mov %%r8, %c[r8](%0) \n\t" |
3031 | "mov %%r9, %c[r9](%0) \n\t" | |
3032 | "mov %%r10, %c[r10](%0) \n\t" | |
3033 | "mov %%r11, %c[r11](%0) \n\t" | |
3034 | "mov %%r12, %c[r12](%0) \n\t" | |
3035 | "mov %%r13, %c[r13](%0) \n\t" | |
3036 | "mov %%r14, %c[r14](%0) \n\t" | |
3037 | "mov %%r15, %c[r15](%0) \n\t" | |
6aa8b732 | 3038 | #endif |
c801949d AK |
3039 | "mov %%cr2, %%"R"ax \n\t" |
3040 | "mov %%"R"ax, %c[cr2](%0) \n\t" | |
3041 | ||
3042 | "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t" | |
e08aa78a AK |
3043 | "setbe %c[fail](%0) \n\t" |
3044 | : : "c"(vmx), "d"((unsigned long)HOST_RSP), | |
3045 | [launched]"i"(offsetof(struct vcpu_vmx, launched)), | |
3046 | [fail]"i"(offsetof(struct vcpu_vmx, fail)), | |
313dbd49 | 3047 | [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)), |
ad312c7c ZX |
3048 | [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])), |
3049 | [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])), | |
3050 | [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])), | |
3051 | [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])), | |
3052 | [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])), | |
3053 | [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])), | |
3054 | [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])), | |
05b3e0c2 | 3055 | #ifdef CONFIG_X86_64 |
ad312c7c ZX |
3056 | [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])), |
3057 | [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])), | |
3058 | [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])), | |
3059 | [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])), | |
3060 | [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])), | |
3061 | [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])), | |
3062 | [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])), | |
3063 | [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])), | |
6aa8b732 | 3064 | #endif |
ad312c7c | 3065 | [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)) |
c2036300 | 3066 | : "cc", "memory" |
c801949d | 3067 | , R"bx", R"di", R"si" |
c2036300 | 3068 | #ifdef CONFIG_X86_64 |
c2036300 LV |
3069 | , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
3070 | #endif | |
3071 | ); | |
6aa8b732 | 3072 | |
5fdbf976 MT |
3073 | vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)); |
3074 | vcpu->arch.regs_dirty = 0; | |
3075 | ||
1155f76a | 3076 | vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); |
9c8cba37 AK |
3077 | if (vmx->rmode.irq.pending) |
3078 | fixup_rmode_irq(vmx); | |
1155f76a | 3079 | |
ad312c7c | 3080 | vcpu->arch.interrupt_window_open = |
f08864b4 SY |
3081 | (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & |
3082 | (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)) == 0; | |
6aa8b732 | 3083 | |
d77c26fc | 3084 | asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS)); |
15ad7146 | 3085 | vmx->launched = 1; |
1b6269db AK |
3086 | |
3087 | intr_info = vmcs_read32(VM_EXIT_INTR_INFO); | |
3088 | ||
3089 | /* We need to handle NMIs before interrupts are enabled */ | |
f08864b4 SY |
3090 | if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200 && |
3091 | (intr_info & INTR_INFO_VALID_MASK)) { | |
2714d1d3 | 3092 | KVMTRACE_0D(NMI, vcpu, handler); |
1b6269db | 3093 | asm("int $2"); |
2714d1d3 | 3094 | } |
cf393f75 AK |
3095 | |
3096 | vmx_complete_interrupts(vmx); | |
6aa8b732 AK |
3097 | } |
3098 | ||
c801949d AK |
3099 | #undef R |
3100 | #undef Q | |
3101 | ||
6aa8b732 AK |
3102 | static void vmx_free_vmcs(struct kvm_vcpu *vcpu) |
3103 | { | |
a2fa3e9f GH |
3104 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3105 | ||
3106 | if (vmx->vmcs) { | |
543e4243 | 3107 | vcpu_clear(vmx); |
a2fa3e9f GH |
3108 | free_vmcs(vmx->vmcs); |
3109 | vmx->vmcs = NULL; | |
6aa8b732 AK |
3110 | } |
3111 | } | |
3112 | ||
3113 | static void vmx_free_vcpu(struct kvm_vcpu *vcpu) | |
3114 | { | |
fb3f0f51 RR |
3115 | struct vcpu_vmx *vmx = to_vmx(vcpu); |
3116 | ||
2384d2b3 SY |
3117 | spin_lock(&vmx_vpid_lock); |
3118 | if (vmx->vpid != 0) | |
3119 | __clear_bit(vmx->vpid, vmx_vpid_bitmap); | |
3120 | spin_unlock(&vmx_vpid_lock); | |
6aa8b732 | 3121 | vmx_free_vmcs(vcpu); |
fb3f0f51 RR |
3122 | kfree(vmx->host_msrs); |
3123 | kfree(vmx->guest_msrs); | |
3124 | kvm_vcpu_uninit(vcpu); | |
a4770347 | 3125 | kmem_cache_free(kvm_vcpu_cache, vmx); |
6aa8b732 AK |
3126 | } |
3127 | ||
fb3f0f51 | 3128 | static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id) |
6aa8b732 | 3129 | { |
fb3f0f51 | 3130 | int err; |
c16f862d | 3131 | struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL); |
15ad7146 | 3132 | int cpu; |
6aa8b732 | 3133 | |
a2fa3e9f | 3134 | if (!vmx) |
fb3f0f51 RR |
3135 | return ERR_PTR(-ENOMEM); |
3136 | ||
2384d2b3 SY |
3137 | allocate_vpid(vmx); |
3138 | ||
fb3f0f51 RR |
3139 | err = kvm_vcpu_init(&vmx->vcpu, kvm, id); |
3140 | if (err) | |
3141 | goto free_vcpu; | |
965b58a5 | 3142 | |
a2fa3e9f | 3143 | vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
fb3f0f51 RR |
3144 | if (!vmx->guest_msrs) { |
3145 | err = -ENOMEM; | |
3146 | goto uninit_vcpu; | |
3147 | } | |
965b58a5 | 3148 | |
a2fa3e9f GH |
3149 | vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL); |
3150 | if (!vmx->host_msrs) | |
fb3f0f51 | 3151 | goto free_guest_msrs; |
965b58a5 | 3152 | |
a2fa3e9f GH |
3153 | vmx->vmcs = alloc_vmcs(); |
3154 | if (!vmx->vmcs) | |
fb3f0f51 | 3155 | goto free_msrs; |
a2fa3e9f GH |
3156 | |
3157 | vmcs_clear(vmx->vmcs); | |
3158 | ||
15ad7146 AK |
3159 | cpu = get_cpu(); |
3160 | vmx_vcpu_load(&vmx->vcpu, cpu); | |
8b9cf98c | 3161 | err = vmx_vcpu_setup(vmx); |
fb3f0f51 | 3162 | vmx_vcpu_put(&vmx->vcpu); |
15ad7146 | 3163 | put_cpu(); |
fb3f0f51 RR |
3164 | if (err) |
3165 | goto free_vmcs; | |
5e4a0b3c MT |
3166 | if (vm_need_virtualize_apic_accesses(kvm)) |
3167 | if (alloc_apic_access_page(kvm) != 0) | |
3168 | goto free_vmcs; | |
fb3f0f51 | 3169 | |
b7ebfb05 SY |
3170 | if (vm_need_ept()) |
3171 | if (alloc_identity_pagetable(kvm) != 0) | |
3172 | goto free_vmcs; | |
3173 | ||
fb3f0f51 RR |
3174 | return &vmx->vcpu; |
3175 | ||
3176 | free_vmcs: | |
3177 | free_vmcs(vmx->vmcs); | |
3178 | free_msrs: | |
3179 | kfree(vmx->host_msrs); | |
3180 | free_guest_msrs: | |
3181 | kfree(vmx->guest_msrs); | |
3182 | uninit_vcpu: | |
3183 | kvm_vcpu_uninit(&vmx->vcpu); | |
3184 | free_vcpu: | |
a4770347 | 3185 | kmem_cache_free(kvm_vcpu_cache, vmx); |
fb3f0f51 | 3186 | return ERR_PTR(err); |
6aa8b732 AK |
3187 | } |
3188 | ||
002c7f7c YS |
3189 | static void __init vmx_check_processor_compat(void *rtn) |
3190 | { | |
3191 | struct vmcs_config vmcs_conf; | |
3192 | ||
3193 | *(int *)rtn = 0; | |
3194 | if (setup_vmcs_config(&vmcs_conf) < 0) | |
3195 | *(int *)rtn = -EIO; | |
3196 | if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { | |
3197 | printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", | |
3198 | smp_processor_id()); | |
3199 | *(int *)rtn = -EIO; | |
3200 | } | |
3201 | } | |
3202 | ||
67253af5 SY |
3203 | static int get_ept_level(void) |
3204 | { | |
3205 | return VMX_EPT_DEFAULT_GAW + 1; | |
3206 | } | |
3207 | ||
cbdd1bea | 3208 | static struct kvm_x86_ops vmx_x86_ops = { |
6aa8b732 AK |
3209 | .cpu_has_kvm_support = cpu_has_kvm_support, |
3210 | .disabled_by_bios = vmx_disabled_by_bios, | |
3211 | .hardware_setup = hardware_setup, | |
3212 | .hardware_unsetup = hardware_unsetup, | |
002c7f7c | 3213 | .check_processor_compatibility = vmx_check_processor_compat, |
6aa8b732 AK |
3214 | .hardware_enable = hardware_enable, |
3215 | .hardware_disable = hardware_disable, | |
774ead3a | 3216 | .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses, |
6aa8b732 AK |
3217 | |
3218 | .vcpu_create = vmx_create_vcpu, | |
3219 | .vcpu_free = vmx_free_vcpu, | |
04d2cc77 | 3220 | .vcpu_reset = vmx_vcpu_reset, |
6aa8b732 | 3221 | |
04d2cc77 | 3222 | .prepare_guest_switch = vmx_save_host_state, |
6aa8b732 AK |
3223 | .vcpu_load = vmx_vcpu_load, |
3224 | .vcpu_put = vmx_vcpu_put, | |
3225 | ||
3226 | .set_guest_debug = set_guest_debug, | |
04d2cc77 | 3227 | .guest_debug_pre = kvm_guest_debug_pre, |
6aa8b732 AK |
3228 | .get_msr = vmx_get_msr, |
3229 | .set_msr = vmx_set_msr, | |
3230 | .get_segment_base = vmx_get_segment_base, | |
3231 | .get_segment = vmx_get_segment, | |
3232 | .set_segment = vmx_set_segment, | |
2e4d2653 | 3233 | .get_cpl = vmx_get_cpl, |
6aa8b732 | 3234 | .get_cs_db_l_bits = vmx_get_cs_db_l_bits, |
25c4c276 | 3235 | .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, |
6aa8b732 | 3236 | .set_cr0 = vmx_set_cr0, |
6aa8b732 AK |
3237 | .set_cr3 = vmx_set_cr3, |
3238 | .set_cr4 = vmx_set_cr4, | |
6aa8b732 | 3239 | .set_efer = vmx_set_efer, |
6aa8b732 AK |
3240 | .get_idt = vmx_get_idt, |
3241 | .set_idt = vmx_set_idt, | |
3242 | .get_gdt = vmx_get_gdt, | |
3243 | .set_gdt = vmx_set_gdt, | |
5fdbf976 | 3244 | .cache_reg = vmx_cache_reg, |
6aa8b732 AK |
3245 | .get_rflags = vmx_get_rflags, |
3246 | .set_rflags = vmx_set_rflags, | |
3247 | ||
3248 | .tlb_flush = vmx_flush_tlb, | |
6aa8b732 | 3249 | |
6aa8b732 | 3250 | .run = vmx_vcpu_run, |
04d2cc77 | 3251 | .handle_exit = kvm_handle_exit, |
6aa8b732 | 3252 | .skip_emulated_instruction = skip_emulated_instruction, |
102d8325 | 3253 | .patch_hypercall = vmx_patch_hypercall, |
2a8067f1 ED |
3254 | .get_irq = vmx_get_irq, |
3255 | .set_irq = vmx_inject_irq, | |
298101da AK |
3256 | .queue_exception = vmx_queue_exception, |
3257 | .exception_injected = vmx_exception_injected, | |
04d2cc77 AK |
3258 | .inject_pending_irq = vmx_intr_assist, |
3259 | .inject_pending_vectors = do_interrupt_requests, | |
cbc94022 IE |
3260 | |
3261 | .set_tss_addr = vmx_set_tss_addr, | |
67253af5 | 3262 | .get_tdp_level = get_ept_level, |
6aa8b732 AK |
3263 | }; |
3264 | ||
3265 | static int __init vmx_init(void) | |
3266 | { | |
25c5f225 | 3267 | void *va; |
fdef3ad1 HQ |
3268 | int r; |
3269 | ||
3270 | vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3271 | if (!vmx_io_bitmap_a) | |
3272 | return -ENOMEM; | |
3273 | ||
3274 | vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); | |
3275 | if (!vmx_io_bitmap_b) { | |
3276 | r = -ENOMEM; | |
3277 | goto out; | |
3278 | } | |
3279 | ||
25c5f225 SY |
3280 | vmx_msr_bitmap = alloc_page(GFP_KERNEL | __GFP_HIGHMEM); |
3281 | if (!vmx_msr_bitmap) { | |
3282 | r = -ENOMEM; | |
3283 | goto out1; | |
3284 | } | |
3285 | ||
fdef3ad1 HQ |
3286 | /* |
3287 | * Allow direct access to the PC debug port (it is often used for I/O | |
3288 | * delays, but the vmexits simply slow things down). | |
3289 | */ | |
25c5f225 SY |
3290 | va = kmap(vmx_io_bitmap_a); |
3291 | memset(va, 0xff, PAGE_SIZE); | |
3292 | clear_bit(0x80, va); | |
cd0536d7 | 3293 | kunmap(vmx_io_bitmap_a); |
fdef3ad1 | 3294 | |
25c5f225 SY |
3295 | va = kmap(vmx_io_bitmap_b); |
3296 | memset(va, 0xff, PAGE_SIZE); | |
cd0536d7 | 3297 | kunmap(vmx_io_bitmap_b); |
fdef3ad1 | 3298 | |
25c5f225 SY |
3299 | va = kmap(vmx_msr_bitmap); |
3300 | memset(va, 0xff, PAGE_SIZE); | |
3301 | kunmap(vmx_msr_bitmap); | |
3302 | ||
2384d2b3 SY |
3303 | set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ |
3304 | ||
cb498ea2 | 3305 | r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE); |
fdef3ad1 | 3306 | if (r) |
25c5f225 SY |
3307 | goto out2; |
3308 | ||
3309 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_FS_BASE); | |
3310 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_GS_BASE); | |
3311 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_CS); | |
3312 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_ESP); | |
3313 | vmx_disable_intercept_for_msr(vmx_msr_bitmap, MSR_IA32_SYSENTER_EIP); | |
fdef3ad1 | 3314 | |
5fdbcb9d | 3315 | if (vm_need_ept()) { |
1439442c | 3316 | bypass_guest_pf = 0; |
5fdbcb9d SY |
3317 | kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK | |
3318 | VMX_EPT_WRITABLE_MASK | | |
3319 | VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT); | |
534e38b4 | 3320 | kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull, |
5fdbcb9d SY |
3321 | VMX_EPT_EXECUTABLE_MASK); |
3322 | kvm_enable_tdp(); | |
3323 | } else | |
3324 | kvm_disable_tdp(); | |
1439442c | 3325 | |
c7addb90 AK |
3326 | if (bypass_guest_pf) |
3327 | kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull); | |
3328 | ||
1439442c SY |
3329 | ept_sync_global(); |
3330 | ||
fdef3ad1 HQ |
3331 | return 0; |
3332 | ||
25c5f225 SY |
3333 | out2: |
3334 | __free_page(vmx_msr_bitmap); | |
fdef3ad1 HQ |
3335 | out1: |
3336 | __free_page(vmx_io_bitmap_b); | |
3337 | out: | |
3338 | __free_page(vmx_io_bitmap_a); | |
3339 | return r; | |
6aa8b732 AK |
3340 | } |
3341 | ||
3342 | static void __exit vmx_exit(void) | |
3343 | { | |
25c5f225 | 3344 | __free_page(vmx_msr_bitmap); |
fdef3ad1 HQ |
3345 | __free_page(vmx_io_bitmap_b); |
3346 | __free_page(vmx_io_bitmap_a); | |
3347 | ||
cb498ea2 | 3348 | kvm_exit(); |
6aa8b732 AK |
3349 | } |
3350 | ||
3351 | module_init(vmx_init) | |
3352 | module_exit(vmx_exit) |