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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
4ff4b44c | 40 | #include <linux/hash.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
9ee32fea | 43 | #include <linux/pm_qos.h> |
d07f0e59 | 44 | #include <linux/reservation.h> |
e73bdd20 CW |
45 | #include <linux/shmem_fs.h> |
46 | ||
47 | #include <drm/drmP.h> | |
48 | #include <drm/intel-gtt.h> | |
49 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
50 | #include <drm/drm_gem.h> | |
3b96a0b1 | 51 | #include <drm/drm_auth.h> |
f9a87bd7 | 52 | #include <drm/drm_cache.h> |
e73bdd20 CW |
53 | |
54 | #include "i915_params.h" | |
55 | #include "i915_reg.h" | |
40b326ee | 56 | #include "i915_utils.h" |
e73bdd20 | 57 | |
16586fcd | 58 | #include "intel_uncore.h" |
e73bdd20 | 59 | #include "intel_bios.h" |
ac7f11c6 | 60 | #include "intel_dpll_mgr.h" |
8c4f24f9 | 61 | #include "intel_uc.h" |
e73bdd20 CW |
62 | #include "intel_lrc.h" |
63 | #include "intel_ringbuffer.h" | |
64 | ||
d501b1d2 | 65 | #include "i915_gem.h" |
6095868a | 66 | #include "i915_gem_context.h" |
b42fe9ca JL |
67 | #include "i915_gem_fence_reg.h" |
68 | #include "i915_gem_object.h" | |
e73bdd20 CW |
69 | #include "i915_gem_gtt.h" |
70 | #include "i915_gem_render_state.h" | |
05235c53 | 71 | #include "i915_gem_request.h" |
73cb9701 | 72 | #include "i915_gem_timeline.h" |
585fb111 | 73 | |
b42fe9ca JL |
74 | #include "i915_vma.h" |
75 | ||
0ad35fed ZW |
76 | #include "intel_gvt.h" |
77 | ||
1da177e4 LT |
78 | /* General customization: |
79 | */ | |
80 | ||
1da177e4 LT |
81 | #define DRIVER_NAME "i915" |
82 | #define DRIVER_DESC "Intel Graphics" | |
58947144 DV |
83 | #define DRIVER_DATE "20170717" |
84 | #define DRIVER_TIMESTAMP 1500275179 | |
1da177e4 | 85 | |
e2c719b7 RC |
86 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
87 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
88 | * which may not necessarily be a user visible problem. This will either | |
89 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
90 | * enable distros and users to tailor their preferred amount of i915 abrt | |
91 | * spam. | |
92 | */ | |
93 | #define I915_STATE_WARN(condition, format...) ({ \ | |
94 | int __ret_warn_on = !!(condition); \ | |
32753cb8 JL |
95 | if (unlikely(__ret_warn_on)) \ |
96 | if (!WARN(i915.verbose_state_checks, format)) \ | |
e2c719b7 | 97 | DRM_ERROR(format); \ |
e2c719b7 RC |
98 | unlikely(__ret_warn_on); \ |
99 | }) | |
100 | ||
152b2262 JL |
101 | #define I915_STATE_WARN_ON(x) \ |
102 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 103 | |
4fec15d1 ID |
104 | bool __i915_inject_load_failure(const char *func, int line); |
105 | #define i915_inject_load_failure() \ | |
106 | __i915_inject_load_failure(__func__, __LINE__) | |
107 | ||
b95320bd MK |
108 | typedef struct { |
109 | uint32_t val; | |
110 | } uint_fixed_16_16_t; | |
111 | ||
112 | #define FP_16_16_MAX ({ \ | |
113 | uint_fixed_16_16_t fp; \ | |
114 | fp.val = UINT_MAX; \ | |
115 | fp; \ | |
116 | }) | |
117 | ||
d555cb58 KM |
118 | static inline bool is_fixed16_zero(uint_fixed_16_16_t val) |
119 | { | |
120 | if (val.val == 0) | |
121 | return true; | |
122 | return false; | |
123 | } | |
124 | ||
eac2cb81 | 125 | static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val) |
b95320bd MK |
126 | { |
127 | uint_fixed_16_16_t fp; | |
128 | ||
129 | WARN_ON(val >> 16); | |
130 | ||
131 | fp.val = val << 16; | |
132 | return fp; | |
133 | } | |
134 | ||
eac2cb81 | 135 | static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp) |
b95320bd MK |
136 | { |
137 | return DIV_ROUND_UP(fp.val, 1 << 16); | |
138 | } | |
139 | ||
eac2cb81 | 140 | static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp) |
b95320bd MK |
141 | { |
142 | return fp.val >> 16; | |
143 | } | |
144 | ||
eac2cb81 | 145 | static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1, |
b95320bd MK |
146 | uint_fixed_16_16_t min2) |
147 | { | |
148 | uint_fixed_16_16_t min; | |
149 | ||
150 | min.val = min(min1.val, min2.val); | |
151 | return min; | |
152 | } | |
153 | ||
eac2cb81 | 154 | static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1, |
b95320bd MK |
155 | uint_fixed_16_16_t max2) |
156 | { | |
157 | uint_fixed_16_16_t max; | |
158 | ||
159 | max.val = max(max1.val, max2.val); | |
160 | return max; | |
161 | } | |
162 | ||
07ab976d KM |
163 | static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val) |
164 | { | |
165 | uint_fixed_16_16_t fp; | |
166 | WARN_ON(val >> 32); | |
167 | fp.val = clamp_t(uint32_t, val, 0, ~0); | |
168 | return fp; | |
169 | } | |
170 | ||
a9d055de KM |
171 | static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val, |
172 | uint_fixed_16_16_t d) | |
173 | { | |
174 | return DIV_ROUND_UP(val.val, d.val); | |
175 | } | |
176 | ||
177 | static inline uint32_t mul_round_up_u32_fixed16(uint32_t val, | |
178 | uint_fixed_16_16_t mul) | |
179 | { | |
180 | uint64_t intermediate_val; | |
a9d055de KM |
181 | |
182 | intermediate_val = (uint64_t) val * mul.val; | |
183 | intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16); | |
184 | WARN_ON(intermediate_val >> 32); | |
07ab976d | 185 | return clamp_t(uint32_t, intermediate_val, 0, ~0); |
a9d055de KM |
186 | } |
187 | ||
188 | static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val, | |
189 | uint_fixed_16_16_t mul) | |
190 | { | |
191 | uint64_t intermediate_val; | |
a9d055de KM |
192 | |
193 | intermediate_val = (uint64_t) val.val * mul.val; | |
194 | intermediate_val = intermediate_val >> 16; | |
07ab976d | 195 | return clamp_u64_to_fixed16(intermediate_val); |
a9d055de KM |
196 | } |
197 | ||
eac2cb81 | 198 | static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d) |
b95320bd | 199 | { |
b95320bd MK |
200 | uint64_t interm_val; |
201 | ||
202 | interm_val = (uint64_t)val << 16; | |
203 | interm_val = DIV_ROUND_UP_ULL(interm_val, d); | |
07ab976d | 204 | return clamp_u64_to_fixed16(interm_val); |
b95320bd MK |
205 | } |
206 | ||
a9d055de KM |
207 | static inline uint32_t div_round_up_u32_fixed16(uint32_t val, |
208 | uint_fixed_16_16_t d) | |
209 | { | |
210 | uint64_t interm_val; | |
211 | ||
212 | interm_val = (uint64_t)val << 16; | |
213 | interm_val = DIV_ROUND_UP_ULL(interm_val, d.val); | |
214 | WARN_ON(interm_val >> 32); | |
215 | return clamp_t(uint32_t, interm_val, 0, ~0); | |
216 | } | |
217 | ||
eac2cb81 | 218 | static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val, |
b95320bd MK |
219 | uint_fixed_16_16_t mul) |
220 | { | |
221 | uint64_t intermediate_val; | |
b95320bd MK |
222 | |
223 | intermediate_val = (uint64_t) val * mul.val; | |
07ab976d | 224 | return clamp_u64_to_fixed16(intermediate_val); |
b95320bd MK |
225 | } |
226 | ||
6ea593c0 KM |
227 | static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1, |
228 | uint_fixed_16_16_t add2) | |
229 | { | |
230 | uint64_t interm_sum; | |
231 | ||
232 | interm_sum = (uint64_t) add1.val + add2.val; | |
233 | return clamp_u64_to_fixed16(interm_sum); | |
234 | } | |
235 | ||
236 | static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1, | |
237 | uint32_t add2) | |
238 | { | |
239 | uint64_t interm_sum; | |
240 | uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2); | |
241 | ||
242 | interm_sum = (uint64_t) add1.val + interm_add2.val; | |
243 | return clamp_u64_to_fixed16(interm_sum); | |
244 | } | |
245 | ||
42a8ca4c JN |
246 | static inline const char *yesno(bool v) |
247 | { | |
248 | return v ? "yes" : "no"; | |
249 | } | |
250 | ||
87ad3212 JN |
251 | static inline const char *onoff(bool v) |
252 | { | |
253 | return v ? "on" : "off"; | |
254 | } | |
255 | ||
08c4d7fc TU |
256 | static inline const char *enableddisabled(bool v) |
257 | { | |
258 | return v ? "enabled" : "disabled"; | |
259 | } | |
260 | ||
317c35d1 | 261 | enum pipe { |
752aa88a | 262 | INVALID_PIPE = -1, |
317c35d1 JB |
263 | PIPE_A = 0, |
264 | PIPE_B, | |
9db4a9c7 | 265 | PIPE_C, |
a57c774a AK |
266 | _PIPE_EDP, |
267 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 268 | }; |
9db4a9c7 | 269 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 270 | |
a5c961d1 PZ |
271 | enum transcoder { |
272 | TRANSCODER_A = 0, | |
273 | TRANSCODER_B, | |
274 | TRANSCODER_C, | |
a57c774a | 275 | TRANSCODER_EDP, |
4d1de975 JN |
276 | TRANSCODER_DSI_A, |
277 | TRANSCODER_DSI_C, | |
a57c774a | 278 | I915_MAX_TRANSCODERS |
a5c961d1 | 279 | }; |
da205630 JN |
280 | |
281 | static inline const char *transcoder_name(enum transcoder transcoder) | |
282 | { | |
283 | switch (transcoder) { | |
284 | case TRANSCODER_A: | |
285 | return "A"; | |
286 | case TRANSCODER_B: | |
287 | return "B"; | |
288 | case TRANSCODER_C: | |
289 | return "C"; | |
290 | case TRANSCODER_EDP: | |
291 | return "EDP"; | |
4d1de975 JN |
292 | case TRANSCODER_DSI_A: |
293 | return "DSI A"; | |
294 | case TRANSCODER_DSI_C: | |
295 | return "DSI C"; | |
da205630 JN |
296 | default: |
297 | return "<invalid>"; | |
298 | } | |
299 | } | |
a5c961d1 | 300 | |
4d1de975 JN |
301 | static inline bool transcoder_is_dsi(enum transcoder transcoder) |
302 | { | |
303 | return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C; | |
304 | } | |
305 | ||
84139d1e | 306 | /* |
b14e5848 VS |
307 | * Global legacy plane identifier. Valid only for primary/sprite |
308 | * planes on pre-g4x, and only for primary planes on g4x+. | |
84139d1e | 309 | */ |
80824003 | 310 | enum plane { |
b14e5848 | 311 | PLANE_A, |
80824003 | 312 | PLANE_B, |
9db4a9c7 | 313 | PLANE_C, |
80824003 | 314 | }; |
9db4a9c7 | 315 | #define plane_name(p) ((p) + 'A') |
52440211 | 316 | |
580503c7 | 317 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 318 | |
b14e5848 VS |
319 | /* |
320 | * Per-pipe plane identifier. | |
321 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) | |
322 | * number of planes per CRTC. Not all platforms really have this many planes, | |
323 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
324 | * between the topmost sprite plane and the cursor plane. | |
325 | * | |
326 | * This is expected to be passed to various register macros | |
327 | * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. | |
328 | */ | |
329 | enum plane_id { | |
330 | PLANE_PRIMARY, | |
331 | PLANE_SPRITE0, | |
332 | PLANE_SPRITE1, | |
19c3164d | 333 | PLANE_SPRITE2, |
b14e5848 VS |
334 | PLANE_CURSOR, |
335 | I915_MAX_PLANES, | |
336 | }; | |
337 | ||
d97d7b48 VS |
338 | #define for_each_plane_id_on_crtc(__crtc, __p) \ |
339 | for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \ | |
340 | for_each_if ((__crtc)->plane_ids_mask & BIT(__p)) | |
341 | ||
2b139522 | 342 | enum port { |
03cdc1d4 | 343 | PORT_NONE = -1, |
2b139522 ED |
344 | PORT_A = 0, |
345 | PORT_B, | |
346 | PORT_C, | |
347 | PORT_D, | |
348 | PORT_E, | |
349 | I915_MAX_PORTS | |
350 | }; | |
351 | #define port_name(p) ((p) + 'A') | |
352 | ||
a09caddd | 353 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
354 | |
355 | enum dpio_channel { | |
356 | DPIO_CH0, | |
357 | DPIO_CH1 | |
358 | }; | |
359 | ||
360 | enum dpio_phy { | |
361 | DPIO_PHY0, | |
0a116ce8 ACO |
362 | DPIO_PHY1, |
363 | DPIO_PHY2, | |
e4607fcf CML |
364 | }; |
365 | ||
b97186f0 PZ |
366 | enum intel_display_power_domain { |
367 | POWER_DOMAIN_PIPE_A, | |
368 | POWER_DOMAIN_PIPE_B, | |
369 | POWER_DOMAIN_PIPE_C, | |
370 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
371 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
372 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
373 | POWER_DOMAIN_TRANSCODER_A, | |
374 | POWER_DOMAIN_TRANSCODER_B, | |
375 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 376 | POWER_DOMAIN_TRANSCODER_EDP, |
4d1de975 JN |
377 | POWER_DOMAIN_TRANSCODER_DSI_A, |
378 | POWER_DOMAIN_TRANSCODER_DSI_C, | |
6331a704 PJ |
379 | POWER_DOMAIN_PORT_DDI_A_LANES, |
380 | POWER_DOMAIN_PORT_DDI_B_LANES, | |
381 | POWER_DOMAIN_PORT_DDI_C_LANES, | |
382 | POWER_DOMAIN_PORT_DDI_D_LANES, | |
383 | POWER_DOMAIN_PORT_DDI_E_LANES, | |
62b69566 ACO |
384 | POWER_DOMAIN_PORT_DDI_A_IO, |
385 | POWER_DOMAIN_PORT_DDI_B_IO, | |
386 | POWER_DOMAIN_PORT_DDI_C_IO, | |
387 | POWER_DOMAIN_PORT_DDI_D_IO, | |
388 | POWER_DOMAIN_PORT_DDI_E_IO, | |
319be8ae ID |
389 | POWER_DOMAIN_PORT_DSI, |
390 | POWER_DOMAIN_PORT_CRT, | |
391 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 392 | POWER_DOMAIN_VGA, |
fbeeaa23 | 393 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 394 | POWER_DOMAIN_PLLS, |
1407121a S |
395 | POWER_DOMAIN_AUX_A, |
396 | POWER_DOMAIN_AUX_B, | |
397 | POWER_DOMAIN_AUX_C, | |
398 | POWER_DOMAIN_AUX_D, | |
f0ab43e6 | 399 | POWER_DOMAIN_GMBUS, |
dfa57627 | 400 | POWER_DOMAIN_MODESET, |
baa70707 | 401 | POWER_DOMAIN_INIT, |
bddc7645 ID |
402 | |
403 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
404 | }; |
405 | ||
406 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
407 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
408 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
409 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
410 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
411 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 412 | |
1d843f9d EE |
413 | enum hpd_pin { |
414 | HPD_NONE = 0, | |
1d843f9d EE |
415 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
416 | HPD_CRT, | |
417 | HPD_SDVO_B, | |
418 | HPD_SDVO_C, | |
cc24fcdc | 419 | HPD_PORT_A, |
1d843f9d EE |
420 | HPD_PORT_B, |
421 | HPD_PORT_C, | |
422 | HPD_PORT_D, | |
26951caf | 423 | HPD_PORT_E, |
1d843f9d EE |
424 | HPD_NUM_PINS |
425 | }; | |
426 | ||
c91711f9 JN |
427 | #define for_each_hpd_pin(__pin) \ |
428 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
429 | ||
317eaa95 L |
430 | #define HPD_STORM_DEFAULT_THRESHOLD 5 |
431 | ||
5fcece80 JN |
432 | struct i915_hotplug { |
433 | struct work_struct hotplug_work; | |
434 | ||
435 | struct { | |
436 | unsigned long last_jiffies; | |
437 | int count; | |
438 | enum { | |
439 | HPD_ENABLED = 0, | |
440 | HPD_DISABLED = 1, | |
441 | HPD_MARK_DISABLED = 2 | |
442 | } state; | |
443 | } stats[HPD_NUM_PINS]; | |
444 | u32 event_bits; | |
445 | struct delayed_work reenable_work; | |
446 | ||
447 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
448 | u32 long_port_mask; | |
449 | u32 short_port_mask; | |
450 | struct work_struct dig_port_work; | |
451 | ||
19625e85 L |
452 | struct work_struct poll_init_work; |
453 | bool poll_enabled; | |
454 | ||
317eaa95 L |
455 | unsigned int hpd_storm_threshold; |
456 | ||
5fcece80 JN |
457 | /* |
458 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
459 | * the non-DP HPD could block the workqueue on a mode config | |
460 | * mutex getting, that userspace may have taken. However | |
461 | * userspace is waiting on the DP workqueue to run which is | |
462 | * blocked behind the non-DP one. | |
463 | */ | |
464 | struct workqueue_struct *dp_wq; | |
465 | }; | |
466 | ||
2a2d5482 CW |
467 | #define I915_GEM_GPU_DOMAINS \ |
468 | (I915_GEM_DOMAIN_RENDER | \ | |
469 | I915_GEM_DOMAIN_SAMPLER | \ | |
470 | I915_GEM_DOMAIN_COMMAND | \ | |
471 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
472 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 473 | |
055e393f DL |
474 | #define for_each_pipe(__dev_priv, __p) \ |
475 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
6831f3e3 VS |
476 | #define for_each_pipe_masked(__dev_priv, __p, __mask) \ |
477 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \ | |
478 | for_each_if ((__mask) & (1 << (__p))) | |
8b364b41 | 479 | #define for_each_universal_plane(__dev_priv, __pipe, __p) \ |
dd740780 DL |
480 | for ((__p) = 0; \ |
481 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
482 | (__p)++) | |
3bdcfc0c DL |
483 | #define for_each_sprite(__dev_priv, __p, __s) \ |
484 | for ((__s) = 0; \ | |
485 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
486 | (__s)++) | |
9db4a9c7 | 487 | |
c3aeadc8 JN |
488 | #define for_each_port_masked(__port, __ports_mask) \ |
489 | for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \ | |
490 | for_each_if ((__ports_mask) & (1 << (__port))) | |
491 | ||
d79b814d | 492 | #define for_each_crtc(dev, crtc) \ |
91c8a326 | 493 | list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) |
d79b814d | 494 | |
27321ae8 ML |
495 | #define for_each_intel_plane(dev, intel_plane) \ |
496 | list_for_each_entry(intel_plane, \ | |
91c8a326 | 497 | &(dev)->mode_config.plane_list, \ |
27321ae8 ML |
498 | base.head) |
499 | ||
c107acfe | 500 | #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \ |
91c8a326 CW |
501 | list_for_each_entry(intel_plane, \ |
502 | &(dev)->mode_config.plane_list, \ | |
c107acfe MR |
503 | base.head) \ |
504 | for_each_if ((plane_mask) & \ | |
505 | (1 << drm_plane_index(&intel_plane->base))) | |
506 | ||
262cd2e1 VS |
507 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
508 | list_for_each_entry(intel_plane, \ | |
509 | &(dev)->mode_config.plane_list, \ | |
510 | base.head) \ | |
95150bdf | 511 | for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe) |
262cd2e1 | 512 | |
91c8a326 CW |
513 | #define for_each_intel_crtc(dev, intel_crtc) \ |
514 | list_for_each_entry(intel_crtc, \ | |
515 | &(dev)->mode_config.crtc_list, \ | |
516 | base.head) | |
d063ae48 | 517 | |
91c8a326 CW |
518 | #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \ |
519 | list_for_each_entry(intel_crtc, \ | |
520 | &(dev)->mode_config.crtc_list, \ | |
521 | base.head) \ | |
98d39494 MR |
522 | for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base))) |
523 | ||
b2784e15 DL |
524 | #define for_each_intel_encoder(dev, intel_encoder) \ |
525 | list_for_each_entry(intel_encoder, \ | |
526 | &(dev)->mode_config.encoder_list, \ | |
527 | base.head) | |
528 | ||
3f6a5e1e DV |
529 | #define for_each_intel_connector_iter(intel_connector, iter) \ |
530 | while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter)))) | |
531 | ||
6c2b7c12 DV |
532 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
533 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
95150bdf | 534 | for_each_if ((intel_encoder)->base.crtc == (__crtc)) |
6c2b7c12 | 535 | |
53f5e3ca JB |
536 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
537 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
95150bdf | 538 | for_each_if ((intel_connector)->base.encoder == (__encoder)) |
53f5e3ca | 539 | |
b04c5bd6 BF |
540 | #define for_each_power_domain(domain, mask) \ |
541 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
d8fc70b7 | 542 | for_each_if (BIT_ULL(domain) & (mask)) |
b04c5bd6 | 543 | |
75ccb2ec ID |
544 | #define for_each_power_well(__dev_priv, __power_well) \ |
545 | for ((__power_well) = (__dev_priv)->power_domains.power_wells; \ | |
546 | (__power_well) - (__dev_priv)->power_domains.power_wells < \ | |
547 | (__dev_priv)->power_domains.power_well_count; \ | |
548 | (__power_well)++) | |
549 | ||
550 | #define for_each_power_well_rev(__dev_priv, __power_well) \ | |
551 | for ((__power_well) = (__dev_priv)->power_domains.power_wells + \ | |
552 | (__dev_priv)->power_domains.power_well_count - 1; \ | |
553 | (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \ | |
554 | (__power_well)--) | |
555 | ||
556 | #define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \ | |
557 | for_each_power_well(__dev_priv, __power_well) \ | |
558 | for_each_if ((__power_well)->domains & (__domain_mask)) | |
559 | ||
560 | #define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \ | |
561 | for_each_power_well_rev(__dev_priv, __power_well) \ | |
562 | for_each_if ((__power_well)->domains & (__domain_mask)) | |
563 | ||
ff32c54e VS |
564 | #define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \ |
565 | for ((__i) = 0; \ | |
566 | (__i) < (__state)->base.dev->mode_config.num_total_plane && \ | |
567 | ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \ | |
568 | (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \ | |
569 | (__i)++) \ | |
570 | for_each_if (plane_state) | |
571 | ||
e7b903d2 | 572 | struct drm_i915_private; |
ad46cb53 | 573 | struct i915_mm_struct; |
5cc9ed4b | 574 | struct i915_mmu_object; |
e7b903d2 | 575 | |
a6f766f3 CW |
576 | struct drm_i915_file_private { |
577 | struct drm_i915_private *dev_priv; | |
578 | struct drm_file *file; | |
579 | ||
580 | struct { | |
581 | spinlock_t lock; | |
582 | struct list_head request_list; | |
d0bc54f2 CW |
583 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
584 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
585 | * (when using lax throttling for the frontbuffer). We also use it to | |
586 | * offer free GPU waitboosts for severely congested workloads. | |
587 | */ | |
588 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
589 | } mm; |
590 | struct idr context_idr; | |
591 | ||
2e1b8730 | 592 | struct intel_rps_client { |
7b92c1bd | 593 | atomic_t boosts; |
2e1b8730 | 594 | } rps; |
a6f766f3 | 595 | |
c80ff16e | 596 | unsigned int bsd_engine; |
b083a087 MK |
597 | |
598 | /* Client can have a maximum of 3 contexts banned before | |
599 | * it is denied of creating new contexts. As one context | |
600 | * ban needs 4 consecutive hangs, and more if there is | |
601 | * progress in between, this is a last resort stop gap measure | |
602 | * to limit the badly behaving clients access to gpu. | |
603 | */ | |
604 | #define I915_MAX_CLIENT_CONTEXT_BANS 3 | |
77b25a97 | 605 | atomic_t context_bans; |
a6f766f3 CW |
606 | }; |
607 | ||
e69d0bc1 DV |
608 | /* Used by dp and fdi links */ |
609 | struct intel_link_m_n { | |
610 | uint32_t tu; | |
611 | uint32_t gmch_m; | |
612 | uint32_t gmch_n; | |
613 | uint32_t link_m; | |
614 | uint32_t link_n; | |
615 | }; | |
616 | ||
617 | void intel_link_compute_m_n(int bpp, int nlanes, | |
618 | int pixel_clock, int link_clock, | |
b31e85ed JN |
619 | struct intel_link_m_n *m_n, |
620 | bool reduce_m_n); | |
e69d0bc1 | 621 | |
1da177e4 LT |
622 | /* Interface history: |
623 | * | |
624 | * 1.1: Original. | |
0d6aa60b DA |
625 | * 1.2: Add Power Management |
626 | * 1.3: Add vblank support | |
de227f5f | 627 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 628 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
629 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
630 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
631 | */ |
632 | #define DRIVER_MAJOR 1 | |
2228ed67 | 633 | #define DRIVER_MINOR 6 |
1da177e4 LT |
634 | #define DRIVER_PATCHLEVEL 0 |
635 | ||
0a3e67a4 JB |
636 | struct opregion_header; |
637 | struct opregion_acpi; | |
638 | struct opregion_swsci; | |
639 | struct opregion_asle; | |
640 | ||
8ee1c3db | 641 | struct intel_opregion { |
115719fc WD |
642 | struct opregion_header *header; |
643 | struct opregion_acpi *acpi; | |
644 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
645 | u32 swsci_gbda_sub_functions; |
646 | u32 swsci_sbcb_sub_functions; | |
115719fc | 647 | struct opregion_asle *asle; |
04ebaadb | 648 | void *rvda; |
82730385 | 649 | const void *vbt; |
ada8f955 | 650 | u32 vbt_size; |
115719fc | 651 | u32 *lid_state; |
91a60f20 | 652 | struct work_struct asle_work; |
8ee1c3db | 653 | }; |
44834a67 | 654 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 655 | |
6ef3d427 CW |
656 | struct intel_overlay; |
657 | struct intel_overlay_error_state; | |
658 | ||
9b9d172d | 659 | struct sdvo_device_mapping { |
e957d772 | 660 | u8 initialized; |
9b9d172d | 661 | u8 dvo_port; |
662 | u8 slave_addr; | |
663 | u8 dvo_wiring; | |
e957d772 | 664 | u8 i2c_pin; |
b1083333 | 665 | u8 ddc_pin; |
9b9d172d | 666 | }; |
667 | ||
7bd688cd | 668 | struct intel_connector; |
820d2d77 | 669 | struct intel_encoder; |
ccf010fb | 670 | struct intel_atomic_state; |
5cec258b | 671 | struct intel_crtc_state; |
5724dbd1 | 672 | struct intel_initial_plane_config; |
0e8ffe1b | 673 | struct intel_crtc; |
ee9300bb DV |
674 | struct intel_limit; |
675 | struct dpll; | |
49cd97a3 | 676 | struct intel_cdclk_state; |
b8cecdf5 | 677 | |
e70236a8 | 678 | struct drm_i915_display_funcs { |
49cd97a3 VS |
679 | void (*get_cdclk)(struct drm_i915_private *dev_priv, |
680 | struct intel_cdclk_state *cdclk_state); | |
b0587e4d VS |
681 | void (*set_cdclk)(struct drm_i915_private *dev_priv, |
682 | const struct intel_cdclk_state *cdclk_state); | |
ef0f5e93 | 683 | int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane); |
e3bddded | 684 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
685 | int (*compute_intermediate_wm)(struct drm_device *dev, |
686 | struct intel_crtc *intel_crtc, | |
687 | struct intel_crtc_state *newstate); | |
ccf010fb ML |
688 | void (*initial_watermarks)(struct intel_atomic_state *state, |
689 | struct intel_crtc_state *cstate); | |
690 | void (*atomic_update_watermarks)(struct intel_atomic_state *state, | |
691 | struct intel_crtc_state *cstate); | |
692 | void (*optimize_watermarks)(struct intel_atomic_state *state, | |
693 | struct intel_crtc_state *cstate); | |
98d39494 | 694 | int (*compute_global_watermarks)(struct drm_atomic_state *state); |
432081bc | 695 | void (*update_wm)(struct intel_crtc *crtc); |
27c329ed | 696 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
0e8ffe1b DV |
697 | /* Returns the active state of the crtc, and if the crtc is active, |
698 | * fills out the pipe-config with the hw state. */ | |
699 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 700 | struct intel_crtc_state *); |
5724dbd1 DL |
701 | void (*get_initial_plane_config)(struct intel_crtc *, |
702 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
703 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
704 | struct intel_crtc_state *crtc_state); | |
4a806558 ML |
705 | void (*crtc_enable)(struct intel_crtc_state *pipe_config, |
706 | struct drm_atomic_state *old_state); | |
707 | void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, | |
708 | struct drm_atomic_state *old_state); | |
896e5bb0 L |
709 | void (*update_crtcs)(struct drm_atomic_state *state, |
710 | unsigned int *crtc_vblank_mask); | |
69bfe1a9 JN |
711 | void (*audio_codec_enable)(struct drm_connector *connector, |
712 | struct intel_encoder *encoder, | |
5e7234c9 | 713 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 714 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
dc4a1094 ACO |
715 | void (*fdi_link_train)(struct intel_crtc *crtc, |
716 | const struct intel_crtc_state *crtc_state); | |
46f16e63 | 717 | void (*init_clock_gating)(struct drm_i915_private *dev_priv); |
91d14251 | 718 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
719 | /* clock updates for mode set */ |
720 | /* cursor updates */ | |
721 | /* render clock increase/decrease */ | |
722 | /* display clock increase/decrease */ | |
723 | /* pll clock increase/decrease */ | |
8563b1e8 | 724 | |
b95c5321 ML |
725 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
726 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
727 | }; |
728 | ||
b6e7d894 DL |
729 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
730 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
731 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
732 | ||
eb805623 | 733 | struct intel_csr { |
8144ac59 | 734 | struct work_struct work; |
eb805623 | 735 | const char *fw_path; |
a7f749f9 | 736 | uint32_t *dmc_payload; |
eb805623 | 737 | uint32_t dmc_fw_size; |
b6e7d894 | 738 | uint32_t version; |
eb805623 | 739 | uint32_t mmio_count; |
f0f59a00 | 740 | i915_reg_t mmioaddr[8]; |
eb805623 | 741 | uint32_t mmiodata[8]; |
832dba88 | 742 | uint32_t dc_state; |
a37baf3b | 743 | uint32_t allowed_dc_mask; |
eb805623 DV |
744 | }; |
745 | ||
604db650 JL |
746 | #define DEV_INFO_FOR_EACH_FLAG(func) \ |
747 | func(is_mobile); \ | |
3e4274f8 | 748 | func(is_lp); \ |
c007fb4a | 749 | func(is_alpha_support); \ |
566c56a4 | 750 | /* Keep has_* in alphabetical order */ \ |
dfc5148f | 751 | func(has_64bit_reloc); \ |
9e1d0e60 | 752 | func(has_aliasing_ppgtt); \ |
604db650 | 753 | func(has_csr); \ |
566c56a4 | 754 | func(has_ddi); \ |
604db650 | 755 | func(has_dp_mst); \ |
142bc7d9 | 756 | func(has_reset_engine); \ |
566c56a4 JL |
757 | func(has_fbc); \ |
758 | func(has_fpga_dbg); \ | |
9e1d0e60 MT |
759 | func(has_full_ppgtt); \ |
760 | func(has_full_48bit_ppgtt); \ | |
604db650 | 761 | func(has_gmbus_irq); \ |
604db650 JL |
762 | func(has_gmch_display); \ |
763 | func(has_guc); \ | |
f8a58d63 | 764 | func(has_guc_ct); \ |
604db650 | 765 | func(has_hotplug); \ |
566c56a4 | 766 | func(has_l3_dpf); \ |
604db650 | 767 | func(has_llc); \ |
566c56a4 JL |
768 | func(has_logical_ring_contexts); \ |
769 | func(has_overlay); \ | |
770 | func(has_pipe_cxsr); \ | |
771 | func(has_pooled_eu); \ | |
772 | func(has_psr); \ | |
773 | func(has_rc6); \ | |
774 | func(has_rc6p); \ | |
775 | func(has_resource_streamer); \ | |
776 | func(has_runtime_pm); \ | |
604db650 | 777 | func(has_snoop); \ |
f4ce766f | 778 | func(unfenced_needs_alignment); \ |
566c56a4 JL |
779 | func(cursor_needs_physical); \ |
780 | func(hws_needs_physical); \ | |
781 | func(overlay_needs_physical); \ | |
70821af6 | 782 | func(supports_tv); |
c96ea64e | 783 | |
915490d5 | 784 | struct sseu_dev_info { |
f08a0c92 | 785 | u8 slice_mask; |
57ec171e | 786 | u8 subslice_mask; |
915490d5 ID |
787 | u8 eu_total; |
788 | u8 eu_per_subslice; | |
43b67998 ID |
789 | u8 min_eu_in_pool; |
790 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ | |
791 | u8 subslice_7eu[3]; | |
792 | u8 has_slice_pg:1; | |
793 | u8 has_subslice_pg:1; | |
794 | u8 has_eu_pg:1; | |
915490d5 ID |
795 | }; |
796 | ||
57ec171e ID |
797 | static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) |
798 | { | |
799 | return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); | |
800 | } | |
801 | ||
2e0d26f8 JN |
802 | /* Keep in gen based order, and chronological order within a gen */ |
803 | enum intel_platform { | |
804 | INTEL_PLATFORM_UNINITIALIZED = 0, | |
805 | INTEL_I830, | |
806 | INTEL_I845G, | |
807 | INTEL_I85X, | |
808 | INTEL_I865G, | |
809 | INTEL_I915G, | |
810 | INTEL_I915GM, | |
811 | INTEL_I945G, | |
812 | INTEL_I945GM, | |
813 | INTEL_G33, | |
814 | INTEL_PINEVIEW, | |
c0f86832 JN |
815 | INTEL_I965G, |
816 | INTEL_I965GM, | |
f69c11ae JN |
817 | INTEL_G45, |
818 | INTEL_GM45, | |
2e0d26f8 JN |
819 | INTEL_IRONLAKE, |
820 | INTEL_SANDYBRIDGE, | |
821 | INTEL_IVYBRIDGE, | |
822 | INTEL_VALLEYVIEW, | |
823 | INTEL_HASWELL, | |
824 | INTEL_BROADWELL, | |
825 | INTEL_CHERRYVIEW, | |
826 | INTEL_SKYLAKE, | |
827 | INTEL_BROXTON, | |
828 | INTEL_KABYLAKE, | |
829 | INTEL_GEMINILAKE, | |
71851fa8 | 830 | INTEL_COFFEELAKE, |
413f3c19 | 831 | INTEL_CANNONLAKE, |
9160095c | 832 | INTEL_MAX_PLATFORMS |
2e0d26f8 JN |
833 | }; |
834 | ||
cfdf1fa2 | 835 | struct intel_device_info { |
10fce67a | 836 | u32 display_mmio_offset; |
87f1f465 | 837 | u16 device_id; |
ac208a8b | 838 | u8 num_pipes; |
d615a166 | 839 | u8 num_sprites[I915_MAX_PIPES]; |
1c74eeaf | 840 | u8 num_scalers[I915_MAX_PIPES]; |
c96c3a8c | 841 | u8 gen; |
ae5702d2 | 842 | u16 gen_mask; |
2e0d26f8 | 843 | enum intel_platform platform; |
73ae478c | 844 | u8 ring_mask; /* Rings supported by the HW */ |
c1bb1145 | 845 | u8 num_rings; |
604db650 JL |
846 | #define DEFINE_FLAG(name) u8 name:1 |
847 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG); | |
848 | #undef DEFINE_FLAG | |
6f3fff60 | 849 | u16 ddb_size; /* in blocks */ |
a57c774a AK |
850 | /* Register offsets for the various display pipes and transcoders */ |
851 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
852 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 853 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 854 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
855 | |
856 | /* Slice/subslice/EU info */ | |
43b67998 | 857 | struct sseu_dev_info sseu; |
82cf435b LL |
858 | |
859 | struct color_luts { | |
860 | u16 degamma_lut_size; | |
861 | u16 gamma_lut_size; | |
862 | } color; | |
cfdf1fa2 KH |
863 | }; |
864 | ||
2bd160a1 CW |
865 | struct intel_display_error_state; |
866 | ||
5a4c6f1b | 867 | struct i915_gpu_state { |
2bd160a1 CW |
868 | struct kref ref; |
869 | struct timeval time; | |
de867c20 CW |
870 | struct timeval boottime; |
871 | struct timeval uptime; | |
2bd160a1 | 872 | |
9f267eb8 CW |
873 | struct drm_i915_private *i915; |
874 | ||
2bd160a1 CW |
875 | char error_msg[128]; |
876 | bool simulated; | |
f73b5674 | 877 | bool awake; |
e5aac87e CW |
878 | bool wakelock; |
879 | bool suspended; | |
2bd160a1 CW |
880 | int iommu; |
881 | u32 reset_count; | |
882 | u32 suspend_count; | |
883 | struct intel_device_info device_info; | |
642c8a72 | 884 | struct i915_params params; |
2bd160a1 CW |
885 | |
886 | /* Generic register state */ | |
887 | u32 eir; | |
888 | u32 pgtbl_er; | |
889 | u32 ier; | |
5a4c6f1b | 890 | u32 gtier[4], ngtier; |
2bd160a1 CW |
891 | u32 ccid; |
892 | u32 derrmr; | |
893 | u32 forcewake; | |
894 | u32 error; /* gen6+ */ | |
895 | u32 err_int; /* gen7 */ | |
896 | u32 fault_data0; /* gen8, gen9 */ | |
897 | u32 fault_data1; /* gen8, gen9 */ | |
898 | u32 done_reg; | |
899 | u32 gac_eco; | |
900 | u32 gam_ecochk; | |
901 | u32 gab_ctl; | |
902 | u32 gfx_mode; | |
d636951e | 903 | |
5a4c6f1b | 904 | u32 nfence; |
2bd160a1 CW |
905 | u64 fence[I915_MAX_NUM_FENCES]; |
906 | struct intel_overlay_error_state *overlay; | |
907 | struct intel_display_error_state *display; | |
51d545d0 | 908 | struct drm_i915_error_object *semaphore; |
27b85bea | 909 | struct drm_i915_error_object *guc_log; |
2bd160a1 CW |
910 | |
911 | struct drm_i915_error_engine { | |
912 | int engine_id; | |
913 | /* Software tracked state */ | |
914 | bool waiting; | |
915 | int num_waiters; | |
3fe3b030 MK |
916 | unsigned long hangcheck_timestamp; |
917 | bool hangcheck_stalled; | |
2bd160a1 CW |
918 | enum intel_engine_hangcheck_action hangcheck_action; |
919 | struct i915_address_space *vm; | |
920 | int num_requests; | |
702c8f8e | 921 | u32 reset_count; |
2bd160a1 | 922 | |
cdb324bd CW |
923 | /* position of active request inside the ring */ |
924 | u32 rq_head, rq_post, rq_tail; | |
925 | ||
2bd160a1 CW |
926 | /* our own tracking of ring head and tail */ |
927 | u32 cpu_ring_head; | |
928 | u32 cpu_ring_tail; | |
929 | ||
930 | u32 last_seqno; | |
2bd160a1 CW |
931 | |
932 | /* Register state */ | |
933 | u32 start; | |
934 | u32 tail; | |
935 | u32 head; | |
936 | u32 ctl; | |
21a2c58a | 937 | u32 mode; |
2bd160a1 CW |
938 | u32 hws; |
939 | u32 ipeir; | |
940 | u32 ipehr; | |
2bd160a1 CW |
941 | u32 bbstate; |
942 | u32 instpm; | |
943 | u32 instps; | |
944 | u32 seqno; | |
945 | u64 bbaddr; | |
946 | u64 acthd; | |
947 | u32 fault_reg; | |
948 | u64 faddr; | |
949 | u32 rc_psmi; /* sleep state */ | |
950 | u32 semaphore_mboxes[I915_NUM_ENGINES - 1]; | |
d636951e | 951 | struct intel_instdone instdone; |
2bd160a1 | 952 | |
4fa6053e CW |
953 | struct drm_i915_error_context { |
954 | char comm[TASK_COMM_LEN]; | |
955 | pid_t pid; | |
956 | u32 handle; | |
957 | u32 hw_id; | |
958 | int ban_score; | |
959 | int active; | |
960 | int guilty; | |
961 | } context; | |
962 | ||
2bd160a1 | 963 | struct drm_i915_error_object { |
2bd160a1 | 964 | u64 gtt_offset; |
03382dfb | 965 | u64 gtt_size; |
0a97015d CW |
966 | int page_count; |
967 | int unused; | |
2bd160a1 CW |
968 | u32 *pages[0]; |
969 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; | |
970 | ||
b0fd47ad CW |
971 | struct drm_i915_error_object **user_bo; |
972 | long user_bo_count; | |
973 | ||
2bd160a1 CW |
974 | struct drm_i915_error_object *wa_ctx; |
975 | ||
976 | struct drm_i915_error_request { | |
977 | long jiffies; | |
c84455b4 | 978 | pid_t pid; |
35ca039e | 979 | u32 context; |
84102171 | 980 | int ban_score; |
2bd160a1 CW |
981 | u32 seqno; |
982 | u32 head; | |
983 | u32 tail; | |
35ca039e | 984 | } *requests, execlist[2]; |
2bd160a1 CW |
985 | |
986 | struct drm_i915_error_waiter { | |
987 | char comm[TASK_COMM_LEN]; | |
988 | pid_t pid; | |
989 | u32 seqno; | |
990 | } *waiters; | |
991 | ||
992 | struct { | |
993 | u32 gfx_mode; | |
994 | union { | |
995 | u64 pdp[4]; | |
996 | u32 pp_dir_base; | |
997 | }; | |
998 | } vm_info; | |
2bd160a1 CW |
999 | } engine[I915_NUM_ENGINES]; |
1000 | ||
1001 | struct drm_i915_error_buffer { | |
1002 | u32 size; | |
1003 | u32 name; | |
1004 | u32 rseqno[I915_NUM_ENGINES], wseqno; | |
1005 | u64 gtt_offset; | |
1006 | u32 read_domains; | |
1007 | u32 write_domain; | |
1008 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; | |
1009 | u32 tiling:2; | |
1010 | u32 dirty:1; | |
1011 | u32 purgeable:1; | |
1012 | u32 userptr:1; | |
1013 | s32 engine:4; | |
1014 | u32 cache_level:3; | |
1015 | } *active_bo[I915_NUM_ENGINES], *pinned_bo; | |
1016 | u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count; | |
1017 | struct i915_address_space *active_vm[I915_NUM_ENGINES]; | |
1018 | }; | |
1019 | ||
7faf1ab2 DV |
1020 | enum i915_cache_level { |
1021 | I915_CACHE_NONE = 0, | |
350ec881 CW |
1022 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
1023 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
1024 | caches, eg sampler/render caches, and the | |
1025 | large Last-Level-Cache. LLC is coherent with | |
1026 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 1027 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
1028 | }; |
1029 | ||
85fd4f58 CW |
1030 | #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ |
1031 | ||
a4001f1b PZ |
1032 | enum fb_op_origin { |
1033 | ORIGIN_GTT, | |
1034 | ORIGIN_CPU, | |
1035 | ORIGIN_CS, | |
1036 | ORIGIN_FLIP, | |
74b4ea1e | 1037 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
1038 | }; |
1039 | ||
ab34a7e8 | 1040 | struct intel_fbc { |
25ad93fd PZ |
1041 | /* This is always the inner lock when overlapping with struct_mutex and |
1042 | * it's the outer lock when overlapping with stolen_lock. */ | |
1043 | struct mutex lock; | |
5e59f717 | 1044 | unsigned threshold; |
dbef0f15 PZ |
1045 | unsigned int possible_framebuffer_bits; |
1046 | unsigned int busy_bits; | |
010cf73d | 1047 | unsigned int visible_pipes_mask; |
e35fef21 | 1048 | struct intel_crtc *crtc; |
5c3fe8b0 | 1049 | |
c4213885 | 1050 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
1051 | struct drm_mm_node *compressed_llb; |
1052 | ||
da46f936 RV |
1053 | bool false_color; |
1054 | ||
d029bcad | 1055 | bool enabled; |
0e631adc | 1056 | bool active; |
9adccc60 | 1057 | |
61a585d6 PZ |
1058 | bool underrun_detected; |
1059 | struct work_struct underrun_work; | |
1060 | ||
aaf78d27 | 1061 | struct intel_fbc_state_cache { |
be1e3415 CW |
1062 | struct i915_vma *vma; |
1063 | ||
aaf78d27 PZ |
1064 | struct { |
1065 | unsigned int mode_flags; | |
1066 | uint32_t hsw_bdw_pixel_rate; | |
1067 | } crtc; | |
1068 | ||
1069 | struct { | |
1070 | unsigned int rotation; | |
1071 | int src_w; | |
1072 | int src_h; | |
1073 | bool visible; | |
1074 | } plane; | |
1075 | ||
1076 | struct { | |
801c8fe8 | 1077 | const struct drm_format_info *format; |
aaf78d27 | 1078 | unsigned int stride; |
aaf78d27 PZ |
1079 | } fb; |
1080 | } state_cache; | |
1081 | ||
b183b3f1 | 1082 | struct intel_fbc_reg_params { |
be1e3415 CW |
1083 | struct i915_vma *vma; |
1084 | ||
b183b3f1 PZ |
1085 | struct { |
1086 | enum pipe pipe; | |
1087 | enum plane plane; | |
1088 | unsigned int fence_y_offset; | |
1089 | } crtc; | |
1090 | ||
1091 | struct { | |
801c8fe8 | 1092 | const struct drm_format_info *format; |
b183b3f1 | 1093 | unsigned int stride; |
b183b3f1 PZ |
1094 | } fb; |
1095 | ||
1096 | int cfb_size; | |
1097 | } params; | |
1098 | ||
5c3fe8b0 | 1099 | struct intel_fbc_work { |
128d7356 | 1100 | bool scheduled; |
ca18d51d | 1101 | u32 scheduled_vblank; |
128d7356 | 1102 | struct work_struct work; |
128d7356 | 1103 | } work; |
5c3fe8b0 | 1104 | |
bf6189c6 | 1105 | const char *no_fbc_reason; |
b5e50c3f JB |
1106 | }; |
1107 | ||
fe88d122 | 1108 | /* |
96178eeb VK |
1109 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
1110 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
1111 | * parsing for same resolution. | |
1112 | */ | |
1113 | enum drrs_refresh_rate_type { | |
1114 | DRRS_HIGH_RR, | |
1115 | DRRS_LOW_RR, | |
1116 | DRRS_MAX_RR, /* RR count */ | |
1117 | }; | |
1118 | ||
1119 | enum drrs_support_type { | |
1120 | DRRS_NOT_SUPPORTED = 0, | |
1121 | STATIC_DRRS_SUPPORT = 1, | |
1122 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
1123 | }; |
1124 | ||
2807cf69 | 1125 | struct intel_dp; |
96178eeb VK |
1126 | struct i915_drrs { |
1127 | struct mutex mutex; | |
1128 | struct delayed_work work; | |
1129 | struct intel_dp *dp; | |
1130 | unsigned busy_frontbuffer_bits; | |
1131 | enum drrs_refresh_rate_type refresh_rate_type; | |
1132 | enum drrs_support_type type; | |
1133 | }; | |
1134 | ||
a031d709 | 1135 | struct i915_psr { |
f0355c4a | 1136 | struct mutex lock; |
a031d709 RV |
1137 | bool sink_support; |
1138 | bool source_ok; | |
2807cf69 | 1139 | struct intel_dp *enabled; |
7c8f8a70 RV |
1140 | bool active; |
1141 | struct delayed_work work; | |
9ca15301 | 1142 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
1143 | bool psr2_support; |
1144 | bool aux_frame_sync; | |
60e5ffe3 | 1145 | bool link_standby; |
97da2ef4 NV |
1146 | bool y_cord_support; |
1147 | bool colorimetry_support; | |
340c93c0 | 1148 | bool alpm; |
3f51e471 | 1149 | }; |
5c3fe8b0 | 1150 | |
3bad0781 | 1151 | enum intel_pch { |
f0350830 | 1152 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 | 1153 | PCH_IBX, /* Ibexpeak PCH */ |
243dec58 VS |
1154 | PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ |
1155 | PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ | |
e7e7ea20 | 1156 | PCH_SPT, /* Sunrisepoint PCH */ |
22dea0be | 1157 | PCH_KBP, /* Kabypoint PCH */ |
7b22b8c4 | 1158 | PCH_CNP, /* Cannonpoint PCH */ |
40c7ead9 | 1159 | PCH_NOP, |
3bad0781 ZW |
1160 | }; |
1161 | ||
988d6ee8 PZ |
1162 | enum intel_sbi_destination { |
1163 | SBI_ICLK, | |
1164 | SBI_MPHY, | |
1165 | }; | |
1166 | ||
435793df | 1167 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1168 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1169 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
656bfa3a | 1170 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
c99a259b | 1171 | #define QUIRK_INCREASE_T12_DELAY (1<<6) |
b690e96c | 1172 | |
8be48d92 | 1173 | struct intel_fbdev; |
1630fe75 | 1174 | struct intel_fbc_work; |
38651674 | 1175 | |
c2b9152f DV |
1176 | struct intel_gmbus { |
1177 | struct i2c_adapter adapter; | |
3e4d44e0 | 1178 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 1179 | u32 force_bit; |
c2b9152f | 1180 | u32 reg0; |
f0f59a00 | 1181 | i915_reg_t gpio_reg; |
c167a6fc | 1182 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1183 | struct drm_i915_private *dev_priv; |
1184 | }; | |
1185 | ||
f4c956ad | 1186 | struct i915_suspend_saved_registers { |
e948e994 | 1187 | u32 saveDSPARB; |
ba8bbcf6 | 1188 | u32 saveFBC_CONTROL; |
1f84e550 | 1189 | u32 saveCACHE_MODE_0; |
1f84e550 | 1190 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1191 | u32 saveSWF0[16]; |
1192 | u32 saveSWF1[16]; | |
85fa792b | 1193 | u32 saveSWF3[3]; |
4b9de737 | 1194 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1195 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1196 | u16 saveGCDGMBUS; |
f4c956ad | 1197 | }; |
c85aa885 | 1198 | |
ddeea5b0 ID |
1199 | struct vlv_s0ix_state { |
1200 | /* GAM */ | |
1201 | u32 wr_watermark; | |
1202 | u32 gfx_prio_ctrl; | |
1203 | u32 arb_mode; | |
1204 | u32 gfx_pend_tlb0; | |
1205 | u32 gfx_pend_tlb1; | |
1206 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1207 | u32 media_max_req_count; | |
1208 | u32 gfx_max_req_count; | |
1209 | u32 render_hwsp; | |
1210 | u32 ecochk; | |
1211 | u32 bsd_hwsp; | |
1212 | u32 blt_hwsp; | |
1213 | u32 tlb_rd_addr; | |
1214 | ||
1215 | /* MBC */ | |
1216 | u32 g3dctl; | |
1217 | u32 gsckgctl; | |
1218 | u32 mbctl; | |
1219 | ||
1220 | /* GCP */ | |
1221 | u32 ucgctl1; | |
1222 | u32 ucgctl3; | |
1223 | u32 rcgctl1; | |
1224 | u32 rcgctl2; | |
1225 | u32 rstctl; | |
1226 | u32 misccpctl; | |
1227 | ||
1228 | /* GPM */ | |
1229 | u32 gfxpause; | |
1230 | u32 rpdeuhwtc; | |
1231 | u32 rpdeuc; | |
1232 | u32 ecobus; | |
1233 | u32 pwrdwnupctl; | |
1234 | u32 rp_down_timeout; | |
1235 | u32 rp_deucsw; | |
1236 | u32 rcubmabdtmr; | |
1237 | u32 rcedata; | |
1238 | u32 spare2gh; | |
1239 | ||
1240 | /* Display 1 CZ domain */ | |
1241 | u32 gt_imr; | |
1242 | u32 gt_ier; | |
1243 | u32 pm_imr; | |
1244 | u32 pm_ier; | |
1245 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1246 | ||
1247 | /* GT SA CZ domain */ | |
1248 | u32 tilectl; | |
1249 | u32 gt_fifoctl; | |
1250 | u32 gtlc_wake_ctrl; | |
1251 | u32 gtlc_survive; | |
1252 | u32 pmwgicz; | |
1253 | ||
1254 | /* Display 2 CZ domain */ | |
1255 | u32 gu_ctl0; | |
1256 | u32 gu_ctl1; | |
9c25210f | 1257 | u32 pcbr; |
ddeea5b0 ID |
1258 | u32 clock_gate_dis2; |
1259 | }; | |
1260 | ||
bf225f20 | 1261 | struct intel_rps_ei { |
679cb6c1 | 1262 | ktime_t ktime; |
bf225f20 CW |
1263 | u32 render_c0; |
1264 | u32 media_c0; | |
31685c25 D |
1265 | }; |
1266 | ||
c85aa885 | 1267 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1268 | /* |
1269 | * work, interrupts_enabled and pm_iir are protected by | |
1270 | * dev_priv->irq_lock | |
1271 | */ | |
c85aa885 | 1272 | struct work_struct work; |
d4d70aa5 | 1273 | bool interrupts_enabled; |
c85aa885 | 1274 | u32 pm_iir; |
59cdb63d | 1275 | |
b20e3cfe | 1276 | /* PM interrupt bits that should never be masked */ |
5dd04556 | 1277 | u32 pm_intrmsk_mbz; |
1800ad25 | 1278 | |
b39fb297 BW |
1279 | /* Frequencies are stored in potentially platform dependent multiples. |
1280 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1281 | * Soft limits are those which are used for the dynamic reclocking done | |
1282 | * by the driver (raise frequencies under heavy loads, and lower for | |
1283 | * lighter loads). Hard limits are those imposed by the hardware. | |
1284 | * | |
1285 | * A distinction is made for overclocking, which is never enabled by | |
1286 | * default, and is considered to be above the hard limit if it's | |
1287 | * possible at all. | |
1288 | */ | |
1289 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1290 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1291 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1292 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1293 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
29ecd78d | 1294 | u8 boost_freq; /* Frequency to request when wait boosting */ |
aed242ff | 1295 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1296 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1297 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1298 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 1299 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 1300 | |
8fb55197 CW |
1301 | u8 up_threshold; /* Current %busy required to uplock */ |
1302 | u8 down_threshold; /* Current %busy required to downclock */ | |
1303 | ||
dd75fdc8 CW |
1304 | int last_adj; |
1305 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1306 | ||
c0951f0c | 1307 | bool enabled; |
54b4f68f | 1308 | struct delayed_work autoenable_work; |
7b92c1bd CW |
1309 | atomic_t num_waiters; |
1310 | atomic_t boosts; | |
4fc688ce | 1311 | |
bf225f20 | 1312 | /* manual wa residency calculations */ |
e0e8c7cb | 1313 | struct intel_rps_ei ei; |
bf225f20 | 1314 | |
4fc688ce JB |
1315 | /* |
1316 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1317 | * Must be taken after struct_mutex if nested. Note that |
1318 | * this lock may be held for long periods of time when | |
1319 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1320 | */ |
1321 | struct mutex hw_lock; | |
c85aa885 DV |
1322 | }; |
1323 | ||
1a240d4d DV |
1324 | /* defined intel_pm.c */ |
1325 | extern spinlock_t mchdev_lock; | |
1326 | ||
c85aa885 DV |
1327 | struct intel_ilk_power_mgmt { |
1328 | u8 cur_delay; | |
1329 | u8 min_delay; | |
1330 | u8 max_delay; | |
1331 | u8 fmax; | |
1332 | u8 fstart; | |
1333 | ||
1334 | u64 last_count1; | |
1335 | unsigned long last_time1; | |
1336 | unsigned long chipset_power; | |
1337 | u64 last_count2; | |
5ed0bdf2 | 1338 | u64 last_time2; |
c85aa885 DV |
1339 | unsigned long gfx_power; |
1340 | u8 corr; | |
1341 | ||
1342 | int c_m; | |
1343 | int r_t; | |
1344 | }; | |
1345 | ||
c6cb582e ID |
1346 | struct drm_i915_private; |
1347 | struct i915_power_well; | |
1348 | ||
1349 | struct i915_power_well_ops { | |
1350 | /* | |
1351 | * Synchronize the well's hw state to match the current sw state, for | |
1352 | * example enable/disable it based on the current refcount. Called | |
1353 | * during driver init and resume time, possibly after first calling | |
1354 | * the enable/disable handlers. | |
1355 | */ | |
1356 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1357 | struct i915_power_well *power_well); | |
1358 | /* | |
1359 | * Enable the well and resources that depend on it (for example | |
1360 | * interrupts located on the well). Called after the 0->1 refcount | |
1361 | * transition. | |
1362 | */ | |
1363 | void (*enable)(struct drm_i915_private *dev_priv, | |
1364 | struct i915_power_well *power_well); | |
1365 | /* | |
1366 | * Disable the well and resources that depend on it. Called after | |
1367 | * the 1->0 refcount transition. | |
1368 | */ | |
1369 | void (*disable)(struct drm_i915_private *dev_priv, | |
1370 | struct i915_power_well *power_well); | |
1371 | /* Returns the hw enabled state. */ | |
1372 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1373 | struct i915_power_well *power_well); | |
1374 | }; | |
1375 | ||
a38911a3 WX |
1376 | /* Power well structure for haswell */ |
1377 | struct i915_power_well { | |
c1ca727f | 1378 | const char *name; |
6f3ef5dd | 1379 | bool always_on; |
a38911a3 WX |
1380 | /* power well enable/disable usage count */ |
1381 | int count; | |
bfafe93a ID |
1382 | /* cached hw enabled state */ |
1383 | bool hw_enabled; | |
d8fc70b7 | 1384 | u64 domains; |
01c3faa7 | 1385 | /* unique identifier for this power well */ |
438b8dc4 | 1386 | enum i915_power_well_id id; |
362624c9 ACO |
1387 | /* |
1388 | * Arbitraty data associated with this power well. Platform and power | |
1389 | * well specific. | |
1390 | */ | |
b5565a2e ID |
1391 | union { |
1392 | struct { | |
1393 | enum dpio_phy phy; | |
1394 | } bxt; | |
1395 | }; | |
c6cb582e | 1396 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1397 | }; |
1398 | ||
83c00f55 | 1399 | struct i915_power_domains { |
baa70707 ID |
1400 | /* |
1401 | * Power wells needed for initialization at driver init and suspend | |
1402 | * time are on. They are kept on until after the first modeset. | |
1403 | */ | |
1404 | bool init_power_on; | |
0d116a29 | 1405 | bool initializing; |
c1ca727f | 1406 | int power_well_count; |
baa70707 | 1407 | |
83c00f55 | 1408 | struct mutex lock; |
1da51581 | 1409 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1410 | struct i915_power_well *power_wells; |
83c00f55 ID |
1411 | }; |
1412 | ||
35a85ac6 | 1413 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1414 | struct intel_l3_parity { |
35a85ac6 | 1415 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1416 | struct work_struct error_work; |
35a85ac6 | 1417 | int which_slice; |
a4da4fa4 DV |
1418 | }; |
1419 | ||
4b5aed62 | 1420 | struct i915_gem_mm { |
4b5aed62 DV |
1421 | /** Memory allocator for GTT stolen memory */ |
1422 | struct drm_mm stolen; | |
92e97d2f PZ |
1423 | /** Protects the usage of the GTT stolen memory allocator. This is |
1424 | * always the inner lock when overlapping with struct_mutex. */ | |
1425 | struct mutex stolen_lock; | |
1426 | ||
4b5aed62 DV |
1427 | /** List of all objects in gtt_space. Used to restore gtt |
1428 | * mappings on resume */ | |
1429 | struct list_head bound_list; | |
1430 | /** | |
1431 | * List of objects which are not bound to the GTT (thus | |
fbbd37b3 CW |
1432 | * are idle and not used by the GPU). These objects may or may |
1433 | * not actually have any pages attached. | |
4b5aed62 DV |
1434 | */ |
1435 | struct list_head unbound_list; | |
1436 | ||
275f039d CW |
1437 | /** List of all objects in gtt_space, currently mmaped by userspace. |
1438 | * All objects within this list must also be on bound_list. | |
1439 | */ | |
1440 | struct list_head userfault_list; | |
1441 | ||
fbbd37b3 CW |
1442 | /** |
1443 | * List of objects which are pending destruction. | |
1444 | */ | |
1445 | struct llist_head free_list; | |
1446 | struct work_struct free_work; | |
1447 | ||
4b5aed62 | 1448 | /** Usable portion of the GTT for GEM */ |
c8847387 | 1449 | dma_addr_t stolen_base; /* limited to low memory (32-bit) */ |
4b5aed62 | 1450 | |
4b5aed62 DV |
1451 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1452 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1453 | ||
2cfcd32a | 1454 | struct notifier_block oom_notifier; |
e87666b5 | 1455 | struct notifier_block vmap_notifier; |
ceabbba5 | 1456 | struct shrinker shrinker; |
4b5aed62 | 1457 | |
4b5aed62 DV |
1458 | /** LRU list of objects with fence regs on them. */ |
1459 | struct list_head fence_list; | |
1460 | ||
8a2421bd CW |
1461 | /** |
1462 | * Workqueue to fault in userptr pages, flushed by the execbuf | |
1463 | * when required but otherwise left to userspace to try again | |
1464 | * on EAGAIN. | |
1465 | */ | |
1466 | struct workqueue_struct *userptr_wq; | |
1467 | ||
94312828 CW |
1468 | u64 unordered_timeline; |
1469 | ||
bdf1e7e3 | 1470 | /* the indicator for dispatch video commands on two BSD rings */ |
6f633402 | 1471 | atomic_t bsd_engine_dispatch_index; |
bdf1e7e3 | 1472 | |
4b5aed62 DV |
1473 | /** Bit 6 swizzling required for X tiling */ |
1474 | uint32_t bit_6_swizzle_x; | |
1475 | /** Bit 6 swizzling required for Y tiling */ | |
1476 | uint32_t bit_6_swizzle_y; | |
1477 | ||
4b5aed62 | 1478 | /* accounting, useful for userland debugging */ |
c20e8355 | 1479 | spinlock_t object_stat_lock; |
3ef7f228 | 1480 | u64 object_memory; |
4b5aed62 DV |
1481 | u32 object_count; |
1482 | }; | |
1483 | ||
edc3d884 | 1484 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1485 | struct drm_i915_private *i915; |
edc3d884 MK |
1486 | unsigned bytes; |
1487 | unsigned size; | |
1488 | int err; | |
1489 | u8 *buf; | |
1490 | loff_t start; | |
1491 | loff_t pos; | |
1492 | }; | |
1493 | ||
b52992c0 CW |
1494 | #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ |
1495 | #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ | |
1496 | ||
3fe3b030 MK |
1497 | #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ |
1498 | #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ | |
1499 | ||
99584db3 DV |
1500 | struct i915_gpu_error { |
1501 | /* For hangcheck timer */ | |
1502 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1503 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 | 1504 | |
737b1506 | 1505 | struct delayed_work hangcheck_work; |
99584db3 DV |
1506 | |
1507 | /* For reset and error_state handling. */ | |
1508 | spinlock_t lock; | |
1509 | /* Protected by the above dev->gpu_error.lock. */ | |
5a4c6f1b | 1510 | struct i915_gpu_state *first_error; |
094f9a54 CW |
1511 | |
1512 | unsigned long missed_irq_rings; | |
1513 | ||
1f83fee0 | 1514 | /** |
2ac0f450 | 1515 | * State variable controlling the reset flow and count |
1f83fee0 | 1516 | * |
2ac0f450 | 1517 | * This is a counter which gets incremented when reset is triggered, |
8af29b0c | 1518 | * |
56306c6e | 1519 | * Before the reset commences, the I915_RESET_BACKOFF bit is set |
8af29b0c CW |
1520 | * meaning that any waiters holding onto the struct_mutex should |
1521 | * relinquish the lock immediately in order for the reset to start. | |
2ac0f450 MK |
1522 | * |
1523 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1524 | * set meaning that hardware is terminally sour and there is no | |
1525 | * recovery. All waiters on the reset_queue will be woken when | |
1526 | * that happens. | |
1527 | * | |
1528 | * This counter is used by the wait_seqno code to notice that reset | |
1529 | * event happened and it needs to restart the entire ioctl (since most | |
1530 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1531 | * |
1532 | * This is important for lock-free wait paths, where no contended lock | |
1533 | * naturally enforces the correct ordering between the bail-out of the | |
1534 | * waiter and the gpu reset work code. | |
1f83fee0 | 1535 | */ |
8af29b0c | 1536 | unsigned long reset_count; |
1f83fee0 | 1537 | |
8c185eca CW |
1538 | /** |
1539 | * flags: Control various stages of the GPU reset | |
1540 | * | |
1541 | * #I915_RESET_BACKOFF - When we start a reset, we want to stop any | |
1542 | * other users acquiring the struct_mutex. To do this we set the | |
1543 | * #I915_RESET_BACKOFF bit in the error flags when we detect a reset | |
1544 | * and then check for that bit before acquiring the struct_mutex (in | |
1545 | * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a | |
1546 | * secondary role in preventing two concurrent global reset attempts. | |
1547 | * | |
1548 | * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the | |
1549 | * struct_mutex. We try to acquire the struct_mutex in the reset worker, | |
1550 | * but it may be held by some long running waiter (that we cannot | |
1551 | * interrupt without causing trouble). Once we are ready to do the GPU | |
1552 | * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If | |
1553 | * they already hold the struct_mutex and want to participate they can | |
1554 | * inspect the bit and do the reset directly, otherwise the worker | |
1555 | * waits for the struct_mutex. | |
1556 | * | |
142bc7d9 MT |
1557 | * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to |
1558 | * acquire the struct_mutex to reset an engine, we need an explicit | |
1559 | * flag to prevent two concurrent reset attempts in the same engine. | |
1560 | * As the number of engines continues to grow, allocate the flags from | |
1561 | * the most significant bits. | |
1562 | * | |
8c185eca CW |
1563 | * #I915_WEDGED - If reset fails and we can no longer use the GPU, |
1564 | * we set the #I915_WEDGED bit. Prior to command submission, e.g. | |
1565 | * i915_gem_request_alloc(), this bit is checked and the sequence | |
1566 | * aborted (with -EIO reported to userspace) if set. | |
1567 | */ | |
8af29b0c | 1568 | unsigned long flags; |
8c185eca CW |
1569 | #define I915_RESET_BACKOFF 0 |
1570 | #define I915_RESET_HANDOFF 1 | |
8af29b0c | 1571 | #define I915_WEDGED (BITS_PER_LONG - 1) |
142bc7d9 | 1572 | #define I915_RESET_ENGINE (I915_WEDGED - I915_NUM_ENGINES) |
1f83fee0 | 1573 | |
702c8f8e MT |
1574 | /** Number of times an engine has been reset */ |
1575 | u32 reset_engine_count[I915_NUM_ENGINES]; | |
1576 | ||
1f15b76f CW |
1577 | /** |
1578 | * Waitqueue to signal when a hang is detected. Used to for waiters | |
1579 | * to release the struct_mutex for the reset to procede. | |
1580 | */ | |
1581 | wait_queue_head_t wait_queue; | |
1582 | ||
1f83fee0 DV |
1583 | /** |
1584 | * Waitqueue to signal when the reset has completed. Used by clients | |
1585 | * that wait for dev_priv->mm.wedged to settle. | |
1586 | */ | |
1587 | wait_queue_head_t reset_queue; | |
33196ded | 1588 | |
094f9a54 | 1589 | /* For missed irq/seqno simulation. */ |
688e6c72 | 1590 | unsigned long test_irq_rings; |
99584db3 DV |
1591 | }; |
1592 | ||
b8efb17b ZR |
1593 | enum modeset_restore { |
1594 | MODESET_ON_LID_OPEN, | |
1595 | MODESET_DONE, | |
1596 | MODESET_SUSPENDED, | |
1597 | }; | |
1598 | ||
500ea70d RV |
1599 | #define DP_AUX_A 0x40 |
1600 | #define DP_AUX_B 0x10 | |
1601 | #define DP_AUX_C 0x20 | |
1602 | #define DP_AUX_D 0x30 | |
1603 | ||
11c1b657 XZ |
1604 | #define DDC_PIN_B 0x05 |
1605 | #define DDC_PIN_C 0x04 | |
1606 | #define DDC_PIN_D 0x06 | |
1607 | ||
6acab15a | 1608 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1609 | /* |
1610 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1611 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1612 | * populate this field. | |
1613 | */ | |
1614 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1615 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1616 | |
1617 | uint8_t supports_dvi:1; | |
1618 | uint8_t supports_hdmi:1; | |
1619 | uint8_t supports_dp:1; | |
a98d9c1d | 1620 | uint8_t supports_edp:1; |
500ea70d RV |
1621 | |
1622 | uint8_t alternate_aux_channel; | |
11c1b657 | 1623 | uint8_t alternate_ddc_pin; |
75067dde AK |
1624 | |
1625 | uint8_t dp_boost_level; | |
1626 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1627 | }; |
1628 | ||
bfd7ebda RV |
1629 | enum psr_lines_to_wait { |
1630 | PSR_0_LINES_TO_WAIT = 0, | |
1631 | PSR_1_LINE_TO_WAIT, | |
1632 | PSR_4_LINES_TO_WAIT, | |
1633 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1634 | }; |
1635 | ||
41aa3448 RV |
1636 | struct intel_vbt_data { |
1637 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1638 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1639 | ||
1640 | /* Feature bits */ | |
1641 | unsigned int int_tv_support:1; | |
1642 | unsigned int lvds_dither:1; | |
1643 | unsigned int lvds_vbt:1; | |
1644 | unsigned int int_crt_support:1; | |
1645 | unsigned int lvds_use_ssc:1; | |
1646 | unsigned int display_clock_mode:1; | |
1647 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 1648 | unsigned int panel_type:4; |
41aa3448 RV |
1649 | int lvds_ssc_freq; |
1650 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1651 | ||
83a7280e PB |
1652 | enum drrs_support_type drrs_type; |
1653 | ||
6aa23e65 JN |
1654 | struct { |
1655 | int rate; | |
1656 | int lanes; | |
1657 | int preemphasis; | |
1658 | int vswing; | |
06411f08 | 1659 | bool low_vswing; |
6aa23e65 JN |
1660 | bool initialized; |
1661 | bool support; | |
1662 | int bpp; | |
1663 | struct edp_power_seq pps; | |
1664 | } edp; | |
41aa3448 | 1665 | |
bfd7ebda RV |
1666 | struct { |
1667 | bool full_link; | |
1668 | bool require_aux_wakeup; | |
1669 | int idle_frames; | |
1670 | enum psr_lines_to_wait lines_to_wait; | |
1671 | int tp1_wakeup_time; | |
1672 | int tp2_tp3_wakeup_time; | |
1673 | } psr; | |
1674 | ||
f00076d2 JN |
1675 | struct { |
1676 | u16 pwm_freq_hz; | |
39fbc9c8 | 1677 | bool present; |
f00076d2 | 1678 | bool active_low_pwm; |
1de6068e | 1679 | u8 min_brightness; /* min_brightness/255 of max */ |
add03379 | 1680 | u8 controller; /* brightness controller number */ |
9a41e17d | 1681 | enum intel_backlight_type type; |
f00076d2 JN |
1682 | } backlight; |
1683 | ||
d17c5443 SK |
1684 | /* MIPI DSI */ |
1685 | struct { | |
1686 | u16 panel_id; | |
d3b542fc SK |
1687 | struct mipi_config *config; |
1688 | struct mipi_pps_data *pps; | |
1689 | u8 seq_version; | |
1690 | u32 size; | |
1691 | u8 *data; | |
8d3ed2f3 | 1692 | const u8 *sequence[MIPI_SEQ_MAX]; |
d17c5443 SK |
1693 | } dsi; |
1694 | ||
41aa3448 RV |
1695 | int crt_ddc_pin; |
1696 | ||
1697 | int child_dev_num; | |
768f69c9 | 1698 | union child_device_config *child_dev; |
6acab15a PZ |
1699 | |
1700 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1701 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1702 | }; |
1703 | ||
77c122bc VS |
1704 | enum intel_ddb_partitioning { |
1705 | INTEL_DDB_PART_1_2, | |
1706 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1707 | }; | |
1708 | ||
1fd527cc VS |
1709 | struct intel_wm_level { |
1710 | bool enable; | |
1711 | uint32_t pri_val; | |
1712 | uint32_t spr_val; | |
1713 | uint32_t cur_val; | |
1714 | uint32_t fbc_val; | |
1715 | }; | |
1716 | ||
820c1980 | 1717 | struct ilk_wm_values { |
609cedef VS |
1718 | uint32_t wm_pipe[3]; |
1719 | uint32_t wm_lp[3]; | |
1720 | uint32_t wm_lp_spr[3]; | |
1721 | uint32_t wm_linetime[3]; | |
1722 | bool enable_fbc_wm; | |
1723 | enum intel_ddb_partitioning partitioning; | |
1724 | }; | |
1725 | ||
114d7dc0 | 1726 | struct g4x_pipe_wm { |
1b31389c | 1727 | uint16_t plane[I915_MAX_PLANES]; |
04548cba | 1728 | uint16_t fbc; |
262cd2e1 | 1729 | }; |
ae80152d | 1730 | |
114d7dc0 | 1731 | struct g4x_sr_wm { |
262cd2e1 | 1732 | uint16_t plane; |
1b31389c | 1733 | uint16_t cursor; |
04548cba | 1734 | uint16_t fbc; |
1b31389c VS |
1735 | }; |
1736 | ||
1737 | struct vlv_wm_ddl_values { | |
1738 | uint8_t plane[I915_MAX_PLANES]; | |
262cd2e1 | 1739 | }; |
ae80152d | 1740 | |
262cd2e1 | 1741 | struct vlv_wm_values { |
114d7dc0 VS |
1742 | struct g4x_pipe_wm pipe[3]; |
1743 | struct g4x_sr_wm sr; | |
1b31389c | 1744 | struct vlv_wm_ddl_values ddl[3]; |
6eb1a681 VS |
1745 | uint8_t level; |
1746 | bool cxsr; | |
0018fda1 VS |
1747 | }; |
1748 | ||
04548cba VS |
1749 | struct g4x_wm_values { |
1750 | struct g4x_pipe_wm pipe[2]; | |
1751 | struct g4x_sr_wm sr; | |
1752 | struct g4x_sr_wm hpll; | |
1753 | bool cxsr; | |
1754 | bool hpll_en; | |
1755 | bool fbc_en; | |
1756 | }; | |
1757 | ||
c193924e | 1758 | struct skl_ddb_entry { |
16160e3d | 1759 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1760 | }; |
1761 | ||
1762 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1763 | { | |
16160e3d | 1764 | return entry->end - entry->start; |
c193924e DL |
1765 | } |
1766 | ||
08db6652 DL |
1767 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1768 | const struct skl_ddb_entry *e2) | |
1769 | { | |
1770 | if (e1->start == e2->start && e1->end == e2->end) | |
1771 | return true; | |
1772 | ||
1773 | return false; | |
1774 | } | |
1775 | ||
c193924e | 1776 | struct skl_ddb_allocation { |
2cd601c6 | 1777 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1778 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1779 | }; |
1780 | ||
2ac96d2a | 1781 | struct skl_wm_values { |
2b4b9f35 | 1782 | unsigned dirty_pipes; |
c193924e | 1783 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1784 | }; |
1785 | ||
1786 | struct skl_wm_level { | |
a62163e9 L |
1787 | bool plane_en; |
1788 | uint16_t plane_res_b; | |
1789 | uint8_t plane_res_l; | |
2ac96d2a PB |
1790 | }; |
1791 | ||
c67a470b | 1792 | /* |
765dab67 PZ |
1793 | * This struct helps tracking the state needed for runtime PM, which puts the |
1794 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1795 | * graphics device works, even register access, so we don't get interrupts nor | |
1796 | * anything else. | |
c67a470b | 1797 | * |
765dab67 PZ |
1798 | * Every piece of our code that needs to actually touch the hardware needs to |
1799 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1800 | * appropriate power domain. | |
a8a8bd54 | 1801 | * |
765dab67 PZ |
1802 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1803 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1804 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1805 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1806 | * |
1807 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1808 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1809 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1810 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1811 | * case it happens. |
c67a470b | 1812 | * |
765dab67 | 1813 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1814 | */ |
5d584b2e | 1815 | struct i915_runtime_pm { |
1f814dac | 1816 | atomic_t wakeref_count; |
5d584b2e | 1817 | bool suspended; |
2aeb7d3a | 1818 | bool irqs_enabled; |
c67a470b PZ |
1819 | }; |
1820 | ||
926321d5 DV |
1821 | enum intel_pipe_crc_source { |
1822 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1823 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1824 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1825 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1826 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1827 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1828 | INTEL_PIPE_CRC_SOURCE_TV, | |
1829 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1830 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1831 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1832 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1833 | INTEL_PIPE_CRC_SOURCE_MAX, |
1834 | }; | |
1835 | ||
8bf1e9f1 | 1836 | struct intel_pipe_crc_entry { |
ac2300d4 | 1837 | uint32_t frame; |
8bf1e9f1 SH |
1838 | uint32_t crc[5]; |
1839 | }; | |
1840 | ||
b2c88f5b | 1841 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1842 | struct intel_pipe_crc { |
d538bbdf DL |
1843 | spinlock_t lock; |
1844 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1845 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1846 | enum intel_pipe_crc_source source; |
d538bbdf | 1847 | int head, tail; |
07144428 | 1848 | wait_queue_head_t wq; |
8c6b709d | 1849 | int skipped; |
8bf1e9f1 SH |
1850 | }; |
1851 | ||
f99d7069 | 1852 | struct i915_frontbuffer_tracking { |
b5add959 | 1853 | spinlock_t lock; |
f99d7069 DV |
1854 | |
1855 | /* | |
1856 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1857 | * scheduled flips. | |
1858 | */ | |
1859 | unsigned busy_bits; | |
1860 | unsigned flip_bits; | |
1861 | }; | |
1862 | ||
7225342a | 1863 | struct i915_wa_reg { |
f0f59a00 | 1864 | i915_reg_t addr; |
7225342a MK |
1865 | u32 value; |
1866 | /* bitmask representing WA bits */ | |
1867 | u32 mask; | |
1868 | }; | |
1869 | ||
33136b06 AS |
1870 | /* |
1871 | * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only | |
1872 | * allowing it for RCS as we don't foresee any requirement of having | |
1873 | * a whitelist for other engines. When it is really required for | |
1874 | * other engines then the limit need to be increased. | |
1875 | */ | |
1876 | #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS) | |
7225342a MK |
1877 | |
1878 | struct i915_workarounds { | |
1879 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1880 | u32 count; | |
666796da | 1881 | u32 hw_whitelist_count[I915_NUM_ENGINES]; |
7225342a MK |
1882 | }; |
1883 | ||
cf9d2890 YZ |
1884 | struct i915_virtual_gpu { |
1885 | bool active; | |
1886 | }; | |
1887 | ||
aa363136 MR |
1888 | /* used in computing the new watermarks state */ |
1889 | struct intel_wm_config { | |
1890 | unsigned int num_pipes_active; | |
1891 | bool sprites_enabled; | |
1892 | bool sprites_scaled; | |
1893 | }; | |
1894 | ||
d7965152 RB |
1895 | struct i915_oa_format { |
1896 | u32 format; | |
1897 | int size; | |
1898 | }; | |
1899 | ||
8a3003dd RB |
1900 | struct i915_oa_reg { |
1901 | i915_reg_t addr; | |
1902 | u32 value; | |
1903 | }; | |
1904 | ||
eec688e1 RB |
1905 | struct i915_perf_stream; |
1906 | ||
16d98b31 RB |
1907 | /** |
1908 | * struct i915_perf_stream_ops - the OPs to support a specific stream type | |
1909 | */ | |
eec688e1 | 1910 | struct i915_perf_stream_ops { |
16d98b31 RB |
1911 | /** |
1912 | * @enable: Enables the collection of HW samples, either in response to | |
1913 | * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened | |
1914 | * without `I915_PERF_FLAG_DISABLED`. | |
eec688e1 RB |
1915 | */ |
1916 | void (*enable)(struct i915_perf_stream *stream); | |
1917 | ||
16d98b31 RB |
1918 | /** |
1919 | * @disable: Disables the collection of HW samples, either in response | |
1920 | * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying | |
1921 | * the stream. | |
eec688e1 RB |
1922 | */ |
1923 | void (*disable)(struct i915_perf_stream *stream); | |
1924 | ||
16d98b31 RB |
1925 | /** |
1926 | * @poll_wait: Call poll_wait, passing a wait queue that will be woken | |
eec688e1 RB |
1927 | * once there is something ready to read() for the stream |
1928 | */ | |
1929 | void (*poll_wait)(struct i915_perf_stream *stream, | |
1930 | struct file *file, | |
1931 | poll_table *wait); | |
1932 | ||
16d98b31 RB |
1933 | /** |
1934 | * @wait_unlocked: For handling a blocking read, wait until there is | |
1935 | * something to ready to read() for the stream. E.g. wait on the same | |
d7965152 | 1936 | * wait queue that would be passed to poll_wait(). |
eec688e1 RB |
1937 | */ |
1938 | int (*wait_unlocked)(struct i915_perf_stream *stream); | |
1939 | ||
16d98b31 RB |
1940 | /** |
1941 | * @read: Copy buffered metrics as records to userspace | |
1942 | * **buf**: the userspace, destination buffer | |
1943 | * **count**: the number of bytes to copy, requested by userspace | |
1944 | * **offset**: zero at the start of the read, updated as the read | |
1945 | * proceeds, it represents how many bytes have been copied so far and | |
1946 | * the buffer offset for copying the next record. | |
eec688e1 | 1947 | * |
16d98b31 RB |
1948 | * Copy as many buffered i915 perf samples and records for this stream |
1949 | * to userspace as will fit in the given buffer. | |
eec688e1 | 1950 | * |
16d98b31 RB |
1951 | * Only write complete records; returning -%ENOSPC if there isn't room |
1952 | * for a complete record. | |
eec688e1 | 1953 | * |
16d98b31 RB |
1954 | * Return any error condition that results in a short read such as |
1955 | * -%ENOSPC or -%EFAULT, even though these may be squashed before | |
1956 | * returning to userspace. | |
eec688e1 RB |
1957 | */ |
1958 | int (*read)(struct i915_perf_stream *stream, | |
1959 | char __user *buf, | |
1960 | size_t count, | |
1961 | size_t *offset); | |
1962 | ||
16d98b31 RB |
1963 | /** |
1964 | * @destroy: Cleanup any stream specific resources. | |
eec688e1 RB |
1965 | * |
1966 | * The stream will always be disabled before this is called. | |
1967 | */ | |
1968 | void (*destroy)(struct i915_perf_stream *stream); | |
1969 | }; | |
1970 | ||
16d98b31 RB |
1971 | /** |
1972 | * struct i915_perf_stream - state for a single open stream FD | |
1973 | */ | |
eec688e1 | 1974 | struct i915_perf_stream { |
16d98b31 RB |
1975 | /** |
1976 | * @dev_priv: i915 drm device | |
1977 | */ | |
eec688e1 RB |
1978 | struct drm_i915_private *dev_priv; |
1979 | ||
16d98b31 RB |
1980 | /** |
1981 | * @link: Links the stream into ``&drm_i915_private->streams`` | |
1982 | */ | |
eec688e1 RB |
1983 | struct list_head link; |
1984 | ||
16d98b31 RB |
1985 | /** |
1986 | * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` | |
1987 | * properties given when opening a stream, representing the contents | |
1988 | * of a single sample as read() by userspace. | |
1989 | */ | |
eec688e1 | 1990 | u32 sample_flags; |
16d98b31 RB |
1991 | |
1992 | /** | |
1993 | * @sample_size: Considering the configured contents of a sample | |
1994 | * combined with the required header size, this is the total size | |
1995 | * of a single sample record. | |
1996 | */ | |
d7965152 | 1997 | int sample_size; |
eec688e1 | 1998 | |
16d98b31 RB |
1999 | /** |
2000 | * @ctx: %NULL if measuring system-wide across all contexts or a | |
2001 | * specific context that is being monitored. | |
2002 | */ | |
eec688e1 | 2003 | struct i915_gem_context *ctx; |
16d98b31 RB |
2004 | |
2005 | /** | |
2006 | * @enabled: Whether the stream is currently enabled, considering | |
2007 | * whether the stream was opened in a disabled state and based | |
2008 | * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. | |
2009 | */ | |
eec688e1 RB |
2010 | bool enabled; |
2011 | ||
16d98b31 RB |
2012 | /** |
2013 | * @ops: The callbacks providing the implementation of this specific | |
2014 | * type of configured stream. | |
2015 | */ | |
d7965152 RB |
2016 | const struct i915_perf_stream_ops *ops; |
2017 | }; | |
2018 | ||
16d98b31 RB |
2019 | /** |
2020 | * struct i915_oa_ops - Gen specific implementation of an OA unit stream | |
2021 | */ | |
d7965152 | 2022 | struct i915_oa_ops { |
16d98b31 RB |
2023 | /** |
2024 | * @init_oa_buffer: Resets the head and tail pointers of the | |
2025 | * circular buffer for periodic OA reports. | |
2026 | * | |
2027 | * Called when first opening a stream for OA metrics, but also may be | |
2028 | * called in response to an OA buffer overflow or other error | |
2029 | * condition. | |
2030 | * | |
2031 | * Note it may be necessary to clear the full OA buffer here as part of | |
2032 | * maintaining the invariable that new reports must be written to | |
2033 | * zeroed memory for us to be able to reliable detect if an expected | |
2034 | * report has not yet landed in memory. (At least on Haswell the OA | |
2035 | * buffer tail pointer is not synchronized with reports being visible | |
2036 | * to the CPU) | |
2037 | */ | |
d7965152 | 2038 | void (*init_oa_buffer)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
2039 | |
2040 | /** | |
19f81df2 RB |
2041 | * @select_metric_set: The auto generated code that checks whether a |
2042 | * requested OA config is applicable to the system and if so sets up | |
2043 | * the mux, oa and flex eu register config pointers according to the | |
2044 | * current dev_priv->perf.oa.metrics_set. | |
2045 | */ | |
2046 | int (*select_metric_set)(struct drm_i915_private *dev_priv); | |
2047 | ||
2048 | /** | |
2049 | * @enable_metric_set: Selects and applies any MUX configuration to set | |
2050 | * up the Boolean and Custom (B/C) counters that are part of the | |
2051 | * counter reports being sampled. May apply system constraints such as | |
16d98b31 RB |
2052 | * disabling EU clock gating as required. |
2053 | */ | |
d7965152 | 2054 | int (*enable_metric_set)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
2055 | |
2056 | /** | |
2057 | * @disable_metric_set: Remove system constraints associated with using | |
2058 | * the OA unit. | |
2059 | */ | |
d7965152 | 2060 | void (*disable_metric_set)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
2061 | |
2062 | /** | |
2063 | * @oa_enable: Enable periodic sampling | |
2064 | */ | |
d7965152 | 2065 | void (*oa_enable)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
2066 | |
2067 | /** | |
2068 | * @oa_disable: Disable periodic sampling | |
2069 | */ | |
d7965152 | 2070 | void (*oa_disable)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
2071 | |
2072 | /** | |
2073 | * @read: Copy data from the circular OA buffer into a given userspace | |
2074 | * buffer. | |
2075 | */ | |
d7965152 RB |
2076 | int (*read)(struct i915_perf_stream *stream, |
2077 | char __user *buf, | |
2078 | size_t count, | |
2079 | size_t *offset); | |
16d98b31 RB |
2080 | |
2081 | /** | |
19f81df2 | 2082 | * @oa_hw_tail_read: read the OA tail pointer register |
16d98b31 | 2083 | * |
19f81df2 RB |
2084 | * In particular this enables us to share all the fiddly code for |
2085 | * handling the OA unit tail pointer race that affects multiple | |
2086 | * generations. | |
16d98b31 | 2087 | */ |
19f81df2 | 2088 | u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv); |
eec688e1 RB |
2089 | }; |
2090 | ||
49cd97a3 VS |
2091 | struct intel_cdclk_state { |
2092 | unsigned int cdclk, vco, ref; | |
2093 | }; | |
2094 | ||
77fec556 | 2095 | struct drm_i915_private { |
8f460e2c CW |
2096 | struct drm_device drm; |
2097 | ||
efab6d8d | 2098 | struct kmem_cache *objects; |
e20d2ab7 | 2099 | struct kmem_cache *vmas; |
efab6d8d | 2100 | struct kmem_cache *requests; |
52e54209 | 2101 | struct kmem_cache *dependencies; |
c5cf9a91 | 2102 | struct kmem_cache *priorities; |
f4c956ad | 2103 | |
5c969aa7 | 2104 | const struct intel_device_info info; |
f4c956ad | 2105 | |
f4c956ad DV |
2106 | void __iomem *regs; |
2107 | ||
907b28c5 | 2108 | struct intel_uncore uncore; |
f4c956ad | 2109 | |
cf9d2890 YZ |
2110 | struct i915_virtual_gpu vgpu; |
2111 | ||
feddf6e8 | 2112 | struct intel_gvt *gvt; |
0ad35fed | 2113 | |
bd132858 | 2114 | struct intel_huc huc; |
33a732f4 AD |
2115 | struct intel_guc guc; |
2116 | ||
eb805623 DV |
2117 | struct intel_csr csr; |
2118 | ||
5ea6e5e3 | 2119 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 2120 | |
f4c956ad DV |
2121 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
2122 | * controller on different i2c buses. */ | |
2123 | struct mutex gmbus_mutex; | |
2124 | ||
2125 | /** | |
2126 | * Base address of the gmbus and gpio block. | |
2127 | */ | |
2128 | uint32_t gpio_mmio_base; | |
2129 | ||
b6fdd0f2 SS |
2130 | /* MMIO base address for MIPI regs */ |
2131 | uint32_t mipi_mmio_base; | |
2132 | ||
443a389f VS |
2133 | uint32_t psr_mmio_base; |
2134 | ||
44cb734c ID |
2135 | uint32_t pps_mmio_base; |
2136 | ||
28c70f16 DV |
2137 | wait_queue_head_t gmbus_wait_queue; |
2138 | ||
f4c956ad | 2139 | struct pci_dev *bridge_dev; |
0ca5fa3a | 2140 | struct i915_gem_context *kernel_context; |
3b3f1650 | 2141 | struct intel_engine_cs *engine[I915_NUM_ENGINES]; |
51d545d0 | 2142 | struct i915_vma *semaphore; |
f4c956ad | 2143 | |
ba8286fa | 2144 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
2145 | struct resource mch_res; |
2146 | ||
f4c956ad DV |
2147 | /* protects the irq masks */ |
2148 | spinlock_t irq_lock; | |
2149 | ||
f8b79e58 ID |
2150 | bool display_irqs_enabled; |
2151 | ||
9ee32fea DV |
2152 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
2153 | struct pm_qos_request pm_qos; | |
2154 | ||
a580516d VS |
2155 | /* Sideband mailbox protection */ |
2156 | struct mutex sb_lock; | |
f4c956ad DV |
2157 | |
2158 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
2159 | union { |
2160 | u32 irq_mask; | |
2161 | u32 de_irq_mask[I915_MAX_PIPES]; | |
2162 | }; | |
f4c956ad | 2163 | u32 gt_irq_mask; |
f4e9af4f AG |
2164 | u32 pm_imr; |
2165 | u32 pm_ier; | |
a6706b45 | 2166 | u32 pm_rps_events; |
26705e20 | 2167 | u32 pm_guc_events; |
91d181dd | 2168 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 2169 | |
5fcece80 | 2170 | struct i915_hotplug hotplug; |
ab34a7e8 | 2171 | struct intel_fbc fbc; |
439d7ac0 | 2172 | struct i915_drrs drrs; |
f4c956ad | 2173 | struct intel_opregion opregion; |
41aa3448 | 2174 | struct intel_vbt_data vbt; |
f4c956ad | 2175 | |
d9ceb816 JB |
2176 | bool preserve_bios_swizzle; |
2177 | ||
f4c956ad DV |
2178 | /* overlay */ |
2179 | struct intel_overlay *overlay; | |
f4c956ad | 2180 | |
58c68779 | 2181 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 2182 | struct mutex backlight_lock; |
31ad8ec6 | 2183 | |
f4c956ad | 2184 | /* LVDS info */ |
f4c956ad DV |
2185 | bool no_aux_handshake; |
2186 | ||
e39b999a VS |
2187 | /* protects panel power sequencer state */ |
2188 | struct mutex pps_mutex; | |
2189 | ||
f4c956ad | 2190 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
2191 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
2192 | ||
2193 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
b2045352 | 2194 | unsigned int skl_preferred_vco_freq; |
49cd97a3 | 2195 | unsigned int max_cdclk_freq; |
8d96561a | 2196 | |
adafdc6f | 2197 | unsigned int max_dotclk_freq; |
e7dc33f3 | 2198 | unsigned int rawclk_freq; |
6bcda4f0 | 2199 | unsigned int hpll_freq; |
bfa7df01 | 2200 | unsigned int czclk_freq; |
f4c956ad | 2201 | |
63911d72 | 2202 | struct { |
bb0f4aab VS |
2203 | /* |
2204 | * The current logical cdclk state. | |
2205 | * See intel_atomic_state.cdclk.logical | |
2206 | * | |
2207 | * For reading holding any crtc lock is sufficient, | |
2208 | * for writing must hold all of them. | |
2209 | */ | |
2210 | struct intel_cdclk_state logical; | |
2211 | /* | |
2212 | * The current actual cdclk state. | |
2213 | * See intel_atomic_state.cdclk.actual | |
2214 | */ | |
2215 | struct intel_cdclk_state actual; | |
2216 | /* The current hardware cdclk state */ | |
49cd97a3 VS |
2217 | struct intel_cdclk_state hw; |
2218 | } cdclk; | |
63911d72 | 2219 | |
645416f5 DV |
2220 | /** |
2221 | * wq - Driver workqueue for GEM. | |
2222 | * | |
2223 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
2224 | * locks, for otherwise the flushing done in the pageflip code will | |
2225 | * result in deadlocks. | |
2226 | */ | |
f4c956ad DV |
2227 | struct workqueue_struct *wq; |
2228 | ||
2229 | /* Display functions */ | |
2230 | struct drm_i915_display_funcs display; | |
2231 | ||
2232 | /* PCH chipset type */ | |
2233 | enum intel_pch pch_type; | |
17a303ec | 2234 | unsigned short pch_id; |
f4c956ad DV |
2235 | |
2236 | unsigned long quirks; | |
2237 | ||
b8efb17b ZR |
2238 | enum modeset_restore modeset_restore; |
2239 | struct mutex modeset_restore_lock; | |
e2c8b870 | 2240 | struct drm_atomic_state *modeset_restore_state; |
73974893 | 2241 | struct drm_modeset_acquire_ctx reset_ctx; |
673a394b | 2242 | |
a7bbbd63 | 2243 | struct list_head vm_list; /* Global list of all address spaces */ |
62106b4f | 2244 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 2245 | |
4b5aed62 | 2246 | struct i915_gem_mm mm; |
ad46cb53 CW |
2247 | DECLARE_HASHTABLE(mm_structs, 7); |
2248 | struct mutex mm_lock; | |
8781342d | 2249 | |
8781342d DV |
2250 | /* Kernel Modesetting */ |
2251 | ||
e2af48c6 VS |
2252 | struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
2253 | struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 | 2254 | |
c4597872 DV |
2255 | #ifdef CONFIG_DEBUG_FS |
2256 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
2257 | #endif | |
2258 | ||
565602d7 | 2259 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
2260 | int num_shared_dpll; |
2261 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 2262 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 2263 | |
fbf6d879 ML |
2264 | /* |
2265 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
2266 | * Must be global rather than per dpll, because on some platforms | |
2267 | * plls share registers. | |
2268 | */ | |
2269 | struct mutex dpll_lock; | |
2270 | ||
565602d7 ML |
2271 | unsigned int active_crtcs; |
2272 | unsigned int min_pixclk[I915_MAX_PIPES]; | |
2273 | ||
e4607fcf | 2274 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 2275 | |
7225342a | 2276 | struct i915_workarounds workarounds; |
888b5995 | 2277 | |
f99d7069 DV |
2278 | struct i915_frontbuffer_tracking fb_tracking; |
2279 | ||
eb955eee CW |
2280 | struct intel_atomic_helper { |
2281 | struct llist_head free_list; | |
2282 | struct work_struct free_work; | |
2283 | } atomic_helper; | |
2284 | ||
652c393a | 2285 | u16 orig_clock; |
f97108d1 | 2286 | |
c4804411 | 2287 | bool mchbar_need_disable; |
f97108d1 | 2288 | |
a4da4fa4 DV |
2289 | struct intel_l3_parity l3_parity; |
2290 | ||
59124506 | 2291 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 2292 | u32 edram_cap; |
59124506 | 2293 | |
c6a828d3 | 2294 | /* gen6+ rps state */ |
c85aa885 | 2295 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 2296 | |
20e4d407 DV |
2297 | /* ilk-only ips/rps state. Everything in here is protected by the global |
2298 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 2299 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 2300 | |
83c00f55 | 2301 | struct i915_power_domains power_domains; |
a38911a3 | 2302 | |
a031d709 | 2303 | struct i915_psr psr; |
3f51e471 | 2304 | |
99584db3 | 2305 | struct i915_gpu_error gpu_error; |
ae681d96 | 2306 | |
c9cddffc JB |
2307 | struct drm_i915_gem_object *vlv_pctx; |
2308 | ||
8be48d92 DA |
2309 | /* list of fbdev register on this device */ |
2310 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 2311 | struct work_struct fbdev_suspend_work; |
e953fd7b CW |
2312 | |
2313 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 2314 | struct drm_property *force_audio_property; |
e3689190 | 2315 | |
58fddc28 | 2316 | /* hda/i915 audio component */ |
51e1d83c | 2317 | struct i915_audio_component *audio_component; |
58fddc28 | 2318 | bool audio_component_registered; |
4a21ef7d LY |
2319 | /** |
2320 | * av_mutex - mutex for audio/video sync | |
2321 | * | |
2322 | */ | |
2323 | struct mutex av_mutex; | |
58fddc28 | 2324 | |
829a0af2 CW |
2325 | struct { |
2326 | struct list_head list; | |
5f09a9c8 CW |
2327 | struct llist_head free_list; |
2328 | struct work_struct free_work; | |
829a0af2 CW |
2329 | |
2330 | /* The hw wants to have a stable context identifier for the | |
2331 | * lifetime of the context (for OA, PASID, faults, etc). | |
2332 | * This is limited in execlists to 21 bits. | |
2333 | */ | |
2334 | struct ida hw_ida; | |
2335 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
2336 | } contexts; | |
f4c956ad | 2337 | |
3e68320e | 2338 | u32 fdi_rx_config; |
68d18ad7 | 2339 | |
c231775c | 2340 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 2341 | u32 chv_phy_control; |
c231775c VS |
2342 | /* |
2343 | * Shadows for CHV DPLL_MD regs to keep the state | |
2344 | * checker somewhat working in the presence hardware | |
2345 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
2346 | */ | |
2347 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 2348 | u32 bxt_phy_grc; |
70722468 | 2349 | |
842f1c8b | 2350 | u32 suspend_count; |
bc87229f | 2351 | bool suspended_to_idle; |
f4c956ad | 2352 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 2353 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 2354 | |
656d1b89 | 2355 | enum { |
16dcdc4e PZ |
2356 | I915_SAGV_UNKNOWN = 0, |
2357 | I915_SAGV_DISABLED, | |
2358 | I915_SAGV_ENABLED, | |
2359 | I915_SAGV_NOT_CONTROLLED | |
2360 | } sagv_status; | |
656d1b89 | 2361 | |
53615a5e VS |
2362 | struct { |
2363 | /* | |
2364 | * Raw watermark latency values: | |
2365 | * in 0.1us units for WM0, | |
2366 | * in 0.5us units for WM1+. | |
2367 | */ | |
2368 | /* primary */ | |
2369 | uint16_t pri_latency[5]; | |
2370 | /* sprite */ | |
2371 | uint16_t spr_latency[5]; | |
2372 | /* cursor */ | |
2373 | uint16_t cur_latency[5]; | |
2af30a5c PB |
2374 | /* |
2375 | * Raw watermark memory latency values | |
2376 | * for SKL for all 8 levels | |
2377 | * in 1us units. | |
2378 | */ | |
2379 | uint16_t skl_latency[8]; | |
609cedef VS |
2380 | |
2381 | /* current hardware state */ | |
2d41c0b5 PB |
2382 | union { |
2383 | struct ilk_wm_values hw; | |
2384 | struct skl_wm_values skl_hw; | |
0018fda1 | 2385 | struct vlv_wm_values vlv; |
04548cba | 2386 | struct g4x_wm_values g4x; |
2d41c0b5 | 2387 | }; |
58590c14 VS |
2388 | |
2389 | uint8_t max_level; | |
ed4a6a7c MR |
2390 | |
2391 | /* | |
2392 | * Should be held around atomic WM register writing; also | |
2393 | * protects * intel_crtc->wm.active and | |
2394 | * cstate->wm.need_postvbl_update. | |
2395 | */ | |
2396 | struct mutex wm_mutex; | |
279e99d7 MR |
2397 | |
2398 | /* | |
2399 | * Set during HW readout of watermarks/DDB. Some platforms | |
2400 | * need to know when we're still using BIOS-provided values | |
2401 | * (which we don't fully trust). | |
2402 | */ | |
2403 | bool distrust_bios_wm; | |
53615a5e VS |
2404 | } wm; |
2405 | ||
8a187455 PZ |
2406 | struct i915_runtime_pm pm; |
2407 | ||
eec688e1 RB |
2408 | struct { |
2409 | bool initialized; | |
d7965152 | 2410 | |
442b8c06 | 2411 | struct kobject *metrics_kobj; |
ccdf6341 | 2412 | struct ctl_table_header *sysctl_header; |
442b8c06 | 2413 | |
eec688e1 RB |
2414 | struct mutex lock; |
2415 | struct list_head streams; | |
8a3003dd RB |
2416 | |
2417 | struct { | |
d7965152 RB |
2418 | struct i915_perf_stream *exclusive_stream; |
2419 | ||
2420 | u32 specific_ctx_id; | |
d7965152 RB |
2421 | |
2422 | struct hrtimer poll_check_timer; | |
2423 | wait_queue_head_t poll_wq; | |
2424 | bool pollin; | |
2425 | ||
712122ea RB |
2426 | /** |
2427 | * For rate limiting any notifications of spurious | |
2428 | * invalid OA reports | |
2429 | */ | |
2430 | struct ratelimit_state spurious_report_rs; | |
2431 | ||
d7965152 RB |
2432 | bool periodic; |
2433 | int period_exponent; | |
155e941f | 2434 | int timestamp_frequency; |
d7965152 RB |
2435 | |
2436 | int metrics_set; | |
8a3003dd | 2437 | |
fc599211 RB |
2438 | const struct i915_oa_reg *mux_regs[6]; |
2439 | int mux_regs_lens[6]; | |
3f488d99 LL |
2440 | int n_mux_configs; |
2441 | ||
8a3003dd RB |
2442 | const struct i915_oa_reg *b_counter_regs; |
2443 | int b_counter_regs_len; | |
5182f646 RB |
2444 | const struct i915_oa_reg *flex_regs; |
2445 | int flex_regs_len; | |
d7965152 RB |
2446 | |
2447 | struct { | |
2448 | struct i915_vma *vma; | |
2449 | u8 *vaddr; | |
19f81df2 | 2450 | u32 last_ctx_id; |
d7965152 RB |
2451 | int format; |
2452 | int format_size; | |
f279020a | 2453 | |
0dd860cf RB |
2454 | /** |
2455 | * Locks reads and writes to all head/tail state | |
2456 | * | |
2457 | * Consider: the head and tail pointer state | |
2458 | * needs to be read consistently from a hrtimer | |
2459 | * callback (atomic context) and read() fop | |
2460 | * (user context) with tail pointer updates | |
2461 | * happening in atomic context and head updates | |
2462 | * in user context and the (unlikely) | |
2463 | * possibility of read() errors needing to | |
2464 | * reset all head/tail state. | |
2465 | * | |
2466 | * Note: Contention or performance aren't | |
2467 | * currently a significant concern here | |
2468 | * considering the relatively low frequency of | |
2469 | * hrtimer callbacks (5ms period) and that | |
2470 | * reads typically only happen in response to a | |
2471 | * hrtimer event and likely complete before the | |
2472 | * next callback. | |
2473 | * | |
2474 | * Note: This lock is not held *while* reading | |
2475 | * and copying data to userspace so the value | |
2476 | * of head observed in htrimer callbacks won't | |
2477 | * represent any partial consumption of data. | |
2478 | */ | |
2479 | spinlock_t ptr_lock; | |
2480 | ||
2481 | /** | |
2482 | * One 'aging' tail pointer and one 'aged' | |
2483 | * tail pointer ready to used for reading. | |
2484 | * | |
2485 | * Initial values of 0xffffffff are invalid | |
2486 | * and imply that an update is required | |
2487 | * (and should be ignored by an attempted | |
2488 | * read) | |
2489 | */ | |
2490 | struct { | |
2491 | u32 offset; | |
2492 | } tails[2]; | |
2493 | ||
2494 | /** | |
2495 | * Index for the aged tail ready to read() | |
2496 | * data up to. | |
2497 | */ | |
2498 | unsigned int aged_tail_idx; | |
2499 | ||
2500 | /** | |
2501 | * A monotonic timestamp for when the current | |
2502 | * aging tail pointer was read; used to | |
2503 | * determine when it is old enough to trust. | |
2504 | */ | |
2505 | u64 aging_timestamp; | |
2506 | ||
f279020a RB |
2507 | /** |
2508 | * Although we can always read back the head | |
2509 | * pointer register, we prefer to avoid | |
2510 | * trusting the HW state, just to avoid any | |
2511 | * risk that some hardware condition could | |
2512 | * somehow bump the head pointer unpredictably | |
2513 | * and cause us to forward the wrong OA buffer | |
2514 | * data to userspace. | |
2515 | */ | |
2516 | u32 head; | |
d7965152 RB |
2517 | } oa_buffer; |
2518 | ||
2519 | u32 gen7_latched_oastatus1; | |
19f81df2 RB |
2520 | u32 ctx_oactxctrl_offset; |
2521 | u32 ctx_flexeu0_offset; | |
2522 | ||
2523 | /** | |
2524 | * The RPT_ID/reason field for Gen8+ includes a bit | |
2525 | * to determine if the CTX ID in the report is valid | |
2526 | * but the specific bit differs between Gen 8 and 9 | |
2527 | */ | |
2528 | u32 gen8_valid_ctx_bit; | |
d7965152 RB |
2529 | |
2530 | struct i915_oa_ops ops; | |
2531 | const struct i915_oa_format *oa_formats; | |
2532 | int n_builtin_sets; | |
8a3003dd | 2533 | } oa; |
eec688e1 RB |
2534 | } perf; |
2535 | ||
a83014d3 OM |
2536 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
2537 | struct { | |
821ed7df | 2538 | void (*resume)(struct drm_i915_private *); |
117897f4 | 2539 | void (*cleanup_engine)(struct intel_engine_cs *engine); |
67d97da3 | 2540 | |
73cb9701 CW |
2541 | struct list_head timelines; |
2542 | struct i915_gem_timeline global_timeline; | |
28176ef4 | 2543 | u32 active_requests; |
73cb9701 | 2544 | |
67d97da3 CW |
2545 | /** |
2546 | * Is the GPU currently considered idle, or busy executing | |
2547 | * userspace requests? Whilst idle, we allow runtime power | |
2548 | * management to power down the hardware and display clocks. | |
2549 | * In order to reduce the effect on performance, there | |
2550 | * is a slight delay before we do so. | |
2551 | */ | |
67d97da3 CW |
2552 | bool awake; |
2553 | ||
2554 | /** | |
2555 | * We leave the user IRQ off as much as possible, | |
2556 | * but this means that requests will finish and never | |
2557 | * be retired once the system goes idle. Set a timer to | |
2558 | * fire periodically while the ring is running. When it | |
2559 | * fires, go retire requests. | |
2560 | */ | |
2561 | struct delayed_work retire_work; | |
2562 | ||
2563 | /** | |
2564 | * When we detect an idle GPU, we want to turn on | |
2565 | * powersaving features. So once we see that there | |
2566 | * are no more requests outstanding and no more | |
2567 | * arrive within a small period of time, we fire | |
2568 | * off the idle_work. | |
2569 | */ | |
2570 | struct delayed_work idle_work; | |
de867c20 CW |
2571 | |
2572 | ktime_t last_init_time; | |
a83014d3 OM |
2573 | } gt; |
2574 | ||
3be60de9 VS |
2575 | /* perform PHY state sanity checks? */ |
2576 | bool chv_phy_assert[2]; | |
2577 | ||
a3a8986c MK |
2578 | bool ipc_enabled; |
2579 | ||
f9318941 PD |
2580 | /* Used to save the pipe-to-encoder mapping for audio */ |
2581 | struct intel_encoder *av_enc_map[I915_MAX_PIPES]; | |
0bdf5a05 | 2582 | |
eef57324 JA |
2583 | /* necessary resource sharing with HDMI LPE audio driver. */ |
2584 | struct { | |
2585 | struct platform_device *platdev; | |
2586 | int irq; | |
2587 | } lpe_audio; | |
2588 | ||
bdf1e7e3 DV |
2589 | /* |
2590 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2591 | * will be rejected. Instead look for a better place. | |
2592 | */ | |
77fec556 | 2593 | }; |
1da177e4 | 2594 | |
2c1792a1 CW |
2595 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2596 | { | |
091387c1 | 2597 | return container_of(dev, struct drm_i915_private, drm); |
2c1792a1 CW |
2598 | } |
2599 | ||
c49d13ee | 2600 | static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) |
888d0d42 | 2601 | { |
c49d13ee | 2602 | return to_i915(dev_get_drvdata(kdev)); |
888d0d42 ID |
2603 | } |
2604 | ||
33a732f4 AD |
2605 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2606 | { | |
2607 | return container_of(guc, struct drm_i915_private, guc); | |
2608 | } | |
2609 | ||
50beba55 AH |
2610 | static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) |
2611 | { | |
2612 | return container_of(huc, struct drm_i915_private, huc); | |
2613 | } | |
2614 | ||
b4ac5afc | 2615 | /* Simple iterator over all initialised engines */ |
3b3f1650 AG |
2616 | #define for_each_engine(engine__, dev_priv__, id__) \ |
2617 | for ((id__) = 0; \ | |
2618 | (id__) < I915_NUM_ENGINES; \ | |
2619 | (id__)++) \ | |
2620 | for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) | |
c3232b18 DG |
2621 | |
2622 | /* Iterator over subset of engines selected by mask */ | |
bafb0fce CW |
2623 | #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ |
2624 | for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask; \ | |
3b3f1650 | 2625 | tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; ) |
ee4b6faf | 2626 | |
b1d7e4b4 WF |
2627 | enum hdmi_force_audio { |
2628 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2629 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2630 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2631 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2632 | }; | |
2633 | ||
190d6cd5 | 2634 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2635 | |
a071fa00 DV |
2636 | /* |
2637 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2638 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2639 | * doesn't mean that the hw necessarily already scans it out, but that any |
2640 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2641 | * | |
2642 | * We have one bit per pipe and per scanout plane type. | |
2643 | */ | |
d1b9d039 SAK |
2644 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2645 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2646 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ |
2647 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2648 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2649 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2650 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2651 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2652 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2653 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2654 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2655 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2656 | |
85d1225e DG |
2657 | /* |
2658 | * Optimised SGL iterator for GEM objects | |
2659 | */ | |
2660 | static __always_inline struct sgt_iter { | |
2661 | struct scatterlist *sgp; | |
2662 | union { | |
2663 | unsigned long pfn; | |
2664 | dma_addr_t dma; | |
2665 | }; | |
2666 | unsigned int curr; | |
2667 | unsigned int max; | |
2668 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2669 | struct sgt_iter s = { .sgp = sgl }; | |
2670 | ||
2671 | if (s.sgp) { | |
2672 | s.max = s.curr = s.sgp->offset; | |
2673 | s.max += s.sgp->length; | |
2674 | if (dma) | |
2675 | s.dma = sg_dma_address(s.sgp); | |
2676 | else | |
2677 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2678 | } | |
2679 | ||
2680 | return s; | |
2681 | } | |
2682 | ||
96d77634 CW |
2683 | static inline struct scatterlist *____sg_next(struct scatterlist *sg) |
2684 | { | |
2685 | ++sg; | |
2686 | if (unlikely(sg_is_chain(sg))) | |
2687 | sg = sg_chain_ptr(sg); | |
2688 | return sg; | |
2689 | } | |
2690 | ||
63d15326 DG |
2691 | /** |
2692 | * __sg_next - return the next scatterlist entry in a list | |
2693 | * @sg: The current sg entry | |
2694 | * | |
2695 | * Description: | |
2696 | * If the entry is the last, return NULL; otherwise, step to the next | |
2697 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2698 | * otherwise just return the pointer to the current element. | |
2699 | **/ | |
2700 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2701 | { | |
2702 | #ifdef CONFIG_DEBUG_SG | |
2703 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2704 | #endif | |
96d77634 | 2705 | return sg_is_last(sg) ? NULL : ____sg_next(sg); |
63d15326 DG |
2706 | } |
2707 | ||
85d1225e DG |
2708 | /** |
2709 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2710 | * @__dmap: DMA address (output) | |
2711 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2712 | * @__sgt: sg_table to iterate over (input) | |
2713 | */ | |
2714 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2715 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2716 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
2717 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2718 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0)) |
85d1225e DG |
2719 | |
2720 | /** | |
2721 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2722 | * @__pp: page pointer (output) | |
2723 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2724 | * @__sgt: sg_table to iterate over (input) | |
2725 | */ | |
2726 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2727 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2728 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2729 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
2730 | (((__iter).curr += PAGE_SIZE) < (__iter).max) || \ | |
63d15326 | 2731 | ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0)) |
a071fa00 | 2732 | |
5ca43ef0 TU |
2733 | static inline const struct intel_device_info * |
2734 | intel_info(const struct drm_i915_private *dev_priv) | |
2735 | { | |
2736 | return &dev_priv->info; | |
2737 | } | |
2738 | ||
2739 | #define INTEL_INFO(dev_priv) intel_info((dev_priv)) | |
50a0bc90 | 2740 | |
55b8f2a7 | 2741 | #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) |
50a0bc90 | 2742 | #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) |
cae5852d | 2743 | |
e87a005d | 2744 | #define REVID_FOREVER 0xff |
4805fe82 | 2745 | #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) |
ac657f64 TU |
2746 | |
2747 | #define GEN_FOREVER (0) | |
2748 | /* | |
2749 | * Returns true if Gen is in inclusive range [Start, End]. | |
2750 | * | |
2751 | * Use GEN_FOREVER for unbound start and or end. | |
2752 | */ | |
c1812bdb | 2753 | #define IS_GEN(dev_priv, s, e) ({ \ |
ac657f64 TU |
2754 | unsigned int __s = (s), __e = (e); \ |
2755 | BUILD_BUG_ON(!__builtin_constant_p(s)); \ | |
2756 | BUILD_BUG_ON(!__builtin_constant_p(e)); \ | |
2757 | if ((__s) != GEN_FOREVER) \ | |
2758 | __s = (s) - 1; \ | |
2759 | if ((__e) == GEN_FOREVER) \ | |
2760 | __e = BITS_PER_LONG - 1; \ | |
2761 | else \ | |
2762 | __e = (e) - 1; \ | |
c1812bdb | 2763 | !!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \ |
ac657f64 TU |
2764 | }) |
2765 | ||
e87a005d JN |
2766 | /* |
2767 | * Return true if revision is in range [since,until] inclusive. | |
2768 | * | |
2769 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2770 | */ | |
2771 | #define IS_REVID(p, since, until) \ | |
2772 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2773 | ||
06bcd848 JN |
2774 | #define IS_I830(dev_priv) ((dev_priv)->info.platform == INTEL_I830) |
2775 | #define IS_I845G(dev_priv) ((dev_priv)->info.platform == INTEL_I845G) | |
2e0d26f8 | 2776 | #define IS_I85X(dev_priv) ((dev_priv)->info.platform == INTEL_I85X) |
06bcd848 | 2777 | #define IS_I865G(dev_priv) ((dev_priv)->info.platform == INTEL_I865G) |
2e0d26f8 | 2778 | #define IS_I915G(dev_priv) ((dev_priv)->info.platform == INTEL_I915G) |
06bcd848 JN |
2779 | #define IS_I915GM(dev_priv) ((dev_priv)->info.platform == INTEL_I915GM) |
2780 | #define IS_I945G(dev_priv) ((dev_priv)->info.platform == INTEL_I945G) | |
2e0d26f8 | 2781 | #define IS_I945GM(dev_priv) ((dev_priv)->info.platform == INTEL_I945GM) |
c0f86832 JN |
2782 | #define IS_I965G(dev_priv) ((dev_priv)->info.platform == INTEL_I965G) |
2783 | #define IS_I965GM(dev_priv) ((dev_priv)->info.platform == INTEL_I965GM) | |
f69c11ae JN |
2784 | #define IS_G45(dev_priv) ((dev_priv)->info.platform == INTEL_G45) |
2785 | #define IS_GM45(dev_priv) ((dev_priv)->info.platform == INTEL_GM45) | |
2786 | #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) | |
50a0bc90 TU |
2787 | #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) |
2788 | #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) | |
73f67aa8 | 2789 | #define IS_PINEVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_PINEVIEW) |
2e0d26f8 | 2790 | #define IS_G33(dev_priv) ((dev_priv)->info.platform == INTEL_G33) |
50a0bc90 | 2791 | #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) |
2e0d26f8 | 2792 | #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE) |
50a0bc90 TU |
2793 | #define IS_IVB_GT1(dev_priv) (INTEL_DEVID(dev_priv) == 0x0156 || \ |
2794 | INTEL_DEVID(dev_priv) == 0x0152 || \ | |
2795 | INTEL_DEVID(dev_priv) == 0x015a) | |
2e0d26f8 JN |
2796 | #define IS_VALLEYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_VALLEYVIEW) |
2797 | #define IS_CHERRYVIEW(dev_priv) ((dev_priv)->info.platform == INTEL_CHERRYVIEW) | |
2798 | #define IS_HASWELL(dev_priv) ((dev_priv)->info.platform == INTEL_HASWELL) | |
2799 | #define IS_BROADWELL(dev_priv) ((dev_priv)->info.platform == INTEL_BROADWELL) | |
2800 | #define IS_SKYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_SKYLAKE) | |
2801 | #define IS_BROXTON(dev_priv) ((dev_priv)->info.platform == INTEL_BROXTON) | |
2802 | #define IS_KABYLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_KABYLAKE) | |
2803 | #define IS_GEMINILAKE(dev_priv) ((dev_priv)->info.platform == INTEL_GEMINILAKE) | |
71851fa8 | 2804 | #define IS_COFFEELAKE(dev_priv) ((dev_priv)->info.platform == INTEL_COFFEELAKE) |
413f3c19 | 2805 | #define IS_CANNONLAKE(dev_priv) ((dev_priv)->info.platform == INTEL_CANNONLAKE) |
646d5772 | 2806 | #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) |
50a0bc90 TU |
2807 | #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ |
2808 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) | |
2809 | #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
2810 | ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ | |
2811 | (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ | |
2812 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) | |
ebb72aad | 2813 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
2814 | #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ |
2815 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe) | |
2816 | #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
2817 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) | |
2818 | #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ | |
2819 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) | |
2820 | #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ | |
2821 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) | |
9bbfd20a | 2822 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
2823 | #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ |
2824 | INTEL_DEVID(dev_priv) == 0x0A1E) | |
2825 | #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ | |
2826 | INTEL_DEVID(dev_priv) == 0x1913 || \ | |
2827 | INTEL_DEVID(dev_priv) == 0x1916 || \ | |
2828 | INTEL_DEVID(dev_priv) == 0x1921 || \ | |
2829 | INTEL_DEVID(dev_priv) == 0x1926) | |
2830 | #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ | |
2831 | INTEL_DEVID(dev_priv) == 0x1915 || \ | |
2832 | INTEL_DEVID(dev_priv) == 0x191E) | |
2833 | #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ | |
2834 | INTEL_DEVID(dev_priv) == 0x5913 || \ | |
2835 | INTEL_DEVID(dev_priv) == 0x5916 || \ | |
2836 | INTEL_DEVID(dev_priv) == 0x5921 || \ | |
2837 | INTEL_DEVID(dev_priv) == 0x5926) | |
2838 | #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ | |
2839 | INTEL_DEVID(dev_priv) == 0x5915 || \ | |
2840 | INTEL_DEVID(dev_priv) == 0x591E) | |
19f81df2 RB |
2841 | #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
2842 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010) | |
50a0bc90 TU |
2843 | #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
2844 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) | |
2845 | #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ | |
2846 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030) | |
3891589e LL |
2847 | #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ |
2848 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0010) | |
2849 | #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ | |
2850 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020) | |
da411a48 RV |
2851 | #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ |
2852 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) | |
7a58bad0 | 2853 | |
c007fb4a | 2854 | #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) |
cae5852d | 2855 | |
ef712bb4 JN |
2856 | #define SKL_REVID_A0 0x0 |
2857 | #define SKL_REVID_B0 0x1 | |
2858 | #define SKL_REVID_C0 0x2 | |
2859 | #define SKL_REVID_D0 0x3 | |
2860 | #define SKL_REVID_E0 0x4 | |
2861 | #define SKL_REVID_F0 0x5 | |
4ba9c1f7 MK |
2862 | #define SKL_REVID_G0 0x6 |
2863 | #define SKL_REVID_H0 0x7 | |
ef712bb4 | 2864 | |
e87a005d JN |
2865 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2866 | ||
ef712bb4 | 2867 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2868 | #define BXT_REVID_A1 0x1 |
ef712bb4 | 2869 | #define BXT_REVID_B0 0x3 |
a3f79ca6 | 2870 | #define BXT_REVID_B_LAST 0x8 |
ef712bb4 | 2871 | #define BXT_REVID_C0 0x9 |
6c74c87f | 2872 | |
e2d214ae TU |
2873 | #define IS_BXT_REVID(dev_priv, since, until) \ |
2874 | (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) | |
e87a005d | 2875 | |
c033a37c MK |
2876 | #define KBL_REVID_A0 0x0 |
2877 | #define KBL_REVID_B0 0x1 | |
fe905819 MK |
2878 | #define KBL_REVID_C0 0x2 |
2879 | #define KBL_REVID_D0 0x3 | |
2880 | #define KBL_REVID_E0 0x4 | |
c033a37c | 2881 | |
0853723b TU |
2882 | #define IS_KBL_REVID(dev_priv, since, until) \ |
2883 | (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
c033a37c | 2884 | |
f4f4b59b ACO |
2885 | #define GLK_REVID_A0 0x0 |
2886 | #define GLK_REVID_A1 0x1 | |
2887 | ||
2888 | #define IS_GLK_REVID(dev_priv, since, until) \ | |
2889 | (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
2890 | ||
3c2e0fd9 PZ |
2891 | #define CNL_REVID_A0 0x0 |
2892 | #define CNL_REVID_B0 0x1 | |
2893 | ||
2894 | #define IS_CNL_REVID(p, since, until) \ | |
2895 | (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) | |
2896 | ||
85436696 JB |
2897 | /* |
2898 | * The genX designation typically refers to the render engine, so render | |
2899 | * capability related checks should use IS_GEN, while display and other checks | |
2900 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2901 | * chips, etc.). | |
2902 | */ | |
5db94019 TU |
2903 | #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) |
2904 | #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) | |
2905 | #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) | |
2906 | #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) | |
2907 | #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) | |
2908 | #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) | |
2909 | #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) | |
2910 | #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) | |
413f3c19 | 2911 | #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) |
cae5852d | 2912 | |
8727dc09 | 2913 | #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) |
b976dc53 RV |
2914 | #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) |
2915 | #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) | |
3e4274f8 | 2916 | |
a19d6ff2 TU |
2917 | #define ENGINE_MASK(id) BIT(id) |
2918 | #define RENDER_RING ENGINE_MASK(RCS) | |
2919 | #define BSD_RING ENGINE_MASK(VCS) | |
2920 | #define BLT_RING ENGINE_MASK(BCS) | |
2921 | #define VEBOX_RING ENGINE_MASK(VECS) | |
2922 | #define BSD2_RING ENGINE_MASK(VCS2) | |
2923 | #define ALL_ENGINES (~0) | |
2924 | ||
2925 | #define HAS_ENGINE(dev_priv, id) \ | |
0031fb96 | 2926 | (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) |
a19d6ff2 TU |
2927 | |
2928 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
2929 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
2930 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
2931 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
2932 | ||
0031fb96 TU |
2933 | #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) |
2934 | #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) | |
2935 | #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) | |
8652744b TU |
2936 | #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ |
2937 | IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) | |
cae5852d | 2938 | |
0031fb96 | 2939 | #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) |
1d2a314c | 2940 | |
0031fb96 TU |
2941 | #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ |
2942 | ((dev_priv)->info.has_logical_ring_contexts) | |
2943 | #define USES_PPGTT(dev_priv) (i915.enable_ppgtt) | |
2944 | #define USES_FULL_PPGTT(dev_priv) (i915.enable_ppgtt >= 2) | |
2945 | #define USES_FULL_48BIT_PPGTT(dev_priv) (i915.enable_ppgtt == 3) | |
2946 | ||
2947 | #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) | |
2948 | #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ | |
2949 | ((dev_priv)->info.overlay_needs_physical) | |
cae5852d | 2950 | |
b45305fc | 2951 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2a307c2e | 2952 | #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
06e668ac MK |
2953 | |
2954 | /* WaRsDisableCoarsePowerGating:skl,bxt */ | |
61251512 | 2955 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ |
f2254d29 | 2956 | (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) |
185c66e5 | 2957 | |
4e6b788c DV |
2958 | /* |
2959 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2960 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2961 | * legacy irq no. is shared with another device. The kernel then disables that | |
2962 | * interrupt source and so prevents the other device from working properly. | |
2963 | */ | |
0031fb96 TU |
2964 | #define HAS_AUX_IRQ(dev_priv) ((dev_priv)->info.gen >= 5) |
2965 | #define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq) | |
b45305fc | 2966 | |
cae5852d ZN |
2967 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2968 | * rows, which changed the alignment requirements and fence programming. | |
2969 | */ | |
50a0bc90 TU |
2970 | #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ |
2971 | !(IS_I915G(dev_priv) || \ | |
2972 | IS_I915GM(dev_priv))) | |
56b857a5 TU |
2973 | #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) |
2974 | #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) | |
cae5852d | 2975 | |
56b857a5 TU |
2976 | #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) |
2977 | #define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr) | |
2978 | #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) | |
024faac7 | 2979 | #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7) |
cae5852d | 2980 | |
50a0bc90 | 2981 | #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) |
f5adf94e | 2982 | |
56b857a5 | 2983 | #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) |
0c9b3715 | 2984 | |
56b857a5 TU |
2985 | #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) |
2986 | #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) | |
2987 | #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) | |
2988 | #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) | |
2989 | #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) | |
affa9354 | 2990 | |
56b857a5 | 2991 | #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) |
eb805623 | 2992 | |
6772ffe0 | 2993 | #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) |
dfc5148f JL |
2994 | #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) |
2995 | ||
1a3d1898 DG |
2996 | /* |
2997 | * For now, anything with a GuC requires uCode loading, and then supports | |
2998 | * command submission once loaded. But these are logically independent | |
2999 | * properties, so we have separate macros to test them. | |
3000 | */ | |
4805fe82 | 3001 | #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) |
f8a58d63 | 3002 | #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) |
4805fe82 TU |
3003 | #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) |
3004 | #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) | |
bd132858 | 3005 | #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) |
33a732f4 | 3006 | |
4805fe82 | 3007 | #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) |
a9ed33ca | 3008 | |
4805fe82 | 3009 | #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) |
33e141ed | 3010 | |
c5e855d0 | 3011 | #define INTEL_PCH_DEVICE_ID_MASK 0xff80 |
17a303ec PZ |
3012 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
3013 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
3014 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
3015 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
3016 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
c5e855d0 VS |
3017 | #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 |
3018 | #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 | |
e7e7ea20 S |
3019 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
3020 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
c5e855d0 | 3021 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 |
7b22b8c4 | 3022 | #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 |
ec7e0bb3 | 3023 | #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 |
30c964a6 | 3024 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 3025 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 3026 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 3027 | |
6e266956 | 3028 | #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) |
7b22b8c4 | 3029 | #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) |
ec7e0bb3 DP |
3030 | #define HAS_PCH_CNP_LP(dev_priv) \ |
3031 | ((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) | |
6e266956 TU |
3032 | #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP) |
3033 | #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) | |
3034 | #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) | |
4f8036a2 | 3035 | #define HAS_PCH_LPT_LP(dev_priv) \ |
c5e855d0 VS |
3036 | ((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ |
3037 | (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) | |
4f8036a2 | 3038 | #define HAS_PCH_LPT_H(dev_priv) \ |
c5e855d0 VS |
3039 | ((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ |
3040 | (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE) | |
6e266956 TU |
3041 | #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) |
3042 | #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) | |
3043 | #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) | |
3044 | #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) | |
cae5852d | 3045 | |
49cff963 | 3046 | #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) |
5fafe292 | 3047 | |
ff15947e | 3048 | #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) |
6389dd83 | 3049 | |
040d2baa | 3050 | /* DPF == dynamic parity feature */ |
3c9192bc | 3051 | #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) |
50a0bc90 TU |
3052 | #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ |
3053 | 2 : HAS_L3_DPF(dev_priv)) | |
e1ef7cc2 | 3054 | |
c8735b0c | 3055 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 3056 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 3057 | |
05394f39 CW |
3058 | #include "i915_trace.h" |
3059 | ||
80debff8 | 3060 | static inline bool intel_vtd_active(void) |
48f112fe CW |
3061 | { |
3062 | #ifdef CONFIG_INTEL_IOMMU | |
80debff8 | 3063 | if (intel_iommu_gfx_mapped) |
48f112fe CW |
3064 | return true; |
3065 | #endif | |
3066 | return false; | |
3067 | } | |
3068 | ||
80debff8 CW |
3069 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) |
3070 | { | |
3071 | return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); | |
3072 | } | |
3073 | ||
0ef34ad6 JB |
3074 | static inline bool |
3075 | intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) | |
3076 | { | |
80debff8 | 3077 | return IS_BROXTON(dev_priv) && intel_vtd_active(); |
0ef34ad6 JB |
3078 | } |
3079 | ||
c033666a | 3080 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
351c3b53 | 3081 | int enable_ppgtt); |
0e4ca100 | 3082 | |
39df9190 CW |
3083 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value); |
3084 | ||
0673ad47 | 3085 | /* i915_drv.c */ |
d15d7538 ID |
3086 | void __printf(3, 4) |
3087 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
3088 | const char *fmt, ...); | |
3089 | ||
3090 | #define i915_report_error(dev_priv, fmt, ...) \ | |
3091 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
3092 | ||
c43b5634 | 3093 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
3094 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
3095 | unsigned long arg); | |
55edf41b JN |
3096 | #else |
3097 | #define i915_compat_ioctl NULL | |
c43b5634 | 3098 | #endif |
efab0698 JN |
3099 | extern const struct dev_pm_ops i915_pm_ops; |
3100 | ||
3101 | extern int i915_driver_load(struct pci_dev *pdev, | |
3102 | const struct pci_device_id *ent); | |
3103 | extern void i915_driver_unload(struct drm_device *dev); | |
dc97997a CW |
3104 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); |
3105 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
780f262a | 3106 | extern void i915_reset(struct drm_i915_private *dev_priv); |
142bc7d9 MT |
3107 | extern int i915_reset_engine(struct intel_engine_cs *engine); |
3108 | extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv); | |
6b332fa2 | 3109 | extern int intel_guc_reset(struct drm_i915_private *dev_priv); |
fc0768ce | 3110 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
3ac168a7 | 3111 | extern void intel_hangcheck_init(struct drm_i915_private *dev_priv); |
7648fa99 JB |
3112 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
3113 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
3114 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
3115 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 3116 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 3117 | |
63ffbcda | 3118 | int intel_engines_init_mmio(struct drm_i915_private *dev_priv); |
bb8f0f5a CW |
3119 | int intel_engines_init(struct drm_i915_private *dev_priv); |
3120 | ||
77913b39 | 3121 | /* intel_hotplug.c */ |
91d14251 TU |
3122 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
3123 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
3124 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
3125 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
3126 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 3127 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
b236d7c8 L |
3128 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); |
3129 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
77913b39 | 3130 | |
1da177e4 | 3131 | /* i915_irq.c */ |
26a02b8f CW |
3132 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
3133 | { | |
3134 | unsigned long delay; | |
3135 | ||
3136 | if (unlikely(!i915.enable_hangcheck)) | |
3137 | return; | |
3138 | ||
3139 | /* Don't continually defer the hangcheck so that it is always run at | |
3140 | * least once after work has been scheduled on any ring. Otherwise, | |
3141 | * we will ignore a hung ring if a second ring is kept busy. | |
3142 | */ | |
3143 | ||
3144 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
3145 | queue_delayed_work(system_long_wq, | |
3146 | &dev_priv->gpu_error.hangcheck_work, delay); | |
3147 | } | |
3148 | ||
58174462 | 3149 | __printf(3, 4) |
c033666a CW |
3150 | void i915_handle_error(struct drm_i915_private *dev_priv, |
3151 | u32 engine_mask, | |
58174462 | 3152 | const char *fmt, ...); |
1da177e4 | 3153 | |
b963291c | 3154 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
cefcff8f | 3155 | extern void intel_irq_fini(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
3156 | int intel_irq_install(struct drm_i915_private *dev_priv); |
3157 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 | 3158 | |
0ad35fed ZW |
3159 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) |
3160 | { | |
feddf6e8 | 3161 | return dev_priv->gvt; |
0ad35fed ZW |
3162 | } |
3163 | ||
c033666a | 3164 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) |
cf9d2890 | 3165 | { |
c033666a | 3166 | return dev_priv->vgpu.active; |
cf9d2890 | 3167 | } |
b1f14ad0 | 3168 | |
7c463586 | 3169 | void |
50227e1c | 3170 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 3171 | u32 status_mask); |
7c463586 KP |
3172 | |
3173 | void | |
50227e1c | 3174 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 3175 | u32 status_mask); |
7c463586 | 3176 | |
f8b79e58 ID |
3177 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
3178 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
3179 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
3180 | uint32_t mask, | |
3181 | uint32_t bits); | |
fbdedaea VS |
3182 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
3183 | uint32_t interrupt_mask, | |
3184 | uint32_t enabled_irq_mask); | |
3185 | static inline void | |
3186 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
3187 | { | |
3188 | ilk_update_display_irq(dev_priv, bits, bits); | |
3189 | } | |
3190 | static inline void | |
3191 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
3192 | { | |
3193 | ilk_update_display_irq(dev_priv, bits, 0); | |
3194 | } | |
013d3752 VS |
3195 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
3196 | enum pipe pipe, | |
3197 | uint32_t interrupt_mask, | |
3198 | uint32_t enabled_irq_mask); | |
3199 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
3200 | enum pipe pipe, uint32_t bits) | |
3201 | { | |
3202 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
3203 | } | |
3204 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
3205 | enum pipe pipe, uint32_t bits) | |
3206 | { | |
3207 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
3208 | } | |
47339cd9 DV |
3209 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
3210 | uint32_t interrupt_mask, | |
3211 | uint32_t enabled_irq_mask); | |
14443261 VS |
3212 | static inline void |
3213 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3214 | { | |
3215 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
3216 | } | |
3217 | static inline void | |
3218 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
3219 | { | |
3220 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
3221 | } | |
3222 | ||
673a394b | 3223 | /* i915_gem.c */ |
673a394b EA |
3224 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
3225 | struct drm_file *file_priv); | |
3226 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
3227 | struct drm_file *file_priv); | |
3228 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
3229 | struct drm_file *file_priv); | |
3230 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
3231 | struct drm_file *file_priv); | |
de151cf6 JB |
3232 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
3233 | struct drm_file *file_priv); | |
673a394b EA |
3234 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
3235 | struct drm_file *file_priv); | |
3236 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
3237 | struct drm_file *file_priv); | |
3238 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3239 | struct drm_file *file_priv); | |
76446cac JB |
3240 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
3241 | struct drm_file *file_priv); | |
673a394b EA |
3242 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
3243 | struct drm_file *file_priv); | |
199adf40 BW |
3244 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3245 | struct drm_file *file); | |
3246 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
3247 | struct drm_file *file); | |
673a394b EA |
3248 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
3249 | struct drm_file *file_priv); | |
3ef94daa CW |
3250 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
3251 | struct drm_file *file_priv); | |
111dbcab CW |
3252 | int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
3253 | struct drm_file *file_priv); | |
3254 | int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
3255 | struct drm_file *file_priv); | |
8a2421bd CW |
3256 | int i915_gem_init_userptr(struct drm_i915_private *dev_priv); |
3257 | void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); | |
5cc9ed4b CW |
3258 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
3259 | struct drm_file *file); | |
5a125c3c EA |
3260 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
3261 | struct drm_file *file_priv); | |
23ba4fd0 BW |
3262 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
3263 | struct drm_file *file_priv); | |
24145517 | 3264 | void i915_gem_sanitize(struct drm_i915_private *i915); |
cb15d9f8 TU |
3265 | int i915_gem_load_init(struct drm_i915_private *dev_priv); |
3266 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv); | |
40ae4e16 | 3267 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
6a800eab | 3268 | int i915_gem_freeze(struct drm_i915_private *dev_priv); |
461fb99c CW |
3269 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); |
3270 | ||
187685cb | 3271 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv); |
42dcedd4 | 3272 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
37e680a1 CW |
3273 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3274 | const struct drm_i915_gem_object_ops *ops); | |
12d79d78 TU |
3275 | struct drm_i915_gem_object * |
3276 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size); | |
3277 | struct drm_i915_gem_object * | |
3278 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, | |
3279 | const void *data, size_t size); | |
b1f788c6 | 3280 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); |
673a394b | 3281 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 3282 | |
bdeb9785 CW |
3283 | static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) |
3284 | { | |
3285 | /* A single pass should suffice to release all the freed objects (along | |
3286 | * most call paths) , but be a little more paranoid in that freeing | |
3287 | * the objects does take a little amount of time, during which the rcu | |
3288 | * callbacks could have added new objects into the freed list, and | |
3289 | * armed the work again. | |
3290 | */ | |
3291 | do { | |
3292 | rcu_barrier(); | |
3293 | } while (flush_work(&i915->mm.free_work)); | |
3294 | } | |
3295 | ||
3b19f16a CW |
3296 | static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) |
3297 | { | |
3298 | /* | |
3299 | * Similar to objects above (see i915_gem_drain_freed-objects), in | |
3300 | * general we have workers that are armed by RCU and then rearm | |
3301 | * themselves in their callbacks. To be paranoid, we need to | |
3302 | * drain the workqueue a second time after waiting for the RCU | |
3303 | * grace period so that we catch work queued via RCU from the first | |
3304 | * pass. As neither drain_workqueue() nor flush_workqueue() report | |
3305 | * a result, we make an assumption that we only don't require more | |
3306 | * than 2 passes to catch all recursive RCU delayed work. | |
3307 | * | |
3308 | */ | |
3309 | int pass = 2; | |
3310 | do { | |
3311 | rcu_barrier(); | |
3312 | drain_workqueue(i915->wq); | |
3313 | } while (--pass); | |
3314 | } | |
3315 | ||
058d88c4 | 3316 | struct i915_vma * __must_check |
ec7adb6e JL |
3317 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3318 | const struct i915_ggtt_view *view, | |
91b2db6f | 3319 | u64 size, |
2ffffd0f CW |
3320 | u64 alignment, |
3321 | u64 flags); | |
fe14d5f4 | 3322 | |
aa653a68 | 3323 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 3324 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 3325 | |
7c108fd8 CW |
3326 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); |
3327 | ||
a4f5ea64 | 3328 | static inline int __sg_page_count(const struct scatterlist *sg) |
9da3da66 | 3329 | { |
ee286370 CW |
3330 | return sg->length >> PAGE_SHIFT; |
3331 | } | |
67d5a50c | 3332 | |
96d77634 CW |
3333 | struct scatterlist * |
3334 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
3335 | unsigned int n, unsigned int *offset); | |
341be1cd | 3336 | |
96d77634 CW |
3337 | struct page * |
3338 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, | |
3339 | unsigned int n); | |
67d5a50c | 3340 | |
96d77634 CW |
3341 | struct page * |
3342 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
3343 | unsigned int n); | |
67d5a50c | 3344 | |
96d77634 CW |
3345 | dma_addr_t |
3346 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
3347 | unsigned long n); | |
ee286370 | 3348 | |
03ac84f1 CW |
3349 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, |
3350 | struct sg_table *pages); | |
a4f5ea64 CW |
3351 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
3352 | ||
3353 | static inline int __must_check | |
3354 | i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
3355 | { | |
1233e2db | 3356 | might_lock(&obj->mm.lock); |
a4f5ea64 | 3357 | |
1233e2db | 3358 | if (atomic_inc_not_zero(&obj->mm.pages_pin_count)) |
a4f5ea64 CW |
3359 | return 0; |
3360 | ||
3361 | return __i915_gem_object_get_pages(obj); | |
3362 | } | |
3363 | ||
3364 | static inline void | |
3365 | __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 3366 | { |
a4f5ea64 CW |
3367 | GEM_BUG_ON(!obj->mm.pages); |
3368 | ||
1233e2db | 3369 | atomic_inc(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
3370 | } |
3371 | ||
3372 | static inline bool | |
3373 | i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj) | |
3374 | { | |
1233e2db | 3375 | return atomic_read(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
3376 | } |
3377 | ||
3378 | static inline void | |
3379 | __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
3380 | { | |
a4f5ea64 CW |
3381 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
3382 | GEM_BUG_ON(!obj->mm.pages); | |
3383 | ||
1233e2db | 3384 | atomic_dec(&obj->mm.pages_pin_count); |
a5570178 | 3385 | } |
0a798eb9 | 3386 | |
1233e2db CW |
3387 | static inline void |
3388 | i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 3389 | { |
a4f5ea64 | 3390 | __i915_gem_object_unpin_pages(obj); |
a5570178 CW |
3391 | } |
3392 | ||
548625ee CW |
3393 | enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */ |
3394 | I915_MM_NORMAL = 0, | |
3395 | I915_MM_SHRINKER | |
3396 | }; | |
3397 | ||
3398 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, | |
3399 | enum i915_mm_subclass subclass); | |
03ac84f1 | 3400 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj); |
a4f5ea64 | 3401 | |
d31d7cb1 CW |
3402 | enum i915_map_type { |
3403 | I915_MAP_WB = 0, | |
3404 | I915_MAP_WC, | |
3405 | }; | |
3406 | ||
0a798eb9 CW |
3407 | /** |
3408 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
a73c7a44 CW |
3409 | * @obj: the object to map into kernel address space |
3410 | * @type: the type of mapping, used to select pgprot_t | |
0a798eb9 CW |
3411 | * |
3412 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3413 | * pages and then returns a contiguous mapping of the backing storage into | |
d31d7cb1 CW |
3414 | * the kernel address space. Based on the @type of mapping, the PTE will be |
3415 | * set to either WriteBack or WriteCombine (via pgprot_t). | |
0a798eb9 | 3416 | * |
1233e2db CW |
3417 | * The caller is responsible for calling i915_gem_object_unpin_map() when the |
3418 | * mapping is no longer required. | |
0a798eb9 | 3419 | * |
8305216f DG |
3420 | * Returns the pointer through which to access the mapped object, or an |
3421 | * ERR_PTR() on error. | |
0a798eb9 | 3422 | */ |
d31d7cb1 CW |
3423 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
3424 | enum i915_map_type type); | |
0a798eb9 CW |
3425 | |
3426 | /** | |
3427 | * i915_gem_object_unpin_map - releases an earlier mapping | |
a73c7a44 | 3428 | * @obj: the object to unmap |
0a798eb9 CW |
3429 | * |
3430 | * After pinning the object and mapping its pages, once you are finished | |
3431 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3432 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3433 | * removed. | |
0a798eb9 CW |
3434 | */ |
3435 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3436 | { | |
0a798eb9 CW |
3437 | i915_gem_object_unpin_pages(obj); |
3438 | } | |
3439 | ||
43394c7d CW |
3440 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
3441 | unsigned int *needs_clflush); | |
3442 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
3443 | unsigned int *needs_clflush); | |
7f5f95d8 CW |
3444 | #define CLFLUSH_BEFORE BIT(0) |
3445 | #define CLFLUSH_AFTER BIT(1) | |
3446 | #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) | |
43394c7d CW |
3447 | |
3448 | static inline void | |
3449 | i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) | |
3450 | { | |
3451 | i915_gem_object_unpin_pages(obj); | |
3452 | } | |
3453 | ||
54cf91dc | 3454 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
e2d05a8b | 3455 | void i915_vma_move_to_active(struct i915_vma *vma, |
5cf3d280 CW |
3456 | struct drm_i915_gem_request *req, |
3457 | unsigned int flags); | |
ff72145b DA |
3458 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3459 | struct drm_device *dev, | |
3460 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3461 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3462 | uint32_t handle, uint64_t *offset); | |
4cc69075 | 3463 | int i915_gem_mmap_gtt_version(void); |
85d1225e DG |
3464 | |
3465 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3466 | struct drm_i915_gem_object *new, | |
3467 | unsigned frontbuffer_bits); | |
3468 | ||
73cb9701 | 3469 | int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); |
1690e1eb | 3470 | |
8d9fc7fd | 3471 | struct drm_i915_gem_request * |
0bc40be8 | 3472 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3473 | |
67d97da3 | 3474 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv); |
84c33a64 | 3475 | |
8c185eca CW |
3476 | static inline bool i915_reset_backoff(struct i915_gpu_error *error) |
3477 | { | |
3478 | return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags)); | |
3479 | } | |
3480 | ||
3481 | static inline bool i915_reset_handoff(struct i915_gpu_error *error) | |
1f83fee0 | 3482 | { |
8c185eca | 3483 | return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags)); |
c19ae989 CW |
3484 | } |
3485 | ||
8af29b0c | 3486 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
c19ae989 | 3487 | { |
8af29b0c | 3488 | return unlikely(test_bit(I915_WEDGED, &error->flags)); |
1f83fee0 DV |
3489 | } |
3490 | ||
8c185eca | 3491 | static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error) |
1f83fee0 | 3492 | { |
8c185eca | 3493 | return i915_reset_backoff(error) | i915_terminally_wedged(error); |
2ac0f450 MK |
3494 | } |
3495 | ||
3496 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3497 | { | |
8af29b0c | 3498 | return READ_ONCE(error->reset_count); |
1f83fee0 | 3499 | } |
a71d8d94 | 3500 | |
702c8f8e MT |
3501 | static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, |
3502 | struct intel_engine_cs *engine) | |
3503 | { | |
3504 | return READ_ONCE(error->reset_engine_count[engine->id]); | |
3505 | } | |
3506 | ||
a1ef70e1 MT |
3507 | struct drm_i915_gem_request * |
3508 | i915_gem_reset_prepare_engine(struct intel_engine_cs *engine); | |
0e178aef | 3509 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv); |
d8027093 | 3510 | void i915_gem_reset(struct drm_i915_private *dev_priv); |
a1ef70e1 | 3511 | void i915_gem_reset_finish_engine(struct intel_engine_cs *engine); |
b1ed35d9 | 3512 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv); |
821ed7df | 3513 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv); |
2e8f9d32 | 3514 | bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv); |
a1ef70e1 MT |
3515 | void i915_gem_reset_engine(struct intel_engine_cs *engine, |
3516 | struct drm_i915_gem_request *request); | |
57822dc6 | 3517 | |
24145517 | 3518 | void i915_gem_init_mmio(struct drm_i915_private *i915); |
bf9e8429 TU |
3519 | int __must_check i915_gem_init(struct drm_i915_private *dev_priv); |
3520 | int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv); | |
c6be607a | 3521 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv); |
cb15d9f8 | 3522 | void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv); |
496b575e CW |
3523 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
3524 | unsigned int flags); | |
bf9e8429 TU |
3525 | int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv); |
3526 | void i915_gem_resume(struct drm_i915_private *dev_priv); | |
11bac800 | 3527 | int i915_gem_fault(struct vm_fault *vmf); |
e95433c7 CW |
3528 | int i915_gem_object_wait(struct drm_i915_gem_object *obj, |
3529 | unsigned int flags, | |
3530 | long timeout, | |
3531 | struct intel_rps_client *rps); | |
6b5e90f5 CW |
3532 | int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, |
3533 | unsigned int flags, | |
3534 | int priority); | |
3535 | #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX | |
3536 | ||
2e2f351d | 3537 | int __must_check |
e22d8e3c CW |
3538 | i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write); |
3539 | int __must_check | |
3540 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write); | |
2021746e | 3541 | int __must_check |
dabdfe02 | 3542 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
058d88c4 | 3543 | struct i915_vma * __must_check |
2da3b9b9 CW |
3544 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3545 | u32 alignment, | |
e6617330 | 3546 | const struct i915_ggtt_view *view); |
058d88c4 | 3547 | void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); |
00731155 | 3548 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3549 | int align); |
829a0af2 | 3550 | int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); |
05394f39 | 3551 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3552 | |
e4ffd173 CW |
3553 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3554 | enum i915_cache_level cache_level); | |
3555 | ||
1286ff73 DV |
3556 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3557 | struct dma_buf *dma_buf); | |
3558 | ||
3559 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3560 | struct drm_gem_object *gem_obj, int flags); | |
3561 | ||
841cd773 DV |
3562 | static inline struct i915_hw_ppgtt * |
3563 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3564 | { | |
841cd773 DV |
3565 | return container_of(vm, struct i915_hw_ppgtt, base); |
3566 | } | |
3567 | ||
b42fe9ca | 3568 | /* i915_gem_fence_reg.c */ |
49ef5294 CW |
3569 | int __must_check i915_vma_get_fence(struct i915_vma *vma); |
3570 | int __must_check i915_vma_put_fence(struct i915_vma *vma); | |
3571 | ||
b1ed35d9 | 3572 | void i915_gem_revoke_fences(struct drm_i915_private *dev_priv); |
4362f4f6 | 3573 | void i915_gem_restore_fences(struct drm_i915_private *dev_priv); |
41a36b73 | 3574 | |
4362f4f6 | 3575 | void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv); |
03ac84f1 CW |
3576 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, |
3577 | struct sg_table *pages); | |
3578 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, | |
3579 | struct sg_table *pages); | |
7f96ecaf | 3580 | |
1acfc104 CW |
3581 | static inline struct i915_gem_context * |
3582 | __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) | |
3583 | { | |
3584 | return idr_find(&file_priv->context_idr, id); | |
3585 | } | |
3586 | ||
ca585b5d CW |
3587 | static inline struct i915_gem_context * |
3588 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3589 | { | |
3590 | struct i915_gem_context *ctx; | |
3591 | ||
1acfc104 CW |
3592 | rcu_read_lock(); |
3593 | ctx = __i915_gem_context_lookup_rcu(file_priv, id); | |
3594 | if (ctx && !kref_get_unless_zero(&ctx->ref)) | |
3595 | ctx = NULL; | |
3596 | rcu_read_unlock(); | |
ca585b5d CW |
3597 | |
3598 | return ctx; | |
3599 | } | |
3600 | ||
80b204bc CW |
3601 | static inline struct intel_timeline * |
3602 | i915_gem_context_lookup_timeline(struct i915_gem_context *ctx, | |
3603 | struct intel_engine_cs *engine) | |
3604 | { | |
3605 | struct i915_address_space *vm; | |
3606 | ||
3607 | vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base; | |
3608 | return &vm->timeline.engine[engine->id]; | |
3609 | } | |
3610 | ||
eec688e1 RB |
3611 | int i915_perf_open_ioctl(struct drm_device *dev, void *data, |
3612 | struct drm_file *file); | |
19f81df2 RB |
3613 | void i915_oa_init_reg_state(struct intel_engine_cs *engine, |
3614 | struct i915_gem_context *ctx, | |
3615 | uint32_t *reg_state); | |
eec688e1 | 3616 | |
679845ed | 3617 | /* i915_gem_evict.c */ |
e522ac23 | 3618 | int __must_check i915_gem_evict_something(struct i915_address_space *vm, |
2ffffd0f | 3619 | u64 min_size, u64 alignment, |
679845ed | 3620 | unsigned cache_level, |
2ffffd0f | 3621 | u64 start, u64 end, |
1ec9e26d | 3622 | unsigned flags); |
625d988a CW |
3623 | int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, |
3624 | struct drm_mm_node *node, | |
3625 | unsigned int flags); | |
2889caa9 | 3626 | int i915_gem_evict_vm(struct i915_address_space *vm); |
1d2a314c | 3627 | |
0260c420 | 3628 | /* belongs in i915_gem_gtt.h */ |
c033666a | 3629 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) |
e76e9aeb | 3630 | { |
600f4368 | 3631 | wmb(); |
c033666a | 3632 | if (INTEL_GEN(dev_priv) < 6) |
e76e9aeb BW |
3633 | intel_gtt_chipset_flush(); |
3634 | } | |
246cbfb5 | 3635 | |
9797fbfb | 3636 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3637 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3638 | struct drm_mm_node *node, u64 size, | |
3639 | unsigned alignment); | |
a9da512b PZ |
3640 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3641 | struct drm_mm_node *node, u64 size, | |
3642 | unsigned alignment, u64 start, | |
3643 | u64 end); | |
d713fd49 PZ |
3644 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3645 | struct drm_mm_node *node); | |
7ace3d30 | 3646 | int i915_gem_init_stolen(struct drm_i915_private *dev_priv); |
9797fbfb | 3647 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb | 3648 | struct drm_i915_gem_object * |
187685cb | 3649 | i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size); |
866d12b4 | 3650 | struct drm_i915_gem_object * |
187685cb | 3651 | i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, |
866d12b4 CW |
3652 | u32 stolen_offset, |
3653 | u32 gtt_offset, | |
3654 | u32 size); | |
9797fbfb | 3655 | |
920cf419 CW |
3656 | /* i915_gem_internal.c */ |
3657 | struct drm_i915_gem_object * | |
3658 | i915_gem_object_create_internal(struct drm_i915_private *dev_priv, | |
fcd46e53 | 3659 | phys_addr_t size); |
920cf419 | 3660 | |
be6a0376 DV |
3661 | /* i915_gem_shrinker.c */ |
3662 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3663 | unsigned long target, |
be6a0376 DV |
3664 | unsigned flags); |
3665 | #define I915_SHRINK_PURGEABLE 0x1 | |
3666 | #define I915_SHRINK_UNBOUND 0x2 | |
3667 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3668 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3669 | #define I915_SHRINK_VMAPS 0x10 |
be6a0376 DV |
3670 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3671 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
a8a40589 | 3672 | void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv); |
be6a0376 DV |
3673 | |
3674 | ||
673a394b | 3675 | /* i915_gem_tiling.c */ |
2c1792a1 | 3676 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3677 | { |
091387c1 | 3678 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e9b73c67 CW |
3679 | |
3680 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3e510a8e | 3681 | i915_gem_object_is_tiled(obj); |
e9b73c67 CW |
3682 | } |
3683 | ||
91d4e0aa CW |
3684 | u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, |
3685 | unsigned int tiling, unsigned int stride); | |
3686 | u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, | |
3687 | unsigned int tiling, unsigned int stride); | |
3688 | ||
2017263e | 3689 | /* i915_debugfs.c */ |
f8c168fa | 3690 | #ifdef CONFIG_DEBUG_FS |
1dac891c | 3691 | int i915_debugfs_register(struct drm_i915_private *dev_priv); |
249e87de | 3692 | int i915_debugfs_connector_add(struct drm_connector *connector); |
36cdd013 | 3693 | void intel_display_crc_init(struct drm_i915_private *dev_priv); |
07144428 | 3694 | #else |
8d35acba | 3695 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} |
101057fa DV |
3696 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3697 | { return 0; } | |
ce5e2ac1 | 3698 | static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} |
07144428 | 3699 | #endif |
84734a04 MK |
3700 | |
3701 | /* i915_gpu_error.c */ | |
98a2f411 CW |
3702 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
3703 | ||
edc3d884 MK |
3704 | __printf(2, 3) |
3705 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b | 3706 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
5a4c6f1b | 3707 | const struct i915_gpu_state *gpu); |
4dc955f7 | 3708 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3709 | struct drm_i915_private *i915, |
4dc955f7 MK |
3710 | size_t count, loff_t pos); |
3711 | static inline void i915_error_state_buf_release( | |
3712 | struct drm_i915_error_state_buf *eb) | |
3713 | { | |
3714 | kfree(eb->buf); | |
3715 | } | |
5a4c6f1b CW |
3716 | |
3717 | struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915); | |
c033666a CW |
3718 | void i915_capture_error_state(struct drm_i915_private *dev_priv, |
3719 | u32 engine_mask, | |
58174462 | 3720 | const char *error_msg); |
5a4c6f1b CW |
3721 | |
3722 | static inline struct i915_gpu_state * | |
3723 | i915_gpu_state_get(struct i915_gpu_state *gpu) | |
3724 | { | |
3725 | kref_get(&gpu->ref); | |
3726 | return gpu; | |
3727 | } | |
3728 | ||
3729 | void __i915_gpu_state_free(struct kref *kref); | |
3730 | static inline void i915_gpu_state_put(struct i915_gpu_state *gpu) | |
3731 | { | |
3732 | if (gpu) | |
3733 | kref_put(&gpu->ref, __i915_gpu_state_free); | |
3734 | } | |
3735 | ||
3736 | struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915); | |
3737 | void i915_reset_error_state(struct drm_i915_private *i915); | |
84734a04 | 3738 | |
98a2f411 CW |
3739 | #else |
3740 | ||
3741 | static inline void i915_capture_error_state(struct drm_i915_private *dev_priv, | |
3742 | u32 engine_mask, | |
3743 | const char *error_msg) | |
3744 | { | |
3745 | } | |
3746 | ||
5a4c6f1b CW |
3747 | static inline struct i915_gpu_state * |
3748 | i915_first_error_state(struct drm_i915_private *i915) | |
3749 | { | |
3750 | return NULL; | |
3751 | } | |
3752 | ||
3753 | static inline void i915_reset_error_state(struct drm_i915_private *i915) | |
98a2f411 CW |
3754 | { |
3755 | } | |
3756 | ||
3757 | #endif | |
3758 | ||
0a4cd7c8 | 3759 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3760 | |
351e3db2 | 3761 | /* i915_cmd_parser.c */ |
1ca3712c | 3762 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
7756e454 | 3763 | void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 | 3764 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 CW |
3765 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, |
3766 | struct drm_i915_gem_object *batch_obj, | |
3767 | struct drm_i915_gem_object *shadow_batch_obj, | |
3768 | u32 batch_start_offset, | |
3769 | u32 batch_len, | |
3770 | bool is_master); | |
351e3db2 | 3771 | |
eec688e1 RB |
3772 | /* i915_perf.c */ |
3773 | extern void i915_perf_init(struct drm_i915_private *dev_priv); | |
3774 | extern void i915_perf_fini(struct drm_i915_private *dev_priv); | |
442b8c06 RB |
3775 | extern void i915_perf_register(struct drm_i915_private *dev_priv); |
3776 | extern void i915_perf_unregister(struct drm_i915_private *dev_priv); | |
eec688e1 | 3777 | |
317c35d1 | 3778 | /* i915_suspend.c */ |
af6dc742 TU |
3779 | extern int i915_save_state(struct drm_i915_private *dev_priv); |
3780 | extern int i915_restore_state(struct drm_i915_private *dev_priv); | |
0a3e67a4 | 3781 | |
0136db58 | 3782 | /* i915_sysfs.c */ |
694c2828 DW |
3783 | void i915_setup_sysfs(struct drm_i915_private *dev_priv); |
3784 | void i915_teardown_sysfs(struct drm_i915_private *dev_priv); | |
0136db58 | 3785 | |
eef57324 JA |
3786 | /* intel_lpe_audio.c */ |
3787 | int intel_lpe_audio_init(struct drm_i915_private *dev_priv); | |
3788 | void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); | |
3789 | void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); | |
46d196ec | 3790 | void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, |
20be551e VS |
3791 | enum pipe pipe, enum port port, |
3792 | const void *eld, int ls_clock, bool dp_output); | |
eef57324 | 3793 | |
f899fc64 | 3794 | /* intel_i2c.c */ |
40196446 TU |
3795 | extern int intel_setup_gmbus(struct drm_i915_private *dev_priv); |
3796 | extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv); | |
88ac7939 JN |
3797 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3798 | unsigned int pin); | |
3bd7d909 | 3799 | |
0184df46 JN |
3800 | extern struct i2c_adapter * |
3801 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3802 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3803 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3804 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3805 | { |
3806 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3807 | } | |
af6dc742 | 3808 | extern void intel_i2c_reset(struct drm_i915_private *dev_priv); |
f899fc64 | 3809 | |
8b8e1a89 | 3810 | /* intel_bios.c */ |
66578857 | 3811 | void intel_bios_init(struct drm_i915_private *dev_priv); |
f0067a31 | 3812 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 3813 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 3814 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
22f35042 | 3815 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
951d9efe | 3816 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 3817 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 3818 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
3819 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
3820 | enum port port); | |
6389dd83 SS |
3821 | bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, |
3822 | enum port port); | |
3823 | ||
8b8e1a89 | 3824 | |
3b617967 | 3825 | /* intel_opregion.c */ |
44834a67 | 3826 | #ifdef CONFIG_ACPI |
6f9f4b7a | 3827 | extern int intel_opregion_setup(struct drm_i915_private *dev_priv); |
03d92e47 CW |
3828 | extern void intel_opregion_register(struct drm_i915_private *dev_priv); |
3829 | extern void intel_opregion_unregister(struct drm_i915_private *dev_priv); | |
91d14251 | 3830 | extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv); |
9c4b0a68 JN |
3831 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3832 | bool enable); | |
6f9f4b7a | 3833 | extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv, |
ecbc5cf3 | 3834 | pci_power_t state); |
6f9f4b7a | 3835 | extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv); |
65e082c9 | 3836 | #else |
6f9f4b7a | 3837 | static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; } |
bdaa2dfb RD |
3838 | static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { } |
3839 | static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { } | |
91d14251 TU |
3840 | static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv) |
3841 | { | |
3842 | } | |
9c4b0a68 JN |
3843 | static inline int |
3844 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3845 | { | |
3846 | return 0; | |
3847 | } | |
ecbc5cf3 | 3848 | static inline int |
6f9f4b7a | 3849 | intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state) |
ecbc5cf3 JN |
3850 | { |
3851 | return 0; | |
3852 | } | |
6f9f4b7a | 3853 | static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev) |
a0562819 VS |
3854 | { |
3855 | return -ENODEV; | |
3856 | } | |
65e082c9 | 3857 | #endif |
8ee1c3db | 3858 | |
723bfd70 JB |
3859 | /* intel_acpi.c */ |
3860 | #ifdef CONFIG_ACPI | |
3861 | extern void intel_register_dsm_handler(void); | |
3862 | extern void intel_unregister_dsm_handler(void); | |
3863 | #else | |
3864 | static inline void intel_register_dsm_handler(void) { return; } | |
3865 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3866 | #endif /* CONFIG_ACPI */ | |
3867 | ||
94b4f3ba CW |
3868 | /* intel_device_info.c */ |
3869 | static inline struct intel_device_info * | |
3870 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
3871 | { | |
3872 | return (struct intel_device_info *)&dev_priv->info; | |
3873 | } | |
3874 | ||
2e0d26f8 | 3875 | const char *intel_platform_name(enum intel_platform platform); |
94b4f3ba CW |
3876 | void intel_device_info_runtime_init(struct drm_i915_private *dev_priv); |
3877 | void intel_device_info_dump(struct drm_i915_private *dev_priv); | |
3878 | ||
79e53945 | 3879 | /* modesetting */ |
f817586c | 3880 | extern void intel_modeset_init_hw(struct drm_device *dev); |
b079bd17 | 3881 | extern int intel_modeset_init(struct drm_device *dev); |
2c7111db | 3882 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3883 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1ebaa0b9 | 3884 | extern int intel_connector_register(struct drm_connector *); |
c191eca1 | 3885 | extern void intel_connector_unregister(struct drm_connector *); |
6315b5d3 TU |
3886 | extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, |
3887 | bool state); | |
043e9bda | 3888 | extern void intel_display_resume(struct drm_device *dev); |
29b74b7f TU |
3889 | extern void i915_redisable_vga(struct drm_i915_private *dev_priv); |
3890 | extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); | |
91d14251 | 3891 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
c39055b0 | 3892 | extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv); |
9fcee2f7 | 3893 | extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); |
11a85d6a | 3894 | extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
5209b1f4 | 3895 | bool enable); |
3bad0781 | 3896 | |
c0c7babc BW |
3897 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3898 | struct drm_file *file); | |
575155a9 | 3899 | |
6ef3d427 | 3900 | /* overlay */ |
c033666a CW |
3901 | extern struct intel_overlay_error_state * |
3902 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 MK |
3903 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3904 | struct intel_overlay_error_state *error); | |
c4a1d9e4 | 3905 | |
c033666a CW |
3906 | extern struct intel_display_error_state * |
3907 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 | 3908 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 | 3909 | struct intel_display_error_state *error); |
6ef3d427 | 3910 | |
151a49d0 TR |
3911 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3912 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
a0b8a1fe ID |
3913 | int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, |
3914 | u32 reply_mask, u32 reply, int timeout_base_ms); | |
59de0813 JN |
3915 | |
3916 | /* intel_sideband.c */ | |
707b6e3d | 3917 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
9fcee2f7 | 3918 | int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); |
64936258 | 3919 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3920 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3921 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3922 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3923 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3924 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3925 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3926 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3927 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3928 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3929 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3930 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3931 | enum intel_sbi_destination destination); | |
3932 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3933 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3934 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3935 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3936 | |
b7fa22d8 | 3937 | /* intel_dpio_phy.c */ |
0a116ce8 | 3938 | void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, |
ed37892e | 3939 | enum dpio_phy *phy, enum dpio_channel *ch); |
b6e08203 ACO |
3940 | void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, |
3941 | enum port port, u32 margin, u32 scale, | |
3942 | u32 enable, u32 deemphasis); | |
47a6bc61 ACO |
3943 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); |
3944 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); | |
3945 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, | |
3946 | enum dpio_phy phy); | |
3947 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, | |
3948 | enum dpio_phy phy); | |
3949 | uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder, | |
3950 | uint8_t lane_count); | |
3951 | void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, | |
3952 | uint8_t lane_lat_optim_mask); | |
3953 | uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); | |
3954 | ||
b7fa22d8 ACO |
3955 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
3956 | u32 deemph_reg_value, u32 margin_reg_value, | |
3957 | bool uniq_trans_scale); | |
844b2f9a ACO |
3958 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
3959 | bool reset); | |
419b1b7a | 3960 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder); |
e7d2a717 ACO |
3961 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
3962 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); | |
204970b5 | 3963 | void chv_phy_post_pll_disable(struct intel_encoder *encoder); |
b7fa22d8 | 3964 | |
53d98725 ACO |
3965 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
3966 | u32 demph_reg_value, u32 preemph_reg_value, | |
3967 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
6da2e616 | 3968 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder); |
5f68c275 | 3969 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder); |
0f572ebe | 3970 | void vlv_phy_reset_lanes(struct intel_encoder *encoder); |
53d98725 | 3971 | |
616bc820 VS |
3972 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3973 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c5a0ad11 MK |
3974 | u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, |
3975 | const i915_reg_t reg); | |
c8d9a590 | 3976 | |
0b274481 BW |
3977 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3978 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3979 | ||
3980 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3981 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3982 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3983 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3984 | ||
3985 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3986 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3987 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3988 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3989 | ||
698b3135 CW |
3990 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3991 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3992 | * an arbitrary delay between them. This can cause the hardware to | |
3993 | * act upon the intermediate value, possibly leading to corruption and | |
b18c1bb4 CW |
3994 | * machine death. For this reason we do not support I915_WRITE64, or |
3995 | * dev_priv->uncore.funcs.mmio_writeq. | |
3996 | * | |
3997 | * When reading a 64-bit value as two 32-bit values, the delay may cause | |
3998 | * the two reads to mismatch, e.g. a timestamp overflowing. Also note that | |
3999 | * occasionally a 64-bit register does not actualy support a full readq | |
4000 | * and must be read using two 32-bit reads. | |
4001 | * | |
4002 | * You have been warned. | |
698b3135 | 4003 | */ |
0b274481 | 4004 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
cae5852d | 4005 | |
50877445 | 4006 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
4007 | u32 upper, lower, old_upper, loop = 0; \ |
4008 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 4009 | do { \ |
acd29f7b | 4010 | old_upper = upper; \ |
ee0a227b | 4011 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
4012 | upper = I915_READ(upper_reg); \ |
4013 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 4014 | (u64)upper << 32 | lower; }) |
50877445 | 4015 | |
cae5852d ZN |
4016 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
4017 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
4018 | ||
75aa3f63 | 4019 | #define __raw_read(x, s) \ |
6e3955a5 | 4020 | static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \ |
f0f59a00 | 4021 | i915_reg_t reg) \ |
75aa3f63 | 4022 | { \ |
f0f59a00 | 4023 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
4024 | } |
4025 | ||
4026 | #define __raw_write(x, s) \ | |
6e3955a5 | 4027 | static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \ |
f0f59a00 | 4028 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 4029 | { \ |
f0f59a00 | 4030 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
4031 | } |
4032 | __raw_read(8, b) | |
4033 | __raw_read(16, w) | |
4034 | __raw_read(32, l) | |
4035 | __raw_read(64, q) | |
4036 | ||
4037 | __raw_write(8, b) | |
4038 | __raw_write(16, w) | |
4039 | __raw_write(32, l) | |
4040 | __raw_write(64, q) | |
4041 | ||
4042 | #undef __raw_read | |
4043 | #undef __raw_write | |
4044 | ||
a6111f7b | 4045 | /* These are untraced mmio-accessors that are only valid to be used inside |
aafee2eb | 4046 | * critical sections, such as inside IRQ handlers, where forcewake is explicitly |
a6111f7b | 4047 | * controlled. |
aafee2eb | 4048 | * |
a6111f7b | 4049 | * Think twice, and think again, before using these. |
aafee2eb AH |
4050 | * |
4051 | * As an example, these accessors can possibly be used between: | |
4052 | * | |
4053 | * spin_lock_irq(&dev_priv->uncore.lock); | |
4054 | * intel_uncore_forcewake_get__locked(); | |
4055 | * | |
4056 | * and | |
4057 | * | |
4058 | * intel_uncore_forcewake_put__locked(); | |
4059 | * spin_unlock_irq(&dev_priv->uncore.lock); | |
4060 | * | |
4061 | * | |
4062 | * Note: some registers may not need forcewake held, so | |
4063 | * intel_uncore_forcewake_{get,put} can be omitted, see | |
4064 | * intel_uncore_forcewake_for_reg(). | |
4065 | * | |
4066 | * Certain architectures will die if the same cacheline is concurrently accessed | |
4067 | * by different clients (e.g. on Ivybridge). Access to registers should | |
4068 | * therefore generally be serialised, by either the dev_priv->uncore.lock or | |
4069 | * a more localised lock guarding all access to that bank of registers. | |
a6111f7b | 4070 | */ |
75aa3f63 VS |
4071 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
4072 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
76f8421f | 4073 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) |
a6111f7b CW |
4074 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
4075 | ||
55bc60db VS |
4076 | /* "Broadcast RGB" property */ |
4077 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
4078 | #define INTEL_BROADCAST_RGB_FULL 1 | |
4079 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 4080 | |
920a14b2 | 4081 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) |
766aa1c4 | 4082 | { |
920a14b2 | 4083 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
766aa1c4 | 4084 | return VLV_VGACNTRL; |
920a14b2 | 4085 | else if (INTEL_GEN(dev_priv) >= 5) |
92e23b99 | 4086 | return CPU_VGACNTRL; |
766aa1c4 VS |
4087 | else |
4088 | return VGACNTRL; | |
4089 | } | |
4090 | ||
df97729f ID |
4091 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
4092 | { | |
4093 | unsigned long j = msecs_to_jiffies(m); | |
4094 | ||
4095 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
4096 | } | |
4097 | ||
7bd0e226 DV |
4098 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
4099 | { | |
4100 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
4101 | } | |
4102 | ||
df97729f ID |
4103 | static inline unsigned long |
4104 | timespec_to_jiffies_timeout(const struct timespec *value) | |
4105 | { | |
4106 | unsigned long j = timespec_to_jiffies(value); | |
4107 | ||
4108 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
4109 | } | |
4110 | ||
dce56b3c PZ |
4111 | /* |
4112 | * If you need to wait X milliseconds between events A and B, but event B | |
4113 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
4114 | * when event A happened, then just before event B you call this function and | |
4115 | * pass the timestamp as the first argument, and X as the second argument. | |
4116 | */ | |
4117 | static inline void | |
4118 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
4119 | { | |
ec5e0cfb | 4120 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
4121 | |
4122 | /* | |
4123 | * Don't re-read the value of "jiffies" every time since it may change | |
4124 | * behind our back and break the math. | |
4125 | */ | |
4126 | tmp_jiffies = jiffies; | |
4127 | target_jiffies = timestamp_jiffies + | |
4128 | msecs_to_jiffies_timeout(to_wait_ms); | |
4129 | ||
4130 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
4131 | remaining_jiffies = target_jiffies - tmp_jiffies; |
4132 | while (remaining_jiffies) | |
4133 | remaining_jiffies = | |
4134 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
4135 | } |
4136 | } | |
221fe799 CW |
4137 | |
4138 | static inline bool | |
754c9fd5 | 4139 | __i915_request_irq_complete(const struct drm_i915_gem_request *req) |
688e6c72 | 4140 | { |
f69a02c9 | 4141 | struct intel_engine_cs *engine = req->engine; |
754c9fd5 | 4142 | u32 seqno; |
f69a02c9 | 4143 | |
309663ab CW |
4144 | /* Note that the engine may have wrapped around the seqno, and |
4145 | * so our request->global_seqno will be ahead of the hardware, | |
4146 | * even though it completed the request before wrapping. We catch | |
4147 | * this by kicking all the waiters before resetting the seqno | |
4148 | * in hardware, and also signal the fence. | |
4149 | */ | |
4150 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags)) | |
4151 | return true; | |
4152 | ||
754c9fd5 CW |
4153 | /* The request was dequeued before we were awoken. We check after |
4154 | * inspecting the hw to confirm that this was the same request | |
4155 | * that generated the HWS update. The memory barriers within | |
4156 | * the request execution are sufficient to ensure that a check | |
4157 | * after reading the value from hw matches this request. | |
4158 | */ | |
4159 | seqno = i915_gem_request_global_seqno(req); | |
4160 | if (!seqno) | |
4161 | return false; | |
4162 | ||
7ec2c73b CW |
4163 | /* Before we do the heavier coherent read of the seqno, |
4164 | * check the value (hopefully) in the CPU cacheline. | |
4165 | */ | |
754c9fd5 | 4166 | if (__i915_gem_request_completed(req, seqno)) |
7ec2c73b CW |
4167 | return true; |
4168 | ||
688e6c72 CW |
4169 | /* Ensure our read of the seqno is coherent so that we |
4170 | * do not "miss an interrupt" (i.e. if this is the last | |
4171 | * request and the seqno write from the GPU is not visible | |
4172 | * by the time the interrupt fires, we will see that the | |
4173 | * request is incomplete and go back to sleep awaiting | |
4174 | * another interrupt that will never come.) | |
4175 | * | |
4176 | * Strictly, we only need to do this once after an interrupt, | |
4177 | * but it is easier and safer to do it every time the waiter | |
4178 | * is woken. | |
4179 | */ | |
3d5564e9 | 4180 | if (engine->irq_seqno_barrier && |
538b257d | 4181 | test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) { |
56299fb7 | 4182 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
99fe4a5f | 4183 | |
3d5564e9 CW |
4184 | /* The ordering of irq_posted versus applying the barrier |
4185 | * is crucial. The clearing of the current irq_posted must | |
4186 | * be visible before we perform the barrier operation, | |
4187 | * such that if a subsequent interrupt arrives, irq_posted | |
4188 | * is reasserted and our task rewoken (which causes us to | |
4189 | * do another __i915_request_irq_complete() immediately | |
4190 | * and reapply the barrier). Conversely, if the clear | |
4191 | * occurs after the barrier, then an interrupt that arrived | |
4192 | * whilst we waited on the barrier would not trigger a | |
4193 | * barrier on the next pass, and the read may not see the | |
4194 | * seqno update. | |
4195 | */ | |
f69a02c9 | 4196 | engine->irq_seqno_barrier(engine); |
99fe4a5f CW |
4197 | |
4198 | /* If we consume the irq, but we are no longer the bottom-half, | |
4199 | * the real bottom-half may not have serialised their own | |
4200 | * seqno check with the irq-barrier (i.e. may have inspected | |
4201 | * the seqno before we believe it coherent since they see | |
4202 | * irq_posted == false but we are still running). | |
4203 | */ | |
2c33b541 | 4204 | spin_lock_irq(&b->irq_lock); |
61d3dc70 | 4205 | if (b->irq_wait && b->irq_wait->tsk != current) |
99fe4a5f CW |
4206 | /* Note that if the bottom-half is changed as we |
4207 | * are sending the wake-up, the new bottom-half will | |
4208 | * be woken by whomever made the change. We only have | |
4209 | * to worry about when we steal the irq-posted for | |
4210 | * ourself. | |
4211 | */ | |
61d3dc70 | 4212 | wake_up_process(b->irq_wait->tsk); |
2c33b541 | 4213 | spin_unlock_irq(&b->irq_lock); |
99fe4a5f | 4214 | |
754c9fd5 | 4215 | if (__i915_gem_request_completed(req, seqno)) |
7ec2c73b CW |
4216 | return true; |
4217 | } | |
688e6c72 | 4218 | |
688e6c72 CW |
4219 | return false; |
4220 | } | |
4221 | ||
0b1de5d5 CW |
4222 | void i915_memcpy_init_early(struct drm_i915_private *dev_priv); |
4223 | bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); | |
4224 | ||
c4d3ae68 CW |
4225 | /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment, |
4226 | * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot | |
4227 | * perform the operation. To check beforehand, pass in the parameters to | |
4228 | * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits, | |
4229 | * you only need to pass in the minor offsets, page-aligned pointers are | |
4230 | * always valid. | |
4231 | * | |
4232 | * For just checking for SSE4.1, in the foreknowledge that the future use | |
4233 | * will be correctly aligned, just use i915_has_memcpy_from_wc(). | |
4234 | */ | |
4235 | #define i915_can_memcpy_from_wc(dst, src, len) \ | |
4236 | i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0) | |
4237 | ||
4238 | #define i915_has_memcpy_from_wc() \ | |
4239 | i915_memcpy_from_wc(NULL, NULL, 0) | |
4240 | ||
c58305af CW |
4241 | /* i915_mm.c */ |
4242 | int remap_io_mapping(struct vm_area_struct *vma, | |
4243 | unsigned long addr, unsigned long pfn, unsigned long size, | |
4244 | struct io_mapping *iomap); | |
4245 | ||
e59dc172 CW |
4246 | static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj) |
4247 | { | |
4248 | return (obj->cache_level != I915_CACHE_NONE || | |
4249 | HAS_LLC(to_i915(obj->base.dev))); | |
4250 | } | |
4251 | ||
1da177e4 | 4252 | #endif |