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Commit | Line | Data |
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327d8e4e AJ |
1 | /* |
2 | * OpenPOWER Palmetto BMC | |
3 | * | |
4 | * Andrew Jeffery <andrew@aj.id.au> | |
5 | * | |
6 | * Copyright 2016 IBM Corp. | |
7 | * | |
8 | * This code is licensed under the GPL version 2 or later. See | |
9 | * the COPYING file in the top-level directory. | |
10 | */ | |
11 | ||
12 | #include "qemu/osdep.h" | |
da34e65c | 13 | #include "qapi/error.h" |
4771d756 | 14 | #include "cpu.h" |
327d8e4e | 15 | #include "exec/address-spaces.h" |
12ec8bd5 | 16 | #include "hw/arm/boot.h" |
fca9ca1b | 17 | #include "hw/arm/aspeed.h" |
00442402 | 18 | #include "hw/arm/aspeed_soc.h" |
327d8e4e | 19 | #include "hw/boards.h" |
93198b6c | 20 | #include "hw/i2c/smbus_eeprom.h" |
044475f3 PMD |
21 | #include "hw/misc/pca9552.h" |
22 | #include "hw/misc/tmp105.h" | |
a27bd6c7 | 23 | #include "hw/qdev-properties.h" |
03dd024f | 24 | #include "qemu/log.h" |
e1ad9bc4 | 25 | #include "sysemu/block-backend.h" |
ece09bee | 26 | #include "sysemu/sysemu.h" |
d769a1da CLG |
27 | #include "hw/loader.h" |
28 | #include "qemu/error-report.h" | |
a9df9622 | 29 | #include "qemu/units.h" |
327d8e4e | 30 | |
74fb1f38 | 31 | static struct arm_boot_info aspeed_board_binfo = { |
b033271f | 32 | .board_id = -1, /* device-tree-only board */ |
327d8e4e AJ |
33 | }; |
34 | ||
612b219a | 35 | struct AspeedMachineState { |
888b2b03 PMD |
36 | /* Private */ |
37 | MachineState parent_obj; | |
38 | /* Public */ | |
39 | ||
ff90606f | 40 | AspeedSoCState soc; |
ad1a9782 | 41 | MemoryRegion ram_container; |
ebe31c0a | 42 | MemoryRegion max_ram; |
888b2b03 | 43 | bool mmio_exec; |
ea066d39 | 44 | }; |
327d8e4e | 45 | |
ef17f836 | 46 | /* Palmetto hardware value: 0x120CE416 */ |
8da33ef7 CLG |
47 | #define PALMETTO_BMC_HW_STRAP1 ( \ |
48 | SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ | |
49 | SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ | |
50 | SCU_AST2400_HW_STRAP_ACPI_DIS | \ | |
51 | SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ | |
52 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
53 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
54 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ | |
55 | SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ | |
56 | SCU_HW_STRAP_SPI_WIDTH | \ | |
57 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
58 | SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) | |
59 | ||
40a38df5 ES |
60 | /* TODO: Find the actual hardware value */ |
61 | #define SUPERMICROX11_BMC_HW_STRAP1 ( \ | |
62 | SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ | |
63 | SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \ | |
64 | SCU_AST2400_HW_STRAP_ACPI_DIS | \ | |
65 | SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ | |
66 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
67 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
68 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ | |
69 | SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ | |
70 | SCU_HW_STRAP_SPI_WIDTH | \ | |
71 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
72 | SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) | |
73 | ||
ef17f836 | 74 | /* AST2500 evb hardware value: 0xF100C2E6 */ |
9a7c1750 CLG |
75 | #define AST2500_EVB_HW_STRAP1 (( \ |
76 | AST2500_HW_STRAP1_DEFAULTS | \ | |
77 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
78 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
79 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
80 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
81 | SCU_HW_STRAP_MAC1_RGMII | \ | |
82 | SCU_HW_STRAP_MAC0_RGMII) & \ | |
83 | ~SCU_HW_STRAP_2ND_BOOT_WDT) | |
84 | ||
ef17f836 CLG |
85 | /* Romulus hardware value: 0xF10AD206 */ |
86 | #define ROMULUS_BMC_HW_STRAP1 ( \ | |
87 | AST2500_HW_STRAP1_DEFAULTS | \ | |
88 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
89 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
90 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
91 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
92 | SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ | |
93 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) | |
94 | ||
143b040f PW |
95 | /* Sonorapass hardware value: 0xF100D216 */ |
96 | #define SONORAPASS_BMC_HW_STRAP1 ( \ | |
97 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
98 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
99 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
100 | SCU_AST2500_HW_STRAP_RESERVED28 | \ | |
101 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
102 | SCU_HW_STRAP_VGA_CLASS_CODE | \ | |
103 | SCU_HW_STRAP_LPC_RESET_PIN | \ | |
104 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \ | |
105 | SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \ | |
106 | SCU_HW_STRAP_VGA_BIOS_ROM | \ | |
107 | SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ | |
108 | SCU_AST2500_HW_STRAP_RESERVED1) | |
109 | ||
aae7a18d AK |
110 | /* Swift hardware value: 0xF11AD206 */ |
111 | #define SWIFT_BMC_HW_STRAP1 ( \ | |
112 | AST2500_HW_STRAP1_DEFAULTS | \ | |
113 | SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ | |
114 | SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ | |
115 | SCU_AST2500_HW_STRAP_UART_DEBUG | \ | |
116 | SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ | |
117 | SCU_H_PLL_BYPASS_EN | \ | |
118 | SCU_AST2500_HW_STRAP_ACPI_ENABLE | \ | |
119 | SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER)) | |
120 | ||
62c2c2eb CLG |
121 | /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ |
122 | #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 | |
123 | ||
ccc2c418 CLG |
124 | /* AST2600 evb hardware value */ |
125 | #define AST2600_EVB_HW_STRAP1 0x000000C0 | |
126 | #define AST2600_EVB_HW_STRAP2 0x00000003 | |
127 | ||
63ceb818 CLG |
128 | /* Tacoma hardware value */ |
129 | #define TACOMA_BMC_HW_STRAP1 0x00000000 | |
7582591a | 130 | #define TACOMA_BMC_HW_STRAP2 0x00000040 |
63ceb818 | 131 | |
ebe31c0a CLG |
132 | /* |
133 | * The max ram region is for firmwares that scan the address space | |
134 | * with load/store to guess how much RAM the SoC has. | |
135 | */ | |
136 | static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size) | |
137 | { | |
138 | return 0; | |
139 | } | |
140 | ||
141 | static void max_ram_write(void *opaque, hwaddr offset, uint64_t value, | |
142 | unsigned size) | |
143 | { | |
144 | /* Discard writes */ | |
145 | } | |
146 | ||
147 | static const MemoryRegionOps max_ram_ops = { | |
148 | .read = max_ram_read, | |
149 | .write = max_ram_write, | |
150 | .endianness = DEVICE_NATIVE_ENDIAN, | |
151 | }; | |
152 | ||
9bb6d140 JS |
153 | #define AST_SMP_MAILBOX_BASE 0x1e6e2180 |
154 | #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0) | |
155 | #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4) | |
156 | #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8) | |
157 | #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc) | |
158 | #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10) | |
159 | #define AST_SMP_MBOX_GOSIGN 0xabbaab00 | |
160 | ||
161 | static void aspeed_write_smpboot(ARMCPU *cpu, | |
162 | const struct arm_boot_info *info) | |
163 | { | |
164 | static const uint32_t poll_mailbox_ready[] = { | |
165 | /* | |
166 | * r2 = per-cpu go sign value | |
167 | * r1 = AST_SMP_MBOX_FIELD_ENTRY | |
168 | * r0 = AST_SMP_MBOX_FIELD_GOSIGN | |
169 | */ | |
170 | 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */ | |
171 | 0xe21000ff, /* ands r0, r0, #255 */ | |
172 | 0xe59f201c, /* ldr r2, [pc, #28] */ | |
173 | 0xe1822000, /* orr r2, r2, r0 */ | |
174 | ||
175 | 0xe59f1018, /* ldr r1, [pc, #24] */ | |
176 | 0xe59f0018, /* ldr r0, [pc, #24] */ | |
177 | ||
178 | 0xe320f002, /* wfe */ | |
179 | 0xe5904000, /* ldr r4, [r0] */ | |
180 | 0xe1520004, /* cmp r2, r4 */ | |
181 | 0x1afffffb, /* bne <wfe> */ | |
182 | 0xe591f000, /* ldr pc, [r1] */ | |
183 | AST_SMP_MBOX_GOSIGN, | |
184 | AST_SMP_MBOX_FIELD_ENTRY, | |
185 | AST_SMP_MBOX_FIELD_GOSIGN, | |
186 | }; | |
187 | ||
188 | rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready, | |
189 | sizeof(poll_mailbox_ready), | |
190 | info->smp_loader_start); | |
191 | } | |
192 | ||
193 | static void aspeed_reset_secondary(ARMCPU *cpu, | |
194 | const struct arm_boot_info *info) | |
195 | { | |
196 | AddressSpace *as = arm_boot_address_space(cpu, info); | |
197 | CPUState *cs = CPU(cpu); | |
198 | ||
199 | /* info->smp_bootreg_addr */ | |
200 | address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0, | |
201 | MEMTXATTRS_UNSPECIFIED, NULL); | |
202 | cpu_set_pc(cs, info->smp_loader_start); | |
203 | } | |
204 | ||
d769a1da CLG |
205 | #define FIRMWARE_ADDR 0x0 |
206 | ||
207 | static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size, | |
208 | Error **errp) | |
209 | { | |
210 | BlockBackend *blk = blk_by_legacy_dinfo(dinfo); | |
211 | uint8_t *storage; | |
0c7209be CLG |
212 | int64_t size; |
213 | ||
214 | /* The block backend size should have already been 'validated' by | |
215 | * the creation of the m25p80 object. | |
216 | */ | |
217 | size = blk_getlength(blk); | |
218 | if (size <= 0) { | |
219 | error_setg(errp, "failed to get flash size"); | |
220 | return; | |
221 | } | |
d769a1da | 222 | |
0c7209be CLG |
223 | if (rom_size > size) { |
224 | rom_size = size; | |
d769a1da CLG |
225 | } |
226 | ||
227 | storage = g_new0(uint8_t, rom_size); | |
228 | if (blk_pread(blk, 0, storage, rom_size) < 0) { | |
229 | error_setg(errp, "failed to read the initial flash content"); | |
230 | return; | |
231 | } | |
232 | ||
233 | rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr); | |
234 | g_free(storage); | |
235 | } | |
236 | ||
c20b4ccc MA |
237 | static void aspeed_board_init_flashes(AspeedSMCState *s, |
238 | const char *flashtype) | |
e1ad9bc4 CLG |
239 | { |
240 | int i ; | |
241 | ||
242 | for (i = 0; i < s->num_cs; ++i) { | |
243 | AspeedSMCFlash *fl = &s->flashes[i]; | |
244 | DriveInfo *dinfo = drive_get_next(IF_MTD); | |
245 | qemu_irq cs_line; | |
246 | ||
57d479c9 | 247 | fl->flash = qdev_new(flashtype); |
e1ad9bc4 | 248 | if (dinfo) { |
c20b4ccc MA |
249 | qdev_prop_set_drive(fl->flash, "drive", |
250 | blk_by_legacy_dinfo(dinfo)); | |
e1ad9bc4 | 251 | } |
57d479c9 | 252 | qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal); |
e1ad9bc4 CLG |
253 | |
254 | cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0); | |
255 | sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line); | |
256 | } | |
257 | } | |
258 | ||
a29e3e12 AJ |
259 | static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo) |
260 | { | |
261 | DeviceState *card; | |
262 | ||
756f739b PMD |
263 | if (!dinfo) { |
264 | return; | |
a29e3e12 | 265 | } |
756f739b PMD |
266 | card = qdev_new(TYPE_SD_CARD); |
267 | qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), | |
268 | &error_fatal); | |
3e80f690 MA |
269 | qdev_realize_and_unref(card, |
270 | qdev_get_child_bus(DEVICE(sdhci), "sd-bus"), | |
271 | &error_fatal); | |
a29e3e12 AJ |
272 | } |
273 | ||
baa4732b | 274 | static void aspeed_machine_init(MachineState *machine) |
327d8e4e | 275 | { |
888b2b03 | 276 | AspeedMachineState *bmc = ASPEED_MACHINE(machine); |
baa4732b | 277 | AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine); |
b033271f | 278 | AspeedSoCClass *sc; |
d769a1da | 279 | DriveInfo *drive0 = drive_get(IF_MTD, 0, 0); |
ebe31c0a | 280 | ram_addr_t max_ram_size; |
2bea128c | 281 | int i; |
d3bad7e7 | 282 | NICInfo *nd = &nd_table[0]; |
327d8e4e | 283 | |
ad1a9782 | 284 | memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container", |
7df9f028 | 285 | 4 * GiB); |
afcbaed6 | 286 | memory_region_add_subregion(&bmc->ram_container, 0, machine->ram); |
ad1a9782 | 287 | |
9fc7fc4d | 288 | object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name); |
327d8e4e | 289 | |
b033271f CLG |
290 | sc = ASPEED_SOC_GET_CLASS(&bmc->soc); |
291 | ||
533eb415 IM |
292 | /* |
293 | * This will error out if isize is not supported by memory controller. | |
294 | */ | |
5325cc34 | 295 | object_property_set_uint(OBJECT(&bmc->soc), "ram-size", ram_size, |
533eb415 IM |
296 | &error_fatal); |
297 | ||
d3bad7e7 CLG |
298 | for (i = 0; i < sc->macs_num; i++) { |
299 | if ((amc->macs_mask & (1 << i)) && nd->used) { | |
300 | qemu_check_nic_model(nd, TYPE_FTGMAC100); | |
301 | qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd); | |
302 | nd++; | |
303 | } | |
304 | } | |
305 | ||
5325cc34 | 306 | object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1, |
87e79af0 | 307 | &error_abort); |
5325cc34 | 308 | object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2, |
ccc2c418 | 309 | &error_abort); |
5325cc34 | 310 | object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, |
26d5df95 | 311 | &error_abort); |
5325cc34 MA |
312 | object_property_set_link(OBJECT(&bmc->soc), "dram", |
313 | OBJECT(&bmc->ram_container), &error_abort); | |
b6e70d1d JS |
314 | if (machine->kernel_filename) { |
315 | /* | |
316 | * When booting with a -kernel command line there is no u-boot | |
317 | * that runs to unlock the SCU. In this case set the default to | |
318 | * be unlocked as the kernel expects | |
319 | */ | |
5325cc34 MA |
320 | object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key", |
321 | ASPEED_SCU_PROT_KEY, &error_abort); | |
b6e70d1d | 322 | } |
ce189ab2 | 323 | qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); |
327d8e4e | 324 | |
d783d1fe | 325 | memory_region_add_subregion(get_system_memory(), |
347df6f8 | 326 | sc->memmap[ASPEED_DEV_SDRAM], |
ad1a9782 | 327 | &bmc->ram_container); |
de46f5f4 | 328 | |
ebe31c0a CLG |
329 | max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size", |
330 | &error_abort); | |
331 | memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL, | |
332 | "max_ram", max_ram_size - ram_size); | |
ad1a9782 | 333 | memory_region_add_subregion(&bmc->ram_container, ram_size, &bmc->max_ram); |
ebe31c0a | 334 | |
c20b4ccc MA |
335 | aspeed_board_init_flashes(&bmc->soc.fmc, amc->fmc_model); |
336 | aspeed_board_init_flashes(&bmc->soc.spi[0], amc->spi_model); | |
74fb1f38 | 337 | |
d769a1da CLG |
338 | /* Install first FMC flash content as a boot rom. */ |
339 | if (drive0) { | |
340 | AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0]; | |
341 | MemoryRegion *boot_rom = g_new(MemoryRegion, 1); | |
342 | ||
343 | /* | |
344 | * create a ROM region using the default mapping window size of | |
93bf276d CLG |
345 | * the flash module. The window size is 64MB for the AST2400 |
346 | * SoC and 128MB for the AST2500 SoC, which is twice as big as | |
347 | * needed by the flash modules of the Aspeed machines. | |
d769a1da | 348 | */ |
1a15311a | 349 | if (ASPEED_MACHINE(machine)->mmio_exec) { |
f489960d | 350 | memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom", |
1a15311a CLG |
351 | &fl->mmio, 0, fl->size); |
352 | memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, | |
353 | boot_rom); | |
354 | } else { | |
f489960d | 355 | memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom", |
1a15311a CLG |
356 | fl->size, &error_abort); |
357 | memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR, | |
358 | boot_rom); | |
359 | write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort); | |
360 | } | |
d769a1da CLG |
361 | } |
362 | ||
b7f1a0cb | 363 | if (machine->kernel_filename && sc->num_cpus > 1) { |
9bb6d140 JS |
364 | /* With no u-boot we must set up a boot stub for the secondary CPU */ |
365 | MemoryRegion *smpboot = g_new(MemoryRegion, 1); | |
f489960d | 366 | memory_region_init_ram(smpboot, NULL, "aspeed.smpboot", |
9bb6d140 JS |
367 | 0x80, &error_abort); |
368 | memory_region_add_subregion(get_system_memory(), | |
369 | AST_SMP_MAILBOX_BASE, smpboot); | |
370 | ||
371 | aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot; | |
372 | aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary; | |
373 | aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE; | |
374 | } | |
375 | ||
74fb1f38 | 376 | aspeed_board_binfo.ram_size = ram_size; |
347df6f8 | 377 | aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM]; |
b7f1a0cb | 378 | aspeed_board_binfo.nb_cpus = sc->num_cpus; |
e1ad9bc4 | 379 | |
baa4732b CLG |
380 | if (amc->i2c_init) { |
381 | amc->i2c_init(bmc); | |
2cf6cb50 CLG |
382 | } |
383 | ||
0e2c24c6 | 384 | for (i = 0; i < bmc->soc.sdhci.num_slots; i++) { |
a29e3e12 AJ |
385 | sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD)); |
386 | } | |
2bea128c | 387 | |
a29e3e12 AJ |
388 | if (bmc->soc.emmc.num_slots) { |
389 | sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD)); | |
2bea128c EJ |
390 | } |
391 | ||
2744ece8 | 392 | arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo); |
74fb1f38 | 393 | } |
b033271f | 394 | |
612b219a | 395 | static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) |
2cf6cb50 CLG |
396 | { |
397 | AspeedSoCState *soc = &bmc->soc; | |
a87e81b9 | 398 | DeviceState *dev; |
3d165f12 | 399 | uint8_t *eeprom_buf = g_malloc0(32 * 1024); |
2cf6cb50 CLG |
400 | |
401 | /* The palmetto platform expects a ds3231 RTC but a ds1338 is | |
402 | * enough to provide basic RTC features. Alarms will be missing */ | |
1373b15b | 403 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); |
a87e81b9 | 404 | |
7a204cbd | 405 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, |
3d165f12 CLG |
406 | eeprom_buf); |
407 | ||
a87e81b9 | 408 | /* add a TMP423 temperature sensor */ |
1373b15b PMD |
409 | dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), |
410 | "tmp423", 0x4c)); | |
5325cc34 MA |
411 | object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); |
412 | object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); | |
413 | object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); | |
414 | object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); | |
2cf6cb50 CLG |
415 | } |
416 | ||
612b219a | 417 | static void ast2500_evb_i2c_init(AspeedMachineState *bmc) |
2cf6cb50 CLG |
418 | { |
419 | AspeedSoCState *soc = &bmc->soc; | |
3d165f12 CLG |
420 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); |
421 | ||
7a204cbd | 422 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50, |
3d165f12 | 423 | eeprom_buf); |
2cf6cb50 CLG |
424 | |
425 | /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ | |
1373b15b | 426 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), |
044475f3 | 427 | TYPE_TMP105, 0x4d); |
6c4567c7 CLG |
428 | |
429 | /* The AST2500 EVB does not have an RTC. Let's pretend that one is | |
430 | * plugged on the I2C bus header */ | |
1373b15b | 431 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); |
2cf6cb50 CLG |
432 | } |
433 | ||
612b219a | 434 | static void ast2600_evb_i2c_init(AspeedMachineState *bmc) |
ccc2c418 CLG |
435 | { |
436 | /* Start with some devices on our I2C busses */ | |
437 | ast2500_evb_i2c_init(bmc); | |
438 | } | |
439 | ||
612b219a | 440 | static void romulus_bmc_i2c_init(AspeedMachineState *bmc) |
6c4567c7 CLG |
441 | { |
442 | AspeedSoCState *soc = &bmc->soc; | |
443 | ||
444 | /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is | |
445 | * good enough */ | |
1373b15b | 446 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); |
6c4567c7 CLG |
447 | } |
448 | ||
612b219a | 449 | static void swift_bmc_i2c_init(AspeedMachineState *bmc) |
aae7a18d AK |
450 | { |
451 | AspeedSoCState *soc = &bmc->soc; | |
452 | ||
1373b15b | 453 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60); |
aae7a18d AK |
454 | |
455 | /* The swift board expects a TMP275 but a TMP105 is compatible */ | |
1373b15b | 456 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48); |
aae7a18d | 457 | /* The swift board expects a pca9551 but a pca9552 is compatible */ |
1373b15b | 458 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60); |
aae7a18d AK |
459 | |
460 | /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */ | |
1373b15b PMD |
461 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32); |
462 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); | |
aae7a18d | 463 | |
1373b15b | 464 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); |
aae7a18d | 465 | /* The swift board expects a pca9539 but a pca9552 is compatible */ |
1373b15b | 466 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74); |
aae7a18d | 467 | |
1373b15b | 468 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); |
aae7a18d | 469 | /* The swift board expects a pca9539 but a pca9552 is compatible */ |
1373b15b | 470 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552", |
aae7a18d AK |
471 | 0x74); |
472 | ||
473 | /* The swift board expects a TMP275 but a TMP105 is compatible */ | |
1373b15b PMD |
474 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48); |
475 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a); | |
aae7a18d AK |
476 | } |
477 | ||
612b219a | 478 | static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc) |
143b040f PW |
479 | { |
480 | AspeedSoCState *soc = &bmc->soc; | |
481 | ||
482 | /* bus 2 : */ | |
1373b15b PMD |
483 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48); |
484 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49); | |
143b040f PW |
485 | /* bus 2 : pca9546 @ 0x73 */ |
486 | ||
487 | /* bus 3 : pca9548 @ 0x70 */ | |
488 | ||
489 | /* bus 4 : */ | |
490 | uint8_t *eeprom4_54 = g_malloc0(8 * 1024); | |
7a204cbd | 491 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54, |
143b040f PW |
492 | eeprom4_54); |
493 | /* PCA9539 @ 0x76, but PCA9552 is compatible */ | |
1373b15b | 494 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76); |
143b040f | 495 | /* PCA9539 @ 0x77, but PCA9552 is compatible */ |
1373b15b | 496 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77); |
143b040f PW |
497 | |
498 | /* bus 6 : */ | |
1373b15b PMD |
499 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48); |
500 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49); | |
143b040f PW |
501 | /* bus 6 : pca9546 @ 0x73 */ |
502 | ||
503 | /* bus 8 : */ | |
504 | uint8_t *eeprom8_56 = g_malloc0(8 * 1024); | |
7a204cbd | 505 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56, |
143b040f | 506 | eeprom8_56); |
1373b15b PMD |
507 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60); |
508 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); | |
143b040f PW |
509 | /* bus 8 : adc128d818 @ 0x1d */ |
510 | /* bus 8 : adc128d818 @ 0x1f */ | |
511 | ||
512 | /* | |
513 | * bus 13 : pca9548 @ 0x71 | |
514 | * - channel 3: | |
515 | * - tmm421 @ 0x4c | |
516 | * - tmp421 @ 0x4e | |
517 | * - tmp421 @ 0x4f | |
518 | */ | |
519 | ||
520 | } | |
521 | ||
612b219a | 522 | static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc) |
62c2c2eb CLG |
523 | { |
524 | AspeedSoCState *soc = &bmc->soc; | |
3d165f12 | 525 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); |
15ce12cf | 526 | DeviceState *dev; |
62c2c2eb | 527 | |
63ceb818 CLG |
528 | /* Bus 3: TODO bmp280@77 */ |
529 | /* Bus 3: TODO max31785@52 */ | |
530 | /* Bus 3: TODO dps310@76 */ | |
db437ca6 | 531 | dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); |
15ce12cf | 532 | qdev_prop_set_string(dev, "description", "pca1"); |
2616f572 PMD |
533 | i2c_slave_realize_and_unref(I2C_SLAVE(dev), |
534 | aspeed_i2c_get_bus(&soc->i2c, 3), | |
535 | &error_fatal); | |
8c9a61d7 | 536 | |
1373b15b PMD |
537 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c); |
538 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c); | |
62c2c2eb CLG |
539 | |
540 | /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ | |
1373b15b | 541 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105, |
044475f3 | 542 | 0x4a); |
6c4567c7 CLG |
543 | |
544 | /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is | |
545 | * good enough */ | |
1373b15b | 546 | i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32); |
3d165f12 | 547 | |
7a204cbd | 548 | smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51, |
3d165f12 | 549 | eeprom_buf); |
db437ca6 | 550 | dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60)); |
15ce12cf | 551 | qdev_prop_set_string(dev, "description", "pca0"); |
2616f572 PMD |
552 | i2c_slave_realize_and_unref(I2C_SLAVE(dev), |
553 | aspeed_i2c_get_bus(&soc->i2c, 11), | |
554 | &error_fatal); | |
63ceb818 | 555 | /* Bus 11: TODO ucd90160@64 */ |
62c2c2eb CLG |
556 | } |
557 | ||
1a15311a CLG |
558 | static bool aspeed_get_mmio_exec(Object *obj, Error **errp) |
559 | { | |
560 | return ASPEED_MACHINE(obj)->mmio_exec; | |
561 | } | |
562 | ||
563 | static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp) | |
564 | { | |
565 | ASPEED_MACHINE(obj)->mmio_exec = value; | |
566 | } | |
567 | ||
568 | static void aspeed_machine_instance_init(Object *obj) | |
569 | { | |
570 | ASPEED_MACHINE(obj)->mmio_exec = false; | |
571 | } | |
572 | ||
573 | static void aspeed_machine_class_props_init(ObjectClass *oc) | |
574 | { | |
575 | object_class_property_add_bool(oc, "execute-in-place", | |
576 | aspeed_get_mmio_exec, | |
d2623129 | 577 | aspeed_set_mmio_exec); |
1a15311a | 578 | object_class_property_set_description(oc, "execute-in-place", |
7eecec7d | 579 | "boot directly from CE0 flash device"); |
1a15311a CLG |
580 | } |
581 | ||
b7f1a0cb CLG |
582 | static int aspeed_soc_num_cpus(const char *soc_name) |
583 | { | |
584 | AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name)); | |
585 | return sc->num_cpus; | |
586 | } | |
587 | ||
fca9ca1b | 588 | static void aspeed_machine_class_init(ObjectClass *oc, void *data) |
62c2c2eb CLG |
589 | { |
590 | MachineClass *mc = MACHINE_CLASS(oc); | |
d3bad7e7 | 591 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); |
62c2c2eb | 592 | |
fca9ca1b | 593 | mc->init = aspeed_machine_init; |
62c2c2eb CLG |
594 | mc->no_floppy = 1; |
595 | mc->no_cdrom = 1; | |
596 | mc->no_parallel = 1; | |
afcbaed6 | 597 | mc->default_ram_id = "ram"; |
d3bad7e7 | 598 | amc->macs_mask = ASPEED_MAC0_ON; |
1a15311a CLG |
599 | |
600 | aspeed_machine_class_props_init(oc); | |
62c2c2eb CLG |
601 | } |
602 | ||
baa4732b CLG |
603 | static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) |
604 | { | |
605 | MachineClass *mc = MACHINE_CLASS(oc); | |
606 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
607 | ||
608 | mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)"; | |
609 | amc->soc_name = "ast2400-a1"; | |
610 | amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1; | |
611 | amc->fmc_model = "n25q256a"; | |
612 | amc->spi_model = "mx25l25635e"; | |
613 | amc->num_cs = 1; | |
614 | amc->i2c_init = palmetto_bmc_i2c_init; | |
615 | mc->default_ram_size = 256 * MiB; | |
b7f1a0cb CLG |
616 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
617 | aspeed_soc_num_cpus(amc->soc_name); | |
baa4732b CLG |
618 | }; |
619 | ||
40a38df5 ES |
620 | static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, |
621 | void *data) | |
622 | { | |
623 | MachineClass *mc = MACHINE_CLASS(oc); | |
624 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
625 | ||
626 | mc->desc = "Supermicro X11 BMC (ARM926EJ-S)"; | |
627 | amc->soc_name = "ast2400-a1"; | |
628 | amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1; | |
629 | amc->fmc_model = "mx25l25635e"; | |
630 | amc->spi_model = "mx25l25635e"; | |
631 | amc->num_cs = 1; | |
632 | amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; | |
633 | amc->i2c_init = palmetto_bmc_i2c_init; | |
634 | mc->default_ram_size = 256 * MiB; | |
635 | } | |
636 | ||
baa4732b CLG |
637 | static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data) |
638 | { | |
639 | MachineClass *mc = MACHINE_CLASS(oc); | |
640 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
641 | ||
642 | mc->desc = "Aspeed AST2500 EVB (ARM1176)"; | |
643 | amc->soc_name = "ast2500-a1"; | |
644 | amc->hw_strap1 = AST2500_EVB_HW_STRAP1; | |
645 | amc->fmc_model = "w25q256"; | |
646 | amc->spi_model = "mx25l25635e"; | |
647 | amc->num_cs = 1; | |
648 | amc->i2c_init = ast2500_evb_i2c_init; | |
649 | mc->default_ram_size = 512 * MiB; | |
b7f1a0cb CLG |
650 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
651 | aspeed_soc_num_cpus(amc->soc_name); | |
baa4732b CLG |
652 | }; |
653 | ||
654 | static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data) | |
655 | { | |
656 | MachineClass *mc = MACHINE_CLASS(oc); | |
657 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
658 | ||
659 | mc->desc = "OpenPOWER Romulus BMC (ARM1176)"; | |
660 | amc->soc_name = "ast2500-a1"; | |
661 | amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1; | |
662 | amc->fmc_model = "n25q256a"; | |
663 | amc->spi_model = "mx66l1g45g"; | |
664 | amc->num_cs = 2; | |
665 | amc->i2c_init = romulus_bmc_i2c_init; | |
666 | mc->default_ram_size = 512 * MiB; | |
b7f1a0cb CLG |
667 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
668 | aspeed_soc_num_cpus(amc->soc_name); | |
fca9ca1b CLG |
669 | }; |
670 | ||
143b040f PW |
671 | static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data) |
672 | { | |
673 | MachineClass *mc = MACHINE_CLASS(oc); | |
674 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
675 | ||
676 | mc->desc = "OCP SonoraPass BMC (ARM1176)"; | |
677 | amc->soc_name = "ast2500-a1"; | |
678 | amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1; | |
679 | amc->fmc_model = "mx66l1g45g"; | |
680 | amc->spi_model = "mx66l1g45g"; | |
681 | amc->num_cs = 2; | |
682 | amc->i2c_init = sonorapass_bmc_i2c_init; | |
683 | mc->default_ram_size = 512 * MiB; | |
b7f1a0cb CLG |
684 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
685 | aspeed_soc_num_cpus(amc->soc_name); | |
143b040f PW |
686 | }; |
687 | ||
baa4732b CLG |
688 | static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) |
689 | { | |
690 | MachineClass *mc = MACHINE_CLASS(oc); | |
691 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
692 | ||
693 | mc->desc = "OpenPOWER Swift BMC (ARM1176)"; | |
694 | amc->soc_name = "ast2500-a1"; | |
695 | amc->hw_strap1 = SWIFT_BMC_HW_STRAP1; | |
696 | amc->fmc_model = "mx66l1g45g"; | |
697 | amc->spi_model = "mx66l1g45g"; | |
698 | amc->num_cs = 2; | |
699 | amc->i2c_init = swift_bmc_i2c_init; | |
700 | mc->default_ram_size = 512 * MiB; | |
b7f1a0cb CLG |
701 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
702 | aspeed_soc_num_cpus(amc->soc_name); | |
baa4732b CLG |
703 | }; |
704 | ||
705 | static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) | |
706 | { | |
707 | MachineClass *mc = MACHINE_CLASS(oc); | |
708 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
709 | ||
710 | mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)"; | |
711 | amc->soc_name = "ast2500-a1"; | |
712 | amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1; | |
713 | amc->fmc_model = "mx25l25635e"; | |
714 | amc->spi_model = "mx66l1g45g"; | |
715 | amc->num_cs = 2; | |
716 | amc->i2c_init = witherspoon_bmc_i2c_init; | |
717 | mc->default_ram_size = 512 * MiB; | |
b7f1a0cb CLG |
718 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
719 | aspeed_soc_num_cpus(amc->soc_name); | |
baa4732b CLG |
720 | }; |
721 | ||
722 | static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data) | |
723 | { | |
724 | MachineClass *mc = MACHINE_CLASS(oc); | |
725 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
726 | ||
727 | mc->desc = "Aspeed AST2600 EVB (Cortex A7)"; | |
7582591a | 728 | amc->soc_name = "ast2600-a1"; |
baa4732b CLG |
729 | amc->hw_strap1 = AST2600_EVB_HW_STRAP1; |
730 | amc->hw_strap2 = AST2600_EVB_HW_STRAP2; | |
731 | amc->fmc_model = "w25q512jv"; | |
732 | amc->spi_model = "mx66u51235f"; | |
733 | amc->num_cs = 1; | |
d3bad7e7 | 734 | amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON; |
baa4732b CLG |
735 | amc->i2c_init = ast2600_evb_i2c_init; |
736 | mc->default_ram_size = 1 * GiB; | |
b7f1a0cb CLG |
737 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
738 | aspeed_soc_num_cpus(amc->soc_name); | |
baa4732b CLG |
739 | }; |
740 | ||
63ceb818 CLG |
741 | static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data) |
742 | { | |
743 | MachineClass *mc = MACHINE_CLASS(oc); | |
744 | AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); | |
745 | ||
7582591a JS |
746 | mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)"; |
747 | amc->soc_name = "ast2600-a1"; | |
63ceb818 CLG |
748 | amc->hw_strap1 = TACOMA_BMC_HW_STRAP1; |
749 | amc->hw_strap2 = TACOMA_BMC_HW_STRAP2; | |
750 | amc->fmc_model = "mx66l1g45g"; | |
751 | amc->spi_model = "mx66l1g45g"; | |
752 | amc->num_cs = 2; | |
d3bad7e7 | 753 | amc->macs_mask = ASPEED_MAC2_ON; |
63ceb818 CLG |
754 | amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */ |
755 | mc->default_ram_size = 1 * GiB; | |
b7f1a0cb CLG |
756 | mc->default_cpus = mc->min_cpus = mc->max_cpus = |
757 | aspeed_soc_num_cpus(amc->soc_name); | |
63ceb818 CLG |
758 | }; |
759 | ||
baa4732b | 760 | static const TypeInfo aspeed_machine_types[] = { |
fca9ca1b | 761 | { |
baa4732b CLG |
762 | .name = MACHINE_TYPE_NAME("palmetto-bmc"), |
763 | .parent = TYPE_ASPEED_MACHINE, | |
764 | .class_init = aspeed_machine_palmetto_class_init, | |
40a38df5 ES |
765 | }, { |
766 | .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), | |
767 | .parent = TYPE_ASPEED_MACHINE, | |
768 | .class_init = aspeed_machine_supermicrox11_bmc_class_init, | |
fca9ca1b | 769 | }, { |
baa4732b CLG |
770 | .name = MACHINE_TYPE_NAME("ast2500-evb"), |
771 | .parent = TYPE_ASPEED_MACHINE, | |
772 | .class_init = aspeed_machine_ast2500_evb_class_init, | |
fca9ca1b | 773 | }, { |
baa4732b CLG |
774 | .name = MACHINE_TYPE_NAME("romulus-bmc"), |
775 | .parent = TYPE_ASPEED_MACHINE, | |
776 | .class_init = aspeed_machine_romulus_class_init, | |
aae7a18d | 777 | }, { |
baa4732b CLG |
778 | .name = MACHINE_TYPE_NAME("swift-bmc"), |
779 | .parent = TYPE_ASPEED_MACHINE, | |
780 | .class_init = aspeed_machine_swift_class_init, | |
143b040f PW |
781 | }, { |
782 | .name = MACHINE_TYPE_NAME("sonorapass-bmc"), | |
783 | .parent = TYPE_ASPEED_MACHINE, | |
784 | .class_init = aspeed_machine_sonorapass_class_init, | |
fca9ca1b | 785 | }, { |
baa4732b CLG |
786 | .name = MACHINE_TYPE_NAME("witherspoon-bmc"), |
787 | .parent = TYPE_ASPEED_MACHINE, | |
788 | .class_init = aspeed_machine_witherspoon_class_init, | |
ccc2c418 | 789 | }, { |
baa4732b CLG |
790 | .name = MACHINE_TYPE_NAME("ast2600-evb"), |
791 | .parent = TYPE_ASPEED_MACHINE, | |
792 | .class_init = aspeed_machine_ast2600_evb_class_init, | |
63ceb818 CLG |
793 | }, { |
794 | .name = MACHINE_TYPE_NAME("tacoma-bmc"), | |
795 | .parent = TYPE_ASPEED_MACHINE, | |
796 | .class_init = aspeed_machine_tacoma_class_init, | |
baa4732b CLG |
797 | }, { |
798 | .name = TYPE_ASPEED_MACHINE, | |
799 | .parent = TYPE_MACHINE, | |
888b2b03 | 800 | .instance_size = sizeof(AspeedMachineState), |
1a15311a | 801 | .instance_init = aspeed_machine_instance_init, |
baa4732b CLG |
802 | .class_size = sizeof(AspeedMachineClass), |
803 | .class_init = aspeed_machine_class_init, | |
804 | .abstract = true, | |
fca9ca1b | 805 | } |
baa4732b | 806 | }; |
74fb1f38 | 807 | |
baa4732b | 808 | DEFINE_TYPES(aspeed_machine_types) |