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i386: kvm: extend kvm_{get, put}_vcpu_events to support pending triple fault
[mirror_qemu.git] / target / i386 / kvm / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
8efc4e51 16#include "qapi/qapi-events-run-state.h"
da34e65c 17#include "qapi/error.h"
05330448 18#include <sys/ioctl.h>
25d2e361 19#include <sys/utsname.h>
19db68ca 20#include <sys/syscall.h>
05330448
AL		 21
22#include <linux/kvm.h>
1814eab6 23#include "standard-headers/asm-x86/kvm_para.h"
05330448 24
33c11879 25#include "cpu.h"
f5cc5a5c 26#include "host-cpu.h"
9c17d615 27#include "sysemu/sysemu.h"
b3946626 28#include "sysemu/hw_accel.h"
6410848b 29#include "sysemu/kvm_int.h"
54d31236 30#include "sysemu/runstate.h"
1d31f66b 31#include "kvm_i386.h"
93777de3 32#include "sev.h"
50efe82c 33#include "hyperv.h"
5e953812 34#include "hyperv-proto.h"
50efe82c 35
022c62cb 36#include "exec/gdbstub.h"
1de7afc9 37#include "qemu/host-utils.h"
db725815 38#include "qemu/main-loop.h"
1de7afc9 39#include "qemu/config-file.h"
1c4a55db 40#include "qemu/error-report.h"
5df022cf 41#include "qemu/memalign.h"
89a289c7 42#include "hw/i386/x86.h"
0d09e41a 43#include "hw/i386/apic.h"
e0723c45
PB		 44#include "hw/i386/apic_internal.h"
45#include "hw/i386/apic-msidef.h"
8b5ed7df 46#include "hw/i386/intel_iommu.h"
e1d4fb2d 47#include "hw/i386/x86-iommu.h"
d6d059ca 48#include "hw/i386/e820_memory_layout.h"
50efe82c 49
a2cb15b0 50#include "hw/pci/pci.h"
15eafc2e 51#include "hw/pci/msi.h"
fd563564 52#include "hw/pci/msix.h"
795c40b8 53#include "migration/blocker.h"
4c663752 54#include "exec/memattrs.h"
8b5ed7df 55#include "trace.h"
05330448 56
d8701185
JD		 57#include CONFIG_DEVICES
58
05330448
AL		 59//#define DEBUG_KVM
60
61#ifdef DEBUG_KVM
8c0d577e 62#define DPRINTF(fmt, ...) \
05330448
AL		 63 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
64#else
8c0d577e 65#define DPRINTF(fmt, ...) \
05330448
AL		 66 do { } while (0)
67#endif
68
73b994f6
LA		 69/* From arch/x86/kvm/lapic.h */
70#define KVM_APIC_BUS_CYCLE_NS 1
71#define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
72
1a03675d
GC		 73#define MSR_KVM_WALL_CLOCK 0x11
74#define MSR_KVM_SYSTEM_TIME 0x12
75
d1138251
EH		 76/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
77 * 255 kvm_msr_entry structs */
78#define MSR_BUF_SIZE 4096
d71b62a1 79
420ae1fc
PB		 80static void kvm_init_msrs(X86CPU *cpu);
81
94a8d39a
JK		 82const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
83 KVM_CAP_INFO(SET_TSS_ADDR),
84 KVM_CAP_INFO(EXT_CPUID),
85 KVM_CAP_INFO(MP_STATE),
86 KVM_CAP_LAST_INFO
87};
25d2e361 88
c3a3a7d3
JK		 89static bool has_msr_star;
90static bool has_msr_hsave_pa;
c9b8f6b6 91static bool has_msr_tsc_aux;
f28558d3 92static bool has_msr_tsc_adjust;
aa82ba54 93static bool has_msr_tsc_deadline;
df67696e 94static bool has_msr_feature_control;
21e87c46 95static bool has_msr_misc_enable;
fc12d72e 96static bool has_msr_smbase;
79e9ebeb 97static bool has_msr_bndcfgs;
25d2e361 98static int lm_capable_kernel;
7bc3d711 99static bool has_msr_hv_hypercall;
f2a53c9e 100static bool has_msr_hv_crash;
744b8a94 101static bool has_msr_hv_reset;
8c145d7c 102static bool has_msr_hv_vpindex;
e9688fab 103static bool hv_vpindex_settable;
46eb8f98 104static bool has_msr_hv_runtime;
866eea9a 105static bool has_msr_hv_synic;
ff99aa64 106static bool has_msr_hv_stimer;
d72bc7f6 107static bool has_msr_hv_frequencies;
ba6a4fd9 108static bool has_msr_hv_reenlightenment;
73d24074 109static bool has_msr_hv_syndbg_options;
18cd2c17 110static bool has_msr_xss;
65087997 111static bool has_msr_umwait;
a33a2cfe 112static bool has_msr_spec_ctrl;
cabf9862 113static bool has_tsc_scale_msr;
2a9758c5 114static bool has_msr_tsx_ctrl;
cfeea0c0 115static bool has_msr_virt_ssbd;
e13713db 116static bool has_msr_smi_count;
aec5e9c3 117static bool has_msr_arch_capabs;
597360c0 118static bool has_msr_core_capabs;
20a78b02 119static bool has_msr_vmx_vmfunc;
67025148 120static bool has_msr_ucode_rev;
4a910e1f 121static bool has_msr_vmx_procbased_ctls2;
ea39f9b6 122static bool has_msr_perf_capabs;
6aa4228b 123static bool has_msr_pkrs;
b827df58 124
0b368a10
JD		 125static uint32_t has_architectural_pmu_version;
126static uint32_t num_architectural_pmu_gp_counters;
127static uint32_t num_architectural_pmu_fixed_counters;
0d894367 128
28143b40 129static int has_xsave;
e56dd3c7 130static int has_xsave2;
28143b40
TH		 131static int has_xcrs;
132static int has_pit_state2;
8f515d38 133static int has_sregs2;
fd13f23b 134static int has_exception_payload;
12f89a39 135static int has_triple_fault_event;
28143b40 136
87f8b626
AR		 137static bool has_msr_mcg_ext_ctl;
138
494e95e9 139static struct kvm_cpuid2 *cpuid_cache;
a8439be6 140static struct kvm_cpuid2 *hv_cpuid_cache;
f57bceb6 141static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 142
035d1ef2
CQ		 143#define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
144static RateLimit bus_lock_ratelimit_ctrl;
5a778a5f 145static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
035d1ef2 146
28143b40
TH		 147int kvm_has_pit_state2(void)
148{
149 return has_pit_state2;
150}
151
355023f2
PB		 152bool kvm_has_smm(void)
153{
23edf8b5 154 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
355023f2
PB		 155}
156
6053a86f
MT		 157bool kvm_has_adjust_clock_stable(void)
158{
159 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
160
c4ef867f 161 return (ret & KVM_CLOCK_TSC_STABLE);
6053a86f
MT		 162}
163
8700a984
VK		 164bool kvm_has_adjust_clock(void)
165{
166 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
167}
168
79a197ab
LA		 169bool kvm_has_exception_payload(void)
170{
171 return has_exception_payload;
172}
173
fb506e70
RK		 174static bool kvm_x2apic_api_set_flags(uint64_t flags)
175{
4f7f5893 176 KVMState *s = KVM_STATE(current_accel());
fb506e70
RK		 177
178 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
179}
180
e391c009 181#define MEMORIZE(fn, _result) \
2a138ec3 182 ({ \
2a138ec3
RK		 183 static bool _memorized; \
184 \
185 if (_memorized) { \
186 return _result; \
187 } \
188 _memorized = true; \
189 _result = fn; \
190 })
191
e391c009
IM		 192static bool has_x2apic_api;
193
194bool kvm_has_x2apic_api(void)
195{
196 return has_x2apic_api;
197}
198
fb506e70
RK		 199bool kvm_enable_x2apic(void)
200{
2a138ec3
RK		 201 return MEMORIZE(
202 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 203 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
204 has_x2apic_api);
fb506e70
RK		 205}
206
e9688fab
RK		 207bool kvm_hv_vpindex_settable(void)
208{
209 return hv_vpindex_settable;
210}
211
0fd7e098
LL		 212static int kvm_get_tsc(CPUState *cs)
213{
214 X86CPU *cpu = X86_CPU(cs);
215 CPUX86State *env = &cpu->env;
5a778a5f 216 uint64_t value;
0fd7e098
LL		 217 int ret;
218
219 if (env->tsc_valid) {
220 return 0;
221 }
222
0fd7e098
LL		 223 env->tsc_valid = !runstate_is_running();
224
5a778a5f 225 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
0fd7e098
LL		 226 if (ret < 0) {
227 return ret;
228 }
229
5a778a5f 230 env->tsc = value;
0fd7e098
LL		 231 return 0;
232}
233
14e6fe12 234static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 235{
0fd7e098
LL		 236 kvm_get_tsc(cpu);
237}
238
239void kvm_synchronize_all_tsc(void)
240{
241 CPUState *cpu;
242
243 if (kvm_enabled()) {
244 CPU_FOREACH(cpu) {
14e6fe12 245 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 246 }
247 }
248}
249
b827df58
AK		 250static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
251{
252 struct kvm_cpuid2 *cpuid;
253 int r, size;
254
255 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 256 cpuid = g_malloc0(size);
b827df58
AK		 257 cpuid->nent = max;
258 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 259 if (r == 0 && cpuid->nent >= max) {
260 r = -E2BIG;
261 }
b827df58
AK		 262 if (r < 0) {
263 if (r == -E2BIG) {
7267c094 264 g_free(cpuid);
b827df58
AK		 265 return NULL;
266 } else {
267 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
268 strerror(-r));
269 exit(1);
270 }
271 }
272 return cpuid;
273}
274
dd87f8a6
EH		 275/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
276 * for all entries.
277 */
278static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
279{
280 struct kvm_cpuid2 *cpuid;
281 int max = 1;
494e95e9
CP		 282
283 if (cpuid_cache != NULL) {
284 return cpuid_cache;
285 }
dd87f8a6
EH		 286 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
287 max *= 2;
288 }
494e95e9 289 cpuid_cache = cpuid;
dd87f8a6
EH		 290 return cpuid;
291}
292
b199c682 293static bool host_tsx_broken(void)
40e80ee4
EH		 294{
295 int family, model, stepping;\
296 char vendor[CPUID_VENDOR_SZ + 1];
297
f5cc5a5c 298 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
40e80ee4
EH		 299
300 /* Check if we are running on a Haswell host known to have broken TSX */
301 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
302 (family == 6) &&
303 ((model == 63 && stepping < 4) ||
304 model == 60 || model == 69 || model == 70);
305}
0c31b744 306
829ae2f9
EH		 307/* Returns the value for a specific register on the cpuid entry
308 */
309static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
310{
311 uint32_t ret = 0;
312 switch (reg) {
313 case R_EAX:
314 ret = entry->eax;
315 break;
316 case R_EBX:
317 ret = entry->ebx;
318 break;
319 case R_ECX:
320 ret = entry->ecx;
321 break;
322 case R_EDX:
323 ret = entry->edx;
324 break;
325 }
326 return ret;
327}
328
4fb73f1d
EH		 329/* Find matching entry for function/index on kvm_cpuid2 struct
330 */
331static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
332 uint32_t function,
333 uint32_t index)
334{
335 int i;
336 for (i = 0; i < cpuid->nent; ++i) {
337 if (cpuid->entries[i].function == function &&
338 cpuid->entries[i].index == index) {
339 return &cpuid->entries[i];
340 }
341 }
342 /* not found: */
343 return NULL;
344}
345
ba9bc59e 346uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 347 uint32_t index, int reg)
b827df58
AK		 348{
349 struct kvm_cpuid2 *cpuid;
b827df58
AK		 350 uint32_t ret = 0;
351 uint32_t cpuid_1_edx;
19db68ca 352 uint64_t bitmask;
b827df58 353
dd87f8a6 354 cpuid = get_supported_cpuid(s);
b827df58 355
4fb73f1d
EH		 356 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
357 if (entry) {
4fb73f1d 358 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 359 }
360
7b46e5ce
EH		 361 /* Fixups for the data returned by KVM, below */
362
c2acb022
EH		 363 if (function == 1 && reg == R_EDX) {
364 /* KVM before 2.6.30 misreports the following features */
365 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 366 } else if (function == 1 && reg == R_ECX) {
367 /* We can set the hypervisor flag, even if KVM does not return it on
368 * GET_SUPPORTED_CPUID
369 */
370 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 371 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
372 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
373 * and the irqchip is in the kernel.
374 */
375 if (kvm_irqchip_in_kernel() &&
376 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
377 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
378 }
41e5e76d
EH		 379
380 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
381 * without the in-kernel irqchip
382 */
383 if (!kvm_irqchip_in_kernel()) {
384 ret &= ~CPUID_EXT_X2APIC;
b827df58 385 }
2266d443
MT		 386
387 if (enable_cpu_pm) {
388 int disable_exits = kvm_check_extension(s,
389 KVM_CAP_X86_DISABLE_EXITS);
390
391 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
392 ret |= CPUID_EXT_MONITOR;
393 }
394 }
28b8e4d0
JK		 395 } else if (function == 6 && reg == R_EAX) {
396 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4 397 } else if (function == 7 && index == 0 && reg == R_EBX) {
b199c682 398 if (host_tsx_broken()) {
40e80ee4
EH		 399 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
400 }
485b1d25
EH		 401 } else if (function == 7 && index == 0 && reg == R_EDX) {
402 /*
403 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
404 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
405 * returned by KVM_GET_MSR_INDEX_LIST.
406 */
407 if (!has_msr_arch_capabs) {
408 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
409 }
19db68ca
YZ		 410 } else if (function == 0xd && index == 0 &&
411 (reg == R_EAX || reg == R_EDX)) {
3ec5ad40
PB		 412 /*
413 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
414 * features that still have to be enabled with the arch_prctl
415 * system call. QEMU needs the full value, which is retrieved
416 * with KVM_GET_DEVICE_ATTR.
417 */
19db68ca
YZ		 418 struct kvm_device_attr attr = {
419 .group = 0,
420 .attr = KVM_X86_XCOMP_GUEST_SUPP,
421 .addr = (unsigned long) &bitmask
422 };
423
424 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
425 if (!sys_attr) {
3ec5ad40 426 return ret;
19db68ca
YZ		 427 }
428
429 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
3ec5ad40
PB		 430 if (rc < 0) {
431 if (rc != -ENXIO) {
432 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
433 "error: %d", rc);
434 }
435 return ret;
19db68ca
YZ		 436 }
437 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
f98bbd83
BM		 438 } else if (function == 0x80000001 && reg == R_ECX) {
439 /*
440 * It's safe to enable TOPOEXT even if it's not returned by
441 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
442 * us to keep CPU models including TOPOEXT runnable on older kernels.
443 */
444 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 445 } else if (function == 0x80000001 && reg == R_EDX) {
446 /* On Intel, kvm returns cpuid according to the Intel spec,
447 * so add missing bits according to the AMD spec:
448 */
449 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
450 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 451 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
452 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
453 * be enabled without the in-kernel irqchip
454 */
455 if (!kvm_irqchip_in_kernel()) {
456 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
457 }
c1bb5418
DW		 458 if (kvm_irqchip_is_split()) {
459 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
460 }
be777326 461 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 462 ret |= 1U << KVM_HINTS_REALTIME;
b9bec74b 463 }
0c31b744
GC		 464
465 return ret;
bb0300dc 466}
bb0300dc 467
ede146c2 468uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
f57bceb6
RH		 469{
470 struct {
471 struct kvm_msrs info;
472 struct kvm_msr_entry entries[1];
a1834d97 473 } msr_data = {};
20a78b02
PB		 474 uint64_t value;
475 uint32_t ret, can_be_one, must_be_one;
f57bceb6
RH		 476
477 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
478 return 0;
479 }
480
481 /* Check if requested MSR is supported feature MSR */
482 int i;
483 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
484 if (kvm_feature_msrs->indices[i] == index) {
485 break;
486 }
487 if (i == kvm_feature_msrs->nmsrs) {
488 return 0; /* if the feature MSR is not supported, simply return 0 */
489 }
490
491 msr_data.info.nmsrs = 1;
492 msr_data.entries[0].index = index;
493
494 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
495 if (ret != 1) {
496 error_report("KVM get MSR (index=0x%x) feature failed, %s",
497 index, strerror(-ret));
498 exit(1);
499 }
500
20a78b02
PB		 501 value = msr_data.entries[0].data;
502 switch (index) {
503 case MSR_IA32_VMX_PROCBASED_CTLS2:
4a910e1f
VK		 504 if (!has_msr_vmx_procbased_ctls2) {
505 /* KVM forgot to add these bits for some time, do this ourselves. */
506 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
507 CPUID_XSAVE_XSAVES) {
508 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
509 }
510 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
511 CPUID_EXT_RDRAND) {
512 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
513 }
514 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
515 CPUID_7_0_EBX_INVPCID) {
516 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
517 }
518 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
519 CPUID_7_0_EBX_RDSEED) {
520 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
521 }
522 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
523 CPUID_EXT2_RDTSCP) {
524 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
525 }
048c9516
PB		 526 }
527 /* fall through */
20a78b02
PB		 528 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
529 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
530 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
531 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
532 /*
533 * Return true for bits that can be one, but do not have to be one.
534 * The SDM tells us which bits could have a "must be one" setting,
535 * so we can do the opposite transformation in make_vmx_msr_value.
536 */
537 must_be_one = (uint32_t)value;
538 can_be_one = (uint32_t)(value >> 32);
539 return can_be_one & ~must_be_one;
540
541 default:
542 return value;
543 }
f57bceb6
RH		 544}
545
e7701825
MT		 546static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
547 int *max_banks)
548{
549 int r;
550
14a09518 551 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 552 if (r > 0) {
553 *max_banks = r;
554 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
555 }
556 return -ENOSYS;
557}
558
bee615d4 559static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 560{
87f8b626 561 CPUState *cs = CPU(cpu);
bee615d4 562 CPUX86State *env = &cpu->env;
c34d440a
JK		 563 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
564 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
565 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 566 int flags = 0;
e7701825 567
c34d440a
JK		 568 if (code == BUS_MCEERR_AR) {
569 status |= MCI_STATUS_AR | 0x134;
cb48748a 570 mcg_status |= MCG_STATUS_RIPV | MCG_STATUS_EIPV;
c34d440a
JK		 571 } else {
572 status |= 0xc0;
573 mcg_status |= MCG_STATUS_RIPV;
419fb20a 574 }
87f8b626
AR		 575
576 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
577 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
578 * guest kernel back into env->mcg_ext_ctl.
579 */
580 cpu_synchronize_state(cs);
581 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
582 mcg_status |= MCG_STATUS_LMCE;
583 flags = 0;
584 }
585
8c5cf3b6 586 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 587 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 588}
419fb20a 589
8efc4e51
ZP		 590static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
591{
592 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
593
594 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
595 &mff);
596}
597
73284563 598static void hardware_memory_error(void *host_addr)
419fb20a 599{
8efc4e51 600 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
73284563 601 error_report("QEMU got Hardware memory error at addr %p", host_addr);
419fb20a
JK		 602 exit(1);
603}
604
2ae41db2 605void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 606{
20d695a9
AF		 607 X86CPU *cpu = X86_CPU(c);
608 CPUX86State *env = &cpu->env;
419fb20a 609 ram_addr_t ram_addr;
a8170e5e 610 hwaddr paddr;
419fb20a 611
4d39892c
PB		 612 /* If we get an action required MCE, it has been injected by KVM
613 * while the VM was running. An action optional MCE instead should
614 * be coming from the main thread, which qemu_init_sigbus identifies
615 * as the "early kill" thread.
616 */
a16fc07e 617 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 618
20e0ff59 619 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 620 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 621 if (ram_addr != RAM_ADDR_INVALID &&
622 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
623 kvm_hwpoison_page_add(ram_addr);
624 kvm_mce_inject(cpu, paddr, code);
73284563
MS		 625
626 /*
627 * Use different logging severity based on error type.
628 * If there is additional MCE reporting on the hypervisor, QEMU VA
629 * could be another source to identify the PA and MCE details.
630 */
631 if (code == BUS_MCEERR_AR) {
632 error_report("Guest MCE Memory Error at QEMU addr %p and "
633 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
634 addr, paddr, "BUS_MCEERR_AR");
635 } else {
636 warn_report("Guest MCE Memory Error at QEMU addr %p and "
637 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
638 addr, paddr, "BUS_MCEERR_AO");
639 }
640
2ae41db2 641 return;
419fb20a 642 }
20e0ff59 643
73284563
MS		 644 if (code == BUS_MCEERR_AO) {
645 warn_report("Hardware memory error at addr %p of type %s "
646 "for memory used by QEMU itself instead of guest system!",
647 addr, "BUS_MCEERR_AO");
648 }
419fb20a 649 }
20e0ff59
PB		 650
651 if (code == BUS_MCEERR_AR) {
73284563 652 hardware_memory_error(addr);
20e0ff59
PB		 653 }
654
8efc4e51
ZP		 655 /* Hope we are lucky for AO MCE, just notify a event */
656 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
419fb20a
JK		 657}
658
fd13f23b
LA		 659static void kvm_reset_exception(CPUX86State *env)
660{
661 env->exception_nr = -1;
662 env->exception_pending = 0;
663 env->exception_injected = 0;
664 env->exception_has_payload = false;
665 env->exception_payload = 0;
666}
667
668static void kvm_queue_exception(CPUX86State *env,
669 int32_t exception_nr,
670 uint8_t exception_has_payload,
671 uint64_t exception_payload)
672{
673 assert(env->exception_nr == -1);
674 assert(!env->exception_pending);
675 assert(!env->exception_injected);
676 assert(!env->exception_has_payload);
677
678 env->exception_nr = exception_nr;
679
680 if (has_exception_payload) {
681 env->exception_pending = 1;
682
683 env->exception_has_payload = exception_has_payload;
684 env->exception_payload = exception_payload;
685 } else {
686 env->exception_injected = 1;
687
688 if (exception_nr == EXCP01_DB) {
689 assert(exception_has_payload);
690 env->dr[6] = exception_payload;
691 } else if (exception_nr == EXCP0E_PAGE) {
692 assert(exception_has_payload);
693 env->cr[2] = exception_payload;
694 } else {
695 assert(!exception_has_payload);
696 }
697 }
698}
699
1bc22652 700static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 701{
1bc22652
AF		 702 CPUX86State *env = &cpu->env;
703
fd13f23b 704 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 705 unsigned int bank, bank_num = env->mcg_cap & 0xff;
706 struct kvm_x86_mce mce;
707
fd13f23b 708 kvm_reset_exception(env);
ab443475
JK		 709
710 /*
711 * There must be at least one bank in use if an MCE is pending.
712 * Find it and use its values for the event injection.
713 */
714 for (bank = 0; bank < bank_num; bank++) {
715 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
716 break;
717 }
718 }
719 assert(bank < bank_num);
720
721 mce.bank = bank;
722 mce.status = env->mce_banks[bank * 4 + 1];
723 mce.mcg_status = env->mcg_status;
724 mce.addr = env->mce_banks[bank * 4 + 2];
725 mce.misc = env->mce_banks[bank * 4 + 3];
726
1bc22652 727 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 728 }
ab443475
JK		 729 return 0;
730}
731
538f0497 732static void cpu_update_state(void *opaque, bool running, RunState state)
b8cc45d6 733{
317ac620 734 CPUX86State *env = opaque;
b8cc45d6
GC		 735
736 if (running) {
737 env->tsc_valid = false;
738 }
739}
740
83b17af5 741unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 742{
83b17af5 743 X86CPU *cpu = X86_CPU(cs);
7e72a45c 744 return cpu->apic_id;
b164e48e
EH		 745}
746
92067bf4
IM		 747#ifndef KVM_CPUID_SIGNATURE_NEXT
748#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
749#endif
750
92067bf4
IM		 751static bool hyperv_enabled(X86CPU *cpu)
752{
5aa9ef5e 753 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
f701c082 754 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
e48ddcc6 755 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 756}
757
74aaddc6
MT		 758/*
759 * Check whether target_freq is within conservative
760 * ntp correctable bounds (250ppm) of freq
761 */
762static inline bool freq_within_bounds(int freq, int target_freq)
763{
764 int max_freq = freq + (freq * 250 / 1000000);
765 int min_freq = freq - (freq * 250 / 1000000);
766
767 if (target_freq >= min_freq && target_freq <= max_freq) {
768 return true;
769 }
770
771 return false;
772}
773
5031283d
HZ		 774static int kvm_arch_set_tsc_khz(CPUState *cs)
775{
776 X86CPU *cpu = X86_CPU(cs);
777 CPUX86State *env = &cpu->env;
74aaddc6
MT		 778 int r, cur_freq;
779 bool set_ioctl = false;
5031283d
HZ		 780
781 if (!env->tsc_khz) {
782 return 0;
783 }
784
74aaddc6
MT		 785 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
786 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
787
788 /*
789 * If TSC scaling is supported, attempt to set TSC frequency.
790 */
791 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
792 set_ioctl = true;
793 }
794
795 /*
796 * If desired TSC frequency is within bounds of NTP correction,
797 * attempt to set TSC frequency.
798 */
799 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
800 set_ioctl = true;
801 }
802
803 r = set_ioctl ?
5031283d
HZ		 804 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
805 -ENOTSUP;
74aaddc6 806
5031283d
HZ		 807 if (r < 0) {
808 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
809 * TSC frequency doesn't match the one we want.
810 */
74aaddc6
MT		 811 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
812 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
813 -ENOTSUP;
5031283d 814 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 815 warn_report("TSC frequency mismatch between "
816 "VM (%" PRId64 " kHz) and host (%d kHz), "
817 "and TSC scaling unavailable",
818 env->tsc_khz, cur_freq);
5031283d
HZ		 819 return r;
820 }
821 }
822
823 return 0;
824}
825
4bb95b82
LP		 826static bool tsc_is_stable_and_known(CPUX86State *env)
827{
828 if (!env->tsc_khz) {
829 return false;
830 }
831 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
832 || env->user_tsc_khz;
833}
834
7110fe56
VK		 835#define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
836
6760bd20
VK		 837static struct {
838 const char *desc;
839 struct {
061817a7
VK		 840 uint32_t func;
841 int reg;
6760bd20
VK		 842 uint32_t bits;
843 } flags[2];
c6861930 844 uint64_t dependencies;
6760bd20
VK		 845} kvm_hyperv_properties[] = {
846 [HYPERV_FEAT_RELAXED] = {
847 .desc = "relaxed timing (hv-relaxed)",
848 .flags = {
061817a7 849 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 850 .bits = HV_RELAXED_TIMING_RECOMMENDED}
851 }
852 },
853 [HYPERV_FEAT_VAPIC] = {
854 .desc = "virtual APIC (hv-vapic)",
855 .flags = {
061817a7 856 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
05071629 857 .bits = HV_APIC_ACCESS_AVAILABLE}
6760bd20
VK		 858 }
859 },
860 [HYPERV_FEAT_TIME] = {
861 .desc = "clocksources (hv-time)",
862 .flags = {
061817a7 863 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
b26f68c3 864 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
6760bd20
VK		 865 }
866 },
867 [HYPERV_FEAT_CRASH] = {
868 .desc = "crash MSRs (hv-crash)",
869 .flags = {
061817a7 870 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 871 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
872 }
873 },
874 [HYPERV_FEAT_RESET] = {
875 .desc = "reset MSR (hv-reset)",
876 .flags = {
061817a7 877 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 878 .bits = HV_RESET_AVAILABLE}
879 }
880 },
881 [HYPERV_FEAT_VPINDEX] = {
882 .desc = "VP_INDEX MSR (hv-vpindex)",
883 .flags = {
061817a7 884 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 885 .bits = HV_VP_INDEX_AVAILABLE}
886 }
887 },
888 [HYPERV_FEAT_RUNTIME] = {
889 .desc = "VP_RUNTIME MSR (hv-runtime)",
890 .flags = {
061817a7 891 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 892 .bits = HV_VP_RUNTIME_AVAILABLE}
893 }
894 },
895 [HYPERV_FEAT_SYNIC] = {
896 .desc = "synthetic interrupt controller (hv-synic)",
897 .flags = {
061817a7 898 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 899 .bits = HV_SYNIC_AVAILABLE}
900 }
901 },
902 [HYPERV_FEAT_STIMER] = {
903 .desc = "synthetic timers (hv-stimer)",
904 .flags = {
061817a7 905 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 906 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 907 },
908 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 909 },
910 [HYPERV_FEAT_FREQUENCIES] = {
911 .desc = "frequency MSRs (hv-frequencies)",
912 .flags = {
061817a7 913 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 914 .bits = HV_ACCESS_FREQUENCY_MSRS},
061817a7 915 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 916 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
917 }
918 },
919 [HYPERV_FEAT_REENLIGHTENMENT] = {
920 .desc = "reenlightenment MSRs (hv-reenlightenment)",
921 .flags = {
061817a7 922 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 923 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
924 }
925 },
926 [HYPERV_FEAT_TLBFLUSH] = {
927 .desc = "paravirtualized TLB flush (hv-tlbflush)",
928 .flags = {
061817a7 929 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 930 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
931 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 932 },
933 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 934 },
935 [HYPERV_FEAT_EVMCS] = {
936 .desc = "enlightened VMCS (hv-evmcs)",
937 .flags = {
061817a7 938 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20 939 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 940 },
941 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 942 },
943 [HYPERV_FEAT_IPI] = {
944 .desc = "paravirtualized IPI (hv-ipi)",
945 .flags = {
061817a7 946 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 947 .bits = HV_CLUSTER_IPI_RECOMMENDED |
948 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 949 },
950 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 951 },
128531d9
VK		 952 [HYPERV_FEAT_STIMER_DIRECT] = {
953 .desc = "direct mode synthetic timers (hv-stimer-direct)",
954 .flags = {
061817a7 955 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
128531d9
VK		 956 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
957 },
958 .dependencies = BIT(HYPERV_FEAT_STIMER)
959 },
e1f9a8e8
VK		 960 [HYPERV_FEAT_AVIC] = {
961 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
962 .flags = {
963 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
964 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
965 }
966 },
d8701185 967#ifdef CONFIG_SYNDBG
73d24074
JD		 968 [HYPERV_FEAT_SYNDBG] = {
969 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)",
970 .flags = {
971 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
972 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE}
973 },
974 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED)
975 },
d8701185 976#endif
869840d2
VK		 977 [HYPERV_FEAT_MSR_BITMAP] = {
978 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)",
979 .flags = {
980 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
981 .bits = HV_NESTED_MSR_BITMAP}
982 }
983 },
9411e8b6
VK		 984 [HYPERV_FEAT_XMM_INPUT] = {
985 .desc = "XMM fast hypercall input (hv-xmm-input)",
986 .flags = {
987 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
988 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE}
989 }
990 },
aa6bb5fa
VK		 991 [HYPERV_FEAT_TLBFLUSH_EXT] = {
992 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)",
993 .flags = {
994 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
995 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE}
996 },
997 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
998 },
3aae0854
VK		 999 [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
1000 .desc = "direct TLB flush (hv-tlbflush-direct)",
1001 .flags = {
1002 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1003 .bits = HV_NESTED_DIRECT_FLUSH}
1004 },
1005 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1006 },
6760bd20
VK		 1007};
1008
2e905438
VK		 1009static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
1010 bool do_sys_ioctl)
6760bd20
VK		 1011{
1012 struct kvm_cpuid2 *cpuid;
1013 int r, size;
1014
1015 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
1016 cpuid = g_malloc0(size);
1017 cpuid->nent = max;
1018
2e905438
VK		 1019 if (do_sys_ioctl) {
1020 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1021 } else {
1022 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1023 }
6760bd20
VK		 1024 if (r == 0 && cpuid->nent >= max) {
1025 r = -E2BIG;
1026 }
1027 if (r < 0) {
1028 if (r == -E2BIG) {
1029 g_free(cpuid);
1030 return NULL;
1031 } else {
1032 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
1033 strerror(-r));
1034 exit(1);
1035 }
1036 }
1037 return cpuid;
1038}
1039
1040/*
1041 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1042 * for all entries.
1043 */
1044static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1045{
1046 struct kvm_cpuid2 *cpuid;
73d24074
JD		 1047 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */
1048 int max = 11;
decb4f20 1049 int i;
2e905438
VK		 1050 bool do_sys_ioctl;
1051
1052 do_sys_ioctl =
1053 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
6760bd20 1054
e4adb09f
VK		 1055 /*
1056 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1057 * unsupported, kvm_hyperv_expand_features() checks for that.
1058 */
1059 assert(do_sys_ioctl || cs->kvm_state);
1060
6760bd20
VK		 1061 /*
1062 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1063 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1064 * it and re-trying until we succeed.
1065 */
2e905438 1066 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
6760bd20
VK		 1067 max++;
1068 }
decb4f20
VK		 1069
1070 /*
1071 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1072 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1073 * information early, just check for the capability and set the bit
1074 * manually.
1075 */
2e905438 1076 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
decb4f20
VK		 1077 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1078 for (i = 0; i < cpuid->nent; i++) {
1079 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1080 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1081 }
1082 }
1083 }
1084
6760bd20
VK		 1085 return cpuid;
1086}
1087
1088/*
1089 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1090 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1091 */
1092static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 1093{
1094 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 1095 struct kvm_cpuid2 *cpuid;
1096 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1097
1098 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1099 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1100 cpuid->nent = 2;
1101
1102 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1103 entry_feat = &cpuid->entries[0];
1104 entry_feat->function = HV_CPUID_FEATURES;
1105
1106 entry_recomm = &cpuid->entries[1];
1107 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1108 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1109
1110 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1111 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1112 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1113 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1114 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1115 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1116 }
c35bd19a 1117
6760bd20
VK		 1118 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1119 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1120 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 1121 }
6760bd20
VK		 1122
1123 if (has_msr_hv_frequencies) {
1124 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1125 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 1126 }
6760bd20
VK		 1127
1128 if (has_msr_hv_crash) {
1129 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 1130 }
6760bd20
VK		 1131
1132 if (has_msr_hv_reenlightenment) {
1133 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 1134 }
6760bd20
VK		 1135
1136 if (has_msr_hv_reset) {
1137 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 1138 }
6760bd20
VK		 1139
1140 if (has_msr_hv_vpindex) {
1141 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 1142 }
6760bd20
VK		 1143
1144 if (has_msr_hv_runtime) {
1145 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 1146 }
6760bd20
VK		 1147
1148 if (has_msr_hv_synic) {
1149 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1150 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1151
1152 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1153 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 1154 }
c35bd19a 1155 }
6760bd20
VK		 1156
1157 if (has_msr_hv_stimer) {
1158 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 1159 }
9b4cf107 1160
73d24074
JD		 1161 if (has_msr_hv_syndbg_options) {
1162 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE;
1163 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
1164 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED;
1165 }
1166
6760bd20
VK		 1167 if (kvm_check_extension(cs->kvm_state,
1168 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1169 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1170 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1171 }
c35bd19a 1172
6760bd20
VK		 1173 if (kvm_check_extension(cs->kvm_state,
1174 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1175 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 1176 }
6760bd20
VK		 1177
1178 if (kvm_check_extension(cs->kvm_state,
1179 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1180 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1181 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 1182 }
6760bd20
VK		 1183
1184 return cpuid;
1185}
1186
a8439be6 1187static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
e1a66a1e
VK		 1188{
1189 struct kvm_cpuid_entry2 *entry;
a8439be6
VK		 1190 struct kvm_cpuid2 *cpuid;
1191
1192 if (hv_cpuid_cache) {
1193 cpuid = hv_cpuid_cache;
1194 } else {
1195 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1196 cpuid = get_supported_hv_cpuid(cs);
1197 } else {
e4adb09f
VK		 1198 /*
1199 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1200 * before KVM context is created but this is only done when
1201 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1202 * KVM_CAP_HYPERV_CPUID.
1203 */
1204 assert(cs->kvm_state);
1205
a8439be6
VK		 1206 cpuid = get_supported_hv_cpuid_legacy(cs);
1207 }
1208 hv_cpuid_cache = cpuid;
1209 }
1210
1211 if (!cpuid) {
1212 return 0;
1213 }
e1a66a1e
VK		 1214
1215 entry = cpuid_find_entry(cpuid, func, 0);
1216 if (!entry) {
1217 return 0;
1218 }
1219
1220 return cpuid_entry_get_reg(entry, reg);
1221}
1222
a8439be6 1223static bool hyperv_feature_supported(CPUState *cs, int feature)
7682f857 1224{
061817a7
VK		 1225 uint32_t func, bits;
1226 int i, reg;
7682f857
VK		 1227
1228 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
061817a7
VK		 1229
1230 func = kvm_hyperv_properties[feature].flags[i].func;
1231 reg = kvm_hyperv_properties[feature].flags[i].reg;
7682f857
VK		 1232 bits = kvm_hyperv_properties[feature].flags[i].bits;
1233
061817a7 1234 if (!func) {
7682f857
VK		 1235 continue;
1236 }
1237
a8439be6 1238 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
7682f857
VK		 1239 return false;
1240 }
1241 }
1242
1243 return true;
1244}
1245
5ce48fa3
VK		 1246/* Checks that all feature dependencies are enabled */
1247static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
6760bd20 1248{
c6861930 1249 uint64_t deps;
7682f857 1250 int dep_feat;
6760bd20 1251
c6861930 1252 deps = kvm_hyperv_properties[feature].dependencies;
9dc83cd9
HR		 1253 while (deps) {
1254 dep_feat = ctz64(deps);
c6861930 1255 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
f4a62495
VK		 1256 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1257 kvm_hyperv_properties[feature].desc,
1258 kvm_hyperv_properties[dep_feat].desc);
5ce48fa3 1259 return false;
c6861930 1260 }
9dc83cd9 1261 deps &= ~(1ull << dep_feat);
c6861930
VK		 1262 }
1263
5ce48fa3 1264 return true;
6760bd20
VK		 1265}
1266
061817a7 1267static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
c830015e
VK		 1268{
1269 X86CPU *cpu = X86_CPU(cs);
1270 uint32_t r = 0;
1271 int i, j;
1272
1273 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1274 if (!hyperv_feat_enabled(cpu, i)) {
1275 continue;
1276 }
1277
1278 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
061817a7
VK		 1279 if (kvm_hyperv_properties[i].flags[j].func != func) {
1280 continue;
1281 }
1282 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
c830015e
VK		 1283 continue;
1284 }
1285
1286 r |= kvm_hyperv_properties[i].flags[j].bits;
1287 }
1288 }
1289
7110fe56
VK		 1290 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */
1291 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) {
1292 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1293 r |= DEFAULT_EVMCS_VERSION;
1294 }
1295 }
1296
c830015e
VK		 1297 return r;
1298}
1299
2344d22e 1300/*
f6e01ab5
VK		 1301 * Expand Hyper-V CPU features. In partucular, check that all the requested
1302 * features are supported by the host and the sanity of the configuration
1303 * (that all the required dependencies are included). Also, this takes care
1304 * of 'hv_passthrough' mode and fills the environment with all supported
1305 * Hyper-V features.
2344d22e 1306 */
071ce4b0 1307bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
6760bd20 1308{
071ce4b0 1309 CPUState *cs = CPU(cpu);
5ce48fa3
VK		 1310 Error *local_err = NULL;
1311 int feat;
6760bd20 1312
2344d22e 1313 if (!hyperv_enabled(cpu))
d7652b77 1314 return true;
2344d22e 1315
071ce4b0
VK		 1316 /*
1317 * When kvm_hyperv_expand_features is called at CPU feature expansion
1318 * time per-CPU kvm_state is not available yet so we can only proceed
1319 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1320 */
1321 if (!cs->kvm_state &&
1322 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1323 return true;
1324
e48ddcc6 1325 if (cpu->hyperv_passthrough) {
e1a66a1e 1326 cpu->hyperv_vendor_id[0] =
a8439be6 1327 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
e1a66a1e 1328 cpu->hyperv_vendor_id[1] =
a8439be6 1329 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
e1a66a1e 1330 cpu->hyperv_vendor_id[2] =
a8439be6 1331 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
e1a66a1e
VK		 1332 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1333 sizeof(cpu->hyperv_vendor_id) + 1);
1334 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1335 sizeof(cpu->hyperv_vendor_id));
1336 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1337
1338 cpu->hyperv_interface_id[0] =
a8439be6 1339 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
e1a66a1e 1340 cpu->hyperv_interface_id[1] =
a8439be6 1341 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
e1a66a1e 1342 cpu->hyperv_interface_id[2] =
a8439be6 1343 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
e1a66a1e 1344 cpu->hyperv_interface_id[3] =
a8439be6 1345 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
e1a66a1e 1346
af7228b8 1347 cpu->hyperv_ver_id_build =
a8439be6 1348 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
af7228b8
VK		 1349 cpu->hyperv_ver_id_major =
1350 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1351 cpu->hyperv_ver_id_minor =
1352 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1353 cpu->hyperv_ver_id_sp =
a8439be6 1354 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
af7228b8
VK		 1355 cpu->hyperv_ver_id_sb =
1356 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1357 cpu->hyperv_ver_id_sn =
1358 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
e1a66a1e 1359
a8439be6 1360 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
e1a66a1e
VK		 1361 R_EAX);
1362 cpu->hyperv_limits[0] =
a8439be6 1363 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
e1a66a1e 1364 cpu->hyperv_limits[1] =
a8439be6 1365 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
e1a66a1e 1366 cpu->hyperv_limits[2] =
a8439be6 1367 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
e1a66a1e
VK		 1368
1369 cpu->hyperv_spinlock_attempts =
a8439be6 1370 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
30d6ff66 1371
5ce48fa3
VK		 1372 /*
1373 * Mark feature as enabled in 'cpu->hyperv_features' as
1374 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1375 */
1376 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1377 if (hyperv_feature_supported(cs, feat)) {
1378 cpu->hyperv_features |= BIT(feat);
1379 }
1380 }
1381 } else {
1382 /* Check features availability and dependencies */
1383 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1384 /* If the feature was not requested skip it. */
1385 if (!hyperv_feat_enabled(cpu, feat)) {
1386 continue;
1387 }
1388
1389 /* Check if the feature is supported by KVM */
1390 if (!hyperv_feature_supported(cs, feat)) {
1391 error_setg(errp, "Hyper-V %s is not supported by kernel",
1392 kvm_hyperv_properties[feat].desc);
1393 return false;
1394 }
1395
1396 /* Check dependencies */
1397 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1398 error_propagate(errp, local_err);
1399 return false;
1400 }
1401 }
f4a62495 1402 }
6760bd20 1403
c6861930 1404 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1405 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1406 !cpu->hyperv_synic_kvm_only &&
1407 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
f4a62495
VK		 1408 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1409 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1410 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
d7652b77 1411 return false;
6760bd20 1412 }
d7652b77
VK		 1413
1414 return true;
f6e01ab5
VK		 1415}
1416
1417/*
1418 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1419 */
1420static int hyperv_fill_cpuids(CPUState *cs,
1421 struct kvm_cpuid_entry2 *cpuid_ent)
1422{
1423 X86CPU *cpu = X86_CPU(cs);
1424 struct kvm_cpuid_entry2 *c;
73d24074
JD		 1425 uint32_t signature[3];
1426 uint32_t cpuid_i = 0, max_cpuid_leaf = 0;
7110fe56
VK		 1427 uint32_t nested_eax =
1428 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX);
73d24074 1429
7110fe56
VK		 1430 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES :
1431 HV_CPUID_IMPLEMENT_LIMITS;
73d24074
JD		 1432
1433 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1434 max_cpuid_leaf =
1435 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
1436 }
f6e01ab5 1437
2344d22e
VK		 1438 c = &cpuid_ent[cpuid_i++];
1439 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
73d24074 1440 c->eax = max_cpuid_leaf;
08856771
VK		 1441 c->ebx = cpu->hyperv_vendor_id[0];
1442 c->ecx = cpu->hyperv_vendor_id[1];
1443 c->edx = cpu->hyperv_vendor_id[2];
2344d22e
VK		 1444
1445 c = &cpuid_ent[cpuid_i++];
1446 c->function = HV_CPUID_INTERFACE;
735db465
VK		 1447 c->eax = cpu->hyperv_interface_id[0];
1448 c->ebx = cpu->hyperv_interface_id[1];
1449 c->ecx = cpu->hyperv_interface_id[2];
1450 c->edx = cpu->hyperv_interface_id[3];
2344d22e
VK		 1451
1452 c = &cpuid_ent[cpuid_i++];
1453 c->function = HV_CPUID_VERSION;
af7228b8
VK		 1454 c->eax = cpu->hyperv_ver_id_build;
1455 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1456 cpu->hyperv_ver_id_minor;
1457 c->ecx = cpu->hyperv_ver_id_sp;
1458 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1459 (cpu->hyperv_ver_id_sn & 0xffffff);
2344d22e
VK		 1460
1461 c = &cpuid_ent[cpuid_i++];
1462 c->function = HV_CPUID_FEATURES;
061817a7
VK		 1463 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1464 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1465 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
c830015e 1466
b26f68c3
VK		 1467 /* Unconditionally required with any Hyper-V enlightenment */
1468 c->eax |= HV_HYPERCALL_AVAILABLE;
1469
cce087f6
VK		 1470 /* SynIC and Vmbus devices require messages/signals hypercalls */
1471 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1472 !cpu->hyperv_synic_kvm_only) {
1473 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1474 }
1475
05071629 1476
c830015e
VK		 1477 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1478 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
2344d22e
VK		 1479
1480 c = &cpuid_ent[cpuid_i++];
1481 c->function = HV_CPUID_ENLIGHTMENT_INFO;
061817a7 1482 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
2344d22e
VK		 1483 c->ebx = cpu->hyperv_spinlock_attempts;
1484
e1f9a8e8
VK		 1485 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1486 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
05071629
VK		 1487 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1488 }
1489
c830015e
VK		 1490 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1491 c->eax |= HV_NO_NONARCH_CORESHARING;
1492 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
a8439be6 1493 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
e1a66a1e 1494 HV_NO_NONARCH_CORESHARING;
c830015e
VK		 1495 }
1496
2344d22e
VK		 1497 c = &cpuid_ent[cpuid_i++];
1498 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1499 c->eax = cpu->hv_max_vps;
23eb5d03
VK		 1500 c->ebx = cpu->hyperv_limits[0];
1501 c->ecx = cpu->hyperv_limits[1];
1502 c->edx = cpu->hyperv_limits[2];
2344d22e 1503
7110fe56 1504 if (nested_eax) {
dc7d6caf 1505 uint32_t function;
2344d22e
VK		 1506
1507 /* Create zeroed 0x40000006..0x40000009 leaves */
1508 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1509 function < HV_CPUID_NESTED_FEATURES; function++) {
1510 c = &cpuid_ent[cpuid_i++];
1511 c->function = function;
1512 }
1513
1514 c = &cpuid_ent[cpuid_i++];
1515 c->function = HV_CPUID_NESTED_FEATURES;
7110fe56 1516 c->eax = nested_eax;
2344d22e 1517 }
6760bd20 1518
73d24074
JD		 1519 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1520 c = &cpuid_ent[cpuid_i++];
1521 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS;
1522 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1523 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1524 memcpy(signature, "Microsoft VS", 12);
1525 c->eax = 0;
1526 c->ebx = signature[0];
1527 c->ecx = signature[1];
1528 c->edx = signature[2];
1529
1530 c = &cpuid_ent[cpuid_i++];
1531 c->function = HV_CPUID_SYNDBG_INTERFACE;
1532 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12);
1533 c->eax = signature[0];
1534 c->ebx = 0;
1535 c->ecx = 0;
1536 c->edx = 0;
1537
1538 c = &cpuid_ent[cpuid_i++];
1539 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES;
1540 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
1541 c->ebx = 0;
1542 c->ecx = 0;
1543 c->edx = 0;
1544 }
1545
a8439be6 1546 return cpuid_i;
c35bd19a
EY		 1547}
1548
e48ddcc6 1549static Error *hv_passthrough_mig_blocker;
30d6ff66 1550static Error *hv_no_nonarch_cs_mig_blocker;
e48ddcc6 1551
07454e2e
VK		 1552/* Checks that the exposed eVMCS version range is supported by KVM */
1553static bool evmcs_version_supported(uint16_t evmcs_version,
1554 uint16_t supported_evmcs_version)
1555{
1556 uint8_t min_version = evmcs_version & 0xff;
1557 uint8_t max_version = evmcs_version >> 8;
1558 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1559 uint8_t max_supported_version = supported_evmcs_version >> 8;
1560
1561 return (min_version >= min_supported_version) &&
1562 (max_version <= max_supported_version);
1563}
1564
e9688fab
RK		 1565static int hyperv_init_vcpu(X86CPU *cpu)
1566{
729ce7e1 1567 CPUState *cs = CPU(cpu);
e48ddcc6 1568 Error *local_err = NULL;
729ce7e1
RK		 1569 int ret;
1570
e48ddcc6
VK		 1571 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1572 error_setg(&hv_passthrough_mig_blocker,
1573 "'hv-passthrough' CPU flag prevents migration, use explicit"
1574 " set of hv-* flags instead");
1575 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
436c831a 1576 if (ret < 0) {
e48ddcc6 1577 error_report_err(local_err);
e48ddcc6
VK		 1578 return ret;
1579 }
1580 }
1581
30d6ff66
VK		 1582 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1583 hv_no_nonarch_cs_mig_blocker == NULL) {
1584 error_setg(&hv_no_nonarch_cs_mig_blocker,
1585 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1586 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1587 " make sure SMT is disabled and/or that vCPUs are properly"
1588 " pinned)");
1589 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
436c831a 1590 if (ret < 0) {
30d6ff66 1591 error_report_err(local_err);
30d6ff66
VK		 1592 return ret;
1593 }
1594 }
1595
2d384d7c 1596 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1597 /*
1598 * the kernel doesn't support setting vp_index; assert that its value
1599 * is in sync
1600 */
5a778a5f 1601 uint64_t value;
e9688fab 1602
5a778a5f 1603 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
e9688fab
RK		 1604 if (ret < 0) {
1605 return ret;
1606 }
e9688fab 1607
5a778a5f 1608 if (value != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1609 error_report("kernel's vp_index != QEMU's vp_index");
1610 return -ENXIO;
1611 }
1612 }
1613
2d384d7c 1614 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1615 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1616 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1617 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1618 if (ret < 0) {
1619 error_report("failed to turn on HyperV SynIC in KVM: %s",
1620 strerror(-ret));
1621 return ret;
1622 }
606c34bf 1623
9b4cf107
RK		 1624 if (!cpu->hyperv_synic_kvm_only) {
1625 ret = hyperv_x86_synic_add(cpu);
1626 if (ret < 0) {
1627 error_report("failed to create HyperV SynIC: %s",
1628 strerror(-ret));
1629 return ret;
1630 }
606c34bf 1631 }
729ce7e1
RK		 1632 }
1633
decb4f20 1634 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
07454e2e
VK		 1635 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1636 uint16_t supported_evmcs_version;
decb4f20
VK		 1637
1638 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
07454e2e 1639 (uintptr_t)&supported_evmcs_version);
decb4f20 1640
07454e2e
VK		 1641 /*
1642 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1643 * option sets. Note: we hardcode the maximum supported eVMCS version
1644 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1645 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1646 * to be added.
1647 */
decb4f20 1648 if (ret < 0) {
07454e2e
VK		 1649 error_report("Hyper-V %s is not supported by kernel",
1650 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
decb4f20
VK		 1651 return ret;
1652 }
1653
07454e2e
VK		 1654 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1655 error_report("eVMCS version range [%d..%d] is not supported by "
1656 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1657 evmcs_version >> 8, supported_evmcs_version & 0xff,
1658 supported_evmcs_version >> 8);
1659 return -ENOTSUP;
1660 }
decb4f20
VK		 1661 }
1662
70367f09
VK		 1663 if (cpu->hyperv_enforce_cpuid) {
1664 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1665 if (ret < 0) {
1666 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1667 strerror(-ret));
1668 return ret;
1669 }
1670 }
1671
e9688fab
RK		 1672 return 0;
1673}
1674
68bfd0ad
MT		 1675static Error *invtsc_mig_blocker;
1676
f8bb0565 1677#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1678
e56dd3c7
JL		 1679static void kvm_init_xsave(CPUX86State *env)
1680{
1681 if (has_xsave2) {
1682 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1683 } else if (has_xsave) {
1684 env->xsave_buf_len = sizeof(struct kvm_xsave);
1685 } else {
1686 return;
1687 }
1688
1689 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1690 memset(env->xsave_buf, 0, env->xsave_buf_len);
1691 /*
1692 * The allocated storage must be large enough for all of the
1693 * possible XSAVE state components.
1694 */
1695 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1696 env->xsave_buf_len);
1697}
1698
3cafdb67
VK		 1699static void kvm_init_nested_state(CPUX86State *env)
1700{
1701 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1702 uint32_t size;
1703
1704 if (!env->nested_state) {
1705 return;
1706 }
1707
1708 size = env->nested_state->size;
1709
1710 memset(env->nested_state, 0, size);
1711 env->nested_state->size = size;
1712
1713 if (cpu_has_vmx(env)) {
1714 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1715 vmx_hdr = &env->nested_state->hdr.vmx;
1716 vmx_hdr->vmxon_pa = -1ull;
1717 vmx_hdr->vmcs12_pa = -1ull;
1718 } else if (cpu_has_svm(env)) {
1719 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1720 }
1721}
1722
20d695a9 1723int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1724{
1725 struct {
486bd5a2 1726 struct kvm_cpuid2 cpuid;
f8bb0565 1727 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1728 } cpuid_data;
1729 /*
1730 * The kernel defines these structs with padding fields so there
1731 * should be no extra padding in our cpuid_data struct.
1732 */
1733 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1734 sizeof(struct kvm_cpuid2) +
1735 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1736
20d695a9
AF		 1737 X86CPU *cpu = X86_CPU(cs);
1738 CPUX86State *env = &cpu->env;
486bd5a2 1739 uint32_t limit, i, j, cpuid_i;
a33609ca 1740 uint32_t unused;
bb0300dc 1741 struct kvm_cpuid_entry2 *c;
bb0300dc 1742 uint32_t signature[3];
234cc647 1743 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1744 int max_nested_state_len;
e7429073 1745 int r;
fe44dc91 1746 Error *local_err = NULL;
05330448 1747
ef4cbe14
SW		 1748 memset(&cpuid_data, 0, sizeof(cpuid_data));
1749
05330448
AL		 1750 cpuid_i = 0;
1751
e56dd3c7
JL		 1752 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
1753
ddb98b5a
LP		 1754 r = kvm_arch_set_tsc_khz(cs);
1755 if (r < 0) {
6b2341ee 1756 return r;
ddb98b5a
LP		 1757 }
1758
1759 /* vcpu's TSC frequency is either specified by user, or following
1760 * the value used by KVM if the former is not present. In the
1761 * latter case, we query it from KVM and record in env->tsc_khz,
1762 * so that vcpu's TSC frequency can be migrated later via this field.
1763 */
1764 if (!env->tsc_khz) {
1765 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1766 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1767 -ENOTSUP;
1768 if (r > 0) {
1769 env->tsc_khz = r;
1770 }
1771 }
1772
73b994f6
LA		 1773 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1774
071ce4b0
VK		 1775 /*
1776 * kvm_hyperv_expand_features() is called here for the second time in case
1777 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
1778 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
1779 * check which Hyper-V enlightenments are supported and which are not, we
1780 * can still proceed and check/expand Hyper-V enlightenments here so legacy
1781 * behavior is preserved.
1782 */
1783 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
f4a62495
VK		 1784 error_report_err(local_err);
1785 return -ENOSYS;
f6e01ab5
VK		 1786 }
1787
1788 if (hyperv_enabled(cpu)) {
decb4f20
VK		 1789 r = hyperv_init_vcpu(cpu);
1790 if (r) {
1791 return r;
1792 }
1793
f6e01ab5 1794 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
234cc647 1795 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1796 has_msr_hv_hypercall = true;
eab70139
VR		 1797 }
1798
f522d2ac
AW		 1799 if (cpu->expose_kvm) {
1800 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1801 c = &cpuid_data.entries[cpuid_i++];
1802 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1803 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1804 c->ebx = signature[0];
1805 c->ecx = signature[1];
1806 c->edx = signature[2];
234cc647 1807
f522d2ac
AW		 1808 c = &cpuid_data.entries[cpuid_i++];
1809 c->function = KVM_CPUID_FEATURES | kvm_base;
1810 c->eax = env->features[FEAT_KVM];
be777326 1811 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1812 }
917367aa 1813
a33609ca 1814 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448 1815
988f7b8b
VK		 1816 if (cpu->kvm_pv_enforce_cpuid) {
1817 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
1818 if (r < 0) {
1819 fprintf(stderr,
1820 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
1821 strerror(-r));
1822 abort();
1823 }
1824 }
1825
05330448 1826 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1827 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1828 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1829 abort();
1830 }
bb0300dc 1831 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1832
1833 switch (i) {
a36b1029
AL		 1834 case 2: {
1835 /* Keep reading function 2 till all the input is received */
1836 int times;
1837
a36b1029 1838 c->function = i;
a33609ca
AL		 1839 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1840 KVM_CPUID_FLAG_STATE_READ_NEXT;
1841 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1842 times = c->eax & 0xff;
a36b1029
AL		 1843
1844 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1845 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1846 fprintf(stderr, "cpuid_data is full, no space for "
1847 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1848 abort();
1849 }
a33609ca 1850 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1851 c->function = i;
a33609ca
AL		 1852 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1853 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1854 }
1855 break;
1856 }
a94e1428
LX		 1857 case 0x1f:
1858 if (env->nr_dies < 2) {
1859 break;
1860 }
8821e214 1861 /* fallthrough */
486bd5a2
AL		 1862 case 4:
1863 case 0xb:
1864 case 0xd:
1865 for (j = 0; ; j++) {
31e8c696
AP		 1866 if (i == 0xd && j == 64) {
1867 break;
1868 }
a94e1428
LX		 1869
1870 if (i == 0x1f && j == 64) {
1871 break;
1872 }
1873
486bd5a2
AL		 1874 c->function = i;
1875 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1876 c->index = j;
a33609ca 1877 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1878
b9bec74b 1879 if (i == 4 && c->eax == 0) {
486bd5a2 1880 break;
b9bec74b
JK		 1881 }
1882 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1883 break;
b9bec74b 1884 }
a94e1428
LX		 1885 if (i == 0x1f && !(c->ecx & 0xff00)) {
1886 break;
1887 }
b9bec74b 1888 if (i == 0xd && c->eax == 0) {
31e8c696 1889 continue;
b9bec74b 1890 }
f8bb0565
IM		 1891 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1892 fprintf(stderr, "cpuid_data is full, no space for "
1893 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1894 abort();
1895 }
a33609ca 1896 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1897 }
1898 break;
80db491d 1899 case 0x7:
b9edbade
SC		 1900 case 0x12:
1901 for (j = 0; ; j++) {
1902 c->function = i;
1903 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1904 c->index = j;
1905 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1906
1907 if (j > 1 && (c->eax & 0xf) != 1) {
1908 break;
1909 }
1910
1911 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1912 fprintf(stderr, "cpuid_data is full, no space for "
1913 "cpuid(eax:0x12,ecx:0x%x)\n", j);
1914 abort();
1915 }
1916 c = &cpuid_data.entries[cpuid_i++];
1917 }
1918 break;
f21a4817
JL		 1919 case 0x14:
1920 case 0x1d:
1921 case 0x1e: {
e37a5c7f
CP		 1922 uint32_t times;
1923
1924 c->function = i;
1925 c->index = 0;
1926 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1927 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1928 times = c->eax;
1929
1930 for (j = 1; j <= times; ++j) {
1931 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1932 fprintf(stderr, "cpuid_data is full, no space for "
80db491d 1933 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
e37a5c7f
CP		 1934 abort();
1935 }
1936 c = &cpuid_data.entries[cpuid_i++];
1937 c->function = i;
1938 c->index = j;
1939 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1940 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1941 }
1942 break;
1943 }
486bd5a2 1944 default:
486bd5a2 1945 c->function = i;
a33609ca
AL		 1946 c->flags = 0;
1947 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1948 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1949 /*
1950 * KVM already returns all zeroes if a CPUID entry is missing,
1951 * so we can omit it and avoid hitting KVM's 80-entry limit.
1952 */
1953 cpuid_i--;
1954 }
486bd5a2
AL		 1955 break;
1956 }
05330448 1957 }
0d894367
PB		 1958
1959 if (limit >= 0x0a) {
0b368a10 1960 uint32_t eax, edx;
0d894367 1961
0b368a10
JD		 1962 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1963
1964 has_architectural_pmu_version = eax & 0xff;
1965 if (has_architectural_pmu_version > 0) {
1966 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1967
1968 /* Shouldn't be more than 32, since that's the number of bits
1969 * available in EBX to tell us _which_ counters are available.
1970 * Play it safe.
1971 */
0b368a10
JD		 1972 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1973 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1974 }
1975
1976 if (has_architectural_pmu_version > 1) {
1977 num_architectural_pmu_fixed_counters = edx & 0x1f;
1978
1979 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1980 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1981 }
0d894367
PB		 1982 }
1983 }
1984 }
1985
a33609ca 1986 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1987
1988 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1989 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1990 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1991 abort();
1992 }
bb0300dc 1993 c = &cpuid_data.entries[cpuid_i++];
05330448 1994
8f4202fb
BM		 1995 switch (i) {
1996 case 0x8000001d:
1997 /* Query for all AMD cache information leaves */
1998 for (j = 0; ; j++) {
1999 c->function = i;
2000 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2001 c->index = j;
2002 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2003
2004 if (c->eax == 0) {
2005 break;
2006 }
2007 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2008 fprintf(stderr, "cpuid_data is full, no space for "
2009 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
2010 abort();
2011 }
2012 c = &cpuid_data.entries[cpuid_i++];
2013 }
2014 break;
2015 default:
2016 c->function = i;
2017 c->flags = 0;
2018 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 2019 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2020 /*
2021 * KVM already returns all zeroes if a CPUID entry is missing,
2022 * so we can omit it and avoid hitting KVM's 80-entry limit.
2023 */
2024 cpuid_i--;
2025 }
8f4202fb
BM		 2026 break;
2027 }
05330448
AL		 2028 }
2029
b3baa152
BW		 2030 /* Call Centaur's CPUID instructions they are supported. */
2031 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 2032 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
2033
2034 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 2035 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2036 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
2037 abort();
2038 }
b3baa152
BW		 2039 c = &cpuid_data.entries[cpuid_i++];
2040
2041 c->function = i;
2042 c->flags = 0;
2043 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2044 }
2045 }
2046
05330448
AL		 2047 cpuid_data.cpuid.nent = cpuid_i;
2048
e7701825 2049 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 2050 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 2051 (CPUID_MCE | CPUID_MCA)
a60f24b5 2052 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 2053 uint64_t mcg_cap, unsupported_caps;
e7701825 2054 int banks;
32a42024 2055 int ret;
e7701825 2056
a60f24b5 2057 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 2058 if (ret < 0) {
2059 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
2060 return ret;
e7701825 2061 }
75d49497 2062
2590f15b 2063 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 2064 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 2065 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 2066 return -ENOTSUP;
75d49497 2067 }
49b69cbf 2068
5120901a
EH		 2069 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
2070 if (unsupported_caps) {
87f8b626
AR		 2071 if (unsupported_caps & MCG_LMCE_P) {
2072 error_report("kvm: LMCE not supported");
2073 return -ENOTSUP;
2074 }
3dc6f869
AF		 2075 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
2076 unsupported_caps);
5120901a
EH		 2077 }
2078
2590f15b
EH		 2079 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
2080 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 2081 if (ret < 0) {
2082 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
2083 return ret;
2084 }
e7701825 2085 }
e7701825 2086
2a693142 2087 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
b8cc45d6 2088
df67696e
LJ		 2089 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
2090 if (c) {
2091 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
2092 !!(c->ecx & CPUID_EXT_SMX);
2093 }
2094
a0483541
SC		 2095 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
2096 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
2097 has_msr_feature_control = true;
2098 }
2099
87f8b626
AR		 2100 if (env->mcg_cap & MCG_LMCE_P) {
2101 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
2102 }
2103
d99569d9
EH		 2104 if (!env->user_tsc_khz) {
2105 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2106 invtsc_mig_blocker == NULL) {
d99569d9
EH		 2107 error_setg(&invtsc_mig_blocker,
2108 "State blocked by non-migratable CPU device"
2109 " (invtsc flag)");
fe44dc91 2110 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
436c831a 2111 if (r < 0) {
fe44dc91 2112 error_report_err(local_err);
79a197ab 2113 return r;
fe44dc91 2114 }
d99569d9 2115 }
68bfd0ad
MT		 2116 }
2117
9954a158
PDJ		 2118 if (cpu->vmware_cpuid_freq
2119 /* Guests depend on 0x40000000 to detect this feature, so only expose
2120 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2121 && cpu->expose_kvm
2122 && kvm_base == KVM_CPUID_SIGNATURE
2123 /* TSC clock must be stable and known for this feature. */
4bb95b82 2124 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 2125
2126 c = &cpuid_data.entries[cpuid_i++];
2127 c->function = KVM_CPUID_SIGNATURE | 0x10;
2128 c->eax = env->tsc_khz;
73b994f6 2129 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
9954a158
PDJ		 2130 c->ecx = c->edx = 0;
2131
2132 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2133 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2134 }
2135
2136 cpuid_data.cpuid.nent = cpuid_i;
2137
2138 cpuid_data.cpuid.padding = 0;
2139 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2140 if (r) {
2141 goto fail;
2142 }
e56dd3c7 2143 kvm_init_xsave(env);
ebbfef2f
LA		 2144
2145 max_nested_state_len = kvm_max_nested_state_length();
2146 if (max_nested_state_len > 0) {
2147 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
ebbfef2f 2148
b16c0e20 2149 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
1e44f3ab
PB		 2150 env->nested_state = g_malloc0(max_nested_state_len);
2151 env->nested_state->size = max_nested_state_len;
1e44f3ab 2152
3cafdb67 2153 kvm_init_nested_state(env);
ebbfef2f
LA		 2154 }
2155 }
2156
d71b62a1 2157 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 2158
273c515c
PB		 2159 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2160 has_msr_tsc_aux = false;
2161 }
d1ae67f6 2162
420ae1fc
PB		 2163 kvm_init_msrs(cpu);
2164
e7429073 2165 return 0;
fe44dc91
AA		 2166
2167 fail:
2168 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 2169
fe44dc91 2170 return r;
05330448
AL		 2171}
2172
b1115c99
LA		 2173int kvm_arch_destroy_vcpu(CPUState *cs)
2174{
2175 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 2176 CPUX86State *env = &cpu->env;
b1115c99 2177
dcebbb65
PMD		 2178 g_free(env->xsave_buf);
2179
76eb88b1
MA		 2180 g_free(cpu->kvm_msr_buf);
2181 cpu->kvm_msr_buf = NULL;
b1115c99 2182
76eb88b1
MA		 2183 g_free(env->nested_state);
2184 env->nested_state = NULL;
ebbfef2f 2185
2a693142
PN		 2186 qemu_del_vm_change_state_handler(cpu->vmsentry);
2187
b1115c99
LA		 2188 return 0;
2189}
2190
50a2c6e5 2191void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 2192{
20d695a9 2193 CPUX86State *env = &cpu->env;
dd673288 2194
1a5e9d2f 2195 env->xcr0 = 1;
ddced198 2196 if (kvm_irqchip_in_kernel()) {
dd673288 2197 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 2198 KVM_MP_STATE_UNINITIALIZED;
2199 } else {
2200 env->mp_state = KVM_MP_STATE_RUNNABLE;
2201 }
689141dd 2202
2d384d7c 2203 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 2204 int i;
2205 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2206 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2207 }
606c34bf
RK		 2208
2209 hyperv_x86_synic_reset(cpu);
689141dd 2210 }
d645e132
MT		 2211 /* enabled by default */
2212 env->poll_control_msr = 1;
b2f73a07 2213
3cafdb67
VK		 2214 kvm_init_nested_state(env);
2215
b2f73a07 2216 sev_es_set_reset_vector(CPU(cpu));
caa5af0f
JK		 2217}
2218
e0723c45
PB		 2219void kvm_arch_do_init_vcpu(X86CPU *cpu)
2220{
2221 CPUX86State *env = &cpu->env;
2222
2223 /* APs get directly into wait-for-SIPI state. */
2224 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2225 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2226 }
2227}
2228
f57bceb6
RH		 2229static int kvm_get_supported_feature_msrs(KVMState *s)
2230{
2231 int ret = 0;
2232
2233 if (kvm_feature_msrs != NULL) {
2234 return 0;
2235 }
2236
2237 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2238 return 0;
2239 }
2240
2241 struct kvm_msr_list msr_list;
2242
2243 msr_list.nmsrs = 0;
2244 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2245 if (ret < 0 && ret != -E2BIG) {
2246 error_report("Fetch KVM feature MSR list failed: %s",
2247 strerror(-ret));
2248 return ret;
2249 }
2250
2251 assert(msr_list.nmsrs > 0);
2252 kvm_feature_msrs = (struct kvm_msr_list *) \
2253 g_malloc0(sizeof(msr_list) +
2254 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2255
2256 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2257 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2258
2259 if (ret < 0) {
2260 error_report("Fetch KVM feature MSR list failed: %s",
2261 strerror(-ret));
2262 g_free(kvm_feature_msrs);
2263 kvm_feature_msrs = NULL;
2264 return ret;
2265 }
2266
2267 return 0;
2268}
2269
c3a3a7d3 2270static int kvm_get_supported_msrs(KVMState *s)
05330448 2271{
c3a3a7d3 2272 int ret = 0;
de428cea 2273 struct kvm_msr_list msr_list, *kvm_msr_list;
05330448 2274
de428cea
LQ		 2275 /*
2276 * Obtain MSR list from KVM. These are the MSRs that we must
2277 * save/restore.
2278 */
2279 msr_list.nmsrs = 0;
2280 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2281 if (ret < 0 && ret != -E2BIG) {
2282 return ret;
2283 }
2284 /*
2285 * Old kernel modules had a bug and could write beyond the provided
2286 * memory. Allocate at least a safe amount of 1K.
2287 */
2288 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2289 msr_list.nmsrs *
2290 sizeof(msr_list.indices[0])));
05330448 2291
de428cea
LQ		 2292 kvm_msr_list->nmsrs = msr_list.nmsrs;
2293 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2294 if (ret >= 0) {
2295 int i;
05330448 2296
de428cea
LQ		 2297 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2298 switch (kvm_msr_list->indices[i]) {
2299 case MSR_STAR:
2300 has_msr_star = true;
2301 break;
2302 case MSR_VM_HSAVE_PA:
2303 has_msr_hsave_pa = true;
2304 break;
2305 case MSR_TSC_AUX:
2306 has_msr_tsc_aux = true;
2307 break;
2308 case MSR_TSC_ADJUST:
2309 has_msr_tsc_adjust = true;
2310 break;
2311 case MSR_IA32_TSCDEADLINE:
2312 has_msr_tsc_deadline = true;
2313 break;
2314 case MSR_IA32_SMBASE:
2315 has_msr_smbase = true;
2316 break;
2317 case MSR_SMI_COUNT:
2318 has_msr_smi_count = true;
2319 break;
2320 case MSR_IA32_MISC_ENABLE:
2321 has_msr_misc_enable = true;
2322 break;
2323 case MSR_IA32_BNDCFGS:
2324 has_msr_bndcfgs = true;
2325 break;
2326 case MSR_IA32_XSS:
2327 has_msr_xss = true;
2328 break;
65087997
TX		 2329 case MSR_IA32_UMWAIT_CONTROL:
2330 has_msr_umwait = true;
2331 break;
de428cea
LQ		 2332 case HV_X64_MSR_CRASH_CTL:
2333 has_msr_hv_crash = true;
2334 break;
2335 case HV_X64_MSR_RESET:
2336 has_msr_hv_reset = true;
2337 break;
2338 case HV_X64_MSR_VP_INDEX:
2339 has_msr_hv_vpindex = true;
2340 break;
2341 case HV_X64_MSR_VP_RUNTIME:
2342 has_msr_hv_runtime = true;
2343 break;
2344 case HV_X64_MSR_SCONTROL:
2345 has_msr_hv_synic = true;
2346 break;
2347 case HV_X64_MSR_STIMER0_CONFIG:
2348 has_msr_hv_stimer = true;
2349 break;
2350 case HV_X64_MSR_TSC_FREQUENCY:
2351 has_msr_hv_frequencies = true;
2352 break;
2353 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2354 has_msr_hv_reenlightenment = true;
2355 break;
73d24074
JD		 2356 case HV_X64_MSR_SYNDBG_OPTIONS:
2357 has_msr_hv_syndbg_options = true;
2358 break;
de428cea
LQ		 2359 case MSR_IA32_SPEC_CTRL:
2360 has_msr_spec_ctrl = true;
2361 break;
cabf9862
ML		 2362 case MSR_AMD64_TSC_RATIO:
2363 has_tsc_scale_msr = true;
2364 break;
2a9758c5
PB		 2365 case MSR_IA32_TSX_CTRL:
2366 has_msr_tsx_ctrl = true;
2367 break;
de428cea
LQ		 2368 case MSR_VIRT_SSBD:
2369 has_msr_virt_ssbd = true;
2370 break;
2371 case MSR_IA32_ARCH_CAPABILITIES:
2372 has_msr_arch_capabs = true;
2373 break;
2374 case MSR_IA32_CORE_CAPABILITY:
2375 has_msr_core_capabs = true;
2376 break;
ea39f9b6
LX		 2377 case MSR_IA32_PERF_CAPABILITIES:
2378 has_msr_perf_capabs = true;
2379 break;
20a78b02
PB		 2380 case MSR_IA32_VMX_VMFUNC:
2381 has_msr_vmx_vmfunc = true;
2382 break;
67025148
PB		 2383 case MSR_IA32_UCODE_REV:
2384 has_msr_ucode_rev = true;
2385 break;
4a910e1f
VK		 2386 case MSR_IA32_VMX_PROCBASED_CTLS2:
2387 has_msr_vmx_procbased_ctls2 = true;
2388 break;
6aa4228b
CQ		 2389 case MSR_IA32_PKRS:
2390 has_msr_pkrs = true;
2391 break;
05330448
AL		 2392 }
2393 }
05330448
AL		 2394 }
2395
de428cea
LQ		 2396 g_free(kvm_msr_list);
2397
c3a3a7d3 2398 return ret;
05330448
AL		 2399}
2400
6410848b
PB		 2401static Notifier smram_machine_done;
2402static KVMMemoryListener smram_listener;
2403static AddressSpace smram_address_space;
2404static MemoryRegion smram_as_root;
2405static MemoryRegion smram_as_mem;
2406
2407static void register_smram_listener(Notifier *n, void *unused)
2408{
2409 MemoryRegion *smram =
2410 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2411
2412 /* Outer container... */
2413 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2414 memory_region_set_enabled(&smram_as_root, true);
2415
2416 /* ... with two regions inside: normal system memory with low
2417 * priority, and...
2418 */
2419 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2420 get_system_memory(), 0, ~0ull);
2421 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2422 memory_region_set_enabled(&smram_as_mem, true);
2423
2424 if (smram) {
2425 /* ... SMRAM with higher priority */
2426 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2427 memory_region_set_enabled(smram, true);
2428 }
2429
2430 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2431 kvm_memory_listener_register(kvm_state, &smram_listener,
142518bd 2432 &smram_address_space, 1, "kvm-smram");
6410848b
PB		 2433}
2434
b16565b3 2435int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 2436{
11076198 2437 uint64_t identity_base = 0xfffbc000;
39d6960a 2438 uint64_t shadow_mem;
20420430 2439 int ret;
25d2e361 2440 struct utsname utsname;
ec78e2cd
DG		 2441 Error *local_err = NULL;
2442
2443 /*
2444 * Initialize SEV context, if required
2445 *
2446 * If no memory encryption is requested (ms->cgs == NULL) this is
2447 * a no-op.
2448 *
2449 * It's also a no-op if a non-SEV confidential guest support
2450 * mechanism is selected. SEV is the only mechanism available to
2451 * select on x86 at present, so this doesn't arise, but if new
2452 * mechanisms are supported in future (e.g. TDX), they'll need
2453 * their own initialization either here or elsewhere.
2454 */
2455 ret = sev_kvm_init(ms->cgs, &local_err);
2456 if (ret < 0) {
2457 error_report_err(local_err);
2458 return ret;
2459 }
20420430 2460
1a6dff5f
EH		 2461 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2462 error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM");
2463 return -ENOTSUP;
2464 }
2465
28143b40 2466 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 2467 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 2468 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
8f515d38 2469 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
28143b40 2470
e9688fab
RK		 2471 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2472
fd13f23b
LA		 2473 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2474 if (has_exception_payload) {
2475 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2476 if (ret < 0) {
2477 error_report("kvm: Failed to enable exception payload cap: %s",
2478 strerror(-ret));
2479 return ret;
2480 }
2481 }
2482
12f89a39
CQ		 2483 has_triple_fault_event = kvm_check_extension(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT);
2484 if (has_triple_fault_event) {
2485 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true);
2486 if (ret < 0) {
2487 error_report("kvm: Failed to enable triple fault event cap: %s",
2488 strerror(-ret));
2489 return ret;
2490 }
2491 }
2492
c3a3a7d3 2493 ret = kvm_get_supported_msrs(s);
20420430 2494 if (ret < 0) {
20420430
SY		 2495 return ret;
2496 }
25d2e361 2497
f57bceb6
RH		 2498 kvm_get_supported_feature_msrs(s);
2499
25d2e361
MT		 2500 uname(&utsname);
2501 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2502
4c5b10b7 2503 /*
11076198
JK		 2504 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2505 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2506 * Since these must be part of guest physical memory, we need to allocate
2507 * them, both by setting their start addresses in the kernel and by
2508 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2509 *
2510 * Older KVM versions may not support setting the identity map base. In
2511 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2512 * size.
4c5b10b7 2513 */
11076198
JK		 2514 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2515 /* Allows up to 16M BIOSes. */
2516 identity_base = 0xfeffc000;
2517
2518 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2519 if (ret < 0) {
2520 return ret;
2521 }
4c5b10b7 2522 }
e56ff191 2523
11076198
JK		 2524 /* Set TSS base one page after EPT identity map. */
2525 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2526 if (ret < 0) {
2527 return ret;
2528 }
2529
11076198
JK		 2530 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2531 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2532 if (ret < 0) {
11076198 2533 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2534 return ret;
2535 }
2536
23b0898e 2537 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
36ad0e94
MA		 2538 if (shadow_mem != -1) {
2539 shadow_mem /= 4096;
2540 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2541 if (ret < 0) {
2542 return ret;
39d6960a
JK		 2543 }
2544 }
6410848b 2545
d870cfde 2546 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
8f54bbd0 2547 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
ed9e923c 2548 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
6410848b
PB		 2549 smram_machine_done.notify = register_smram_listener;
2550 qemu_add_machine_init_done_notifier(&smram_machine_done);
2551 }
6f131f13
MT		 2552
2553 if (enable_cpu_pm) {
2554 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2555 int ret;
2556
2557/* Work around for kernel header with a typo. TODO: fix header and drop. */
2558#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2559#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2560#endif
2561 if (disable_exits) {
2562 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2563 KVM_X86_DISABLE_EXITS_HLT |
d38d201f
WL		 2564 KVM_X86_DISABLE_EXITS_PAUSE |
2565 KVM_X86_DISABLE_EXITS_CSTATE);
6f131f13
MT		 2566 }
2567
2568 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2569 disable_exits);
2570 if (ret < 0) {
2571 error_report("kvm: guest stopping CPU not supported: %s",
2572 strerror(-ret));
2573 }
2574 }
2575
035d1ef2
CQ		 2576 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
2577 X86MachineState *x86ms = X86_MACHINE(ms);
2578
2579 if (x86ms->bus_lock_ratelimit > 0) {
2580 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
2581 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
2582 error_report("kvm: bus lock detection unsupported");
2583 return -ENOTSUP;
2584 }
2585 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
2586 KVM_BUS_LOCK_DETECTION_EXIT);
2587 if (ret < 0) {
2588 error_report("kvm: Failed to enable bus lock detection cap: %s",
2589 strerror(-ret));
2590 return ret;
2591 }
2592 ratelimit_init(&bus_lock_ratelimit_ctrl);
2593 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
2594 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
2595 }
2596 }
2597
11076198 2598 return 0;
05330448 2599}
b9bec74b 2600
05330448
AL		 2601static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2602{
2603 lhs->selector = rhs->selector;
2604 lhs->base = rhs->base;
2605 lhs->limit = rhs->limit;
2606 lhs->type = 3;
2607 lhs->present = 1;
2608 lhs->dpl = 3;
2609 lhs->db = 0;
2610 lhs->s = 1;
2611 lhs->l = 0;
2612 lhs->g = 0;
2613 lhs->avl = 0;
2614 lhs->unusable = 0;
2615}
2616
2617static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2618{
2619 unsigned flags = rhs->flags;
2620 lhs->selector = rhs->selector;
2621 lhs->base = rhs->base;
2622 lhs->limit = rhs->limit;
2623 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2624 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2625 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2626 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2627 lhs->s = (flags & DESC_S_MASK) != 0;
2628 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2629 lhs->g = (flags & DESC_G_MASK) != 0;
2630 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2631 lhs->unusable = !lhs->present;
7e680753 2632 lhs->padding = 0;
05330448
AL		 2633}
2634
2635static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2636{
2637 lhs->selector = rhs->selector;
2638 lhs->base = rhs->base;
2639 lhs->limit = rhs->limit;
d45fc087
RP		 2640 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2641 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2642 (rhs->dpl << DESC_DPL_SHIFT) |
2643 (rhs->db << DESC_B_SHIFT) |
2644 (rhs->s * DESC_S_MASK) |
2645 (rhs->l << DESC_L_SHIFT) |
2646 (rhs->g * DESC_G_MASK) |
2647 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2648}
2649
2650static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2651{
b9bec74b 2652 if (set) {
05330448 2653 *kvm_reg = *qemu_reg;
b9bec74b 2654 } else {
05330448 2655 *qemu_reg = *kvm_reg;
b9bec74b 2656 }
05330448
AL		 2657}
2658
1bc22652 2659static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2660{
1bc22652 2661 CPUX86State *env = &cpu->env;
05330448
AL		 2662 struct kvm_regs regs;
2663 int ret = 0;
2664
2665 if (!set) {
1bc22652 2666 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2667 if (ret < 0) {
05330448 2668 return ret;
b9bec74b 2669 }
05330448
AL		 2670 }
2671
2672 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2673 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2674 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2675 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2676 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2677 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2678 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2679 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2680#ifdef TARGET_X86_64
2681 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2682 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2683 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2684 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2685 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2686 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2687 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2688 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2689#endif
2690
2691 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2692 kvm_getput_reg(&regs.rip, &env->eip, set);
2693
b9bec74b 2694 if (set) {
1bc22652 2695 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2696 }
05330448
AL		 2697
2698 return ret;
2699}
2700
1bc22652 2701static int kvm_put_fpu(X86CPU *cpu)
05330448 2702{
1bc22652 2703 CPUX86State *env = &cpu->env;
05330448
AL		 2704 struct kvm_fpu fpu;
2705 int i;
2706
2707 memset(&fpu, 0, sizeof fpu);
2708 fpu.fsw = env->fpus & ~(7 << 11);
2709 fpu.fsw |= (env->fpstt & 7) << 11;
2710 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2711 fpu.last_opcode = env->fpop;
2712 fpu.last_ip = env->fpip;
2713 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2714 for (i = 0; i < 8; ++i) {
2715 fpu.ftwx |= (!env->fptags[i]) << i;
2716 }
05330448 2717 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2718 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2719 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2720 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2721 }
05330448
AL		 2722 fpu.mxcsr = env->mxcsr;
2723
1bc22652 2724 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2725}
2726
1bc22652 2727static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2728{
1bc22652 2729 CPUX86State *env = &cpu->env;
c0198c5f 2730 void *xsave = env->xsave_buf;
f1665b21 2731
28143b40 2732 if (!has_xsave) {
1bc22652 2733 return kvm_put_fpu(cpu);
b9bec74b 2734 }
c0198c5f 2735 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
f1665b21 2736
9be38598 2737 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2738}
2739
1bc22652 2740static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2741{
1bc22652 2742 CPUX86State *env = &cpu->env;
bdfc8480 2743 struct kvm_xcrs xcrs = {};
f1665b21 2744
28143b40 2745 if (!has_xcrs) {
f1665b21 2746 return 0;
b9bec74b 2747 }
f1665b21
SY		 2748
2749 xcrs.nr_xcrs = 1;
2750 xcrs.flags = 0;
2751 xcrs.xcrs[0].xcr = 0;
2752 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2753 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2754}
2755
1bc22652 2756static int kvm_put_sregs(X86CPU *cpu)
05330448 2757{
1bc22652 2758 CPUX86State *env = &cpu->env;
05330448
AL		 2759 struct kvm_sregs sregs;
2760
1520f8bb
PB		 2761 /*
2762 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
2763 * always followed by KVM_SET_VCPU_EVENTS.
2764 */
0e607a80 2765 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
05330448
AL		 2766
2767 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2768 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2769 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2770 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2771 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2772 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2773 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2774 } else {
b9bec74b
JK		 2775 set_seg(&sregs.cs, &env->segs[R_CS]);
2776 set_seg(&sregs.ds, &env->segs[R_DS]);
2777 set_seg(&sregs.es, &env->segs[R_ES]);
2778 set_seg(&sregs.fs, &env->segs[R_FS]);
2779 set_seg(&sregs.gs, &env->segs[R_GS]);
2780 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2781 }
2782
2783 set_seg(&sregs.tr, &env->tr);
2784 set_seg(&sregs.ldt, &env->ldt);
2785
2786 sregs.idt.limit = env->idt.limit;
2787 sregs.idt.base = env->idt.base;
7e680753 2788 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2789 sregs.gdt.limit = env->gdt.limit;
2790 sregs.gdt.base = env->gdt.base;
7e680753 2791 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2792
2793 sregs.cr0 = env->cr[0];
2794 sregs.cr2 = env->cr[2];
2795 sregs.cr3 = env->cr[3];
2796 sregs.cr4 = env->cr[4];
2797
02e51483
CF		 2798 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2799 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2800
2801 sregs.efer = env->efer;
2802
1bc22652 2803 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2804}
2805
8f515d38
ML		 2806static int kvm_put_sregs2(X86CPU *cpu)
2807{
2808 CPUX86State *env = &cpu->env;
2809 struct kvm_sregs2 sregs;
2810 int i;
2811
2812 sregs.flags = 0;
2813
2814 if ((env->eflags & VM_MASK)) {
2815 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2816 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2817 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2818 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2819 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2820 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2821 } else {
2822 set_seg(&sregs.cs, &env->segs[R_CS]);
2823 set_seg(&sregs.ds, &env->segs[R_DS]);
2824 set_seg(&sregs.es, &env->segs[R_ES]);
2825 set_seg(&sregs.fs, &env->segs[R_FS]);
2826 set_seg(&sregs.gs, &env->segs[R_GS]);
2827 set_seg(&sregs.ss, &env->segs[R_SS]);
2828 }
2829
2830 set_seg(&sregs.tr, &env->tr);
2831 set_seg(&sregs.ldt, &env->ldt);
2832
2833 sregs.idt.limit = env->idt.limit;
2834 sregs.idt.base = env->idt.base;
2835 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2836 sregs.gdt.limit = env->gdt.limit;
2837 sregs.gdt.base = env->gdt.base;
2838 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2839
2840 sregs.cr0 = env->cr[0];
2841 sregs.cr2 = env->cr[2];
2842 sregs.cr3 = env->cr[3];
2843 sregs.cr4 = env->cr[4];
2844
2845 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2846 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2847
2848 sregs.efer = env->efer;
2849
2850 if (env->pdptrs_valid) {
2851 for (i = 0; i < 4; i++) {
2852 sregs.pdptrs[i] = env->pdptrs[i];
2853 }
2854 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
2855 }
2856
2857 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
2858}
2859
2860
d71b62a1
EH		 2861static void kvm_msr_buf_reset(X86CPU *cpu)
2862{
2863 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2864}
2865
9c600a84
EH		 2866static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2867{
2868 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2869 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2870 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2871
2872 assert((void *)(entry + 1) <= limit);
2873
1abc2cae
EH		 2874 entry->index = index;
2875 entry->reserved = 0;
2876 entry->data = value;
9c600a84
EH		 2877 msrs->nmsrs++;
2878}
2879
73e1b8f2
PB		 2880static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2881{
2882 kvm_msr_buf_reset(cpu);
2883 kvm_msr_entry_add(cpu, index, value);
2884
2885 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2886}
2887
5a778a5f
YW		 2888static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
2889{
2890 int ret;
2891 struct {
2892 struct kvm_msrs info;
2893 struct kvm_msr_entry entries[1];
2894 } msr_data = {
2895 .info.nmsrs = 1,
2896 .entries[0].index = index,
2897 };
2898
2899 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
2900 if (ret < 0) {
2901 return ret;
2902 }
2903 assert(ret == 1);
2904 *value = msr_data.entries[0].data;
2905 return ret;
2906}
f8d9ccf8
DDAG		 2907void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2908{
2909 int ret;
2910
2911 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2912 assert(ret == 1);
2913}
2914
7477cd38
MT		 2915static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2916{
2917 CPUX86State *env = &cpu->env;
48e1a45c 2918 int ret;
7477cd38
MT		 2919
2920 if (!has_msr_tsc_deadline) {
2921 return 0;
2922 }
2923
73e1b8f2 2924 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2925 if (ret < 0) {
2926 return ret;
2927 }
2928
2929 assert(ret == 1);
2930 return 0;
7477cd38
MT		 2931}
2932
6bdf863d
JK		 2933/*
2934 * Provide a separate write service for the feature control MSR in order to
2935 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2936 * before writing any other state because forcibly leaving nested mode
2937 * invalidates the VCPU state.
2938 */
2939static int kvm_put_msr_feature_control(X86CPU *cpu)
2940{
48e1a45c
PB		 2941 int ret;
2942
2943 if (!has_msr_feature_control) {
2944 return 0;
2945 }
6bdf863d 2946
73e1b8f2
PB		 2947 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2948 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2949 if (ret < 0) {
2950 return ret;
2951 }
2952
2953 assert(ret == 1);
2954 return 0;
6bdf863d
JK		 2955}
2956
20a78b02
PB		 2957static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2958{
2959 uint32_t default1, can_be_one, can_be_zero;
2960 uint32_t must_be_one;
2961
2962 switch (index) {
2963 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2964 default1 = 0x00000016;
2965 break;
2966 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2967 default1 = 0x0401e172;
2968 break;
2969 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2970 default1 = 0x000011ff;
2971 break;
2972 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2973 default1 = 0x00036dff;
2974 break;
2975 case MSR_IA32_VMX_PROCBASED_CTLS2:
2976 default1 = 0;
2977 break;
2978 default:
2979 abort();
2980 }
2981
2982 /* If a feature bit is set, the control can be either set or clear.
2983 * Otherwise the value is limited to either 0 or 1 by default1.
2984 */
2985 can_be_one = features | default1;
2986 can_be_zero = features | ~default1;
2987 must_be_one = ~can_be_zero;
2988
2989 /*
2990 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2991 * Bit 32:63 -> 1 if the control bit can be one.
2992 */
2993 return must_be_one | (((uint64_t)can_be_one) << 32);
2994}
2995
20a78b02
PB		 2996static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2997{
2998 uint64_t kvm_vmx_basic =
2999 kvm_arch_get_supported_msr_feature(kvm_state,
3000 MSR_IA32_VMX_BASIC);
26051882
YZ		 3001
3002 if (!kvm_vmx_basic) {
3003 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
3004 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
3005 */
3006 return;
3007 }
3008
20a78b02
PB		 3009 uint64_t kvm_vmx_misc =
3010 kvm_arch_get_supported_msr_feature(kvm_state,
3011 MSR_IA32_VMX_MISC);
3012 uint64_t kvm_vmx_ept_vpid =
3013 kvm_arch_get_supported_msr_feature(kvm_state,
3014 MSR_IA32_VMX_EPT_VPID_CAP);
3015
3016 /*
3017 * If the guest is 64-bit, a value of 1 is allowed for the host address
3018 * space size vmexit control.
3019 */
3020 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
3021 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
3022
3023 /*
3024 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
3025 * not change them for backwards compatibility.
3026 */
3027 uint64_t fixed_vmx_basic = kvm_vmx_basic &
3028 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
3029 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
3030 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
3031
3032 /*
3033 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
3034 * change in the future but are always zero for now, clear them to be
3035 * future proof. Bits 32-63 in theory could change, though KVM does
3036 * not support dual-monitor treatment and probably never will; mask
3037 * them out as well.
3038 */
3039 uint64_t fixed_vmx_misc = kvm_vmx_misc &
3040 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
3041 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
3042
3043 /*
3044 * EPT memory types should not change either, so we do not bother
3045 * adding features for them.
3046 */
3047 uint64_t fixed_vmx_ept_mask =
3048 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
3049 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
3050 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
3051
3052 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3053 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3054 f[FEAT_VMX_PROCBASED_CTLS]));
3055 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3056 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3057 f[FEAT_VMX_PINBASED_CTLS]));
3058 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
3059 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
3060 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
3061 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3062 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3063 f[FEAT_VMX_ENTRY_CTLS]));
3064 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
3065 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
3066 f[FEAT_VMX_SECONDARY_CTLS]));
3067 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
3068 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
3069 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
3070 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
3071 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
3072 f[FEAT_VMX_MISC] | fixed_vmx_misc);
3073 if (has_msr_vmx_vmfunc) {
3074 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
3075 }
3076
3077 /*
3078 * Just to be safe, write these with constant values. The CRn_FIXED1
3079 * MSRs are generated by KVM based on the vCPU's CPUID.
3080 */
3081 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
3082 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
3083 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
3084 CR4_VMXE_MASK);
9ce8af4d
PB		 3085
3086 if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
3087 /* TSC multiplier (0x2032). */
3088 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
3089 } else {
3090 /* Preemption timer (0x482E). */
3091 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
3092 }
20a78b02
PB		 3093}
3094
ea39f9b6
LX		 3095static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
3096{
3097 uint64_t kvm_perf_cap =
3098 kvm_arch_get_supported_msr_feature(kvm_state,
3099 MSR_IA32_PERF_CAPABILITIES);
3100
3101 if (kvm_perf_cap) {
3102 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
3103 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
3104 }
3105}
3106
420ae1fc
PB		 3107static int kvm_buf_set_msrs(X86CPU *cpu)
3108{
3109 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3110 if (ret < 0) {
3111 return ret;
3112 }
3113
3114 if (ret < cpu->kvm_msr_buf->nmsrs) {
3115 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3116 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
3117 (uint32_t)e->index, (uint64_t)e->data);
3118 }
3119
3120 assert(ret == cpu->kvm_msr_buf->nmsrs);
3121 return 0;
3122}
3123
3124static void kvm_init_msrs(X86CPU *cpu)
3125{
3126 CPUX86State *env = &cpu->env;
3127
3128 kvm_msr_buf_reset(cpu);
3129 if (has_msr_arch_capabs) {
3130 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3131 env->features[FEAT_ARCH_CAPABILITIES]);
3132 }
3133
3134 if (has_msr_core_capabs) {
3135 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3136 env->features[FEAT_CORE_CAPABILITY]);
3137 }
3138
ea39f9b6
LX		 3139 if (has_msr_perf_capabs && cpu->enable_pmu) {
3140 kvm_msr_entry_add_perf(cpu, env->features);
3141 }
3142
67025148 3143 if (has_msr_ucode_rev) {
32c87d70
PB		 3144 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3145 }
3146
420ae1fc
PB		 3147 /*
3148 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3149 * all kernels with MSR features should have them.
3150 */
3151 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3152 kvm_msr_entry_add_vmx(cpu, env->features);
3153 }
3154
3155 assert(kvm_buf_set_msrs(cpu) == 0);
3156}
3157
1bc22652 3158static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 3159{
1bc22652 3160 CPUX86State *env = &cpu->env;
9c600a84 3161 int i;
05330448 3162
d71b62a1
EH		 3163 kvm_msr_buf_reset(cpu);
3164
9c600a84
EH		 3165 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3166 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3167 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3168 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 3169 if (has_msr_star) {
9c600a84 3170 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 3171 }
c3a3a7d3 3172 if (has_msr_hsave_pa) {
9c600a84 3173 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 3174 }
c9b8f6b6 3175 if (has_msr_tsc_aux) {
9c600a84 3176 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 3177 }
f28558d3 3178 if (has_msr_tsc_adjust) {
9c600a84 3179 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 3180 }
21e87c46 3181 if (has_msr_misc_enable) {
9c600a84 3182 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 3183 env->msr_ia32_misc_enable);
3184 }
fc12d72e 3185 if (has_msr_smbase) {
9c600a84 3186 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 3187 }
e13713db
LA		 3188 if (has_msr_smi_count) {
3189 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3190 }
6aa4228b
CQ		 3191 if (has_msr_pkrs) {
3192 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3193 }
439d19f2 3194 if (has_msr_bndcfgs) {
9c600a84 3195 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 3196 }
18cd2c17 3197 if (has_msr_xss) {
9c600a84 3198 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 3199 }
65087997
TX		 3200 if (has_msr_umwait) {
3201 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3202 }
a33a2cfe
PB		 3203 if (has_msr_spec_ctrl) {
3204 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3205 }
cabf9862
ML		 3206 if (has_tsc_scale_msr) {
3207 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3208 }
3209
2a9758c5
PB		 3210 if (has_msr_tsx_ctrl) {
3211 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3212 }
cfeea0c0
KRW		 3213 if (has_msr_virt_ssbd) {
3214 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3215 }
3216
05330448 3217#ifdef TARGET_X86_64
25d2e361 3218 if (lm_capable_kernel) {
9c600a84
EH		 3219 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3220 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3221 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3222 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 3223 }
05330448 3224#endif
a33a2cfe 3225
ff5c186b 3226 /*
0d894367
PB		 3227 * The following MSRs have side effects on the guest or are too heavy
3228 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 3229 */
3230 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 3231 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
3232 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
3233 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
6615be07
VK		 3234 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3235 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
3236 }
55c911a5 3237 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 3238 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 3239 }
55c911a5 3240 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3241 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 3242 }
55c911a5 3243 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3244 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 3245 }
d645e132
MT		 3246
3247 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3248 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
3249 }
3250
0b368a10
JD		 3251 if (has_architectural_pmu_version > 0) {
3252 if (has_architectural_pmu_version > 1) {
3253 /* Stop the counter. */
3254 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3255 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3256 }
0d894367
PB		 3257
3258 /* Set the counter values. */
0b368a10 3259 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3260 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 3261 env->msr_fixed_counters[i]);
3262 }
0b368a10 3263 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 3264 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 3265 env->msr_gp_counters[i]);
9c600a84 3266 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 3267 env->msr_gp_evtsel[i]);
3268 }
0b368a10
JD		 3269 if (has_architectural_pmu_version > 1) {
3270 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
3271 env->msr_global_status);
3272 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
3273 env->msr_global_ovf_ctrl);
3274
3275 /* Now start the PMU. */
3276 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
3277 env->msr_fixed_ctr_ctrl);
3278 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
3279 env->msr_global_ctrl);
3280 }
0d894367 3281 }
da1cc323
EY		 3282 /*
3283 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
3284 * only sync them to KVM on the first cpu
3285 */
3286 if (current_cpu == first_cpu) {
3287 if (has_msr_hv_hypercall) {
3288 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
3289 env->msr_hv_guest_os_id);
3290 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
3291 env->msr_hv_hypercall);
3292 }
2d384d7c 3293 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 3294 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
3295 env->msr_hv_tsc);
3296 }
2d384d7c 3297 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3298 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
3299 env->msr_hv_reenlightenment_control);
3300 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
3301 env->msr_hv_tsc_emulation_control);
3302 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
3303 env->msr_hv_tsc_emulation_status);
3304 }
d8701185 3305#ifdef CONFIG_SYNDBG
73d24074
JD		 3306 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) &&
3307 has_msr_hv_syndbg_options) {
3308 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS,
3309 hyperv_syndbg_query_options());
3310 }
d8701185 3311#endif
eab70139 3312 }
2d384d7c 3313 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3314 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 3315 env->msr_hv_vapic);
eab70139 3316 }
f2a53c9e
AS		 3317 if (has_msr_hv_crash) {
3318 int j;
3319
5e953812 3320 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 3321 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 3322 env->msr_hv_crash_params[j]);
3323
5e953812 3324 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 3325 }
46eb8f98 3326 if (has_msr_hv_runtime) {
9c600a84 3327 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 3328 }
2d384d7c
VK		 3329 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
3330 && hv_vpindex_settable) {
701189e3
RK		 3331 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
3332 hyperv_vp_index(CPU(cpu)));
e9688fab 3333 }
2d384d7c 3334 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3335 int j;
3336
09df29b6
RK		 3337 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
3338
9c600a84 3339 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 3340 env->msr_hv_synic_control);
9c600a84 3341 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 3342 env->msr_hv_synic_evt_page);
9c600a84 3343 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 3344 env->msr_hv_synic_msg_page);
3345
3346 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 3347 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 3348 env->msr_hv_synic_sint[j]);
3349 }
3350 }
ff99aa64
AS		 3351 if (has_msr_hv_stimer) {
3352 int j;
3353
3354 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 3355 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 3356 env->msr_hv_stimer_config[j]);
3357 }
3358
3359 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 3360 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 3361 env->msr_hv_stimer_count[j]);
3362 }
3363 }
1eabfce6 3364 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 3365 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
3366
9c600a84
EH		 3367 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
3368 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
3369 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
3370 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
3371 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
3372 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
3373 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
3374 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
3375 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
3376 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
3377 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
3378 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 3379 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 3380 /* The CPU GPs if we write to a bit above the physical limit of
3381 * the host CPU (and KVM emulates that)
3382 */
3383 uint64_t mask = env->mtrr_var[i].mask;
3384 mask &= phys_mask;
3385
9c600a84
EH		 3386 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
3387 env->mtrr_var[i].base);
112dad69 3388 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 3389 }
3390 }
b77146e9
CP		 3391 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3392 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
3393 0x14, 1, R_EAX) & 0x7;
3394
3395 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
3396 env->msr_rtit_ctrl);
3397 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
3398 env->msr_rtit_status);
3399 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
3400 env->msr_rtit_output_base);
3401 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
3402 env->msr_rtit_output_mask);
3403 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
3404 env->msr_rtit_cr3_match);
3405 for (i = 0; i < addr_num; i++) {
3406 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
3407 env->msr_rtit_addrs[i]);
3408 }
3409 }
6bdf863d 3410
db888065
SC		 3411 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
3412 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
3413 env->msr_ia32_sgxlepubkeyhash[0]);
3414 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
3415 env->msr_ia32_sgxlepubkeyhash[1]);
3416 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
3417 env->msr_ia32_sgxlepubkeyhash[2]);
3418 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
3419 env->msr_ia32_sgxlepubkeyhash[3]);
3420 }
3421
cdec2b75
ZG		 3422 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
3423 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
3424 env->msr_xfd);
3425 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
3426 env->msr_xfd_err);
3427 }
3428
12703d4e
YW		 3429 if (kvm_enabled() && cpu->enable_pmu &&
3430 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
3431 uint64_t depth;
3432 int i, ret;
3433
3434 /*
3a7a27cf
YW		 3435 * Only migrate Arch LBR states when the host Arch LBR depth
3436 * equals that of source guest's, this is to avoid mismatch
3437 * of guest/host config for the msr hence avoid unexpected
3438 * misbehavior.
12703d4e
YW		 3439 */
3440 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
3441
3a7a27cf 3442 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
12703d4e
YW		 3443 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
3444 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
3445
3446 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
3447 if (!env->lbr_records[i].from) {
3448 continue;
3449 }
3450 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i,
3451 env->lbr_records[i].from);
3452 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i,
3453 env->lbr_records[i].to);
3454 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i,
3455 env->lbr_records[i].info);
3456 }
3457 }
3458 }
3459
6bdf863d
JK		 3460 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
3461 * kvm_put_msr_feature_control. */
ea643051 3462 }
20a78b02 3463
57780495 3464 if (env->mcg_cap) {
d8da8574 3465 int i;
b9bec74b 3466
9c600a84
EH		 3467 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
3468 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 3469 if (has_msr_mcg_ext_ctl) {
3470 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3471 }
c34d440a 3472 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3473 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 3474 }
3475 }
1a03675d 3476
420ae1fc 3477 return kvm_buf_set_msrs(cpu);
05330448
AL		 3478}
3479
3480
1bc22652 3481static int kvm_get_fpu(X86CPU *cpu)
05330448 3482{
1bc22652 3483 CPUX86State *env = &cpu->env;
05330448
AL		 3484 struct kvm_fpu fpu;
3485 int i, ret;
3486
1bc22652 3487 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 3488 if (ret < 0) {
05330448 3489 return ret;
b9bec74b 3490 }
05330448
AL		 3491
3492 env->fpstt = (fpu.fsw >> 11) & 7;
3493 env->fpus = fpu.fsw;
3494 env->fpuc = fpu.fcw;
42cc8fa6
JK		 3495 env->fpop = fpu.last_opcode;
3496 env->fpip = fpu.last_ip;
3497 env->fpdp = fpu.last_dp;
b9bec74b
JK		 3498 for (i = 0; i < 8; ++i) {
3499 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3500 }
05330448 3501 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 3502 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 3503 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3504 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 3505 }
05330448
AL		 3506 env->mxcsr = fpu.mxcsr;
3507
3508 return 0;
3509}
3510
1bc22652 3511static int kvm_get_xsave(X86CPU *cpu)
f1665b21 3512{
1bc22652 3513 CPUX86State *env = &cpu->env;
c0198c5f 3514 void *xsave = env->xsave_buf;
e56dd3c7 3515 int type, ret;
f1665b21 3516
28143b40 3517 if (!has_xsave) {
1bc22652 3518 return kvm_get_fpu(cpu);
b9bec74b 3519 }
f1665b21 3520
e56dd3c7
JL		 3521 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
3522 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
0f53994f 3523 if (ret < 0) {
f1665b21 3524 return ret;
0f53994f 3525 }
c0198c5f 3526 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
f1665b21 3527
f1665b21 3528 return 0;
f1665b21
SY		 3529}
3530
1bc22652 3531static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 3532{
1bc22652 3533 CPUX86State *env = &cpu->env;
f1665b21
SY		 3534 int i, ret;
3535 struct kvm_xcrs xcrs;
3536
28143b40 3537 if (!has_xcrs) {
f1665b21 3538 return 0;
b9bec74b 3539 }
f1665b21 3540
1bc22652 3541 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 3542 if (ret < 0) {
f1665b21 3543 return ret;
b9bec74b 3544 }
f1665b21 3545
b9bec74b 3546 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 3547 /* Only support xcr0 now */
0fd53fec
PB		 3548 if (xcrs.xcrs[i].xcr == 0) {
3549 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 3550 break;
3551 }
b9bec74b 3552 }
f1665b21 3553 return 0;
f1665b21
SY		 3554}
3555
1bc22652 3556static int kvm_get_sregs(X86CPU *cpu)
05330448 3557{
1bc22652 3558 CPUX86State *env = &cpu->env;
05330448 3559 struct kvm_sregs sregs;
1520f8bb 3560 int ret;
05330448 3561
1bc22652 3562 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 3563 if (ret < 0) {
05330448 3564 return ret;
b9bec74b 3565 }
05330448 3566
1520f8bb
PB		 3567 /*
3568 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
3569 * always preceded by KVM_GET_VCPU_EVENTS.
3570 */
05330448
AL		 3571
3572 get_seg(&env->segs[R_CS], &sregs.cs);
3573 get_seg(&env->segs[R_DS], &sregs.ds);
3574 get_seg(&env->segs[R_ES], &sregs.es);
3575 get_seg(&env->segs[R_FS], &sregs.fs);
3576 get_seg(&env->segs[R_GS], &sregs.gs);
3577 get_seg(&env->segs[R_SS], &sregs.ss);
3578
3579 get_seg(&env->tr, &sregs.tr);
3580 get_seg(&env->ldt, &sregs.ldt);
3581
3582 env->idt.limit = sregs.idt.limit;
3583 env->idt.base = sregs.idt.base;
3584 env->gdt.limit = sregs.gdt.limit;
3585 env->gdt.base = sregs.gdt.base;
3586
3587 env->cr[0] = sregs.cr0;
3588 env->cr[2] = sregs.cr2;
3589 env->cr[3] = sregs.cr3;
3590 env->cr[4] = sregs.cr4;
3591
05330448 3592 env->efer = sregs.efer;
cce47516
JK		 3593
3594 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 3595 x86_update_hflags(env);
05330448
AL		 3596
3597 return 0;
3598}
3599
8f515d38
ML		 3600static int kvm_get_sregs2(X86CPU *cpu)
3601{
3602 CPUX86State *env = &cpu->env;
3603 struct kvm_sregs2 sregs;
3604 int i, ret;
3605
3606 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
3607 if (ret < 0) {
3608 return ret;
3609 }
3610
3611 get_seg(&env->segs[R_CS], &sregs.cs);
3612 get_seg(&env->segs[R_DS], &sregs.ds);
3613 get_seg(&env->segs[R_ES], &sregs.es);
3614 get_seg(&env->segs[R_FS], &sregs.fs);
3615 get_seg(&env->segs[R_GS], &sregs.gs);
3616 get_seg(&env->segs[R_SS], &sregs.ss);
3617
3618 get_seg(&env->tr, &sregs.tr);
3619 get_seg(&env->ldt, &sregs.ldt);
3620
3621 env->idt.limit = sregs.idt.limit;
3622 env->idt.base = sregs.idt.base;
3623 env->gdt.limit = sregs.gdt.limit;
3624 env->gdt.base = sregs.gdt.base;
3625
3626 env->cr[0] = sregs.cr0;
3627 env->cr[2] = sregs.cr2;
3628 env->cr[3] = sregs.cr3;
3629 env->cr[4] = sregs.cr4;
3630
3631 env->efer = sregs.efer;
3632
3633 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
3634
3635 if (env->pdptrs_valid) {
3636 for (i = 0; i < 4; i++) {
3637 env->pdptrs[i] = sregs.pdptrs[i];
3638 }
3639 }
3640
3641 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3642 x86_update_hflags(env);
3643
3644 return 0;
3645}
3646
1bc22652 3647static int kvm_get_msrs(X86CPU *cpu)
05330448 3648{
1bc22652 3649 CPUX86State *env = &cpu->env;
d71b62a1 3650 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 3651 int ret, i;
fcc35e7c 3652 uint64_t mtrr_top_bits;
05330448 3653
d71b62a1
EH		 3654 kvm_msr_buf_reset(cpu);
3655
9c600a84
EH		 3656 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3657 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3658 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3659 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 3660 if (has_msr_star) {
9c600a84 3661 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 3662 }
c3a3a7d3 3663 if (has_msr_hsave_pa) {
9c600a84 3664 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 3665 }
c9b8f6b6 3666 if (has_msr_tsc_aux) {
9c600a84 3667 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 3668 }
f28558d3 3669 if (has_msr_tsc_adjust) {
9c600a84 3670 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 3671 }
aa82ba54 3672 if (has_msr_tsc_deadline) {
9c600a84 3673 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 3674 }
21e87c46 3675 if (has_msr_misc_enable) {
9c600a84 3676 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 3677 }
fc12d72e 3678 if (has_msr_smbase) {
9c600a84 3679 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 3680 }
e13713db
LA		 3681 if (has_msr_smi_count) {
3682 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3683 }
df67696e 3684 if (has_msr_feature_control) {
9c600a84 3685 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 3686 }
6aa4228b
CQ		 3687 if (has_msr_pkrs) {
3688 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
3689 }
79e9ebeb 3690 if (has_msr_bndcfgs) {
9c600a84 3691 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 3692 }
18cd2c17 3693 if (has_msr_xss) {
9c600a84 3694 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 3695 }
65087997
TX		 3696 if (has_msr_umwait) {
3697 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3698 }
a33a2cfe
PB		 3699 if (has_msr_spec_ctrl) {
3700 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3701 }
cabf9862
ML		 3702 if (has_tsc_scale_msr) {
3703 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
3704 }
3705
2a9758c5
PB		 3706 if (has_msr_tsx_ctrl) {
3707 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3708 }
cfeea0c0
KRW		 3709 if (has_msr_virt_ssbd) {
3710 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3711 }
b8cc45d6 3712 if (!env->tsc_valid) {
9c600a84 3713 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 3714 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 3715 }
3716
05330448 3717#ifdef TARGET_X86_64
25d2e361 3718 if (lm_capable_kernel) {
9c600a84
EH		 3719 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3720 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3721 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3722 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 3723 }
05330448 3724#endif
9c600a84
EH		 3725 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3726 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
db5daafa
VK		 3727 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3728 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3729 }
6615be07
VK		 3730 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3731 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3732 }
55c911a5 3733 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3734 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 3735 }
55c911a5 3736 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3737 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 3738 }
d645e132
MT		 3739 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3740 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3741 }
0b368a10
JD		 3742 if (has_architectural_pmu_version > 0) {
3743 if (has_architectural_pmu_version > 1) {
3744 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3745 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3746 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3747 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3748 }
3749 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3750 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 3751 }
0b368a10 3752 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 3753 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3754 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 3755 }
3756 }
1a03675d 3757
57780495 3758 if (env->mcg_cap) {
9c600a84
EH		 3759 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3760 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 3761 if (has_msr_mcg_ext_ctl) {
3762 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3763 }
b9bec74b 3764 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3765 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 3766 }
57780495 3767 }
57780495 3768
1c90ef26 3769 if (has_msr_hv_hypercall) {
9c600a84
EH		 3770 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3771 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 3772 }
2d384d7c 3773 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3774 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 3775 }
2d384d7c 3776 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 3777 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 3778 }
2d384d7c 3779 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3780 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3781 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3782 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3783 }
73d24074
JD		 3784 if (has_msr_hv_syndbg_options) {
3785 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0);
3786 }
f2a53c9e
AS		 3787 if (has_msr_hv_crash) {
3788 int j;
3789
5e953812 3790 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 3791 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 3792 }
3793 }
46eb8f98 3794 if (has_msr_hv_runtime) {
9c600a84 3795 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 3796 }
2d384d7c 3797 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3798 uint32_t msr;
3799
9c600a84 3800 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 3801 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3802 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 3803 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 3804 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 3805 }
3806 }
ff99aa64
AS		 3807 if (has_msr_hv_stimer) {
3808 uint32_t msr;
3809
3810 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3811 msr++) {
9c600a84 3812 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 3813 }
3814 }
1eabfce6 3815 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 3816 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3817 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3818 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3819 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3820 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3821 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3822 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3823 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3824 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3825 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3826 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3827 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 3828 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 3829 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3830 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 3831 }
3832 }
5ef68987 3833
b77146e9
CP		 3834 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3835 int addr_num =
3836 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3837
3838 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3839 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3840 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3841 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3842 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3843 for (i = 0; i < addr_num; i++) {
3844 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3845 }
3846 }
3847
db888065
SC		 3848 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
3849 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
3850 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
3851 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
3852 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
3853 }
3854
cdec2b75
ZG		 3855 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
3856 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
3857 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
3858 }
3859
12703d4e
YW		 3860 if (kvm_enabled() && cpu->enable_pmu &&
3861 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
3a7a27cf
YW		 3862 uint64_t depth;
3863 int i, ret;
12703d4e 3864
3a7a27cf
YW		 3865 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
3866 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
12703d4e
YW		 3867 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
3868 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
3869
3870 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
3871 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0);
3872 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0);
3873 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0);
3874 }
3875 }
3876 }
3877
d71b62a1 3878 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 3879 if (ret < 0) {
05330448 3880 return ret;
b9bec74b 3881 }
05330448 3882
c70b11d1
EH		 3883 if (ret < cpu->kvm_msr_buf->nmsrs) {
3884 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3885 error_report("error: failed to get MSR 0x%" PRIx32,
3886 (uint32_t)e->index);
3887 }
3888
9c600a84 3889 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 3890 /*
3891 * MTRR masks: Each mask consists of 5 parts
3892 * a 10..0: must be zero
3893 * b 11 : valid bit
3894 * c n-1.12: actual mask bits
3895 * d 51..n: reserved must be zero
3896 * e 63.52: reserved must be zero
3897 *
3898 * 'n' is the number of physical bits supported by the CPU and is
3899 * apparently always <= 52. We know our 'n' but don't know what
3900 * the destinations 'n' is; it might be smaller, in which case
3901 * it masks (c) on loading. It might be larger, in which case
3902 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3903 * we're migrating to.
3904 */
3905
3906 if (cpu->fill_mtrr_mask) {
3907 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3908 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3909 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3910 } else {
3911 mtrr_top_bits = 0;
3912 }
3913
05330448 3914 for (i = 0; i < ret; i++) {
0d894367
PB		 3915 uint32_t index = msrs[i].index;
3916 switch (index) {
05330448
AL		 3917 case MSR_IA32_SYSENTER_CS:
3918 env->sysenter_cs = msrs[i].data;
3919 break;
3920 case MSR_IA32_SYSENTER_ESP:
3921 env->sysenter_esp = msrs[i].data;
3922 break;
3923 case MSR_IA32_SYSENTER_EIP:
3924 env->sysenter_eip = msrs[i].data;
3925 break;
0c03266a
JK		 3926 case MSR_PAT:
3927 env->pat = msrs[i].data;
3928 break;
05330448
AL		 3929 case MSR_STAR:
3930 env->star = msrs[i].data;
3931 break;
3932#ifdef TARGET_X86_64
3933 case MSR_CSTAR:
3934 env->cstar = msrs[i].data;
3935 break;
3936 case MSR_KERNELGSBASE:
3937 env->kernelgsbase = msrs[i].data;
3938 break;
3939 case MSR_FMASK:
3940 env->fmask = msrs[i].data;
3941 break;
3942 case MSR_LSTAR:
3943 env->lstar = msrs[i].data;
3944 break;
3945#endif
3946 case MSR_IA32_TSC:
3947 env->tsc = msrs[i].data;
3948 break;
c9b8f6b6
AS		 3949 case MSR_TSC_AUX:
3950 env->tsc_aux = msrs[i].data;
3951 break;
f28558d3
WA		 3952 case MSR_TSC_ADJUST:
3953 env->tsc_adjust = msrs[i].data;
3954 break;
aa82ba54
LJ		 3955 case MSR_IA32_TSCDEADLINE:
3956 env->tsc_deadline = msrs[i].data;
3957 break;
aa851e36
MT		 3958 case MSR_VM_HSAVE_PA:
3959 env->vm_hsave = msrs[i].data;
3960 break;
1a03675d
GC		 3961 case MSR_KVM_SYSTEM_TIME:
3962 env->system_time_msr = msrs[i].data;
3963 break;
3964 case MSR_KVM_WALL_CLOCK:
3965 env->wall_clock_msr = msrs[i].data;
3966 break;
57780495
MT		 3967 case MSR_MCG_STATUS:
3968 env->mcg_status = msrs[i].data;
3969 break;
3970 case MSR_MCG_CTL:
3971 env->mcg_ctl = msrs[i].data;
3972 break;
87f8b626
AR		 3973 case MSR_MCG_EXT_CTL:
3974 env->mcg_ext_ctl = msrs[i].data;
3975 break;
21e87c46
AK		 3976 case MSR_IA32_MISC_ENABLE:
3977 env->msr_ia32_misc_enable = msrs[i].data;
3978 break;
fc12d72e
PB		 3979 case MSR_IA32_SMBASE:
3980 env->smbase = msrs[i].data;
3981 break;
e13713db
LA		 3982 case MSR_SMI_COUNT:
3983 env->msr_smi_count = msrs[i].data;
3984 break;
0779caeb
ACL		 3985 case MSR_IA32_FEATURE_CONTROL:
3986 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3987 break;
79e9ebeb
LJ		 3988 case MSR_IA32_BNDCFGS:
3989 env->msr_bndcfgs = msrs[i].data;
3990 break;
18cd2c17
WL		 3991 case MSR_IA32_XSS:
3992 env->xss = msrs[i].data;
3993 break;
65087997
TX		 3994 case MSR_IA32_UMWAIT_CONTROL:
3995 env->umwait = msrs[i].data;
3996 break;
6aa4228b
CQ		 3997 case MSR_IA32_PKRS:
3998 env->pkrs = msrs[i].data;
3999 break;
57780495 4000 default:
57780495
MT		 4001 if (msrs[i].index >= MSR_MC0_CTL &&
4002 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
4003 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 4004 }
d8da8574 4005 break;
f6584ee2
GN		 4006 case MSR_KVM_ASYNC_PF_EN:
4007 env->async_pf_en_msr = msrs[i].data;
4008 break;
db5daafa
VK		 4009 case MSR_KVM_ASYNC_PF_INT:
4010 env->async_pf_int_msr = msrs[i].data;
4011 break;
bc9a839d
MT		 4012 case MSR_KVM_PV_EOI_EN:
4013 env->pv_eoi_en_msr = msrs[i].data;
4014 break;
917367aa
MT		 4015 case MSR_KVM_STEAL_TIME:
4016 env->steal_time_msr = msrs[i].data;
4017 break;
d645e132
MT		 4018 case MSR_KVM_POLL_CONTROL: {
4019 env->poll_control_msr = msrs[i].data;
4020 break;
4021 }
0d894367
PB		 4022 case MSR_CORE_PERF_FIXED_CTR_CTRL:
4023 env->msr_fixed_ctr_ctrl = msrs[i].data;
4024 break;
4025 case MSR_CORE_PERF_GLOBAL_CTRL:
4026 env->msr_global_ctrl = msrs[i].data;
4027 break;
4028 case MSR_CORE_PERF_GLOBAL_STATUS:
4029 env->msr_global_status = msrs[i].data;
4030 break;
4031 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
4032 env->msr_global_ovf_ctrl = msrs[i].data;
4033 break;
4034 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
4035 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
4036 break;
4037 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
4038 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
4039 break;
4040 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
4041 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
4042 break;
1c90ef26
VR		 4043 case HV_X64_MSR_HYPERCALL:
4044 env->msr_hv_hypercall = msrs[i].data;
4045 break;
4046 case HV_X64_MSR_GUEST_OS_ID:
4047 env->msr_hv_guest_os_id = msrs[i].data;
4048 break;
5ef68987
VR		 4049 case HV_X64_MSR_APIC_ASSIST_PAGE:
4050 env->msr_hv_vapic = msrs[i].data;
4051 break;
48a5f3bc
VR		 4052 case HV_X64_MSR_REFERENCE_TSC:
4053 env->msr_hv_tsc = msrs[i].data;
4054 break;
f2a53c9e
AS		 4055 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4056 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
4057 break;
46eb8f98
AS		 4058 case HV_X64_MSR_VP_RUNTIME:
4059 env->msr_hv_runtime = msrs[i].data;
4060 break;
866eea9a
AS		 4061 case HV_X64_MSR_SCONTROL:
4062 env->msr_hv_synic_control = msrs[i].data;
4063 break;
866eea9a
AS		 4064 case HV_X64_MSR_SIEFP:
4065 env->msr_hv_synic_evt_page = msrs[i].data;
4066 break;
4067 case HV_X64_MSR_SIMP:
4068 env->msr_hv_synic_msg_page = msrs[i].data;
4069 break;
4070 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
4071 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 4072 break;
4073 case HV_X64_MSR_STIMER0_CONFIG:
4074 case HV_X64_MSR_STIMER1_CONFIG:
4075 case HV_X64_MSR_STIMER2_CONFIG:
4076 case HV_X64_MSR_STIMER3_CONFIG:
4077 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
4078 msrs[i].data;
4079 break;
4080 case HV_X64_MSR_STIMER0_COUNT:
4081 case HV_X64_MSR_STIMER1_COUNT:
4082 case HV_X64_MSR_STIMER2_COUNT:
4083 case HV_X64_MSR_STIMER3_COUNT:
4084 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
4085 msrs[i].data;
866eea9a 4086 break;
ba6a4fd9
VK		 4087 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4088 env->msr_hv_reenlightenment_control = msrs[i].data;
4089 break;
4090 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4091 env->msr_hv_tsc_emulation_control = msrs[i].data;
4092 break;
4093 case HV_X64_MSR_TSC_EMULATION_STATUS:
4094 env->msr_hv_tsc_emulation_status = msrs[i].data;
4095 break;
73d24074
JD		 4096 case HV_X64_MSR_SYNDBG_OPTIONS:
4097 env->msr_hv_syndbg_options = msrs[i].data;
4098 break;
d1ae67f6
AW		 4099 case MSR_MTRRdefType:
4100 env->mtrr_deftype = msrs[i].data;
4101 break;
4102 case MSR_MTRRfix64K_00000:
4103 env->mtrr_fixed[0] = msrs[i].data;
4104 break;
4105 case MSR_MTRRfix16K_80000:
4106 env->mtrr_fixed[1] = msrs[i].data;
4107 break;
4108 case MSR_MTRRfix16K_A0000:
4109 env->mtrr_fixed[2] = msrs[i].data;
4110 break;
4111 case MSR_MTRRfix4K_C0000:
4112 env->mtrr_fixed[3] = msrs[i].data;
4113 break;
4114 case MSR_MTRRfix4K_C8000:
4115 env->mtrr_fixed[4] = msrs[i].data;
4116 break;
4117 case MSR_MTRRfix4K_D0000:
4118 env->mtrr_fixed[5] = msrs[i].data;
4119 break;
4120 case MSR_MTRRfix4K_D8000:
4121 env->mtrr_fixed[6] = msrs[i].data;
4122 break;
4123 case MSR_MTRRfix4K_E0000:
4124 env->mtrr_fixed[7] = msrs[i].data;
4125 break;
4126 case MSR_MTRRfix4K_E8000:
4127 env->mtrr_fixed[8] = msrs[i].data;
4128 break;
4129 case MSR_MTRRfix4K_F0000:
4130 env->mtrr_fixed[9] = msrs[i].data;
4131 break;
4132 case MSR_MTRRfix4K_F8000:
4133 env->mtrr_fixed[10] = msrs[i].data;
4134 break;
4135 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
4136 if (index & 1) {
fcc35e7c
DDAG		 4137 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
4138 mtrr_top_bits;
d1ae67f6
AW		 4139 } else {
4140 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
4141 }
4142 break;
a33a2cfe
PB		 4143 case MSR_IA32_SPEC_CTRL:
4144 env->spec_ctrl = msrs[i].data;
4145 break;
cabf9862
ML		 4146 case MSR_AMD64_TSC_RATIO:
4147 env->amd_tsc_scale_msr = msrs[i].data;
4148 break;
2a9758c5
PB		 4149 case MSR_IA32_TSX_CTRL:
4150 env->tsx_ctrl = msrs[i].data;
4151 break;
cfeea0c0
KRW		 4152 case MSR_VIRT_SSBD:
4153 env->virt_ssbd = msrs[i].data;
4154 break;
b77146e9
CP		 4155 case MSR_IA32_RTIT_CTL:
4156 env->msr_rtit_ctrl = msrs[i].data;
4157 break;
4158 case MSR_IA32_RTIT_STATUS:
4159 env->msr_rtit_status = msrs[i].data;
4160 break;
4161 case MSR_IA32_RTIT_OUTPUT_BASE:
4162 env->msr_rtit_output_base = msrs[i].data;
4163 break;
4164 case MSR_IA32_RTIT_OUTPUT_MASK:
4165 env->msr_rtit_output_mask = msrs[i].data;
4166 break;
4167 case MSR_IA32_RTIT_CR3_MATCH:
4168 env->msr_rtit_cr3_match = msrs[i].data;
4169 break;
4170 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
4171 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
4172 break;
db888065
SC		 4173 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
4174 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
4175 msrs[i].data;
4176 break;
cdec2b75
ZG		 4177 case MSR_IA32_XFD:
4178 env->msr_xfd = msrs[i].data;
4179 break;
4180 case MSR_IA32_XFD_ERR:
4181 env->msr_xfd_err = msrs[i].data;
4182 break;
12703d4e
YW		 4183 case MSR_ARCH_LBR_CTL:
4184 env->msr_lbr_ctl = msrs[i].data;
4185 break;
4186 case MSR_ARCH_LBR_DEPTH:
4187 env->msr_lbr_depth = msrs[i].data;
4188 break;
4189 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31:
4190 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data;
4191 break;
4192 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31:
4193 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data;
4194 break;
4195 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
4196 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
4197 break;
05330448
AL		 4198 }
4199 }
4200
4201 return 0;
4202}
4203
1bc22652 4204static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 4205{
1bc22652 4206 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 4207
1bc22652 4208 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 4209}
4210
23d02d9b 4211static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 4212{
259186a7 4213 CPUState *cs = CPU(cpu);
23d02d9b 4214 CPUX86State *env = &cpu->env;
9bdbe550
HB		 4215 struct kvm_mp_state mp_state;
4216 int ret;
4217
259186a7 4218 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 4219 if (ret < 0) {
4220 return ret;
4221 }
4222 env->mp_state = mp_state.mp_state;
c14750e8 4223 if (kvm_irqchip_in_kernel()) {
259186a7 4224 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 4225 }
9bdbe550
HB		 4226 return 0;
4227}
4228
1bc22652 4229static int kvm_get_apic(X86CPU *cpu)
680c1c6f 4230{
02e51483 4231 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 4232 struct kvm_lapic_state kapic;
4233 int ret;
4234
3d4b2649 4235 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 4236 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 4237 if (ret < 0) {
4238 return ret;
4239 }
4240
4241 kvm_get_apic_state(apic, &kapic);
4242 }
4243 return 0;
4244}
4245
1bc22652 4246static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 4247{
fc12d72e 4248 CPUState *cs = CPU(cpu);
1bc22652 4249 CPUX86State *env = &cpu->env;
076796f8 4250 struct kvm_vcpu_events events = {};
a0fb002c
JK		 4251
4252 if (!kvm_has_vcpu_events()) {
4253 return 0;
4254 }
4255
fd13f23b
LA		 4256 events.flags = 0;
4257
4258 if (has_exception_payload) {
4259 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4260 events.exception.pending = env->exception_pending;
4261 events.exception_has_payload = env->exception_has_payload;
4262 events.exception_payload = env->exception_payload;
4263 }
4264 events.exception.nr = env->exception_nr;
4265 events.exception.injected = env->exception_injected;
a0fb002c
JK		 4266 events.exception.has_error_code = env->has_error_code;
4267 events.exception.error_code = env->error_code;
4268
4269 events.interrupt.injected = (env->interrupt_injected >= 0);
4270 events.interrupt.nr = env->interrupt_injected;
4271 events.interrupt.soft = env->soft_interrupt;
4272
4273 events.nmi.injected = env->nmi_injected;
4274 events.nmi.pending = env->nmi_pending;
4275 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
4276
4277 events.sipi_vector = env->sipi_vector;
4278
fc12d72e
PB		 4279 if (has_msr_smbase) {
4280 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
4281 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
4282 if (kvm_irqchip_in_kernel()) {
4283 /* As soon as these are moved to the kernel, remove them
4284 * from cs->interrupt_request.
4285 */
4286 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
4287 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
4288 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
4289 } else {
4290 /* Keep these in cs->interrupt_request. */
4291 events.smi.pending = 0;
4292 events.smi.latched_init = 0;
4293 }
fc3a1fd7
DDAG		 4294 /* Stop SMI delivery on old machine types to avoid a reboot
4295 * on an inward migration of an old VM.
4296 */
4297 if (!cpu->kvm_no_smi_migration) {
4298 events.flags |= KVM_VCPUEVENT_VALID_SMM;
4299 }
fc12d72e
PB		 4300 }
4301
ea643051 4302 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 4303 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
4304 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
4305 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
4306 }
ea643051 4307 }
aee028b9 4308
12f89a39
CQ		 4309 if (has_triple_fault_event) {
4310 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
4311 events.triple_fault.pending = env->triple_fault_pending;
4312 }
4313
1bc22652 4314 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 4315}
4316
1bc22652 4317static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 4318{
1bc22652 4319 CPUX86State *env = &cpu->env;
a0fb002c
JK		 4320 struct kvm_vcpu_events events;
4321 int ret;
4322
4323 if (!kvm_has_vcpu_events()) {
4324 return 0;
4325 }
4326
fc12d72e 4327 memset(&events, 0, sizeof(events));
1bc22652 4328 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 4329 if (ret < 0) {
4330 return ret;
4331 }
fd13f23b
LA		 4332
4333 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4334 env->exception_pending = events.exception.pending;
4335 env->exception_has_payload = events.exception_has_payload;
4336 env->exception_payload = events.exception_payload;
4337 } else {
4338 env->exception_pending = 0;
4339 env->exception_has_payload = false;
4340 }
4341 env->exception_injected = events.exception.injected;
4342 env->exception_nr =
4343 (env->exception_pending || env->exception_injected) ?
4344 events.exception.nr : -1;
a0fb002c
JK		 4345 env->has_error_code = events.exception.has_error_code;
4346 env->error_code = events.exception.error_code;
4347
4348 env->interrupt_injected =
4349 events.interrupt.injected ? events.interrupt.nr : -1;
4350 env->soft_interrupt = events.interrupt.soft;
4351
4352 env->nmi_injected = events.nmi.injected;
4353 env->nmi_pending = events.nmi.pending;
4354 if (events.nmi.masked) {
4355 env->hflags2 |= HF2_NMI_MASK;
4356 } else {
4357 env->hflags2 &= ~HF2_NMI_MASK;
4358 }
4359
fc12d72e
PB		 4360 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
4361 if (events.smi.smm) {
4362 env->hflags |= HF_SMM_MASK;
4363 } else {
4364 env->hflags &= ~HF_SMM_MASK;
4365 }
4366 if (events.smi.pending) {
4367 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
4368 } else {
4369 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
4370 }
4371 if (events.smi.smm_inside_nmi) {
4372 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
4373 } else {
4374 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
4375 }
4376 if (events.smi.latched_init) {
4377 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
4378 } else {
4379 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
4380 }
4381 }
4382
12f89a39
CQ		 4383 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
4384 env->triple_fault_pending = events.triple_fault.pending;
4385 }
4386
a0fb002c 4387 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 4388
4389 return 0;
4390}
4391
1bc22652 4392static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 4393{
ed2803da 4394 CPUState *cs = CPU(cpu);
1bc22652 4395 CPUX86State *env = &cpu->env;
b0b1d690 4396 int ret = 0;
b0b1d690
JK		 4397 unsigned long reinject_trap = 0;
4398
4399 if (!kvm_has_vcpu_events()) {
fd13f23b 4400 if (env->exception_nr == EXCP01_DB) {
b0b1d690 4401 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 4402 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 4403 reinject_trap = KVM_GUESTDBG_INJECT_BP;
4404 }
fd13f23b 4405 kvm_reset_exception(env);
b0b1d690
JK		 4406 }
4407
4408 /*
4409 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
4410 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
4411 * by updating the debug state once again if single-stepping is on.
4412 * Another reason to call kvm_update_guest_debug here is a pending debug
4413 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
4414 * reinject them via SET_GUEST_DEBUG.
4415 */
4416 if (reinject_trap ||
ed2803da 4417 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 4418 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 4419 }
b0b1d690
JK		 4420 return ret;
4421}
4422
1bc22652 4423static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 4424{
1bc22652 4425 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 4426 struct kvm_debugregs dbgregs;
4427 int i;
4428
4429 if (!kvm_has_debugregs()) {
4430 return 0;
4431 }
4432
1f670a95 4433 memset(&dbgregs, 0, sizeof(dbgregs));
ff44f1a3
JK		 4434 for (i = 0; i < 4; i++) {
4435 dbgregs.db[i] = env->dr[i];
4436 }
4437 dbgregs.dr6 = env->dr[6];
4438 dbgregs.dr7 = env->dr[7];
4439 dbgregs.flags = 0;
4440
1bc22652 4441 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 4442}
4443
1bc22652 4444static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 4445{
1bc22652 4446 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 4447 struct kvm_debugregs dbgregs;
4448 int i, ret;
4449
4450 if (!kvm_has_debugregs()) {
4451 return 0;
4452 }
4453
1bc22652 4454 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 4455 if (ret < 0) {
b9bec74b 4456 return ret;
ff44f1a3
JK		 4457 }
4458 for (i = 0; i < 4; i++) {
4459 env->dr[i] = dbgregs.db[i];
4460 }
4461 env->dr[4] = env->dr[6] = dbgregs.dr6;
4462 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 4463
4464 return 0;
4465}
4466
ebbfef2f
LA		 4467static int kvm_put_nested_state(X86CPU *cpu)
4468{
4469 CPUX86State *env = &cpu->env;
4470 int max_nested_state_len = kvm_max_nested_state_length();
4471
1e44f3ab 4472 if (!env->nested_state) {
ebbfef2f
LA		 4473 return 0;
4474 }
4475
b16c0e20
PB		 4476 /*
4477 * Copy flags that are affected by reset from env->hflags and env->hflags2.
4478 */
4479 if (env->hflags & HF_GUEST_MASK) {
4480 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
4481 } else {
4482 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
4483 }
0baa4b44
VK		 4484
4485 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
4486 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
b16c0e20
PB		 4487 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
4488 } else {
4489 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
4490 }
4491
ebbfef2f
LA		 4492 assert(env->nested_state->size <= max_nested_state_len);
4493 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
4494}
4495
4496static int kvm_get_nested_state(X86CPU *cpu)
4497{
4498 CPUX86State *env = &cpu->env;
4499 int max_nested_state_len = kvm_max_nested_state_length();
4500 int ret;
4501
1e44f3ab 4502 if (!env->nested_state) {
ebbfef2f
LA		 4503 return 0;
4504 }
4505
4506 /*
4507 * It is possible that migration restored a smaller size into
4508 * nested_state->hdr.size than what our kernel support.
4509 * We preserve migration origin nested_state->hdr.size for
4510 * call to KVM_SET_NESTED_STATE but wish that our next call
4511 * to KVM_GET_NESTED_STATE will use max size our kernel support.
4512 */
4513 env->nested_state->size = max_nested_state_len;
4514
4515 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
4516 if (ret < 0) {
4517 return ret;
4518 }
4519
b16c0e20
PB		 4520 /*
4521 * Copy flags that are affected by reset to env->hflags and env->hflags2.
4522 */
ebbfef2f
LA		 4523 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
4524 env->hflags |= HF_GUEST_MASK;
4525 } else {
4526 env->hflags &= ~HF_GUEST_MASK;
4527 }
0baa4b44
VK		 4528
4529 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
4530 if (cpu_has_svm(env)) {
4531 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
4532 env->hflags2 |= HF2_GIF_MASK;
4533 } else {
4534 env->hflags2 &= ~HF2_GIF_MASK;
4535 }
b16c0e20 4536 }
ebbfef2f
LA		 4537
4538 return ret;
4539}
4540
20d695a9 4541int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 4542{
20d695a9 4543 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 4544 int ret;
4545
2fa45344 4546 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 4547
45ed68a1
VK		 4548 /*
4549 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX
4550 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also
4551 * preceed kvm_put_nested_state() when 'real' nested state is set.
4552 */
4553 if (level >= KVM_PUT_RESET_STATE) {
4554 ret = kvm_put_msr_feature_control(x86_cpu);
4555 if (ret < 0) {
4556 return ret;
4557 }
4558 }
4559
b16c0e20 4560 /* must be before kvm_put_nested_state so that EFER.SVME is set */
8f515d38 4561 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
b16c0e20
PB		 4562 if (ret < 0) {
4563 return ret;
4564 }
4565
48e1a45c 4566 if (level >= KVM_PUT_RESET_STATE) {
bec7156a
JK		 4567 ret = kvm_put_nested_state(x86_cpu);
4568 if (ret < 0) {
4569 return ret;
4570 }
6bdf863d
JK		 4571 }
4572
36f96c4b
HZ		 4573 if (level == KVM_PUT_FULL_STATE) {
4574 /* We don't check for kvm_arch_set_tsc_khz() errors here,
4575 * because TSC frequency mismatch shouldn't abort migration,
4576 * unless the user explicitly asked for a more strict TSC
4577 * setting (e.g. using an explicit "tsc-freq" option).
4578 */
4579 kvm_arch_set_tsc_khz(cpu);
4580 }
4581
1bc22652 4582 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 4583 if (ret < 0) {
05330448 4584 return ret;
b9bec74b 4585 }
1bc22652 4586 ret = kvm_put_xsave(x86_cpu);
b9bec74b 4587 if (ret < 0) {
f1665b21 4588 return ret;
b9bec74b 4589 }
1bc22652 4590 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 4591 if (ret < 0) {
05330448 4592 return ret;
b9bec74b 4593 }
ab443475 4594 /* must be before kvm_put_msrs */
1bc22652 4595 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 4596 if (ret < 0) {
4597 return ret;
4598 }
1bc22652 4599 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 4600 if (ret < 0) {
05330448 4601 return ret;
b9bec74b 4602 }
4fadfa00
PH		 4603 ret = kvm_put_vcpu_events(x86_cpu, level);
4604 if (ret < 0) {
4605 return ret;
4606 }
ea643051 4607 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 4608 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 4609 if (ret < 0) {
680c1c6f
JK		 4610 return ret;
4611 }
ea643051 4612 }
7477cd38
MT		 4613
4614 ret = kvm_put_tscdeadline_msr(x86_cpu);
4615 if (ret < 0) {
4616 return ret;
4617 }
1bc22652 4618 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 4619 if (ret < 0) {
b0b1d690 4620 return ret;
b9bec74b 4621 }
b0b1d690 4622 /* must be last */
1bc22652 4623 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 4624 if (ret < 0) {
ff44f1a3 4625 return ret;
b9bec74b 4626 }
05330448
AL		 4627 return 0;
4628}
4629
20d695a9 4630int kvm_arch_get_registers(CPUState *cs)
05330448 4631{
20d695a9 4632 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 4633 int ret;
4634
20d695a9 4635 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 4636
4fadfa00 4637 ret = kvm_get_vcpu_events(cpu);
b9bec74b 4638 if (ret < 0) {
f4f1110e 4639 goto out;
b9bec74b 4640 }
4fadfa00
PH		 4641 /*
4642 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4643 * KVM_GET_REGS and KVM_GET_SREGS.
4644 */
4645 ret = kvm_get_mp_state(cpu);
b9bec74b 4646 if (ret < 0) {
f4f1110e 4647 goto out;
b9bec74b 4648 }
4fadfa00 4649 ret = kvm_getput_regs(cpu, 0);
b9bec74b 4650 if (ret < 0) {
f4f1110e 4651 goto out;
b9bec74b 4652 }
4fadfa00 4653 ret = kvm_get_xsave(cpu);
b9bec74b 4654 if (ret < 0) {
f4f1110e 4655 goto out;
b9bec74b 4656 }
4fadfa00 4657 ret = kvm_get_xcrs(cpu);
b9bec74b 4658 if (ret < 0) {
f4f1110e 4659 goto out;
b9bec74b 4660 }
8f515d38 4661 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
b9bec74b 4662 if (ret < 0) {
f4f1110e 4663 goto out;
b9bec74b 4664 }
4fadfa00 4665 ret = kvm_get_msrs(cpu);
680c1c6f 4666 if (ret < 0) {
f4f1110e 4667 goto out;
680c1c6f 4668 }
4fadfa00 4669 ret = kvm_get_apic(cpu);
b9bec74b 4670 if (ret < 0) {
f4f1110e 4671 goto out;
b9bec74b 4672 }
1bc22652 4673 ret = kvm_get_debugregs(cpu);
b9bec74b 4674 if (ret < 0) {
f4f1110e 4675 goto out;
b9bec74b 4676 }
ebbfef2f
LA		 4677 ret = kvm_get_nested_state(cpu);
4678 if (ret < 0) {
4679 goto out;
4680 }
f4f1110e
RH		 4681 ret = 0;
4682 out:
4683 cpu_sync_bndcs_hflags(&cpu->env);
4684 return ret;
05330448
AL		 4685}
4686
20d695a9 4687void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 4688{
20d695a9
AF		 4689 X86CPU *x86_cpu = X86_CPU(cpu);
4690 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 4691 int ret;
4692
276ce815 4693 /* Inject NMI */
fc12d72e
PB		 4694 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4695 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4696 qemu_mutex_lock_iothread();
4697 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4698 qemu_mutex_unlock_iothread();
4699 DPRINTF("injected NMI\n");
4700 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4701 if (ret < 0) {
4702 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4703 strerror(-ret));
4704 }
4705 }
4706 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4707 qemu_mutex_lock_iothread();
4708 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4709 qemu_mutex_unlock_iothread();
4710 DPRINTF("injected SMI\n");
4711 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4712 if (ret < 0) {
4713 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4714 strerror(-ret));
4715 }
ce377af3 4716 }
276ce815
LJ		 4717 }
4718
15eafc2e 4719 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 4720 qemu_mutex_lock_iothread();
4721 }
4722
e0723c45
PB		 4723 /* Force the VCPU out of its inner loop to process any INIT requests
4724 * or (for userspace APIC, but it is cheap to combine the checks here)
4725 * pending TPR access reports.
4726 */
4727 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 4728 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4729 !(env->hflags & HF_SMM_MASK)) {
4730 cpu->exit_request = 1;
4731 }
4732 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4733 cpu->exit_request = 1;
4734 }
e0723c45 4735 }
05330448 4736
15eafc2e 4737 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 4738 /* Try to inject an interrupt if the guest can accept it */
4739 if (run->ready_for_interrupt_injection &&
259186a7 4740 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 4741 (env->eflags & IF_MASK)) {
4742 int irq;
4743
259186a7 4744 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 4745 irq = cpu_get_pic_interrupt(env);
4746 if (irq >= 0) {
4747 struct kvm_interrupt intr;
4748
4749 intr.irq = irq;
db1669bc 4750 DPRINTF("injected interrupt %d\n", irq);
1bc22652 4751 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 4752 if (ret < 0) {
4753 fprintf(stderr,
4754 "KVM: injection failed, interrupt lost (%s)\n",
4755 strerror(-ret));
4756 }
db1669bc
JK		 4757 }
4758 }
05330448 4759
db1669bc
JK		 4760 /* If we have an interrupt but the guest is not ready to receive an
4761 * interrupt, request an interrupt window exit. This will
4762 * cause a return to userspace as soon as the guest is ready to
4763 * receive interrupts. */
259186a7 4764 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 4765 run->request_interrupt_window = 1;
4766 } else {
4767 run->request_interrupt_window = 0;
4768 }
4769
4770 DPRINTF("setting tpr\n");
02e51483 4771 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 4772
4773 qemu_mutex_unlock_iothread();
db1669bc 4774 }
05330448
AL		 4775}
4776
035d1ef2
CQ		 4777static void kvm_rate_limit_on_bus_lock(void)
4778{
4779 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
4780
4781 if (delay_ns) {
4782 g_usleep(delay_ns / SCALE_US);
4783 }
4784}
4785
4c663752 4786MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 4787{
20d695a9
AF		 4788 X86CPU *x86_cpu = X86_CPU(cpu);
4789 CPUX86State *env = &x86_cpu->env;
4790
fc12d72e
PB		 4791 if (run->flags & KVM_RUN_X86_SMM) {
4792 env->hflags |= HF_SMM_MASK;
4793 } else {
f5c052b9 4794 env->hflags &= ~HF_SMM_MASK;
fc12d72e 4795 }
b9bec74b 4796 if (run->if_flag) {
05330448 4797 env->eflags |= IF_MASK;
b9bec74b 4798 } else {
05330448 4799 env->eflags &= ~IF_MASK;
b9bec74b 4800 }
035d1ef2
CQ		 4801 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
4802 kvm_rate_limit_on_bus_lock();
4803 }
4b8523ee
JK		 4804
4805 /* We need to protect the apic state against concurrent accesses from
4806 * different threads in case the userspace irqchip is used. */
4807 if (!kvm_irqchip_in_kernel()) {
4808 qemu_mutex_lock_iothread();
4809 }
02e51483
CF		 4810 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4811 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 4812 if (!kvm_irqchip_in_kernel()) {
4813 qemu_mutex_unlock_iothread();
4814 }
f794aa4a 4815 return cpu_get_mem_attrs(env);
05330448
AL		 4816}
4817
20d695a9 4818int kvm_arch_process_async_events(CPUState *cs)
0af691d7 4819{
20d695a9
AF		 4820 X86CPU *cpu = X86_CPU(cs);
4821 CPUX86State *env = &cpu->env;
232fc23b 4822
259186a7 4823 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 4824 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4825 assert(env->mcg_cap);
4826
259186a7 4827 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 4828
dd1750d7 4829 kvm_cpu_synchronize_state(cs);
ab443475 4830
fd13f23b 4831 if (env->exception_nr == EXCP08_DBLE) {
ab443475 4832 /* this means triple fault */
cf83f140 4833 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 4834 cs->exit_request = 1;
ab443475
JK		 4835 return 0;
4836 }
fd13f23b 4837 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 4838 env->has_error_code = 0;
4839
259186a7 4840 cs->halted = 0;
ab443475
JK		 4841 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4842 env->mp_state = KVM_MP_STATE_RUNNABLE;
4843 }
4844 }
4845
fc12d72e
PB		 4846 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4847 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 4848 kvm_cpu_synchronize_state(cs);
4849 do_cpu_init(cpu);
4850 }
4851
db1669bc
JK		 4852 if (kvm_irqchip_in_kernel()) {
4853 return 0;
4854 }
4855
259186a7
AF		 4856 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4857 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 4858 apic_poll_irq(cpu->apic_state);
5d62c43a 4859 }
259186a7 4860 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 4861 (env->eflags & IF_MASK)) ||
259186a7
AF		 4862 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4863 cs->halted = 0;
6792a57b 4864 }
259186a7 4865 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 4866 kvm_cpu_synchronize_state(cs);
232fc23b 4867 do_cpu_sipi(cpu);
0af691d7 4868 }
259186a7
AF		 4869 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4870 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 4871 kvm_cpu_synchronize_state(cs);
02e51483 4872 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 4873 env->tpr_access_type);
4874 }
0af691d7 4875
259186a7 4876 return cs->halted;
0af691d7
MT		 4877}
4878
839b5630 4879static int kvm_handle_halt(X86CPU *cpu)
05330448 4880{
259186a7 4881 CPUState *cs = CPU(cpu);
839b5630
AF		 4882 CPUX86State *env = &cpu->env;
4883
259186a7 4884 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 4885 (env->eflags & IF_MASK)) &&
259186a7
AF		 4886 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4887 cs->halted = 1;
bb4ea393 4888 return EXCP_HLT;
05330448
AL		 4889 }
4890
bb4ea393 4891 return 0;
05330448
AL		 4892}
4893
f7575c96 4894static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 4895{
f7575c96
AF		 4896 CPUState *cs = CPU(cpu);
4897 struct kvm_run *run = cs->kvm_run;
d362e757 4898
02e51483 4899 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 4900 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4901 : TPR_ACCESS_READ);
4902 return 1;
4903}
4904
f17ec444 4905int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 4906{
38972938 4907 static const uint8_t int3 = 0xcc;
64bf3f4e 4908
f17ec444
AF		 4909 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4910 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 4911 return -EINVAL;
b9bec74b 4912 }
e22a25c9
AL		 4913 return 0;
4914}
4915
f17ec444 4916int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 4917{
4918 uint8_t int3;
4919
c6986f16
PB		 4920 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
4921 return -EINVAL;
4922 }
4923 if (int3 != 0xcc) {
4924 return 0;
4925 }
4926 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 4927 return -EINVAL;
b9bec74b 4928 }
e22a25c9
AL		 4929 return 0;
4930}
4931
4932static struct {
4933 target_ulong addr;
4934 int len;
4935 int type;
4936} hw_breakpoint[4];
4937
4938static int nb_hw_breakpoint;
4939
4940static int find_hw_breakpoint(target_ulong addr, int len, int type)
4941{
4942 int n;
4943
b9bec74b 4944 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 4945 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 4946 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 4947 return n;
b9bec74b
JK		 4948 }
4949 }
e22a25c9
AL		 4950 return -1;
4951}
4952
4953int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4954 target_ulong len, int type)
4955{
4956 switch (type) {
4957 case GDB_BREAKPOINT_HW:
4958 len = 1;
4959 break;
4960 case GDB_WATCHPOINT_WRITE:
4961 case GDB_WATCHPOINT_ACCESS:
4962 switch (len) {
4963 case 1:
4964 break;
4965 case 2:
4966 case 4:
4967 case 8:
b9bec74b 4968 if (addr & (len - 1)) {
e22a25c9 4969 return -EINVAL;
b9bec74b 4970 }
e22a25c9
AL		 4971 break;
4972 default:
4973 return -EINVAL;
4974 }
4975 break;
4976 default:
4977 return -ENOSYS;
4978 }
4979
b9bec74b 4980 if (nb_hw_breakpoint == 4) {
e22a25c9 4981 return -ENOBUFS;
b9bec74b
JK		 4982 }
4983 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 4984 return -EEXIST;
b9bec74b 4985 }
e22a25c9
AL		 4986 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4987 hw_breakpoint[nb_hw_breakpoint].len = len;
4988 hw_breakpoint[nb_hw_breakpoint].type = type;
4989 nb_hw_breakpoint++;
4990
4991 return 0;
4992}
4993
4994int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4995 target_ulong len, int type)
4996{
4997 int n;
4998
4999 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 5000 if (n < 0) {
e22a25c9 5001 return -ENOENT;
b9bec74b 5002 }
e22a25c9
AL		 5003 nb_hw_breakpoint--;
5004 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
5005
5006 return 0;
5007}
5008
5009void kvm_arch_remove_all_hw_breakpoints(void)
5010{
5011 nb_hw_breakpoint = 0;
5012}
5013
5014static CPUWatchpoint hw_watchpoint;
5015
a60f24b5 5016static int kvm_handle_debug(X86CPU *cpu,
48405526 5017 struct kvm_debug_exit_arch *arch_info)
e22a25c9 5018{
ed2803da 5019 CPUState *cs = CPU(cpu);
a60f24b5 5020 CPUX86State *env = &cpu->env;
f2574737 5021 int ret = 0;
e22a25c9
AL		 5022 int n;
5023
37936ac7
LA		 5024 if (arch_info->exception == EXCP01_DB) {
5025 if (arch_info->dr6 & DR6_BS) {
ed2803da 5026 if (cs->singlestep_enabled) {
f2574737 5027 ret = EXCP_DEBUG;
b9bec74b 5028 }
e22a25c9 5029 } else {
b9bec74b
JK		 5030 for (n = 0; n < 4; n++) {
5031 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 5032 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
5033 case 0x0:
f2574737 5034 ret = EXCP_DEBUG;
e22a25c9
AL		 5035 break;
5036 case 0x1:
f2574737 5037 ret = EXCP_DEBUG;
ff4700b0 5038 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 5039 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5040 hw_watchpoint.flags = BP_MEM_WRITE;
5041 break;
5042 case 0x3:
f2574737 5043 ret = EXCP_DEBUG;
ff4700b0 5044 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 5045 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5046 hw_watchpoint.flags = BP_MEM_ACCESS;
5047 break;
5048 }
b9bec74b
JK		 5049 }
5050 }
e22a25c9 5051 }
ff4700b0 5052 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 5053 ret = EXCP_DEBUG;
b9bec74b 5054 }
f2574737 5055 if (ret == 0) {
ff4700b0 5056 cpu_synchronize_state(cs);
fd13f23b 5057 assert(env->exception_nr == -1);
b0b1d690 5058
f2574737 5059 /* pass to guest */
fd13f23b
LA		 5060 kvm_queue_exception(env, arch_info->exception,
5061 arch_info->exception == EXCP01_DB,
5062 arch_info->dr6);
48405526 5063 env->has_error_code = 0;
b0b1d690 5064 }
e22a25c9 5065
f2574737 5066 return ret;
e22a25c9
AL		 5067}
5068
20d695a9 5069void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 5070{
5071 const uint8_t type_code[] = {
5072 [GDB_BREAKPOINT_HW] = 0x0,
5073 [GDB_WATCHPOINT_WRITE] = 0x1,
5074 [GDB_WATCHPOINT_ACCESS] = 0x3
5075 };
5076 const uint8_t len_code[] = {
5077 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
5078 };
5079 int n;
5080
a60f24b5 5081 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 5082 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 5083 }
e22a25c9
AL		 5084 if (nb_hw_breakpoint > 0) {
5085 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
5086 dbg->arch.debugreg[7] = 0x0600;
5087 for (n = 0; n < nb_hw_breakpoint; n++) {
5088 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
5089 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
5090 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 5091 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 5092 }
5093 }
5094}
4513d923 5095
c22f5467
SC		 5096static bool has_sgx_provisioning;
5097
5098static bool __kvm_enable_sgx_provisioning(KVMState *s)
5099{
5100 int fd, ret;
5101
5102 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
5103 return false;
5104 }
5105
5106 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
5107 if (fd < 0) {
5108 return false;
5109 }
5110
5111 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
5112 if (ret) {
5113 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
5114 exit(1);
5115 }
5116 close(fd);
5117 return true;
5118}
5119
5120bool kvm_enable_sgx_provisioning(KVMState *s)
5121{
5122 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
5123}
5124
2a4dac83
JK		 5125static bool host_supports_vmx(void)
5126{
5127 uint32_t ecx, unused;
5128
5129 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
5130 return ecx & CPUID_EXT_VMX;
5131}
5132
5133#define VMX_INVALID_GUEST_STATE 0x80000021
5134
20d695a9 5135int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 5136{
20d695a9 5137 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 5138 uint64_t code;
5139 int ret;
5140
5141 switch (run->exit_reason) {
5142 case KVM_EXIT_HLT:
5143 DPRINTF("handle_hlt\n");
4b8523ee 5144 qemu_mutex_lock_iothread();
839b5630 5145 ret = kvm_handle_halt(cpu);
4b8523ee 5146 qemu_mutex_unlock_iothread();
2a4dac83
JK		 5147 break;
5148 case KVM_EXIT_SET_TPR:
5149 ret = 0;
5150 break;
d362e757 5151 case KVM_EXIT_TPR_ACCESS:
4b8523ee 5152 qemu_mutex_lock_iothread();
f7575c96 5153 ret = kvm_handle_tpr_access(cpu);
4b8523ee 5154 qemu_mutex_unlock_iothread();
d362e757 5155 break;
2a4dac83
JK		 5156 case KVM_EXIT_FAIL_ENTRY:
5157 code = run->fail_entry.hardware_entry_failure_reason;
5158 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
5159 code);
5160 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
5161 fprintf(stderr,
12619721 5162 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 5163 "unrestricted mode\n"
5164 "support, the failure can be most likely due to the guest "
5165 "entering an invalid\n"
5166 "state for Intel VT. For example, the guest maybe running "
5167 "in big real mode\n"
5168 "which is not supported on less recent Intel processors."
5169 "\n\n");
5170 }
5171 ret = -1;
5172 break;
5173 case KVM_EXIT_EXCEPTION:
5174 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
5175 run->ex.exception, run->ex.error_code);
5176 ret = -1;
5177 break;
f2574737
JK		 5178 case KVM_EXIT_DEBUG:
5179 DPRINTF("kvm_exit_debug\n");
4b8523ee 5180 qemu_mutex_lock_iothread();
a60f24b5 5181 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 5182 qemu_mutex_unlock_iothread();
f2574737 5183 break;
50efe82c
AS		 5184 case KVM_EXIT_HYPERV:
5185 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
5186 break;
15eafc2e
PB		 5187 case KVM_EXIT_IOAPIC_EOI:
5188 ioapic_eoi_broadcast(run->eoi.vector);
5189 ret = 0;
5190 break;
035d1ef2
CQ		 5191 case KVM_EXIT_X86_BUS_LOCK:
5192 /* already handled in kvm_arch_post_run */
5193 ret = 0;
5194 break;
2a4dac83
JK		 5195 default:
5196 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
5197 ret = -1;
5198 break;
5199 }
5200
5201 return ret;
5202}
5203
20d695a9 5204bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 5205{
20d695a9
AF		 5206 X86CPU *cpu = X86_CPU(cs);
5207 CPUX86State *env = &cpu->env;
5208
dd1750d7 5209 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 5210 return !(env->cr[0] & CR0_PE_MASK) ||
5211 ((env->segs[R_CS].selector & 3) != 3);
4513d923 5212}
84b058d7
JK		 5213
5214void kvm_arch_init_irq_routing(KVMState *s)
5215{
cc7e0ddf 5216 /* We know at this point that we're using the in-kernel
614e41bc 5217 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 5218 * we can use msi via irqfd and GSI routing.
cc7e0ddf 5219 */
614e41bc 5220 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 5221 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 5222
5223 if (kvm_irqchip_is_split()) {
def4c557 5224 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
15eafc2e
PB		 5225 int i;
5226
5227 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
5228 MSI routes for signaling interrupts to the local apics. */
5229 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
def4c557 5230 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
15eafc2e
PB		 5231 error_report("Could not enable split IRQ mode.");
5232 exit(1);
5233 }
5234 }
def4c557 5235 kvm_irqchip_commit_route_changes(&c);
15eafc2e
PB		 5236 }
5237}
5238
4376c40d 5239int kvm_arch_irqchip_create(KVMState *s)
15eafc2e
PB		 5240{
5241 int ret;
4376c40d 5242 if (kvm_kernel_irqchip_split()) {
15eafc2e
PB		 5243 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
5244 if (ret) {
df3c286c 5245 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 5246 strerror(-ret));
5247 exit(1);
5248 } else {
5249 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
5250 kvm_split_irqchip = true;
5251 return 1;
5252 }
5253 } else {
5254 return 0;
5255 }
84b058d7 5256}
b139bd30 5257
c1bb5418
DW		 5258uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
5259{
5260 CPUX86State *env;
5261 uint64_t ext_id;
5262
5263 if (!first_cpu) {
5264 return address;
5265 }
5266 env = &X86_CPU(first_cpu)->env;
5267 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
5268 return address;
5269 }
5270
5271 /*
5272 * If the remappable format bit is set, or the upper bits are
5273 * already set in address_hi, or the low extended bits aren't
5274 * there anyway, do nothing.
5275 */
5276 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
5277 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
5278 return address;
5279 }
5280
5281 address &= ~ext_id;
5282 address |= ext_id << 35;
5283 return address;
5284}
5285
9e03a040 5286int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 5287 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 5288{
8b5ed7df
PX		 5289 X86IOMMUState *iommu = x86_iommu_get_default();
5290
5291 if (iommu) {
30c60f77 5292 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
8b5ed7df 5293
c1bb5418
DW		 5294 if (class->int_remap) {
5295 int ret;
5296 MSIMessage src, dst;
0ea1472d 5297
c1bb5418
DW		 5298 src.address = route->u.msi.address_hi;
5299 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
5300 src.address |= route->u.msi.address_lo;
5301 src.data = route->u.msi.data;
8b5ed7df 5302
c1bb5418
DW		 5303 ret = class->int_remap(iommu, &src, &dst, dev ? \
5304 pci_requester_id(dev) : \
5305 X86_IOMMU_SID_INVALID);
5306 if (ret) {
5307 trace_kvm_x86_fixup_msi_error(route->gsi);
5308 return 1;
5309 }
5310
5311 /*
5312 * Handled untranslated compatibilty format interrupt with
5313 * extended destination ID in the low bits 11-5. */
5314 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
8b5ed7df 5315
c1bb5418
DW		 5316 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
5317 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
5318 route->u.msi.data = dst.data;
5319 return 0;
5320 }
8b5ed7df
PX		 5321 }
5322
c1bb5418
DW		 5323 address = kvm_swizzle_msi_ext_dest_id(address);
5324 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
5325 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
9e03a040
FB		 5326 return 0;
5327}
1850b6b7 5328
38d87493
PX		 5329typedef struct MSIRouteEntry MSIRouteEntry;
5330
5331struct MSIRouteEntry {
5332 PCIDevice *dev; /* Device pointer */
5333 int vector; /* MSI/MSIX vector index */
5334 int virq; /* Virtual IRQ index */
5335 QLIST_ENTRY(MSIRouteEntry) list;
5336};
5337
5338/* List of used GSI routes */
5339static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
5340 QLIST_HEAD_INITIALIZER(msi_route_list);
5341
e1d4fb2d
PX		 5342static void kvm_update_msi_routes_all(void *private, bool global,
5343 uint32_t index, uint32_t mask)
5344{
a56de056 5345 int cnt = 0, vector;
e1d4fb2d
PX		 5346 MSIRouteEntry *entry;
5347 MSIMessage msg;
fd563564
PX		 5348 PCIDevice *dev;
5349
e1d4fb2d
PX		 5350 /* TODO: explicit route update */
5351 QLIST_FOREACH(entry, &msi_route_list, list) {
5352 cnt++;
a56de056 5353 vector = entry->vector;
fd563564 5354 dev = entry->dev;
a56de056
PX		 5355 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
5356 msg = msix_get_message(dev, vector);
5357 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
5358 msg = msi_get_message(dev, vector);
5359 } else {
5360 /*
5361 * Either MSI/MSIX is disabled for the device, or the
5362 * specific message was masked out. Skip this one.
5363 */
fd563564
PX		 5364 continue;
5365 }
fd563564 5366 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 5367 }
3f1fea0f 5368 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 5369 trace_kvm_x86_update_msi_routes(cnt);
5370}
5371
38d87493
PX		 5372int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
5373 int vector, PCIDevice *dev)
5374{
e1d4fb2d 5375 static bool notify_list_inited = false;
38d87493
PX		 5376 MSIRouteEntry *entry;
5377
5378 if (!dev) {
5379 /* These are (possibly) IOAPIC routes only used for split
5380 * kernel irqchip mode, while what we are housekeeping are
5381 * PCI devices only. */
5382 return 0;
5383 }
5384
5385 entry = g_new0(MSIRouteEntry, 1);
5386 entry->dev = dev;
5387 entry->vector = vector;
5388 entry->virq = route->gsi;
5389 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
5390
5391 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 5392
5393 if (!notify_list_inited) {
5394 /* For the first time we do add route, add ourselves into
5395 * IOMMU's IEC notify list if needed. */
5396 X86IOMMUState *iommu = x86_iommu_get_default();
5397 if (iommu) {
5398 x86_iommu_iec_register_notifier(iommu,
5399 kvm_update_msi_routes_all,
5400 NULL);
5401 }
5402 notify_list_inited = true;
5403 }
38d87493
PX		 5404 return 0;
5405}
5406
5407int kvm_arch_release_virq_post(int virq)
5408{
5409 MSIRouteEntry *entry, *next;
5410 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
5411 if (entry->virq == virq) {
5412 trace_kvm_x86_remove_msi_route(virq);
5413 QLIST_REMOVE(entry, list);
01960e6d 5414 g_free(entry);
38d87493
PX		 5415 break;
5416 }
5417 }
9e03a040
FB		 5418 return 0;
5419}
1850b6b7
EA		 5420
5421int kvm_arch_msi_data_to_gsi(uint32_t data)
5422{
5423 abort();
5424}
e1e43813
PB		 5425
5426bool kvm_has_waitpkg(void)
5427{
5428 return has_msr_umwait;
5429}
92a5199b
TL		 5430
5431bool kvm_arch_cpu_check_are_resettable(void)
5432{
5433 return !sev_es_enabled();
5434}
19db68ca
YZ		 5435
5436#define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
5437
5438void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
5439{
5440 KVMState *s = kvm_state;
5441 uint64_t supported;
5442
5443 mask &= XSTATE_DYNAMIC_MASK;
5444 if (!mask) {
5445 return;
5446 }
5447 /*
5448 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
5449 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
5450 * about them already because they are not supported features.
5451 */
5452 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
5453 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
5454 mask &= supported;
5455
5456 while (mask) {
5457 int bit = ctz64(mask);
5458 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
5459 if (rc) {
5460 /*
5461 * Older kernel version (<5.17) do not support
5462 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
5463 * any dynamic feature from kvm_arch_get_supported_cpuid.
5464 */
5465 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
5466 "for feature bit %d", bit);
5467 }
5468 mask &= ~BIT_ULL(bit);
5469 }
5470}
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