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Update version for v7.0.0-rc1 release
[mirror_qemu.git] / target / i386 / kvm / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
8efc4e51 16#include "qapi/qapi-events-run-state.h"
da34e65c 17#include "qapi/error.h"
05330448 18#include <sys/ioctl.h>
25d2e361 19#include <sys/utsname.h>
19db68ca 20#include <sys/syscall.h>
05330448
AL		 21
22#include <linux/kvm.h>
1814eab6 23#include "standard-headers/asm-x86/kvm_para.h"
05330448 24
33c11879 25#include "cpu.h"
f5cc5a5c 26#include "host-cpu.h"
9c17d615 27#include "sysemu/sysemu.h"
b3946626 28#include "sysemu/hw_accel.h"
6410848b 29#include "sysemu/kvm_int.h"
54d31236 30#include "sysemu/runstate.h"
1d31f66b 31#include "kvm_i386.h"
93777de3 32#include "sev.h"
50efe82c 33#include "hyperv.h"
5e953812 34#include "hyperv-proto.h"
50efe82c 35
022c62cb 36#include "exec/gdbstub.h"
1de7afc9 37#include "qemu/host-utils.h"
db725815 38#include "qemu/main-loop.h"
1de7afc9 39#include "qemu/config-file.h"
1c4a55db 40#include "qemu/error-report.h"
5df022cf 41#include "qemu/memalign.h"
89a289c7 42#include "hw/i386/x86.h"
0d09e41a 43#include "hw/i386/apic.h"
e0723c45
PB		 44#include "hw/i386/apic_internal.h"
45#include "hw/i386/apic-msidef.h"
8b5ed7df 46#include "hw/i386/intel_iommu.h"
e1d4fb2d 47#include "hw/i386/x86-iommu.h"
d6d059ca 48#include "hw/i386/e820_memory_layout.h"
50efe82c 49
a2cb15b0 50#include "hw/pci/pci.h"
15eafc2e 51#include "hw/pci/msi.h"
fd563564 52#include "hw/pci/msix.h"
795c40b8 53#include "migration/blocker.h"
4c663752 54#include "exec/memattrs.h"
8b5ed7df 55#include "trace.h"
05330448
AL		 56
57//#define DEBUG_KVM
58
59#ifdef DEBUG_KVM
8c0d577e 60#define DPRINTF(fmt, ...) \
05330448
AL		 61 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
62#else
8c0d577e 63#define DPRINTF(fmt, ...) \
05330448
AL		 64 do { } while (0)
65#endif
66
73b994f6
LA		 67/* From arch/x86/kvm/lapic.h */
68#define KVM_APIC_BUS_CYCLE_NS 1
69#define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
70
1a03675d
GC		 71#define MSR_KVM_WALL_CLOCK 0x11
72#define MSR_KVM_SYSTEM_TIME 0x12
73
d1138251
EH		 74/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
75 * 255 kvm_msr_entry structs */
76#define MSR_BUF_SIZE 4096
d71b62a1 77
420ae1fc
PB		 78static void kvm_init_msrs(X86CPU *cpu);
79
94a8d39a
JK		 80const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
81 KVM_CAP_INFO(SET_TSS_ADDR),
82 KVM_CAP_INFO(EXT_CPUID),
83 KVM_CAP_INFO(MP_STATE),
84 KVM_CAP_LAST_INFO
85};
25d2e361 86
c3a3a7d3
JK		 87static bool has_msr_star;
88static bool has_msr_hsave_pa;
c9b8f6b6 89static bool has_msr_tsc_aux;
f28558d3 90static bool has_msr_tsc_adjust;
aa82ba54 91static bool has_msr_tsc_deadline;
df67696e 92static bool has_msr_feature_control;
21e87c46 93static bool has_msr_misc_enable;
fc12d72e 94static bool has_msr_smbase;
79e9ebeb 95static bool has_msr_bndcfgs;
25d2e361 96static int lm_capable_kernel;
7bc3d711 97static bool has_msr_hv_hypercall;
f2a53c9e 98static bool has_msr_hv_crash;
744b8a94 99static bool has_msr_hv_reset;
8c145d7c 100static bool has_msr_hv_vpindex;
e9688fab 101static bool hv_vpindex_settable;
46eb8f98 102static bool has_msr_hv_runtime;
866eea9a 103static bool has_msr_hv_synic;
ff99aa64 104static bool has_msr_hv_stimer;
d72bc7f6 105static bool has_msr_hv_frequencies;
ba6a4fd9 106static bool has_msr_hv_reenlightenment;
18cd2c17 107static bool has_msr_xss;
65087997 108static bool has_msr_umwait;
a33a2cfe 109static bool has_msr_spec_ctrl;
cabf9862 110static bool has_tsc_scale_msr;
2a9758c5 111static bool has_msr_tsx_ctrl;
cfeea0c0 112static bool has_msr_virt_ssbd;
e13713db 113static bool has_msr_smi_count;
aec5e9c3 114static bool has_msr_arch_capabs;
597360c0 115static bool has_msr_core_capabs;
20a78b02 116static bool has_msr_vmx_vmfunc;
67025148 117static bool has_msr_ucode_rev;
4a910e1f 118static bool has_msr_vmx_procbased_ctls2;
ea39f9b6 119static bool has_msr_perf_capabs;
6aa4228b 120static bool has_msr_pkrs;
b827df58 121
0b368a10
JD		 122static uint32_t has_architectural_pmu_version;
123static uint32_t num_architectural_pmu_gp_counters;
124static uint32_t num_architectural_pmu_fixed_counters;
0d894367 125
28143b40 126static int has_xsave;
e56dd3c7 127static int has_xsave2;
28143b40
TH		 128static int has_xcrs;
129static int has_pit_state2;
8f515d38 130static int has_sregs2;
fd13f23b 131static int has_exception_payload;
28143b40 132
87f8b626
AR		 133static bool has_msr_mcg_ext_ctl;
134
494e95e9 135static struct kvm_cpuid2 *cpuid_cache;
a8439be6 136static struct kvm_cpuid2 *hv_cpuid_cache;
f57bceb6 137static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 138
035d1ef2
CQ		 139#define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
140static RateLimit bus_lock_ratelimit_ctrl;
141
28143b40
TH		 142int kvm_has_pit_state2(void)
143{
144 return has_pit_state2;
145}
146
355023f2
PB		 147bool kvm_has_smm(void)
148{
23edf8b5 149 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
355023f2
PB		 150}
151
6053a86f
MT		 152bool kvm_has_adjust_clock_stable(void)
153{
154 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
155
156 return (ret == KVM_CLOCK_TSC_STABLE);
157}
158
8700a984
VK		 159bool kvm_has_adjust_clock(void)
160{
161 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
162}
163
79a197ab
LA		 164bool kvm_has_exception_payload(void)
165{
166 return has_exception_payload;
167}
168
fb506e70
RK		 169static bool kvm_x2apic_api_set_flags(uint64_t flags)
170{
4f7f5893 171 KVMState *s = KVM_STATE(current_accel());
fb506e70
RK		 172
173 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
174}
175
e391c009 176#define MEMORIZE(fn, _result) \
2a138ec3 177 ({ \
2a138ec3
RK		 178 static bool _memorized; \
179 \
180 if (_memorized) { \
181 return _result; \
182 } \
183 _memorized = true; \
184 _result = fn; \
185 })
186
e391c009
IM		 187static bool has_x2apic_api;
188
189bool kvm_has_x2apic_api(void)
190{
191 return has_x2apic_api;
192}
193
fb506e70
RK		 194bool kvm_enable_x2apic(void)
195{
2a138ec3
RK		 196 return MEMORIZE(
197 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 198 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
199 has_x2apic_api);
fb506e70
RK		 200}
201
e9688fab
RK		 202bool kvm_hv_vpindex_settable(void)
203{
204 return hv_vpindex_settable;
205}
206
0fd7e098
LL		 207static int kvm_get_tsc(CPUState *cs)
208{
209 X86CPU *cpu = X86_CPU(cs);
210 CPUX86State *env = &cpu->env;
211 struct {
212 struct kvm_msrs info;
213 struct kvm_msr_entry entries[1];
a1834d97 214 } msr_data = {};
0fd7e098
LL		 215 int ret;
216
217 if (env->tsc_valid) {
218 return 0;
219 }
220
1f670a95 221 memset(&msr_data, 0, sizeof(msr_data));
0fd7e098
LL		 222 msr_data.info.nmsrs = 1;
223 msr_data.entries[0].index = MSR_IA32_TSC;
224 env->tsc_valid = !runstate_is_running();
225
226 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
227 if (ret < 0) {
228 return ret;
229 }
230
48e1a45c 231 assert(ret == 1);
0fd7e098
LL		 232 env->tsc = msr_data.entries[0].data;
233 return 0;
234}
235
14e6fe12 236static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 237{
0fd7e098
LL		 238 kvm_get_tsc(cpu);
239}
240
241void kvm_synchronize_all_tsc(void)
242{
243 CPUState *cpu;
244
245 if (kvm_enabled()) {
246 CPU_FOREACH(cpu) {
14e6fe12 247 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 248 }
249 }
250}
251
b827df58
AK		 252static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
253{
254 struct kvm_cpuid2 *cpuid;
255 int r, size;
256
257 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 258 cpuid = g_malloc0(size);
b827df58
AK		 259 cpuid->nent = max;
260 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 261 if (r == 0 && cpuid->nent >= max) {
262 r = -E2BIG;
263 }
b827df58
AK		 264 if (r < 0) {
265 if (r == -E2BIG) {
7267c094 266 g_free(cpuid);
b827df58
AK		 267 return NULL;
268 } else {
269 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
270 strerror(-r));
271 exit(1);
272 }
273 }
274 return cpuid;
275}
276
dd87f8a6
EH		 277/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
278 * for all entries.
279 */
280static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
281{
282 struct kvm_cpuid2 *cpuid;
283 int max = 1;
494e95e9
CP		 284
285 if (cpuid_cache != NULL) {
286 return cpuid_cache;
287 }
dd87f8a6
EH		 288 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
289 max *= 2;
290 }
494e95e9 291 cpuid_cache = cpuid;
dd87f8a6
EH		 292 return cpuid;
293}
294
b199c682 295static bool host_tsx_broken(void)
40e80ee4
EH		 296{
297 int family, model, stepping;\
298 char vendor[CPUID_VENDOR_SZ + 1];
299
f5cc5a5c 300 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
40e80ee4
EH		 301
302 /* Check if we are running on a Haswell host known to have broken TSX */
303 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
304 (family == 6) &&
305 ((model == 63 && stepping < 4) ||
306 model == 60 || model == 69 || model == 70);
307}
0c31b744 308
829ae2f9
EH		 309/* Returns the value for a specific register on the cpuid entry
310 */
311static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
312{
313 uint32_t ret = 0;
314 switch (reg) {
315 case R_EAX:
316 ret = entry->eax;
317 break;
318 case R_EBX:
319 ret = entry->ebx;
320 break;
321 case R_ECX:
322 ret = entry->ecx;
323 break;
324 case R_EDX:
325 ret = entry->edx;
326 break;
327 }
328 return ret;
329}
330
4fb73f1d
EH		 331/* Find matching entry for function/index on kvm_cpuid2 struct
332 */
333static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
334 uint32_t function,
335 uint32_t index)
336{
337 int i;
338 for (i = 0; i < cpuid->nent; ++i) {
339 if (cpuid->entries[i].function == function &&
340 cpuid->entries[i].index == index) {
341 return &cpuid->entries[i];
342 }
343 }
344 /* not found: */
345 return NULL;
346}
347
ba9bc59e 348uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 349 uint32_t index, int reg)
b827df58
AK		 350{
351 struct kvm_cpuid2 *cpuid;
b827df58
AK		 352 uint32_t ret = 0;
353 uint32_t cpuid_1_edx;
19db68ca 354 uint64_t bitmask;
b827df58 355
dd87f8a6 356 cpuid = get_supported_cpuid(s);
b827df58 357
4fb73f1d
EH		 358 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
359 if (entry) {
4fb73f1d 360 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 361 }
362
7b46e5ce
EH		 363 /* Fixups for the data returned by KVM, below */
364
c2acb022
EH		 365 if (function == 1 && reg == R_EDX) {
366 /* KVM before 2.6.30 misreports the following features */
367 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 368 } else if (function == 1 && reg == R_ECX) {
369 /* We can set the hypervisor flag, even if KVM does not return it on
370 * GET_SUPPORTED_CPUID
371 */
372 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 373 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
374 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
375 * and the irqchip is in the kernel.
376 */
377 if (kvm_irqchip_in_kernel() &&
378 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
379 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
380 }
41e5e76d
EH		 381
382 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
383 * without the in-kernel irqchip
384 */
385 if (!kvm_irqchip_in_kernel()) {
386 ret &= ~CPUID_EXT_X2APIC;
b827df58 387 }
2266d443
MT		 388
389 if (enable_cpu_pm) {
390 int disable_exits = kvm_check_extension(s,
391 KVM_CAP_X86_DISABLE_EXITS);
392
393 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
394 ret |= CPUID_EXT_MONITOR;
395 }
396 }
28b8e4d0
JK		 397 } else if (function == 6 && reg == R_EAX) {
398 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4 399 } else if (function == 7 && index == 0 && reg == R_EBX) {
b199c682 400 if (host_tsx_broken()) {
40e80ee4
EH		 401 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
402 }
485b1d25
EH		 403 } else if (function == 7 && index == 0 && reg == R_EDX) {
404 /*
405 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
406 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
407 * returned by KVM_GET_MSR_INDEX_LIST.
408 */
409 if (!has_msr_arch_capabs) {
410 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
411 }
19db68ca
YZ		 412 } else if (function == 0xd && index == 0 &&
413 (reg == R_EAX || reg == R_EDX)) {
3ec5ad40
PB		 414 /*
415 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
416 * features that still have to be enabled with the arch_prctl
417 * system call. QEMU needs the full value, which is retrieved
418 * with KVM_GET_DEVICE_ATTR.
419 */
19db68ca
YZ		 420 struct kvm_device_attr attr = {
421 .group = 0,
422 .attr = KVM_X86_XCOMP_GUEST_SUPP,
423 .addr = (unsigned long) &bitmask
424 };
425
426 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
427 if (!sys_attr) {
3ec5ad40 428 return ret;
19db68ca
YZ		 429 }
430
431 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
3ec5ad40
PB		 432 if (rc < 0) {
433 if (rc != -ENXIO) {
434 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
435 "error: %d", rc);
436 }
437 return ret;
19db68ca
YZ		 438 }
439 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
f98bbd83
BM		 440 } else if (function == 0x80000001 && reg == R_ECX) {
441 /*
442 * It's safe to enable TOPOEXT even if it's not returned by
443 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
444 * us to keep CPU models including TOPOEXT runnable on older kernels.
445 */
446 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 447 } else if (function == 0x80000001 && reg == R_EDX) {
448 /* On Intel, kvm returns cpuid according to the Intel spec,
449 * so add missing bits according to the AMD spec:
450 */
451 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
452 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 453 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
454 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
455 * be enabled without the in-kernel irqchip
456 */
457 if (!kvm_irqchip_in_kernel()) {
458 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
459 }
c1bb5418
DW		 460 if (kvm_irqchip_is_split()) {
461 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
462 }
be777326 463 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 464 ret |= 1U << KVM_HINTS_REALTIME;
b9bec74b 465 }
0c31b744
GC		 466
467 return ret;
bb0300dc 468}
bb0300dc 469
ede146c2 470uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
f57bceb6
RH		 471{
472 struct {
473 struct kvm_msrs info;
474 struct kvm_msr_entry entries[1];
a1834d97 475 } msr_data = {};
20a78b02
PB		 476 uint64_t value;
477 uint32_t ret, can_be_one, must_be_one;
f57bceb6
RH		 478
479 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
480 return 0;
481 }
482
483 /* Check if requested MSR is supported feature MSR */
484 int i;
485 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
486 if (kvm_feature_msrs->indices[i] == index) {
487 break;
488 }
489 if (i == kvm_feature_msrs->nmsrs) {
490 return 0; /* if the feature MSR is not supported, simply return 0 */
491 }
492
493 msr_data.info.nmsrs = 1;
494 msr_data.entries[0].index = index;
495
496 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
497 if (ret != 1) {
498 error_report("KVM get MSR (index=0x%x) feature failed, %s",
499 index, strerror(-ret));
500 exit(1);
501 }
502
20a78b02
PB		 503 value = msr_data.entries[0].data;
504 switch (index) {
505 case MSR_IA32_VMX_PROCBASED_CTLS2:
4a910e1f
VK		 506 if (!has_msr_vmx_procbased_ctls2) {
507 /* KVM forgot to add these bits for some time, do this ourselves. */
508 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
509 CPUID_XSAVE_XSAVES) {
510 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
511 }
512 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
513 CPUID_EXT_RDRAND) {
514 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
515 }
516 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
517 CPUID_7_0_EBX_INVPCID) {
518 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
519 }
520 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
521 CPUID_7_0_EBX_RDSEED) {
522 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
523 }
524 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
525 CPUID_EXT2_RDTSCP) {
526 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
527 }
048c9516
PB		 528 }
529 /* fall through */
20a78b02
PB		 530 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
531 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
532 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
533 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
534 /*
535 * Return true for bits that can be one, but do not have to be one.
536 * The SDM tells us which bits could have a "must be one" setting,
537 * so we can do the opposite transformation in make_vmx_msr_value.
538 */
539 must_be_one = (uint32_t)value;
540 can_be_one = (uint32_t)(value >> 32);
541 return can_be_one & ~must_be_one;
542
543 default:
544 return value;
545 }
f57bceb6
RH		 546}
547
e7701825
MT		 548static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
549 int *max_banks)
550{
551 int r;
552
14a09518 553 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 554 if (r > 0) {
555 *max_banks = r;
556 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
557 }
558 return -ENOSYS;
559}
560
bee615d4 561static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 562{
87f8b626 563 CPUState *cs = CPU(cpu);
bee615d4 564 CPUX86State *env = &cpu->env;
c34d440a
JK		 565 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
566 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
567 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 568 int flags = 0;
e7701825 569
c34d440a
JK		 570 if (code == BUS_MCEERR_AR) {
571 status |= MCI_STATUS_AR | 0x134;
572 mcg_status |= MCG_STATUS_EIPV;
573 } else {
574 status |= 0xc0;
575 mcg_status |= MCG_STATUS_RIPV;
419fb20a 576 }
87f8b626
AR		 577
578 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
579 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
580 * guest kernel back into env->mcg_ext_ctl.
581 */
582 cpu_synchronize_state(cs);
583 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
584 mcg_status |= MCG_STATUS_LMCE;
585 flags = 0;
586 }
587
8c5cf3b6 588 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 589 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 590}
419fb20a 591
8efc4e51
ZP		 592static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
593{
594 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
595
596 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
597 &mff);
598}
599
73284563 600static void hardware_memory_error(void *host_addr)
419fb20a 601{
8efc4e51 602 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
73284563 603 error_report("QEMU got Hardware memory error at addr %p", host_addr);
419fb20a
JK		 604 exit(1);
605}
606
2ae41db2 607void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 608{
20d695a9
AF		 609 X86CPU *cpu = X86_CPU(c);
610 CPUX86State *env = &cpu->env;
419fb20a 611 ram_addr_t ram_addr;
a8170e5e 612 hwaddr paddr;
419fb20a 613
4d39892c
PB		 614 /* If we get an action required MCE, it has been injected by KVM
615 * while the VM was running. An action optional MCE instead should
616 * be coming from the main thread, which qemu_init_sigbus identifies
617 * as the "early kill" thread.
618 */
a16fc07e 619 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 620
20e0ff59 621 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 622 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 623 if (ram_addr != RAM_ADDR_INVALID &&
624 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
625 kvm_hwpoison_page_add(ram_addr);
626 kvm_mce_inject(cpu, paddr, code);
73284563
MS		 627
628 /*
629 * Use different logging severity based on error type.
630 * If there is additional MCE reporting on the hypervisor, QEMU VA
631 * could be another source to identify the PA and MCE details.
632 */
633 if (code == BUS_MCEERR_AR) {
634 error_report("Guest MCE Memory Error at QEMU addr %p and "
635 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
636 addr, paddr, "BUS_MCEERR_AR");
637 } else {
638 warn_report("Guest MCE Memory Error at QEMU addr %p and "
639 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
640 addr, paddr, "BUS_MCEERR_AO");
641 }
642
2ae41db2 643 return;
419fb20a 644 }
20e0ff59 645
73284563
MS		 646 if (code == BUS_MCEERR_AO) {
647 warn_report("Hardware memory error at addr %p of type %s "
648 "for memory used by QEMU itself instead of guest system!",
649 addr, "BUS_MCEERR_AO");
650 }
419fb20a 651 }
20e0ff59
PB		 652
653 if (code == BUS_MCEERR_AR) {
73284563 654 hardware_memory_error(addr);
20e0ff59
PB		 655 }
656
8efc4e51
ZP		 657 /* Hope we are lucky for AO MCE, just notify a event */
658 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
419fb20a
JK		 659}
660
fd13f23b
LA		 661static void kvm_reset_exception(CPUX86State *env)
662{
663 env->exception_nr = -1;
664 env->exception_pending = 0;
665 env->exception_injected = 0;
666 env->exception_has_payload = false;
667 env->exception_payload = 0;
668}
669
670static void kvm_queue_exception(CPUX86State *env,
671 int32_t exception_nr,
672 uint8_t exception_has_payload,
673 uint64_t exception_payload)
674{
675 assert(env->exception_nr == -1);
676 assert(!env->exception_pending);
677 assert(!env->exception_injected);
678 assert(!env->exception_has_payload);
679
680 env->exception_nr = exception_nr;
681
682 if (has_exception_payload) {
683 env->exception_pending = 1;
684
685 env->exception_has_payload = exception_has_payload;
686 env->exception_payload = exception_payload;
687 } else {
688 env->exception_injected = 1;
689
690 if (exception_nr == EXCP01_DB) {
691 assert(exception_has_payload);
692 env->dr[6] = exception_payload;
693 } else if (exception_nr == EXCP0E_PAGE) {
694 assert(exception_has_payload);
695 env->cr[2] = exception_payload;
696 } else {
697 assert(!exception_has_payload);
698 }
699 }
700}
701
1bc22652 702static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 703{
1bc22652
AF		 704 CPUX86State *env = &cpu->env;
705
fd13f23b 706 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 707 unsigned int bank, bank_num = env->mcg_cap & 0xff;
708 struct kvm_x86_mce mce;
709
fd13f23b 710 kvm_reset_exception(env);
ab443475
JK		 711
712 /*
713 * There must be at least one bank in use if an MCE is pending.
714 * Find it and use its values for the event injection.
715 */
716 for (bank = 0; bank < bank_num; bank++) {
717 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
718 break;
719 }
720 }
721 assert(bank < bank_num);
722
723 mce.bank = bank;
724 mce.status = env->mce_banks[bank * 4 + 1];
725 mce.mcg_status = env->mcg_status;
726 mce.addr = env->mce_banks[bank * 4 + 2];
727 mce.misc = env->mce_banks[bank * 4 + 3];
728
1bc22652 729 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 730 }
ab443475
JK		 731 return 0;
732}
733
538f0497 734static void cpu_update_state(void *opaque, bool running, RunState state)
b8cc45d6 735{
317ac620 736 CPUX86State *env = opaque;
b8cc45d6
GC		 737
738 if (running) {
739 env->tsc_valid = false;
740 }
741}
742
83b17af5 743unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 744{
83b17af5 745 X86CPU *cpu = X86_CPU(cs);
7e72a45c 746 return cpu->apic_id;
b164e48e
EH		 747}
748
92067bf4
IM		 749#ifndef KVM_CPUID_SIGNATURE_NEXT
750#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
751#endif
752
92067bf4
IM		 753static bool hyperv_enabled(X86CPU *cpu)
754{
5aa9ef5e 755 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
f701c082 756 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
e48ddcc6 757 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 758}
759
74aaddc6
MT		 760/*
761 * Check whether target_freq is within conservative
762 * ntp correctable bounds (250ppm) of freq
763 */
764static inline bool freq_within_bounds(int freq, int target_freq)
765{
766 int max_freq = freq + (freq * 250 / 1000000);
767 int min_freq = freq - (freq * 250 / 1000000);
768
769 if (target_freq >= min_freq && target_freq <= max_freq) {
770 return true;
771 }
772
773 return false;
774}
775
5031283d
HZ		 776static int kvm_arch_set_tsc_khz(CPUState *cs)
777{
778 X86CPU *cpu = X86_CPU(cs);
779 CPUX86State *env = &cpu->env;
74aaddc6
MT		 780 int r, cur_freq;
781 bool set_ioctl = false;
5031283d
HZ		 782
783 if (!env->tsc_khz) {
784 return 0;
785 }
786
74aaddc6
MT		 787 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
788 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
789
790 /*
791 * If TSC scaling is supported, attempt to set TSC frequency.
792 */
793 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
794 set_ioctl = true;
795 }
796
797 /*
798 * If desired TSC frequency is within bounds of NTP correction,
799 * attempt to set TSC frequency.
800 */
801 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
802 set_ioctl = true;
803 }
804
805 r = set_ioctl ?
5031283d
HZ		 806 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
807 -ENOTSUP;
74aaddc6 808
5031283d
HZ		 809 if (r < 0) {
810 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
811 * TSC frequency doesn't match the one we want.
812 */
74aaddc6
MT		 813 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
814 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
815 -ENOTSUP;
5031283d 816 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 817 warn_report("TSC frequency mismatch between "
818 "VM (%" PRId64 " kHz) and host (%d kHz), "
819 "and TSC scaling unavailable",
820 env->tsc_khz, cur_freq);
5031283d
HZ		 821 return r;
822 }
823 }
824
825 return 0;
826}
827
4bb95b82
LP		 828static bool tsc_is_stable_and_known(CPUX86State *env)
829{
830 if (!env->tsc_khz) {
831 return false;
832 }
833 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
834 || env->user_tsc_khz;
835}
836
6760bd20
VK		 837static struct {
838 const char *desc;
839 struct {
061817a7
VK		 840 uint32_t func;
841 int reg;
6760bd20
VK		 842 uint32_t bits;
843 } flags[2];
c6861930 844 uint64_t dependencies;
6760bd20
VK		 845} kvm_hyperv_properties[] = {
846 [HYPERV_FEAT_RELAXED] = {
847 .desc = "relaxed timing (hv-relaxed)",
848 .flags = {
061817a7 849 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 850 .bits = HV_RELAXED_TIMING_RECOMMENDED}
851 }
852 },
853 [HYPERV_FEAT_VAPIC] = {
854 .desc = "virtual APIC (hv-vapic)",
855 .flags = {
061817a7 856 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
05071629 857 .bits = HV_APIC_ACCESS_AVAILABLE}
6760bd20
VK		 858 }
859 },
860 [HYPERV_FEAT_TIME] = {
861 .desc = "clocksources (hv-time)",
862 .flags = {
061817a7 863 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
b26f68c3 864 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
6760bd20
VK		 865 }
866 },
867 [HYPERV_FEAT_CRASH] = {
868 .desc = "crash MSRs (hv-crash)",
869 .flags = {
061817a7 870 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 871 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
872 }
873 },
874 [HYPERV_FEAT_RESET] = {
875 .desc = "reset MSR (hv-reset)",
876 .flags = {
061817a7 877 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 878 .bits = HV_RESET_AVAILABLE}
879 }
880 },
881 [HYPERV_FEAT_VPINDEX] = {
882 .desc = "VP_INDEX MSR (hv-vpindex)",
883 .flags = {
061817a7 884 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 885 .bits = HV_VP_INDEX_AVAILABLE}
886 }
887 },
888 [HYPERV_FEAT_RUNTIME] = {
889 .desc = "VP_RUNTIME MSR (hv-runtime)",
890 .flags = {
061817a7 891 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 892 .bits = HV_VP_RUNTIME_AVAILABLE}
893 }
894 },
895 [HYPERV_FEAT_SYNIC] = {
896 .desc = "synthetic interrupt controller (hv-synic)",
897 .flags = {
061817a7 898 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 899 .bits = HV_SYNIC_AVAILABLE}
900 }
901 },
902 [HYPERV_FEAT_STIMER] = {
903 .desc = "synthetic timers (hv-stimer)",
904 .flags = {
061817a7 905 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 906 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 907 },
908 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 909 },
910 [HYPERV_FEAT_FREQUENCIES] = {
911 .desc = "frequency MSRs (hv-frequencies)",
912 .flags = {
061817a7 913 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 914 .bits = HV_ACCESS_FREQUENCY_MSRS},
061817a7 915 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 916 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
917 }
918 },
919 [HYPERV_FEAT_REENLIGHTENMENT] = {
920 .desc = "reenlightenment MSRs (hv-reenlightenment)",
921 .flags = {
061817a7 922 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 923 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
924 }
925 },
926 [HYPERV_FEAT_TLBFLUSH] = {
927 .desc = "paravirtualized TLB flush (hv-tlbflush)",
928 .flags = {
061817a7 929 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 930 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
931 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 932 },
933 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 934 },
935 [HYPERV_FEAT_EVMCS] = {
936 .desc = "enlightened VMCS (hv-evmcs)",
937 .flags = {
061817a7 938 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20 939 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 940 },
941 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 942 },
943 [HYPERV_FEAT_IPI] = {
944 .desc = "paravirtualized IPI (hv-ipi)",
945 .flags = {
061817a7 946 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 947 .bits = HV_CLUSTER_IPI_RECOMMENDED |
948 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 949 },
950 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 951 },
128531d9
VK		 952 [HYPERV_FEAT_STIMER_DIRECT] = {
953 .desc = "direct mode synthetic timers (hv-stimer-direct)",
954 .flags = {
061817a7 955 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
128531d9
VK		 956 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
957 },
958 .dependencies = BIT(HYPERV_FEAT_STIMER)
959 },
e1f9a8e8
VK		 960 [HYPERV_FEAT_AVIC] = {
961 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
962 .flags = {
963 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
964 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
965 }
966 },
6760bd20
VK		 967};
968
2e905438
VK		 969static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
970 bool do_sys_ioctl)
6760bd20
VK		 971{
972 struct kvm_cpuid2 *cpuid;
973 int r, size;
974
975 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
976 cpuid = g_malloc0(size);
977 cpuid->nent = max;
978
2e905438
VK		 979 if (do_sys_ioctl) {
980 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
981 } else {
982 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
983 }
6760bd20
VK		 984 if (r == 0 && cpuid->nent >= max) {
985 r = -E2BIG;
986 }
987 if (r < 0) {
988 if (r == -E2BIG) {
989 g_free(cpuid);
990 return NULL;
991 } else {
992 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
993 strerror(-r));
994 exit(1);
995 }
996 }
997 return cpuid;
998}
999
1000/*
1001 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1002 * for all entries.
1003 */
1004static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1005{
1006 struct kvm_cpuid2 *cpuid;
05c900ce
VK		 1007 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000080 leaves */
1008 int max = 10;
decb4f20 1009 int i;
2e905438
VK		 1010 bool do_sys_ioctl;
1011
1012 do_sys_ioctl =
1013 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
6760bd20 1014
e4adb09f
VK		 1015 /*
1016 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1017 * unsupported, kvm_hyperv_expand_features() checks for that.
1018 */
1019 assert(do_sys_ioctl || cs->kvm_state);
1020
6760bd20
VK		 1021 /*
1022 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1023 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1024 * it and re-trying until we succeed.
1025 */
2e905438 1026 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
6760bd20
VK		 1027 max++;
1028 }
decb4f20
VK		 1029
1030 /*
1031 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1032 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1033 * information early, just check for the capability and set the bit
1034 * manually.
1035 */
2e905438 1036 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
decb4f20
VK		 1037 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1038 for (i = 0; i < cpuid->nent; i++) {
1039 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1040 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1041 }
1042 }
1043 }
1044
6760bd20
VK		 1045 return cpuid;
1046}
1047
1048/*
1049 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1050 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1051 */
1052static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 1053{
1054 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 1055 struct kvm_cpuid2 *cpuid;
1056 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1057
1058 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1059 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1060 cpuid->nent = 2;
1061
1062 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1063 entry_feat = &cpuid->entries[0];
1064 entry_feat->function = HV_CPUID_FEATURES;
1065
1066 entry_recomm = &cpuid->entries[1];
1067 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1068 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1069
1070 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1071 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1072 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1073 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1074 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1075 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1076 }
c35bd19a 1077
6760bd20
VK		 1078 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1079 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1080 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 1081 }
6760bd20
VK		 1082
1083 if (has_msr_hv_frequencies) {
1084 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1085 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 1086 }
6760bd20
VK		 1087
1088 if (has_msr_hv_crash) {
1089 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 1090 }
6760bd20
VK		 1091
1092 if (has_msr_hv_reenlightenment) {
1093 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 1094 }
6760bd20
VK		 1095
1096 if (has_msr_hv_reset) {
1097 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 1098 }
6760bd20
VK		 1099
1100 if (has_msr_hv_vpindex) {
1101 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 1102 }
6760bd20
VK		 1103
1104 if (has_msr_hv_runtime) {
1105 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 1106 }
6760bd20
VK		 1107
1108 if (has_msr_hv_synic) {
1109 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1110 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1111
1112 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1113 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 1114 }
c35bd19a 1115 }
6760bd20
VK		 1116
1117 if (has_msr_hv_stimer) {
1118 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 1119 }
9b4cf107 1120
6760bd20
VK		 1121 if (kvm_check_extension(cs->kvm_state,
1122 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1123 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1124 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1125 }
c35bd19a 1126
6760bd20
VK		 1127 if (kvm_check_extension(cs->kvm_state,
1128 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1129 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 1130 }
6760bd20
VK		 1131
1132 if (kvm_check_extension(cs->kvm_state,
1133 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1134 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1135 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 1136 }
6760bd20
VK		 1137
1138 return cpuid;
1139}
1140
a8439be6 1141static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
e1a66a1e
VK		 1142{
1143 struct kvm_cpuid_entry2 *entry;
a8439be6
VK		 1144 struct kvm_cpuid2 *cpuid;
1145
1146 if (hv_cpuid_cache) {
1147 cpuid = hv_cpuid_cache;
1148 } else {
1149 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1150 cpuid = get_supported_hv_cpuid(cs);
1151 } else {
e4adb09f
VK		 1152 /*
1153 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1154 * before KVM context is created but this is only done when
1155 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1156 * KVM_CAP_HYPERV_CPUID.
1157 */
1158 assert(cs->kvm_state);
1159
a8439be6
VK		 1160 cpuid = get_supported_hv_cpuid_legacy(cs);
1161 }
1162 hv_cpuid_cache = cpuid;
1163 }
1164
1165 if (!cpuid) {
1166 return 0;
1167 }
e1a66a1e
VK		 1168
1169 entry = cpuid_find_entry(cpuid, func, 0);
1170 if (!entry) {
1171 return 0;
1172 }
1173
1174 return cpuid_entry_get_reg(entry, reg);
1175}
1176
a8439be6 1177static bool hyperv_feature_supported(CPUState *cs, int feature)
7682f857 1178{
061817a7
VK		 1179 uint32_t func, bits;
1180 int i, reg;
7682f857
VK		 1181
1182 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
061817a7
VK		 1183
1184 func = kvm_hyperv_properties[feature].flags[i].func;
1185 reg = kvm_hyperv_properties[feature].flags[i].reg;
7682f857
VK		 1186 bits = kvm_hyperv_properties[feature].flags[i].bits;
1187
061817a7 1188 if (!func) {
7682f857
VK		 1189 continue;
1190 }
1191
a8439be6 1192 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
7682f857
VK		 1193 return false;
1194 }
1195 }
1196
1197 return true;
1198}
1199
5ce48fa3
VK		 1200/* Checks that all feature dependencies are enabled */
1201static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
6760bd20 1202{
c6861930 1203 uint64_t deps;
7682f857 1204 int dep_feat;
6760bd20 1205
c6861930 1206 deps = kvm_hyperv_properties[feature].dependencies;
9dc83cd9
HR		 1207 while (deps) {
1208 dep_feat = ctz64(deps);
c6861930 1209 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
f4a62495
VK		 1210 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1211 kvm_hyperv_properties[feature].desc,
1212 kvm_hyperv_properties[dep_feat].desc);
5ce48fa3 1213 return false;
c6861930 1214 }
9dc83cd9 1215 deps &= ~(1ull << dep_feat);
c6861930
VK		 1216 }
1217
5ce48fa3 1218 return true;
6760bd20
VK		 1219}
1220
061817a7 1221static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
c830015e
VK		 1222{
1223 X86CPU *cpu = X86_CPU(cs);
1224 uint32_t r = 0;
1225 int i, j;
1226
1227 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1228 if (!hyperv_feat_enabled(cpu, i)) {
1229 continue;
1230 }
1231
1232 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
061817a7
VK		 1233 if (kvm_hyperv_properties[i].flags[j].func != func) {
1234 continue;
1235 }
1236 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
c830015e
VK		 1237 continue;
1238 }
1239
1240 r |= kvm_hyperv_properties[i].flags[j].bits;
1241 }
1242 }
1243
1244 return r;
1245}
1246
2344d22e 1247/*
f6e01ab5
VK		 1248 * Expand Hyper-V CPU features. In partucular, check that all the requested
1249 * features are supported by the host and the sanity of the configuration
1250 * (that all the required dependencies are included). Also, this takes care
1251 * of 'hv_passthrough' mode and fills the environment with all supported
1252 * Hyper-V features.
2344d22e 1253 */
071ce4b0 1254bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
6760bd20 1255{
071ce4b0 1256 CPUState *cs = CPU(cpu);
5ce48fa3
VK		 1257 Error *local_err = NULL;
1258 int feat;
6760bd20 1259
2344d22e 1260 if (!hyperv_enabled(cpu))
d7652b77 1261 return true;
2344d22e 1262
071ce4b0
VK		 1263 /*
1264 * When kvm_hyperv_expand_features is called at CPU feature expansion
1265 * time per-CPU kvm_state is not available yet so we can only proceed
1266 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1267 */
1268 if (!cs->kvm_state &&
1269 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1270 return true;
1271
e48ddcc6 1272 if (cpu->hyperv_passthrough) {
e1a66a1e 1273 cpu->hyperv_vendor_id[0] =
a8439be6 1274 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
e1a66a1e 1275 cpu->hyperv_vendor_id[1] =
a8439be6 1276 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
e1a66a1e 1277 cpu->hyperv_vendor_id[2] =
a8439be6 1278 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
e1a66a1e
VK		 1279 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1280 sizeof(cpu->hyperv_vendor_id) + 1);
1281 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1282 sizeof(cpu->hyperv_vendor_id));
1283 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1284
1285 cpu->hyperv_interface_id[0] =
a8439be6 1286 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
e1a66a1e 1287 cpu->hyperv_interface_id[1] =
a8439be6 1288 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
e1a66a1e 1289 cpu->hyperv_interface_id[2] =
a8439be6 1290 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
e1a66a1e 1291 cpu->hyperv_interface_id[3] =
a8439be6 1292 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
e1a66a1e 1293
af7228b8 1294 cpu->hyperv_ver_id_build =
a8439be6 1295 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
af7228b8
VK		 1296 cpu->hyperv_ver_id_major =
1297 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1298 cpu->hyperv_ver_id_minor =
1299 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1300 cpu->hyperv_ver_id_sp =
a8439be6 1301 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
af7228b8
VK		 1302 cpu->hyperv_ver_id_sb =
1303 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1304 cpu->hyperv_ver_id_sn =
1305 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
e1a66a1e 1306
a8439be6 1307 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
e1a66a1e
VK		 1308 R_EAX);
1309 cpu->hyperv_limits[0] =
a8439be6 1310 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
e1a66a1e 1311 cpu->hyperv_limits[1] =
a8439be6 1312 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
e1a66a1e 1313 cpu->hyperv_limits[2] =
a8439be6 1314 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
e1a66a1e
VK		 1315
1316 cpu->hyperv_spinlock_attempts =
a8439be6 1317 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
30d6ff66 1318
5ce48fa3
VK		 1319 /*
1320 * Mark feature as enabled in 'cpu->hyperv_features' as
1321 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1322 */
1323 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1324 if (hyperv_feature_supported(cs, feat)) {
1325 cpu->hyperv_features |= BIT(feat);
1326 }
1327 }
1328 } else {
1329 /* Check features availability and dependencies */
1330 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1331 /* If the feature was not requested skip it. */
1332 if (!hyperv_feat_enabled(cpu, feat)) {
1333 continue;
1334 }
1335
1336 /* Check if the feature is supported by KVM */
1337 if (!hyperv_feature_supported(cs, feat)) {
1338 error_setg(errp, "Hyper-V %s is not supported by kernel",
1339 kvm_hyperv_properties[feat].desc);
1340 return false;
1341 }
1342
1343 /* Check dependencies */
1344 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1345 error_propagate(errp, local_err);
1346 return false;
1347 }
1348 }
f4a62495 1349 }
6760bd20 1350
c6861930 1351 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1352 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1353 !cpu->hyperv_synic_kvm_only &&
1354 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
f4a62495
VK		 1355 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1356 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1357 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
d7652b77 1358 return false;
6760bd20 1359 }
d7652b77
VK		 1360
1361 return true;
f6e01ab5
VK		 1362}
1363
1364/*
1365 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1366 */
1367static int hyperv_fill_cpuids(CPUState *cs,
1368 struct kvm_cpuid_entry2 *cpuid_ent)
1369{
1370 X86CPU *cpu = X86_CPU(cs);
1371 struct kvm_cpuid_entry2 *c;
1372 uint32_t cpuid_i = 0;
1373
2344d22e
VK		 1374 c = &cpuid_ent[cpuid_i++];
1375 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
2344d22e
VK		 1376 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1377 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
08856771
VK		 1378 c->ebx = cpu->hyperv_vendor_id[0];
1379 c->ecx = cpu->hyperv_vendor_id[1];
1380 c->edx = cpu->hyperv_vendor_id[2];
2344d22e
VK		 1381
1382 c = &cpuid_ent[cpuid_i++];
1383 c->function = HV_CPUID_INTERFACE;
735db465
VK		 1384 c->eax = cpu->hyperv_interface_id[0];
1385 c->ebx = cpu->hyperv_interface_id[1];
1386 c->ecx = cpu->hyperv_interface_id[2];
1387 c->edx = cpu->hyperv_interface_id[3];
2344d22e
VK		 1388
1389 c = &cpuid_ent[cpuid_i++];
1390 c->function = HV_CPUID_VERSION;
af7228b8
VK		 1391 c->eax = cpu->hyperv_ver_id_build;
1392 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1393 cpu->hyperv_ver_id_minor;
1394 c->ecx = cpu->hyperv_ver_id_sp;
1395 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1396 (cpu->hyperv_ver_id_sn & 0xffffff);
2344d22e
VK		 1397
1398 c = &cpuid_ent[cpuid_i++];
1399 c->function = HV_CPUID_FEATURES;
061817a7
VK		 1400 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1401 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1402 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
c830015e 1403
b26f68c3
VK		 1404 /* Unconditionally required with any Hyper-V enlightenment */
1405 c->eax |= HV_HYPERCALL_AVAILABLE;
1406
cce087f6
VK		 1407 /* SynIC and Vmbus devices require messages/signals hypercalls */
1408 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1409 !cpu->hyperv_synic_kvm_only) {
1410 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1411 }
1412
05071629 1413
c830015e
VK		 1414 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1415 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
2344d22e
VK		 1416
1417 c = &cpuid_ent[cpuid_i++];
1418 c->function = HV_CPUID_ENLIGHTMENT_INFO;
061817a7 1419 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
2344d22e
VK		 1420 c->ebx = cpu->hyperv_spinlock_attempts;
1421
e1f9a8e8
VK		 1422 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1423 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
05071629
VK		 1424 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1425 }
1426
c830015e
VK		 1427 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1428 c->eax |= HV_NO_NONARCH_CORESHARING;
1429 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
a8439be6 1430 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
e1a66a1e 1431 HV_NO_NONARCH_CORESHARING;
c830015e
VK		 1432 }
1433
2344d22e
VK		 1434 c = &cpuid_ent[cpuid_i++];
1435 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1436 c->eax = cpu->hv_max_vps;
23eb5d03
VK		 1437 c->ebx = cpu->hyperv_limits[0];
1438 c->ecx = cpu->hyperv_limits[1];
1439 c->edx = cpu->hyperv_limits[2];
2344d22e
VK		 1440
1441 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
dc7d6caf 1442 uint32_t function;
2344d22e
VK		 1443
1444 /* Create zeroed 0x40000006..0x40000009 leaves */
1445 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1446 function < HV_CPUID_NESTED_FEATURES; function++) {
1447 c = &cpuid_ent[cpuid_i++];
1448 c->function = function;
1449 }
1450
1451 c = &cpuid_ent[cpuid_i++];
1452 c->function = HV_CPUID_NESTED_FEATURES;
c830015e 1453 c->eax = cpu->hyperv_nested[0];
2344d22e 1454 }
6760bd20 1455
a8439be6 1456 return cpuid_i;
c35bd19a
EY		 1457}
1458
e48ddcc6 1459static Error *hv_passthrough_mig_blocker;
30d6ff66 1460static Error *hv_no_nonarch_cs_mig_blocker;
e48ddcc6 1461
07454e2e
VK		 1462/* Checks that the exposed eVMCS version range is supported by KVM */
1463static bool evmcs_version_supported(uint16_t evmcs_version,
1464 uint16_t supported_evmcs_version)
1465{
1466 uint8_t min_version = evmcs_version & 0xff;
1467 uint8_t max_version = evmcs_version >> 8;
1468 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1469 uint8_t max_supported_version = supported_evmcs_version >> 8;
1470
1471 return (min_version >= min_supported_version) &&
1472 (max_version <= max_supported_version);
1473}
1474
1475#define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
1476
e9688fab
RK		 1477static int hyperv_init_vcpu(X86CPU *cpu)
1478{
729ce7e1 1479 CPUState *cs = CPU(cpu);
e48ddcc6 1480 Error *local_err = NULL;
729ce7e1
RK		 1481 int ret;
1482
e48ddcc6
VK		 1483 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1484 error_setg(&hv_passthrough_mig_blocker,
1485 "'hv-passthrough' CPU flag prevents migration, use explicit"
1486 " set of hv-* flags instead");
1487 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
436c831a 1488 if (ret < 0) {
e48ddcc6 1489 error_report_err(local_err);
e48ddcc6
VK		 1490 return ret;
1491 }
1492 }
1493
30d6ff66
VK		 1494 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1495 hv_no_nonarch_cs_mig_blocker == NULL) {
1496 error_setg(&hv_no_nonarch_cs_mig_blocker,
1497 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1498 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1499 " make sure SMT is disabled and/or that vCPUs are properly"
1500 " pinned)");
1501 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
436c831a 1502 if (ret < 0) {
30d6ff66 1503 error_report_err(local_err);
30d6ff66
VK		 1504 return ret;
1505 }
1506 }
1507
2d384d7c 1508 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1509 /*
1510 * the kernel doesn't support setting vp_index; assert that its value
1511 * is in sync
1512 */
e9688fab
RK		 1513 struct {
1514 struct kvm_msrs info;
1515 struct kvm_msr_entry entries[1];
1516 } msr_data = {
1517 .info.nmsrs = 1,
1518 .entries[0].index = HV_X64_MSR_VP_INDEX,
1519 };
1520
729ce7e1 1521 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1522 if (ret < 0) {
1523 return ret;
1524 }
1525 assert(ret == 1);
1526
701189e3 1527 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1528 error_report("kernel's vp_index != QEMU's vp_index");
1529 return -ENXIO;
1530 }
1531 }
1532
2d384d7c 1533 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1534 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1535 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1536 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1537 if (ret < 0) {
1538 error_report("failed to turn on HyperV SynIC in KVM: %s",
1539 strerror(-ret));
1540 return ret;
1541 }
606c34bf 1542
9b4cf107
RK		 1543 if (!cpu->hyperv_synic_kvm_only) {
1544 ret = hyperv_x86_synic_add(cpu);
1545 if (ret < 0) {
1546 error_report("failed to create HyperV SynIC: %s",
1547 strerror(-ret));
1548 return ret;
1549 }
606c34bf 1550 }
729ce7e1
RK		 1551 }
1552
decb4f20 1553 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
07454e2e
VK		 1554 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1555 uint16_t supported_evmcs_version;
decb4f20
VK		 1556
1557 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
07454e2e 1558 (uintptr_t)&supported_evmcs_version);
decb4f20 1559
07454e2e
VK		 1560 /*
1561 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1562 * option sets. Note: we hardcode the maximum supported eVMCS version
1563 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1564 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1565 * to be added.
1566 */
decb4f20 1567 if (ret < 0) {
07454e2e
VK		 1568 error_report("Hyper-V %s is not supported by kernel",
1569 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
decb4f20
VK		 1570 return ret;
1571 }
1572
07454e2e
VK		 1573 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1574 error_report("eVMCS version range [%d..%d] is not supported by "
1575 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1576 evmcs_version >> 8, supported_evmcs_version & 0xff,
1577 supported_evmcs_version >> 8);
1578 return -ENOTSUP;
1579 }
1580
decb4f20
VK		 1581 cpu->hyperv_nested[0] = evmcs_version;
1582 }
1583
70367f09
VK		 1584 if (cpu->hyperv_enforce_cpuid) {
1585 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1586 if (ret < 0) {
1587 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1588 strerror(-ret));
1589 return ret;
1590 }
1591 }
1592
e9688fab
RK		 1593 return 0;
1594}
1595
68bfd0ad
MT		 1596static Error *invtsc_mig_blocker;
1597
f8bb0565 1598#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1599
e56dd3c7
JL		 1600static void kvm_init_xsave(CPUX86State *env)
1601{
1602 if (has_xsave2) {
1603 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1604 } else if (has_xsave) {
1605 env->xsave_buf_len = sizeof(struct kvm_xsave);
1606 } else {
1607 return;
1608 }
1609
1610 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1611 memset(env->xsave_buf, 0, env->xsave_buf_len);
1612 /*
1613 * The allocated storage must be large enough for all of the
1614 * possible XSAVE state components.
1615 */
1616 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1617 env->xsave_buf_len);
1618}
1619
20d695a9 1620int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1621{
1622 struct {
486bd5a2 1623 struct kvm_cpuid2 cpuid;
f8bb0565 1624 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1625 } cpuid_data;
1626 /*
1627 * The kernel defines these structs with padding fields so there
1628 * should be no extra padding in our cpuid_data struct.
1629 */
1630 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1631 sizeof(struct kvm_cpuid2) +
1632 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1633
20d695a9
AF		 1634 X86CPU *cpu = X86_CPU(cs);
1635 CPUX86State *env = &cpu->env;
486bd5a2 1636 uint32_t limit, i, j, cpuid_i;
a33609ca 1637 uint32_t unused;
bb0300dc 1638 struct kvm_cpuid_entry2 *c;
bb0300dc 1639 uint32_t signature[3];
234cc647 1640 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1641 int max_nested_state_len;
e7429073 1642 int r;
fe44dc91 1643 Error *local_err = NULL;
05330448 1644
ef4cbe14
SW		 1645 memset(&cpuid_data, 0, sizeof(cpuid_data));
1646
05330448
AL		 1647 cpuid_i = 0;
1648
e56dd3c7
JL		 1649 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
1650
ddb98b5a
LP		 1651 r = kvm_arch_set_tsc_khz(cs);
1652 if (r < 0) {
6b2341ee 1653 return r;
ddb98b5a
LP		 1654 }
1655
1656 /* vcpu's TSC frequency is either specified by user, or following
1657 * the value used by KVM if the former is not present. In the
1658 * latter case, we query it from KVM and record in env->tsc_khz,
1659 * so that vcpu's TSC frequency can be migrated later via this field.
1660 */
1661 if (!env->tsc_khz) {
1662 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1663 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1664 -ENOTSUP;
1665 if (r > 0) {
1666 env->tsc_khz = r;
1667 }
1668 }
1669
73b994f6
LA		 1670 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1671
071ce4b0
VK		 1672 /*
1673 * kvm_hyperv_expand_features() is called here for the second time in case
1674 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
1675 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
1676 * check which Hyper-V enlightenments are supported and which are not, we
1677 * can still proceed and check/expand Hyper-V enlightenments here so legacy
1678 * behavior is preserved.
1679 */
1680 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
f4a62495
VK		 1681 error_report_err(local_err);
1682 return -ENOSYS;
f6e01ab5
VK		 1683 }
1684
1685 if (hyperv_enabled(cpu)) {
decb4f20
VK		 1686 r = hyperv_init_vcpu(cpu);
1687 if (r) {
1688 return r;
1689 }
1690
f6e01ab5 1691 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
234cc647 1692 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1693 has_msr_hv_hypercall = true;
eab70139
VR		 1694 }
1695
f522d2ac
AW		 1696 if (cpu->expose_kvm) {
1697 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1698 c = &cpuid_data.entries[cpuid_i++];
1699 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1700 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1701 c->ebx = signature[0];
1702 c->ecx = signature[1];
1703 c->edx = signature[2];
234cc647 1704
f522d2ac
AW		 1705 c = &cpuid_data.entries[cpuid_i++];
1706 c->function = KVM_CPUID_FEATURES | kvm_base;
1707 c->eax = env->features[FEAT_KVM];
be777326 1708 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1709 }
917367aa 1710
a33609ca 1711 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448 1712
988f7b8b
VK		 1713 if (cpu->kvm_pv_enforce_cpuid) {
1714 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
1715 if (r < 0) {
1716 fprintf(stderr,
1717 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
1718 strerror(-r));
1719 abort();
1720 }
1721 }
1722
05330448 1723 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1724 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1725 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1726 abort();
1727 }
bb0300dc 1728 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1729
1730 switch (i) {
a36b1029
AL		 1731 case 2: {
1732 /* Keep reading function 2 till all the input is received */
1733 int times;
1734
a36b1029 1735 c->function = i;
a33609ca
AL		 1736 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1737 KVM_CPUID_FLAG_STATE_READ_NEXT;
1738 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1739 times = c->eax & 0xff;
a36b1029
AL		 1740
1741 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1742 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1743 fprintf(stderr, "cpuid_data is full, no space for "
1744 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1745 abort();
1746 }
a33609ca 1747 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1748 c->function = i;
a33609ca
AL		 1749 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1750 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1751 }
1752 break;
1753 }
a94e1428
LX		 1754 case 0x1f:
1755 if (env->nr_dies < 2) {
1756 break;
1757 }
8821e214 1758 /* fallthrough */
486bd5a2
AL		 1759 case 4:
1760 case 0xb:
1761 case 0xd:
1762 for (j = 0; ; j++) {
31e8c696
AP		 1763 if (i == 0xd && j == 64) {
1764 break;
1765 }
a94e1428
LX		 1766
1767 if (i == 0x1f && j == 64) {
1768 break;
1769 }
1770
486bd5a2
AL		 1771 c->function = i;
1772 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1773 c->index = j;
a33609ca 1774 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1775
b9bec74b 1776 if (i == 4 && c->eax == 0) {
486bd5a2 1777 break;
b9bec74b
JK		 1778 }
1779 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1780 break;
b9bec74b 1781 }
a94e1428
LX		 1782 if (i == 0x1f && !(c->ecx & 0xff00)) {
1783 break;
1784 }
b9bec74b 1785 if (i == 0xd && c->eax == 0) {
31e8c696 1786 continue;
b9bec74b 1787 }
f8bb0565
IM		 1788 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1789 fprintf(stderr, "cpuid_data is full, no space for "
1790 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1791 abort();
1792 }
a33609ca 1793 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1794 }
1795 break;
80db491d 1796 case 0x7:
b9edbade
SC		 1797 case 0x12:
1798 for (j = 0; ; j++) {
1799 c->function = i;
1800 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1801 c->index = j;
1802 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1803
1804 if (j > 1 && (c->eax & 0xf) != 1) {
1805 break;
1806 }
1807
1808 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1809 fprintf(stderr, "cpuid_data is full, no space for "
1810 "cpuid(eax:0x12,ecx:0x%x)\n", j);
1811 abort();
1812 }
1813 c = &cpuid_data.entries[cpuid_i++];
1814 }
1815 break;
f21a4817
JL		 1816 case 0x14:
1817 case 0x1d:
1818 case 0x1e: {
e37a5c7f
CP		 1819 uint32_t times;
1820
1821 c->function = i;
1822 c->index = 0;
1823 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1824 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1825 times = c->eax;
1826
1827 for (j = 1; j <= times; ++j) {
1828 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1829 fprintf(stderr, "cpuid_data is full, no space for "
80db491d 1830 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
e37a5c7f
CP		 1831 abort();
1832 }
1833 c = &cpuid_data.entries[cpuid_i++];
1834 c->function = i;
1835 c->index = j;
1836 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1837 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1838 }
1839 break;
1840 }
486bd5a2 1841 default:
486bd5a2 1842 c->function = i;
a33609ca
AL		 1843 c->flags = 0;
1844 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1845 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1846 /*
1847 * KVM already returns all zeroes if a CPUID entry is missing,
1848 * so we can omit it and avoid hitting KVM's 80-entry limit.
1849 */
1850 cpuid_i--;
1851 }
486bd5a2
AL		 1852 break;
1853 }
05330448 1854 }
0d894367
PB		 1855
1856 if (limit >= 0x0a) {
0b368a10 1857 uint32_t eax, edx;
0d894367 1858
0b368a10
JD		 1859 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1860
1861 has_architectural_pmu_version = eax & 0xff;
1862 if (has_architectural_pmu_version > 0) {
1863 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1864
1865 /* Shouldn't be more than 32, since that's the number of bits
1866 * available in EBX to tell us _which_ counters are available.
1867 * Play it safe.
1868 */
0b368a10
JD		 1869 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1870 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1871 }
1872
1873 if (has_architectural_pmu_version > 1) {
1874 num_architectural_pmu_fixed_counters = edx & 0x1f;
1875
1876 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1877 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1878 }
0d894367
PB		 1879 }
1880 }
1881 }
1882
a33609ca 1883 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1884
1885 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1886 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1887 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1888 abort();
1889 }
bb0300dc 1890 c = &cpuid_data.entries[cpuid_i++];
05330448 1891
8f4202fb
BM		 1892 switch (i) {
1893 case 0x8000001d:
1894 /* Query for all AMD cache information leaves */
1895 for (j = 0; ; j++) {
1896 c->function = i;
1897 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1898 c->index = j;
1899 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1900
1901 if (c->eax == 0) {
1902 break;
1903 }
1904 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1905 fprintf(stderr, "cpuid_data is full, no space for "
1906 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1907 abort();
1908 }
1909 c = &cpuid_data.entries[cpuid_i++];
1910 }
1911 break;
1912 default:
1913 c->function = i;
1914 c->flags = 0;
1915 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1916 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1917 /*
1918 * KVM already returns all zeroes if a CPUID entry is missing,
1919 * so we can omit it and avoid hitting KVM's 80-entry limit.
1920 */
1921 cpuid_i--;
1922 }
8f4202fb
BM		 1923 break;
1924 }
05330448
AL		 1925 }
1926
b3baa152
BW		 1927 /* Call Centaur's CPUID instructions they are supported. */
1928 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1929 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1930
1931 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1932 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1933 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1934 abort();
1935 }
b3baa152
BW		 1936 c = &cpuid_data.entries[cpuid_i++];
1937
1938 c->function = i;
1939 c->flags = 0;
1940 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1941 }
1942 }
1943
05330448
AL		 1944 cpuid_data.cpuid.nent = cpuid_i;
1945
e7701825 1946 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1947 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1948 (CPUID_MCE | CPUID_MCA)
a60f24b5 1949 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1950 uint64_t mcg_cap, unsupported_caps;
e7701825 1951 int banks;
32a42024 1952 int ret;
e7701825 1953
a60f24b5 1954 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1955 if (ret < 0) {
1956 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1957 return ret;
e7701825 1958 }
75d49497 1959
2590f15b 1960 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1961 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1962 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1963 return -ENOTSUP;
75d49497 1964 }
49b69cbf 1965
5120901a
EH		 1966 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1967 if (unsupported_caps) {
87f8b626
AR		 1968 if (unsupported_caps & MCG_LMCE_P) {
1969 error_report("kvm: LMCE not supported");
1970 return -ENOTSUP;
1971 }
3dc6f869
AF		 1972 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1973 unsupported_caps);
5120901a
EH		 1974 }
1975
2590f15b
EH		 1976 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1977 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1978 if (ret < 0) {
1979 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1980 return ret;
1981 }
e7701825 1982 }
e7701825 1983
2a693142 1984 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
b8cc45d6 1985
df67696e
LJ		 1986 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1987 if (c) {
1988 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1989 !!(c->ecx & CPUID_EXT_SMX);
1990 }
1991
a0483541
SC		 1992 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
1993 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
1994 has_msr_feature_control = true;
1995 }
1996
87f8b626
AR		 1997 if (env->mcg_cap & MCG_LMCE_P) {
1998 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1999 }
2000
d99569d9
EH		 2001 if (!env->user_tsc_khz) {
2002 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2003 invtsc_mig_blocker == NULL) {
d99569d9
EH		 2004 error_setg(&invtsc_mig_blocker,
2005 "State blocked by non-migratable CPU device"
2006 " (invtsc flag)");
fe44dc91 2007 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
436c831a 2008 if (r < 0) {
fe44dc91 2009 error_report_err(local_err);
79a197ab 2010 return r;
fe44dc91 2011 }
d99569d9 2012 }
68bfd0ad
MT		 2013 }
2014
9954a158
PDJ		 2015 if (cpu->vmware_cpuid_freq
2016 /* Guests depend on 0x40000000 to detect this feature, so only expose
2017 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2018 && cpu->expose_kvm
2019 && kvm_base == KVM_CPUID_SIGNATURE
2020 /* TSC clock must be stable and known for this feature. */
4bb95b82 2021 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 2022
2023 c = &cpuid_data.entries[cpuid_i++];
2024 c->function = KVM_CPUID_SIGNATURE | 0x10;
2025 c->eax = env->tsc_khz;
73b994f6 2026 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
9954a158
PDJ		 2027 c->ecx = c->edx = 0;
2028
2029 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2030 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2031 }
2032
2033 cpuid_data.cpuid.nent = cpuid_i;
2034
2035 cpuid_data.cpuid.padding = 0;
2036 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2037 if (r) {
2038 goto fail;
2039 }
e56dd3c7 2040 kvm_init_xsave(env);
ebbfef2f
LA		 2041
2042 max_nested_state_len = kvm_max_nested_state_length();
2043 if (max_nested_state_len > 0) {
2044 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
ebbfef2f 2045
b16c0e20 2046 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
1e44f3ab 2047 struct kvm_vmx_nested_state_hdr *vmx_hdr;
ebbfef2f 2048
1e44f3ab
PB		 2049 env->nested_state = g_malloc0(max_nested_state_len);
2050 env->nested_state->size = max_nested_state_len;
1e44f3ab 2051
b16c0e20 2052 if (cpu_has_vmx(env)) {
2654ace1
TL		 2053 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
2054 vmx_hdr = &env->nested_state->hdr.vmx;
2055 vmx_hdr->vmxon_pa = -1ull;
2056 vmx_hdr->vmcs12_pa = -1ull;
2057 } else {
2058 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
b16c0e20 2059 }
ebbfef2f
LA		 2060 }
2061 }
2062
d71b62a1 2063 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 2064
273c515c
PB		 2065 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2066 has_msr_tsc_aux = false;
2067 }
d1ae67f6 2068
420ae1fc
PB		 2069 kvm_init_msrs(cpu);
2070
e7429073 2071 return 0;
fe44dc91
AA		 2072
2073 fail:
2074 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 2075
fe44dc91 2076 return r;
05330448
AL		 2077}
2078
b1115c99
LA		 2079int kvm_arch_destroy_vcpu(CPUState *cs)
2080{
2081 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 2082 CPUX86State *env = &cpu->env;
b1115c99
LA		 2083
2084 if (cpu->kvm_msr_buf) {
2085 g_free(cpu->kvm_msr_buf);
2086 cpu->kvm_msr_buf = NULL;
2087 }
2088
ebbfef2f
LA		 2089 if (env->nested_state) {
2090 g_free(env->nested_state);
2091 env->nested_state = NULL;
2092 }
2093
2a693142
PN		 2094 qemu_del_vm_change_state_handler(cpu->vmsentry);
2095
b1115c99
LA		 2096 return 0;
2097}
2098
50a2c6e5 2099void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 2100{
20d695a9 2101 CPUX86State *env = &cpu->env;
dd673288 2102
1a5e9d2f 2103 env->xcr0 = 1;
ddced198 2104 if (kvm_irqchip_in_kernel()) {
dd673288 2105 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 2106 KVM_MP_STATE_UNINITIALIZED;
2107 } else {
2108 env->mp_state = KVM_MP_STATE_RUNNABLE;
2109 }
689141dd 2110
2d384d7c 2111 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 2112 int i;
2113 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2114 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2115 }
606c34bf
RK		 2116
2117 hyperv_x86_synic_reset(cpu);
689141dd 2118 }
d645e132
MT		 2119 /* enabled by default */
2120 env->poll_control_msr = 1;
b2f73a07
PB		 2121
2122 sev_es_set_reset_vector(CPU(cpu));
caa5af0f
JK		 2123}
2124
e0723c45
PB		 2125void kvm_arch_do_init_vcpu(X86CPU *cpu)
2126{
2127 CPUX86State *env = &cpu->env;
2128
2129 /* APs get directly into wait-for-SIPI state. */
2130 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2131 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2132 }
2133}
2134
f57bceb6
RH		 2135static int kvm_get_supported_feature_msrs(KVMState *s)
2136{
2137 int ret = 0;
2138
2139 if (kvm_feature_msrs != NULL) {
2140 return 0;
2141 }
2142
2143 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2144 return 0;
2145 }
2146
2147 struct kvm_msr_list msr_list;
2148
2149 msr_list.nmsrs = 0;
2150 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2151 if (ret < 0 && ret != -E2BIG) {
2152 error_report("Fetch KVM feature MSR list failed: %s",
2153 strerror(-ret));
2154 return ret;
2155 }
2156
2157 assert(msr_list.nmsrs > 0);
2158 kvm_feature_msrs = (struct kvm_msr_list *) \
2159 g_malloc0(sizeof(msr_list) +
2160 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2161
2162 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2163 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2164
2165 if (ret < 0) {
2166 error_report("Fetch KVM feature MSR list failed: %s",
2167 strerror(-ret));
2168 g_free(kvm_feature_msrs);
2169 kvm_feature_msrs = NULL;
2170 return ret;
2171 }
2172
2173 return 0;
2174}
2175
c3a3a7d3 2176static int kvm_get_supported_msrs(KVMState *s)
05330448 2177{
c3a3a7d3 2178 int ret = 0;
de428cea 2179 struct kvm_msr_list msr_list, *kvm_msr_list;
05330448 2180
de428cea
LQ		 2181 /*
2182 * Obtain MSR list from KVM. These are the MSRs that we must
2183 * save/restore.
2184 */
2185 msr_list.nmsrs = 0;
2186 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2187 if (ret < 0 && ret != -E2BIG) {
2188 return ret;
2189 }
2190 /*
2191 * Old kernel modules had a bug and could write beyond the provided
2192 * memory. Allocate at least a safe amount of 1K.
2193 */
2194 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2195 msr_list.nmsrs *
2196 sizeof(msr_list.indices[0])));
05330448 2197
de428cea
LQ		 2198 kvm_msr_list->nmsrs = msr_list.nmsrs;
2199 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2200 if (ret >= 0) {
2201 int i;
05330448 2202
de428cea
LQ		 2203 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2204 switch (kvm_msr_list->indices[i]) {
2205 case MSR_STAR:
2206 has_msr_star = true;
2207 break;
2208 case MSR_VM_HSAVE_PA:
2209 has_msr_hsave_pa = true;
2210 break;
2211 case MSR_TSC_AUX:
2212 has_msr_tsc_aux = true;
2213 break;
2214 case MSR_TSC_ADJUST:
2215 has_msr_tsc_adjust = true;
2216 break;
2217 case MSR_IA32_TSCDEADLINE:
2218 has_msr_tsc_deadline = true;
2219 break;
2220 case MSR_IA32_SMBASE:
2221 has_msr_smbase = true;
2222 break;
2223 case MSR_SMI_COUNT:
2224 has_msr_smi_count = true;
2225 break;
2226 case MSR_IA32_MISC_ENABLE:
2227 has_msr_misc_enable = true;
2228 break;
2229 case MSR_IA32_BNDCFGS:
2230 has_msr_bndcfgs = true;
2231 break;
2232 case MSR_IA32_XSS:
2233 has_msr_xss = true;
2234 break;
65087997
TX		 2235 case MSR_IA32_UMWAIT_CONTROL:
2236 has_msr_umwait = true;
2237 break;
de428cea
LQ		 2238 case HV_X64_MSR_CRASH_CTL:
2239 has_msr_hv_crash = true;
2240 break;
2241 case HV_X64_MSR_RESET:
2242 has_msr_hv_reset = true;
2243 break;
2244 case HV_X64_MSR_VP_INDEX:
2245 has_msr_hv_vpindex = true;
2246 break;
2247 case HV_X64_MSR_VP_RUNTIME:
2248 has_msr_hv_runtime = true;
2249 break;
2250 case HV_X64_MSR_SCONTROL:
2251 has_msr_hv_synic = true;
2252 break;
2253 case HV_X64_MSR_STIMER0_CONFIG:
2254 has_msr_hv_stimer = true;
2255 break;
2256 case HV_X64_MSR_TSC_FREQUENCY:
2257 has_msr_hv_frequencies = true;
2258 break;
2259 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2260 has_msr_hv_reenlightenment = true;
2261 break;
2262 case MSR_IA32_SPEC_CTRL:
2263 has_msr_spec_ctrl = true;
2264 break;
cabf9862
ML		 2265 case MSR_AMD64_TSC_RATIO:
2266 has_tsc_scale_msr = true;
2267 break;
2a9758c5
PB		 2268 case MSR_IA32_TSX_CTRL:
2269 has_msr_tsx_ctrl = true;
2270 break;
de428cea
LQ		 2271 case MSR_VIRT_SSBD:
2272 has_msr_virt_ssbd = true;
2273 break;
2274 case MSR_IA32_ARCH_CAPABILITIES:
2275 has_msr_arch_capabs = true;
2276 break;
2277 case MSR_IA32_CORE_CAPABILITY:
2278 has_msr_core_capabs = true;
2279 break;
ea39f9b6
LX		 2280 case MSR_IA32_PERF_CAPABILITIES:
2281 has_msr_perf_capabs = true;
2282 break;
20a78b02
PB		 2283 case MSR_IA32_VMX_VMFUNC:
2284 has_msr_vmx_vmfunc = true;
2285 break;
67025148
PB		 2286 case MSR_IA32_UCODE_REV:
2287 has_msr_ucode_rev = true;
2288 break;
4a910e1f
VK		 2289 case MSR_IA32_VMX_PROCBASED_CTLS2:
2290 has_msr_vmx_procbased_ctls2 = true;
2291 break;
6aa4228b
CQ		 2292 case MSR_IA32_PKRS:
2293 has_msr_pkrs = true;
2294 break;
05330448
AL		 2295 }
2296 }
05330448
AL		 2297 }
2298
de428cea
LQ		 2299 g_free(kvm_msr_list);
2300
c3a3a7d3 2301 return ret;
05330448
AL		 2302}
2303
6410848b
PB		 2304static Notifier smram_machine_done;
2305static KVMMemoryListener smram_listener;
2306static AddressSpace smram_address_space;
2307static MemoryRegion smram_as_root;
2308static MemoryRegion smram_as_mem;
2309
2310static void register_smram_listener(Notifier *n, void *unused)
2311{
2312 MemoryRegion *smram =
2313 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2314
2315 /* Outer container... */
2316 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2317 memory_region_set_enabled(&smram_as_root, true);
2318
2319 /* ... with two regions inside: normal system memory with low
2320 * priority, and...
2321 */
2322 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2323 get_system_memory(), 0, ~0ull);
2324 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2325 memory_region_set_enabled(&smram_as_mem, true);
2326
2327 if (smram) {
2328 /* ... SMRAM with higher priority */
2329 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2330 memory_region_set_enabled(smram, true);
2331 }
2332
2333 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2334 kvm_memory_listener_register(kvm_state, &smram_listener,
142518bd 2335 &smram_address_space, 1, "kvm-smram");
6410848b
PB		 2336}
2337
b16565b3 2338int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 2339{
11076198 2340 uint64_t identity_base = 0xfffbc000;
39d6960a 2341 uint64_t shadow_mem;
20420430 2342 int ret;
25d2e361 2343 struct utsname utsname;
ec78e2cd
DG		 2344 Error *local_err = NULL;
2345
2346 /*
2347 * Initialize SEV context, if required
2348 *
2349 * If no memory encryption is requested (ms->cgs == NULL) this is
2350 * a no-op.
2351 *
2352 * It's also a no-op if a non-SEV confidential guest support
2353 * mechanism is selected. SEV is the only mechanism available to
2354 * select on x86 at present, so this doesn't arise, but if new
2355 * mechanisms are supported in future (e.g. TDX), they'll need
2356 * their own initialization either here or elsewhere.
2357 */
2358 ret = sev_kvm_init(ms->cgs, &local_err);
2359 if (ret < 0) {
2360 error_report_err(local_err);
2361 return ret;
2362 }
20420430 2363
1a6dff5f
EH		 2364 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2365 error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM");
2366 return -ENOTSUP;
2367 }
2368
28143b40 2369 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 2370 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 2371 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
8f515d38 2372 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
28143b40 2373
e9688fab
RK		 2374 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2375
fd13f23b
LA		 2376 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2377 if (has_exception_payload) {
2378 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2379 if (ret < 0) {
2380 error_report("kvm: Failed to enable exception payload cap: %s",
2381 strerror(-ret));
2382 return ret;
2383 }
2384 }
2385
c3a3a7d3 2386 ret = kvm_get_supported_msrs(s);
20420430 2387 if (ret < 0) {
20420430
SY		 2388 return ret;
2389 }
25d2e361 2390
f57bceb6
RH		 2391 kvm_get_supported_feature_msrs(s);
2392
25d2e361
MT		 2393 uname(&utsname);
2394 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2395
4c5b10b7 2396 /*
11076198
JK		 2397 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2398 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2399 * Since these must be part of guest physical memory, we need to allocate
2400 * them, both by setting their start addresses in the kernel and by
2401 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2402 *
2403 * Older KVM versions may not support setting the identity map base. In
2404 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2405 * size.
4c5b10b7 2406 */
11076198
JK		 2407 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2408 /* Allows up to 16M BIOSes. */
2409 identity_base = 0xfeffc000;
2410
2411 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2412 if (ret < 0) {
2413 return ret;
2414 }
4c5b10b7 2415 }
e56ff191 2416
11076198
JK		 2417 /* Set TSS base one page after EPT identity map. */
2418 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2419 if (ret < 0) {
2420 return ret;
2421 }
2422
11076198
JK		 2423 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2424 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2425 if (ret < 0) {
11076198 2426 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2427 return ret;
2428 }
2429
23b0898e 2430 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
36ad0e94
MA		 2431 if (shadow_mem != -1) {
2432 shadow_mem /= 4096;
2433 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2434 if (ret < 0) {
2435 return ret;
39d6960a
JK		 2436 }
2437 }
6410848b 2438
d870cfde 2439 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
8f54bbd0 2440 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
ed9e923c 2441 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
6410848b
PB		 2442 smram_machine_done.notify = register_smram_listener;
2443 qemu_add_machine_init_done_notifier(&smram_machine_done);
2444 }
6f131f13
MT		 2445
2446 if (enable_cpu_pm) {
2447 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2448 int ret;
2449
2450/* Work around for kernel header with a typo. TODO: fix header and drop. */
2451#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2452#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2453#endif
2454 if (disable_exits) {
2455 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2456 KVM_X86_DISABLE_EXITS_HLT |
d38d201f
WL		 2457 KVM_X86_DISABLE_EXITS_PAUSE |
2458 KVM_X86_DISABLE_EXITS_CSTATE);
6f131f13
MT		 2459 }
2460
2461 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2462 disable_exits);
2463 if (ret < 0) {
2464 error_report("kvm: guest stopping CPU not supported: %s",
2465 strerror(-ret));
2466 }
2467 }
2468
035d1ef2
CQ		 2469 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
2470 X86MachineState *x86ms = X86_MACHINE(ms);
2471
2472 if (x86ms->bus_lock_ratelimit > 0) {
2473 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
2474 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
2475 error_report("kvm: bus lock detection unsupported");
2476 return -ENOTSUP;
2477 }
2478 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
2479 KVM_BUS_LOCK_DETECTION_EXIT);
2480 if (ret < 0) {
2481 error_report("kvm: Failed to enable bus lock detection cap: %s",
2482 strerror(-ret));
2483 return ret;
2484 }
2485 ratelimit_init(&bus_lock_ratelimit_ctrl);
2486 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
2487 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
2488 }
2489 }
2490
11076198 2491 return 0;
05330448 2492}
b9bec74b 2493
05330448
AL		 2494static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2495{
2496 lhs->selector = rhs->selector;
2497 lhs->base = rhs->base;
2498 lhs->limit = rhs->limit;
2499 lhs->type = 3;
2500 lhs->present = 1;
2501 lhs->dpl = 3;
2502 lhs->db = 0;
2503 lhs->s = 1;
2504 lhs->l = 0;
2505 lhs->g = 0;
2506 lhs->avl = 0;
2507 lhs->unusable = 0;
2508}
2509
2510static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2511{
2512 unsigned flags = rhs->flags;
2513 lhs->selector = rhs->selector;
2514 lhs->base = rhs->base;
2515 lhs->limit = rhs->limit;
2516 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2517 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2518 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2519 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2520 lhs->s = (flags & DESC_S_MASK) != 0;
2521 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2522 lhs->g = (flags & DESC_G_MASK) != 0;
2523 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2524 lhs->unusable = !lhs->present;
7e680753 2525 lhs->padding = 0;
05330448
AL		 2526}
2527
2528static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2529{
2530 lhs->selector = rhs->selector;
2531 lhs->base = rhs->base;
2532 lhs->limit = rhs->limit;
d45fc087
RP		 2533 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2534 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2535 (rhs->dpl << DESC_DPL_SHIFT) |
2536 (rhs->db << DESC_B_SHIFT) |
2537 (rhs->s * DESC_S_MASK) |
2538 (rhs->l << DESC_L_SHIFT) |
2539 (rhs->g * DESC_G_MASK) |
2540 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2541}
2542
2543static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2544{
b9bec74b 2545 if (set) {
05330448 2546 *kvm_reg = *qemu_reg;
b9bec74b 2547 } else {
05330448 2548 *qemu_reg = *kvm_reg;
b9bec74b 2549 }
05330448
AL		 2550}
2551
1bc22652 2552static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2553{
1bc22652 2554 CPUX86State *env = &cpu->env;
05330448
AL		 2555 struct kvm_regs regs;
2556 int ret = 0;
2557
2558 if (!set) {
1bc22652 2559 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2560 if (ret < 0) {
05330448 2561 return ret;
b9bec74b 2562 }
05330448
AL		 2563 }
2564
2565 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2566 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2567 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2568 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2569 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2570 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2571 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2572 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2573#ifdef TARGET_X86_64
2574 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2575 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2576 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2577 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2578 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2579 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2580 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2581 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2582#endif
2583
2584 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2585 kvm_getput_reg(&regs.rip, &env->eip, set);
2586
b9bec74b 2587 if (set) {
1bc22652 2588 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2589 }
05330448
AL		 2590
2591 return ret;
2592}
2593
1bc22652 2594static int kvm_put_fpu(X86CPU *cpu)
05330448 2595{
1bc22652 2596 CPUX86State *env = &cpu->env;
05330448
AL		 2597 struct kvm_fpu fpu;
2598 int i;
2599
2600 memset(&fpu, 0, sizeof fpu);
2601 fpu.fsw = env->fpus & ~(7 << 11);
2602 fpu.fsw |= (env->fpstt & 7) << 11;
2603 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2604 fpu.last_opcode = env->fpop;
2605 fpu.last_ip = env->fpip;
2606 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2607 for (i = 0; i < 8; ++i) {
2608 fpu.ftwx |= (!env->fptags[i]) << i;
2609 }
05330448 2610 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2611 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2612 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2613 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2614 }
05330448
AL		 2615 fpu.mxcsr = env->mxcsr;
2616
1bc22652 2617 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2618}
2619
1bc22652 2620static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2621{
1bc22652 2622 CPUX86State *env = &cpu->env;
c0198c5f 2623 void *xsave = env->xsave_buf;
f1665b21 2624
28143b40 2625 if (!has_xsave) {
1bc22652 2626 return kvm_put_fpu(cpu);
b9bec74b 2627 }
c0198c5f 2628 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
f1665b21 2629
9be38598 2630 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2631}
2632
1bc22652 2633static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2634{
1bc22652 2635 CPUX86State *env = &cpu->env;
bdfc8480 2636 struct kvm_xcrs xcrs = {};
f1665b21 2637
28143b40 2638 if (!has_xcrs) {
f1665b21 2639 return 0;
b9bec74b 2640 }
f1665b21
SY		 2641
2642 xcrs.nr_xcrs = 1;
2643 xcrs.flags = 0;
2644 xcrs.xcrs[0].xcr = 0;
2645 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2646 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2647}
2648
1bc22652 2649static int kvm_put_sregs(X86CPU *cpu)
05330448 2650{
1bc22652 2651 CPUX86State *env = &cpu->env;
05330448
AL		 2652 struct kvm_sregs sregs;
2653
1520f8bb
PB		 2654 /*
2655 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
2656 * always followed by KVM_SET_VCPU_EVENTS.
2657 */
0e607a80 2658 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
05330448
AL		 2659
2660 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2661 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2662 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2663 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2664 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2665 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2666 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2667 } else {
b9bec74b
JK		 2668 set_seg(&sregs.cs, &env->segs[R_CS]);
2669 set_seg(&sregs.ds, &env->segs[R_DS]);
2670 set_seg(&sregs.es, &env->segs[R_ES]);
2671 set_seg(&sregs.fs, &env->segs[R_FS]);
2672 set_seg(&sregs.gs, &env->segs[R_GS]);
2673 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2674 }
2675
2676 set_seg(&sregs.tr, &env->tr);
2677 set_seg(&sregs.ldt, &env->ldt);
2678
2679 sregs.idt.limit = env->idt.limit;
2680 sregs.idt.base = env->idt.base;
7e680753 2681 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2682 sregs.gdt.limit = env->gdt.limit;
2683 sregs.gdt.base = env->gdt.base;
7e680753 2684 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2685
2686 sregs.cr0 = env->cr[0];
2687 sregs.cr2 = env->cr[2];
2688 sregs.cr3 = env->cr[3];
2689 sregs.cr4 = env->cr[4];
2690
02e51483
CF		 2691 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2692 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2693
2694 sregs.efer = env->efer;
2695
1bc22652 2696 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2697}
2698
8f515d38
ML		 2699static int kvm_put_sregs2(X86CPU *cpu)
2700{
2701 CPUX86State *env = &cpu->env;
2702 struct kvm_sregs2 sregs;
2703 int i;
2704
2705 sregs.flags = 0;
2706
2707 if ((env->eflags & VM_MASK)) {
2708 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2709 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2710 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2711 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2712 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2713 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2714 } else {
2715 set_seg(&sregs.cs, &env->segs[R_CS]);
2716 set_seg(&sregs.ds, &env->segs[R_DS]);
2717 set_seg(&sregs.es, &env->segs[R_ES]);
2718 set_seg(&sregs.fs, &env->segs[R_FS]);
2719 set_seg(&sregs.gs, &env->segs[R_GS]);
2720 set_seg(&sregs.ss, &env->segs[R_SS]);
2721 }
2722
2723 set_seg(&sregs.tr, &env->tr);
2724 set_seg(&sregs.ldt, &env->ldt);
2725
2726 sregs.idt.limit = env->idt.limit;
2727 sregs.idt.base = env->idt.base;
2728 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2729 sregs.gdt.limit = env->gdt.limit;
2730 sregs.gdt.base = env->gdt.base;
2731 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2732
2733 sregs.cr0 = env->cr[0];
2734 sregs.cr2 = env->cr[2];
2735 sregs.cr3 = env->cr[3];
2736 sregs.cr4 = env->cr[4];
2737
2738 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2739 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2740
2741 sregs.efer = env->efer;
2742
2743 if (env->pdptrs_valid) {
2744 for (i = 0; i < 4; i++) {
2745 sregs.pdptrs[i] = env->pdptrs[i];
2746 }
2747 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
2748 }
2749
2750 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
2751}
2752
2753
d71b62a1
EH		 2754static void kvm_msr_buf_reset(X86CPU *cpu)
2755{
2756 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2757}
2758
9c600a84
EH		 2759static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2760{
2761 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2762 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2763 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2764
2765 assert((void *)(entry + 1) <= limit);
2766
1abc2cae
EH		 2767 entry->index = index;
2768 entry->reserved = 0;
2769 entry->data = value;
9c600a84
EH		 2770 msrs->nmsrs++;
2771}
2772
73e1b8f2
PB		 2773static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2774{
2775 kvm_msr_buf_reset(cpu);
2776 kvm_msr_entry_add(cpu, index, value);
2777
2778 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2779}
2780
f8d9ccf8
DDAG		 2781void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2782{
2783 int ret;
2784
2785 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2786 assert(ret == 1);
2787}
2788
7477cd38
MT		 2789static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2790{
2791 CPUX86State *env = &cpu->env;
48e1a45c 2792 int ret;
7477cd38
MT		 2793
2794 if (!has_msr_tsc_deadline) {
2795 return 0;
2796 }
2797
73e1b8f2 2798 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2799 if (ret < 0) {
2800 return ret;
2801 }
2802
2803 assert(ret == 1);
2804 return 0;
7477cd38
MT		 2805}
2806
6bdf863d
JK		 2807/*
2808 * Provide a separate write service for the feature control MSR in order to
2809 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2810 * before writing any other state because forcibly leaving nested mode
2811 * invalidates the VCPU state.
2812 */
2813static int kvm_put_msr_feature_control(X86CPU *cpu)
2814{
48e1a45c
PB		 2815 int ret;
2816
2817 if (!has_msr_feature_control) {
2818 return 0;
2819 }
6bdf863d 2820
73e1b8f2
PB		 2821 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2822 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2823 if (ret < 0) {
2824 return ret;
2825 }
2826
2827 assert(ret == 1);
2828 return 0;
6bdf863d
JK		 2829}
2830
20a78b02
PB		 2831static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2832{
2833 uint32_t default1, can_be_one, can_be_zero;
2834 uint32_t must_be_one;
2835
2836 switch (index) {
2837 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2838 default1 = 0x00000016;
2839 break;
2840 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2841 default1 = 0x0401e172;
2842 break;
2843 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2844 default1 = 0x000011ff;
2845 break;
2846 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2847 default1 = 0x00036dff;
2848 break;
2849 case MSR_IA32_VMX_PROCBASED_CTLS2:
2850 default1 = 0;
2851 break;
2852 default:
2853 abort();
2854 }
2855
2856 /* If a feature bit is set, the control can be either set or clear.
2857 * Otherwise the value is limited to either 0 or 1 by default1.
2858 */
2859 can_be_one = features | default1;
2860 can_be_zero = features | ~default1;
2861 must_be_one = ~can_be_zero;
2862
2863 /*
2864 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2865 * Bit 32:63 -> 1 if the control bit can be one.
2866 */
2867 return must_be_one | (((uint64_t)can_be_one) << 32);
2868}
2869
20a78b02
PB		 2870static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2871{
2872 uint64_t kvm_vmx_basic =
2873 kvm_arch_get_supported_msr_feature(kvm_state,
2874 MSR_IA32_VMX_BASIC);
26051882
YZ		 2875
2876 if (!kvm_vmx_basic) {
2877 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2878 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2879 */
2880 return;
2881 }
2882
20a78b02
PB		 2883 uint64_t kvm_vmx_misc =
2884 kvm_arch_get_supported_msr_feature(kvm_state,
2885 MSR_IA32_VMX_MISC);
2886 uint64_t kvm_vmx_ept_vpid =
2887 kvm_arch_get_supported_msr_feature(kvm_state,
2888 MSR_IA32_VMX_EPT_VPID_CAP);
2889
2890 /*
2891 * If the guest is 64-bit, a value of 1 is allowed for the host address
2892 * space size vmexit control.
2893 */
2894 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2895 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2896
2897 /*
2898 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2899 * not change them for backwards compatibility.
2900 */
2901 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2902 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2903 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2904 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2905
2906 /*
2907 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2908 * change in the future but are always zero for now, clear them to be
2909 * future proof. Bits 32-63 in theory could change, though KVM does
2910 * not support dual-monitor treatment and probably never will; mask
2911 * them out as well.
2912 */
2913 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2914 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2915 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2916
2917 /*
2918 * EPT memory types should not change either, so we do not bother
2919 * adding features for them.
2920 */
2921 uint64_t fixed_vmx_ept_mask =
2922 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2923 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2924 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2925
2926 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2927 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2928 f[FEAT_VMX_PROCBASED_CTLS]));
2929 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2930 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2931 f[FEAT_VMX_PINBASED_CTLS]));
2932 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2933 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2934 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2935 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2936 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2937 f[FEAT_VMX_ENTRY_CTLS]));
2938 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2939 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2940 f[FEAT_VMX_SECONDARY_CTLS]));
2941 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2942 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2943 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2944 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2945 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2946 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2947 if (has_msr_vmx_vmfunc) {
2948 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2949 }
2950
2951 /*
2952 * Just to be safe, write these with constant values. The CRn_FIXED1
2953 * MSRs are generated by KVM based on the vCPU's CPUID.
2954 */
2955 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2956 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2957 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2958 CR4_VMXE_MASK);
9ce8af4d
PB		 2959
2960 if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
2961 /* TSC multiplier (0x2032). */
2962 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
2963 } else {
2964 /* Preemption timer (0x482E). */
2965 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
2966 }
20a78b02
PB		 2967}
2968
ea39f9b6
LX		 2969static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
2970{
2971 uint64_t kvm_perf_cap =
2972 kvm_arch_get_supported_msr_feature(kvm_state,
2973 MSR_IA32_PERF_CAPABILITIES);
2974
2975 if (kvm_perf_cap) {
2976 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
2977 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
2978 }
2979}
2980
420ae1fc
PB		 2981static int kvm_buf_set_msrs(X86CPU *cpu)
2982{
2983 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2984 if (ret < 0) {
2985 return ret;
2986 }
2987
2988 if (ret < cpu->kvm_msr_buf->nmsrs) {
2989 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2990 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2991 (uint32_t)e->index, (uint64_t)e->data);
2992 }
2993
2994 assert(ret == cpu->kvm_msr_buf->nmsrs);
2995 return 0;
2996}
2997
2998static void kvm_init_msrs(X86CPU *cpu)
2999{
3000 CPUX86State *env = &cpu->env;
3001
3002 kvm_msr_buf_reset(cpu);
3003 if (has_msr_arch_capabs) {
3004 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3005 env->features[FEAT_ARCH_CAPABILITIES]);
3006 }
3007
3008 if (has_msr_core_capabs) {
3009 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3010 env->features[FEAT_CORE_CAPABILITY]);
3011 }
3012
ea39f9b6
LX		 3013 if (has_msr_perf_capabs && cpu->enable_pmu) {
3014 kvm_msr_entry_add_perf(cpu, env->features);
3015 }
3016
67025148 3017 if (has_msr_ucode_rev) {
32c87d70
PB		 3018 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3019 }
3020
420ae1fc
PB		 3021 /*
3022 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3023 * all kernels with MSR features should have them.
3024 */
3025 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3026 kvm_msr_entry_add_vmx(cpu, env->features);
3027 }
3028
3029 assert(kvm_buf_set_msrs(cpu) == 0);
3030}
3031
1bc22652 3032static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 3033{
1bc22652 3034 CPUX86State *env = &cpu->env;
9c600a84 3035 int i;
05330448 3036
d71b62a1
EH		 3037 kvm_msr_buf_reset(cpu);
3038
9c600a84
EH		 3039 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3040 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3041 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3042 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 3043 if (has_msr_star) {
9c600a84 3044 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 3045 }
c3a3a7d3 3046 if (has_msr_hsave_pa) {
9c600a84 3047 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 3048 }
c9b8f6b6 3049 if (has_msr_tsc_aux) {
9c600a84 3050 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 3051 }
f28558d3 3052 if (has_msr_tsc_adjust) {
9c600a84 3053 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 3054 }
21e87c46 3055 if (has_msr_misc_enable) {
9c600a84 3056 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 3057 env->msr_ia32_misc_enable);
3058 }
fc12d72e 3059 if (has_msr_smbase) {
9c600a84 3060 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 3061 }
e13713db
LA		 3062 if (has_msr_smi_count) {
3063 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3064 }
6aa4228b
CQ		 3065 if (has_msr_pkrs) {
3066 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3067 }
439d19f2 3068 if (has_msr_bndcfgs) {
9c600a84 3069 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 3070 }
18cd2c17 3071 if (has_msr_xss) {
9c600a84 3072 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 3073 }
65087997
TX		 3074 if (has_msr_umwait) {
3075 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3076 }
a33a2cfe
PB		 3077 if (has_msr_spec_ctrl) {
3078 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3079 }
cabf9862
ML		 3080 if (has_tsc_scale_msr) {
3081 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3082 }
3083
2a9758c5
PB		 3084 if (has_msr_tsx_ctrl) {
3085 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3086 }
cfeea0c0
KRW		 3087 if (has_msr_virt_ssbd) {
3088 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3089 }
3090
05330448 3091#ifdef TARGET_X86_64
25d2e361 3092 if (lm_capable_kernel) {
9c600a84
EH		 3093 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3094 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3095 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3096 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 3097 }
05330448 3098#endif
a33a2cfe 3099
ff5c186b 3100 /*
0d894367
PB		 3101 * The following MSRs have side effects on the guest or are too heavy
3102 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 3103 */
3104 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 3105 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
3106 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
3107 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
6615be07
VK		 3108 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3109 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
3110 }
55c911a5 3111 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 3112 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 3113 }
55c911a5 3114 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3115 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 3116 }
55c911a5 3117 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3118 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 3119 }
d645e132
MT		 3120
3121 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3122 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
3123 }
3124
0b368a10
JD		 3125 if (has_architectural_pmu_version > 0) {
3126 if (has_architectural_pmu_version > 1) {
3127 /* Stop the counter. */
3128 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3129 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3130 }
0d894367
PB		 3131
3132 /* Set the counter values. */
0b368a10 3133 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3134 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 3135 env->msr_fixed_counters[i]);
3136 }
0b368a10 3137 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 3138 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 3139 env->msr_gp_counters[i]);
9c600a84 3140 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 3141 env->msr_gp_evtsel[i]);
3142 }
0b368a10
JD		 3143 if (has_architectural_pmu_version > 1) {
3144 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
3145 env->msr_global_status);
3146 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
3147 env->msr_global_ovf_ctrl);
3148
3149 /* Now start the PMU. */
3150 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
3151 env->msr_fixed_ctr_ctrl);
3152 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
3153 env->msr_global_ctrl);
3154 }
0d894367 3155 }
da1cc323
EY		 3156 /*
3157 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
3158 * only sync them to KVM on the first cpu
3159 */
3160 if (current_cpu == first_cpu) {
3161 if (has_msr_hv_hypercall) {
3162 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
3163 env->msr_hv_guest_os_id);
3164 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
3165 env->msr_hv_hypercall);
3166 }
2d384d7c 3167 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 3168 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
3169 env->msr_hv_tsc);
3170 }
2d384d7c 3171 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3172 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
3173 env->msr_hv_reenlightenment_control);
3174 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
3175 env->msr_hv_tsc_emulation_control);
3176 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
3177 env->msr_hv_tsc_emulation_status);
3178 }
eab70139 3179 }
2d384d7c 3180 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3181 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 3182 env->msr_hv_vapic);
eab70139 3183 }
f2a53c9e
AS		 3184 if (has_msr_hv_crash) {
3185 int j;
3186
5e953812 3187 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 3188 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 3189 env->msr_hv_crash_params[j]);
3190
5e953812 3191 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 3192 }
46eb8f98 3193 if (has_msr_hv_runtime) {
9c600a84 3194 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 3195 }
2d384d7c
VK		 3196 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
3197 && hv_vpindex_settable) {
701189e3
RK		 3198 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
3199 hyperv_vp_index(CPU(cpu)));
e9688fab 3200 }
2d384d7c 3201 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3202 int j;
3203
09df29b6
RK		 3204 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
3205
9c600a84 3206 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 3207 env->msr_hv_synic_control);
9c600a84 3208 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 3209 env->msr_hv_synic_evt_page);
9c600a84 3210 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 3211 env->msr_hv_synic_msg_page);
3212
3213 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 3214 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 3215 env->msr_hv_synic_sint[j]);
3216 }
3217 }
ff99aa64
AS		 3218 if (has_msr_hv_stimer) {
3219 int j;
3220
3221 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 3222 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 3223 env->msr_hv_stimer_config[j]);
3224 }
3225
3226 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 3227 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 3228 env->msr_hv_stimer_count[j]);
3229 }
3230 }
1eabfce6 3231 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 3232 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
3233
9c600a84
EH		 3234 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
3235 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
3236 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
3237 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
3238 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
3239 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
3240 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
3241 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
3242 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
3243 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
3244 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
3245 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 3246 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 3247 /* The CPU GPs if we write to a bit above the physical limit of
3248 * the host CPU (and KVM emulates that)
3249 */
3250 uint64_t mask = env->mtrr_var[i].mask;
3251 mask &= phys_mask;
3252
9c600a84
EH		 3253 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
3254 env->mtrr_var[i].base);
112dad69 3255 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 3256 }
3257 }
b77146e9
CP		 3258 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3259 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
3260 0x14, 1, R_EAX) & 0x7;
3261
3262 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
3263 env->msr_rtit_ctrl);
3264 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
3265 env->msr_rtit_status);
3266 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
3267 env->msr_rtit_output_base);
3268 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
3269 env->msr_rtit_output_mask);
3270 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
3271 env->msr_rtit_cr3_match);
3272 for (i = 0; i < addr_num; i++) {
3273 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
3274 env->msr_rtit_addrs[i]);
3275 }
3276 }
6bdf863d 3277
db888065
SC		 3278 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
3279 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
3280 env->msr_ia32_sgxlepubkeyhash[0]);
3281 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
3282 env->msr_ia32_sgxlepubkeyhash[1]);
3283 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
3284 env->msr_ia32_sgxlepubkeyhash[2]);
3285 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
3286 env->msr_ia32_sgxlepubkeyhash[3]);
3287 }
3288
cdec2b75
ZG		 3289 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
3290 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
3291 env->msr_xfd);
3292 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
3293 env->msr_xfd_err);
3294 }
3295
6bdf863d
JK		 3296 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
3297 * kvm_put_msr_feature_control. */
ea643051 3298 }
20a78b02 3299
57780495 3300 if (env->mcg_cap) {
d8da8574 3301 int i;
b9bec74b 3302
9c600a84
EH		 3303 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
3304 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 3305 if (has_msr_mcg_ext_ctl) {
3306 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3307 }
c34d440a 3308 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3309 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 3310 }
3311 }
1a03675d 3312
420ae1fc 3313 return kvm_buf_set_msrs(cpu);
05330448
AL		 3314}
3315
3316
1bc22652 3317static int kvm_get_fpu(X86CPU *cpu)
05330448 3318{
1bc22652 3319 CPUX86State *env = &cpu->env;
05330448
AL		 3320 struct kvm_fpu fpu;
3321 int i, ret;
3322
1bc22652 3323 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 3324 if (ret < 0) {
05330448 3325 return ret;
b9bec74b 3326 }
05330448
AL		 3327
3328 env->fpstt = (fpu.fsw >> 11) & 7;
3329 env->fpus = fpu.fsw;
3330 env->fpuc = fpu.fcw;
42cc8fa6
JK		 3331 env->fpop = fpu.last_opcode;
3332 env->fpip = fpu.last_ip;
3333 env->fpdp = fpu.last_dp;
b9bec74b
JK		 3334 for (i = 0; i < 8; ++i) {
3335 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3336 }
05330448 3337 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 3338 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 3339 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3340 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 3341 }
05330448
AL		 3342 env->mxcsr = fpu.mxcsr;
3343
3344 return 0;
3345}
3346
1bc22652 3347static int kvm_get_xsave(X86CPU *cpu)
f1665b21 3348{
1bc22652 3349 CPUX86State *env = &cpu->env;
c0198c5f 3350 void *xsave = env->xsave_buf;
e56dd3c7 3351 int type, ret;
f1665b21 3352
28143b40 3353 if (!has_xsave) {
1bc22652 3354 return kvm_get_fpu(cpu);
b9bec74b 3355 }
f1665b21 3356
e56dd3c7
JL		 3357 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
3358 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
0f53994f 3359 if (ret < 0) {
f1665b21 3360 return ret;
0f53994f 3361 }
c0198c5f 3362 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
f1665b21 3363
f1665b21 3364 return 0;
f1665b21
SY		 3365}
3366
1bc22652 3367static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 3368{
1bc22652 3369 CPUX86State *env = &cpu->env;
f1665b21
SY		 3370 int i, ret;
3371 struct kvm_xcrs xcrs;
3372
28143b40 3373 if (!has_xcrs) {
f1665b21 3374 return 0;
b9bec74b 3375 }
f1665b21 3376
1bc22652 3377 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 3378 if (ret < 0) {
f1665b21 3379 return ret;
b9bec74b 3380 }
f1665b21 3381
b9bec74b 3382 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 3383 /* Only support xcr0 now */
0fd53fec
PB		 3384 if (xcrs.xcrs[i].xcr == 0) {
3385 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 3386 break;
3387 }
b9bec74b 3388 }
f1665b21 3389 return 0;
f1665b21
SY		 3390}
3391
1bc22652 3392static int kvm_get_sregs(X86CPU *cpu)
05330448 3393{
1bc22652 3394 CPUX86State *env = &cpu->env;
05330448 3395 struct kvm_sregs sregs;
1520f8bb 3396 int ret;
05330448 3397
1bc22652 3398 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 3399 if (ret < 0) {
05330448 3400 return ret;
b9bec74b 3401 }
05330448 3402
1520f8bb
PB		 3403 /*
3404 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
3405 * always preceded by KVM_GET_VCPU_EVENTS.
3406 */
05330448
AL		 3407
3408 get_seg(&env->segs[R_CS], &sregs.cs);
3409 get_seg(&env->segs[R_DS], &sregs.ds);
3410 get_seg(&env->segs[R_ES], &sregs.es);
3411 get_seg(&env->segs[R_FS], &sregs.fs);
3412 get_seg(&env->segs[R_GS], &sregs.gs);
3413 get_seg(&env->segs[R_SS], &sregs.ss);
3414
3415 get_seg(&env->tr, &sregs.tr);
3416 get_seg(&env->ldt, &sregs.ldt);
3417
3418 env->idt.limit = sregs.idt.limit;
3419 env->idt.base = sregs.idt.base;
3420 env->gdt.limit = sregs.gdt.limit;
3421 env->gdt.base = sregs.gdt.base;
3422
3423 env->cr[0] = sregs.cr0;
3424 env->cr[2] = sregs.cr2;
3425 env->cr[3] = sregs.cr3;
3426 env->cr[4] = sregs.cr4;
3427
05330448 3428 env->efer = sregs.efer;
cce47516
JK		 3429
3430 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 3431 x86_update_hflags(env);
05330448
AL		 3432
3433 return 0;
3434}
3435
8f515d38
ML		 3436static int kvm_get_sregs2(X86CPU *cpu)
3437{
3438 CPUX86State *env = &cpu->env;
3439 struct kvm_sregs2 sregs;
3440 int i, ret;
3441
3442 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
3443 if (ret < 0) {
3444 return ret;
3445 }
3446
3447 get_seg(&env->segs[R_CS], &sregs.cs);
3448 get_seg(&env->segs[R_DS], &sregs.ds);
3449 get_seg(&env->segs[R_ES], &sregs.es);
3450 get_seg(&env->segs[R_FS], &sregs.fs);
3451 get_seg(&env->segs[R_GS], &sregs.gs);
3452 get_seg(&env->segs[R_SS], &sregs.ss);
3453
3454 get_seg(&env->tr, &sregs.tr);
3455 get_seg(&env->ldt, &sregs.ldt);
3456
3457 env->idt.limit = sregs.idt.limit;
3458 env->idt.base = sregs.idt.base;
3459 env->gdt.limit = sregs.gdt.limit;
3460 env->gdt.base = sregs.gdt.base;
3461
3462 env->cr[0] = sregs.cr0;
3463 env->cr[2] = sregs.cr2;
3464 env->cr[3] = sregs.cr3;
3465 env->cr[4] = sregs.cr4;
3466
3467 env->efer = sregs.efer;
3468
3469 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
3470
3471 if (env->pdptrs_valid) {
3472 for (i = 0; i < 4; i++) {
3473 env->pdptrs[i] = sregs.pdptrs[i];
3474 }
3475 }
3476
3477 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3478 x86_update_hflags(env);
3479
3480 return 0;
3481}
3482
1bc22652 3483static int kvm_get_msrs(X86CPU *cpu)
05330448 3484{
1bc22652 3485 CPUX86State *env = &cpu->env;
d71b62a1 3486 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 3487 int ret, i;
fcc35e7c 3488 uint64_t mtrr_top_bits;
05330448 3489
d71b62a1
EH		 3490 kvm_msr_buf_reset(cpu);
3491
9c600a84
EH		 3492 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3493 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3494 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3495 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 3496 if (has_msr_star) {
9c600a84 3497 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 3498 }
c3a3a7d3 3499 if (has_msr_hsave_pa) {
9c600a84 3500 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 3501 }
c9b8f6b6 3502 if (has_msr_tsc_aux) {
9c600a84 3503 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 3504 }
f28558d3 3505 if (has_msr_tsc_adjust) {
9c600a84 3506 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 3507 }
aa82ba54 3508 if (has_msr_tsc_deadline) {
9c600a84 3509 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 3510 }
21e87c46 3511 if (has_msr_misc_enable) {
9c600a84 3512 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 3513 }
fc12d72e 3514 if (has_msr_smbase) {
9c600a84 3515 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 3516 }
e13713db
LA		 3517 if (has_msr_smi_count) {
3518 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3519 }
df67696e 3520 if (has_msr_feature_control) {
9c600a84 3521 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 3522 }
6aa4228b
CQ		 3523 if (has_msr_pkrs) {
3524 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
3525 }
79e9ebeb 3526 if (has_msr_bndcfgs) {
9c600a84 3527 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 3528 }
18cd2c17 3529 if (has_msr_xss) {
9c600a84 3530 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 3531 }
65087997
TX		 3532 if (has_msr_umwait) {
3533 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3534 }
a33a2cfe
PB		 3535 if (has_msr_spec_ctrl) {
3536 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3537 }
cabf9862
ML		 3538 if (has_tsc_scale_msr) {
3539 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
3540 }
3541
2a9758c5
PB		 3542 if (has_msr_tsx_ctrl) {
3543 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3544 }
cfeea0c0
KRW		 3545 if (has_msr_virt_ssbd) {
3546 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3547 }
b8cc45d6 3548 if (!env->tsc_valid) {
9c600a84 3549 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 3550 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 3551 }
3552
05330448 3553#ifdef TARGET_X86_64
25d2e361 3554 if (lm_capable_kernel) {
9c600a84
EH		 3555 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3556 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3557 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3558 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 3559 }
05330448 3560#endif
9c600a84
EH		 3561 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3562 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
db5daafa
VK		 3563 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3564 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3565 }
6615be07
VK		 3566 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3567 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3568 }
55c911a5 3569 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3570 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 3571 }
55c911a5 3572 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3573 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 3574 }
d645e132
MT		 3575 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3576 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3577 }
0b368a10
JD		 3578 if (has_architectural_pmu_version > 0) {
3579 if (has_architectural_pmu_version > 1) {
3580 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3581 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3582 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3583 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3584 }
3585 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3586 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 3587 }
0b368a10 3588 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 3589 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3590 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 3591 }
3592 }
1a03675d 3593
57780495 3594 if (env->mcg_cap) {
9c600a84
EH		 3595 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3596 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 3597 if (has_msr_mcg_ext_ctl) {
3598 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3599 }
b9bec74b 3600 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3601 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 3602 }
57780495 3603 }
57780495 3604
1c90ef26 3605 if (has_msr_hv_hypercall) {
9c600a84
EH		 3606 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3607 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 3608 }
2d384d7c 3609 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3610 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 3611 }
2d384d7c 3612 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 3613 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 3614 }
2d384d7c 3615 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3616 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3617 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3618 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3619 }
f2a53c9e
AS		 3620 if (has_msr_hv_crash) {
3621 int j;
3622
5e953812 3623 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 3624 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 3625 }
3626 }
46eb8f98 3627 if (has_msr_hv_runtime) {
9c600a84 3628 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 3629 }
2d384d7c 3630 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3631 uint32_t msr;
3632
9c600a84 3633 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 3634 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3635 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 3636 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 3637 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 3638 }
3639 }
ff99aa64
AS		 3640 if (has_msr_hv_stimer) {
3641 uint32_t msr;
3642
3643 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3644 msr++) {
9c600a84 3645 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 3646 }
3647 }
1eabfce6 3648 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 3649 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3650 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3651 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3652 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3653 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3654 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3655 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3656 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3657 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3658 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3659 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3660 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 3661 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 3662 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3663 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 3664 }
3665 }
5ef68987 3666
b77146e9
CP		 3667 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3668 int addr_num =
3669 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3670
3671 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3672 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3673 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3674 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3675 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3676 for (i = 0; i < addr_num; i++) {
3677 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3678 }
3679 }
3680
db888065
SC		 3681 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
3682 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
3683 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
3684 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
3685 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
3686 }
3687
cdec2b75
ZG		 3688 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
3689 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
3690 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
3691 }
3692
d71b62a1 3693 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 3694 if (ret < 0) {
05330448 3695 return ret;
b9bec74b 3696 }
05330448 3697
c70b11d1
EH		 3698 if (ret < cpu->kvm_msr_buf->nmsrs) {
3699 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3700 error_report("error: failed to get MSR 0x%" PRIx32,
3701 (uint32_t)e->index);
3702 }
3703
9c600a84 3704 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 3705 /*
3706 * MTRR masks: Each mask consists of 5 parts
3707 * a 10..0: must be zero
3708 * b 11 : valid bit
3709 * c n-1.12: actual mask bits
3710 * d 51..n: reserved must be zero
3711 * e 63.52: reserved must be zero
3712 *
3713 * 'n' is the number of physical bits supported by the CPU and is
3714 * apparently always <= 52. We know our 'n' but don't know what
3715 * the destinations 'n' is; it might be smaller, in which case
3716 * it masks (c) on loading. It might be larger, in which case
3717 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3718 * we're migrating to.
3719 */
3720
3721 if (cpu->fill_mtrr_mask) {
3722 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3723 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3724 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3725 } else {
3726 mtrr_top_bits = 0;
3727 }
3728
05330448 3729 for (i = 0; i < ret; i++) {
0d894367
PB		 3730 uint32_t index = msrs[i].index;
3731 switch (index) {
05330448
AL		 3732 case MSR_IA32_SYSENTER_CS:
3733 env->sysenter_cs = msrs[i].data;
3734 break;
3735 case MSR_IA32_SYSENTER_ESP:
3736 env->sysenter_esp = msrs[i].data;
3737 break;
3738 case MSR_IA32_SYSENTER_EIP:
3739 env->sysenter_eip = msrs[i].data;
3740 break;
0c03266a
JK		 3741 case MSR_PAT:
3742 env->pat = msrs[i].data;
3743 break;
05330448
AL		 3744 case MSR_STAR:
3745 env->star = msrs[i].data;
3746 break;
3747#ifdef TARGET_X86_64
3748 case MSR_CSTAR:
3749 env->cstar = msrs[i].data;
3750 break;
3751 case MSR_KERNELGSBASE:
3752 env->kernelgsbase = msrs[i].data;
3753 break;
3754 case MSR_FMASK:
3755 env->fmask = msrs[i].data;
3756 break;
3757 case MSR_LSTAR:
3758 env->lstar = msrs[i].data;
3759 break;
3760#endif
3761 case MSR_IA32_TSC:
3762 env->tsc = msrs[i].data;
3763 break;
c9b8f6b6
AS		 3764 case MSR_TSC_AUX:
3765 env->tsc_aux = msrs[i].data;
3766 break;
f28558d3
WA		 3767 case MSR_TSC_ADJUST:
3768 env->tsc_adjust = msrs[i].data;
3769 break;
aa82ba54
LJ		 3770 case MSR_IA32_TSCDEADLINE:
3771 env->tsc_deadline = msrs[i].data;
3772 break;
aa851e36
MT		 3773 case MSR_VM_HSAVE_PA:
3774 env->vm_hsave = msrs[i].data;
3775 break;
1a03675d
GC		 3776 case MSR_KVM_SYSTEM_TIME:
3777 env->system_time_msr = msrs[i].data;
3778 break;
3779 case MSR_KVM_WALL_CLOCK:
3780 env->wall_clock_msr = msrs[i].data;
3781 break;
57780495
MT		 3782 case MSR_MCG_STATUS:
3783 env->mcg_status = msrs[i].data;
3784 break;
3785 case MSR_MCG_CTL:
3786 env->mcg_ctl = msrs[i].data;
3787 break;
87f8b626
AR		 3788 case MSR_MCG_EXT_CTL:
3789 env->mcg_ext_ctl = msrs[i].data;
3790 break;
21e87c46
AK		 3791 case MSR_IA32_MISC_ENABLE:
3792 env->msr_ia32_misc_enable = msrs[i].data;
3793 break;
fc12d72e
PB		 3794 case MSR_IA32_SMBASE:
3795 env->smbase = msrs[i].data;
3796 break;
e13713db
LA		 3797 case MSR_SMI_COUNT:
3798 env->msr_smi_count = msrs[i].data;
3799 break;
0779caeb
ACL		 3800 case MSR_IA32_FEATURE_CONTROL:
3801 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3802 break;
79e9ebeb
LJ		 3803 case MSR_IA32_BNDCFGS:
3804 env->msr_bndcfgs = msrs[i].data;
3805 break;
18cd2c17
WL		 3806 case MSR_IA32_XSS:
3807 env->xss = msrs[i].data;
3808 break;
65087997
TX		 3809 case MSR_IA32_UMWAIT_CONTROL:
3810 env->umwait = msrs[i].data;
3811 break;
6aa4228b
CQ		 3812 case MSR_IA32_PKRS:
3813 env->pkrs = msrs[i].data;
3814 break;
57780495 3815 default:
57780495
MT		 3816 if (msrs[i].index >= MSR_MC0_CTL &&
3817 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3818 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3819 }
d8da8574 3820 break;
f6584ee2
GN		 3821 case MSR_KVM_ASYNC_PF_EN:
3822 env->async_pf_en_msr = msrs[i].data;
3823 break;
db5daafa
VK		 3824 case MSR_KVM_ASYNC_PF_INT:
3825 env->async_pf_int_msr = msrs[i].data;
3826 break;
bc9a839d
MT		 3827 case MSR_KVM_PV_EOI_EN:
3828 env->pv_eoi_en_msr = msrs[i].data;
3829 break;
917367aa
MT		 3830 case MSR_KVM_STEAL_TIME:
3831 env->steal_time_msr = msrs[i].data;
3832 break;
d645e132
MT		 3833 case MSR_KVM_POLL_CONTROL: {
3834 env->poll_control_msr = msrs[i].data;
3835 break;
3836 }
0d894367
PB		 3837 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3838 env->msr_fixed_ctr_ctrl = msrs[i].data;
3839 break;
3840 case MSR_CORE_PERF_GLOBAL_CTRL:
3841 env->msr_global_ctrl = msrs[i].data;
3842 break;
3843 case MSR_CORE_PERF_GLOBAL_STATUS:
3844 env->msr_global_status = msrs[i].data;
3845 break;
3846 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3847 env->msr_global_ovf_ctrl = msrs[i].data;
3848 break;
3849 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3850 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3851 break;
3852 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3853 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3854 break;
3855 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3856 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3857 break;
1c90ef26
VR		 3858 case HV_X64_MSR_HYPERCALL:
3859 env->msr_hv_hypercall = msrs[i].data;
3860 break;
3861 case HV_X64_MSR_GUEST_OS_ID:
3862 env->msr_hv_guest_os_id = msrs[i].data;
3863 break;
5ef68987
VR		 3864 case HV_X64_MSR_APIC_ASSIST_PAGE:
3865 env->msr_hv_vapic = msrs[i].data;
3866 break;
48a5f3bc
VR		 3867 case HV_X64_MSR_REFERENCE_TSC:
3868 env->msr_hv_tsc = msrs[i].data;
3869 break;
f2a53c9e
AS		 3870 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3871 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3872 break;
46eb8f98
AS		 3873 case HV_X64_MSR_VP_RUNTIME:
3874 env->msr_hv_runtime = msrs[i].data;
3875 break;
866eea9a
AS		 3876 case HV_X64_MSR_SCONTROL:
3877 env->msr_hv_synic_control = msrs[i].data;
3878 break;
866eea9a
AS		 3879 case HV_X64_MSR_SIEFP:
3880 env->msr_hv_synic_evt_page = msrs[i].data;
3881 break;
3882 case HV_X64_MSR_SIMP:
3883 env->msr_hv_synic_msg_page = msrs[i].data;
3884 break;
3885 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3886 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3887 break;
3888 case HV_X64_MSR_STIMER0_CONFIG:
3889 case HV_X64_MSR_STIMER1_CONFIG:
3890 case HV_X64_MSR_STIMER2_CONFIG:
3891 case HV_X64_MSR_STIMER3_CONFIG:
3892 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3893 msrs[i].data;
3894 break;
3895 case HV_X64_MSR_STIMER0_COUNT:
3896 case HV_X64_MSR_STIMER1_COUNT:
3897 case HV_X64_MSR_STIMER2_COUNT:
3898 case HV_X64_MSR_STIMER3_COUNT:
3899 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3900 msrs[i].data;
866eea9a 3901 break;
ba6a4fd9
VK		 3902 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3903 env->msr_hv_reenlightenment_control = msrs[i].data;
3904 break;
3905 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3906 env->msr_hv_tsc_emulation_control = msrs[i].data;
3907 break;
3908 case HV_X64_MSR_TSC_EMULATION_STATUS:
3909 env->msr_hv_tsc_emulation_status = msrs[i].data;
3910 break;
d1ae67f6
AW		 3911 case MSR_MTRRdefType:
3912 env->mtrr_deftype = msrs[i].data;
3913 break;
3914 case MSR_MTRRfix64K_00000:
3915 env->mtrr_fixed[0] = msrs[i].data;
3916 break;
3917 case MSR_MTRRfix16K_80000:
3918 env->mtrr_fixed[1] = msrs[i].data;
3919 break;
3920 case MSR_MTRRfix16K_A0000:
3921 env->mtrr_fixed[2] = msrs[i].data;
3922 break;
3923 case MSR_MTRRfix4K_C0000:
3924 env->mtrr_fixed[3] = msrs[i].data;
3925 break;
3926 case MSR_MTRRfix4K_C8000:
3927 env->mtrr_fixed[4] = msrs[i].data;
3928 break;
3929 case MSR_MTRRfix4K_D0000:
3930 env->mtrr_fixed[5] = msrs[i].data;
3931 break;
3932 case MSR_MTRRfix4K_D8000:
3933 env->mtrr_fixed[6] = msrs[i].data;
3934 break;
3935 case MSR_MTRRfix4K_E0000:
3936 env->mtrr_fixed[7] = msrs[i].data;
3937 break;
3938 case MSR_MTRRfix4K_E8000:
3939 env->mtrr_fixed[8] = msrs[i].data;
3940 break;
3941 case MSR_MTRRfix4K_F0000:
3942 env->mtrr_fixed[9] = msrs[i].data;
3943 break;
3944 case MSR_MTRRfix4K_F8000:
3945 env->mtrr_fixed[10] = msrs[i].data;
3946 break;
3947 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3948 if (index & 1) {
fcc35e7c
DDAG		 3949 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3950 mtrr_top_bits;
d1ae67f6
AW		 3951 } else {
3952 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3953 }
3954 break;
a33a2cfe
PB		 3955 case MSR_IA32_SPEC_CTRL:
3956 env->spec_ctrl = msrs[i].data;
3957 break;
cabf9862
ML		 3958 case MSR_AMD64_TSC_RATIO:
3959 env->amd_tsc_scale_msr = msrs[i].data;
3960 break;
2a9758c5
PB		 3961 case MSR_IA32_TSX_CTRL:
3962 env->tsx_ctrl = msrs[i].data;
3963 break;
cfeea0c0
KRW		 3964 case MSR_VIRT_SSBD:
3965 env->virt_ssbd = msrs[i].data;
3966 break;
b77146e9
CP		 3967 case MSR_IA32_RTIT_CTL:
3968 env->msr_rtit_ctrl = msrs[i].data;
3969 break;
3970 case MSR_IA32_RTIT_STATUS:
3971 env->msr_rtit_status = msrs[i].data;
3972 break;
3973 case MSR_IA32_RTIT_OUTPUT_BASE:
3974 env->msr_rtit_output_base = msrs[i].data;
3975 break;
3976 case MSR_IA32_RTIT_OUTPUT_MASK:
3977 env->msr_rtit_output_mask = msrs[i].data;
3978 break;
3979 case MSR_IA32_RTIT_CR3_MATCH:
3980 env->msr_rtit_cr3_match = msrs[i].data;
3981 break;
3982 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3983 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3984 break;
db888065
SC		 3985 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
3986 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
3987 msrs[i].data;
3988 break;
cdec2b75
ZG		 3989 case MSR_IA32_XFD:
3990 env->msr_xfd = msrs[i].data;
3991 break;
3992 case MSR_IA32_XFD_ERR:
3993 env->msr_xfd_err = msrs[i].data;
3994 break;
05330448
AL		 3995 }
3996 }
3997
3998 return 0;
3999}
4000
1bc22652 4001static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 4002{
1bc22652 4003 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 4004
1bc22652 4005 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 4006}
4007
23d02d9b 4008static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 4009{
259186a7 4010 CPUState *cs = CPU(cpu);
23d02d9b 4011 CPUX86State *env = &cpu->env;
9bdbe550
HB		 4012 struct kvm_mp_state mp_state;
4013 int ret;
4014
259186a7 4015 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 4016 if (ret < 0) {
4017 return ret;
4018 }
4019 env->mp_state = mp_state.mp_state;
c14750e8 4020 if (kvm_irqchip_in_kernel()) {
259186a7 4021 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 4022 }
9bdbe550
HB		 4023 return 0;
4024}
4025
1bc22652 4026static int kvm_get_apic(X86CPU *cpu)
680c1c6f 4027{
02e51483 4028 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 4029 struct kvm_lapic_state kapic;
4030 int ret;
4031
3d4b2649 4032 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 4033 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 4034 if (ret < 0) {
4035 return ret;
4036 }
4037
4038 kvm_get_apic_state(apic, &kapic);
4039 }
4040 return 0;
4041}
4042
1bc22652 4043static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 4044{
fc12d72e 4045 CPUState *cs = CPU(cpu);
1bc22652 4046 CPUX86State *env = &cpu->env;
076796f8 4047 struct kvm_vcpu_events events = {};
a0fb002c
JK		 4048
4049 if (!kvm_has_vcpu_events()) {
4050 return 0;
4051 }
4052
fd13f23b
LA		 4053 events.flags = 0;
4054
4055 if (has_exception_payload) {
4056 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4057 events.exception.pending = env->exception_pending;
4058 events.exception_has_payload = env->exception_has_payload;
4059 events.exception_payload = env->exception_payload;
4060 }
4061 events.exception.nr = env->exception_nr;
4062 events.exception.injected = env->exception_injected;
a0fb002c
JK		 4063 events.exception.has_error_code = env->has_error_code;
4064 events.exception.error_code = env->error_code;
4065
4066 events.interrupt.injected = (env->interrupt_injected >= 0);
4067 events.interrupt.nr = env->interrupt_injected;
4068 events.interrupt.soft = env->soft_interrupt;
4069
4070 events.nmi.injected = env->nmi_injected;
4071 events.nmi.pending = env->nmi_pending;
4072 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
4073
4074 events.sipi_vector = env->sipi_vector;
4075
fc12d72e
PB		 4076 if (has_msr_smbase) {
4077 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
4078 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
4079 if (kvm_irqchip_in_kernel()) {
4080 /* As soon as these are moved to the kernel, remove them
4081 * from cs->interrupt_request.
4082 */
4083 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
4084 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
4085 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
4086 } else {
4087 /* Keep these in cs->interrupt_request. */
4088 events.smi.pending = 0;
4089 events.smi.latched_init = 0;
4090 }
fc3a1fd7
DDAG		 4091 /* Stop SMI delivery on old machine types to avoid a reboot
4092 * on an inward migration of an old VM.
4093 */
4094 if (!cpu->kvm_no_smi_migration) {
4095 events.flags |= KVM_VCPUEVENT_VALID_SMM;
4096 }
fc12d72e
PB		 4097 }
4098
ea643051 4099 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 4100 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
4101 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
4102 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
4103 }
ea643051 4104 }
aee028b9 4105
1bc22652 4106 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 4107}
4108
1bc22652 4109static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 4110{
1bc22652 4111 CPUX86State *env = &cpu->env;
a0fb002c
JK		 4112 struct kvm_vcpu_events events;
4113 int ret;
4114
4115 if (!kvm_has_vcpu_events()) {
4116 return 0;
4117 }
4118
fc12d72e 4119 memset(&events, 0, sizeof(events));
1bc22652 4120 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 4121 if (ret < 0) {
4122 return ret;
4123 }
fd13f23b
LA		 4124
4125 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4126 env->exception_pending = events.exception.pending;
4127 env->exception_has_payload = events.exception_has_payload;
4128 env->exception_payload = events.exception_payload;
4129 } else {
4130 env->exception_pending = 0;
4131 env->exception_has_payload = false;
4132 }
4133 env->exception_injected = events.exception.injected;
4134 env->exception_nr =
4135 (env->exception_pending || env->exception_injected) ?
4136 events.exception.nr : -1;
a0fb002c
JK		 4137 env->has_error_code = events.exception.has_error_code;
4138 env->error_code = events.exception.error_code;
4139
4140 env->interrupt_injected =
4141 events.interrupt.injected ? events.interrupt.nr : -1;
4142 env->soft_interrupt = events.interrupt.soft;
4143
4144 env->nmi_injected = events.nmi.injected;
4145 env->nmi_pending = events.nmi.pending;
4146 if (events.nmi.masked) {
4147 env->hflags2 |= HF2_NMI_MASK;
4148 } else {
4149 env->hflags2 &= ~HF2_NMI_MASK;
4150 }
4151
fc12d72e
PB		 4152 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
4153 if (events.smi.smm) {
4154 env->hflags |= HF_SMM_MASK;
4155 } else {
4156 env->hflags &= ~HF_SMM_MASK;
4157 }
4158 if (events.smi.pending) {
4159 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
4160 } else {
4161 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
4162 }
4163 if (events.smi.smm_inside_nmi) {
4164 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
4165 } else {
4166 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
4167 }
4168 if (events.smi.latched_init) {
4169 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
4170 } else {
4171 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
4172 }
4173 }
4174
a0fb002c 4175 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 4176
4177 return 0;
4178}
4179
1bc22652 4180static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 4181{
ed2803da 4182 CPUState *cs = CPU(cpu);
1bc22652 4183 CPUX86State *env = &cpu->env;
b0b1d690 4184 int ret = 0;
b0b1d690
JK		 4185 unsigned long reinject_trap = 0;
4186
4187 if (!kvm_has_vcpu_events()) {
fd13f23b 4188 if (env->exception_nr == EXCP01_DB) {
b0b1d690 4189 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 4190 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 4191 reinject_trap = KVM_GUESTDBG_INJECT_BP;
4192 }
fd13f23b 4193 kvm_reset_exception(env);
b0b1d690
JK		 4194 }
4195
4196 /*
4197 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
4198 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
4199 * by updating the debug state once again if single-stepping is on.
4200 * Another reason to call kvm_update_guest_debug here is a pending debug
4201 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
4202 * reinject them via SET_GUEST_DEBUG.
4203 */
4204 if (reinject_trap ||
ed2803da 4205 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 4206 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 4207 }
b0b1d690
JK		 4208 return ret;
4209}
4210
1bc22652 4211static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 4212{
1bc22652 4213 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 4214 struct kvm_debugregs dbgregs;
4215 int i;
4216
4217 if (!kvm_has_debugregs()) {
4218 return 0;
4219 }
4220
1f670a95 4221 memset(&dbgregs, 0, sizeof(dbgregs));
ff44f1a3
JK		 4222 for (i = 0; i < 4; i++) {
4223 dbgregs.db[i] = env->dr[i];
4224 }
4225 dbgregs.dr6 = env->dr[6];
4226 dbgregs.dr7 = env->dr[7];
4227 dbgregs.flags = 0;
4228
1bc22652 4229 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 4230}
4231
1bc22652 4232static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 4233{
1bc22652 4234 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 4235 struct kvm_debugregs dbgregs;
4236 int i, ret;
4237
4238 if (!kvm_has_debugregs()) {
4239 return 0;
4240 }
4241
1bc22652 4242 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 4243 if (ret < 0) {
b9bec74b 4244 return ret;
ff44f1a3
JK		 4245 }
4246 for (i = 0; i < 4; i++) {
4247 env->dr[i] = dbgregs.db[i];
4248 }
4249 env->dr[4] = env->dr[6] = dbgregs.dr6;
4250 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 4251
4252 return 0;
4253}
4254
ebbfef2f
LA		 4255static int kvm_put_nested_state(X86CPU *cpu)
4256{
4257 CPUX86State *env = &cpu->env;
4258 int max_nested_state_len = kvm_max_nested_state_length();
4259
1e44f3ab 4260 if (!env->nested_state) {
ebbfef2f
LA		 4261 return 0;
4262 }
4263
b16c0e20
PB		 4264 /*
4265 * Copy flags that are affected by reset from env->hflags and env->hflags2.
4266 */
4267 if (env->hflags & HF_GUEST_MASK) {
4268 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
4269 } else {
4270 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
4271 }
0baa4b44
VK		 4272
4273 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
4274 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
b16c0e20
PB		 4275 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
4276 } else {
4277 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
4278 }
4279
ebbfef2f
LA		 4280 assert(env->nested_state->size <= max_nested_state_len);
4281 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
4282}
4283
4284static int kvm_get_nested_state(X86CPU *cpu)
4285{
4286 CPUX86State *env = &cpu->env;
4287 int max_nested_state_len = kvm_max_nested_state_length();
4288 int ret;
4289
1e44f3ab 4290 if (!env->nested_state) {
ebbfef2f
LA		 4291 return 0;
4292 }
4293
4294 /*
4295 * It is possible that migration restored a smaller size into
4296 * nested_state->hdr.size than what our kernel support.
4297 * We preserve migration origin nested_state->hdr.size for
4298 * call to KVM_SET_NESTED_STATE but wish that our next call
4299 * to KVM_GET_NESTED_STATE will use max size our kernel support.
4300 */
4301 env->nested_state->size = max_nested_state_len;
4302
4303 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
4304 if (ret < 0) {
4305 return ret;
4306 }
4307
b16c0e20
PB		 4308 /*
4309 * Copy flags that are affected by reset to env->hflags and env->hflags2.
4310 */
ebbfef2f
LA		 4311 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
4312 env->hflags |= HF_GUEST_MASK;
4313 } else {
4314 env->hflags &= ~HF_GUEST_MASK;
4315 }
0baa4b44
VK		 4316
4317 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
4318 if (cpu_has_svm(env)) {
4319 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
4320 env->hflags2 |= HF2_GIF_MASK;
4321 } else {
4322 env->hflags2 &= ~HF2_GIF_MASK;
4323 }
b16c0e20 4324 }
ebbfef2f
LA		 4325
4326 return ret;
4327}
4328
20d695a9 4329int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 4330{
20d695a9 4331 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 4332 int ret;
4333
2fa45344 4334 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 4335
b16c0e20 4336 /* must be before kvm_put_nested_state so that EFER.SVME is set */
8f515d38 4337 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
b16c0e20
PB		 4338 if (ret < 0) {
4339 return ret;
4340 }
4341
48e1a45c 4342 if (level >= KVM_PUT_RESET_STATE) {
bec7156a
JK		 4343 ret = kvm_put_nested_state(x86_cpu);
4344 if (ret < 0) {
4345 return ret;
4346 }
4347
6bdf863d
JK		 4348 ret = kvm_put_msr_feature_control(x86_cpu);
4349 if (ret < 0) {
4350 return ret;
4351 }
4352 }
4353
36f96c4b
HZ		 4354 if (level == KVM_PUT_FULL_STATE) {
4355 /* We don't check for kvm_arch_set_tsc_khz() errors here,
4356 * because TSC frequency mismatch shouldn't abort migration,
4357 * unless the user explicitly asked for a more strict TSC
4358 * setting (e.g. using an explicit "tsc-freq" option).
4359 */
4360 kvm_arch_set_tsc_khz(cpu);
4361 }
4362
1bc22652 4363 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 4364 if (ret < 0) {
05330448 4365 return ret;
b9bec74b 4366 }
1bc22652 4367 ret = kvm_put_xsave(x86_cpu);
b9bec74b 4368 if (ret < 0) {
f1665b21 4369 return ret;
b9bec74b 4370 }
1bc22652 4371 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 4372 if (ret < 0) {
05330448 4373 return ret;
b9bec74b 4374 }
ab443475 4375 /* must be before kvm_put_msrs */
1bc22652 4376 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 4377 if (ret < 0) {
4378 return ret;
4379 }
1bc22652 4380 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 4381 if (ret < 0) {
05330448 4382 return ret;
b9bec74b 4383 }
4fadfa00
PH		 4384 ret = kvm_put_vcpu_events(x86_cpu, level);
4385 if (ret < 0) {
4386 return ret;
4387 }
ea643051 4388 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 4389 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 4390 if (ret < 0) {
680c1c6f
JK		 4391 return ret;
4392 }
ea643051 4393 }
7477cd38
MT		 4394
4395 ret = kvm_put_tscdeadline_msr(x86_cpu);
4396 if (ret < 0) {
4397 return ret;
4398 }
1bc22652 4399 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 4400 if (ret < 0) {
b0b1d690 4401 return ret;
b9bec74b 4402 }
b0b1d690 4403 /* must be last */
1bc22652 4404 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 4405 if (ret < 0) {
ff44f1a3 4406 return ret;
b9bec74b 4407 }
05330448
AL		 4408 return 0;
4409}
4410
20d695a9 4411int kvm_arch_get_registers(CPUState *cs)
05330448 4412{
20d695a9 4413 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 4414 int ret;
4415
20d695a9 4416 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 4417
4fadfa00 4418 ret = kvm_get_vcpu_events(cpu);
b9bec74b 4419 if (ret < 0) {
f4f1110e 4420 goto out;
b9bec74b 4421 }
4fadfa00
PH		 4422 /*
4423 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4424 * KVM_GET_REGS and KVM_GET_SREGS.
4425 */
4426 ret = kvm_get_mp_state(cpu);
b9bec74b 4427 if (ret < 0) {
f4f1110e 4428 goto out;
b9bec74b 4429 }
4fadfa00 4430 ret = kvm_getput_regs(cpu, 0);
b9bec74b 4431 if (ret < 0) {
f4f1110e 4432 goto out;
b9bec74b 4433 }
4fadfa00 4434 ret = kvm_get_xsave(cpu);
b9bec74b 4435 if (ret < 0) {
f4f1110e 4436 goto out;
b9bec74b 4437 }
4fadfa00 4438 ret = kvm_get_xcrs(cpu);
b9bec74b 4439 if (ret < 0) {
f4f1110e 4440 goto out;
b9bec74b 4441 }
8f515d38 4442 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
b9bec74b 4443 if (ret < 0) {
f4f1110e 4444 goto out;
b9bec74b 4445 }
4fadfa00 4446 ret = kvm_get_msrs(cpu);
680c1c6f 4447 if (ret < 0) {
f4f1110e 4448 goto out;
680c1c6f 4449 }
4fadfa00 4450 ret = kvm_get_apic(cpu);
b9bec74b 4451 if (ret < 0) {
f4f1110e 4452 goto out;
b9bec74b 4453 }
1bc22652 4454 ret = kvm_get_debugregs(cpu);
b9bec74b 4455 if (ret < 0) {
f4f1110e 4456 goto out;
b9bec74b 4457 }
ebbfef2f
LA		 4458 ret = kvm_get_nested_state(cpu);
4459 if (ret < 0) {
4460 goto out;
4461 }
f4f1110e
RH		 4462 ret = 0;
4463 out:
4464 cpu_sync_bndcs_hflags(&cpu->env);
4465 return ret;
05330448
AL		 4466}
4467
20d695a9 4468void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 4469{
20d695a9
AF		 4470 X86CPU *x86_cpu = X86_CPU(cpu);
4471 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 4472 int ret;
4473
276ce815 4474 /* Inject NMI */
fc12d72e
PB		 4475 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4476 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4477 qemu_mutex_lock_iothread();
4478 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4479 qemu_mutex_unlock_iothread();
4480 DPRINTF("injected NMI\n");
4481 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4482 if (ret < 0) {
4483 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4484 strerror(-ret));
4485 }
4486 }
4487 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4488 qemu_mutex_lock_iothread();
4489 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4490 qemu_mutex_unlock_iothread();
4491 DPRINTF("injected SMI\n");
4492 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4493 if (ret < 0) {
4494 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4495 strerror(-ret));
4496 }
ce377af3 4497 }
276ce815
LJ		 4498 }
4499
15eafc2e 4500 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 4501 qemu_mutex_lock_iothread();
4502 }
4503
e0723c45
PB		 4504 /* Force the VCPU out of its inner loop to process any INIT requests
4505 * or (for userspace APIC, but it is cheap to combine the checks here)
4506 * pending TPR access reports.
4507 */
4508 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 4509 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4510 !(env->hflags & HF_SMM_MASK)) {
4511 cpu->exit_request = 1;
4512 }
4513 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4514 cpu->exit_request = 1;
4515 }
e0723c45 4516 }
05330448 4517
15eafc2e 4518 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 4519 /* Try to inject an interrupt if the guest can accept it */
4520 if (run->ready_for_interrupt_injection &&
259186a7 4521 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 4522 (env->eflags & IF_MASK)) {
4523 int irq;
4524
259186a7 4525 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 4526 irq = cpu_get_pic_interrupt(env);
4527 if (irq >= 0) {
4528 struct kvm_interrupt intr;
4529
4530 intr.irq = irq;
db1669bc 4531 DPRINTF("injected interrupt %d\n", irq);
1bc22652 4532 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 4533 if (ret < 0) {
4534 fprintf(stderr,
4535 "KVM: injection failed, interrupt lost (%s)\n",
4536 strerror(-ret));
4537 }
db1669bc
JK		 4538 }
4539 }
05330448 4540
db1669bc
JK		 4541 /* If we have an interrupt but the guest is not ready to receive an
4542 * interrupt, request an interrupt window exit. This will
4543 * cause a return to userspace as soon as the guest is ready to
4544 * receive interrupts. */
259186a7 4545 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 4546 run->request_interrupt_window = 1;
4547 } else {
4548 run->request_interrupt_window = 0;
4549 }
4550
4551 DPRINTF("setting tpr\n");
02e51483 4552 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 4553
4554 qemu_mutex_unlock_iothread();
db1669bc 4555 }
05330448
AL		 4556}
4557
035d1ef2
CQ		 4558static void kvm_rate_limit_on_bus_lock(void)
4559{
4560 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
4561
4562 if (delay_ns) {
4563 g_usleep(delay_ns / SCALE_US);
4564 }
4565}
4566
4c663752 4567MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 4568{
20d695a9
AF		 4569 X86CPU *x86_cpu = X86_CPU(cpu);
4570 CPUX86State *env = &x86_cpu->env;
4571
fc12d72e
PB		 4572 if (run->flags & KVM_RUN_X86_SMM) {
4573 env->hflags |= HF_SMM_MASK;
4574 } else {
f5c052b9 4575 env->hflags &= ~HF_SMM_MASK;
fc12d72e 4576 }
b9bec74b 4577 if (run->if_flag) {
05330448 4578 env->eflags |= IF_MASK;
b9bec74b 4579 } else {
05330448 4580 env->eflags &= ~IF_MASK;
b9bec74b 4581 }
035d1ef2
CQ		 4582 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
4583 kvm_rate_limit_on_bus_lock();
4584 }
4b8523ee
JK		 4585
4586 /* We need to protect the apic state against concurrent accesses from
4587 * different threads in case the userspace irqchip is used. */
4588 if (!kvm_irqchip_in_kernel()) {
4589 qemu_mutex_lock_iothread();
4590 }
02e51483
CF		 4591 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4592 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 4593 if (!kvm_irqchip_in_kernel()) {
4594 qemu_mutex_unlock_iothread();
4595 }
f794aa4a 4596 return cpu_get_mem_attrs(env);
05330448
AL		 4597}
4598
20d695a9 4599int kvm_arch_process_async_events(CPUState *cs)
0af691d7 4600{
20d695a9
AF		 4601 X86CPU *cpu = X86_CPU(cs);
4602 CPUX86State *env = &cpu->env;
232fc23b 4603
259186a7 4604 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 4605 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4606 assert(env->mcg_cap);
4607
259186a7 4608 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 4609
dd1750d7 4610 kvm_cpu_synchronize_state(cs);
ab443475 4611
fd13f23b 4612 if (env->exception_nr == EXCP08_DBLE) {
ab443475 4613 /* this means triple fault */
cf83f140 4614 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 4615 cs->exit_request = 1;
ab443475
JK		 4616 return 0;
4617 }
fd13f23b 4618 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 4619 env->has_error_code = 0;
4620
259186a7 4621 cs->halted = 0;
ab443475
JK		 4622 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4623 env->mp_state = KVM_MP_STATE_RUNNABLE;
4624 }
4625 }
4626
fc12d72e
PB		 4627 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4628 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 4629 kvm_cpu_synchronize_state(cs);
4630 do_cpu_init(cpu);
4631 }
4632
db1669bc
JK		 4633 if (kvm_irqchip_in_kernel()) {
4634 return 0;
4635 }
4636
259186a7
AF		 4637 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4638 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 4639 apic_poll_irq(cpu->apic_state);
5d62c43a 4640 }
259186a7 4641 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 4642 (env->eflags & IF_MASK)) ||
259186a7
AF		 4643 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4644 cs->halted = 0;
6792a57b 4645 }
259186a7 4646 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 4647 kvm_cpu_synchronize_state(cs);
232fc23b 4648 do_cpu_sipi(cpu);
0af691d7 4649 }
259186a7
AF		 4650 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4651 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 4652 kvm_cpu_synchronize_state(cs);
02e51483 4653 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 4654 env->tpr_access_type);
4655 }
0af691d7 4656
259186a7 4657 return cs->halted;
0af691d7
MT		 4658}
4659
839b5630 4660static int kvm_handle_halt(X86CPU *cpu)
05330448 4661{
259186a7 4662 CPUState *cs = CPU(cpu);
839b5630
AF		 4663 CPUX86State *env = &cpu->env;
4664
259186a7 4665 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 4666 (env->eflags & IF_MASK)) &&
259186a7
AF		 4667 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4668 cs->halted = 1;
bb4ea393 4669 return EXCP_HLT;
05330448
AL		 4670 }
4671
bb4ea393 4672 return 0;
05330448
AL		 4673}
4674
f7575c96 4675static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 4676{
f7575c96
AF		 4677 CPUState *cs = CPU(cpu);
4678 struct kvm_run *run = cs->kvm_run;
d362e757 4679
02e51483 4680 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 4681 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4682 : TPR_ACCESS_READ);
4683 return 1;
4684}
4685
f17ec444 4686int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 4687{
38972938 4688 static const uint8_t int3 = 0xcc;
64bf3f4e 4689
f17ec444
AF		 4690 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4691 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 4692 return -EINVAL;
b9bec74b 4693 }
e22a25c9
AL		 4694 return 0;
4695}
4696
f17ec444 4697int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 4698{
4699 uint8_t int3;
4700
c6986f16
PB		 4701 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
4702 return -EINVAL;
4703 }
4704 if (int3 != 0xcc) {
4705 return 0;
4706 }
4707 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 4708 return -EINVAL;
b9bec74b 4709 }
e22a25c9
AL		 4710 return 0;
4711}
4712
4713static struct {
4714 target_ulong addr;
4715 int len;
4716 int type;
4717} hw_breakpoint[4];
4718
4719static int nb_hw_breakpoint;
4720
4721static int find_hw_breakpoint(target_ulong addr, int len, int type)
4722{
4723 int n;
4724
b9bec74b 4725 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 4726 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 4727 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 4728 return n;
b9bec74b
JK		 4729 }
4730 }
e22a25c9
AL		 4731 return -1;
4732}
4733
4734int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4735 target_ulong len, int type)
4736{
4737 switch (type) {
4738 case GDB_BREAKPOINT_HW:
4739 len = 1;
4740 break;
4741 case GDB_WATCHPOINT_WRITE:
4742 case GDB_WATCHPOINT_ACCESS:
4743 switch (len) {
4744 case 1:
4745 break;
4746 case 2:
4747 case 4:
4748 case 8:
b9bec74b 4749 if (addr & (len - 1)) {
e22a25c9 4750 return -EINVAL;
b9bec74b 4751 }
e22a25c9
AL		 4752 break;
4753 default:
4754 return -EINVAL;
4755 }
4756 break;
4757 default:
4758 return -ENOSYS;
4759 }
4760
b9bec74b 4761 if (nb_hw_breakpoint == 4) {
e22a25c9 4762 return -ENOBUFS;
b9bec74b
JK		 4763 }
4764 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 4765 return -EEXIST;
b9bec74b 4766 }
e22a25c9
AL		 4767 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4768 hw_breakpoint[nb_hw_breakpoint].len = len;
4769 hw_breakpoint[nb_hw_breakpoint].type = type;
4770 nb_hw_breakpoint++;
4771
4772 return 0;
4773}
4774
4775int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4776 target_ulong len, int type)
4777{
4778 int n;
4779
4780 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 4781 if (n < 0) {
e22a25c9 4782 return -ENOENT;
b9bec74b 4783 }
e22a25c9
AL		 4784 nb_hw_breakpoint--;
4785 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4786
4787 return 0;
4788}
4789
4790void kvm_arch_remove_all_hw_breakpoints(void)
4791{
4792 nb_hw_breakpoint = 0;
4793}
4794
4795static CPUWatchpoint hw_watchpoint;
4796
a60f24b5 4797static int kvm_handle_debug(X86CPU *cpu,
48405526 4798 struct kvm_debug_exit_arch *arch_info)
e22a25c9 4799{
ed2803da 4800 CPUState *cs = CPU(cpu);
a60f24b5 4801 CPUX86State *env = &cpu->env;
f2574737 4802 int ret = 0;
e22a25c9
AL		 4803 int n;
4804
37936ac7
LA		 4805 if (arch_info->exception == EXCP01_DB) {
4806 if (arch_info->dr6 & DR6_BS) {
ed2803da 4807 if (cs->singlestep_enabled) {
f2574737 4808 ret = EXCP_DEBUG;
b9bec74b 4809 }
e22a25c9 4810 } else {
b9bec74b
JK		 4811 for (n = 0; n < 4; n++) {
4812 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 4813 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4814 case 0x0:
f2574737 4815 ret = EXCP_DEBUG;
e22a25c9
AL		 4816 break;
4817 case 0x1:
f2574737 4818 ret = EXCP_DEBUG;
ff4700b0 4819 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4820 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4821 hw_watchpoint.flags = BP_MEM_WRITE;
4822 break;
4823 case 0x3:
f2574737 4824 ret = EXCP_DEBUG;
ff4700b0 4825 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4826 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4827 hw_watchpoint.flags = BP_MEM_ACCESS;
4828 break;
4829 }
b9bec74b
JK		 4830 }
4831 }
e22a25c9 4832 }
ff4700b0 4833 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 4834 ret = EXCP_DEBUG;
b9bec74b 4835 }
f2574737 4836 if (ret == 0) {
ff4700b0 4837 cpu_synchronize_state(cs);
fd13f23b 4838 assert(env->exception_nr == -1);
b0b1d690 4839
f2574737 4840 /* pass to guest */
fd13f23b
LA		 4841 kvm_queue_exception(env, arch_info->exception,
4842 arch_info->exception == EXCP01_DB,
4843 arch_info->dr6);
48405526 4844 env->has_error_code = 0;
b0b1d690 4845 }
e22a25c9 4846
f2574737 4847 return ret;
e22a25c9
AL		 4848}
4849
20d695a9 4850void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 4851{
4852 const uint8_t type_code[] = {
4853 [GDB_BREAKPOINT_HW] = 0x0,
4854 [GDB_WATCHPOINT_WRITE] = 0x1,
4855 [GDB_WATCHPOINT_ACCESS] = 0x3
4856 };
4857 const uint8_t len_code[] = {
4858 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4859 };
4860 int n;
4861
a60f24b5 4862 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 4863 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 4864 }
e22a25c9
AL		 4865 if (nb_hw_breakpoint > 0) {
4866 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4867 dbg->arch.debugreg[7] = 0x0600;
4868 for (n = 0; n < nb_hw_breakpoint; n++) {
4869 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4870 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4871 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 4872 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 4873 }
4874 }
4875}
4513d923 4876
c22f5467
SC		 4877static bool has_sgx_provisioning;
4878
4879static bool __kvm_enable_sgx_provisioning(KVMState *s)
4880{
4881 int fd, ret;
4882
4883 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
4884 return false;
4885 }
4886
4887 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
4888 if (fd < 0) {
4889 return false;
4890 }
4891
4892 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
4893 if (ret) {
4894 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
4895 exit(1);
4896 }
4897 close(fd);
4898 return true;
4899}
4900
4901bool kvm_enable_sgx_provisioning(KVMState *s)
4902{
4903 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
4904}
4905
2a4dac83
JK		 4906static bool host_supports_vmx(void)
4907{
4908 uint32_t ecx, unused;
4909
4910 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4911 return ecx & CPUID_EXT_VMX;
4912}
4913
4914#define VMX_INVALID_GUEST_STATE 0x80000021
4915
20d695a9 4916int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 4917{
20d695a9 4918 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 4919 uint64_t code;
4920 int ret;
4921
4922 switch (run->exit_reason) {
4923 case KVM_EXIT_HLT:
4924 DPRINTF("handle_hlt\n");
4b8523ee 4925 qemu_mutex_lock_iothread();
839b5630 4926 ret = kvm_handle_halt(cpu);
4b8523ee 4927 qemu_mutex_unlock_iothread();
2a4dac83
JK		 4928 break;
4929 case KVM_EXIT_SET_TPR:
4930 ret = 0;
4931 break;
d362e757 4932 case KVM_EXIT_TPR_ACCESS:
4b8523ee 4933 qemu_mutex_lock_iothread();
f7575c96 4934 ret = kvm_handle_tpr_access(cpu);
4b8523ee 4935 qemu_mutex_unlock_iothread();
d362e757 4936 break;
2a4dac83
JK		 4937 case KVM_EXIT_FAIL_ENTRY:
4938 code = run->fail_entry.hardware_entry_failure_reason;
4939 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4940 code);
4941 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4942 fprintf(stderr,
12619721 4943 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 4944 "unrestricted mode\n"
4945 "support, the failure can be most likely due to the guest "
4946 "entering an invalid\n"
4947 "state for Intel VT. For example, the guest maybe running "
4948 "in big real mode\n"
4949 "which is not supported on less recent Intel processors."
4950 "\n\n");
4951 }
4952 ret = -1;
4953 break;
4954 case KVM_EXIT_EXCEPTION:
4955 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4956 run->ex.exception, run->ex.error_code);
4957 ret = -1;
4958 break;
f2574737
JK		 4959 case KVM_EXIT_DEBUG:
4960 DPRINTF("kvm_exit_debug\n");
4b8523ee 4961 qemu_mutex_lock_iothread();
a60f24b5 4962 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 4963 qemu_mutex_unlock_iothread();
f2574737 4964 break;
50efe82c
AS		 4965 case KVM_EXIT_HYPERV:
4966 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4967 break;
15eafc2e
PB		 4968 case KVM_EXIT_IOAPIC_EOI:
4969 ioapic_eoi_broadcast(run->eoi.vector);
4970 ret = 0;
4971 break;
035d1ef2
CQ		 4972 case KVM_EXIT_X86_BUS_LOCK:
4973 /* already handled in kvm_arch_post_run */
4974 ret = 0;
4975 break;
2a4dac83
JK		 4976 default:
4977 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4978 ret = -1;
4979 break;
4980 }
4981
4982 return ret;
4983}
4984
20d695a9 4985bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4986{
20d695a9
AF		 4987 X86CPU *cpu = X86_CPU(cs);
4988 CPUX86State *env = &cpu->env;
4989
dd1750d7 4990 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4991 return !(env->cr[0] & CR0_PE_MASK) ||
4992 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4993}
84b058d7
JK		 4994
4995void kvm_arch_init_irq_routing(KVMState *s)
4996{
cc7e0ddf 4997 /* We know at this point that we're using the in-kernel
614e41bc 4998 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4999 * we can use msi via irqfd and GSI routing.
cc7e0ddf 5000 */
614e41bc 5001 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 5002 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 5003
5004 if (kvm_irqchip_is_split()) {
def4c557 5005 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
15eafc2e
PB		 5006 int i;
5007
5008 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
5009 MSI routes for signaling interrupts to the local apics. */
5010 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
def4c557 5011 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
15eafc2e
PB		 5012 error_report("Could not enable split IRQ mode.");
5013 exit(1);
5014 }
5015 }
def4c557 5016 kvm_irqchip_commit_route_changes(&c);
15eafc2e
PB		 5017 }
5018}
5019
4376c40d 5020int kvm_arch_irqchip_create(KVMState *s)
15eafc2e
PB		 5021{
5022 int ret;
4376c40d 5023 if (kvm_kernel_irqchip_split()) {
15eafc2e
PB		 5024 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
5025 if (ret) {
df3c286c 5026 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 5027 strerror(-ret));
5028 exit(1);
5029 } else {
5030 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
5031 kvm_split_irqchip = true;
5032 return 1;
5033 }
5034 } else {
5035 return 0;
5036 }
84b058d7 5037}
b139bd30 5038
c1bb5418
DW		 5039uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
5040{
5041 CPUX86State *env;
5042 uint64_t ext_id;
5043
5044 if (!first_cpu) {
5045 return address;
5046 }
5047 env = &X86_CPU(first_cpu)->env;
5048 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
5049 return address;
5050 }
5051
5052 /*
5053 * If the remappable format bit is set, or the upper bits are
5054 * already set in address_hi, or the low extended bits aren't
5055 * there anyway, do nothing.
5056 */
5057 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
5058 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
5059 return address;
5060 }
5061
5062 address &= ~ext_id;
5063 address |= ext_id << 35;
5064 return address;
5065}
5066
9e03a040 5067int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 5068 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 5069{
8b5ed7df
PX		 5070 X86IOMMUState *iommu = x86_iommu_get_default();
5071
5072 if (iommu) {
30c60f77 5073 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
8b5ed7df 5074
c1bb5418
DW		 5075 if (class->int_remap) {
5076 int ret;
5077 MSIMessage src, dst;
0ea1472d 5078
c1bb5418
DW		 5079 src.address = route->u.msi.address_hi;
5080 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
5081 src.address |= route->u.msi.address_lo;
5082 src.data = route->u.msi.data;
8b5ed7df 5083
c1bb5418
DW		 5084 ret = class->int_remap(iommu, &src, &dst, dev ? \
5085 pci_requester_id(dev) : \
5086 X86_IOMMU_SID_INVALID);
5087 if (ret) {
5088 trace_kvm_x86_fixup_msi_error(route->gsi);
5089 return 1;
5090 }
5091
5092 /*
5093 * Handled untranslated compatibilty format interrupt with
5094 * extended destination ID in the low bits 11-5. */
5095 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
8b5ed7df 5096
c1bb5418
DW		 5097 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
5098 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
5099 route->u.msi.data = dst.data;
5100 return 0;
5101 }
8b5ed7df
PX		 5102 }
5103
c1bb5418
DW		 5104 address = kvm_swizzle_msi_ext_dest_id(address);
5105 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
5106 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
9e03a040
FB		 5107 return 0;
5108}
1850b6b7 5109
38d87493
PX		 5110typedef struct MSIRouteEntry MSIRouteEntry;
5111
5112struct MSIRouteEntry {
5113 PCIDevice *dev; /* Device pointer */
5114 int vector; /* MSI/MSIX vector index */
5115 int virq; /* Virtual IRQ index */
5116 QLIST_ENTRY(MSIRouteEntry) list;
5117};
5118
5119/* List of used GSI routes */
5120static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
5121 QLIST_HEAD_INITIALIZER(msi_route_list);
5122
e1d4fb2d
PX		 5123static void kvm_update_msi_routes_all(void *private, bool global,
5124 uint32_t index, uint32_t mask)
5125{
a56de056 5126 int cnt = 0, vector;
e1d4fb2d
PX		 5127 MSIRouteEntry *entry;
5128 MSIMessage msg;
fd563564
PX		 5129 PCIDevice *dev;
5130
e1d4fb2d
PX		 5131 /* TODO: explicit route update */
5132 QLIST_FOREACH(entry, &msi_route_list, list) {
5133 cnt++;
a56de056 5134 vector = entry->vector;
fd563564 5135 dev = entry->dev;
a56de056
PX		 5136 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
5137 msg = msix_get_message(dev, vector);
5138 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
5139 msg = msi_get_message(dev, vector);
5140 } else {
5141 /*
5142 * Either MSI/MSIX is disabled for the device, or the
5143 * specific message was masked out. Skip this one.
5144 */
fd563564
PX		 5145 continue;
5146 }
fd563564 5147 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 5148 }
3f1fea0f 5149 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 5150 trace_kvm_x86_update_msi_routes(cnt);
5151}
5152
38d87493
PX		 5153int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
5154 int vector, PCIDevice *dev)
5155{
e1d4fb2d 5156 static bool notify_list_inited = false;
38d87493
PX		 5157 MSIRouteEntry *entry;
5158
5159 if (!dev) {
5160 /* These are (possibly) IOAPIC routes only used for split
5161 * kernel irqchip mode, while what we are housekeeping are
5162 * PCI devices only. */
5163 return 0;
5164 }
5165
5166 entry = g_new0(MSIRouteEntry, 1);
5167 entry->dev = dev;
5168 entry->vector = vector;
5169 entry->virq = route->gsi;
5170 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
5171
5172 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 5173
5174 if (!notify_list_inited) {
5175 /* For the first time we do add route, add ourselves into
5176 * IOMMU's IEC notify list if needed. */
5177 X86IOMMUState *iommu = x86_iommu_get_default();
5178 if (iommu) {
5179 x86_iommu_iec_register_notifier(iommu,
5180 kvm_update_msi_routes_all,
5181 NULL);
5182 }
5183 notify_list_inited = true;
5184 }
38d87493
PX		 5185 return 0;
5186}
5187
5188int kvm_arch_release_virq_post(int virq)
5189{
5190 MSIRouteEntry *entry, *next;
5191 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
5192 if (entry->virq == virq) {
5193 trace_kvm_x86_remove_msi_route(virq);
5194 QLIST_REMOVE(entry, list);
01960e6d 5195 g_free(entry);
38d87493
PX		 5196 break;
5197 }
5198 }
9e03a040
FB		 5199 return 0;
5200}
1850b6b7
EA		 5201
5202int kvm_arch_msi_data_to_gsi(uint32_t data)
5203{
5204 abort();
5205}
e1e43813
PB		 5206
5207bool kvm_has_waitpkg(void)
5208{
5209 return has_msr_umwait;
5210}
92a5199b
TL		 5211
5212bool kvm_arch_cpu_check_are_resettable(void)
5213{
5214 return !sev_es_enabled();
5215}
19db68ca
YZ		 5216
5217#define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
5218
5219void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
5220{
5221 KVMState *s = kvm_state;
5222 uint64_t supported;
5223
5224 mask &= XSTATE_DYNAMIC_MASK;
5225 if (!mask) {
5226 return;
5227 }
5228 /*
5229 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
5230 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
5231 * about them already because they are not supported features.
5232 */
5233 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
5234 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
5235 mask &= supported;
5236
5237 while (mask) {
5238 int bit = ctz64(mask);
5239 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
5240 if (rc) {
5241 /*
5242 * Older kernel version (<5.17) do not support
5243 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
5244 * any dynamic feature from kvm_arch_get_supported_cpuid.
5245 */
5246 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
5247 "for feature bit %d", bit);
5248 }
5249 mask &= ~BIT_ULL(bit);
5250 }
5251}
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