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i386: prefer system KVM_GET_SUPPORTED_HV_CPUID ioctl over vCPU's one
[mirror_qemu.git] / target / i386 / kvm / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
8efc4e51 16#include "qapi/qapi-events-run-state.h"
da34e65c 17#include "qapi/error.h"
05330448 18#include <sys/ioctl.h>
25d2e361 19#include <sys/utsname.h>
05330448
AL		 20
21#include <linux/kvm.h>
1814eab6 22#include "standard-headers/asm-x86/kvm_para.h"
05330448 23
33c11879 24#include "cpu.h"
f5cc5a5c 25#include "host-cpu.h"
9c17d615 26#include "sysemu/sysemu.h"
b3946626 27#include "sysemu/hw_accel.h"
6410848b 28#include "sysemu/kvm_int.h"
54d31236 29#include "sysemu/runstate.h"
1d31f66b 30#include "kvm_i386.h"
92a5199b 31#include "sev_i386.h"
50efe82c 32#include "hyperv.h"
5e953812 33#include "hyperv-proto.h"
50efe82c 34
022c62cb 35#include "exec/gdbstub.h"
1de7afc9 36#include "qemu/host-utils.h"
db725815 37#include "qemu/main-loop.h"
1de7afc9 38#include "qemu/config-file.h"
1c4a55db 39#include "qemu/error-report.h"
89a289c7 40#include "hw/i386/x86.h"
0d09e41a 41#include "hw/i386/apic.h"
e0723c45
PB		 42#include "hw/i386/apic_internal.h"
43#include "hw/i386/apic-msidef.h"
8b5ed7df 44#include "hw/i386/intel_iommu.h"
e1d4fb2d 45#include "hw/i386/x86-iommu.h"
d6d059ca 46#include "hw/i386/e820_memory_layout.h"
ec78e2cd 47#include "sysemu/sev.h"
50efe82c 48
a2cb15b0 49#include "hw/pci/pci.h"
15eafc2e 50#include "hw/pci/msi.h"
fd563564 51#include "hw/pci/msix.h"
795c40b8 52#include "migration/blocker.h"
4c663752 53#include "exec/memattrs.h"
8b5ed7df 54#include "trace.h"
05330448
AL		 55
56//#define DEBUG_KVM
57
58#ifdef DEBUG_KVM
8c0d577e 59#define DPRINTF(fmt, ...) \
05330448
AL		 60 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
61#else
8c0d577e 62#define DPRINTF(fmt, ...) \
05330448
AL		 63 do { } while (0)
64#endif
65
73b994f6
LA		 66/* From arch/x86/kvm/lapic.h */
67#define KVM_APIC_BUS_CYCLE_NS 1
68#define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
69
1a03675d
GC		 70#define MSR_KVM_WALL_CLOCK 0x11
71#define MSR_KVM_SYSTEM_TIME 0x12
72
d1138251
EH		 73/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
74 * 255 kvm_msr_entry structs */
75#define MSR_BUF_SIZE 4096
d71b62a1 76
420ae1fc
PB		 77static void kvm_init_msrs(X86CPU *cpu);
78
94a8d39a
JK		 79const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
80 KVM_CAP_INFO(SET_TSS_ADDR),
81 KVM_CAP_INFO(EXT_CPUID),
82 KVM_CAP_INFO(MP_STATE),
83 KVM_CAP_LAST_INFO
84};
25d2e361 85
c3a3a7d3
JK		 86static bool has_msr_star;
87static bool has_msr_hsave_pa;
c9b8f6b6 88static bool has_msr_tsc_aux;
f28558d3 89static bool has_msr_tsc_adjust;
aa82ba54 90static bool has_msr_tsc_deadline;
df67696e 91static bool has_msr_feature_control;
21e87c46 92static bool has_msr_misc_enable;
fc12d72e 93static bool has_msr_smbase;
79e9ebeb 94static bool has_msr_bndcfgs;
25d2e361 95static int lm_capable_kernel;
7bc3d711 96static bool has_msr_hv_hypercall;
f2a53c9e 97static bool has_msr_hv_crash;
744b8a94 98static bool has_msr_hv_reset;
8c145d7c 99static bool has_msr_hv_vpindex;
e9688fab 100static bool hv_vpindex_settable;
46eb8f98 101static bool has_msr_hv_runtime;
866eea9a 102static bool has_msr_hv_synic;
ff99aa64 103static bool has_msr_hv_stimer;
d72bc7f6 104static bool has_msr_hv_frequencies;
ba6a4fd9 105static bool has_msr_hv_reenlightenment;
18cd2c17 106static bool has_msr_xss;
65087997 107static bool has_msr_umwait;
a33a2cfe 108static bool has_msr_spec_ctrl;
2a9758c5 109static bool has_msr_tsx_ctrl;
cfeea0c0 110static bool has_msr_virt_ssbd;
e13713db 111static bool has_msr_smi_count;
aec5e9c3 112static bool has_msr_arch_capabs;
597360c0 113static bool has_msr_core_capabs;
20a78b02 114static bool has_msr_vmx_vmfunc;
67025148 115static bool has_msr_ucode_rev;
4a910e1f 116static bool has_msr_vmx_procbased_ctls2;
ea39f9b6 117static bool has_msr_perf_capabs;
6aa4228b 118static bool has_msr_pkrs;
b827df58 119
0b368a10
JD		 120static uint32_t has_architectural_pmu_version;
121static uint32_t num_architectural_pmu_gp_counters;
122static uint32_t num_architectural_pmu_fixed_counters;
0d894367 123
28143b40
TH		 124static int has_xsave;
125static int has_xcrs;
126static int has_pit_state2;
fd13f23b 127static int has_exception_payload;
28143b40 128
87f8b626
AR		 129static bool has_msr_mcg_ext_ctl;
130
494e95e9 131static struct kvm_cpuid2 *cpuid_cache;
a8439be6 132static struct kvm_cpuid2 *hv_cpuid_cache;
f57bceb6 133static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 134
28143b40
TH		 135int kvm_has_pit_state2(void)
136{
137 return has_pit_state2;
138}
139
355023f2
PB		 140bool kvm_has_smm(void)
141{
23edf8b5 142 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
355023f2
PB		 143}
144
6053a86f
MT		 145bool kvm_has_adjust_clock_stable(void)
146{
147 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
148
149 return (ret == KVM_CLOCK_TSC_STABLE);
150}
151
8700a984
VK		 152bool kvm_has_adjust_clock(void)
153{
154 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
155}
156
79a197ab
LA		 157bool kvm_has_exception_payload(void)
158{
159 return has_exception_payload;
160}
161
fb506e70
RK		 162static bool kvm_x2apic_api_set_flags(uint64_t flags)
163{
4f7f5893 164 KVMState *s = KVM_STATE(current_accel());
fb506e70
RK		 165
166 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
167}
168
e391c009 169#define MEMORIZE(fn, _result) \
2a138ec3 170 ({ \
2a138ec3
RK		 171 static bool _memorized; \
172 \
173 if (_memorized) { \
174 return _result; \
175 } \
176 _memorized = true; \
177 _result = fn; \
178 })
179
e391c009
IM		 180static bool has_x2apic_api;
181
182bool kvm_has_x2apic_api(void)
183{
184 return has_x2apic_api;
185}
186
fb506e70
RK		 187bool kvm_enable_x2apic(void)
188{
2a138ec3
RK		 189 return MEMORIZE(
190 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 191 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
192 has_x2apic_api);
fb506e70
RK		 193}
194
e9688fab
RK		 195bool kvm_hv_vpindex_settable(void)
196{
197 return hv_vpindex_settable;
198}
199
0fd7e098
LL		 200static int kvm_get_tsc(CPUState *cs)
201{
202 X86CPU *cpu = X86_CPU(cs);
203 CPUX86State *env = &cpu->env;
204 struct {
205 struct kvm_msrs info;
206 struct kvm_msr_entry entries[1];
a1834d97 207 } msr_data = {};
0fd7e098
LL		 208 int ret;
209
210 if (env->tsc_valid) {
211 return 0;
212 }
213
1f670a95 214 memset(&msr_data, 0, sizeof(msr_data));
0fd7e098
LL		 215 msr_data.info.nmsrs = 1;
216 msr_data.entries[0].index = MSR_IA32_TSC;
217 env->tsc_valid = !runstate_is_running();
218
219 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
220 if (ret < 0) {
221 return ret;
222 }
223
48e1a45c 224 assert(ret == 1);
0fd7e098
LL		 225 env->tsc = msr_data.entries[0].data;
226 return 0;
227}
228
14e6fe12 229static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 230{
0fd7e098
LL		 231 kvm_get_tsc(cpu);
232}
233
234void kvm_synchronize_all_tsc(void)
235{
236 CPUState *cpu;
237
238 if (kvm_enabled()) {
239 CPU_FOREACH(cpu) {
14e6fe12 240 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 241 }
242 }
243}
244
b827df58
AK		 245static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
246{
247 struct kvm_cpuid2 *cpuid;
248 int r, size;
249
250 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 251 cpuid = g_malloc0(size);
b827df58
AK		 252 cpuid->nent = max;
253 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 254 if (r == 0 && cpuid->nent >= max) {
255 r = -E2BIG;
256 }
b827df58
AK		 257 if (r < 0) {
258 if (r == -E2BIG) {
7267c094 259 g_free(cpuid);
b827df58
AK		 260 return NULL;
261 } else {
262 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
263 strerror(-r));
264 exit(1);
265 }
266 }
267 return cpuid;
268}
269
dd87f8a6
EH		 270/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
271 * for all entries.
272 */
273static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
274{
275 struct kvm_cpuid2 *cpuid;
276 int max = 1;
494e95e9
CP		 277
278 if (cpuid_cache != NULL) {
279 return cpuid_cache;
280 }
dd87f8a6
EH		 281 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
282 max *= 2;
283 }
494e95e9 284 cpuid_cache = cpuid;
dd87f8a6
EH		 285 return cpuid;
286}
287
b199c682 288static bool host_tsx_broken(void)
40e80ee4
EH		 289{
290 int family, model, stepping;\
291 char vendor[CPUID_VENDOR_SZ + 1];
292
f5cc5a5c 293 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
40e80ee4
EH		 294
295 /* Check if we are running on a Haswell host known to have broken TSX */
296 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
297 (family == 6) &&
298 ((model == 63 && stepping < 4) ||
299 model == 60 || model == 69 || model == 70);
300}
0c31b744 301
829ae2f9
EH		 302/* Returns the value for a specific register on the cpuid entry
303 */
304static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
305{
306 uint32_t ret = 0;
307 switch (reg) {
308 case R_EAX:
309 ret = entry->eax;
310 break;
311 case R_EBX:
312 ret = entry->ebx;
313 break;
314 case R_ECX:
315 ret = entry->ecx;
316 break;
317 case R_EDX:
318 ret = entry->edx;
319 break;
320 }
321 return ret;
322}
323
4fb73f1d
EH		 324/* Find matching entry for function/index on kvm_cpuid2 struct
325 */
326static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
327 uint32_t function,
328 uint32_t index)
329{
330 int i;
331 for (i = 0; i < cpuid->nent; ++i) {
332 if (cpuid->entries[i].function == function &&
333 cpuid->entries[i].index == index) {
334 return &cpuid->entries[i];
335 }
336 }
337 /* not found: */
338 return NULL;
339}
340
ba9bc59e 341uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 342 uint32_t index, int reg)
b827df58
AK		 343{
344 struct kvm_cpuid2 *cpuid;
b827df58
AK		 345 uint32_t ret = 0;
346 uint32_t cpuid_1_edx;
347
dd87f8a6 348 cpuid = get_supported_cpuid(s);
b827df58 349
4fb73f1d
EH		 350 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
351 if (entry) {
4fb73f1d 352 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 353 }
354
7b46e5ce
EH		 355 /* Fixups for the data returned by KVM, below */
356
c2acb022
EH		 357 if (function == 1 && reg == R_EDX) {
358 /* KVM before 2.6.30 misreports the following features */
359 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 360 } else if (function == 1 && reg == R_ECX) {
361 /* We can set the hypervisor flag, even if KVM does not return it on
362 * GET_SUPPORTED_CPUID
363 */
364 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 365 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
366 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
367 * and the irqchip is in the kernel.
368 */
369 if (kvm_irqchip_in_kernel() &&
370 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
371 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
372 }
41e5e76d
EH		 373
374 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
375 * without the in-kernel irqchip
376 */
377 if (!kvm_irqchip_in_kernel()) {
378 ret &= ~CPUID_EXT_X2APIC;
b827df58 379 }
2266d443
MT		 380
381 if (enable_cpu_pm) {
382 int disable_exits = kvm_check_extension(s,
383 KVM_CAP_X86_DISABLE_EXITS);
384
385 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
386 ret |= CPUID_EXT_MONITOR;
387 }
388 }
28b8e4d0
JK		 389 } else if (function == 6 && reg == R_EAX) {
390 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4 391 } else if (function == 7 && index == 0 && reg == R_EBX) {
b199c682 392 if (host_tsx_broken()) {
40e80ee4
EH		 393 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
394 }
485b1d25
EH		 395 } else if (function == 7 && index == 0 && reg == R_EDX) {
396 /*
397 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
398 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
399 * returned by KVM_GET_MSR_INDEX_LIST.
400 */
401 if (!has_msr_arch_capabs) {
402 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
403 }
f98bbd83
BM		 404 } else if (function == 0x80000001 && reg == R_ECX) {
405 /*
406 * It's safe to enable TOPOEXT even if it's not returned by
407 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
408 * us to keep CPU models including TOPOEXT runnable on older kernels.
409 */
410 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 411 } else if (function == 0x80000001 && reg == R_EDX) {
412 /* On Intel, kvm returns cpuid according to the Intel spec,
413 * so add missing bits according to the AMD spec:
414 */
415 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
416 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 417 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
418 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
419 * be enabled without the in-kernel irqchip
420 */
421 if (!kvm_irqchip_in_kernel()) {
422 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
423 }
c1bb5418
DW		 424 if (kvm_irqchip_is_split()) {
425 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
426 }
be777326 427 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 428 ret |= 1U << KVM_HINTS_REALTIME;
b9bec74b 429 }
0c31b744
GC		 430
431 return ret;
bb0300dc 432}
bb0300dc 433
ede146c2 434uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
f57bceb6
RH		 435{
436 struct {
437 struct kvm_msrs info;
438 struct kvm_msr_entry entries[1];
a1834d97 439 } msr_data = {};
20a78b02
PB		 440 uint64_t value;
441 uint32_t ret, can_be_one, must_be_one;
f57bceb6
RH		 442
443 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
444 return 0;
445 }
446
447 /* Check if requested MSR is supported feature MSR */
448 int i;
449 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
450 if (kvm_feature_msrs->indices[i] == index) {
451 break;
452 }
453 if (i == kvm_feature_msrs->nmsrs) {
454 return 0; /* if the feature MSR is not supported, simply return 0 */
455 }
456
457 msr_data.info.nmsrs = 1;
458 msr_data.entries[0].index = index;
459
460 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
461 if (ret != 1) {
462 error_report("KVM get MSR (index=0x%x) feature failed, %s",
463 index, strerror(-ret));
464 exit(1);
465 }
466
20a78b02
PB		 467 value = msr_data.entries[0].data;
468 switch (index) {
469 case MSR_IA32_VMX_PROCBASED_CTLS2:
4a910e1f
VK		 470 if (!has_msr_vmx_procbased_ctls2) {
471 /* KVM forgot to add these bits for some time, do this ourselves. */
472 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
473 CPUID_XSAVE_XSAVES) {
474 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
475 }
476 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
477 CPUID_EXT_RDRAND) {
478 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
479 }
480 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
481 CPUID_7_0_EBX_INVPCID) {
482 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
483 }
484 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
485 CPUID_7_0_EBX_RDSEED) {
486 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
487 }
488 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
489 CPUID_EXT2_RDTSCP) {
490 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
491 }
048c9516
PB		 492 }
493 /* fall through */
20a78b02
PB		 494 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
495 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
496 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
497 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
498 /*
499 * Return true for bits that can be one, but do not have to be one.
500 * The SDM tells us which bits could have a "must be one" setting,
501 * so we can do the opposite transformation in make_vmx_msr_value.
502 */
503 must_be_one = (uint32_t)value;
504 can_be_one = (uint32_t)(value >> 32);
505 return can_be_one & ~must_be_one;
506
507 default:
508 return value;
509 }
f57bceb6
RH		 510}
511
e7701825
MT		 512static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
513 int *max_banks)
514{
515 int r;
516
14a09518 517 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 518 if (r > 0) {
519 *max_banks = r;
520 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
521 }
522 return -ENOSYS;
523}
524
bee615d4 525static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 526{
87f8b626 527 CPUState *cs = CPU(cpu);
bee615d4 528 CPUX86State *env = &cpu->env;
c34d440a
JK		 529 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
530 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
531 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 532 int flags = 0;
e7701825 533
c34d440a
JK		 534 if (code == BUS_MCEERR_AR) {
535 status |= MCI_STATUS_AR | 0x134;
536 mcg_status |= MCG_STATUS_EIPV;
537 } else {
538 status |= 0xc0;
539 mcg_status |= MCG_STATUS_RIPV;
419fb20a 540 }
87f8b626
AR		 541
542 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
543 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
544 * guest kernel back into env->mcg_ext_ctl.
545 */
546 cpu_synchronize_state(cs);
547 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
548 mcg_status |= MCG_STATUS_LMCE;
549 flags = 0;
550 }
551
8c5cf3b6 552 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 553 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 554}
419fb20a 555
8efc4e51
ZP		 556static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
557{
558 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
559
560 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
561 &mff);
562}
563
73284563 564static void hardware_memory_error(void *host_addr)
419fb20a 565{
8efc4e51 566 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
73284563 567 error_report("QEMU got Hardware memory error at addr %p", host_addr);
419fb20a
JK		 568 exit(1);
569}
570
2ae41db2 571void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 572{
20d695a9
AF		 573 X86CPU *cpu = X86_CPU(c);
574 CPUX86State *env = &cpu->env;
419fb20a 575 ram_addr_t ram_addr;
a8170e5e 576 hwaddr paddr;
419fb20a 577
4d39892c
PB		 578 /* If we get an action required MCE, it has been injected by KVM
579 * while the VM was running. An action optional MCE instead should
580 * be coming from the main thread, which qemu_init_sigbus identifies
581 * as the "early kill" thread.
582 */
a16fc07e 583 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 584
20e0ff59 585 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 586 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 587 if (ram_addr != RAM_ADDR_INVALID &&
588 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
589 kvm_hwpoison_page_add(ram_addr);
590 kvm_mce_inject(cpu, paddr, code);
73284563
MS		 591
592 /*
593 * Use different logging severity based on error type.
594 * If there is additional MCE reporting on the hypervisor, QEMU VA
595 * could be another source to identify the PA and MCE details.
596 */
597 if (code == BUS_MCEERR_AR) {
598 error_report("Guest MCE Memory Error at QEMU addr %p and "
599 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
600 addr, paddr, "BUS_MCEERR_AR");
601 } else {
602 warn_report("Guest MCE Memory Error at QEMU addr %p and "
603 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
604 addr, paddr, "BUS_MCEERR_AO");
605 }
606
2ae41db2 607 return;
419fb20a 608 }
20e0ff59 609
73284563
MS		 610 if (code == BUS_MCEERR_AO) {
611 warn_report("Hardware memory error at addr %p of type %s "
612 "for memory used by QEMU itself instead of guest system!",
613 addr, "BUS_MCEERR_AO");
614 }
419fb20a 615 }
20e0ff59
PB		 616
617 if (code == BUS_MCEERR_AR) {
73284563 618 hardware_memory_error(addr);
20e0ff59
PB		 619 }
620
8efc4e51
ZP		 621 /* Hope we are lucky for AO MCE, just notify a event */
622 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
419fb20a
JK		 623}
624
fd13f23b
LA		 625static void kvm_reset_exception(CPUX86State *env)
626{
627 env->exception_nr = -1;
628 env->exception_pending = 0;
629 env->exception_injected = 0;
630 env->exception_has_payload = false;
631 env->exception_payload = 0;
632}
633
634static void kvm_queue_exception(CPUX86State *env,
635 int32_t exception_nr,
636 uint8_t exception_has_payload,
637 uint64_t exception_payload)
638{
639 assert(env->exception_nr == -1);
640 assert(!env->exception_pending);
641 assert(!env->exception_injected);
642 assert(!env->exception_has_payload);
643
644 env->exception_nr = exception_nr;
645
646 if (has_exception_payload) {
647 env->exception_pending = 1;
648
649 env->exception_has_payload = exception_has_payload;
650 env->exception_payload = exception_payload;
651 } else {
652 env->exception_injected = 1;
653
654 if (exception_nr == EXCP01_DB) {
655 assert(exception_has_payload);
656 env->dr[6] = exception_payload;
657 } else if (exception_nr == EXCP0E_PAGE) {
658 assert(exception_has_payload);
659 env->cr[2] = exception_payload;
660 } else {
661 assert(!exception_has_payload);
662 }
663 }
664}
665
1bc22652 666static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 667{
1bc22652
AF		 668 CPUX86State *env = &cpu->env;
669
fd13f23b 670 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 671 unsigned int bank, bank_num = env->mcg_cap & 0xff;
672 struct kvm_x86_mce mce;
673
fd13f23b 674 kvm_reset_exception(env);
ab443475
JK		 675
676 /*
677 * There must be at least one bank in use if an MCE is pending.
678 * Find it and use its values for the event injection.
679 */
680 for (bank = 0; bank < bank_num; bank++) {
681 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
682 break;
683 }
684 }
685 assert(bank < bank_num);
686
687 mce.bank = bank;
688 mce.status = env->mce_banks[bank * 4 + 1];
689 mce.mcg_status = env->mcg_status;
690 mce.addr = env->mce_banks[bank * 4 + 2];
691 mce.misc = env->mce_banks[bank * 4 + 3];
692
1bc22652 693 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 694 }
ab443475
JK		 695 return 0;
696}
697
538f0497 698static void cpu_update_state(void *opaque, bool running, RunState state)
b8cc45d6 699{
317ac620 700 CPUX86State *env = opaque;
b8cc45d6
GC		 701
702 if (running) {
703 env->tsc_valid = false;
704 }
705}
706
83b17af5 707unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 708{
83b17af5 709 X86CPU *cpu = X86_CPU(cs);
7e72a45c 710 return cpu->apic_id;
b164e48e
EH		 711}
712
92067bf4
IM		 713#ifndef KVM_CPUID_SIGNATURE_NEXT
714#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
715#endif
716
92067bf4
IM		 717static bool hyperv_enabled(X86CPU *cpu)
718{
7bc3d711
PB		 719 CPUState *cs = CPU(cpu);
720 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
f701c082 721 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
e48ddcc6 722 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 723}
724
74aaddc6
MT		 725/*
726 * Check whether target_freq is within conservative
727 * ntp correctable bounds (250ppm) of freq
728 */
729static inline bool freq_within_bounds(int freq, int target_freq)
730{
731 int max_freq = freq + (freq * 250 / 1000000);
732 int min_freq = freq - (freq * 250 / 1000000);
733
734 if (target_freq >= min_freq && target_freq <= max_freq) {
735 return true;
736 }
737
738 return false;
739}
740
5031283d
HZ		 741static int kvm_arch_set_tsc_khz(CPUState *cs)
742{
743 X86CPU *cpu = X86_CPU(cs);
744 CPUX86State *env = &cpu->env;
74aaddc6
MT		 745 int r, cur_freq;
746 bool set_ioctl = false;
5031283d
HZ		 747
748 if (!env->tsc_khz) {
749 return 0;
750 }
751
74aaddc6
MT		 752 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
753 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
754
755 /*
756 * If TSC scaling is supported, attempt to set TSC frequency.
757 */
758 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
759 set_ioctl = true;
760 }
761
762 /*
763 * If desired TSC frequency is within bounds of NTP correction,
764 * attempt to set TSC frequency.
765 */
766 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
767 set_ioctl = true;
768 }
769
770 r = set_ioctl ?
5031283d
HZ		 771 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
772 -ENOTSUP;
74aaddc6 773
5031283d
HZ		 774 if (r < 0) {
775 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
776 * TSC frequency doesn't match the one we want.
777 */
74aaddc6
MT		 778 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
779 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
780 -ENOTSUP;
5031283d 781 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 782 warn_report("TSC frequency mismatch between "
783 "VM (%" PRId64 " kHz) and host (%d kHz), "
784 "and TSC scaling unavailable",
785 env->tsc_khz, cur_freq);
5031283d
HZ		 786 return r;
787 }
788 }
789
790 return 0;
791}
792
4bb95b82
LP		 793static bool tsc_is_stable_and_known(CPUX86State *env)
794{
795 if (!env->tsc_khz) {
796 return false;
797 }
798 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
799 || env->user_tsc_khz;
800}
801
6760bd20
VK		 802static struct {
803 const char *desc;
804 struct {
061817a7
VK		 805 uint32_t func;
806 int reg;
6760bd20
VK		 807 uint32_t bits;
808 } flags[2];
c6861930 809 uint64_t dependencies;
6760bd20
VK		 810} kvm_hyperv_properties[] = {
811 [HYPERV_FEAT_RELAXED] = {
812 .desc = "relaxed timing (hv-relaxed)",
813 .flags = {
061817a7 814 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 815 .bits = HV_HYPERCALL_AVAILABLE},
061817a7 816 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 817 .bits = HV_RELAXED_TIMING_RECOMMENDED}
818 }
819 },
820 [HYPERV_FEAT_VAPIC] = {
821 .desc = "virtual APIC (hv-vapic)",
822 .flags = {
061817a7 823 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 824 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
061817a7 825 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 826 .bits = HV_APIC_ACCESS_RECOMMENDED}
827 }
828 },
829 [HYPERV_FEAT_TIME] = {
830 .desc = "clocksources (hv-time)",
831 .flags = {
061817a7 832 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 833 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
834 HV_REFERENCE_TSC_AVAILABLE}
835 }
836 },
837 [HYPERV_FEAT_CRASH] = {
838 .desc = "crash MSRs (hv-crash)",
839 .flags = {
061817a7 840 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 841 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
842 }
843 },
844 [HYPERV_FEAT_RESET] = {
845 .desc = "reset MSR (hv-reset)",
846 .flags = {
061817a7 847 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 848 .bits = HV_RESET_AVAILABLE}
849 }
850 },
851 [HYPERV_FEAT_VPINDEX] = {
852 .desc = "VP_INDEX MSR (hv-vpindex)",
853 .flags = {
061817a7 854 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 855 .bits = HV_VP_INDEX_AVAILABLE}
856 }
857 },
858 [HYPERV_FEAT_RUNTIME] = {
859 .desc = "VP_RUNTIME MSR (hv-runtime)",
860 .flags = {
061817a7 861 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 862 .bits = HV_VP_RUNTIME_AVAILABLE}
863 }
864 },
865 [HYPERV_FEAT_SYNIC] = {
866 .desc = "synthetic interrupt controller (hv-synic)",
867 .flags = {
061817a7 868 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 869 .bits = HV_SYNIC_AVAILABLE}
870 }
871 },
872 [HYPERV_FEAT_STIMER] = {
873 .desc = "synthetic timers (hv-stimer)",
874 .flags = {
061817a7 875 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 876 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 877 },
878 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 879 },
880 [HYPERV_FEAT_FREQUENCIES] = {
881 .desc = "frequency MSRs (hv-frequencies)",
882 .flags = {
061817a7 883 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 884 .bits = HV_ACCESS_FREQUENCY_MSRS},
061817a7 885 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 886 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
887 }
888 },
889 [HYPERV_FEAT_REENLIGHTENMENT] = {
890 .desc = "reenlightenment MSRs (hv-reenlightenment)",
891 .flags = {
061817a7 892 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 893 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
894 }
895 },
896 [HYPERV_FEAT_TLBFLUSH] = {
897 .desc = "paravirtualized TLB flush (hv-tlbflush)",
898 .flags = {
061817a7 899 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 900 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
901 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 902 },
903 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 904 },
905 [HYPERV_FEAT_EVMCS] = {
906 .desc = "enlightened VMCS (hv-evmcs)",
907 .flags = {
061817a7 908 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20 909 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 910 },
911 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 912 },
913 [HYPERV_FEAT_IPI] = {
914 .desc = "paravirtualized IPI (hv-ipi)",
915 .flags = {
061817a7 916 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 917 .bits = HV_CLUSTER_IPI_RECOMMENDED |
918 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 919 },
920 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 921 },
128531d9
VK		 922 [HYPERV_FEAT_STIMER_DIRECT] = {
923 .desc = "direct mode synthetic timers (hv-stimer-direct)",
924 .flags = {
061817a7 925 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
128531d9
VK		 926 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
927 },
928 .dependencies = BIT(HYPERV_FEAT_STIMER)
929 },
6760bd20
VK		 930};
931
2e905438
VK		 932static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
933 bool do_sys_ioctl)
6760bd20
VK		 934{
935 struct kvm_cpuid2 *cpuid;
936 int r, size;
937
938 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
939 cpuid = g_malloc0(size);
940 cpuid->nent = max;
941
2e905438
VK		 942 if (do_sys_ioctl) {
943 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
944 } else {
945 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
946 }
6760bd20
VK		 947 if (r == 0 && cpuid->nent >= max) {
948 r = -E2BIG;
949 }
950 if (r < 0) {
951 if (r == -E2BIG) {
952 g_free(cpuid);
953 return NULL;
954 } else {
955 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
956 strerror(-r));
957 exit(1);
958 }
959 }
960 return cpuid;
961}
962
963/*
964 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
965 * for all entries.
966 */
967static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
968{
969 struct kvm_cpuid2 *cpuid;
05c900ce
VK		 970 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000080 leaves */
971 int max = 10;
decb4f20 972 int i;
2e905438
VK		 973 bool do_sys_ioctl;
974
975 do_sys_ioctl =
976 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
6760bd20
VK		 977
978 /*
979 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
980 * -E2BIG, however, it doesn't report back the right size. Keep increasing
981 * it and re-trying until we succeed.
982 */
2e905438 983 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
6760bd20
VK		 984 max++;
985 }
decb4f20
VK		 986
987 /*
988 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
989 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
990 * information early, just check for the capability and set the bit
991 * manually.
992 */
2e905438 993 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
decb4f20
VK		 994 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
995 for (i = 0; i < cpuid->nent; i++) {
996 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
997 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
998 }
999 }
1000 }
1001
6760bd20
VK		 1002 return cpuid;
1003}
1004
1005/*
1006 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1007 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1008 */
1009static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 1010{
1011 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 1012 struct kvm_cpuid2 *cpuid;
1013 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1014
1015 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1016 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1017 cpuid->nent = 2;
1018
1019 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1020 entry_feat = &cpuid->entries[0];
1021 entry_feat->function = HV_CPUID_FEATURES;
1022
1023 entry_recomm = &cpuid->entries[1];
1024 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1025 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1026
1027 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1028 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1029 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1030 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1031 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1032 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1033 }
c35bd19a 1034
6760bd20
VK		 1035 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1036 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1037 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 1038 }
6760bd20
VK		 1039
1040 if (has_msr_hv_frequencies) {
1041 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1042 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 1043 }
6760bd20
VK		 1044
1045 if (has_msr_hv_crash) {
1046 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 1047 }
6760bd20
VK		 1048
1049 if (has_msr_hv_reenlightenment) {
1050 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 1051 }
6760bd20
VK		 1052
1053 if (has_msr_hv_reset) {
1054 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 1055 }
6760bd20
VK		 1056
1057 if (has_msr_hv_vpindex) {
1058 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 1059 }
6760bd20
VK		 1060
1061 if (has_msr_hv_runtime) {
1062 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 1063 }
6760bd20
VK		 1064
1065 if (has_msr_hv_synic) {
1066 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1067 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1068
1069 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1070 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 1071 }
c35bd19a 1072 }
6760bd20
VK		 1073
1074 if (has_msr_hv_stimer) {
1075 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 1076 }
9b4cf107 1077
6760bd20
VK		 1078 if (kvm_check_extension(cs->kvm_state,
1079 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1080 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1081 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1082 }
c35bd19a 1083
6760bd20
VK		 1084 if (kvm_check_extension(cs->kvm_state,
1085 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1086 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 1087 }
6760bd20
VK		 1088
1089 if (kvm_check_extension(cs->kvm_state,
1090 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1091 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1092 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 1093 }
6760bd20
VK		 1094
1095 return cpuid;
1096}
1097
a8439be6 1098static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
e1a66a1e
VK		 1099{
1100 struct kvm_cpuid_entry2 *entry;
a8439be6
VK		 1101 struct kvm_cpuid2 *cpuid;
1102
1103 if (hv_cpuid_cache) {
1104 cpuid = hv_cpuid_cache;
1105 } else {
1106 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1107 cpuid = get_supported_hv_cpuid(cs);
1108 } else {
1109 cpuid = get_supported_hv_cpuid_legacy(cs);
1110 }
1111 hv_cpuid_cache = cpuid;
1112 }
1113
1114 if (!cpuid) {
1115 return 0;
1116 }
e1a66a1e
VK		 1117
1118 entry = cpuid_find_entry(cpuid, func, 0);
1119 if (!entry) {
1120 return 0;
1121 }
1122
1123 return cpuid_entry_get_reg(entry, reg);
1124}
1125
a8439be6 1126static bool hyperv_feature_supported(CPUState *cs, int feature)
7682f857 1127{
061817a7
VK		 1128 uint32_t func, bits;
1129 int i, reg;
7682f857
VK		 1130
1131 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
061817a7
VK		 1132
1133 func = kvm_hyperv_properties[feature].flags[i].func;
1134 reg = kvm_hyperv_properties[feature].flags[i].reg;
7682f857
VK		 1135 bits = kvm_hyperv_properties[feature].flags[i].bits;
1136
061817a7 1137 if (!func) {
7682f857
VK		 1138 continue;
1139 }
1140
a8439be6 1141 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
7682f857
VK		 1142 return false;
1143 }
1144 }
1145
1146 return true;
1147}
1148
f4a62495 1149static int hv_cpuid_check_and_set(CPUState *cs, int feature, Error **errp)
6760bd20
VK		 1150{
1151 X86CPU *cpu = X86_CPU(cs);
c6861930 1152 uint64_t deps;
7682f857 1153 int dep_feat;
6760bd20 1154
e48ddcc6 1155 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1156 return 0;
1157 }
1158
c6861930 1159 deps = kvm_hyperv_properties[feature].dependencies;
9dc83cd9
HR		 1160 while (deps) {
1161 dep_feat = ctz64(deps);
c6861930 1162 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
f4a62495
VK		 1163 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1164 kvm_hyperv_properties[feature].desc,
1165 kvm_hyperv_properties[dep_feat].desc);
1166 return 1;
c6861930 1167 }
9dc83cd9 1168 deps &= ~(1ull << dep_feat);
c6861930
VK		 1169 }
1170
a8439be6 1171 if (!hyperv_feature_supported(cs, feature)) {
7682f857 1172 if (hyperv_feat_enabled(cpu, feature)) {
f4a62495
VK		 1173 error_setg(errp, "Hyper-V %s is not supported by kernel",
1174 kvm_hyperv_properties[feature].desc);
7682f857
VK		 1175 return 1;
1176 } else {
1177 return 0;
6760bd20 1178 }
a2b107db 1179 }
6760bd20 1180
e48ddcc6
VK		 1181 if (cpu->hyperv_passthrough) {
1182 cpu->hyperv_features |= BIT(feature);
1183 }
1184
6760bd20
VK		 1185 return 0;
1186}
1187
061817a7 1188static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
c830015e
VK		 1189{
1190 X86CPU *cpu = X86_CPU(cs);
1191 uint32_t r = 0;
1192 int i, j;
1193
1194 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1195 if (!hyperv_feat_enabled(cpu, i)) {
1196 continue;
1197 }
1198
1199 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
061817a7
VK		 1200 if (kvm_hyperv_properties[i].flags[j].func != func) {
1201 continue;
1202 }
1203 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
c830015e
VK		 1204 continue;
1205 }
1206
1207 r |= kvm_hyperv_properties[i].flags[j].bits;
1208 }
1209 }
1210
1211 return r;
1212}
1213
2344d22e 1214/*
f6e01ab5
VK		 1215 * Expand Hyper-V CPU features. In partucular, check that all the requested
1216 * features are supported by the host and the sanity of the configuration
1217 * (that all the required dependencies are included). Also, this takes care
1218 * of 'hv_passthrough' mode and fills the environment with all supported
1219 * Hyper-V features.
2344d22e 1220 */
f4a62495 1221static void hyperv_expand_features(CPUState *cs, Error **errp)
6760bd20
VK		 1222{
1223 X86CPU *cpu = X86_CPU(cs);
6760bd20 1224
2344d22e 1225 if (!hyperv_enabled(cpu))
f4a62495 1226 return;
2344d22e 1227
e48ddcc6 1228 if (cpu->hyperv_passthrough) {
e1a66a1e 1229 cpu->hyperv_vendor_id[0] =
a8439be6 1230 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
e1a66a1e 1231 cpu->hyperv_vendor_id[1] =
a8439be6 1232 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
e1a66a1e 1233 cpu->hyperv_vendor_id[2] =
a8439be6 1234 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
e1a66a1e
VK		 1235 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1236 sizeof(cpu->hyperv_vendor_id) + 1);
1237 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1238 sizeof(cpu->hyperv_vendor_id));
1239 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1240
1241 cpu->hyperv_interface_id[0] =
a8439be6 1242 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
e1a66a1e 1243 cpu->hyperv_interface_id[1] =
a8439be6 1244 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
e1a66a1e 1245 cpu->hyperv_interface_id[2] =
a8439be6 1246 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
e1a66a1e 1247 cpu->hyperv_interface_id[3] =
a8439be6 1248 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
e1a66a1e
VK		 1249
1250 cpu->hyperv_version_id[0] =
a8439be6 1251 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
e1a66a1e 1252 cpu->hyperv_version_id[1] =
a8439be6 1253 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX);
e1a66a1e 1254 cpu->hyperv_version_id[2] =
a8439be6 1255 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
e1a66a1e 1256 cpu->hyperv_version_id[3] =
a8439be6 1257 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX);
e1a66a1e 1258
a8439be6 1259 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
e1a66a1e
VK		 1260 R_EAX);
1261 cpu->hyperv_limits[0] =
a8439be6 1262 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
e1a66a1e 1263 cpu->hyperv_limits[1] =
a8439be6 1264 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
e1a66a1e 1265 cpu->hyperv_limits[2] =
a8439be6 1266 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
e1a66a1e
VK		 1267
1268 cpu->hyperv_spinlock_attempts =
a8439be6 1269 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
30d6ff66
VK		 1270 }
1271
6760bd20 1272 /* Features */
f4a62495
VK		 1273 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_RELAXED, errp)) {
1274 return;
1275 }
1276 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_VAPIC, errp)) {
1277 return;
1278 }
1279 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_TIME, errp)) {
1280 return;
1281 }
1282 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_CRASH, errp)) {
1283 return;
1284 }
1285 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_RESET, errp)) {
1286 return;
1287 }
1288 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_VPINDEX, errp)) {
1289 return;
1290 }
1291 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_RUNTIME, errp)) {
1292 return;
1293 }
1294 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_SYNIC, errp)) {
1295 return;
1296 }
1297 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER, errp)) {
1298 return;
1299 }
1300 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_FREQUENCIES, errp)) {
1301 return;
1302 }
1303 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_REENLIGHTENMENT, errp)) {
1304 return;
1305 }
1306 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_TLBFLUSH, errp)) {
1307 return;
1308 }
1309 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_EVMCS, errp)) {
1310 return;
1311 }
1312 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_IPI, errp)) {
1313 return;
1314 }
1315 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER_DIRECT, errp)) {
1316 return;
1317 }
6760bd20 1318
c6861930 1319 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1320 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1321 !cpu->hyperv_synic_kvm_only &&
1322 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
f4a62495
VK		 1323 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1324 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1325 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
6760bd20 1326 }
f6e01ab5
VK		 1327}
1328
1329/*
1330 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1331 */
1332static int hyperv_fill_cpuids(CPUState *cs,
1333 struct kvm_cpuid_entry2 *cpuid_ent)
1334{
1335 X86CPU *cpu = X86_CPU(cs);
1336 struct kvm_cpuid_entry2 *c;
1337 uint32_t cpuid_i = 0;
1338
2344d22e
VK		 1339 c = &cpuid_ent[cpuid_i++];
1340 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
2344d22e
VK		 1341 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1342 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
08856771
VK		 1343 c->ebx = cpu->hyperv_vendor_id[0];
1344 c->ecx = cpu->hyperv_vendor_id[1];
1345 c->edx = cpu->hyperv_vendor_id[2];
2344d22e
VK		 1346
1347 c = &cpuid_ent[cpuid_i++];
1348 c->function = HV_CPUID_INTERFACE;
735db465
VK		 1349 c->eax = cpu->hyperv_interface_id[0];
1350 c->ebx = cpu->hyperv_interface_id[1];
1351 c->ecx = cpu->hyperv_interface_id[2];
1352 c->edx = cpu->hyperv_interface_id[3];
2344d22e
VK		 1353
1354 c = &cpuid_ent[cpuid_i++];
1355 c->function = HV_CPUID_VERSION;
fb7e31aa
VK		 1356 c->eax = cpu->hyperv_version_id[0];
1357 c->ebx = cpu->hyperv_version_id[1];
1358 c->ecx = cpu->hyperv_version_id[2];
1359 c->edx = cpu->hyperv_version_id[3];
2344d22e
VK		 1360
1361 c = &cpuid_ent[cpuid_i++];
1362 c->function = HV_CPUID_FEATURES;
061817a7
VK		 1363 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1364 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1365 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
c830015e
VK		 1366
1367 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1368 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
2344d22e
VK		 1369
1370 c = &cpuid_ent[cpuid_i++];
1371 c->function = HV_CPUID_ENLIGHTMENT_INFO;
061817a7 1372 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
2344d22e
VK		 1373 c->ebx = cpu->hyperv_spinlock_attempts;
1374
c830015e
VK		 1375 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1376 c->eax |= HV_NO_NONARCH_CORESHARING;
1377 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
a8439be6 1378 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
e1a66a1e 1379 HV_NO_NONARCH_CORESHARING;
c830015e
VK		 1380 }
1381
2344d22e
VK		 1382 c = &cpuid_ent[cpuid_i++];
1383 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1384 c->eax = cpu->hv_max_vps;
23eb5d03
VK		 1385 c->ebx = cpu->hyperv_limits[0];
1386 c->ecx = cpu->hyperv_limits[1];
1387 c->edx = cpu->hyperv_limits[2];
2344d22e
VK		 1388
1389 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1390 __u32 function;
1391
1392 /* Create zeroed 0x40000006..0x40000009 leaves */
1393 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1394 function < HV_CPUID_NESTED_FEATURES; function++) {
1395 c = &cpuid_ent[cpuid_i++];
1396 c->function = function;
1397 }
1398
1399 c = &cpuid_ent[cpuid_i++];
1400 c->function = HV_CPUID_NESTED_FEATURES;
c830015e 1401 c->eax = cpu->hyperv_nested[0];
2344d22e 1402 }
6760bd20 1403
a8439be6 1404 return cpuid_i;
c35bd19a
EY		 1405}
1406
e48ddcc6 1407static Error *hv_passthrough_mig_blocker;
30d6ff66 1408static Error *hv_no_nonarch_cs_mig_blocker;
e48ddcc6 1409
e9688fab
RK		 1410static int hyperv_init_vcpu(X86CPU *cpu)
1411{
729ce7e1 1412 CPUState *cs = CPU(cpu);
e48ddcc6 1413 Error *local_err = NULL;
729ce7e1
RK		 1414 int ret;
1415
e48ddcc6
VK		 1416 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1417 error_setg(&hv_passthrough_mig_blocker,
1418 "'hv-passthrough' CPU flag prevents migration, use explicit"
1419 " set of hv-* flags instead");
1420 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1421 if (local_err) {
1422 error_report_err(local_err);
1423 error_free(hv_passthrough_mig_blocker);
1424 return ret;
1425 }
1426 }
1427
30d6ff66
VK		 1428 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1429 hv_no_nonarch_cs_mig_blocker == NULL) {
1430 error_setg(&hv_no_nonarch_cs_mig_blocker,
1431 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1432 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1433 " make sure SMT is disabled and/or that vCPUs are properly"
1434 " pinned)");
1435 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
1436 if (local_err) {
1437 error_report_err(local_err);
1438 error_free(hv_no_nonarch_cs_mig_blocker);
1439 return ret;
1440 }
1441 }
1442
2d384d7c 1443 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1444 /*
1445 * the kernel doesn't support setting vp_index; assert that its value
1446 * is in sync
1447 */
e9688fab
RK		 1448 struct {
1449 struct kvm_msrs info;
1450 struct kvm_msr_entry entries[1];
1451 } msr_data = {
1452 .info.nmsrs = 1,
1453 .entries[0].index = HV_X64_MSR_VP_INDEX,
1454 };
1455
729ce7e1 1456 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1457 if (ret < 0) {
1458 return ret;
1459 }
1460 assert(ret == 1);
1461
701189e3 1462 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1463 error_report("kernel's vp_index != QEMU's vp_index");
1464 return -ENXIO;
1465 }
1466 }
1467
2d384d7c 1468 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1469 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1470 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1471 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1472 if (ret < 0) {
1473 error_report("failed to turn on HyperV SynIC in KVM: %s",
1474 strerror(-ret));
1475 return ret;
1476 }
606c34bf 1477
9b4cf107
RK		 1478 if (!cpu->hyperv_synic_kvm_only) {
1479 ret = hyperv_x86_synic_add(cpu);
1480 if (ret < 0) {
1481 error_report("failed to create HyperV SynIC: %s",
1482 strerror(-ret));
1483 return ret;
1484 }
606c34bf 1485 }
729ce7e1
RK		 1486 }
1487
decb4f20
VK		 1488 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1489 uint16_t evmcs_version;
1490
1491 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1492 (uintptr_t)&evmcs_version);
1493
1494 if (ret < 0) {
1495 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1496 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1497 return ret;
1498 }
1499
1500 cpu->hyperv_nested[0] = evmcs_version;
1501 }
1502
e9688fab
RK		 1503 return 0;
1504}
1505
68bfd0ad
MT		 1506static Error *invtsc_mig_blocker;
1507
f8bb0565 1508#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1509
20d695a9 1510int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1511{
1512 struct {
486bd5a2 1513 struct kvm_cpuid2 cpuid;
f8bb0565 1514 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1515 } cpuid_data;
1516 /*
1517 * The kernel defines these structs with padding fields so there
1518 * should be no extra padding in our cpuid_data struct.
1519 */
1520 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1521 sizeof(struct kvm_cpuid2) +
1522 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1523
20d695a9
AF		 1524 X86CPU *cpu = X86_CPU(cs);
1525 CPUX86State *env = &cpu->env;
486bd5a2 1526 uint32_t limit, i, j, cpuid_i;
a33609ca 1527 uint32_t unused;
bb0300dc 1528 struct kvm_cpuid_entry2 *c;
bb0300dc 1529 uint32_t signature[3];
234cc647 1530 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1531 int max_nested_state_len;
e7429073 1532 int r;
fe44dc91 1533 Error *local_err = NULL;
05330448 1534
ef4cbe14
SW		 1535 memset(&cpuid_data, 0, sizeof(cpuid_data));
1536
05330448
AL		 1537 cpuid_i = 0;
1538
ddb98b5a
LP		 1539 r = kvm_arch_set_tsc_khz(cs);
1540 if (r < 0) {
6b2341ee 1541 return r;
ddb98b5a
LP		 1542 }
1543
1544 /* vcpu's TSC frequency is either specified by user, or following
1545 * the value used by KVM if the former is not present. In the
1546 * latter case, we query it from KVM and record in env->tsc_khz,
1547 * so that vcpu's TSC frequency can be migrated later via this field.
1548 */
1549 if (!env->tsc_khz) {
1550 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1551 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1552 -ENOTSUP;
1553 if (r > 0) {
1554 env->tsc_khz = r;
1555 }
1556 }
1557
73b994f6
LA		 1558 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1559
bb0300dc 1560 /* Paravirtualization CPUIDs */
f4a62495
VK		 1561 hyperv_expand_features(cs, &local_err);
1562 if (local_err) {
1563 error_report_err(local_err);
1564 return -ENOSYS;
f6e01ab5
VK		 1565 }
1566
1567 if (hyperv_enabled(cpu)) {
decb4f20
VK		 1568 r = hyperv_init_vcpu(cpu);
1569 if (r) {
1570 return r;
1571 }
1572
f6e01ab5 1573 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
234cc647 1574 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1575 has_msr_hv_hypercall = true;
eab70139
VR		 1576 }
1577
f522d2ac
AW		 1578 if (cpu->expose_kvm) {
1579 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1580 c = &cpuid_data.entries[cpuid_i++];
1581 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1582 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1583 c->ebx = signature[0];
1584 c->ecx = signature[1];
1585 c->edx = signature[2];
234cc647 1586
f522d2ac
AW		 1587 c = &cpuid_data.entries[cpuid_i++];
1588 c->function = KVM_CPUID_FEATURES | kvm_base;
1589 c->eax = env->features[FEAT_KVM];
be777326 1590 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1591 }
917367aa 1592
a33609ca 1593 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1594
1595 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1596 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1597 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1598 abort();
1599 }
bb0300dc 1600 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1601
1602 switch (i) {
a36b1029
AL		 1603 case 2: {
1604 /* Keep reading function 2 till all the input is received */
1605 int times;
1606
a36b1029 1607 c->function = i;
a33609ca
AL		 1608 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1609 KVM_CPUID_FLAG_STATE_READ_NEXT;
1610 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1611 times = c->eax & 0xff;
a36b1029
AL		 1612
1613 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1614 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1615 fprintf(stderr, "cpuid_data is full, no space for "
1616 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1617 abort();
1618 }
a33609ca 1619 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1620 c->function = i;
a33609ca
AL		 1621 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1622 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1623 }
1624 break;
1625 }
a94e1428
LX		 1626 case 0x1f:
1627 if (env->nr_dies < 2) {
1628 break;
1629 }
8821e214 1630 /* fallthrough */
486bd5a2
AL		 1631 case 4:
1632 case 0xb:
1633 case 0xd:
1634 for (j = 0; ; j++) {
31e8c696
AP		 1635 if (i == 0xd && j == 64) {
1636 break;
1637 }
a94e1428
LX		 1638
1639 if (i == 0x1f && j == 64) {
1640 break;
1641 }
1642
486bd5a2
AL		 1643 c->function = i;
1644 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1645 c->index = j;
a33609ca 1646 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1647
b9bec74b 1648 if (i == 4 && c->eax == 0) {
486bd5a2 1649 break;
b9bec74b
JK		 1650 }
1651 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1652 break;
b9bec74b 1653 }
a94e1428
LX		 1654 if (i == 0x1f && !(c->ecx & 0xff00)) {
1655 break;
1656 }
b9bec74b 1657 if (i == 0xd && c->eax == 0) {
31e8c696 1658 continue;
b9bec74b 1659 }
f8bb0565
IM		 1660 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1661 fprintf(stderr, "cpuid_data is full, no space for "
1662 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1663 abort();
1664 }
a33609ca 1665 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1666 }
1667 break;
80db491d 1668 case 0x7:
e37a5c7f
CP		 1669 case 0x14: {
1670 uint32_t times;
1671
1672 c->function = i;
1673 c->index = 0;
1674 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1675 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1676 times = c->eax;
1677
1678 for (j = 1; j <= times; ++j) {
1679 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1680 fprintf(stderr, "cpuid_data is full, no space for "
80db491d 1681 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
e37a5c7f
CP		 1682 abort();
1683 }
1684 c = &cpuid_data.entries[cpuid_i++];
1685 c->function = i;
1686 c->index = j;
1687 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1688 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1689 }
1690 break;
1691 }
486bd5a2 1692 default:
486bd5a2 1693 c->function = i;
a33609ca
AL		 1694 c->flags = 0;
1695 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1696 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1697 /*
1698 * KVM already returns all zeroes if a CPUID entry is missing,
1699 * so we can omit it and avoid hitting KVM's 80-entry limit.
1700 */
1701 cpuid_i--;
1702 }
486bd5a2
AL		 1703 break;
1704 }
05330448 1705 }
0d894367
PB		 1706
1707 if (limit >= 0x0a) {
0b368a10 1708 uint32_t eax, edx;
0d894367 1709
0b368a10
JD		 1710 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1711
1712 has_architectural_pmu_version = eax & 0xff;
1713 if (has_architectural_pmu_version > 0) {
1714 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1715
1716 /* Shouldn't be more than 32, since that's the number of bits
1717 * available in EBX to tell us _which_ counters are available.
1718 * Play it safe.
1719 */
0b368a10
JD		 1720 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1721 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1722 }
1723
1724 if (has_architectural_pmu_version > 1) {
1725 num_architectural_pmu_fixed_counters = edx & 0x1f;
1726
1727 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1728 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1729 }
0d894367
PB		 1730 }
1731 }
1732 }
1733
a33609ca 1734 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1735
1736 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1737 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1738 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1739 abort();
1740 }
bb0300dc 1741 c = &cpuid_data.entries[cpuid_i++];
05330448 1742
8f4202fb
BM		 1743 switch (i) {
1744 case 0x8000001d:
1745 /* Query for all AMD cache information leaves */
1746 for (j = 0; ; j++) {
1747 c->function = i;
1748 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1749 c->index = j;
1750 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1751
1752 if (c->eax == 0) {
1753 break;
1754 }
1755 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1756 fprintf(stderr, "cpuid_data is full, no space for "
1757 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1758 abort();
1759 }
1760 c = &cpuid_data.entries[cpuid_i++];
1761 }
1762 break;
1763 default:
1764 c->function = i;
1765 c->flags = 0;
1766 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1767 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1768 /*
1769 * KVM already returns all zeroes if a CPUID entry is missing,
1770 * so we can omit it and avoid hitting KVM's 80-entry limit.
1771 */
1772 cpuid_i--;
1773 }
8f4202fb
BM		 1774 break;
1775 }
05330448
AL		 1776 }
1777
b3baa152
BW		 1778 /* Call Centaur's CPUID instructions they are supported. */
1779 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1780 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1781
1782 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1783 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1784 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1785 abort();
1786 }
b3baa152
BW		 1787 c = &cpuid_data.entries[cpuid_i++];
1788
1789 c->function = i;
1790 c->flags = 0;
1791 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1792 }
1793 }
1794
05330448
AL		 1795 cpuid_data.cpuid.nent = cpuid_i;
1796
e7701825 1797 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1798 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1799 (CPUID_MCE | CPUID_MCA)
a60f24b5 1800 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1801 uint64_t mcg_cap, unsupported_caps;
e7701825 1802 int banks;
32a42024 1803 int ret;
e7701825 1804
a60f24b5 1805 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1806 if (ret < 0) {
1807 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1808 return ret;
e7701825 1809 }
75d49497 1810
2590f15b 1811 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1812 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1813 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1814 return -ENOTSUP;
75d49497 1815 }
49b69cbf 1816
5120901a
EH		 1817 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1818 if (unsupported_caps) {
87f8b626
AR		 1819 if (unsupported_caps & MCG_LMCE_P) {
1820 error_report("kvm: LMCE not supported");
1821 return -ENOTSUP;
1822 }
3dc6f869
AF		 1823 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1824 unsupported_caps);
5120901a
EH		 1825 }
1826
2590f15b
EH		 1827 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1828 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1829 if (ret < 0) {
1830 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1831 return ret;
1832 }
e7701825 1833 }
e7701825 1834
2a693142 1835 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
b8cc45d6 1836
df67696e
LJ		 1837 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1838 if (c) {
1839 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1840 !!(c->ecx & CPUID_EXT_SMX);
1841 }
1842
87f8b626
AR		 1843 if (env->mcg_cap & MCG_LMCE_P) {
1844 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1845 }
1846
d99569d9
EH		 1847 if (!env->user_tsc_khz) {
1848 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1849 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1850 error_setg(&invtsc_mig_blocker,
1851 "State blocked by non-migratable CPU device"
1852 " (invtsc flag)");
fe44dc91
AA		 1853 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1854 if (local_err) {
1855 error_report_err(local_err);
1856 error_free(invtsc_mig_blocker);
79a197ab 1857 return r;
fe44dc91 1858 }
d99569d9 1859 }
68bfd0ad
MT		 1860 }
1861
9954a158
PDJ		 1862 if (cpu->vmware_cpuid_freq
1863 /* Guests depend on 0x40000000 to detect this feature, so only expose
1864 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1865 && cpu->expose_kvm
1866 && kvm_base == KVM_CPUID_SIGNATURE
1867 /* TSC clock must be stable and known for this feature. */
4bb95b82 1868 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1869
1870 c = &cpuid_data.entries[cpuid_i++];
1871 c->function = KVM_CPUID_SIGNATURE | 0x10;
1872 c->eax = env->tsc_khz;
73b994f6 1873 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
9954a158
PDJ		 1874 c->ecx = c->edx = 0;
1875
1876 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1877 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1878 }
1879
1880 cpuid_data.cpuid.nent = cpuid_i;
1881
1882 cpuid_data.cpuid.padding = 0;
1883 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1884 if (r) {
1885 goto fail;
1886 }
1887
28143b40 1888 if (has_xsave) {
5b8063c4 1889 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1f670a95 1890 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
fabacc0f 1891 }
ebbfef2f
LA		 1892
1893 max_nested_state_len = kvm_max_nested_state_length();
1894 if (max_nested_state_len > 0) {
1895 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
ebbfef2f 1896
b16c0e20 1897 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
1e44f3ab 1898 struct kvm_vmx_nested_state_hdr *vmx_hdr;
ebbfef2f 1899
1e44f3ab
PB		 1900 env->nested_state = g_malloc0(max_nested_state_len);
1901 env->nested_state->size = max_nested_state_len;
1e44f3ab 1902
b16c0e20 1903 if (cpu_has_vmx(env)) {
2654ace1
TL		 1904 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1905 vmx_hdr = &env->nested_state->hdr.vmx;
1906 vmx_hdr->vmxon_pa = -1ull;
1907 vmx_hdr->vmcs12_pa = -1ull;
1908 } else {
1909 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
b16c0e20 1910 }
ebbfef2f
LA		 1911 }
1912 }
1913
d71b62a1 1914 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1915
273c515c
PB		 1916 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1917 has_msr_tsc_aux = false;
1918 }
d1ae67f6 1919
420ae1fc
PB		 1920 kvm_init_msrs(cpu);
1921
e7429073 1922 return 0;
fe44dc91
AA		 1923
1924 fail:
1925 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 1926
fe44dc91 1927 return r;
05330448
AL		 1928}
1929
b1115c99
LA		 1930int kvm_arch_destroy_vcpu(CPUState *cs)
1931{
1932 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 1933 CPUX86State *env = &cpu->env;
b1115c99
LA		 1934
1935 if (cpu->kvm_msr_buf) {
1936 g_free(cpu->kvm_msr_buf);
1937 cpu->kvm_msr_buf = NULL;
1938 }
1939
ebbfef2f
LA		 1940 if (env->nested_state) {
1941 g_free(env->nested_state);
1942 env->nested_state = NULL;
1943 }
1944
2a693142
PN		 1945 qemu_del_vm_change_state_handler(cpu->vmsentry);
1946
b1115c99
LA		 1947 return 0;
1948}
1949
50a2c6e5 1950void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1951{
20d695a9 1952 CPUX86State *env = &cpu->env;
dd673288 1953
1a5e9d2f 1954 env->xcr0 = 1;
ddced198 1955 if (kvm_irqchip_in_kernel()) {
dd673288 1956 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1957 KVM_MP_STATE_UNINITIALIZED;
1958 } else {
1959 env->mp_state = KVM_MP_STATE_RUNNABLE;
1960 }
689141dd 1961
2d384d7c 1962 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1963 int i;
1964 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1965 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1966 }
606c34bf
RK		 1967
1968 hyperv_x86_synic_reset(cpu);
689141dd 1969 }
d645e132
MT		 1970 /* enabled by default */
1971 env->poll_control_msr = 1;
b2f73a07
PB		 1972
1973 sev_es_set_reset_vector(CPU(cpu));
caa5af0f
JK		 1974}
1975
e0723c45
PB		 1976void kvm_arch_do_init_vcpu(X86CPU *cpu)
1977{
1978 CPUX86State *env = &cpu->env;
1979
1980 /* APs get directly into wait-for-SIPI state. */
1981 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1982 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1983 }
1984}
1985
f57bceb6
RH		 1986static int kvm_get_supported_feature_msrs(KVMState *s)
1987{
1988 int ret = 0;
1989
1990 if (kvm_feature_msrs != NULL) {
1991 return 0;
1992 }
1993
1994 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1995 return 0;
1996 }
1997
1998 struct kvm_msr_list msr_list;
1999
2000 msr_list.nmsrs = 0;
2001 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2002 if (ret < 0 && ret != -E2BIG) {
2003 error_report("Fetch KVM feature MSR list failed: %s",
2004 strerror(-ret));
2005 return ret;
2006 }
2007
2008 assert(msr_list.nmsrs > 0);
2009 kvm_feature_msrs = (struct kvm_msr_list *) \
2010 g_malloc0(sizeof(msr_list) +
2011 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2012
2013 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2014 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2015
2016 if (ret < 0) {
2017 error_report("Fetch KVM feature MSR list failed: %s",
2018 strerror(-ret));
2019 g_free(kvm_feature_msrs);
2020 kvm_feature_msrs = NULL;
2021 return ret;
2022 }
2023
2024 return 0;
2025}
2026
c3a3a7d3 2027static int kvm_get_supported_msrs(KVMState *s)
05330448 2028{
c3a3a7d3 2029 int ret = 0;
de428cea 2030 struct kvm_msr_list msr_list, *kvm_msr_list;
05330448 2031
de428cea
LQ		 2032 /*
2033 * Obtain MSR list from KVM. These are the MSRs that we must
2034 * save/restore.
2035 */
2036 msr_list.nmsrs = 0;
2037 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2038 if (ret < 0 && ret != -E2BIG) {
2039 return ret;
2040 }
2041 /*
2042 * Old kernel modules had a bug and could write beyond the provided
2043 * memory. Allocate at least a safe amount of 1K.
2044 */
2045 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2046 msr_list.nmsrs *
2047 sizeof(msr_list.indices[0])));
05330448 2048
de428cea
LQ		 2049 kvm_msr_list->nmsrs = msr_list.nmsrs;
2050 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2051 if (ret >= 0) {
2052 int i;
05330448 2053
de428cea
LQ		 2054 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2055 switch (kvm_msr_list->indices[i]) {
2056 case MSR_STAR:
2057 has_msr_star = true;
2058 break;
2059 case MSR_VM_HSAVE_PA:
2060 has_msr_hsave_pa = true;
2061 break;
2062 case MSR_TSC_AUX:
2063 has_msr_tsc_aux = true;
2064 break;
2065 case MSR_TSC_ADJUST:
2066 has_msr_tsc_adjust = true;
2067 break;
2068 case MSR_IA32_TSCDEADLINE:
2069 has_msr_tsc_deadline = true;
2070 break;
2071 case MSR_IA32_SMBASE:
2072 has_msr_smbase = true;
2073 break;
2074 case MSR_SMI_COUNT:
2075 has_msr_smi_count = true;
2076 break;
2077 case MSR_IA32_MISC_ENABLE:
2078 has_msr_misc_enable = true;
2079 break;
2080 case MSR_IA32_BNDCFGS:
2081 has_msr_bndcfgs = true;
2082 break;
2083 case MSR_IA32_XSS:
2084 has_msr_xss = true;
2085 break;
65087997
TX		 2086 case MSR_IA32_UMWAIT_CONTROL:
2087 has_msr_umwait = true;
2088 break;
de428cea
LQ		 2089 case HV_X64_MSR_CRASH_CTL:
2090 has_msr_hv_crash = true;
2091 break;
2092 case HV_X64_MSR_RESET:
2093 has_msr_hv_reset = true;
2094 break;
2095 case HV_X64_MSR_VP_INDEX:
2096 has_msr_hv_vpindex = true;
2097 break;
2098 case HV_X64_MSR_VP_RUNTIME:
2099 has_msr_hv_runtime = true;
2100 break;
2101 case HV_X64_MSR_SCONTROL:
2102 has_msr_hv_synic = true;
2103 break;
2104 case HV_X64_MSR_STIMER0_CONFIG:
2105 has_msr_hv_stimer = true;
2106 break;
2107 case HV_X64_MSR_TSC_FREQUENCY:
2108 has_msr_hv_frequencies = true;
2109 break;
2110 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2111 has_msr_hv_reenlightenment = true;
2112 break;
2113 case MSR_IA32_SPEC_CTRL:
2114 has_msr_spec_ctrl = true;
2115 break;
2a9758c5
PB		 2116 case MSR_IA32_TSX_CTRL:
2117 has_msr_tsx_ctrl = true;
2118 break;
de428cea
LQ		 2119 case MSR_VIRT_SSBD:
2120 has_msr_virt_ssbd = true;
2121 break;
2122 case MSR_IA32_ARCH_CAPABILITIES:
2123 has_msr_arch_capabs = true;
2124 break;
2125 case MSR_IA32_CORE_CAPABILITY:
2126 has_msr_core_capabs = true;
2127 break;
ea39f9b6
LX		 2128 case MSR_IA32_PERF_CAPABILITIES:
2129 has_msr_perf_capabs = true;
2130 break;
20a78b02
PB		 2131 case MSR_IA32_VMX_VMFUNC:
2132 has_msr_vmx_vmfunc = true;
2133 break;
67025148
PB		 2134 case MSR_IA32_UCODE_REV:
2135 has_msr_ucode_rev = true;
2136 break;
4a910e1f
VK		 2137 case MSR_IA32_VMX_PROCBASED_CTLS2:
2138 has_msr_vmx_procbased_ctls2 = true;
2139 break;
6aa4228b
CQ		 2140 case MSR_IA32_PKRS:
2141 has_msr_pkrs = true;
2142 break;
05330448
AL		 2143 }
2144 }
05330448
AL		 2145 }
2146
de428cea
LQ		 2147 g_free(kvm_msr_list);
2148
c3a3a7d3 2149 return ret;
05330448
AL		 2150}
2151
6410848b
PB		 2152static Notifier smram_machine_done;
2153static KVMMemoryListener smram_listener;
2154static AddressSpace smram_address_space;
2155static MemoryRegion smram_as_root;
2156static MemoryRegion smram_as_mem;
2157
2158static void register_smram_listener(Notifier *n, void *unused)
2159{
2160 MemoryRegion *smram =
2161 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2162
2163 /* Outer container... */
2164 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2165 memory_region_set_enabled(&smram_as_root, true);
2166
2167 /* ... with two regions inside: normal system memory with low
2168 * priority, and...
2169 */
2170 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2171 get_system_memory(), 0, ~0ull);
2172 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2173 memory_region_set_enabled(&smram_as_mem, true);
2174
2175 if (smram) {
2176 /* ... SMRAM with higher priority */
2177 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2178 memory_region_set_enabled(smram, true);
2179 }
2180
2181 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2182 kvm_memory_listener_register(kvm_state, &smram_listener,
2183 &smram_address_space, 1);
2184}
2185
b16565b3 2186int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 2187{
11076198 2188 uint64_t identity_base = 0xfffbc000;
39d6960a 2189 uint64_t shadow_mem;
20420430 2190 int ret;
25d2e361 2191 struct utsname utsname;
ec78e2cd
DG		 2192 Error *local_err = NULL;
2193
2194 /*
2195 * Initialize SEV context, if required
2196 *
2197 * If no memory encryption is requested (ms->cgs == NULL) this is
2198 * a no-op.
2199 *
2200 * It's also a no-op if a non-SEV confidential guest support
2201 * mechanism is selected. SEV is the only mechanism available to
2202 * select on x86 at present, so this doesn't arise, but if new
2203 * mechanisms are supported in future (e.g. TDX), they'll need
2204 * their own initialization either here or elsewhere.
2205 */
2206 ret = sev_kvm_init(ms->cgs, &local_err);
2207 if (ret < 0) {
2208 error_report_err(local_err);
2209 return ret;
2210 }
20420430 2211
1a6dff5f
EH		 2212 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2213 error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM");
2214 return -ENOTSUP;
2215 }
2216
28143b40 2217 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 2218 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 2219 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 2220
e9688fab
RK		 2221 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2222
fd13f23b
LA		 2223 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2224 if (has_exception_payload) {
2225 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2226 if (ret < 0) {
2227 error_report("kvm: Failed to enable exception payload cap: %s",
2228 strerror(-ret));
2229 return ret;
2230 }
2231 }
2232
c3a3a7d3 2233 ret = kvm_get_supported_msrs(s);
20420430 2234 if (ret < 0) {
20420430
SY		 2235 return ret;
2236 }
25d2e361 2237
f57bceb6
RH		 2238 kvm_get_supported_feature_msrs(s);
2239
25d2e361
MT		 2240 uname(&utsname);
2241 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2242
4c5b10b7 2243 /*
11076198
JK		 2244 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2245 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2246 * Since these must be part of guest physical memory, we need to allocate
2247 * them, both by setting their start addresses in the kernel and by
2248 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2249 *
2250 * Older KVM versions may not support setting the identity map base. In
2251 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2252 * size.
4c5b10b7 2253 */
11076198
JK		 2254 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2255 /* Allows up to 16M BIOSes. */
2256 identity_base = 0xfeffc000;
2257
2258 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2259 if (ret < 0) {
2260 return ret;
2261 }
4c5b10b7 2262 }
e56ff191 2263
11076198
JK		 2264 /* Set TSS base one page after EPT identity map. */
2265 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2266 if (ret < 0) {
2267 return ret;
2268 }
2269
11076198
JK		 2270 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2271 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2272 if (ret < 0) {
11076198 2273 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2274 return ret;
2275 }
2276
23b0898e 2277 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
36ad0e94
MA		 2278 if (shadow_mem != -1) {
2279 shadow_mem /= 4096;
2280 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2281 if (ret < 0) {
2282 return ret;
39d6960a
JK		 2283 }
2284 }
6410848b 2285
d870cfde 2286 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
8f54bbd0 2287 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
ed9e923c 2288 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
6410848b
PB		 2289 smram_machine_done.notify = register_smram_listener;
2290 qemu_add_machine_init_done_notifier(&smram_machine_done);
2291 }
6f131f13
MT		 2292
2293 if (enable_cpu_pm) {
2294 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2295 int ret;
2296
2297/* Work around for kernel header with a typo. TODO: fix header and drop. */
2298#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2299#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2300#endif
2301 if (disable_exits) {
2302 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2303 KVM_X86_DISABLE_EXITS_HLT |
d38d201f
WL		 2304 KVM_X86_DISABLE_EXITS_PAUSE |
2305 KVM_X86_DISABLE_EXITS_CSTATE);
6f131f13
MT		 2306 }
2307
2308 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2309 disable_exits);
2310 if (ret < 0) {
2311 error_report("kvm: guest stopping CPU not supported: %s",
2312 strerror(-ret));
2313 }
2314 }
2315
11076198 2316 return 0;
05330448 2317}
b9bec74b 2318
05330448
AL		 2319static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2320{
2321 lhs->selector = rhs->selector;
2322 lhs->base = rhs->base;
2323 lhs->limit = rhs->limit;
2324 lhs->type = 3;
2325 lhs->present = 1;
2326 lhs->dpl = 3;
2327 lhs->db = 0;
2328 lhs->s = 1;
2329 lhs->l = 0;
2330 lhs->g = 0;
2331 lhs->avl = 0;
2332 lhs->unusable = 0;
2333}
2334
2335static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2336{
2337 unsigned flags = rhs->flags;
2338 lhs->selector = rhs->selector;
2339 lhs->base = rhs->base;
2340 lhs->limit = rhs->limit;
2341 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2342 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2343 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2344 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2345 lhs->s = (flags & DESC_S_MASK) != 0;
2346 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2347 lhs->g = (flags & DESC_G_MASK) != 0;
2348 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2349 lhs->unusable = !lhs->present;
7e680753 2350 lhs->padding = 0;
05330448
AL		 2351}
2352
2353static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2354{
2355 lhs->selector = rhs->selector;
2356 lhs->base = rhs->base;
2357 lhs->limit = rhs->limit;
d45fc087
RP		 2358 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2359 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2360 (rhs->dpl << DESC_DPL_SHIFT) |
2361 (rhs->db << DESC_B_SHIFT) |
2362 (rhs->s * DESC_S_MASK) |
2363 (rhs->l << DESC_L_SHIFT) |
2364 (rhs->g * DESC_G_MASK) |
2365 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2366}
2367
2368static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2369{
b9bec74b 2370 if (set) {
05330448 2371 *kvm_reg = *qemu_reg;
b9bec74b 2372 } else {
05330448 2373 *qemu_reg = *kvm_reg;
b9bec74b 2374 }
05330448
AL		 2375}
2376
1bc22652 2377static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2378{
1bc22652 2379 CPUX86State *env = &cpu->env;
05330448
AL		 2380 struct kvm_regs regs;
2381 int ret = 0;
2382
2383 if (!set) {
1bc22652 2384 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2385 if (ret < 0) {
05330448 2386 return ret;
b9bec74b 2387 }
05330448
AL		 2388 }
2389
2390 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2391 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2392 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2393 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2394 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2395 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2396 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2397 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2398#ifdef TARGET_X86_64
2399 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2400 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2401 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2402 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2403 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2404 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2405 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2406 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2407#endif
2408
2409 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2410 kvm_getput_reg(&regs.rip, &env->eip, set);
2411
b9bec74b 2412 if (set) {
1bc22652 2413 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2414 }
05330448
AL		 2415
2416 return ret;
2417}
2418
1bc22652 2419static int kvm_put_fpu(X86CPU *cpu)
05330448 2420{
1bc22652 2421 CPUX86State *env = &cpu->env;
05330448
AL		 2422 struct kvm_fpu fpu;
2423 int i;
2424
2425 memset(&fpu, 0, sizeof fpu);
2426 fpu.fsw = env->fpus & ~(7 << 11);
2427 fpu.fsw |= (env->fpstt & 7) << 11;
2428 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2429 fpu.last_opcode = env->fpop;
2430 fpu.last_ip = env->fpip;
2431 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2432 for (i = 0; i < 8; ++i) {
2433 fpu.ftwx |= (!env->fptags[i]) << i;
2434 }
05330448 2435 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2436 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2437 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2438 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2439 }
05330448
AL		 2440 fpu.mxcsr = env->mxcsr;
2441
1bc22652 2442 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2443}
2444
6b42494b
JK		 2445#define XSAVE_FCW_FSW 0
2446#define XSAVE_FTW_FOP 1
f1665b21
SY		 2447#define XSAVE_CWD_RIP 2
2448#define XSAVE_CWD_RDP 4
2449#define XSAVE_MXCSR 6
2450#define XSAVE_ST_SPACE 8
2451#define XSAVE_XMM_SPACE 40
2452#define XSAVE_XSTATE_BV 128
2453#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2454#define XSAVE_BNDREGS 240
2455#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2456#define XSAVE_OPMASK 272
2457#define XSAVE_ZMM_Hi256 288
2458#define XSAVE_Hi16_ZMM 416
f74eefe0 2459#define XSAVE_PKRU 672
f1665b21 2460
b503717d 2461#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2462 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2463
2464#define ASSERT_OFFSET(word_offset, field) \
2465 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2466 offsetof(X86XSaveArea, field))
2467
2468ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2469ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2470ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2471ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2472ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2473ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2474ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2475ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2476ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2477ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2478ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2479ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2480ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2481ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2482ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2483
1bc22652 2484static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2485{
1bc22652 2486 CPUX86State *env = &cpu->env;
5b8063c4 2487 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2488
28143b40 2489 if (!has_xsave) {
1bc22652 2490 return kvm_put_fpu(cpu);
b9bec74b 2491 }
86a57621 2492 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2493
9be38598 2494 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2495}
2496
1bc22652 2497static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2498{
1bc22652 2499 CPUX86State *env = &cpu->env;
bdfc8480 2500 struct kvm_xcrs xcrs = {};
f1665b21 2501
28143b40 2502 if (!has_xcrs) {
f1665b21 2503 return 0;
b9bec74b 2504 }
f1665b21
SY		 2505
2506 xcrs.nr_xcrs = 1;
2507 xcrs.flags = 0;
2508 xcrs.xcrs[0].xcr = 0;
2509 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2510 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2511}
2512
1bc22652 2513static int kvm_put_sregs(X86CPU *cpu)
05330448 2514{
1bc22652 2515 CPUX86State *env = &cpu->env;
05330448
AL		 2516 struct kvm_sregs sregs;
2517
0e607a80
JK		 2518 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2519 if (env->interrupt_injected >= 0) {
2520 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2521 (uint64_t)1 << (env->interrupt_injected % 64);
2522 }
05330448
AL		 2523
2524 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2525 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2526 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2527 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2528 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2529 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2530 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2531 } else {
b9bec74b
JK		 2532 set_seg(&sregs.cs, &env->segs[R_CS]);
2533 set_seg(&sregs.ds, &env->segs[R_DS]);
2534 set_seg(&sregs.es, &env->segs[R_ES]);
2535 set_seg(&sregs.fs, &env->segs[R_FS]);
2536 set_seg(&sregs.gs, &env->segs[R_GS]);
2537 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2538 }
2539
2540 set_seg(&sregs.tr, &env->tr);
2541 set_seg(&sregs.ldt, &env->ldt);
2542
2543 sregs.idt.limit = env->idt.limit;
2544 sregs.idt.base = env->idt.base;
7e680753 2545 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2546 sregs.gdt.limit = env->gdt.limit;
2547 sregs.gdt.base = env->gdt.base;
7e680753 2548 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2549
2550 sregs.cr0 = env->cr[0];
2551 sregs.cr2 = env->cr[2];
2552 sregs.cr3 = env->cr[3];
2553 sregs.cr4 = env->cr[4];
2554
02e51483
CF		 2555 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2556 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2557
2558 sregs.efer = env->efer;
2559
1bc22652 2560 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2561}
2562
d71b62a1
EH		 2563static void kvm_msr_buf_reset(X86CPU *cpu)
2564{
2565 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2566}
2567
9c600a84
EH		 2568static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2569{
2570 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2571 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2572 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2573
2574 assert((void *)(entry + 1) <= limit);
2575
1abc2cae
EH		 2576 entry->index = index;
2577 entry->reserved = 0;
2578 entry->data = value;
9c600a84
EH		 2579 msrs->nmsrs++;
2580}
2581
73e1b8f2
PB		 2582static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2583{
2584 kvm_msr_buf_reset(cpu);
2585 kvm_msr_entry_add(cpu, index, value);
2586
2587 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2588}
2589
f8d9ccf8
DDAG		 2590void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2591{
2592 int ret;
2593
2594 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2595 assert(ret == 1);
2596}
2597
7477cd38
MT		 2598static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2599{
2600 CPUX86State *env = &cpu->env;
48e1a45c 2601 int ret;
7477cd38
MT		 2602
2603 if (!has_msr_tsc_deadline) {
2604 return 0;
2605 }
2606
73e1b8f2 2607 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2608 if (ret < 0) {
2609 return ret;
2610 }
2611
2612 assert(ret == 1);
2613 return 0;
7477cd38
MT		 2614}
2615
6bdf863d
JK		 2616/*
2617 * Provide a separate write service for the feature control MSR in order to
2618 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2619 * before writing any other state because forcibly leaving nested mode
2620 * invalidates the VCPU state.
2621 */
2622static int kvm_put_msr_feature_control(X86CPU *cpu)
2623{
48e1a45c
PB		 2624 int ret;
2625
2626 if (!has_msr_feature_control) {
2627 return 0;
2628 }
6bdf863d 2629
73e1b8f2
PB		 2630 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2631 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2632 if (ret < 0) {
2633 return ret;
2634 }
2635
2636 assert(ret == 1);
2637 return 0;
6bdf863d
JK		 2638}
2639
20a78b02
PB		 2640static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2641{
2642 uint32_t default1, can_be_one, can_be_zero;
2643 uint32_t must_be_one;
2644
2645 switch (index) {
2646 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2647 default1 = 0x00000016;
2648 break;
2649 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2650 default1 = 0x0401e172;
2651 break;
2652 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2653 default1 = 0x000011ff;
2654 break;
2655 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2656 default1 = 0x00036dff;
2657 break;
2658 case MSR_IA32_VMX_PROCBASED_CTLS2:
2659 default1 = 0;
2660 break;
2661 default:
2662 abort();
2663 }
2664
2665 /* If a feature bit is set, the control can be either set or clear.
2666 * Otherwise the value is limited to either 0 or 1 by default1.
2667 */
2668 can_be_one = features | default1;
2669 can_be_zero = features | ~default1;
2670 must_be_one = ~can_be_zero;
2671
2672 /*
2673 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2674 * Bit 32:63 -> 1 if the control bit can be one.
2675 */
2676 return must_be_one | (((uint64_t)can_be_one) << 32);
2677}
2678
2679#define VMCS12_MAX_FIELD_INDEX (0x17)
2680
2681static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2682{
2683 uint64_t kvm_vmx_basic =
2684 kvm_arch_get_supported_msr_feature(kvm_state,
2685 MSR_IA32_VMX_BASIC);
26051882
YZ		 2686
2687 if (!kvm_vmx_basic) {
2688 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2689 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2690 */
2691 return;
2692 }
2693
20a78b02
PB		 2694 uint64_t kvm_vmx_misc =
2695 kvm_arch_get_supported_msr_feature(kvm_state,
2696 MSR_IA32_VMX_MISC);
2697 uint64_t kvm_vmx_ept_vpid =
2698 kvm_arch_get_supported_msr_feature(kvm_state,
2699 MSR_IA32_VMX_EPT_VPID_CAP);
2700
2701 /*
2702 * If the guest is 64-bit, a value of 1 is allowed for the host address
2703 * space size vmexit control.
2704 */
2705 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2706 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2707
2708 /*
2709 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2710 * not change them for backwards compatibility.
2711 */
2712 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2713 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2714 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2715 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2716
2717 /*
2718 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2719 * change in the future but are always zero for now, clear them to be
2720 * future proof. Bits 32-63 in theory could change, though KVM does
2721 * not support dual-monitor treatment and probably never will; mask
2722 * them out as well.
2723 */
2724 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2725 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2726 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2727
2728 /*
2729 * EPT memory types should not change either, so we do not bother
2730 * adding features for them.
2731 */
2732 uint64_t fixed_vmx_ept_mask =
2733 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2734 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2735 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2736
2737 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2738 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2739 f[FEAT_VMX_PROCBASED_CTLS]));
2740 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2741 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2742 f[FEAT_VMX_PINBASED_CTLS]));
2743 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2744 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2745 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2746 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2747 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2748 f[FEAT_VMX_ENTRY_CTLS]));
2749 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2750 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2751 f[FEAT_VMX_SECONDARY_CTLS]));
2752 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2753 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2754 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2755 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2756 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2757 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2758 if (has_msr_vmx_vmfunc) {
2759 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2760 }
2761
2762 /*
2763 * Just to be safe, write these with constant values. The CRn_FIXED1
2764 * MSRs are generated by KVM based on the vCPU's CPUID.
2765 */
2766 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2767 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2768 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2769 CR4_VMXE_MASK);
2770 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM,
2771 VMCS12_MAX_FIELD_INDEX << 1);
2772}
2773
ea39f9b6
LX		 2774static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
2775{
2776 uint64_t kvm_perf_cap =
2777 kvm_arch_get_supported_msr_feature(kvm_state,
2778 MSR_IA32_PERF_CAPABILITIES);
2779
2780 if (kvm_perf_cap) {
2781 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
2782 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
2783 }
2784}
2785
420ae1fc
PB		 2786static int kvm_buf_set_msrs(X86CPU *cpu)
2787{
2788 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2789 if (ret < 0) {
2790 return ret;
2791 }
2792
2793 if (ret < cpu->kvm_msr_buf->nmsrs) {
2794 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2795 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2796 (uint32_t)e->index, (uint64_t)e->data);
2797 }
2798
2799 assert(ret == cpu->kvm_msr_buf->nmsrs);
2800 return 0;
2801}
2802
2803static void kvm_init_msrs(X86CPU *cpu)
2804{
2805 CPUX86State *env = &cpu->env;
2806
2807 kvm_msr_buf_reset(cpu);
2808 if (has_msr_arch_capabs) {
2809 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2810 env->features[FEAT_ARCH_CAPABILITIES]);
2811 }
2812
2813 if (has_msr_core_capabs) {
2814 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2815 env->features[FEAT_CORE_CAPABILITY]);
2816 }
2817
ea39f9b6
LX		 2818 if (has_msr_perf_capabs && cpu->enable_pmu) {
2819 kvm_msr_entry_add_perf(cpu, env->features);
2820 }
2821
67025148 2822 if (has_msr_ucode_rev) {
32c87d70
PB		 2823 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
2824 }
2825
420ae1fc
PB		 2826 /*
2827 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2828 * all kernels with MSR features should have them.
2829 */
2830 if (kvm_feature_msrs && cpu_has_vmx(env)) {
2831 kvm_msr_entry_add_vmx(cpu, env->features);
2832 }
2833
2834 assert(kvm_buf_set_msrs(cpu) == 0);
2835}
2836
1bc22652 2837static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2838{
1bc22652 2839 CPUX86State *env = &cpu->env;
9c600a84 2840 int i;
05330448 2841
d71b62a1
EH		 2842 kvm_msr_buf_reset(cpu);
2843
9c600a84
EH		 2844 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2845 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2846 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2847 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2848 if (has_msr_star) {
9c600a84 2849 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2850 }
c3a3a7d3 2851 if (has_msr_hsave_pa) {
9c600a84 2852 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2853 }
c9b8f6b6 2854 if (has_msr_tsc_aux) {
9c600a84 2855 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2856 }
f28558d3 2857 if (has_msr_tsc_adjust) {
9c600a84 2858 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2859 }
21e87c46 2860 if (has_msr_misc_enable) {
9c600a84 2861 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2862 env->msr_ia32_misc_enable);
2863 }
fc12d72e 2864 if (has_msr_smbase) {
9c600a84 2865 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2866 }
e13713db
LA		 2867 if (has_msr_smi_count) {
2868 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2869 }
6aa4228b
CQ		 2870 if (has_msr_pkrs) {
2871 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
2872 }
439d19f2 2873 if (has_msr_bndcfgs) {
9c600a84 2874 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2875 }
18cd2c17 2876 if (has_msr_xss) {
9c600a84 2877 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2878 }
65087997
TX		 2879 if (has_msr_umwait) {
2880 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
2881 }
a33a2cfe
PB		 2882 if (has_msr_spec_ctrl) {
2883 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2884 }
2a9758c5
PB		 2885 if (has_msr_tsx_ctrl) {
2886 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
2887 }
cfeea0c0
KRW		 2888 if (has_msr_virt_ssbd) {
2889 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2890 }
2891
05330448 2892#ifdef TARGET_X86_64
25d2e361 2893 if (lm_capable_kernel) {
9c600a84
EH		 2894 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2895 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2896 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2897 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2898 }
05330448 2899#endif
a33a2cfe 2900
ff5c186b 2901 /*
0d894367
PB		 2902 * The following MSRs have side effects on the guest or are too heavy
2903 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2904 */
2905 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2906 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2907 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2908 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
6615be07
VK		 2909 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
2910 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
2911 }
55c911a5 2912 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2913 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2914 }
55c911a5 2915 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2916 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2917 }
55c911a5 2918 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2919 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2920 }
d645e132
MT		 2921
2922 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2923 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2924 }
2925
0b368a10
JD		 2926 if (has_architectural_pmu_version > 0) {
2927 if (has_architectural_pmu_version > 1) {
2928 /* Stop the counter. */
2929 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2930 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2931 }
0d894367
PB		 2932
2933 /* Set the counter values. */
0b368a10 2934 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2935 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2936 env->msr_fixed_counters[i]);
2937 }
0b368a10 2938 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2939 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2940 env->msr_gp_counters[i]);
9c600a84 2941 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2942 env->msr_gp_evtsel[i]);
2943 }
0b368a10
JD		 2944 if (has_architectural_pmu_version > 1) {
2945 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2946 env->msr_global_status);
2947 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2948 env->msr_global_ovf_ctrl);
2949
2950 /* Now start the PMU. */
2951 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2952 env->msr_fixed_ctr_ctrl);
2953 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2954 env->msr_global_ctrl);
2955 }
0d894367 2956 }
da1cc323
EY		 2957 /*
2958 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2959 * only sync them to KVM on the first cpu
2960 */
2961 if (current_cpu == first_cpu) {
2962 if (has_msr_hv_hypercall) {
2963 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2964 env->msr_hv_guest_os_id);
2965 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2966 env->msr_hv_hypercall);
2967 }
2d384d7c 2968 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2969 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2970 env->msr_hv_tsc);
2971 }
2d384d7c 2972 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2973 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2974 env->msr_hv_reenlightenment_control);
2975 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2976 env->msr_hv_tsc_emulation_control);
2977 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2978 env->msr_hv_tsc_emulation_status);
2979 }
eab70139 2980 }
2d384d7c 2981 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2982 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2983 env->msr_hv_vapic);
eab70139 2984 }
f2a53c9e
AS		 2985 if (has_msr_hv_crash) {
2986 int j;
2987
5e953812 2988 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2989 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2990 env->msr_hv_crash_params[j]);
2991
5e953812 2992 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2993 }
46eb8f98 2994 if (has_msr_hv_runtime) {
9c600a84 2995 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2996 }
2d384d7c
VK		 2997 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2998 && hv_vpindex_settable) {
701189e3
RK		 2999 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
3000 hyperv_vp_index(CPU(cpu)));
e9688fab 3001 }
2d384d7c 3002 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3003 int j;
3004
09df29b6
RK		 3005 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
3006
9c600a84 3007 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 3008 env->msr_hv_synic_control);
9c600a84 3009 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 3010 env->msr_hv_synic_evt_page);
9c600a84 3011 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 3012 env->msr_hv_synic_msg_page);
3013
3014 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 3015 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 3016 env->msr_hv_synic_sint[j]);
3017 }
3018 }
ff99aa64
AS		 3019 if (has_msr_hv_stimer) {
3020 int j;
3021
3022 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 3023 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 3024 env->msr_hv_stimer_config[j]);
3025 }
3026
3027 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 3028 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 3029 env->msr_hv_stimer_count[j]);
3030 }
3031 }
1eabfce6 3032 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 3033 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
3034
9c600a84
EH		 3035 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
3036 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
3037 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
3038 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
3039 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
3040 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
3041 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
3042 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
3043 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
3044 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
3045 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
3046 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 3047 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 3048 /* The CPU GPs if we write to a bit above the physical limit of
3049 * the host CPU (and KVM emulates that)
3050 */
3051 uint64_t mask = env->mtrr_var[i].mask;
3052 mask &= phys_mask;
3053
9c600a84
EH		 3054 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
3055 env->mtrr_var[i].base);
112dad69 3056 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 3057 }
3058 }
b77146e9
CP		 3059 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3060 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
3061 0x14, 1, R_EAX) & 0x7;
3062
3063 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
3064 env->msr_rtit_ctrl);
3065 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
3066 env->msr_rtit_status);
3067 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
3068 env->msr_rtit_output_base);
3069 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
3070 env->msr_rtit_output_mask);
3071 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
3072 env->msr_rtit_cr3_match);
3073 for (i = 0; i < addr_num; i++) {
3074 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
3075 env->msr_rtit_addrs[i]);
3076 }
3077 }
6bdf863d
JK		 3078
3079 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
3080 * kvm_put_msr_feature_control. */
ea643051 3081 }
20a78b02 3082
57780495 3083 if (env->mcg_cap) {
d8da8574 3084 int i;
b9bec74b 3085
9c600a84
EH		 3086 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
3087 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 3088 if (has_msr_mcg_ext_ctl) {
3089 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3090 }
c34d440a 3091 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3092 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 3093 }
3094 }
1a03675d 3095
420ae1fc 3096 return kvm_buf_set_msrs(cpu);
05330448
AL		 3097}
3098
3099
1bc22652 3100static int kvm_get_fpu(X86CPU *cpu)
05330448 3101{
1bc22652 3102 CPUX86State *env = &cpu->env;
05330448
AL		 3103 struct kvm_fpu fpu;
3104 int i, ret;
3105
1bc22652 3106 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 3107 if (ret < 0) {
05330448 3108 return ret;
b9bec74b 3109 }
05330448
AL		 3110
3111 env->fpstt = (fpu.fsw >> 11) & 7;
3112 env->fpus = fpu.fsw;
3113 env->fpuc = fpu.fcw;
42cc8fa6
JK		 3114 env->fpop = fpu.last_opcode;
3115 env->fpip = fpu.last_ip;
3116 env->fpdp = fpu.last_dp;
b9bec74b
JK		 3117 for (i = 0; i < 8; ++i) {
3118 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3119 }
05330448 3120 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 3121 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 3122 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3123 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 3124 }
05330448
AL		 3125 env->mxcsr = fpu.mxcsr;
3126
3127 return 0;
3128}
3129
1bc22652 3130static int kvm_get_xsave(X86CPU *cpu)
f1665b21 3131{
1bc22652 3132 CPUX86State *env = &cpu->env;
5b8063c4 3133 X86XSaveArea *xsave = env->xsave_buf;
86a57621 3134 int ret;
f1665b21 3135
28143b40 3136 if (!has_xsave) {
1bc22652 3137 return kvm_get_fpu(cpu);
b9bec74b 3138 }
f1665b21 3139
1bc22652 3140 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 3141 if (ret < 0) {
f1665b21 3142 return ret;
0f53994f 3143 }
86a57621 3144 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 3145
f1665b21 3146 return 0;
f1665b21
SY		 3147}
3148
1bc22652 3149static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 3150{
1bc22652 3151 CPUX86State *env = &cpu->env;
f1665b21
SY		 3152 int i, ret;
3153 struct kvm_xcrs xcrs;
3154
28143b40 3155 if (!has_xcrs) {
f1665b21 3156 return 0;
b9bec74b 3157 }
f1665b21 3158
1bc22652 3159 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 3160 if (ret < 0) {
f1665b21 3161 return ret;
b9bec74b 3162 }
f1665b21 3163
b9bec74b 3164 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 3165 /* Only support xcr0 now */
0fd53fec
PB		 3166 if (xcrs.xcrs[i].xcr == 0) {
3167 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 3168 break;
3169 }
b9bec74b 3170 }
f1665b21 3171 return 0;
f1665b21
SY		 3172}
3173
1bc22652 3174static int kvm_get_sregs(X86CPU *cpu)
05330448 3175{
1bc22652 3176 CPUX86State *env = &cpu->env;
05330448 3177 struct kvm_sregs sregs;
0e607a80 3178 int bit, i, ret;
05330448 3179
1bc22652 3180 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 3181 if (ret < 0) {
05330448 3182 return ret;
b9bec74b 3183 }
05330448 3184
0e607a80
JK		 3185 /* There can only be one pending IRQ set in the bitmap at a time, so try
3186 to find it and save its number instead (-1 for none). */
3187 env->interrupt_injected = -1;
3188 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
3189 if (sregs.interrupt_bitmap[i]) {
3190 bit = ctz64(sregs.interrupt_bitmap[i]);
3191 env->interrupt_injected = i * 64 + bit;
3192 break;
3193 }
3194 }
05330448
AL		 3195
3196 get_seg(&env->segs[R_CS], &sregs.cs);
3197 get_seg(&env->segs[R_DS], &sregs.ds);
3198 get_seg(&env->segs[R_ES], &sregs.es);
3199 get_seg(&env->segs[R_FS], &sregs.fs);
3200 get_seg(&env->segs[R_GS], &sregs.gs);
3201 get_seg(&env->segs[R_SS], &sregs.ss);
3202
3203 get_seg(&env->tr, &sregs.tr);
3204 get_seg(&env->ldt, &sregs.ldt);
3205
3206 env->idt.limit = sregs.idt.limit;
3207 env->idt.base = sregs.idt.base;
3208 env->gdt.limit = sregs.gdt.limit;
3209 env->gdt.base = sregs.gdt.base;
3210
3211 env->cr[0] = sregs.cr0;
3212 env->cr[2] = sregs.cr2;
3213 env->cr[3] = sregs.cr3;
3214 env->cr[4] = sregs.cr4;
3215
05330448 3216 env->efer = sregs.efer;
cce47516
JK		 3217
3218 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 3219 x86_update_hflags(env);
05330448
AL		 3220
3221 return 0;
3222}
3223
1bc22652 3224static int kvm_get_msrs(X86CPU *cpu)
05330448 3225{
1bc22652 3226 CPUX86State *env = &cpu->env;
d71b62a1 3227 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 3228 int ret, i;
fcc35e7c 3229 uint64_t mtrr_top_bits;
05330448 3230
d71b62a1
EH		 3231 kvm_msr_buf_reset(cpu);
3232
9c600a84
EH		 3233 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3234 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3235 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3236 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 3237 if (has_msr_star) {
9c600a84 3238 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 3239 }
c3a3a7d3 3240 if (has_msr_hsave_pa) {
9c600a84 3241 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 3242 }
c9b8f6b6 3243 if (has_msr_tsc_aux) {
9c600a84 3244 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 3245 }
f28558d3 3246 if (has_msr_tsc_adjust) {
9c600a84 3247 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 3248 }
aa82ba54 3249 if (has_msr_tsc_deadline) {
9c600a84 3250 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 3251 }
21e87c46 3252 if (has_msr_misc_enable) {
9c600a84 3253 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 3254 }
fc12d72e 3255 if (has_msr_smbase) {
9c600a84 3256 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 3257 }
e13713db
LA		 3258 if (has_msr_smi_count) {
3259 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3260 }
df67696e 3261 if (has_msr_feature_control) {
9c600a84 3262 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 3263 }
6aa4228b
CQ		 3264 if (has_msr_pkrs) {
3265 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
3266 }
79e9ebeb 3267 if (has_msr_bndcfgs) {
9c600a84 3268 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 3269 }
18cd2c17 3270 if (has_msr_xss) {
9c600a84 3271 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 3272 }
65087997
TX		 3273 if (has_msr_umwait) {
3274 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3275 }
a33a2cfe
PB		 3276 if (has_msr_spec_ctrl) {
3277 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3278 }
2a9758c5
PB		 3279 if (has_msr_tsx_ctrl) {
3280 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3281 }
cfeea0c0
KRW		 3282 if (has_msr_virt_ssbd) {
3283 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3284 }
b8cc45d6 3285 if (!env->tsc_valid) {
9c600a84 3286 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 3287 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 3288 }
3289
05330448 3290#ifdef TARGET_X86_64
25d2e361 3291 if (lm_capable_kernel) {
9c600a84
EH		 3292 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3293 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3294 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3295 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 3296 }
05330448 3297#endif
9c600a84
EH		 3298 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3299 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
db5daafa
VK		 3300 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3301 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3302 }
6615be07
VK		 3303 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3304 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3305 }
55c911a5 3306 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3307 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 3308 }
55c911a5 3309 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3310 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 3311 }
d645e132
MT		 3312 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3313 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3314 }
0b368a10
JD		 3315 if (has_architectural_pmu_version > 0) {
3316 if (has_architectural_pmu_version > 1) {
3317 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3318 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3319 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3320 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3321 }
3322 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3323 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 3324 }
0b368a10 3325 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 3326 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3327 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 3328 }
3329 }
1a03675d 3330
57780495 3331 if (env->mcg_cap) {
9c600a84
EH		 3332 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3333 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 3334 if (has_msr_mcg_ext_ctl) {
3335 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3336 }
b9bec74b 3337 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3338 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 3339 }
57780495 3340 }
57780495 3341
1c90ef26 3342 if (has_msr_hv_hypercall) {
9c600a84
EH		 3343 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3344 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 3345 }
2d384d7c 3346 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3347 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 3348 }
2d384d7c 3349 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 3350 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 3351 }
2d384d7c 3352 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3353 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3354 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3355 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3356 }
f2a53c9e
AS		 3357 if (has_msr_hv_crash) {
3358 int j;
3359
5e953812 3360 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 3361 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 3362 }
3363 }
46eb8f98 3364 if (has_msr_hv_runtime) {
9c600a84 3365 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 3366 }
2d384d7c 3367 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3368 uint32_t msr;
3369
9c600a84 3370 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 3371 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3372 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 3373 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 3374 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 3375 }
3376 }
ff99aa64
AS		 3377 if (has_msr_hv_stimer) {
3378 uint32_t msr;
3379
3380 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3381 msr++) {
9c600a84 3382 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 3383 }
3384 }
1eabfce6 3385 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 3386 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3387 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3388 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3389 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3390 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3391 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3392 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3393 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3394 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3395 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3396 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3397 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 3398 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 3399 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3400 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 3401 }
3402 }
5ef68987 3403
b77146e9
CP		 3404 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3405 int addr_num =
3406 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3407
3408 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3409 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3410 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3411 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3412 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3413 for (i = 0; i < addr_num; i++) {
3414 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3415 }
3416 }
3417
d71b62a1 3418 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 3419 if (ret < 0) {
05330448 3420 return ret;
b9bec74b 3421 }
05330448 3422
c70b11d1
EH		 3423 if (ret < cpu->kvm_msr_buf->nmsrs) {
3424 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3425 error_report("error: failed to get MSR 0x%" PRIx32,
3426 (uint32_t)e->index);
3427 }
3428
9c600a84 3429 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 3430 /*
3431 * MTRR masks: Each mask consists of 5 parts
3432 * a 10..0: must be zero
3433 * b 11 : valid bit
3434 * c n-1.12: actual mask bits
3435 * d 51..n: reserved must be zero
3436 * e 63.52: reserved must be zero
3437 *
3438 * 'n' is the number of physical bits supported by the CPU and is
3439 * apparently always <= 52. We know our 'n' but don't know what
3440 * the destinations 'n' is; it might be smaller, in which case
3441 * it masks (c) on loading. It might be larger, in which case
3442 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3443 * we're migrating to.
3444 */
3445
3446 if (cpu->fill_mtrr_mask) {
3447 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3448 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3449 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3450 } else {
3451 mtrr_top_bits = 0;
3452 }
3453
05330448 3454 for (i = 0; i < ret; i++) {
0d894367
PB		 3455 uint32_t index = msrs[i].index;
3456 switch (index) {
05330448
AL		 3457 case MSR_IA32_SYSENTER_CS:
3458 env->sysenter_cs = msrs[i].data;
3459 break;
3460 case MSR_IA32_SYSENTER_ESP:
3461 env->sysenter_esp = msrs[i].data;
3462 break;
3463 case MSR_IA32_SYSENTER_EIP:
3464 env->sysenter_eip = msrs[i].data;
3465 break;
0c03266a
JK		 3466 case MSR_PAT:
3467 env->pat = msrs[i].data;
3468 break;
05330448
AL		 3469 case MSR_STAR:
3470 env->star = msrs[i].data;
3471 break;
3472#ifdef TARGET_X86_64
3473 case MSR_CSTAR:
3474 env->cstar = msrs[i].data;
3475 break;
3476 case MSR_KERNELGSBASE:
3477 env->kernelgsbase = msrs[i].data;
3478 break;
3479 case MSR_FMASK:
3480 env->fmask = msrs[i].data;
3481 break;
3482 case MSR_LSTAR:
3483 env->lstar = msrs[i].data;
3484 break;
3485#endif
3486 case MSR_IA32_TSC:
3487 env->tsc = msrs[i].data;
3488 break;
c9b8f6b6
AS		 3489 case MSR_TSC_AUX:
3490 env->tsc_aux = msrs[i].data;
3491 break;
f28558d3
WA		 3492 case MSR_TSC_ADJUST:
3493 env->tsc_adjust = msrs[i].data;
3494 break;
aa82ba54
LJ		 3495 case MSR_IA32_TSCDEADLINE:
3496 env->tsc_deadline = msrs[i].data;
3497 break;
aa851e36
MT		 3498 case MSR_VM_HSAVE_PA:
3499 env->vm_hsave = msrs[i].data;
3500 break;
1a03675d
GC		 3501 case MSR_KVM_SYSTEM_TIME:
3502 env->system_time_msr = msrs[i].data;
3503 break;
3504 case MSR_KVM_WALL_CLOCK:
3505 env->wall_clock_msr = msrs[i].data;
3506 break;
57780495
MT		 3507 case MSR_MCG_STATUS:
3508 env->mcg_status = msrs[i].data;
3509 break;
3510 case MSR_MCG_CTL:
3511 env->mcg_ctl = msrs[i].data;
3512 break;
87f8b626
AR		 3513 case MSR_MCG_EXT_CTL:
3514 env->mcg_ext_ctl = msrs[i].data;
3515 break;
21e87c46
AK		 3516 case MSR_IA32_MISC_ENABLE:
3517 env->msr_ia32_misc_enable = msrs[i].data;
3518 break;
fc12d72e
PB		 3519 case MSR_IA32_SMBASE:
3520 env->smbase = msrs[i].data;
3521 break;
e13713db
LA		 3522 case MSR_SMI_COUNT:
3523 env->msr_smi_count = msrs[i].data;
3524 break;
0779caeb
ACL		 3525 case MSR_IA32_FEATURE_CONTROL:
3526 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3527 break;
79e9ebeb
LJ		 3528 case MSR_IA32_BNDCFGS:
3529 env->msr_bndcfgs = msrs[i].data;
3530 break;
18cd2c17
WL		 3531 case MSR_IA32_XSS:
3532 env->xss = msrs[i].data;
3533 break;
65087997
TX		 3534 case MSR_IA32_UMWAIT_CONTROL:
3535 env->umwait = msrs[i].data;
3536 break;
6aa4228b
CQ		 3537 case MSR_IA32_PKRS:
3538 env->pkrs = msrs[i].data;
3539 break;
57780495 3540 default:
57780495
MT		 3541 if (msrs[i].index >= MSR_MC0_CTL &&
3542 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3543 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3544 }
d8da8574 3545 break;
f6584ee2
GN		 3546 case MSR_KVM_ASYNC_PF_EN:
3547 env->async_pf_en_msr = msrs[i].data;
3548 break;
db5daafa
VK		 3549 case MSR_KVM_ASYNC_PF_INT:
3550 env->async_pf_int_msr = msrs[i].data;
3551 break;
bc9a839d
MT		 3552 case MSR_KVM_PV_EOI_EN:
3553 env->pv_eoi_en_msr = msrs[i].data;
3554 break;
917367aa
MT		 3555 case MSR_KVM_STEAL_TIME:
3556 env->steal_time_msr = msrs[i].data;
3557 break;
d645e132
MT		 3558 case MSR_KVM_POLL_CONTROL: {
3559 env->poll_control_msr = msrs[i].data;
3560 break;
3561 }
0d894367
PB		 3562 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3563 env->msr_fixed_ctr_ctrl = msrs[i].data;
3564 break;
3565 case MSR_CORE_PERF_GLOBAL_CTRL:
3566 env->msr_global_ctrl = msrs[i].data;
3567 break;
3568 case MSR_CORE_PERF_GLOBAL_STATUS:
3569 env->msr_global_status = msrs[i].data;
3570 break;
3571 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3572 env->msr_global_ovf_ctrl = msrs[i].data;
3573 break;
3574 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3575 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3576 break;
3577 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3578 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3579 break;
3580 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3581 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3582 break;
1c90ef26
VR		 3583 case HV_X64_MSR_HYPERCALL:
3584 env->msr_hv_hypercall = msrs[i].data;
3585 break;
3586 case HV_X64_MSR_GUEST_OS_ID:
3587 env->msr_hv_guest_os_id = msrs[i].data;
3588 break;
5ef68987
VR		 3589 case HV_X64_MSR_APIC_ASSIST_PAGE:
3590 env->msr_hv_vapic = msrs[i].data;
3591 break;
48a5f3bc
VR		 3592 case HV_X64_MSR_REFERENCE_TSC:
3593 env->msr_hv_tsc = msrs[i].data;
3594 break;
f2a53c9e
AS		 3595 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3596 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3597 break;
46eb8f98
AS		 3598 case HV_X64_MSR_VP_RUNTIME:
3599 env->msr_hv_runtime = msrs[i].data;
3600 break;
866eea9a
AS		 3601 case HV_X64_MSR_SCONTROL:
3602 env->msr_hv_synic_control = msrs[i].data;
3603 break;
866eea9a
AS		 3604 case HV_X64_MSR_SIEFP:
3605 env->msr_hv_synic_evt_page = msrs[i].data;
3606 break;
3607 case HV_X64_MSR_SIMP:
3608 env->msr_hv_synic_msg_page = msrs[i].data;
3609 break;
3610 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3611 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3612 break;
3613 case HV_X64_MSR_STIMER0_CONFIG:
3614 case HV_X64_MSR_STIMER1_CONFIG:
3615 case HV_X64_MSR_STIMER2_CONFIG:
3616 case HV_X64_MSR_STIMER3_CONFIG:
3617 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3618 msrs[i].data;
3619 break;
3620 case HV_X64_MSR_STIMER0_COUNT:
3621 case HV_X64_MSR_STIMER1_COUNT:
3622 case HV_X64_MSR_STIMER2_COUNT:
3623 case HV_X64_MSR_STIMER3_COUNT:
3624 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3625 msrs[i].data;
866eea9a 3626 break;
ba6a4fd9
VK		 3627 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3628 env->msr_hv_reenlightenment_control = msrs[i].data;
3629 break;
3630 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3631 env->msr_hv_tsc_emulation_control = msrs[i].data;
3632 break;
3633 case HV_X64_MSR_TSC_EMULATION_STATUS:
3634 env->msr_hv_tsc_emulation_status = msrs[i].data;
3635 break;
d1ae67f6
AW		 3636 case MSR_MTRRdefType:
3637 env->mtrr_deftype = msrs[i].data;
3638 break;
3639 case MSR_MTRRfix64K_00000:
3640 env->mtrr_fixed[0] = msrs[i].data;
3641 break;
3642 case MSR_MTRRfix16K_80000:
3643 env->mtrr_fixed[1] = msrs[i].data;
3644 break;
3645 case MSR_MTRRfix16K_A0000:
3646 env->mtrr_fixed[2] = msrs[i].data;
3647 break;
3648 case MSR_MTRRfix4K_C0000:
3649 env->mtrr_fixed[3] = msrs[i].data;
3650 break;
3651 case MSR_MTRRfix4K_C8000:
3652 env->mtrr_fixed[4] = msrs[i].data;
3653 break;
3654 case MSR_MTRRfix4K_D0000:
3655 env->mtrr_fixed[5] = msrs[i].data;
3656 break;
3657 case MSR_MTRRfix4K_D8000:
3658 env->mtrr_fixed[6] = msrs[i].data;
3659 break;
3660 case MSR_MTRRfix4K_E0000:
3661 env->mtrr_fixed[7] = msrs[i].data;
3662 break;
3663 case MSR_MTRRfix4K_E8000:
3664 env->mtrr_fixed[8] = msrs[i].data;
3665 break;
3666 case MSR_MTRRfix4K_F0000:
3667 env->mtrr_fixed[9] = msrs[i].data;
3668 break;
3669 case MSR_MTRRfix4K_F8000:
3670 env->mtrr_fixed[10] = msrs[i].data;
3671 break;
3672 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3673 if (index & 1) {
fcc35e7c
DDAG		 3674 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3675 mtrr_top_bits;
d1ae67f6
AW		 3676 } else {
3677 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3678 }
3679 break;
a33a2cfe
PB		 3680 case MSR_IA32_SPEC_CTRL:
3681 env->spec_ctrl = msrs[i].data;
3682 break;
2a9758c5
PB		 3683 case MSR_IA32_TSX_CTRL:
3684 env->tsx_ctrl = msrs[i].data;
3685 break;
cfeea0c0
KRW		 3686 case MSR_VIRT_SSBD:
3687 env->virt_ssbd = msrs[i].data;
3688 break;
b77146e9
CP		 3689 case MSR_IA32_RTIT_CTL:
3690 env->msr_rtit_ctrl = msrs[i].data;
3691 break;
3692 case MSR_IA32_RTIT_STATUS:
3693 env->msr_rtit_status = msrs[i].data;
3694 break;
3695 case MSR_IA32_RTIT_OUTPUT_BASE:
3696 env->msr_rtit_output_base = msrs[i].data;
3697 break;
3698 case MSR_IA32_RTIT_OUTPUT_MASK:
3699 env->msr_rtit_output_mask = msrs[i].data;
3700 break;
3701 case MSR_IA32_RTIT_CR3_MATCH:
3702 env->msr_rtit_cr3_match = msrs[i].data;
3703 break;
3704 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3705 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3706 break;
05330448
AL		 3707 }
3708 }
3709
3710 return 0;
3711}
3712
1bc22652 3713static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3714{
1bc22652 3715 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3716
1bc22652 3717 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3718}
3719
23d02d9b 3720static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3721{
259186a7 3722 CPUState *cs = CPU(cpu);
23d02d9b 3723 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3724 struct kvm_mp_state mp_state;
3725 int ret;
3726
259186a7 3727 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3728 if (ret < 0) {
3729 return ret;
3730 }
3731 env->mp_state = mp_state.mp_state;
c14750e8 3732 if (kvm_irqchip_in_kernel()) {
259186a7 3733 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3734 }
9bdbe550
HB		 3735 return 0;
3736}
3737
1bc22652 3738static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3739{
02e51483 3740 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3741 struct kvm_lapic_state kapic;
3742 int ret;
3743
3d4b2649 3744 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3745 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3746 if (ret < 0) {
3747 return ret;
3748 }
3749
3750 kvm_get_apic_state(apic, &kapic);
3751 }
3752 return 0;
3753}
3754
1bc22652 3755static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3756{
fc12d72e 3757 CPUState *cs = CPU(cpu);
1bc22652 3758 CPUX86State *env = &cpu->env;
076796f8 3759 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3760
3761 if (!kvm_has_vcpu_events()) {
3762 return 0;
3763 }
3764
fd13f23b
LA		 3765 events.flags = 0;
3766
3767 if (has_exception_payload) {
3768 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3769 events.exception.pending = env->exception_pending;
3770 events.exception_has_payload = env->exception_has_payload;
3771 events.exception_payload = env->exception_payload;
3772 }
3773 events.exception.nr = env->exception_nr;
3774 events.exception.injected = env->exception_injected;
a0fb002c
JK		 3775 events.exception.has_error_code = env->has_error_code;
3776 events.exception.error_code = env->error_code;
3777
3778 events.interrupt.injected = (env->interrupt_injected >= 0);
3779 events.interrupt.nr = env->interrupt_injected;
3780 events.interrupt.soft = env->soft_interrupt;
3781
3782 events.nmi.injected = env->nmi_injected;
3783 events.nmi.pending = env->nmi_pending;
3784 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3785
3786 events.sipi_vector = env->sipi_vector;
3787
fc12d72e
PB		 3788 if (has_msr_smbase) {
3789 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3790 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3791 if (kvm_irqchip_in_kernel()) {
3792 /* As soon as these are moved to the kernel, remove them
3793 * from cs->interrupt_request.
3794 */
3795 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3796 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3797 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3798 } else {
3799 /* Keep these in cs->interrupt_request. */
3800 events.smi.pending = 0;
3801 events.smi.latched_init = 0;
3802 }
fc3a1fd7
DDAG		 3803 /* Stop SMI delivery on old machine types to avoid a reboot
3804 * on an inward migration of an old VM.
3805 */
3806 if (!cpu->kvm_no_smi_migration) {
3807 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3808 }
fc12d72e
PB		 3809 }
3810
ea643051 3811 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3812 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3813 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3814 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3815 }
ea643051 3816 }
aee028b9 3817
1bc22652 3818 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3819}
3820
1bc22652 3821static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3822{
1bc22652 3823 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3824 struct kvm_vcpu_events events;
3825 int ret;
3826
3827 if (!kvm_has_vcpu_events()) {
3828 return 0;
3829 }
3830
fc12d72e 3831 memset(&events, 0, sizeof(events));
1bc22652 3832 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3833 if (ret < 0) {
3834 return ret;
3835 }
fd13f23b
LA		 3836
3837 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3838 env->exception_pending = events.exception.pending;
3839 env->exception_has_payload = events.exception_has_payload;
3840 env->exception_payload = events.exception_payload;
3841 } else {
3842 env->exception_pending = 0;
3843 env->exception_has_payload = false;
3844 }
3845 env->exception_injected = events.exception.injected;
3846 env->exception_nr =
3847 (env->exception_pending || env->exception_injected) ?
3848 events.exception.nr : -1;
a0fb002c
JK		 3849 env->has_error_code = events.exception.has_error_code;
3850 env->error_code = events.exception.error_code;
3851
3852 env->interrupt_injected =
3853 events.interrupt.injected ? events.interrupt.nr : -1;
3854 env->soft_interrupt = events.interrupt.soft;
3855
3856 env->nmi_injected = events.nmi.injected;
3857 env->nmi_pending = events.nmi.pending;
3858 if (events.nmi.masked) {
3859 env->hflags2 |= HF2_NMI_MASK;
3860 } else {
3861 env->hflags2 &= ~HF2_NMI_MASK;
3862 }
3863
fc12d72e
PB		 3864 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3865 if (events.smi.smm) {
3866 env->hflags |= HF_SMM_MASK;
3867 } else {
3868 env->hflags &= ~HF_SMM_MASK;
3869 }
3870 if (events.smi.pending) {
3871 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3872 } else {
3873 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3874 }
3875 if (events.smi.smm_inside_nmi) {
3876 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3877 } else {
3878 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3879 }
3880 if (events.smi.latched_init) {
3881 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3882 } else {
3883 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3884 }
3885 }
3886
a0fb002c 3887 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3888
3889 return 0;
3890}
3891
1bc22652 3892static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3893{
ed2803da 3894 CPUState *cs = CPU(cpu);
1bc22652 3895 CPUX86State *env = &cpu->env;
b0b1d690 3896 int ret = 0;
b0b1d690
JK		 3897 unsigned long reinject_trap = 0;
3898
3899 if (!kvm_has_vcpu_events()) {
fd13f23b 3900 if (env->exception_nr == EXCP01_DB) {
b0b1d690 3901 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 3902 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 3903 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3904 }
fd13f23b 3905 kvm_reset_exception(env);
b0b1d690
JK		 3906 }
3907
3908 /*
3909 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3910 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3911 * by updating the debug state once again if single-stepping is on.
3912 * Another reason to call kvm_update_guest_debug here is a pending debug
3913 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3914 * reinject them via SET_GUEST_DEBUG.
3915 */
3916 if (reinject_trap ||
ed2803da 3917 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3918 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3919 }
b0b1d690
JK		 3920 return ret;
3921}
3922
1bc22652 3923static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3924{
1bc22652 3925 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3926 struct kvm_debugregs dbgregs;
3927 int i;
3928
3929 if (!kvm_has_debugregs()) {
3930 return 0;
3931 }
3932
1f670a95 3933 memset(&dbgregs, 0, sizeof(dbgregs));
ff44f1a3
JK		 3934 for (i = 0; i < 4; i++) {
3935 dbgregs.db[i] = env->dr[i];
3936 }
3937 dbgregs.dr6 = env->dr[6];
3938 dbgregs.dr7 = env->dr[7];
3939 dbgregs.flags = 0;
3940
1bc22652 3941 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3942}
3943
1bc22652 3944static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3945{
1bc22652 3946 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3947 struct kvm_debugregs dbgregs;
3948 int i, ret;
3949
3950 if (!kvm_has_debugregs()) {
3951 return 0;
3952 }
3953
1bc22652 3954 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3955 if (ret < 0) {
b9bec74b 3956 return ret;
ff44f1a3
JK		 3957 }
3958 for (i = 0; i < 4; i++) {
3959 env->dr[i] = dbgregs.db[i];
3960 }
3961 env->dr[4] = env->dr[6] = dbgregs.dr6;
3962 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3963
3964 return 0;
3965}
3966
ebbfef2f
LA		 3967static int kvm_put_nested_state(X86CPU *cpu)
3968{
3969 CPUX86State *env = &cpu->env;
3970 int max_nested_state_len = kvm_max_nested_state_length();
3971
1e44f3ab 3972 if (!env->nested_state) {
ebbfef2f
LA		 3973 return 0;
3974 }
3975
b16c0e20
PB		 3976 /*
3977 * Copy flags that are affected by reset from env->hflags and env->hflags2.
3978 */
3979 if (env->hflags & HF_GUEST_MASK) {
3980 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
3981 } else {
3982 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
3983 }
0baa4b44
VK		 3984
3985 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
3986 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
b16c0e20
PB		 3987 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
3988 } else {
3989 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
3990 }
3991
ebbfef2f
LA		 3992 assert(env->nested_state->size <= max_nested_state_len);
3993 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3994}
3995
3996static int kvm_get_nested_state(X86CPU *cpu)
3997{
3998 CPUX86State *env = &cpu->env;
3999 int max_nested_state_len = kvm_max_nested_state_length();
4000 int ret;
4001
1e44f3ab 4002 if (!env->nested_state) {
ebbfef2f
LA		 4003 return 0;
4004 }
4005
4006 /*
4007 * It is possible that migration restored a smaller size into
4008 * nested_state->hdr.size than what our kernel support.
4009 * We preserve migration origin nested_state->hdr.size for
4010 * call to KVM_SET_NESTED_STATE but wish that our next call
4011 * to KVM_GET_NESTED_STATE will use max size our kernel support.
4012 */
4013 env->nested_state->size = max_nested_state_len;
4014
4015 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
4016 if (ret < 0) {
4017 return ret;
4018 }
4019
b16c0e20
PB		 4020 /*
4021 * Copy flags that are affected by reset to env->hflags and env->hflags2.
4022 */
ebbfef2f
LA		 4023 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
4024 env->hflags |= HF_GUEST_MASK;
4025 } else {
4026 env->hflags &= ~HF_GUEST_MASK;
4027 }
0baa4b44
VK		 4028
4029 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
4030 if (cpu_has_svm(env)) {
4031 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
4032 env->hflags2 |= HF2_GIF_MASK;
4033 } else {
4034 env->hflags2 &= ~HF2_GIF_MASK;
4035 }
b16c0e20 4036 }
ebbfef2f
LA		 4037
4038 return ret;
4039}
4040
20d695a9 4041int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 4042{
20d695a9 4043 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 4044 int ret;
4045
2fa45344 4046 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 4047
b16c0e20
PB		 4048 /* must be before kvm_put_nested_state so that EFER.SVME is set */
4049 ret = kvm_put_sregs(x86_cpu);
4050 if (ret < 0) {
4051 return ret;
4052 }
4053
48e1a45c 4054 if (level >= KVM_PUT_RESET_STATE) {
bec7156a
JK		 4055 ret = kvm_put_nested_state(x86_cpu);
4056 if (ret < 0) {
4057 return ret;
4058 }
4059
6bdf863d
JK		 4060 ret = kvm_put_msr_feature_control(x86_cpu);
4061 if (ret < 0) {
4062 return ret;
4063 }
4064 }
4065
36f96c4b
HZ		 4066 if (level == KVM_PUT_FULL_STATE) {
4067 /* We don't check for kvm_arch_set_tsc_khz() errors here,
4068 * because TSC frequency mismatch shouldn't abort migration,
4069 * unless the user explicitly asked for a more strict TSC
4070 * setting (e.g. using an explicit "tsc-freq" option).
4071 */
4072 kvm_arch_set_tsc_khz(cpu);
4073 }
4074
1bc22652 4075 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 4076 if (ret < 0) {
05330448 4077 return ret;
b9bec74b 4078 }
1bc22652 4079 ret = kvm_put_xsave(x86_cpu);
b9bec74b 4080 if (ret < 0) {
f1665b21 4081 return ret;
b9bec74b 4082 }
1bc22652 4083 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 4084 if (ret < 0) {
05330448 4085 return ret;
b9bec74b 4086 }
ab443475 4087 /* must be before kvm_put_msrs */
1bc22652 4088 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 4089 if (ret < 0) {
4090 return ret;
4091 }
1bc22652 4092 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 4093 if (ret < 0) {
05330448 4094 return ret;
b9bec74b 4095 }
4fadfa00
PH		 4096 ret = kvm_put_vcpu_events(x86_cpu, level);
4097 if (ret < 0) {
4098 return ret;
4099 }
ea643051 4100 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 4101 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 4102 if (ret < 0) {
680c1c6f
JK		 4103 return ret;
4104 }
ea643051 4105 }
7477cd38
MT		 4106
4107 ret = kvm_put_tscdeadline_msr(x86_cpu);
4108 if (ret < 0) {
4109 return ret;
4110 }
1bc22652 4111 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 4112 if (ret < 0) {
b0b1d690 4113 return ret;
b9bec74b 4114 }
b0b1d690 4115 /* must be last */
1bc22652 4116 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 4117 if (ret < 0) {
ff44f1a3 4118 return ret;
b9bec74b 4119 }
05330448
AL		 4120 return 0;
4121}
4122
20d695a9 4123int kvm_arch_get_registers(CPUState *cs)
05330448 4124{
20d695a9 4125 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 4126 int ret;
4127
20d695a9 4128 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 4129
4fadfa00 4130 ret = kvm_get_vcpu_events(cpu);
b9bec74b 4131 if (ret < 0) {
f4f1110e 4132 goto out;
b9bec74b 4133 }
4fadfa00
PH		 4134 /*
4135 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4136 * KVM_GET_REGS and KVM_GET_SREGS.
4137 */
4138 ret = kvm_get_mp_state(cpu);
b9bec74b 4139 if (ret < 0) {
f4f1110e 4140 goto out;
b9bec74b 4141 }
4fadfa00 4142 ret = kvm_getput_regs(cpu, 0);
b9bec74b 4143 if (ret < 0) {
f4f1110e 4144 goto out;
b9bec74b 4145 }
4fadfa00 4146 ret = kvm_get_xsave(cpu);
b9bec74b 4147 if (ret < 0) {
f4f1110e 4148 goto out;
b9bec74b 4149 }
4fadfa00 4150 ret = kvm_get_xcrs(cpu);
b9bec74b 4151 if (ret < 0) {
f4f1110e 4152 goto out;
b9bec74b 4153 }
4fadfa00 4154 ret = kvm_get_sregs(cpu);
b9bec74b 4155 if (ret < 0) {
f4f1110e 4156 goto out;
b9bec74b 4157 }
4fadfa00 4158 ret = kvm_get_msrs(cpu);
680c1c6f 4159 if (ret < 0) {
f4f1110e 4160 goto out;
680c1c6f 4161 }
4fadfa00 4162 ret = kvm_get_apic(cpu);
b9bec74b 4163 if (ret < 0) {
f4f1110e 4164 goto out;
b9bec74b 4165 }
1bc22652 4166 ret = kvm_get_debugregs(cpu);
b9bec74b 4167 if (ret < 0) {
f4f1110e 4168 goto out;
b9bec74b 4169 }
ebbfef2f
LA		 4170 ret = kvm_get_nested_state(cpu);
4171 if (ret < 0) {
4172 goto out;
4173 }
f4f1110e
RH		 4174 ret = 0;
4175 out:
4176 cpu_sync_bndcs_hflags(&cpu->env);
4177 return ret;
05330448
AL		 4178}
4179
20d695a9 4180void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 4181{
20d695a9
AF		 4182 X86CPU *x86_cpu = X86_CPU(cpu);
4183 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 4184 int ret;
4185
276ce815 4186 /* Inject NMI */
fc12d72e
PB		 4187 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4188 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4189 qemu_mutex_lock_iothread();
4190 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4191 qemu_mutex_unlock_iothread();
4192 DPRINTF("injected NMI\n");
4193 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4194 if (ret < 0) {
4195 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4196 strerror(-ret));
4197 }
4198 }
4199 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4200 qemu_mutex_lock_iothread();
4201 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4202 qemu_mutex_unlock_iothread();
4203 DPRINTF("injected SMI\n");
4204 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4205 if (ret < 0) {
4206 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4207 strerror(-ret));
4208 }
ce377af3 4209 }
276ce815
LJ		 4210 }
4211
15eafc2e 4212 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 4213 qemu_mutex_lock_iothread();
4214 }
4215
e0723c45
PB		 4216 /* Force the VCPU out of its inner loop to process any INIT requests
4217 * or (for userspace APIC, but it is cheap to combine the checks here)
4218 * pending TPR access reports.
4219 */
4220 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 4221 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4222 !(env->hflags & HF_SMM_MASK)) {
4223 cpu->exit_request = 1;
4224 }
4225 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4226 cpu->exit_request = 1;
4227 }
e0723c45 4228 }
05330448 4229
15eafc2e 4230 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 4231 /* Try to inject an interrupt if the guest can accept it */
4232 if (run->ready_for_interrupt_injection &&
259186a7 4233 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 4234 (env->eflags & IF_MASK)) {
4235 int irq;
4236
259186a7 4237 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 4238 irq = cpu_get_pic_interrupt(env);
4239 if (irq >= 0) {
4240 struct kvm_interrupt intr;
4241
4242 intr.irq = irq;
db1669bc 4243 DPRINTF("injected interrupt %d\n", irq);
1bc22652 4244 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 4245 if (ret < 0) {
4246 fprintf(stderr,
4247 "KVM: injection failed, interrupt lost (%s)\n",
4248 strerror(-ret));
4249 }
db1669bc
JK		 4250 }
4251 }
05330448 4252
db1669bc
JK		 4253 /* If we have an interrupt but the guest is not ready to receive an
4254 * interrupt, request an interrupt window exit. This will
4255 * cause a return to userspace as soon as the guest is ready to
4256 * receive interrupts. */
259186a7 4257 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 4258 run->request_interrupt_window = 1;
4259 } else {
4260 run->request_interrupt_window = 0;
4261 }
4262
4263 DPRINTF("setting tpr\n");
02e51483 4264 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 4265
4266 qemu_mutex_unlock_iothread();
db1669bc 4267 }
05330448
AL		 4268}
4269
4c663752 4270MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 4271{
20d695a9
AF		 4272 X86CPU *x86_cpu = X86_CPU(cpu);
4273 CPUX86State *env = &x86_cpu->env;
4274
fc12d72e
PB		 4275 if (run->flags & KVM_RUN_X86_SMM) {
4276 env->hflags |= HF_SMM_MASK;
4277 } else {
f5c052b9 4278 env->hflags &= ~HF_SMM_MASK;
fc12d72e 4279 }
b9bec74b 4280 if (run->if_flag) {
05330448 4281 env->eflags |= IF_MASK;
b9bec74b 4282 } else {
05330448 4283 env->eflags &= ~IF_MASK;
b9bec74b 4284 }
4b8523ee
JK		 4285
4286 /* We need to protect the apic state against concurrent accesses from
4287 * different threads in case the userspace irqchip is used. */
4288 if (!kvm_irqchip_in_kernel()) {
4289 qemu_mutex_lock_iothread();
4290 }
02e51483
CF		 4291 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4292 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 4293 if (!kvm_irqchip_in_kernel()) {
4294 qemu_mutex_unlock_iothread();
4295 }
f794aa4a 4296 return cpu_get_mem_attrs(env);
05330448
AL		 4297}
4298
20d695a9 4299int kvm_arch_process_async_events(CPUState *cs)
0af691d7 4300{
20d695a9
AF		 4301 X86CPU *cpu = X86_CPU(cs);
4302 CPUX86State *env = &cpu->env;
232fc23b 4303
259186a7 4304 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 4305 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4306 assert(env->mcg_cap);
4307
259186a7 4308 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 4309
dd1750d7 4310 kvm_cpu_synchronize_state(cs);
ab443475 4311
fd13f23b 4312 if (env->exception_nr == EXCP08_DBLE) {
ab443475 4313 /* this means triple fault */
cf83f140 4314 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 4315 cs->exit_request = 1;
ab443475
JK		 4316 return 0;
4317 }
fd13f23b 4318 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 4319 env->has_error_code = 0;
4320
259186a7 4321 cs->halted = 0;
ab443475
JK		 4322 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4323 env->mp_state = KVM_MP_STATE_RUNNABLE;
4324 }
4325 }
4326
fc12d72e
PB		 4327 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4328 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 4329 kvm_cpu_synchronize_state(cs);
4330 do_cpu_init(cpu);
4331 }
4332
db1669bc
JK		 4333 if (kvm_irqchip_in_kernel()) {
4334 return 0;
4335 }
4336
259186a7
AF		 4337 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4338 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 4339 apic_poll_irq(cpu->apic_state);
5d62c43a 4340 }
259186a7 4341 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 4342 (env->eflags & IF_MASK)) ||
259186a7
AF		 4343 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4344 cs->halted = 0;
6792a57b 4345 }
259186a7 4346 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 4347 kvm_cpu_synchronize_state(cs);
232fc23b 4348 do_cpu_sipi(cpu);
0af691d7 4349 }
259186a7
AF		 4350 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4351 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 4352 kvm_cpu_synchronize_state(cs);
02e51483 4353 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 4354 env->tpr_access_type);
4355 }
0af691d7 4356
259186a7 4357 return cs->halted;
0af691d7
MT		 4358}
4359
839b5630 4360static int kvm_handle_halt(X86CPU *cpu)
05330448 4361{
259186a7 4362 CPUState *cs = CPU(cpu);
839b5630
AF		 4363 CPUX86State *env = &cpu->env;
4364
259186a7 4365 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 4366 (env->eflags & IF_MASK)) &&
259186a7
AF		 4367 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4368 cs->halted = 1;
bb4ea393 4369 return EXCP_HLT;
05330448
AL		 4370 }
4371
bb4ea393 4372 return 0;
05330448
AL		 4373}
4374
f7575c96 4375static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 4376{
f7575c96
AF		 4377 CPUState *cs = CPU(cpu);
4378 struct kvm_run *run = cs->kvm_run;
d362e757 4379
02e51483 4380 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 4381 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4382 : TPR_ACCESS_READ);
4383 return 1;
4384}
4385
f17ec444 4386int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 4387{
38972938 4388 static const uint8_t int3 = 0xcc;
64bf3f4e 4389
f17ec444
AF		 4390 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4391 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 4392 return -EINVAL;
b9bec74b 4393 }
e22a25c9
AL		 4394 return 0;
4395}
4396
f17ec444 4397int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 4398{
4399 uint8_t int3;
4400
c6986f16
PB		 4401 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
4402 return -EINVAL;
4403 }
4404 if (int3 != 0xcc) {
4405 return 0;
4406 }
4407 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 4408 return -EINVAL;
b9bec74b 4409 }
e22a25c9
AL		 4410 return 0;
4411}
4412
4413static struct {
4414 target_ulong addr;
4415 int len;
4416 int type;
4417} hw_breakpoint[4];
4418
4419static int nb_hw_breakpoint;
4420
4421static int find_hw_breakpoint(target_ulong addr, int len, int type)
4422{
4423 int n;
4424
b9bec74b 4425 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 4426 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 4427 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 4428 return n;
b9bec74b
JK		 4429 }
4430 }
e22a25c9
AL		 4431 return -1;
4432}
4433
4434int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4435 target_ulong len, int type)
4436{
4437 switch (type) {
4438 case GDB_BREAKPOINT_HW:
4439 len = 1;
4440 break;
4441 case GDB_WATCHPOINT_WRITE:
4442 case GDB_WATCHPOINT_ACCESS:
4443 switch (len) {
4444 case 1:
4445 break;
4446 case 2:
4447 case 4:
4448 case 8:
b9bec74b 4449 if (addr & (len - 1)) {
e22a25c9 4450 return -EINVAL;
b9bec74b 4451 }
e22a25c9
AL		 4452 break;
4453 default:
4454 return -EINVAL;
4455 }
4456 break;
4457 default:
4458 return -ENOSYS;
4459 }
4460
b9bec74b 4461 if (nb_hw_breakpoint == 4) {
e22a25c9 4462 return -ENOBUFS;
b9bec74b
JK		 4463 }
4464 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 4465 return -EEXIST;
b9bec74b 4466 }
e22a25c9
AL		 4467 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4468 hw_breakpoint[nb_hw_breakpoint].len = len;
4469 hw_breakpoint[nb_hw_breakpoint].type = type;
4470 nb_hw_breakpoint++;
4471
4472 return 0;
4473}
4474
4475int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4476 target_ulong len, int type)
4477{
4478 int n;
4479
4480 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 4481 if (n < 0) {
e22a25c9 4482 return -ENOENT;
b9bec74b 4483 }
e22a25c9
AL		 4484 nb_hw_breakpoint--;
4485 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4486
4487 return 0;
4488}
4489
4490void kvm_arch_remove_all_hw_breakpoints(void)
4491{
4492 nb_hw_breakpoint = 0;
4493}
4494
4495static CPUWatchpoint hw_watchpoint;
4496
a60f24b5 4497static int kvm_handle_debug(X86CPU *cpu,
48405526 4498 struct kvm_debug_exit_arch *arch_info)
e22a25c9 4499{
ed2803da 4500 CPUState *cs = CPU(cpu);
a60f24b5 4501 CPUX86State *env = &cpu->env;
f2574737 4502 int ret = 0;
e22a25c9
AL		 4503 int n;
4504
37936ac7
LA		 4505 if (arch_info->exception == EXCP01_DB) {
4506 if (arch_info->dr6 & DR6_BS) {
ed2803da 4507 if (cs->singlestep_enabled) {
f2574737 4508 ret = EXCP_DEBUG;
b9bec74b 4509 }
e22a25c9 4510 } else {
b9bec74b
JK		 4511 for (n = 0; n < 4; n++) {
4512 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 4513 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4514 case 0x0:
f2574737 4515 ret = EXCP_DEBUG;
e22a25c9
AL		 4516 break;
4517 case 0x1:
f2574737 4518 ret = EXCP_DEBUG;
ff4700b0 4519 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4520 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4521 hw_watchpoint.flags = BP_MEM_WRITE;
4522 break;
4523 case 0x3:
f2574737 4524 ret = EXCP_DEBUG;
ff4700b0 4525 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4526 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4527 hw_watchpoint.flags = BP_MEM_ACCESS;
4528 break;
4529 }
b9bec74b
JK		 4530 }
4531 }
e22a25c9 4532 }
ff4700b0 4533 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 4534 ret = EXCP_DEBUG;
b9bec74b 4535 }
f2574737 4536 if (ret == 0) {
ff4700b0 4537 cpu_synchronize_state(cs);
fd13f23b 4538 assert(env->exception_nr == -1);
b0b1d690 4539
f2574737 4540 /* pass to guest */
fd13f23b
LA		 4541 kvm_queue_exception(env, arch_info->exception,
4542 arch_info->exception == EXCP01_DB,
4543 arch_info->dr6);
48405526 4544 env->has_error_code = 0;
b0b1d690 4545 }
e22a25c9 4546
f2574737 4547 return ret;
e22a25c9
AL		 4548}
4549
20d695a9 4550void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 4551{
4552 const uint8_t type_code[] = {
4553 [GDB_BREAKPOINT_HW] = 0x0,
4554 [GDB_WATCHPOINT_WRITE] = 0x1,
4555 [GDB_WATCHPOINT_ACCESS] = 0x3
4556 };
4557 const uint8_t len_code[] = {
4558 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4559 };
4560 int n;
4561
a60f24b5 4562 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 4563 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 4564 }
e22a25c9
AL		 4565 if (nb_hw_breakpoint > 0) {
4566 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4567 dbg->arch.debugreg[7] = 0x0600;
4568 for (n = 0; n < nb_hw_breakpoint; n++) {
4569 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4570 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4571 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 4572 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 4573 }
4574 }
4575}
4513d923 4576
2a4dac83
JK		 4577static bool host_supports_vmx(void)
4578{
4579 uint32_t ecx, unused;
4580
4581 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4582 return ecx & CPUID_EXT_VMX;
4583}
4584
4585#define VMX_INVALID_GUEST_STATE 0x80000021
4586
20d695a9 4587int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 4588{
20d695a9 4589 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 4590 uint64_t code;
4591 int ret;
4592
4593 switch (run->exit_reason) {
4594 case KVM_EXIT_HLT:
4595 DPRINTF("handle_hlt\n");
4b8523ee 4596 qemu_mutex_lock_iothread();
839b5630 4597 ret = kvm_handle_halt(cpu);
4b8523ee 4598 qemu_mutex_unlock_iothread();
2a4dac83
JK		 4599 break;
4600 case KVM_EXIT_SET_TPR:
4601 ret = 0;
4602 break;
d362e757 4603 case KVM_EXIT_TPR_ACCESS:
4b8523ee 4604 qemu_mutex_lock_iothread();
f7575c96 4605 ret = kvm_handle_tpr_access(cpu);
4b8523ee 4606 qemu_mutex_unlock_iothread();
d362e757 4607 break;
2a4dac83
JK		 4608 case KVM_EXIT_FAIL_ENTRY:
4609 code = run->fail_entry.hardware_entry_failure_reason;
4610 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4611 code);
4612 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4613 fprintf(stderr,
12619721 4614 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 4615 "unrestricted mode\n"
4616 "support, the failure can be most likely due to the guest "
4617 "entering an invalid\n"
4618 "state for Intel VT. For example, the guest maybe running "
4619 "in big real mode\n"
4620 "which is not supported on less recent Intel processors."
4621 "\n\n");
4622 }
4623 ret = -1;
4624 break;
4625 case KVM_EXIT_EXCEPTION:
4626 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4627 run->ex.exception, run->ex.error_code);
4628 ret = -1;
4629 break;
f2574737
JK		 4630 case KVM_EXIT_DEBUG:
4631 DPRINTF("kvm_exit_debug\n");
4b8523ee 4632 qemu_mutex_lock_iothread();
a60f24b5 4633 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 4634 qemu_mutex_unlock_iothread();
f2574737 4635 break;
50efe82c
AS		 4636 case KVM_EXIT_HYPERV:
4637 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4638 break;
15eafc2e
PB		 4639 case KVM_EXIT_IOAPIC_EOI:
4640 ioapic_eoi_broadcast(run->eoi.vector);
4641 ret = 0;
4642 break;
2a4dac83
JK		 4643 default:
4644 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4645 ret = -1;
4646 break;
4647 }
4648
4649 return ret;
4650}
4651
20d695a9 4652bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4653{
20d695a9
AF		 4654 X86CPU *cpu = X86_CPU(cs);
4655 CPUX86State *env = &cpu->env;
4656
dd1750d7 4657 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4658 return !(env->cr[0] & CR0_PE_MASK) ||
4659 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4660}
84b058d7
JK		 4661
4662void kvm_arch_init_irq_routing(KVMState *s)
4663{
cc7e0ddf 4664 /* We know at this point that we're using the in-kernel
614e41bc 4665 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4666 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4667 */
614e41bc 4668 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4669 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4670
4671 if (kvm_irqchip_is_split()) {
4672 int i;
4673
4674 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4675 MSI routes for signaling interrupts to the local apics. */
4676 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4677 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4678 error_report("Could not enable split IRQ mode.");
4679 exit(1);
4680 }
4681 }
4682 }
4683}
4684
4376c40d 4685int kvm_arch_irqchip_create(KVMState *s)
15eafc2e
PB		 4686{
4687 int ret;
4376c40d 4688 if (kvm_kernel_irqchip_split()) {
15eafc2e
PB		 4689 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4690 if (ret) {
df3c286c 4691 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4692 strerror(-ret));
4693 exit(1);
4694 } else {
4695 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4696 kvm_split_irqchip = true;
4697 return 1;
4698 }
4699 } else {
4700 return 0;
4701 }
84b058d7 4702}
b139bd30 4703
c1bb5418
DW		 4704uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
4705{
4706 CPUX86State *env;
4707 uint64_t ext_id;
4708
4709 if (!first_cpu) {
4710 return address;
4711 }
4712 env = &X86_CPU(first_cpu)->env;
4713 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
4714 return address;
4715 }
4716
4717 /*
4718 * If the remappable format bit is set, or the upper bits are
4719 * already set in address_hi, or the low extended bits aren't
4720 * there anyway, do nothing.
4721 */
4722 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
4723 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
4724 return address;
4725 }
4726
4727 address &= ~ext_id;
4728 address |= ext_id << 35;
4729 return address;
4730}
4731
9e03a040 4732int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4733 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4734{
8b5ed7df
PX		 4735 X86IOMMUState *iommu = x86_iommu_get_default();
4736
4737 if (iommu) {
30c60f77 4738 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
8b5ed7df 4739
c1bb5418
DW		 4740 if (class->int_remap) {
4741 int ret;
4742 MSIMessage src, dst;
0ea1472d 4743
c1bb5418
DW		 4744 src.address = route->u.msi.address_hi;
4745 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4746 src.address |= route->u.msi.address_lo;
4747 src.data = route->u.msi.data;
8b5ed7df 4748
c1bb5418
DW		 4749 ret = class->int_remap(iommu, &src, &dst, dev ? \
4750 pci_requester_id(dev) : \
4751 X86_IOMMU_SID_INVALID);
4752 if (ret) {
4753 trace_kvm_x86_fixup_msi_error(route->gsi);
4754 return 1;
4755 }
4756
4757 /*
4758 * Handled untranslated compatibilty format interrupt with
4759 * extended destination ID in the low bits 11-5. */
4760 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
8b5ed7df 4761
c1bb5418
DW		 4762 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4763 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4764 route->u.msi.data = dst.data;
4765 return 0;
4766 }
8b5ed7df
PX		 4767 }
4768
c1bb5418
DW		 4769 address = kvm_swizzle_msi_ext_dest_id(address);
4770 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
4771 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
9e03a040
FB		 4772 return 0;
4773}
1850b6b7 4774
38d87493
PX		 4775typedef struct MSIRouteEntry MSIRouteEntry;
4776
4777struct MSIRouteEntry {
4778 PCIDevice *dev; /* Device pointer */
4779 int vector; /* MSI/MSIX vector index */
4780 int virq; /* Virtual IRQ index */
4781 QLIST_ENTRY(MSIRouteEntry) list;
4782};
4783
4784/* List of used GSI routes */
4785static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4786 QLIST_HEAD_INITIALIZER(msi_route_list);
4787
e1d4fb2d
PX		 4788static void kvm_update_msi_routes_all(void *private, bool global,
4789 uint32_t index, uint32_t mask)
4790{
a56de056 4791 int cnt = 0, vector;
e1d4fb2d
PX		 4792 MSIRouteEntry *entry;
4793 MSIMessage msg;
fd563564
PX		 4794 PCIDevice *dev;
4795
e1d4fb2d
PX		 4796 /* TODO: explicit route update */
4797 QLIST_FOREACH(entry, &msi_route_list, list) {
4798 cnt++;
a56de056 4799 vector = entry->vector;
fd563564 4800 dev = entry->dev;
a56de056
PX		 4801 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4802 msg = msix_get_message(dev, vector);
4803 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4804 msg = msi_get_message(dev, vector);
4805 } else {
4806 /*
4807 * Either MSI/MSIX is disabled for the device, or the
4808 * specific message was masked out. Skip this one.
4809 */
fd563564
PX		 4810 continue;
4811 }
fd563564 4812 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4813 }
3f1fea0f 4814 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4815 trace_kvm_x86_update_msi_routes(cnt);
4816}
4817
38d87493
PX		 4818int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4819 int vector, PCIDevice *dev)
4820{
e1d4fb2d 4821 static bool notify_list_inited = false;
38d87493
PX		 4822 MSIRouteEntry *entry;
4823
4824 if (!dev) {
4825 /* These are (possibly) IOAPIC routes only used for split
4826 * kernel irqchip mode, while what we are housekeeping are
4827 * PCI devices only. */
4828 return 0;
4829 }
4830
4831 entry = g_new0(MSIRouteEntry, 1);
4832 entry->dev = dev;
4833 entry->vector = vector;
4834 entry->virq = route->gsi;
4835 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4836
4837 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4838
4839 if (!notify_list_inited) {
4840 /* For the first time we do add route, add ourselves into
4841 * IOMMU's IEC notify list if needed. */
4842 X86IOMMUState *iommu = x86_iommu_get_default();
4843 if (iommu) {
4844 x86_iommu_iec_register_notifier(iommu,
4845 kvm_update_msi_routes_all,
4846 NULL);
4847 }
4848 notify_list_inited = true;
4849 }
38d87493
PX		 4850 return 0;
4851}
4852
4853int kvm_arch_release_virq_post(int virq)
4854{
4855 MSIRouteEntry *entry, *next;
4856 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4857 if (entry->virq == virq) {
4858 trace_kvm_x86_remove_msi_route(virq);
4859 QLIST_REMOVE(entry, list);
01960e6d 4860 g_free(entry);
38d87493
PX		 4861 break;
4862 }
4863 }
9e03a040
FB		 4864 return 0;
4865}
1850b6b7
EA		 4866
4867int kvm_arch_msi_data_to_gsi(uint32_t data)
4868{
4869 abort();
4870}
e1e43813
PB		 4871
4872bool kvm_has_waitpkg(void)
4873{
4874 return has_msr_umwait;
4875}
92a5199b
TL		 4876
4877bool kvm_arch_cpu_check_are_resettable(void)
4878{
4879 return !sev_es_enabled();
4880}
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