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x86: Implement MSR_CORE_THREAD_COUNT MSR
[mirror_qemu.git] / target / i386 / kvm / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
8efc4e51 16#include "qapi/qapi-events-run-state.h"
da34e65c 17#include "qapi/error.h"
e2e69f6b 18#include "qapi/visitor.h"
05330448 19#include <sys/ioctl.h>
25d2e361 20#include <sys/utsname.h>
19db68ca 21#include <sys/syscall.h>
05330448
AL		 22
23#include <linux/kvm.h>
1814eab6 24#include "standard-headers/asm-x86/kvm_para.h"
05330448 25
33c11879 26#include "cpu.h"
f5cc5a5c 27#include "host-cpu.h"
9c17d615 28#include "sysemu/sysemu.h"
b3946626 29#include "sysemu/hw_accel.h"
6410848b 30#include "sysemu/kvm_int.h"
54d31236 31#include "sysemu/runstate.h"
1d31f66b 32#include "kvm_i386.h"
93777de3 33#include "sev.h"
50efe82c 34#include "hyperv.h"
5e953812 35#include "hyperv-proto.h"
50efe82c 36
022c62cb 37#include "exec/gdbstub.h"
1de7afc9 38#include "qemu/host-utils.h"
db725815 39#include "qemu/main-loop.h"
1de7afc9 40#include "qemu/config-file.h"
1c4a55db 41#include "qemu/error-report.h"
5df022cf 42#include "qemu/memalign.h"
89a289c7 43#include "hw/i386/x86.h"
0d09e41a 44#include "hw/i386/apic.h"
e0723c45
PB		 45#include "hw/i386/apic_internal.h"
46#include "hw/i386/apic-msidef.h"
8b5ed7df 47#include "hw/i386/intel_iommu.h"
e1d4fb2d 48#include "hw/i386/x86-iommu.h"
d6d059ca 49#include "hw/i386/e820_memory_layout.h"
50efe82c 50
a2cb15b0 51#include "hw/pci/pci.h"
15eafc2e 52#include "hw/pci/msi.h"
fd563564 53#include "hw/pci/msix.h"
795c40b8 54#include "migration/blocker.h"
4c663752 55#include "exec/memattrs.h"
8b5ed7df 56#include "trace.h"
05330448 57
d8701185
JD		 58#include CONFIG_DEVICES
59
05330448
AL		 60//#define DEBUG_KVM
61
62#ifdef DEBUG_KVM
8c0d577e 63#define DPRINTF(fmt, ...) \
05330448
AL		 64 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
65#else
8c0d577e 66#define DPRINTF(fmt, ...) \
05330448
AL		 67 do { } while (0)
68#endif
69
73b994f6
LA		 70/* From arch/x86/kvm/lapic.h */
71#define KVM_APIC_BUS_CYCLE_NS 1
72#define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
73
1a03675d
GC		 74#define MSR_KVM_WALL_CLOCK 0x11
75#define MSR_KVM_SYSTEM_TIME 0x12
76
d1138251
EH		 77/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
78 * 255 kvm_msr_entry structs */
79#define MSR_BUF_SIZE 4096
d71b62a1 80
420ae1fc
PB		 81static void kvm_init_msrs(X86CPU *cpu);
82
94a8d39a
JK		 83const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
84 KVM_CAP_INFO(SET_TSS_ADDR),
85 KVM_CAP_INFO(EXT_CPUID),
86 KVM_CAP_INFO(MP_STATE),
87 KVM_CAP_LAST_INFO
88};
25d2e361 89
c3a3a7d3
JK		 90static bool has_msr_star;
91static bool has_msr_hsave_pa;
c9b8f6b6 92static bool has_msr_tsc_aux;
f28558d3 93static bool has_msr_tsc_adjust;
aa82ba54 94static bool has_msr_tsc_deadline;
df67696e 95static bool has_msr_feature_control;
21e87c46 96static bool has_msr_misc_enable;
fc12d72e 97static bool has_msr_smbase;
79e9ebeb 98static bool has_msr_bndcfgs;
25d2e361 99static int lm_capable_kernel;
7bc3d711 100static bool has_msr_hv_hypercall;
f2a53c9e 101static bool has_msr_hv_crash;
744b8a94 102static bool has_msr_hv_reset;
8c145d7c 103static bool has_msr_hv_vpindex;
e9688fab 104static bool hv_vpindex_settable;
46eb8f98 105static bool has_msr_hv_runtime;
866eea9a 106static bool has_msr_hv_synic;
ff99aa64 107static bool has_msr_hv_stimer;
d72bc7f6 108static bool has_msr_hv_frequencies;
ba6a4fd9 109static bool has_msr_hv_reenlightenment;
73d24074 110static bool has_msr_hv_syndbg_options;
18cd2c17 111static bool has_msr_xss;
65087997 112static bool has_msr_umwait;
a33a2cfe 113static bool has_msr_spec_ctrl;
cabf9862 114static bool has_tsc_scale_msr;
2a9758c5 115static bool has_msr_tsx_ctrl;
cfeea0c0 116static bool has_msr_virt_ssbd;
e13713db 117static bool has_msr_smi_count;
aec5e9c3 118static bool has_msr_arch_capabs;
597360c0 119static bool has_msr_core_capabs;
20a78b02 120static bool has_msr_vmx_vmfunc;
67025148 121static bool has_msr_ucode_rev;
4a910e1f 122static bool has_msr_vmx_procbased_ctls2;
ea39f9b6 123static bool has_msr_perf_capabs;
6aa4228b 124static bool has_msr_pkrs;
b827df58 125
0b368a10
JD		 126static uint32_t has_architectural_pmu_version;
127static uint32_t num_architectural_pmu_gp_counters;
128static uint32_t num_architectural_pmu_fixed_counters;
0d894367 129
28143b40 130static int has_xsave;
e56dd3c7 131static int has_xsave2;
28143b40
TH		 132static int has_xcrs;
133static int has_pit_state2;
8f515d38 134static int has_sregs2;
fd13f23b 135static int has_exception_payload;
12f89a39 136static int has_triple_fault_event;
28143b40 137
87f8b626
AR		 138static bool has_msr_mcg_ext_ctl;
139
494e95e9 140static struct kvm_cpuid2 *cpuid_cache;
a8439be6 141static struct kvm_cpuid2 *hv_cpuid_cache;
f57bceb6 142static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 143
035d1ef2
CQ		 144#define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
145static RateLimit bus_lock_ratelimit_ctrl;
5a778a5f 146static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value);
035d1ef2 147
28143b40
TH		 148int kvm_has_pit_state2(void)
149{
150 return has_pit_state2;
151}
152
355023f2
PB		 153bool kvm_has_smm(void)
154{
23edf8b5 155 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
355023f2
PB		 156}
157
6053a86f
MT		 158bool kvm_has_adjust_clock_stable(void)
159{
160 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
161
c4ef867f 162 return (ret & KVM_CLOCK_TSC_STABLE);
6053a86f
MT		 163}
164
8700a984
VK		 165bool kvm_has_adjust_clock(void)
166{
167 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
168}
169
79a197ab
LA		 170bool kvm_has_exception_payload(void)
171{
172 return has_exception_payload;
173}
174
fb506e70
RK		 175static bool kvm_x2apic_api_set_flags(uint64_t flags)
176{
4f7f5893 177 KVMState *s = KVM_STATE(current_accel());
fb506e70
RK		 178
179 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
180}
181
e391c009 182#define MEMORIZE(fn, _result) \
2a138ec3 183 ({ \
2a138ec3
RK		 184 static bool _memorized; \
185 \
186 if (_memorized) { \
187 return _result; \
188 } \
189 _memorized = true; \
190 _result = fn; \
191 })
192
e391c009
IM		 193static bool has_x2apic_api;
194
195bool kvm_has_x2apic_api(void)
196{
197 return has_x2apic_api;
198}
199
fb506e70
RK		 200bool kvm_enable_x2apic(void)
201{
2a138ec3
RK		 202 return MEMORIZE(
203 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 204 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
205 has_x2apic_api);
fb506e70
RK		 206}
207
e9688fab
RK		 208bool kvm_hv_vpindex_settable(void)
209{
210 return hv_vpindex_settable;
211}
212
0fd7e098
LL		 213static int kvm_get_tsc(CPUState *cs)
214{
215 X86CPU *cpu = X86_CPU(cs);
216 CPUX86State *env = &cpu->env;
5a778a5f 217 uint64_t value;
0fd7e098
LL		 218 int ret;
219
220 if (env->tsc_valid) {
221 return 0;
222 }
223
0fd7e098
LL		 224 env->tsc_valid = !runstate_is_running();
225
5a778a5f 226 ret = kvm_get_one_msr(cpu, MSR_IA32_TSC, &value);
0fd7e098
LL		 227 if (ret < 0) {
228 return ret;
229 }
230
5a778a5f 231 env->tsc = value;
0fd7e098
LL		 232 return 0;
233}
234
14e6fe12 235static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 236{
0fd7e098
LL		 237 kvm_get_tsc(cpu);
238}
239
240void kvm_synchronize_all_tsc(void)
241{
242 CPUState *cpu;
243
244 if (kvm_enabled()) {
245 CPU_FOREACH(cpu) {
14e6fe12 246 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 247 }
248 }
249}
250
b827df58
AK		 251static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
252{
253 struct kvm_cpuid2 *cpuid;
254 int r, size;
255
256 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 257 cpuid = g_malloc0(size);
b827df58
AK		 258 cpuid->nent = max;
259 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 260 if (r == 0 && cpuid->nent >= max) {
261 r = -E2BIG;
262 }
b827df58
AK		 263 if (r < 0) {
264 if (r == -E2BIG) {
7267c094 265 g_free(cpuid);
b827df58
AK		 266 return NULL;
267 } else {
268 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
269 strerror(-r));
270 exit(1);
271 }
272 }
273 return cpuid;
274}
275
dd87f8a6
EH		 276/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
277 * for all entries.
278 */
279static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
280{
281 struct kvm_cpuid2 *cpuid;
282 int max = 1;
494e95e9
CP		 283
284 if (cpuid_cache != NULL) {
285 return cpuid_cache;
286 }
dd87f8a6
EH		 287 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
288 max *= 2;
289 }
494e95e9 290 cpuid_cache = cpuid;
dd87f8a6
EH		 291 return cpuid;
292}
293
b199c682 294static bool host_tsx_broken(void)
40e80ee4
EH		 295{
296 int family, model, stepping;\
297 char vendor[CPUID_VENDOR_SZ + 1];
298
f5cc5a5c 299 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
40e80ee4
EH		 300
301 /* Check if we are running on a Haswell host known to have broken TSX */
302 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
303 (family == 6) &&
304 ((model == 63 && stepping < 4) ||
305 model == 60 || model == 69 || model == 70);
306}
0c31b744 307
829ae2f9
EH		 308/* Returns the value for a specific register on the cpuid entry
309 */
310static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
311{
312 uint32_t ret = 0;
313 switch (reg) {
314 case R_EAX:
315 ret = entry->eax;
316 break;
317 case R_EBX:
318 ret = entry->ebx;
319 break;
320 case R_ECX:
321 ret = entry->ecx;
322 break;
323 case R_EDX:
324 ret = entry->edx;
325 break;
326 }
327 return ret;
328}
329
4fb73f1d
EH		 330/* Find matching entry for function/index on kvm_cpuid2 struct
331 */
332static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
333 uint32_t function,
334 uint32_t index)
335{
336 int i;
337 for (i = 0; i < cpuid->nent; ++i) {
338 if (cpuid->entries[i].function == function &&
339 cpuid->entries[i].index == index) {
340 return &cpuid->entries[i];
341 }
342 }
343 /* not found: */
344 return NULL;
345}
346
ba9bc59e 347uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 348 uint32_t index, int reg)
b827df58
AK		 349{
350 struct kvm_cpuid2 *cpuid;
b827df58
AK		 351 uint32_t ret = 0;
352 uint32_t cpuid_1_edx;
19db68ca 353 uint64_t bitmask;
b827df58 354
dd87f8a6 355 cpuid = get_supported_cpuid(s);
b827df58 356
4fb73f1d
EH		 357 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
358 if (entry) {
4fb73f1d 359 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 360 }
361
7b46e5ce
EH		 362 /* Fixups for the data returned by KVM, below */
363
c2acb022
EH		 364 if (function == 1 && reg == R_EDX) {
365 /* KVM before 2.6.30 misreports the following features */
366 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 367 } else if (function == 1 && reg == R_ECX) {
368 /* We can set the hypervisor flag, even if KVM does not return it on
369 * GET_SUPPORTED_CPUID
370 */
371 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 372 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
373 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
374 * and the irqchip is in the kernel.
375 */
376 if (kvm_irqchip_in_kernel() &&
377 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
378 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
379 }
41e5e76d
EH		 380
381 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
382 * without the in-kernel irqchip
383 */
384 if (!kvm_irqchip_in_kernel()) {
385 ret &= ~CPUID_EXT_X2APIC;
b827df58 386 }
2266d443
MT		 387
388 if (enable_cpu_pm) {
389 int disable_exits = kvm_check_extension(s,
390 KVM_CAP_X86_DISABLE_EXITS);
391
392 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
393 ret |= CPUID_EXT_MONITOR;
394 }
395 }
28b8e4d0
JK		 396 } else if (function == 6 && reg == R_EAX) {
397 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4 398 } else if (function == 7 && index == 0 && reg == R_EBX) {
b199c682 399 if (host_tsx_broken()) {
40e80ee4
EH		 400 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
401 }
485b1d25
EH		 402 } else if (function == 7 && index == 0 && reg == R_EDX) {
403 /*
404 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
405 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
406 * returned by KVM_GET_MSR_INDEX_LIST.
407 */
408 if (!has_msr_arch_capabs) {
409 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
410 }
19db68ca
YZ		 411 } else if (function == 0xd && index == 0 &&
412 (reg == R_EAX || reg == R_EDX)) {
3ec5ad40
PB		 413 /*
414 * The value returned by KVM_GET_SUPPORTED_CPUID does not include
415 * features that still have to be enabled with the arch_prctl
416 * system call. QEMU needs the full value, which is retrieved
417 * with KVM_GET_DEVICE_ATTR.
418 */
19db68ca
YZ		 419 struct kvm_device_attr attr = {
420 .group = 0,
421 .attr = KVM_X86_XCOMP_GUEST_SUPP,
422 .addr = (unsigned long) &bitmask
423 };
424
425 bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES);
426 if (!sys_attr) {
3ec5ad40 427 return ret;
19db68ca
YZ		 428 }
429
430 int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr);
3ec5ad40
PB		 431 if (rc < 0) {
432 if (rc != -ENXIO) {
433 warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) "
434 "error: %d", rc);
435 }
436 return ret;
19db68ca
YZ		 437 }
438 ret = (reg == R_EAX) ? bitmask : bitmask >> 32;
f98bbd83
BM		 439 } else if (function == 0x80000001 && reg == R_ECX) {
440 /*
441 * It's safe to enable TOPOEXT even if it's not returned by
442 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
443 * us to keep CPU models including TOPOEXT runnable on older kernels.
444 */
445 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 446 } else if (function == 0x80000001 && reg == R_EDX) {
447 /* On Intel, kvm returns cpuid according to the Intel spec,
448 * so add missing bits according to the AMD spec:
449 */
450 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
451 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 452 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
453 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
454 * be enabled without the in-kernel irqchip
455 */
456 if (!kvm_irqchip_in_kernel()) {
457 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
458 }
c1bb5418
DW		 459 if (kvm_irqchip_is_split()) {
460 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
461 }
be777326 462 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 463 ret |= 1U << KVM_HINTS_REALTIME;
b9bec74b 464 }
0c31b744
GC		 465
466 return ret;
bb0300dc 467}
bb0300dc 468
ede146c2 469uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
f57bceb6
RH		 470{
471 struct {
472 struct kvm_msrs info;
473 struct kvm_msr_entry entries[1];
a1834d97 474 } msr_data = {};
20a78b02
PB		 475 uint64_t value;
476 uint32_t ret, can_be_one, must_be_one;
f57bceb6
RH		 477
478 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
479 return 0;
480 }
481
482 /* Check if requested MSR is supported feature MSR */
483 int i;
484 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
485 if (kvm_feature_msrs->indices[i] == index) {
486 break;
487 }
488 if (i == kvm_feature_msrs->nmsrs) {
489 return 0; /* if the feature MSR is not supported, simply return 0 */
490 }
491
492 msr_data.info.nmsrs = 1;
493 msr_data.entries[0].index = index;
494
495 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
496 if (ret != 1) {
497 error_report("KVM get MSR (index=0x%x) feature failed, %s",
498 index, strerror(-ret));
499 exit(1);
500 }
501
20a78b02
PB		 502 value = msr_data.entries[0].data;
503 switch (index) {
504 case MSR_IA32_VMX_PROCBASED_CTLS2:
4a910e1f
VK		 505 if (!has_msr_vmx_procbased_ctls2) {
506 /* KVM forgot to add these bits for some time, do this ourselves. */
507 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
508 CPUID_XSAVE_XSAVES) {
509 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
510 }
511 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
512 CPUID_EXT_RDRAND) {
513 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
514 }
515 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
516 CPUID_7_0_EBX_INVPCID) {
517 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
518 }
519 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
520 CPUID_7_0_EBX_RDSEED) {
521 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
522 }
523 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
524 CPUID_EXT2_RDTSCP) {
525 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
526 }
048c9516
PB		 527 }
528 /* fall through */
20a78b02
PB		 529 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
530 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
531 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
532 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
533 /*
534 * Return true for bits that can be one, but do not have to be one.
535 * The SDM tells us which bits could have a "must be one" setting,
536 * so we can do the opposite transformation in make_vmx_msr_value.
537 */
538 must_be_one = (uint32_t)value;
539 can_be_one = (uint32_t)(value >> 32);
540 return can_be_one & ~must_be_one;
541
542 default:
543 return value;
544 }
f57bceb6
RH		 545}
546
e7701825
MT		 547static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
548 int *max_banks)
549{
550 int r;
551
14a09518 552 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 553 if (r > 0) {
554 *max_banks = r;
555 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
556 }
557 return -ENOSYS;
558}
559
bee615d4 560static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 561{
87f8b626 562 CPUState *cs = CPU(cpu);
bee615d4 563 CPUX86State *env = &cpu->env;
c34d440a
JK		 564 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
565 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
566 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 567 int flags = 0;
e7701825 568
c34d440a
JK		 569 if (code == BUS_MCEERR_AR) {
570 status |= MCI_STATUS_AR | 0x134;
cb48748a 571 mcg_status |= MCG_STATUS_RIPV | MCG_STATUS_EIPV;
c34d440a
JK		 572 } else {
573 status |= 0xc0;
574 mcg_status |= MCG_STATUS_RIPV;
419fb20a 575 }
87f8b626
AR		 576
577 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
578 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
579 * guest kernel back into env->mcg_ext_ctl.
580 */
581 cpu_synchronize_state(cs);
582 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
583 mcg_status |= MCG_STATUS_LMCE;
584 flags = 0;
585 }
586
8c5cf3b6 587 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 588 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 589}
419fb20a 590
8efc4e51
ZP		 591static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
592{
593 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
594
595 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
596 &mff);
597}
598
73284563 599static void hardware_memory_error(void *host_addr)
419fb20a 600{
8efc4e51 601 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
73284563 602 error_report("QEMU got Hardware memory error at addr %p", host_addr);
419fb20a
JK		 603 exit(1);
604}
605
2ae41db2 606void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 607{
20d695a9
AF		 608 X86CPU *cpu = X86_CPU(c);
609 CPUX86State *env = &cpu->env;
419fb20a 610 ram_addr_t ram_addr;
a8170e5e 611 hwaddr paddr;
419fb20a 612
4d39892c
PB		 613 /* If we get an action required MCE, it has been injected by KVM
614 * while the VM was running. An action optional MCE instead should
615 * be coming from the main thread, which qemu_init_sigbus identifies
616 * as the "early kill" thread.
617 */
a16fc07e 618 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 619
20e0ff59 620 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 621 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 622 if (ram_addr != RAM_ADDR_INVALID &&
623 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
624 kvm_hwpoison_page_add(ram_addr);
625 kvm_mce_inject(cpu, paddr, code);
73284563
MS		 626
627 /*
628 * Use different logging severity based on error type.
629 * If there is additional MCE reporting on the hypervisor, QEMU VA
630 * could be another source to identify the PA and MCE details.
631 */
632 if (code == BUS_MCEERR_AR) {
633 error_report("Guest MCE Memory Error at QEMU addr %p and "
634 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
635 addr, paddr, "BUS_MCEERR_AR");
636 } else {
637 warn_report("Guest MCE Memory Error at QEMU addr %p and "
638 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
639 addr, paddr, "BUS_MCEERR_AO");
640 }
641
2ae41db2 642 return;
419fb20a 643 }
20e0ff59 644
73284563
MS		 645 if (code == BUS_MCEERR_AO) {
646 warn_report("Hardware memory error at addr %p of type %s "
647 "for memory used by QEMU itself instead of guest system!",
648 addr, "BUS_MCEERR_AO");
649 }
419fb20a 650 }
20e0ff59
PB		 651
652 if (code == BUS_MCEERR_AR) {
73284563 653 hardware_memory_error(addr);
20e0ff59
PB		 654 }
655
8efc4e51
ZP		 656 /* Hope we are lucky for AO MCE, just notify a event */
657 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
419fb20a
JK		 658}
659
fd13f23b
LA		 660static void kvm_reset_exception(CPUX86State *env)
661{
662 env->exception_nr = -1;
663 env->exception_pending = 0;
664 env->exception_injected = 0;
665 env->exception_has_payload = false;
666 env->exception_payload = 0;
667}
668
669static void kvm_queue_exception(CPUX86State *env,
670 int32_t exception_nr,
671 uint8_t exception_has_payload,
672 uint64_t exception_payload)
673{
674 assert(env->exception_nr == -1);
675 assert(!env->exception_pending);
676 assert(!env->exception_injected);
677 assert(!env->exception_has_payload);
678
679 env->exception_nr = exception_nr;
680
681 if (has_exception_payload) {
682 env->exception_pending = 1;
683
684 env->exception_has_payload = exception_has_payload;
685 env->exception_payload = exception_payload;
686 } else {
687 env->exception_injected = 1;
688
689 if (exception_nr == EXCP01_DB) {
690 assert(exception_has_payload);
691 env->dr[6] = exception_payload;
692 } else if (exception_nr == EXCP0E_PAGE) {
693 assert(exception_has_payload);
694 env->cr[2] = exception_payload;
695 } else {
696 assert(!exception_has_payload);
697 }
698 }
699}
700
1bc22652 701static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 702{
1bc22652
AF		 703 CPUX86State *env = &cpu->env;
704
fd13f23b 705 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 706 unsigned int bank, bank_num = env->mcg_cap & 0xff;
707 struct kvm_x86_mce mce;
708
fd13f23b 709 kvm_reset_exception(env);
ab443475
JK		 710
711 /*
712 * There must be at least one bank in use if an MCE is pending.
713 * Find it and use its values for the event injection.
714 */
715 for (bank = 0; bank < bank_num; bank++) {
716 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
717 break;
718 }
719 }
720 assert(bank < bank_num);
721
722 mce.bank = bank;
723 mce.status = env->mce_banks[bank * 4 + 1];
724 mce.mcg_status = env->mcg_status;
725 mce.addr = env->mce_banks[bank * 4 + 2];
726 mce.misc = env->mce_banks[bank * 4 + 3];
727
1bc22652 728 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 729 }
ab443475
JK		 730 return 0;
731}
732
538f0497 733static void cpu_update_state(void *opaque, bool running, RunState state)
b8cc45d6 734{
317ac620 735 CPUX86State *env = opaque;
b8cc45d6
GC		 736
737 if (running) {
738 env->tsc_valid = false;
739 }
740}
741
83b17af5 742unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 743{
83b17af5 744 X86CPU *cpu = X86_CPU(cs);
7e72a45c 745 return cpu->apic_id;
b164e48e
EH		 746}
747
92067bf4
IM		 748#ifndef KVM_CPUID_SIGNATURE_NEXT
749#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
750#endif
751
92067bf4
IM		 752static bool hyperv_enabled(X86CPU *cpu)
753{
5aa9ef5e 754 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
f701c082 755 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
e48ddcc6 756 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 757}
758
74aaddc6
MT		 759/*
760 * Check whether target_freq is within conservative
761 * ntp correctable bounds (250ppm) of freq
762 */
763static inline bool freq_within_bounds(int freq, int target_freq)
764{
765 int max_freq = freq + (freq * 250 / 1000000);
766 int min_freq = freq - (freq * 250 / 1000000);
767
768 if (target_freq >= min_freq && target_freq <= max_freq) {
769 return true;
770 }
771
772 return false;
773}
774
5031283d
HZ		 775static int kvm_arch_set_tsc_khz(CPUState *cs)
776{
777 X86CPU *cpu = X86_CPU(cs);
778 CPUX86State *env = &cpu->env;
74aaddc6
MT		 779 int r, cur_freq;
780 bool set_ioctl = false;
5031283d
HZ		 781
782 if (!env->tsc_khz) {
783 return 0;
784 }
785
74aaddc6
MT		 786 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
787 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
788
789 /*
790 * If TSC scaling is supported, attempt to set TSC frequency.
791 */
792 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
793 set_ioctl = true;
794 }
795
796 /*
797 * If desired TSC frequency is within bounds of NTP correction,
798 * attempt to set TSC frequency.
799 */
800 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
801 set_ioctl = true;
802 }
803
804 r = set_ioctl ?
5031283d
HZ		 805 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
806 -ENOTSUP;
74aaddc6 807
5031283d
HZ		 808 if (r < 0) {
809 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
810 * TSC frequency doesn't match the one we want.
811 */
74aaddc6
MT		 812 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
813 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
814 -ENOTSUP;
5031283d 815 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 816 warn_report("TSC frequency mismatch between "
817 "VM (%" PRId64 " kHz) and host (%d kHz), "
818 "and TSC scaling unavailable",
819 env->tsc_khz, cur_freq);
5031283d
HZ		 820 return r;
821 }
822 }
823
824 return 0;
825}
826
4bb95b82
LP		 827static bool tsc_is_stable_and_known(CPUX86State *env)
828{
829 if (!env->tsc_khz) {
830 return false;
831 }
832 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
833 || env->user_tsc_khz;
834}
835
7110fe56
VK		 836#define DEFAULT_EVMCS_VERSION ((1 << 8) | 1)
837
6760bd20
VK		 838static struct {
839 const char *desc;
840 struct {
061817a7
VK		 841 uint32_t func;
842 int reg;
6760bd20
VK		 843 uint32_t bits;
844 } flags[2];
c6861930 845 uint64_t dependencies;
6760bd20
VK		 846} kvm_hyperv_properties[] = {
847 [HYPERV_FEAT_RELAXED] = {
848 .desc = "relaxed timing (hv-relaxed)",
849 .flags = {
061817a7 850 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 851 .bits = HV_RELAXED_TIMING_RECOMMENDED}
852 }
853 },
854 [HYPERV_FEAT_VAPIC] = {
855 .desc = "virtual APIC (hv-vapic)",
856 .flags = {
061817a7 857 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
05071629 858 .bits = HV_APIC_ACCESS_AVAILABLE}
6760bd20
VK		 859 }
860 },
861 [HYPERV_FEAT_TIME] = {
862 .desc = "clocksources (hv-time)",
863 .flags = {
061817a7 864 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
b26f68c3 865 .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE}
6760bd20
VK		 866 }
867 },
868 [HYPERV_FEAT_CRASH] = {
869 .desc = "crash MSRs (hv-crash)",
870 .flags = {
061817a7 871 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 872 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
873 }
874 },
875 [HYPERV_FEAT_RESET] = {
876 .desc = "reset MSR (hv-reset)",
877 .flags = {
061817a7 878 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 879 .bits = HV_RESET_AVAILABLE}
880 }
881 },
882 [HYPERV_FEAT_VPINDEX] = {
883 .desc = "VP_INDEX MSR (hv-vpindex)",
884 .flags = {
061817a7 885 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 886 .bits = HV_VP_INDEX_AVAILABLE}
887 }
888 },
889 [HYPERV_FEAT_RUNTIME] = {
890 .desc = "VP_RUNTIME MSR (hv-runtime)",
891 .flags = {
061817a7 892 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 893 .bits = HV_VP_RUNTIME_AVAILABLE}
894 }
895 },
896 [HYPERV_FEAT_SYNIC] = {
897 .desc = "synthetic interrupt controller (hv-synic)",
898 .flags = {
061817a7 899 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 900 .bits = HV_SYNIC_AVAILABLE}
901 }
902 },
903 [HYPERV_FEAT_STIMER] = {
904 .desc = "synthetic timers (hv-stimer)",
905 .flags = {
061817a7 906 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 907 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 908 },
909 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 910 },
911 [HYPERV_FEAT_FREQUENCIES] = {
912 .desc = "frequency MSRs (hv-frequencies)",
913 .flags = {
061817a7 914 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 915 .bits = HV_ACCESS_FREQUENCY_MSRS},
061817a7 916 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 917 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
918 }
919 },
920 [HYPERV_FEAT_REENLIGHTENMENT] = {
921 .desc = "reenlightenment MSRs (hv-reenlightenment)",
922 .flags = {
061817a7 923 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 924 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
925 }
926 },
927 [HYPERV_FEAT_TLBFLUSH] = {
928 .desc = "paravirtualized TLB flush (hv-tlbflush)",
929 .flags = {
061817a7 930 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 931 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
932 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 933 },
934 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 935 },
936 [HYPERV_FEAT_EVMCS] = {
937 .desc = "enlightened VMCS (hv-evmcs)",
938 .flags = {
061817a7 939 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20 940 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 941 },
942 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 943 },
944 [HYPERV_FEAT_IPI] = {
945 .desc = "paravirtualized IPI (hv-ipi)",
946 .flags = {
061817a7 947 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 948 .bits = HV_CLUSTER_IPI_RECOMMENDED |
949 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 950 },
951 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 952 },
128531d9
VK		 953 [HYPERV_FEAT_STIMER_DIRECT] = {
954 .desc = "direct mode synthetic timers (hv-stimer-direct)",
955 .flags = {
061817a7 956 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
128531d9
VK		 957 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
958 },
959 .dependencies = BIT(HYPERV_FEAT_STIMER)
960 },
e1f9a8e8
VK		 961 [HYPERV_FEAT_AVIC] = {
962 .desc = "AVIC/APICv support (hv-avic/hv-apicv)",
963 .flags = {
964 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
965 .bits = HV_DEPRECATING_AEOI_RECOMMENDED}
966 }
967 },
d8701185 968#ifdef CONFIG_SYNDBG
73d24074
JD		 969 [HYPERV_FEAT_SYNDBG] = {
970 .desc = "Enable synthetic kernel debugger channel (hv-syndbg)",
971 .flags = {
972 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
973 .bits = HV_FEATURE_DEBUG_MSRS_AVAILABLE}
974 },
975 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_RELAXED)
976 },
d8701185 977#endif
869840d2
VK		 978 [HYPERV_FEAT_MSR_BITMAP] = {
979 .desc = "enlightened MSR-Bitmap (hv-emsr-bitmap)",
980 .flags = {
981 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
982 .bits = HV_NESTED_MSR_BITMAP}
983 }
984 },
9411e8b6
VK		 985 [HYPERV_FEAT_XMM_INPUT] = {
986 .desc = "XMM fast hypercall input (hv-xmm-input)",
987 .flags = {
988 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
989 .bits = HV_HYPERCALL_XMM_INPUT_AVAILABLE}
990 }
991 },
aa6bb5fa
VK		 992 [HYPERV_FEAT_TLBFLUSH_EXT] = {
993 .desc = "Extended gva ranges for TLB flush hypercalls (hv-tlbflush-ext)",
994 .flags = {
995 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
996 .bits = HV_EXT_GVA_RANGES_FLUSH_AVAILABLE}
997 },
998 .dependencies = BIT(HYPERV_FEAT_TLBFLUSH)
999 },
3aae0854
VK		 1000 [HYPERV_FEAT_TLBFLUSH_DIRECT] = {
1001 .desc = "direct TLB flush (hv-tlbflush-direct)",
1002 .flags = {
1003 {.func = HV_CPUID_NESTED_FEATURES, .reg = R_EAX,
1004 .bits = HV_NESTED_DIRECT_FLUSH}
1005 },
1006 .dependencies = BIT(HYPERV_FEAT_VAPIC)
1007 },
6760bd20
VK		 1008};
1009
2e905438
VK		 1010static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
1011 bool do_sys_ioctl)
6760bd20
VK		 1012{
1013 struct kvm_cpuid2 *cpuid;
1014 int r, size;
1015
1016 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
1017 cpuid = g_malloc0(size);
1018 cpuid->nent = max;
1019
2e905438
VK		 1020 if (do_sys_ioctl) {
1021 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1022 } else {
1023 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
1024 }
6760bd20
VK		 1025 if (r == 0 && cpuid->nent >= max) {
1026 r = -E2BIG;
1027 }
1028 if (r < 0) {
1029 if (r == -E2BIG) {
1030 g_free(cpuid);
1031 return NULL;
1032 } else {
1033 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
1034 strerror(-r));
1035 exit(1);
1036 }
1037 }
1038 return cpuid;
1039}
1040
1041/*
1042 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
1043 * for all entries.
1044 */
1045static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
1046{
1047 struct kvm_cpuid2 *cpuid;
73d24074
JD		 1048 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000082 leaves */
1049 int max = 11;
decb4f20 1050 int i;
2e905438
VK		 1051 bool do_sys_ioctl;
1052
1053 do_sys_ioctl =
1054 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
6760bd20 1055
e4adb09f
VK		 1056 /*
1057 * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is
1058 * unsupported, kvm_hyperv_expand_features() checks for that.
1059 */
1060 assert(do_sys_ioctl || cs->kvm_state);
1061
6760bd20
VK		 1062 /*
1063 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
1064 * -E2BIG, however, it doesn't report back the right size. Keep increasing
1065 * it and re-trying until we succeed.
1066 */
2e905438 1067 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
6760bd20
VK		 1068 max++;
1069 }
decb4f20
VK		 1070
1071 /*
1072 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
1073 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
1074 * information early, just check for the capability and set the bit
1075 * manually.
1076 */
2e905438 1077 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
decb4f20
VK		 1078 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1079 for (i = 0; i < cpuid->nent; i++) {
1080 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
1081 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1082 }
1083 }
1084 }
1085
6760bd20
VK		 1086 return cpuid;
1087}
1088
1089/*
1090 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1091 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1092 */
1093static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 1094{
1095 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 1096 struct kvm_cpuid2 *cpuid;
1097 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1098
1099 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1100 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1101 cpuid->nent = 2;
1102
1103 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1104 entry_feat = &cpuid->entries[0];
1105 entry_feat->function = HV_CPUID_FEATURES;
1106
1107 entry_recomm = &cpuid->entries[1];
1108 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1109 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1110
1111 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1112 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1113 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1114 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1115 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1116 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1117 }
c35bd19a 1118
6760bd20
VK		 1119 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1120 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1121 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 1122 }
6760bd20
VK		 1123
1124 if (has_msr_hv_frequencies) {
1125 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1126 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 1127 }
6760bd20
VK		 1128
1129 if (has_msr_hv_crash) {
1130 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 1131 }
6760bd20
VK		 1132
1133 if (has_msr_hv_reenlightenment) {
1134 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 1135 }
6760bd20
VK		 1136
1137 if (has_msr_hv_reset) {
1138 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 1139 }
6760bd20
VK		 1140
1141 if (has_msr_hv_vpindex) {
1142 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 1143 }
6760bd20
VK		 1144
1145 if (has_msr_hv_runtime) {
1146 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 1147 }
6760bd20
VK		 1148
1149 if (has_msr_hv_synic) {
1150 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1151 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1152
1153 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1154 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 1155 }
c35bd19a 1156 }
6760bd20
VK		 1157
1158 if (has_msr_hv_stimer) {
1159 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 1160 }
9b4cf107 1161
73d24074
JD		 1162 if (has_msr_hv_syndbg_options) {
1163 entry_feat->edx |= HV_GUEST_DEBUGGING_AVAILABLE;
1164 entry_feat->edx |= HV_FEATURE_DEBUG_MSRS_AVAILABLE;
1165 entry_feat->ebx |= HV_PARTITION_DEBUGGING_ALLOWED;
1166 }
1167
6760bd20
VK		 1168 if (kvm_check_extension(cs->kvm_state,
1169 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1170 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1171 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1172 }
c35bd19a 1173
6760bd20
VK		 1174 if (kvm_check_extension(cs->kvm_state,
1175 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1176 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 1177 }
6760bd20
VK		 1178
1179 if (kvm_check_extension(cs->kvm_state,
1180 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1181 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1182 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 1183 }
6760bd20
VK		 1184
1185 return cpuid;
1186}
1187
a8439be6 1188static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
e1a66a1e
VK		 1189{
1190 struct kvm_cpuid_entry2 *entry;
a8439be6
VK		 1191 struct kvm_cpuid2 *cpuid;
1192
1193 if (hv_cpuid_cache) {
1194 cpuid = hv_cpuid_cache;
1195 } else {
1196 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1197 cpuid = get_supported_hv_cpuid(cs);
1198 } else {
e4adb09f
VK		 1199 /*
1200 * 'cs->kvm_state' may be NULL when Hyper-V features are expanded
1201 * before KVM context is created but this is only done when
1202 * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies
1203 * KVM_CAP_HYPERV_CPUID.
1204 */
1205 assert(cs->kvm_state);
1206
a8439be6
VK		 1207 cpuid = get_supported_hv_cpuid_legacy(cs);
1208 }
1209 hv_cpuid_cache = cpuid;
1210 }
1211
1212 if (!cpuid) {
1213 return 0;
1214 }
e1a66a1e
VK		 1215
1216 entry = cpuid_find_entry(cpuid, func, 0);
1217 if (!entry) {
1218 return 0;
1219 }
1220
1221 return cpuid_entry_get_reg(entry, reg);
1222}
1223
a8439be6 1224static bool hyperv_feature_supported(CPUState *cs, int feature)
7682f857 1225{
061817a7
VK		 1226 uint32_t func, bits;
1227 int i, reg;
7682f857
VK		 1228
1229 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
061817a7
VK		 1230
1231 func = kvm_hyperv_properties[feature].flags[i].func;
1232 reg = kvm_hyperv_properties[feature].flags[i].reg;
7682f857
VK		 1233 bits = kvm_hyperv_properties[feature].flags[i].bits;
1234
061817a7 1235 if (!func) {
7682f857
VK		 1236 continue;
1237 }
1238
a8439be6 1239 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
7682f857
VK		 1240 return false;
1241 }
1242 }
1243
1244 return true;
1245}
1246
5ce48fa3
VK		 1247/* Checks that all feature dependencies are enabled */
1248static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp)
6760bd20 1249{
c6861930 1250 uint64_t deps;
7682f857 1251 int dep_feat;
6760bd20 1252
c6861930 1253 deps = kvm_hyperv_properties[feature].dependencies;
9dc83cd9
HR		 1254 while (deps) {
1255 dep_feat = ctz64(deps);
c6861930 1256 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
f4a62495
VK		 1257 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1258 kvm_hyperv_properties[feature].desc,
1259 kvm_hyperv_properties[dep_feat].desc);
5ce48fa3 1260 return false;
c6861930 1261 }
9dc83cd9 1262 deps &= ~(1ull << dep_feat);
c6861930
VK		 1263 }
1264
5ce48fa3 1265 return true;
6760bd20
VK		 1266}
1267
061817a7 1268static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
c830015e
VK		 1269{
1270 X86CPU *cpu = X86_CPU(cs);
1271 uint32_t r = 0;
1272 int i, j;
1273
1274 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1275 if (!hyperv_feat_enabled(cpu, i)) {
1276 continue;
1277 }
1278
1279 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
061817a7
VK		 1280 if (kvm_hyperv_properties[i].flags[j].func != func) {
1281 continue;
1282 }
1283 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
c830015e
VK		 1284 continue;
1285 }
1286
1287 r |= kvm_hyperv_properties[i].flags[j].bits;
1288 }
1289 }
1290
7110fe56
VK		 1291 /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range */
1292 if (func == HV_CPUID_NESTED_FEATURES && reg == R_EAX) {
1293 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1294 r |= DEFAULT_EVMCS_VERSION;
1295 }
1296 }
1297
c830015e
VK		 1298 return r;
1299}
1300
2344d22e 1301/*
f6e01ab5
VK		 1302 * Expand Hyper-V CPU features. In partucular, check that all the requested
1303 * features are supported by the host and the sanity of the configuration
1304 * (that all the required dependencies are included). Also, this takes care
1305 * of 'hv_passthrough' mode and fills the environment with all supported
1306 * Hyper-V features.
2344d22e 1307 */
071ce4b0 1308bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp)
6760bd20 1309{
071ce4b0 1310 CPUState *cs = CPU(cpu);
5ce48fa3
VK		 1311 Error *local_err = NULL;
1312 int feat;
6760bd20 1313
2344d22e 1314 if (!hyperv_enabled(cpu))
d7652b77 1315 return true;
2344d22e 1316
071ce4b0
VK		 1317 /*
1318 * When kvm_hyperv_expand_features is called at CPU feature expansion
1319 * time per-CPU kvm_state is not available yet so we can only proceed
1320 * when KVM_CAP_SYS_HYPERV_CPUID is supported.
1321 */
1322 if (!cs->kvm_state &&
1323 !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID))
1324 return true;
1325
e48ddcc6 1326 if (cpu->hyperv_passthrough) {
e1a66a1e 1327 cpu->hyperv_vendor_id[0] =
a8439be6 1328 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
e1a66a1e 1329 cpu->hyperv_vendor_id[1] =
a8439be6 1330 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
e1a66a1e 1331 cpu->hyperv_vendor_id[2] =
a8439be6 1332 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
e1a66a1e
VK		 1333 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1334 sizeof(cpu->hyperv_vendor_id) + 1);
1335 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1336 sizeof(cpu->hyperv_vendor_id));
1337 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1338
1339 cpu->hyperv_interface_id[0] =
a8439be6 1340 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
e1a66a1e 1341 cpu->hyperv_interface_id[1] =
a8439be6 1342 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
e1a66a1e 1343 cpu->hyperv_interface_id[2] =
a8439be6 1344 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
e1a66a1e 1345 cpu->hyperv_interface_id[3] =
a8439be6 1346 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
e1a66a1e 1347
af7228b8 1348 cpu->hyperv_ver_id_build =
a8439be6 1349 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
af7228b8
VK		 1350 cpu->hyperv_ver_id_major =
1351 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16;
1352 cpu->hyperv_ver_id_minor =
1353 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff;
1354 cpu->hyperv_ver_id_sp =
a8439be6 1355 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
af7228b8
VK		 1356 cpu->hyperv_ver_id_sb =
1357 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24;
1358 cpu->hyperv_ver_id_sn =
1359 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff;
e1a66a1e 1360
a8439be6 1361 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
e1a66a1e
VK		 1362 R_EAX);
1363 cpu->hyperv_limits[0] =
a8439be6 1364 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
e1a66a1e 1365 cpu->hyperv_limits[1] =
a8439be6 1366 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
e1a66a1e 1367 cpu->hyperv_limits[2] =
a8439be6 1368 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
e1a66a1e
VK		 1369
1370 cpu->hyperv_spinlock_attempts =
a8439be6 1371 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
30d6ff66 1372
5ce48fa3
VK		 1373 /*
1374 * Mark feature as enabled in 'cpu->hyperv_features' as
1375 * hv_build_cpuid_leaf() uses this info to build guest CPUIDs.
1376 */
1377 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1378 if (hyperv_feature_supported(cs, feat)) {
1379 cpu->hyperv_features |= BIT(feat);
1380 }
1381 }
1382 } else {
1383 /* Check features availability and dependencies */
1384 for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) {
1385 /* If the feature was not requested skip it. */
1386 if (!hyperv_feat_enabled(cpu, feat)) {
1387 continue;
1388 }
1389
1390 /* Check if the feature is supported by KVM */
1391 if (!hyperv_feature_supported(cs, feat)) {
1392 error_setg(errp, "Hyper-V %s is not supported by kernel",
1393 kvm_hyperv_properties[feat].desc);
1394 return false;
1395 }
1396
1397 /* Check dependencies */
1398 if (!hv_feature_check_deps(cpu, feat, &local_err)) {
1399 error_propagate(errp, local_err);
1400 return false;
1401 }
1402 }
f4a62495 1403 }
6760bd20 1404
c6861930 1405 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1406 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1407 !cpu->hyperv_synic_kvm_only &&
1408 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
f4a62495
VK		 1409 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1410 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1411 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
d7652b77 1412 return false;
6760bd20 1413 }
d7652b77
VK		 1414
1415 return true;
f6e01ab5
VK		 1416}
1417
1418/*
1419 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1420 */
1421static int hyperv_fill_cpuids(CPUState *cs,
1422 struct kvm_cpuid_entry2 *cpuid_ent)
1423{
1424 X86CPU *cpu = X86_CPU(cs);
1425 struct kvm_cpuid_entry2 *c;
73d24074
JD		 1426 uint32_t signature[3];
1427 uint32_t cpuid_i = 0, max_cpuid_leaf = 0;
7110fe56
VK		 1428 uint32_t nested_eax =
1429 hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX);
73d24074 1430
7110fe56
VK		 1431 max_cpuid_leaf = nested_eax ? HV_CPUID_NESTED_FEATURES :
1432 HV_CPUID_IMPLEMENT_LIMITS;
73d24074
JD		 1433
1434 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1435 max_cpuid_leaf =
1436 MAX(max_cpuid_leaf, HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES);
1437 }
f6e01ab5 1438
2344d22e
VK		 1439 c = &cpuid_ent[cpuid_i++];
1440 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
73d24074 1441 c->eax = max_cpuid_leaf;
08856771
VK		 1442 c->ebx = cpu->hyperv_vendor_id[0];
1443 c->ecx = cpu->hyperv_vendor_id[1];
1444 c->edx = cpu->hyperv_vendor_id[2];
2344d22e
VK		 1445
1446 c = &cpuid_ent[cpuid_i++];
1447 c->function = HV_CPUID_INTERFACE;
735db465
VK		 1448 c->eax = cpu->hyperv_interface_id[0];
1449 c->ebx = cpu->hyperv_interface_id[1];
1450 c->ecx = cpu->hyperv_interface_id[2];
1451 c->edx = cpu->hyperv_interface_id[3];
2344d22e
VK		 1452
1453 c = &cpuid_ent[cpuid_i++];
1454 c->function = HV_CPUID_VERSION;
af7228b8
VK		 1455 c->eax = cpu->hyperv_ver_id_build;
1456 c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 |
1457 cpu->hyperv_ver_id_minor;
1458 c->ecx = cpu->hyperv_ver_id_sp;
1459 c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 |
1460 (cpu->hyperv_ver_id_sn & 0xffffff);
2344d22e
VK		 1461
1462 c = &cpuid_ent[cpuid_i++];
1463 c->function = HV_CPUID_FEATURES;
061817a7
VK		 1464 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1465 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1466 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
c830015e 1467
b26f68c3
VK		 1468 /* Unconditionally required with any Hyper-V enlightenment */
1469 c->eax |= HV_HYPERCALL_AVAILABLE;
1470
cce087f6
VK		 1471 /* SynIC and Vmbus devices require messages/signals hypercalls */
1472 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1473 !cpu->hyperv_synic_kvm_only) {
1474 c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS;
1475 }
1476
05071629 1477
c830015e
VK		 1478 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1479 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
2344d22e
VK		 1480
1481 c = &cpuid_ent[cpuid_i++];
1482 c->function = HV_CPUID_ENLIGHTMENT_INFO;
061817a7 1483 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
2344d22e
VK		 1484 c->ebx = cpu->hyperv_spinlock_attempts;
1485
e1f9a8e8
VK		 1486 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) &&
1487 !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) {
05071629
VK		 1488 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
1489 }
1490
c830015e
VK		 1491 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1492 c->eax |= HV_NO_NONARCH_CORESHARING;
1493 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
a8439be6 1494 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
e1a66a1e 1495 HV_NO_NONARCH_CORESHARING;
c830015e
VK		 1496 }
1497
2344d22e
VK		 1498 c = &cpuid_ent[cpuid_i++];
1499 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1500 c->eax = cpu->hv_max_vps;
23eb5d03
VK		 1501 c->ebx = cpu->hyperv_limits[0];
1502 c->ecx = cpu->hyperv_limits[1];
1503 c->edx = cpu->hyperv_limits[2];
2344d22e 1504
7110fe56 1505 if (nested_eax) {
dc7d6caf 1506 uint32_t function;
2344d22e
VK		 1507
1508 /* Create zeroed 0x40000006..0x40000009 leaves */
1509 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1510 function < HV_CPUID_NESTED_FEATURES; function++) {
1511 c = &cpuid_ent[cpuid_i++];
1512 c->function = function;
1513 }
1514
1515 c = &cpuid_ent[cpuid_i++];
1516 c->function = HV_CPUID_NESTED_FEATURES;
7110fe56 1517 c->eax = nested_eax;
2344d22e 1518 }
6760bd20 1519
73d24074
JD		 1520 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG)) {
1521 c = &cpuid_ent[cpuid_i++];
1522 c->function = HV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS;
1523 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1524 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1525 memcpy(signature, "Microsoft VS", 12);
1526 c->eax = 0;
1527 c->ebx = signature[0];
1528 c->ecx = signature[1];
1529 c->edx = signature[2];
1530
1531 c = &cpuid_ent[cpuid_i++];
1532 c->function = HV_CPUID_SYNDBG_INTERFACE;
1533 memcpy(signature, "VS#1\0\0\0\0\0\0\0\0", 12);
1534 c->eax = signature[0];
1535 c->ebx = 0;
1536 c->ecx = 0;
1537 c->edx = 0;
1538
1539 c = &cpuid_ent[cpuid_i++];
1540 c->function = HV_CPUID_SYNDBG_PLATFORM_CAPABILITIES;
1541 c->eax = HV_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING;
1542 c->ebx = 0;
1543 c->ecx = 0;
1544 c->edx = 0;
1545 }
1546
a8439be6 1547 return cpuid_i;
c35bd19a
EY		 1548}
1549
e48ddcc6 1550static Error *hv_passthrough_mig_blocker;
30d6ff66 1551static Error *hv_no_nonarch_cs_mig_blocker;
e48ddcc6 1552
07454e2e
VK		 1553/* Checks that the exposed eVMCS version range is supported by KVM */
1554static bool evmcs_version_supported(uint16_t evmcs_version,
1555 uint16_t supported_evmcs_version)
1556{
1557 uint8_t min_version = evmcs_version & 0xff;
1558 uint8_t max_version = evmcs_version >> 8;
1559 uint8_t min_supported_version = supported_evmcs_version & 0xff;
1560 uint8_t max_supported_version = supported_evmcs_version >> 8;
1561
1562 return (min_version >= min_supported_version) &&
1563 (max_version <= max_supported_version);
1564}
1565
e9688fab
RK		 1566static int hyperv_init_vcpu(X86CPU *cpu)
1567{
729ce7e1 1568 CPUState *cs = CPU(cpu);
e48ddcc6 1569 Error *local_err = NULL;
729ce7e1
RK		 1570 int ret;
1571
e48ddcc6
VK		 1572 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1573 error_setg(&hv_passthrough_mig_blocker,
1574 "'hv-passthrough' CPU flag prevents migration, use explicit"
1575 " set of hv-* flags instead");
1576 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
436c831a 1577 if (ret < 0) {
e48ddcc6 1578 error_report_err(local_err);
e48ddcc6
VK		 1579 return ret;
1580 }
1581 }
1582
30d6ff66
VK		 1583 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1584 hv_no_nonarch_cs_mig_blocker == NULL) {
1585 error_setg(&hv_no_nonarch_cs_mig_blocker,
1586 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1587 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1588 " make sure SMT is disabled and/or that vCPUs are properly"
1589 " pinned)");
1590 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
436c831a 1591 if (ret < 0) {
30d6ff66 1592 error_report_err(local_err);
30d6ff66
VK		 1593 return ret;
1594 }
1595 }
1596
2d384d7c 1597 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1598 /*
1599 * the kernel doesn't support setting vp_index; assert that its value
1600 * is in sync
1601 */
5a778a5f 1602 uint64_t value;
e9688fab 1603
5a778a5f 1604 ret = kvm_get_one_msr(cpu, HV_X64_MSR_VP_INDEX, &value);
e9688fab
RK		 1605 if (ret < 0) {
1606 return ret;
1607 }
e9688fab 1608
5a778a5f 1609 if (value != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1610 error_report("kernel's vp_index != QEMU's vp_index");
1611 return -ENXIO;
1612 }
1613 }
1614
2d384d7c 1615 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1616 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1617 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1618 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1619 if (ret < 0) {
1620 error_report("failed to turn on HyperV SynIC in KVM: %s",
1621 strerror(-ret));
1622 return ret;
1623 }
606c34bf 1624
9b4cf107
RK		 1625 if (!cpu->hyperv_synic_kvm_only) {
1626 ret = hyperv_x86_synic_add(cpu);
1627 if (ret < 0) {
1628 error_report("failed to create HyperV SynIC: %s",
1629 strerror(-ret));
1630 return ret;
1631 }
606c34bf 1632 }
729ce7e1
RK		 1633 }
1634
decb4f20 1635 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
07454e2e
VK		 1636 uint16_t evmcs_version = DEFAULT_EVMCS_VERSION;
1637 uint16_t supported_evmcs_version;
decb4f20
VK		 1638
1639 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
07454e2e 1640 (uintptr_t)&supported_evmcs_version);
decb4f20 1641
07454e2e
VK		 1642 /*
1643 * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs'
1644 * option sets. Note: we hardcode the maximum supported eVMCS version
1645 * to '1' as well so 'hv-evmcs' feature is migratable even when (and if)
1646 * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have
1647 * to be added.
1648 */
decb4f20 1649 if (ret < 0) {
07454e2e
VK		 1650 error_report("Hyper-V %s is not supported by kernel",
1651 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
decb4f20
VK		 1652 return ret;
1653 }
1654
07454e2e
VK		 1655 if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) {
1656 error_report("eVMCS version range [%d..%d] is not supported by "
1657 "kernel (supported: [%d..%d])", evmcs_version & 0xff,
1658 evmcs_version >> 8, supported_evmcs_version & 0xff,
1659 supported_evmcs_version >> 8);
1660 return -ENOTSUP;
1661 }
decb4f20
VK		 1662 }
1663
70367f09
VK		 1664 if (cpu->hyperv_enforce_cpuid) {
1665 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1);
1666 if (ret < 0) {
1667 error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s",
1668 strerror(-ret));
1669 return ret;
1670 }
1671 }
1672
e9688fab
RK		 1673 return 0;
1674}
1675
68bfd0ad
MT		 1676static Error *invtsc_mig_blocker;
1677
f8bb0565 1678#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1679
e56dd3c7
JL		 1680static void kvm_init_xsave(CPUX86State *env)
1681{
1682 if (has_xsave2) {
1683 env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096);
1684 } else if (has_xsave) {
1685 env->xsave_buf_len = sizeof(struct kvm_xsave);
1686 } else {
1687 return;
1688 }
1689
1690 env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len);
1691 memset(env->xsave_buf, 0, env->xsave_buf_len);
1692 /*
1693 * The allocated storage must be large enough for all of the
1694 * possible XSAVE state components.
1695 */
1696 assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=
1697 env->xsave_buf_len);
1698}
1699
3cafdb67
VK		 1700static void kvm_init_nested_state(CPUX86State *env)
1701{
1702 struct kvm_vmx_nested_state_hdr *vmx_hdr;
1703 uint32_t size;
1704
1705 if (!env->nested_state) {
1706 return;
1707 }
1708
1709 size = env->nested_state->size;
1710
1711 memset(env->nested_state, 0, size);
1712 env->nested_state->size = size;
1713
1714 if (cpu_has_vmx(env)) {
1715 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1716 vmx_hdr = &env->nested_state->hdr.vmx;
1717 vmx_hdr->vmxon_pa = -1ull;
1718 vmx_hdr->vmcs12_pa = -1ull;
1719 } else if (cpu_has_svm(env)) {
1720 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
1721 }
1722}
1723
20d695a9 1724int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1725{
1726 struct {
486bd5a2 1727 struct kvm_cpuid2 cpuid;
f8bb0565 1728 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1729 } cpuid_data;
1730 /*
1731 * The kernel defines these structs with padding fields so there
1732 * should be no extra padding in our cpuid_data struct.
1733 */
1734 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1735 sizeof(struct kvm_cpuid2) +
1736 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1737
20d695a9
AF		 1738 X86CPU *cpu = X86_CPU(cs);
1739 CPUX86State *env = &cpu->env;
486bd5a2 1740 uint32_t limit, i, j, cpuid_i;
a33609ca 1741 uint32_t unused;
bb0300dc 1742 struct kvm_cpuid_entry2 *c;
bb0300dc 1743 uint32_t signature[3];
234cc647 1744 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1745 int max_nested_state_len;
e7429073 1746 int r;
fe44dc91 1747 Error *local_err = NULL;
05330448 1748
ef4cbe14
SW		 1749 memset(&cpuid_data, 0, sizeof(cpuid_data));
1750
05330448
AL		 1751 cpuid_i = 0;
1752
e56dd3c7
JL		 1753 has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2);
1754
ddb98b5a
LP		 1755 r = kvm_arch_set_tsc_khz(cs);
1756 if (r < 0) {
6b2341ee 1757 return r;
ddb98b5a
LP		 1758 }
1759
1760 /* vcpu's TSC frequency is either specified by user, or following
1761 * the value used by KVM if the former is not present. In the
1762 * latter case, we query it from KVM and record in env->tsc_khz,
1763 * so that vcpu's TSC frequency can be migrated later via this field.
1764 */
1765 if (!env->tsc_khz) {
1766 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1767 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1768 -ENOTSUP;
1769 if (r > 0) {
1770 env->tsc_khz = r;
1771 }
1772 }
1773
73b994f6
LA		 1774 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1775
071ce4b0
VK		 1776 /*
1777 * kvm_hyperv_expand_features() is called here for the second time in case
1778 * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle
1779 * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to
1780 * check which Hyper-V enlightenments are supported and which are not, we
1781 * can still proceed and check/expand Hyper-V enlightenments here so legacy
1782 * behavior is preserved.
1783 */
1784 if (!kvm_hyperv_expand_features(cpu, &local_err)) {
f4a62495
VK		 1785 error_report_err(local_err);
1786 return -ENOSYS;
f6e01ab5
VK		 1787 }
1788
1789 if (hyperv_enabled(cpu)) {
decb4f20
VK		 1790 r = hyperv_init_vcpu(cpu);
1791 if (r) {
1792 return r;
1793 }
1794
f6e01ab5 1795 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
234cc647 1796 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1797 has_msr_hv_hypercall = true;
eab70139
VR		 1798 }
1799
f522d2ac
AW		 1800 if (cpu->expose_kvm) {
1801 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1802 c = &cpuid_data.entries[cpuid_i++];
1803 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1804 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1805 c->ebx = signature[0];
1806 c->ecx = signature[1];
1807 c->edx = signature[2];
234cc647 1808
f522d2ac
AW		 1809 c = &cpuid_data.entries[cpuid_i++];
1810 c->function = KVM_CPUID_FEATURES | kvm_base;
1811 c->eax = env->features[FEAT_KVM];
be777326 1812 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1813 }
917367aa 1814
a33609ca 1815 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448 1816
988f7b8b
VK		 1817 if (cpu->kvm_pv_enforce_cpuid) {
1818 r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1);
1819 if (r < 0) {
1820 fprintf(stderr,
1821 "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s",
1822 strerror(-r));
1823 abort();
1824 }
1825 }
1826
05330448 1827 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1828 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1829 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1830 abort();
1831 }
bb0300dc 1832 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1833
1834 switch (i) {
a36b1029
AL		 1835 case 2: {
1836 /* Keep reading function 2 till all the input is received */
1837 int times;
1838
a36b1029 1839 c->function = i;
a33609ca
AL		 1840 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1841 KVM_CPUID_FLAG_STATE_READ_NEXT;
1842 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1843 times = c->eax & 0xff;
a36b1029
AL		 1844
1845 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1846 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1847 fprintf(stderr, "cpuid_data is full, no space for "
1848 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1849 abort();
1850 }
a33609ca 1851 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1852 c->function = i;
a33609ca
AL		 1853 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1854 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1855 }
1856 break;
1857 }
a94e1428
LX		 1858 case 0x1f:
1859 if (env->nr_dies < 2) {
1860 break;
1861 }
8821e214 1862 /* fallthrough */
486bd5a2
AL		 1863 case 4:
1864 case 0xb:
1865 case 0xd:
1866 for (j = 0; ; j++) {
31e8c696
AP		 1867 if (i == 0xd && j == 64) {
1868 break;
1869 }
a94e1428
LX		 1870
1871 if (i == 0x1f && j == 64) {
1872 break;
1873 }
1874
486bd5a2
AL		 1875 c->function = i;
1876 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1877 c->index = j;
a33609ca 1878 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1879
b9bec74b 1880 if (i == 4 && c->eax == 0) {
486bd5a2 1881 break;
b9bec74b
JK		 1882 }
1883 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1884 break;
b9bec74b 1885 }
a94e1428
LX		 1886 if (i == 0x1f && !(c->ecx & 0xff00)) {
1887 break;
1888 }
b9bec74b 1889 if (i == 0xd && c->eax == 0) {
31e8c696 1890 continue;
b9bec74b 1891 }
f8bb0565
IM		 1892 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1893 fprintf(stderr, "cpuid_data is full, no space for "
1894 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1895 abort();
1896 }
a33609ca 1897 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1898 }
1899 break;
80db491d 1900 case 0x7:
b9edbade
SC		 1901 case 0x12:
1902 for (j = 0; ; j++) {
1903 c->function = i;
1904 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1905 c->index = j;
1906 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1907
1908 if (j > 1 && (c->eax & 0xf) != 1) {
1909 break;
1910 }
1911
1912 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1913 fprintf(stderr, "cpuid_data is full, no space for "
1914 "cpuid(eax:0x12,ecx:0x%x)\n", j);
1915 abort();
1916 }
1917 c = &cpuid_data.entries[cpuid_i++];
1918 }
1919 break;
f21a4817
JL		 1920 case 0x14:
1921 case 0x1d:
1922 case 0x1e: {
e37a5c7f
CP		 1923 uint32_t times;
1924
1925 c->function = i;
1926 c->index = 0;
1927 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1928 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1929 times = c->eax;
1930
1931 for (j = 1; j <= times; ++j) {
1932 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1933 fprintf(stderr, "cpuid_data is full, no space for "
80db491d 1934 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
e37a5c7f
CP		 1935 abort();
1936 }
1937 c = &cpuid_data.entries[cpuid_i++];
1938 c->function = i;
1939 c->index = j;
1940 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1941 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1942 }
1943 break;
1944 }
486bd5a2 1945 default:
486bd5a2 1946 c->function = i;
a33609ca
AL		 1947 c->flags = 0;
1948 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1949 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1950 /*
1951 * KVM already returns all zeroes if a CPUID entry is missing,
1952 * so we can omit it and avoid hitting KVM's 80-entry limit.
1953 */
1954 cpuid_i--;
1955 }
486bd5a2
AL		 1956 break;
1957 }
05330448 1958 }
0d894367
PB		 1959
1960 if (limit >= 0x0a) {
0b368a10 1961 uint32_t eax, edx;
0d894367 1962
0b368a10
JD		 1963 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1964
1965 has_architectural_pmu_version = eax & 0xff;
1966 if (has_architectural_pmu_version > 0) {
1967 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1968
1969 /* Shouldn't be more than 32, since that's the number of bits
1970 * available in EBX to tell us _which_ counters are available.
1971 * Play it safe.
1972 */
0b368a10
JD		 1973 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1974 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1975 }
1976
1977 if (has_architectural_pmu_version > 1) {
1978 num_architectural_pmu_fixed_counters = edx & 0x1f;
1979
1980 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1981 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1982 }
0d894367
PB		 1983 }
1984 }
1985 }
1986
a33609ca 1987 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1988
1989 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1990 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1991 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1992 abort();
1993 }
bb0300dc 1994 c = &cpuid_data.entries[cpuid_i++];
05330448 1995
8f4202fb
BM		 1996 switch (i) {
1997 case 0x8000001d:
1998 /* Query for all AMD cache information leaves */
1999 for (j = 0; ; j++) {
2000 c->function = i;
2001 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
2002 c->index = j;
2003 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
2004
2005 if (c->eax == 0) {
2006 break;
2007 }
2008 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2009 fprintf(stderr, "cpuid_data is full, no space for "
2010 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
2011 abort();
2012 }
2013 c = &cpuid_data.entries[cpuid_i++];
2014 }
2015 break;
2016 default:
2017 c->function = i;
2018 c->flags = 0;
2019 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 2020 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
2021 /*
2022 * KVM already returns all zeroes if a CPUID entry is missing,
2023 * so we can omit it and avoid hitting KVM's 80-entry limit.
2024 */
2025 cpuid_i--;
2026 }
8f4202fb
BM		 2027 break;
2028 }
05330448
AL		 2029 }
2030
b3baa152
BW		 2031 /* Call Centaur's CPUID instructions they are supported. */
2032 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 2033 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
2034
2035 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 2036 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
2037 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
2038 abort();
2039 }
b3baa152
BW		 2040 c = &cpuid_data.entries[cpuid_i++];
2041
2042 c->function = i;
2043 c->flags = 0;
2044 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
2045 }
2046 }
2047
05330448
AL		 2048 cpuid_data.cpuid.nent = cpuid_i;
2049
e7701825 2050 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 2051 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 2052 (CPUID_MCE | CPUID_MCA)
a60f24b5 2053 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 2054 uint64_t mcg_cap, unsupported_caps;
e7701825 2055 int banks;
32a42024 2056 int ret;
e7701825 2057
a60f24b5 2058 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 2059 if (ret < 0) {
2060 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
2061 return ret;
e7701825 2062 }
75d49497 2063
2590f15b 2064 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 2065 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 2066 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 2067 return -ENOTSUP;
75d49497 2068 }
49b69cbf 2069
5120901a
EH		 2070 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
2071 if (unsupported_caps) {
87f8b626
AR		 2072 if (unsupported_caps & MCG_LMCE_P) {
2073 error_report("kvm: LMCE not supported");
2074 return -ENOTSUP;
2075 }
3dc6f869
AF		 2076 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
2077 unsupported_caps);
5120901a
EH		 2078 }
2079
2590f15b
EH		 2080 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
2081 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 2082 if (ret < 0) {
2083 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
2084 return ret;
2085 }
e7701825 2086 }
e7701825 2087
2a693142 2088 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
b8cc45d6 2089
df67696e
LJ		 2090 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
2091 if (c) {
2092 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
2093 !!(c->ecx & CPUID_EXT_SMX);
2094 }
2095
a0483541
SC		 2096 c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0);
2097 if (c && (c->ebx & CPUID_7_0_EBX_SGX)) {
2098 has_msr_feature_control = true;
2099 }
2100
87f8b626
AR		 2101 if (env->mcg_cap & MCG_LMCE_P) {
2102 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
2103 }
2104
d99569d9
EH		 2105 if (!env->user_tsc_khz) {
2106 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
2107 invtsc_mig_blocker == NULL) {
d99569d9
EH		 2108 error_setg(&invtsc_mig_blocker,
2109 "State blocked by non-migratable CPU device"
2110 " (invtsc flag)");
fe44dc91 2111 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
436c831a 2112 if (r < 0) {
fe44dc91 2113 error_report_err(local_err);
79a197ab 2114 return r;
fe44dc91 2115 }
d99569d9 2116 }
68bfd0ad
MT		 2117 }
2118
9954a158
PDJ		 2119 if (cpu->vmware_cpuid_freq
2120 /* Guests depend on 0x40000000 to detect this feature, so only expose
2121 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
2122 && cpu->expose_kvm
2123 && kvm_base == KVM_CPUID_SIGNATURE
2124 /* TSC clock must be stable and known for this feature. */
4bb95b82 2125 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 2126
2127 c = &cpuid_data.entries[cpuid_i++];
2128 c->function = KVM_CPUID_SIGNATURE | 0x10;
2129 c->eax = env->tsc_khz;
73b994f6 2130 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
9954a158
PDJ		 2131 c->ecx = c->edx = 0;
2132
2133 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
2134 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
2135 }
2136
2137 cpuid_data.cpuid.nent = cpuid_i;
2138
2139 cpuid_data.cpuid.padding = 0;
2140 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
2141 if (r) {
2142 goto fail;
2143 }
e56dd3c7 2144 kvm_init_xsave(env);
ebbfef2f
LA		 2145
2146 max_nested_state_len = kvm_max_nested_state_length();
2147 if (max_nested_state_len > 0) {
2148 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
ebbfef2f 2149
b16c0e20 2150 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
1e44f3ab
PB		 2151 env->nested_state = g_malloc0(max_nested_state_len);
2152 env->nested_state->size = max_nested_state_len;
1e44f3ab 2153
3cafdb67 2154 kvm_init_nested_state(env);
ebbfef2f
LA		 2155 }
2156 }
2157
d71b62a1 2158 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 2159
273c515c
PB		 2160 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
2161 has_msr_tsc_aux = false;
2162 }
d1ae67f6 2163
420ae1fc
PB		 2164 kvm_init_msrs(cpu);
2165
e7429073 2166 return 0;
fe44dc91
AA		 2167
2168 fail:
2169 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 2170
fe44dc91 2171 return r;
05330448
AL		 2172}
2173
b1115c99
LA		 2174int kvm_arch_destroy_vcpu(CPUState *cs)
2175{
2176 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 2177 CPUX86State *env = &cpu->env;
b1115c99 2178
dcebbb65
PMD		 2179 g_free(env->xsave_buf);
2180
76eb88b1
MA		 2181 g_free(cpu->kvm_msr_buf);
2182 cpu->kvm_msr_buf = NULL;
b1115c99 2183
76eb88b1
MA		 2184 g_free(env->nested_state);
2185 env->nested_state = NULL;
ebbfef2f 2186
2a693142
PN		 2187 qemu_del_vm_change_state_handler(cpu->vmsentry);
2188
b1115c99
LA		 2189 return 0;
2190}
2191
50a2c6e5 2192void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 2193{
20d695a9 2194 CPUX86State *env = &cpu->env;
dd673288 2195
1a5e9d2f 2196 env->xcr0 = 1;
ddced198 2197 if (kvm_irqchip_in_kernel()) {
dd673288 2198 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 2199 KVM_MP_STATE_UNINITIALIZED;
2200 } else {
2201 env->mp_state = KVM_MP_STATE_RUNNABLE;
2202 }
689141dd 2203
2d384d7c 2204 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 2205 int i;
2206 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
2207 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
2208 }
606c34bf
RK		 2209
2210 hyperv_x86_synic_reset(cpu);
689141dd 2211 }
d645e132
MT		 2212 /* enabled by default */
2213 env->poll_control_msr = 1;
b2f73a07 2214
3cafdb67
VK		 2215 kvm_init_nested_state(env);
2216
b2f73a07 2217 sev_es_set_reset_vector(CPU(cpu));
caa5af0f
JK		 2218}
2219
e0723c45
PB		 2220void kvm_arch_do_init_vcpu(X86CPU *cpu)
2221{
2222 CPUX86State *env = &cpu->env;
2223
2224 /* APs get directly into wait-for-SIPI state. */
2225 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
2226 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
2227 }
2228}
2229
f57bceb6
RH		 2230static int kvm_get_supported_feature_msrs(KVMState *s)
2231{
2232 int ret = 0;
2233
2234 if (kvm_feature_msrs != NULL) {
2235 return 0;
2236 }
2237
2238 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
2239 return 0;
2240 }
2241
2242 struct kvm_msr_list msr_list;
2243
2244 msr_list.nmsrs = 0;
2245 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2246 if (ret < 0 && ret != -E2BIG) {
2247 error_report("Fetch KVM feature MSR list failed: %s",
2248 strerror(-ret));
2249 return ret;
2250 }
2251
2252 assert(msr_list.nmsrs > 0);
2253 kvm_feature_msrs = (struct kvm_msr_list *) \
2254 g_malloc0(sizeof(msr_list) +
2255 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2256
2257 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2258 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2259
2260 if (ret < 0) {
2261 error_report("Fetch KVM feature MSR list failed: %s",
2262 strerror(-ret));
2263 g_free(kvm_feature_msrs);
2264 kvm_feature_msrs = NULL;
2265 return ret;
2266 }
2267
2268 return 0;
2269}
2270
c3a3a7d3 2271static int kvm_get_supported_msrs(KVMState *s)
05330448 2272{
c3a3a7d3 2273 int ret = 0;
de428cea 2274 struct kvm_msr_list msr_list, *kvm_msr_list;
05330448 2275
de428cea
LQ		 2276 /*
2277 * Obtain MSR list from KVM. These are the MSRs that we must
2278 * save/restore.
2279 */
2280 msr_list.nmsrs = 0;
2281 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2282 if (ret < 0 && ret != -E2BIG) {
2283 return ret;
2284 }
2285 /*
2286 * Old kernel modules had a bug and could write beyond the provided
2287 * memory. Allocate at least a safe amount of 1K.
2288 */
2289 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2290 msr_list.nmsrs *
2291 sizeof(msr_list.indices[0])));
05330448 2292
de428cea
LQ		 2293 kvm_msr_list->nmsrs = msr_list.nmsrs;
2294 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2295 if (ret >= 0) {
2296 int i;
05330448 2297
de428cea
LQ		 2298 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2299 switch (kvm_msr_list->indices[i]) {
2300 case MSR_STAR:
2301 has_msr_star = true;
2302 break;
2303 case MSR_VM_HSAVE_PA:
2304 has_msr_hsave_pa = true;
2305 break;
2306 case MSR_TSC_AUX:
2307 has_msr_tsc_aux = true;
2308 break;
2309 case MSR_TSC_ADJUST:
2310 has_msr_tsc_adjust = true;
2311 break;
2312 case MSR_IA32_TSCDEADLINE:
2313 has_msr_tsc_deadline = true;
2314 break;
2315 case MSR_IA32_SMBASE:
2316 has_msr_smbase = true;
2317 break;
2318 case MSR_SMI_COUNT:
2319 has_msr_smi_count = true;
2320 break;
2321 case MSR_IA32_MISC_ENABLE:
2322 has_msr_misc_enable = true;
2323 break;
2324 case MSR_IA32_BNDCFGS:
2325 has_msr_bndcfgs = true;
2326 break;
2327 case MSR_IA32_XSS:
2328 has_msr_xss = true;
2329 break;
65087997
TX		 2330 case MSR_IA32_UMWAIT_CONTROL:
2331 has_msr_umwait = true;
2332 break;
de428cea
LQ		 2333 case HV_X64_MSR_CRASH_CTL:
2334 has_msr_hv_crash = true;
2335 break;
2336 case HV_X64_MSR_RESET:
2337 has_msr_hv_reset = true;
2338 break;
2339 case HV_X64_MSR_VP_INDEX:
2340 has_msr_hv_vpindex = true;
2341 break;
2342 case HV_X64_MSR_VP_RUNTIME:
2343 has_msr_hv_runtime = true;
2344 break;
2345 case HV_X64_MSR_SCONTROL:
2346 has_msr_hv_synic = true;
2347 break;
2348 case HV_X64_MSR_STIMER0_CONFIG:
2349 has_msr_hv_stimer = true;
2350 break;
2351 case HV_X64_MSR_TSC_FREQUENCY:
2352 has_msr_hv_frequencies = true;
2353 break;
2354 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2355 has_msr_hv_reenlightenment = true;
2356 break;
73d24074
JD		 2357 case HV_X64_MSR_SYNDBG_OPTIONS:
2358 has_msr_hv_syndbg_options = true;
2359 break;
de428cea
LQ		 2360 case MSR_IA32_SPEC_CTRL:
2361 has_msr_spec_ctrl = true;
2362 break;
cabf9862
ML		 2363 case MSR_AMD64_TSC_RATIO:
2364 has_tsc_scale_msr = true;
2365 break;
2a9758c5
PB		 2366 case MSR_IA32_TSX_CTRL:
2367 has_msr_tsx_ctrl = true;
2368 break;
de428cea
LQ		 2369 case MSR_VIRT_SSBD:
2370 has_msr_virt_ssbd = true;
2371 break;
2372 case MSR_IA32_ARCH_CAPABILITIES:
2373 has_msr_arch_capabs = true;
2374 break;
2375 case MSR_IA32_CORE_CAPABILITY:
2376 has_msr_core_capabs = true;
2377 break;
ea39f9b6
LX		 2378 case MSR_IA32_PERF_CAPABILITIES:
2379 has_msr_perf_capabs = true;
2380 break;
20a78b02
PB		 2381 case MSR_IA32_VMX_VMFUNC:
2382 has_msr_vmx_vmfunc = true;
2383 break;
67025148
PB		 2384 case MSR_IA32_UCODE_REV:
2385 has_msr_ucode_rev = true;
2386 break;
4a910e1f
VK		 2387 case MSR_IA32_VMX_PROCBASED_CTLS2:
2388 has_msr_vmx_procbased_ctls2 = true;
2389 break;
6aa4228b
CQ		 2390 case MSR_IA32_PKRS:
2391 has_msr_pkrs = true;
2392 break;
05330448
AL		 2393 }
2394 }
05330448
AL		 2395 }
2396
de428cea
LQ		 2397 g_free(kvm_msr_list);
2398
c3a3a7d3 2399 return ret;
05330448
AL		 2400}
2401
6410848b
PB		 2402static Notifier smram_machine_done;
2403static KVMMemoryListener smram_listener;
2404static AddressSpace smram_address_space;
2405static MemoryRegion smram_as_root;
2406static MemoryRegion smram_as_mem;
2407
2408static void register_smram_listener(Notifier *n, void *unused)
2409{
2410 MemoryRegion *smram =
2411 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2412
2413 /* Outer container... */
2414 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2415 memory_region_set_enabled(&smram_as_root, true);
2416
2417 /* ... with two regions inside: normal system memory with low
2418 * priority, and...
2419 */
2420 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2421 get_system_memory(), 0, ~0ull);
2422 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2423 memory_region_set_enabled(&smram_as_mem, true);
2424
2425 if (smram) {
2426 /* ... SMRAM with higher priority */
2427 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2428 memory_region_set_enabled(smram, true);
2429 }
2430
2431 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2432 kvm_memory_listener_register(kvm_state, &smram_listener,
142518bd 2433 &smram_address_space, 1, "kvm-smram");
6410848b
PB		 2434}
2435
b16565b3 2436int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 2437{
11076198 2438 uint64_t identity_base = 0xfffbc000;
39d6960a 2439 uint64_t shadow_mem;
20420430 2440 int ret;
25d2e361 2441 struct utsname utsname;
ec78e2cd
DG		 2442 Error *local_err = NULL;
2443
2444 /*
2445 * Initialize SEV context, if required
2446 *
2447 * If no memory encryption is requested (ms->cgs == NULL) this is
2448 * a no-op.
2449 *
2450 * It's also a no-op if a non-SEV confidential guest support
2451 * mechanism is selected. SEV is the only mechanism available to
2452 * select on x86 at present, so this doesn't arise, but if new
2453 * mechanisms are supported in future (e.g. TDX), they'll need
2454 * their own initialization either here or elsewhere.
2455 */
2456 ret = sev_kvm_init(ms->cgs, &local_err);
2457 if (ret < 0) {
2458 error_report_err(local_err);
2459 return ret;
2460 }
20420430 2461
1a6dff5f
EH		 2462 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2463 error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM");
2464 return -ENOTSUP;
2465 }
2466
28143b40 2467 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 2468 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 2469 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
8f515d38 2470 has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0;
28143b40 2471
e9688fab
RK		 2472 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2473
fd13f23b
LA		 2474 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2475 if (has_exception_payload) {
2476 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2477 if (ret < 0) {
2478 error_report("kvm: Failed to enable exception payload cap: %s",
2479 strerror(-ret));
2480 return ret;
2481 }
2482 }
2483
12f89a39
CQ		 2484 has_triple_fault_event = kvm_check_extension(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT);
2485 if (has_triple_fault_event) {
2486 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_TRIPLE_FAULT_EVENT, 0, true);
2487 if (ret < 0) {
2488 error_report("kvm: Failed to enable triple fault event cap: %s",
2489 strerror(-ret));
2490 return ret;
2491 }
2492 }
2493
c3a3a7d3 2494 ret = kvm_get_supported_msrs(s);
20420430 2495 if (ret < 0) {
20420430
SY		 2496 return ret;
2497 }
25d2e361 2498
f57bceb6
RH		 2499 kvm_get_supported_feature_msrs(s);
2500
25d2e361
MT		 2501 uname(&utsname);
2502 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2503
4c5b10b7 2504 /*
11076198
JK		 2505 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2506 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2507 * Since these must be part of guest physical memory, we need to allocate
2508 * them, both by setting their start addresses in the kernel and by
2509 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2510 *
2511 * Older KVM versions may not support setting the identity map base. In
2512 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2513 * size.
4c5b10b7 2514 */
11076198
JK		 2515 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2516 /* Allows up to 16M BIOSes. */
2517 identity_base = 0xfeffc000;
2518
2519 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2520 if (ret < 0) {
2521 return ret;
2522 }
4c5b10b7 2523 }
e56ff191 2524
11076198
JK		 2525 /* Set TSS base one page after EPT identity map. */
2526 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2527 if (ret < 0) {
2528 return ret;
2529 }
2530
11076198
JK		 2531 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2532 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2533 if (ret < 0) {
11076198 2534 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2535 return ret;
2536 }
2537
23b0898e 2538 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
36ad0e94
MA		 2539 if (shadow_mem != -1) {
2540 shadow_mem /= 4096;
2541 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2542 if (ret < 0) {
2543 return ret;
39d6960a
JK		 2544 }
2545 }
6410848b 2546
d870cfde 2547 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
8f54bbd0 2548 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
ed9e923c 2549 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
6410848b
PB		 2550 smram_machine_done.notify = register_smram_listener;
2551 qemu_add_machine_init_done_notifier(&smram_machine_done);
2552 }
6f131f13
MT		 2553
2554 if (enable_cpu_pm) {
2555 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2556 int ret;
2557
2558/* Work around for kernel header with a typo. TODO: fix header and drop. */
2559#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2560#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2561#endif
2562 if (disable_exits) {
2563 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2564 KVM_X86_DISABLE_EXITS_HLT |
d38d201f
WL		 2565 KVM_X86_DISABLE_EXITS_PAUSE |
2566 KVM_X86_DISABLE_EXITS_CSTATE);
6f131f13
MT		 2567 }
2568
2569 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2570 disable_exits);
2571 if (ret < 0) {
2572 error_report("kvm: guest stopping CPU not supported: %s",
2573 strerror(-ret));
2574 }
2575 }
2576
035d1ef2
CQ		 2577 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
2578 X86MachineState *x86ms = X86_MACHINE(ms);
2579
2580 if (x86ms->bus_lock_ratelimit > 0) {
2581 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
2582 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
2583 error_report("kvm: bus lock detection unsupported");
2584 return -ENOTSUP;
2585 }
2586 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
2587 KVM_BUS_LOCK_DETECTION_EXIT);
2588 if (ret < 0) {
2589 error_report("kvm: Failed to enable bus lock detection cap: %s",
2590 strerror(-ret));
2591 return ret;
2592 }
2593 ratelimit_init(&bus_lock_ratelimit_ctrl);
2594 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
2595 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
2596 }
2597 }
2598
e2e69f6b
CQ		 2599 if (s->notify_vmexit != NOTIFY_VMEXIT_OPTION_DISABLE &&
2600 kvm_check_extension(s, KVM_CAP_X86_NOTIFY_VMEXIT)) {
2601 uint64_t notify_window_flags =
2602 ((uint64_t)s->notify_window << 32) |
2603 KVM_X86_NOTIFY_VMEXIT_ENABLED |
2604 KVM_X86_NOTIFY_VMEXIT_USER;
2605 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_NOTIFY_VMEXIT, 0,
2606 notify_window_flags);
2607 if (ret < 0) {
2608 error_report("kvm: Failed to enable notify vmexit cap: %s",
2609 strerror(-ret));
2610 return ret;
2611 }
2612 }
2613
11076198 2614 return 0;
05330448 2615}
b9bec74b 2616
05330448
AL		 2617static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2618{
2619 lhs->selector = rhs->selector;
2620 lhs->base = rhs->base;
2621 lhs->limit = rhs->limit;
2622 lhs->type = 3;
2623 lhs->present = 1;
2624 lhs->dpl = 3;
2625 lhs->db = 0;
2626 lhs->s = 1;
2627 lhs->l = 0;
2628 lhs->g = 0;
2629 lhs->avl = 0;
2630 lhs->unusable = 0;
2631}
2632
2633static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2634{
2635 unsigned flags = rhs->flags;
2636 lhs->selector = rhs->selector;
2637 lhs->base = rhs->base;
2638 lhs->limit = rhs->limit;
2639 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2640 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2641 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2642 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2643 lhs->s = (flags & DESC_S_MASK) != 0;
2644 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2645 lhs->g = (flags & DESC_G_MASK) != 0;
2646 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2647 lhs->unusable = !lhs->present;
7e680753 2648 lhs->padding = 0;
05330448
AL		 2649}
2650
2651static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2652{
2653 lhs->selector = rhs->selector;
2654 lhs->base = rhs->base;
2655 lhs->limit = rhs->limit;
d45fc087
RP		 2656 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2657 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2658 (rhs->dpl << DESC_DPL_SHIFT) |
2659 (rhs->db << DESC_B_SHIFT) |
2660 (rhs->s * DESC_S_MASK) |
2661 (rhs->l << DESC_L_SHIFT) |
2662 (rhs->g * DESC_G_MASK) |
2663 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2664}
2665
2666static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2667{
b9bec74b 2668 if (set) {
05330448 2669 *kvm_reg = *qemu_reg;
b9bec74b 2670 } else {
05330448 2671 *qemu_reg = *kvm_reg;
b9bec74b 2672 }
05330448
AL		 2673}
2674
1bc22652 2675static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2676{
1bc22652 2677 CPUX86State *env = &cpu->env;
05330448
AL		 2678 struct kvm_regs regs;
2679 int ret = 0;
2680
2681 if (!set) {
1bc22652 2682 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2683 if (ret < 0) {
05330448 2684 return ret;
b9bec74b 2685 }
05330448
AL		 2686 }
2687
2688 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2689 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2690 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2691 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2692 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2693 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2694 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2695 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2696#ifdef TARGET_X86_64
2697 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2698 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2699 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2700 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2701 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2702 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2703 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2704 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2705#endif
2706
2707 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2708 kvm_getput_reg(&regs.rip, &env->eip, set);
2709
b9bec74b 2710 if (set) {
1bc22652 2711 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2712 }
05330448
AL		 2713
2714 return ret;
2715}
2716
1bc22652 2717static int kvm_put_fpu(X86CPU *cpu)
05330448 2718{
1bc22652 2719 CPUX86State *env = &cpu->env;
05330448
AL		 2720 struct kvm_fpu fpu;
2721 int i;
2722
2723 memset(&fpu, 0, sizeof fpu);
2724 fpu.fsw = env->fpus & ~(7 << 11);
2725 fpu.fsw |= (env->fpstt & 7) << 11;
2726 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2727 fpu.last_opcode = env->fpop;
2728 fpu.last_ip = env->fpip;
2729 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2730 for (i = 0; i < 8; ++i) {
2731 fpu.ftwx |= (!env->fptags[i]) << i;
2732 }
05330448 2733 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2734 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2735 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2736 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2737 }
05330448
AL		 2738 fpu.mxcsr = env->mxcsr;
2739
1bc22652 2740 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2741}
2742
1bc22652 2743static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2744{
1bc22652 2745 CPUX86State *env = &cpu->env;
c0198c5f 2746 void *xsave = env->xsave_buf;
f1665b21 2747
28143b40 2748 if (!has_xsave) {
1bc22652 2749 return kvm_put_fpu(cpu);
b9bec74b 2750 }
c0198c5f 2751 x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len);
f1665b21 2752
9be38598 2753 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2754}
2755
1bc22652 2756static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2757{
1bc22652 2758 CPUX86State *env = &cpu->env;
bdfc8480 2759 struct kvm_xcrs xcrs = {};
f1665b21 2760
28143b40 2761 if (!has_xcrs) {
f1665b21 2762 return 0;
b9bec74b 2763 }
f1665b21
SY		 2764
2765 xcrs.nr_xcrs = 1;
2766 xcrs.flags = 0;
2767 xcrs.xcrs[0].xcr = 0;
2768 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2769 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2770}
2771
1bc22652 2772static int kvm_put_sregs(X86CPU *cpu)
05330448 2773{
1bc22652 2774 CPUX86State *env = &cpu->env;
05330448
AL		 2775 struct kvm_sregs sregs;
2776
1520f8bb
PB		 2777 /*
2778 * The interrupt_bitmap is ignored because KVM_SET_SREGS is
2779 * always followed by KVM_SET_VCPU_EVENTS.
2780 */
0e607a80 2781 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
05330448
AL		 2782
2783 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2784 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2785 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2786 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2787 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2788 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2789 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2790 } else {
b9bec74b
JK		 2791 set_seg(&sregs.cs, &env->segs[R_CS]);
2792 set_seg(&sregs.ds, &env->segs[R_DS]);
2793 set_seg(&sregs.es, &env->segs[R_ES]);
2794 set_seg(&sregs.fs, &env->segs[R_FS]);
2795 set_seg(&sregs.gs, &env->segs[R_GS]);
2796 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2797 }
2798
2799 set_seg(&sregs.tr, &env->tr);
2800 set_seg(&sregs.ldt, &env->ldt);
2801
2802 sregs.idt.limit = env->idt.limit;
2803 sregs.idt.base = env->idt.base;
7e680753 2804 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2805 sregs.gdt.limit = env->gdt.limit;
2806 sregs.gdt.base = env->gdt.base;
7e680753 2807 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2808
2809 sregs.cr0 = env->cr[0];
2810 sregs.cr2 = env->cr[2];
2811 sregs.cr3 = env->cr[3];
2812 sregs.cr4 = env->cr[4];
2813
02e51483
CF		 2814 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2815 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2816
2817 sregs.efer = env->efer;
2818
1bc22652 2819 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2820}
2821
8f515d38
ML		 2822static int kvm_put_sregs2(X86CPU *cpu)
2823{
2824 CPUX86State *env = &cpu->env;
2825 struct kvm_sregs2 sregs;
2826 int i;
2827
2828 sregs.flags = 0;
2829
2830 if ((env->eflags & VM_MASK)) {
2831 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2832 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2833 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2834 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2835 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2836 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
2837 } else {
2838 set_seg(&sregs.cs, &env->segs[R_CS]);
2839 set_seg(&sregs.ds, &env->segs[R_DS]);
2840 set_seg(&sregs.es, &env->segs[R_ES]);
2841 set_seg(&sregs.fs, &env->segs[R_FS]);
2842 set_seg(&sregs.gs, &env->segs[R_GS]);
2843 set_seg(&sregs.ss, &env->segs[R_SS]);
2844 }
2845
2846 set_seg(&sregs.tr, &env->tr);
2847 set_seg(&sregs.ldt, &env->ldt);
2848
2849 sregs.idt.limit = env->idt.limit;
2850 sregs.idt.base = env->idt.base;
2851 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
2852 sregs.gdt.limit = env->gdt.limit;
2853 sregs.gdt.base = env->gdt.base;
2854 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
2855
2856 sregs.cr0 = env->cr[0];
2857 sregs.cr2 = env->cr[2];
2858 sregs.cr3 = env->cr[3];
2859 sregs.cr4 = env->cr[4];
2860
2861 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2862 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
2863
2864 sregs.efer = env->efer;
2865
2866 if (env->pdptrs_valid) {
2867 for (i = 0; i < 4; i++) {
2868 sregs.pdptrs[i] = env->pdptrs[i];
2869 }
2870 sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID;
2871 }
2872
2873 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs);
2874}
2875
2876
d71b62a1
EH		 2877static void kvm_msr_buf_reset(X86CPU *cpu)
2878{
2879 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2880}
2881
9c600a84
EH		 2882static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2883{
2884 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2885 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2886 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2887
2888 assert((void *)(entry + 1) <= limit);
2889
1abc2cae
EH		 2890 entry->index = index;
2891 entry->reserved = 0;
2892 entry->data = value;
9c600a84
EH		 2893 msrs->nmsrs++;
2894}
2895
73e1b8f2
PB		 2896static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2897{
2898 kvm_msr_buf_reset(cpu);
2899 kvm_msr_entry_add(cpu, index, value);
2900
2901 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2902}
2903
5a778a5f
YW		 2904static int kvm_get_one_msr(X86CPU *cpu, int index, uint64_t *value)
2905{
2906 int ret;
2907 struct {
2908 struct kvm_msrs info;
2909 struct kvm_msr_entry entries[1];
2910 } msr_data = {
2911 .info.nmsrs = 1,
2912 .entries[0].index = index,
2913 };
2914
2915 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
2916 if (ret < 0) {
2917 return ret;
2918 }
2919 assert(ret == 1);
2920 *value = msr_data.entries[0].data;
2921 return ret;
2922}
f8d9ccf8
DDAG		 2923void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2924{
2925 int ret;
2926
2927 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2928 assert(ret == 1);
2929}
2930
7477cd38
MT		 2931static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2932{
2933 CPUX86State *env = &cpu->env;
48e1a45c 2934 int ret;
7477cd38
MT		 2935
2936 if (!has_msr_tsc_deadline) {
2937 return 0;
2938 }
2939
73e1b8f2 2940 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2941 if (ret < 0) {
2942 return ret;
2943 }
2944
2945 assert(ret == 1);
2946 return 0;
7477cd38
MT		 2947}
2948
6bdf863d
JK		 2949/*
2950 * Provide a separate write service for the feature control MSR in order to
2951 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2952 * before writing any other state because forcibly leaving nested mode
2953 * invalidates the VCPU state.
2954 */
2955static int kvm_put_msr_feature_control(X86CPU *cpu)
2956{
48e1a45c
PB		 2957 int ret;
2958
2959 if (!has_msr_feature_control) {
2960 return 0;
2961 }
6bdf863d 2962
73e1b8f2
PB		 2963 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2964 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2965 if (ret < 0) {
2966 return ret;
2967 }
2968
2969 assert(ret == 1);
2970 return 0;
6bdf863d
JK		 2971}
2972
20a78b02
PB		 2973static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2974{
2975 uint32_t default1, can_be_one, can_be_zero;
2976 uint32_t must_be_one;
2977
2978 switch (index) {
2979 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2980 default1 = 0x00000016;
2981 break;
2982 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2983 default1 = 0x0401e172;
2984 break;
2985 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2986 default1 = 0x000011ff;
2987 break;
2988 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2989 default1 = 0x00036dff;
2990 break;
2991 case MSR_IA32_VMX_PROCBASED_CTLS2:
2992 default1 = 0;
2993 break;
2994 default:
2995 abort();
2996 }
2997
2998 /* If a feature bit is set, the control can be either set or clear.
2999 * Otherwise the value is limited to either 0 or 1 by default1.
3000 */
3001 can_be_one = features | default1;
3002 can_be_zero = features | ~default1;
3003 must_be_one = ~can_be_zero;
3004
3005 /*
3006 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
3007 * Bit 32:63 -> 1 if the control bit can be one.
3008 */
3009 return must_be_one | (((uint64_t)can_be_one) << 32);
3010}
3011
20a78b02
PB		 3012static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
3013{
3014 uint64_t kvm_vmx_basic =
3015 kvm_arch_get_supported_msr_feature(kvm_state,
3016 MSR_IA32_VMX_BASIC);
26051882
YZ		 3017
3018 if (!kvm_vmx_basic) {
3019 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
3020 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
3021 */
3022 return;
3023 }
3024
20a78b02
PB		 3025 uint64_t kvm_vmx_misc =
3026 kvm_arch_get_supported_msr_feature(kvm_state,
3027 MSR_IA32_VMX_MISC);
3028 uint64_t kvm_vmx_ept_vpid =
3029 kvm_arch_get_supported_msr_feature(kvm_state,
3030 MSR_IA32_VMX_EPT_VPID_CAP);
3031
3032 /*
3033 * If the guest is 64-bit, a value of 1 is allowed for the host address
3034 * space size vmexit control.
3035 */
3036 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
3037 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
3038
3039 /*
3040 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
3041 * not change them for backwards compatibility.
3042 */
3043 uint64_t fixed_vmx_basic = kvm_vmx_basic &
3044 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
3045 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
3046 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
3047
3048 /*
3049 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
3050 * change in the future but are always zero for now, clear them to be
3051 * future proof. Bits 32-63 in theory could change, though KVM does
3052 * not support dual-monitor treatment and probably never will; mask
3053 * them out as well.
3054 */
3055 uint64_t fixed_vmx_misc = kvm_vmx_misc &
3056 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
3057 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
3058
3059 /*
3060 * EPT memory types should not change either, so we do not bother
3061 * adding features for them.
3062 */
3063 uint64_t fixed_vmx_ept_mask =
3064 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
3065 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
3066 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
3067
3068 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3069 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
3070 f[FEAT_VMX_PROCBASED_CTLS]));
3071 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3072 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
3073 f[FEAT_VMX_PINBASED_CTLS]));
3074 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
3075 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
3076 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
3077 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3078 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
3079 f[FEAT_VMX_ENTRY_CTLS]));
3080 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
3081 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
3082 f[FEAT_VMX_SECONDARY_CTLS]));
3083 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
3084 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
3085 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
3086 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
3087 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
3088 f[FEAT_VMX_MISC] | fixed_vmx_misc);
3089 if (has_msr_vmx_vmfunc) {
3090 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
3091 }
3092
3093 /*
3094 * Just to be safe, write these with constant values. The CRn_FIXED1
3095 * MSRs are generated by KVM based on the vCPU's CPUID.
3096 */
3097 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
3098 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
3099 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
3100 CR4_VMXE_MASK);
9ce8af4d
PB		 3101
3102 if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
3103 /* TSC multiplier (0x2032). */
3104 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
3105 } else {
3106 /* Preemption timer (0x482E). */
3107 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
3108 }
20a78b02
PB		 3109}
3110
ea39f9b6
LX		 3111static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
3112{
3113 uint64_t kvm_perf_cap =
3114 kvm_arch_get_supported_msr_feature(kvm_state,
3115 MSR_IA32_PERF_CAPABILITIES);
3116
3117 if (kvm_perf_cap) {
3118 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
3119 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
3120 }
3121}
3122
420ae1fc
PB		 3123static int kvm_buf_set_msrs(X86CPU *cpu)
3124{
3125 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
3126 if (ret < 0) {
3127 return ret;
3128 }
3129
3130 if (ret < cpu->kvm_msr_buf->nmsrs) {
3131 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3132 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
3133 (uint32_t)e->index, (uint64_t)e->data);
3134 }
3135
3136 assert(ret == cpu->kvm_msr_buf->nmsrs);
3137 return 0;
3138}
3139
3140static void kvm_init_msrs(X86CPU *cpu)
3141{
3142 CPUX86State *env = &cpu->env;
3143
3144 kvm_msr_buf_reset(cpu);
3145 if (has_msr_arch_capabs) {
3146 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
3147 env->features[FEAT_ARCH_CAPABILITIES]);
3148 }
3149
3150 if (has_msr_core_capabs) {
3151 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
3152 env->features[FEAT_CORE_CAPABILITY]);
3153 }
3154
ea39f9b6
LX		 3155 if (has_msr_perf_capabs && cpu->enable_pmu) {
3156 kvm_msr_entry_add_perf(cpu, env->features);
3157 }
3158
67025148 3159 if (has_msr_ucode_rev) {
32c87d70
PB		 3160 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
3161 }
3162
420ae1fc
PB		 3163 /*
3164 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
3165 * all kernels with MSR features should have them.
3166 */
3167 if (kvm_feature_msrs && cpu_has_vmx(env)) {
3168 kvm_msr_entry_add_vmx(cpu, env->features);
3169 }
3170
3171 assert(kvm_buf_set_msrs(cpu) == 0);
3172}
3173
1bc22652 3174static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 3175{
1bc22652 3176 CPUX86State *env = &cpu->env;
9c600a84 3177 int i;
05330448 3178
d71b62a1
EH		 3179 kvm_msr_buf_reset(cpu);
3180
9c600a84
EH		 3181 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
3182 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
3183 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
3184 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 3185 if (has_msr_star) {
9c600a84 3186 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 3187 }
c3a3a7d3 3188 if (has_msr_hsave_pa) {
9c600a84 3189 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 3190 }
c9b8f6b6 3191 if (has_msr_tsc_aux) {
9c600a84 3192 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 3193 }
f28558d3 3194 if (has_msr_tsc_adjust) {
9c600a84 3195 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 3196 }
21e87c46 3197 if (has_msr_misc_enable) {
9c600a84 3198 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 3199 env->msr_ia32_misc_enable);
3200 }
fc12d72e 3201 if (has_msr_smbase) {
9c600a84 3202 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 3203 }
e13713db
LA		 3204 if (has_msr_smi_count) {
3205 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
3206 }
6aa4228b
CQ		 3207 if (has_msr_pkrs) {
3208 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
3209 }
439d19f2 3210 if (has_msr_bndcfgs) {
9c600a84 3211 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 3212 }
18cd2c17 3213 if (has_msr_xss) {
9c600a84 3214 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 3215 }
65087997
TX		 3216 if (has_msr_umwait) {
3217 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
3218 }
a33a2cfe
PB		 3219 if (has_msr_spec_ctrl) {
3220 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
3221 }
cabf9862
ML		 3222 if (has_tsc_scale_msr) {
3223 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr);
3224 }
3225
2a9758c5
PB		 3226 if (has_msr_tsx_ctrl) {
3227 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
3228 }
cfeea0c0
KRW		 3229 if (has_msr_virt_ssbd) {
3230 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
3231 }
3232
05330448 3233#ifdef TARGET_X86_64
25d2e361 3234 if (lm_capable_kernel) {
9c600a84
EH		 3235 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
3236 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
3237 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
3238 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 3239 }
05330448 3240#endif
a33a2cfe 3241
ff5c186b 3242 /*
0d894367
PB		 3243 * The following MSRs have side effects on the guest or are too heavy
3244 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 3245 */
3246 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 3247 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
3248 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
3249 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
6615be07
VK		 3250 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3251 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
3252 }
55c911a5 3253 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 3254 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 3255 }
55c911a5 3256 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3257 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 3258 }
55c911a5 3259 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3260 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 3261 }
d645e132
MT		 3262
3263 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3264 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
3265 }
3266
0b368a10
JD		 3267 if (has_architectural_pmu_version > 0) {
3268 if (has_architectural_pmu_version > 1) {
3269 /* Stop the counter. */
3270 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3271 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3272 }
0d894367
PB		 3273
3274 /* Set the counter values. */
0b368a10 3275 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3276 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 3277 env->msr_fixed_counters[i]);
3278 }
0b368a10 3279 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 3280 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 3281 env->msr_gp_counters[i]);
9c600a84 3282 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 3283 env->msr_gp_evtsel[i]);
3284 }
0b368a10
JD		 3285 if (has_architectural_pmu_version > 1) {
3286 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
3287 env->msr_global_status);
3288 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
3289 env->msr_global_ovf_ctrl);
3290
3291 /* Now start the PMU. */
3292 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
3293 env->msr_fixed_ctr_ctrl);
3294 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
3295 env->msr_global_ctrl);
3296 }
0d894367 3297 }
da1cc323
EY		 3298 /*
3299 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
3300 * only sync them to KVM on the first cpu
3301 */
3302 if (current_cpu == first_cpu) {
3303 if (has_msr_hv_hypercall) {
3304 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
3305 env->msr_hv_guest_os_id);
3306 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
3307 env->msr_hv_hypercall);
3308 }
2d384d7c 3309 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 3310 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
3311 env->msr_hv_tsc);
3312 }
2d384d7c 3313 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3314 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
3315 env->msr_hv_reenlightenment_control);
3316 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
3317 env->msr_hv_tsc_emulation_control);
3318 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
3319 env->msr_hv_tsc_emulation_status);
3320 }
d8701185 3321#ifdef CONFIG_SYNDBG
73d24074
JD		 3322 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNDBG) &&
3323 has_msr_hv_syndbg_options) {
3324 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS,
3325 hyperv_syndbg_query_options());
3326 }
d8701185 3327#endif
eab70139 3328 }
2d384d7c 3329 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3330 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 3331 env->msr_hv_vapic);
eab70139 3332 }
f2a53c9e
AS		 3333 if (has_msr_hv_crash) {
3334 int j;
3335
5e953812 3336 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 3337 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 3338 env->msr_hv_crash_params[j]);
3339
5e953812 3340 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 3341 }
46eb8f98 3342 if (has_msr_hv_runtime) {
9c600a84 3343 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 3344 }
2d384d7c
VK		 3345 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
3346 && hv_vpindex_settable) {
701189e3
RK		 3347 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
3348 hyperv_vp_index(CPU(cpu)));
e9688fab 3349 }
2d384d7c 3350 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3351 int j;
3352
09df29b6
RK		 3353 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
3354
9c600a84 3355 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 3356 env->msr_hv_synic_control);
9c600a84 3357 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 3358 env->msr_hv_synic_evt_page);
9c600a84 3359 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 3360 env->msr_hv_synic_msg_page);
3361
3362 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 3363 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 3364 env->msr_hv_synic_sint[j]);
3365 }
3366 }
ff99aa64
AS		 3367 if (has_msr_hv_stimer) {
3368 int j;
3369
3370 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 3371 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 3372 env->msr_hv_stimer_config[j]);
3373 }
3374
3375 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 3376 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 3377 env->msr_hv_stimer_count[j]);
3378 }
3379 }
1eabfce6 3380 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 3381 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
3382
9c600a84
EH		 3383 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
3384 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
3385 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
3386 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
3387 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
3388 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
3389 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
3390 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
3391 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
3392 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
3393 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
3394 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 3395 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 3396 /* The CPU GPs if we write to a bit above the physical limit of
3397 * the host CPU (and KVM emulates that)
3398 */
3399 uint64_t mask = env->mtrr_var[i].mask;
3400 mask &= phys_mask;
3401
9c600a84
EH		 3402 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
3403 env->mtrr_var[i].base);
112dad69 3404 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 3405 }
3406 }
b77146e9
CP		 3407 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3408 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
3409 0x14, 1, R_EAX) & 0x7;
3410
3411 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
3412 env->msr_rtit_ctrl);
3413 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
3414 env->msr_rtit_status);
3415 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
3416 env->msr_rtit_output_base);
3417 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
3418 env->msr_rtit_output_mask);
3419 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
3420 env->msr_rtit_cr3_match);
3421 for (i = 0; i < addr_num; i++) {
3422 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
3423 env->msr_rtit_addrs[i]);
3424 }
3425 }
6bdf863d 3426
db888065
SC		 3427 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
3428 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0,
3429 env->msr_ia32_sgxlepubkeyhash[0]);
3430 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1,
3431 env->msr_ia32_sgxlepubkeyhash[1]);
3432 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2,
3433 env->msr_ia32_sgxlepubkeyhash[2]);
3434 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3,
3435 env->msr_ia32_sgxlepubkeyhash[3]);
3436 }
3437
cdec2b75
ZG		 3438 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
3439 kvm_msr_entry_add(cpu, MSR_IA32_XFD,
3440 env->msr_xfd);
3441 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR,
3442 env->msr_xfd_err);
3443 }
3444
12703d4e
YW		 3445 if (kvm_enabled() && cpu->enable_pmu &&
3446 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
3447 uint64_t depth;
3448 int i, ret;
3449
3450 /*
3a7a27cf
YW		 3451 * Only migrate Arch LBR states when the host Arch LBR depth
3452 * equals that of source guest's, this is to avoid mismatch
3453 * of guest/host config for the msr hence avoid unexpected
3454 * misbehavior.
12703d4e
YW		 3455 */
3456 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
3457
3a7a27cf 3458 if (ret == 1 && !!depth && depth == env->msr_lbr_depth) {
12703d4e
YW		 3459 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, env->msr_lbr_ctl);
3460 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, env->msr_lbr_depth);
3461
3462 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
3463 if (!env->lbr_records[i].from) {
3464 continue;
3465 }
3466 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i,
3467 env->lbr_records[i].from);
3468 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i,
3469 env->lbr_records[i].to);
3470 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i,
3471 env->lbr_records[i].info);
3472 }
3473 }
3474 }
3475
6bdf863d
JK		 3476 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
3477 * kvm_put_msr_feature_control. */
ea643051 3478 }
20a78b02 3479
57780495 3480 if (env->mcg_cap) {
d8da8574 3481 int i;
b9bec74b 3482
9c600a84
EH		 3483 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
3484 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 3485 if (has_msr_mcg_ext_ctl) {
3486 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3487 }
c34d440a 3488 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3489 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 3490 }
3491 }
1a03675d 3492
420ae1fc 3493 return kvm_buf_set_msrs(cpu);
05330448
AL		 3494}
3495
3496
1bc22652 3497static int kvm_get_fpu(X86CPU *cpu)
05330448 3498{
1bc22652 3499 CPUX86State *env = &cpu->env;
05330448
AL		 3500 struct kvm_fpu fpu;
3501 int i, ret;
3502
1bc22652 3503 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 3504 if (ret < 0) {
05330448 3505 return ret;
b9bec74b 3506 }
05330448
AL		 3507
3508 env->fpstt = (fpu.fsw >> 11) & 7;
3509 env->fpus = fpu.fsw;
3510 env->fpuc = fpu.fcw;
42cc8fa6
JK		 3511 env->fpop = fpu.last_opcode;
3512 env->fpip = fpu.last_ip;
3513 env->fpdp = fpu.last_dp;
b9bec74b
JK		 3514 for (i = 0; i < 8; ++i) {
3515 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3516 }
05330448 3517 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 3518 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 3519 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3520 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 3521 }
05330448
AL		 3522 env->mxcsr = fpu.mxcsr;
3523
3524 return 0;
3525}
3526
1bc22652 3527static int kvm_get_xsave(X86CPU *cpu)
f1665b21 3528{
1bc22652 3529 CPUX86State *env = &cpu->env;
c0198c5f 3530 void *xsave = env->xsave_buf;
e56dd3c7 3531 int type, ret;
f1665b21 3532
28143b40 3533 if (!has_xsave) {
1bc22652 3534 return kvm_get_fpu(cpu);
b9bec74b 3535 }
f1665b21 3536
e56dd3c7
JL		 3537 type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE;
3538 ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave);
0f53994f 3539 if (ret < 0) {
f1665b21 3540 return ret;
0f53994f 3541 }
c0198c5f 3542 x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len);
f1665b21 3543
f1665b21 3544 return 0;
f1665b21
SY		 3545}
3546
1bc22652 3547static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 3548{
1bc22652 3549 CPUX86State *env = &cpu->env;
f1665b21
SY		 3550 int i, ret;
3551 struct kvm_xcrs xcrs;
3552
28143b40 3553 if (!has_xcrs) {
f1665b21 3554 return 0;
b9bec74b 3555 }
f1665b21 3556
1bc22652 3557 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 3558 if (ret < 0) {
f1665b21 3559 return ret;
b9bec74b 3560 }
f1665b21 3561
b9bec74b 3562 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 3563 /* Only support xcr0 now */
0fd53fec
PB		 3564 if (xcrs.xcrs[i].xcr == 0) {
3565 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 3566 break;
3567 }
b9bec74b 3568 }
f1665b21 3569 return 0;
f1665b21
SY		 3570}
3571
1bc22652 3572static int kvm_get_sregs(X86CPU *cpu)
05330448 3573{
1bc22652 3574 CPUX86State *env = &cpu->env;
05330448 3575 struct kvm_sregs sregs;
1520f8bb 3576 int ret;
05330448 3577
1bc22652 3578 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 3579 if (ret < 0) {
05330448 3580 return ret;
b9bec74b 3581 }
05330448 3582
1520f8bb
PB		 3583 /*
3584 * The interrupt_bitmap is ignored because KVM_GET_SREGS is
3585 * always preceded by KVM_GET_VCPU_EVENTS.
3586 */
05330448
AL		 3587
3588 get_seg(&env->segs[R_CS], &sregs.cs);
3589 get_seg(&env->segs[R_DS], &sregs.ds);
3590 get_seg(&env->segs[R_ES], &sregs.es);
3591 get_seg(&env->segs[R_FS], &sregs.fs);
3592 get_seg(&env->segs[R_GS], &sregs.gs);
3593 get_seg(&env->segs[R_SS], &sregs.ss);
3594
3595 get_seg(&env->tr, &sregs.tr);
3596 get_seg(&env->ldt, &sregs.ldt);
3597
3598 env->idt.limit = sregs.idt.limit;
3599 env->idt.base = sregs.idt.base;
3600 env->gdt.limit = sregs.gdt.limit;
3601 env->gdt.base = sregs.gdt.base;
3602
3603 env->cr[0] = sregs.cr0;
3604 env->cr[2] = sregs.cr2;
3605 env->cr[3] = sregs.cr3;
3606 env->cr[4] = sregs.cr4;
3607
05330448 3608 env->efer = sregs.efer;
cce47516
JK		 3609
3610 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 3611 x86_update_hflags(env);
05330448
AL		 3612
3613 return 0;
3614}
3615
8f515d38
ML		 3616static int kvm_get_sregs2(X86CPU *cpu)
3617{
3618 CPUX86State *env = &cpu->env;
3619 struct kvm_sregs2 sregs;
3620 int i, ret;
3621
3622 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs);
3623 if (ret < 0) {
3624 return ret;
3625 }
3626
3627 get_seg(&env->segs[R_CS], &sregs.cs);
3628 get_seg(&env->segs[R_DS], &sregs.ds);
3629 get_seg(&env->segs[R_ES], &sregs.es);
3630 get_seg(&env->segs[R_FS], &sregs.fs);
3631 get_seg(&env->segs[R_GS], &sregs.gs);
3632 get_seg(&env->segs[R_SS], &sregs.ss);
3633
3634 get_seg(&env->tr, &sregs.tr);
3635 get_seg(&env->ldt, &sregs.ldt);
3636
3637 env->idt.limit = sregs.idt.limit;
3638 env->idt.base = sregs.idt.base;
3639 env->gdt.limit = sregs.gdt.limit;
3640 env->gdt.base = sregs.gdt.base;
3641
3642 env->cr[0] = sregs.cr0;
3643 env->cr[2] = sregs.cr2;
3644 env->cr[3] = sregs.cr3;
3645 env->cr[4] = sregs.cr4;
3646
3647 env->efer = sregs.efer;
3648
3649 env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID;
3650
3651 if (env->pdptrs_valid) {
3652 for (i = 0; i < 4; i++) {
3653 env->pdptrs[i] = sregs.pdptrs[i];
3654 }
3655 }
3656
3657 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
3658 x86_update_hflags(env);
3659
3660 return 0;
3661}
3662
1bc22652 3663static int kvm_get_msrs(X86CPU *cpu)
05330448 3664{
1bc22652 3665 CPUX86State *env = &cpu->env;
d71b62a1 3666 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 3667 int ret, i;
fcc35e7c 3668 uint64_t mtrr_top_bits;
05330448 3669
d71b62a1
EH		 3670 kvm_msr_buf_reset(cpu);
3671
9c600a84
EH		 3672 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3673 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3674 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3675 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 3676 if (has_msr_star) {
9c600a84 3677 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 3678 }
c3a3a7d3 3679 if (has_msr_hsave_pa) {
9c600a84 3680 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 3681 }
c9b8f6b6 3682 if (has_msr_tsc_aux) {
9c600a84 3683 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 3684 }
f28558d3 3685 if (has_msr_tsc_adjust) {
9c600a84 3686 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 3687 }
aa82ba54 3688 if (has_msr_tsc_deadline) {
9c600a84 3689 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 3690 }
21e87c46 3691 if (has_msr_misc_enable) {
9c600a84 3692 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 3693 }
fc12d72e 3694 if (has_msr_smbase) {
9c600a84 3695 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 3696 }
e13713db
LA		 3697 if (has_msr_smi_count) {
3698 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3699 }
df67696e 3700 if (has_msr_feature_control) {
9c600a84 3701 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 3702 }
6aa4228b
CQ		 3703 if (has_msr_pkrs) {
3704 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
3705 }
79e9ebeb 3706 if (has_msr_bndcfgs) {
9c600a84 3707 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 3708 }
18cd2c17 3709 if (has_msr_xss) {
9c600a84 3710 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 3711 }
65087997
TX		 3712 if (has_msr_umwait) {
3713 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3714 }
a33a2cfe
PB		 3715 if (has_msr_spec_ctrl) {
3716 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3717 }
cabf9862
ML		 3718 if (has_tsc_scale_msr) {
3719 kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0);
3720 }
3721
2a9758c5
PB		 3722 if (has_msr_tsx_ctrl) {
3723 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3724 }
cfeea0c0
KRW		 3725 if (has_msr_virt_ssbd) {
3726 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3727 }
b8cc45d6 3728 if (!env->tsc_valid) {
9c600a84 3729 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 3730 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 3731 }
3732
05330448 3733#ifdef TARGET_X86_64
25d2e361 3734 if (lm_capable_kernel) {
9c600a84
EH		 3735 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3736 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3737 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3738 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 3739 }
05330448 3740#endif
9c600a84
EH		 3741 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3742 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
db5daafa
VK		 3743 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3744 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3745 }
6615be07
VK		 3746 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3747 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3748 }
55c911a5 3749 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3750 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 3751 }
55c911a5 3752 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3753 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 3754 }
d645e132
MT		 3755 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3756 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3757 }
0b368a10
JD		 3758 if (has_architectural_pmu_version > 0) {
3759 if (has_architectural_pmu_version > 1) {
3760 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3761 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3762 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3763 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3764 }
3765 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3766 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 3767 }
0b368a10 3768 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 3769 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3770 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 3771 }
3772 }
1a03675d 3773
57780495 3774 if (env->mcg_cap) {
9c600a84
EH		 3775 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3776 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 3777 if (has_msr_mcg_ext_ctl) {
3778 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3779 }
b9bec74b 3780 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3781 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 3782 }
57780495 3783 }
57780495 3784
1c90ef26 3785 if (has_msr_hv_hypercall) {
9c600a84
EH		 3786 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3787 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 3788 }
2d384d7c 3789 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3790 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 3791 }
2d384d7c 3792 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 3793 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 3794 }
2d384d7c 3795 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3796 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3797 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3798 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3799 }
73d24074
JD		 3800 if (has_msr_hv_syndbg_options) {
3801 kvm_msr_entry_add(cpu, HV_X64_MSR_SYNDBG_OPTIONS, 0);
3802 }
f2a53c9e
AS		 3803 if (has_msr_hv_crash) {
3804 int j;
3805
5e953812 3806 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 3807 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 3808 }
3809 }
46eb8f98 3810 if (has_msr_hv_runtime) {
9c600a84 3811 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 3812 }
2d384d7c 3813 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3814 uint32_t msr;
3815
9c600a84 3816 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 3817 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3818 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 3819 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 3820 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 3821 }
3822 }
ff99aa64
AS		 3823 if (has_msr_hv_stimer) {
3824 uint32_t msr;
3825
3826 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3827 msr++) {
9c600a84 3828 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 3829 }
3830 }
1eabfce6 3831 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 3832 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3833 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3834 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3835 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3836 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3837 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3838 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3839 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3840 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3841 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3842 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3843 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 3844 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 3845 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3846 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 3847 }
3848 }
5ef68987 3849
b77146e9
CP		 3850 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3851 int addr_num =
3852 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3853
3854 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3855 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3856 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3857 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3858 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3859 for (i = 0; i < addr_num; i++) {
3860 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3861 }
3862 }
3863
db888065
SC		 3864 if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) {
3865 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0);
3866 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0);
3867 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0);
3868 kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0);
3869 }
3870
cdec2b75
ZG		 3871 if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) {
3872 kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0);
3873 kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0);
3874 }
3875
12703d4e
YW		 3876 if (kvm_enabled() && cpu->enable_pmu &&
3877 (env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_ARCH_LBR)) {
3a7a27cf
YW		 3878 uint64_t depth;
3879 int i, ret;
12703d4e 3880
3a7a27cf
YW		 3881 ret = kvm_get_one_msr(cpu, MSR_ARCH_LBR_DEPTH, &depth);
3882 if (ret == 1 && depth == ARCH_LBR_NR_ENTRIES) {
12703d4e
YW		 3883 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_CTL, 0);
3884 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_DEPTH, 0);
3885
3886 for (i = 0; i < ARCH_LBR_NR_ENTRIES; i++) {
3887 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_FROM_0 + i, 0);
3888 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_TO_0 + i, 0);
3889 kvm_msr_entry_add(cpu, MSR_ARCH_LBR_INFO_0 + i, 0);
3890 }
3891 }
3892 }
3893
d71b62a1 3894 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 3895 if (ret < 0) {
05330448 3896 return ret;
b9bec74b 3897 }
05330448 3898
c70b11d1
EH		 3899 if (ret < cpu->kvm_msr_buf->nmsrs) {
3900 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3901 error_report("error: failed to get MSR 0x%" PRIx32,
3902 (uint32_t)e->index);
3903 }
3904
9c600a84 3905 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 3906 /*
3907 * MTRR masks: Each mask consists of 5 parts
3908 * a 10..0: must be zero
3909 * b 11 : valid bit
3910 * c n-1.12: actual mask bits
3911 * d 51..n: reserved must be zero
3912 * e 63.52: reserved must be zero
3913 *
3914 * 'n' is the number of physical bits supported by the CPU and is
3915 * apparently always <= 52. We know our 'n' but don't know what
3916 * the destinations 'n' is; it might be smaller, in which case
3917 * it masks (c) on loading. It might be larger, in which case
3918 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3919 * we're migrating to.
3920 */
3921
3922 if (cpu->fill_mtrr_mask) {
3923 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3924 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3925 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3926 } else {
3927 mtrr_top_bits = 0;
3928 }
3929
05330448 3930 for (i = 0; i < ret; i++) {
0d894367
PB		 3931 uint32_t index = msrs[i].index;
3932 switch (index) {
05330448
AL		 3933 case MSR_IA32_SYSENTER_CS:
3934 env->sysenter_cs = msrs[i].data;
3935 break;
3936 case MSR_IA32_SYSENTER_ESP:
3937 env->sysenter_esp = msrs[i].data;
3938 break;
3939 case MSR_IA32_SYSENTER_EIP:
3940 env->sysenter_eip = msrs[i].data;
3941 break;
0c03266a
JK		 3942 case MSR_PAT:
3943 env->pat = msrs[i].data;
3944 break;
05330448
AL		 3945 case MSR_STAR:
3946 env->star = msrs[i].data;
3947 break;
3948#ifdef TARGET_X86_64
3949 case MSR_CSTAR:
3950 env->cstar = msrs[i].data;
3951 break;
3952 case MSR_KERNELGSBASE:
3953 env->kernelgsbase = msrs[i].data;
3954 break;
3955 case MSR_FMASK:
3956 env->fmask = msrs[i].data;
3957 break;
3958 case MSR_LSTAR:
3959 env->lstar = msrs[i].data;
3960 break;
3961#endif
3962 case MSR_IA32_TSC:
3963 env->tsc = msrs[i].data;
3964 break;
c9b8f6b6
AS		 3965 case MSR_TSC_AUX:
3966 env->tsc_aux = msrs[i].data;
3967 break;
f28558d3
WA		 3968 case MSR_TSC_ADJUST:
3969 env->tsc_adjust = msrs[i].data;
3970 break;
aa82ba54
LJ		 3971 case MSR_IA32_TSCDEADLINE:
3972 env->tsc_deadline = msrs[i].data;
3973 break;
aa851e36
MT		 3974 case MSR_VM_HSAVE_PA:
3975 env->vm_hsave = msrs[i].data;
3976 break;
1a03675d
GC		 3977 case MSR_KVM_SYSTEM_TIME:
3978 env->system_time_msr = msrs[i].data;
3979 break;
3980 case MSR_KVM_WALL_CLOCK:
3981 env->wall_clock_msr = msrs[i].data;
3982 break;
57780495
MT		 3983 case MSR_MCG_STATUS:
3984 env->mcg_status = msrs[i].data;
3985 break;
3986 case MSR_MCG_CTL:
3987 env->mcg_ctl = msrs[i].data;
3988 break;
87f8b626
AR		 3989 case MSR_MCG_EXT_CTL:
3990 env->mcg_ext_ctl = msrs[i].data;
3991 break;
21e87c46
AK		 3992 case MSR_IA32_MISC_ENABLE:
3993 env->msr_ia32_misc_enable = msrs[i].data;
3994 break;
fc12d72e
PB		 3995 case MSR_IA32_SMBASE:
3996 env->smbase = msrs[i].data;
3997 break;
e13713db
LA		 3998 case MSR_SMI_COUNT:
3999 env->msr_smi_count = msrs[i].data;
4000 break;
0779caeb
ACL		 4001 case MSR_IA32_FEATURE_CONTROL:
4002 env->msr_ia32_feature_control = msrs[i].data;
df67696e 4003 break;
79e9ebeb
LJ		 4004 case MSR_IA32_BNDCFGS:
4005 env->msr_bndcfgs = msrs[i].data;
4006 break;
18cd2c17
WL		 4007 case MSR_IA32_XSS:
4008 env->xss = msrs[i].data;
4009 break;
65087997
TX		 4010 case MSR_IA32_UMWAIT_CONTROL:
4011 env->umwait = msrs[i].data;
4012 break;
6aa4228b
CQ		 4013 case MSR_IA32_PKRS:
4014 env->pkrs = msrs[i].data;
4015 break;
57780495 4016 default:
57780495
MT		 4017 if (msrs[i].index >= MSR_MC0_CTL &&
4018 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
4019 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 4020 }
d8da8574 4021 break;
f6584ee2
GN		 4022 case MSR_KVM_ASYNC_PF_EN:
4023 env->async_pf_en_msr = msrs[i].data;
4024 break;
db5daafa
VK		 4025 case MSR_KVM_ASYNC_PF_INT:
4026 env->async_pf_int_msr = msrs[i].data;
4027 break;
bc9a839d
MT		 4028 case MSR_KVM_PV_EOI_EN:
4029 env->pv_eoi_en_msr = msrs[i].data;
4030 break;
917367aa
MT		 4031 case MSR_KVM_STEAL_TIME:
4032 env->steal_time_msr = msrs[i].data;
4033 break;
d645e132
MT		 4034 case MSR_KVM_POLL_CONTROL: {
4035 env->poll_control_msr = msrs[i].data;
4036 break;
4037 }
0d894367
PB		 4038 case MSR_CORE_PERF_FIXED_CTR_CTRL:
4039 env->msr_fixed_ctr_ctrl = msrs[i].data;
4040 break;
4041 case MSR_CORE_PERF_GLOBAL_CTRL:
4042 env->msr_global_ctrl = msrs[i].data;
4043 break;
4044 case MSR_CORE_PERF_GLOBAL_STATUS:
4045 env->msr_global_status = msrs[i].data;
4046 break;
4047 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
4048 env->msr_global_ovf_ctrl = msrs[i].data;
4049 break;
4050 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
4051 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
4052 break;
4053 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
4054 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
4055 break;
4056 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
4057 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
4058 break;
1c90ef26
VR		 4059 case HV_X64_MSR_HYPERCALL:
4060 env->msr_hv_hypercall = msrs[i].data;
4061 break;
4062 case HV_X64_MSR_GUEST_OS_ID:
4063 env->msr_hv_guest_os_id = msrs[i].data;
4064 break;
5ef68987
VR		 4065 case HV_X64_MSR_APIC_ASSIST_PAGE:
4066 env->msr_hv_vapic = msrs[i].data;
4067 break;
48a5f3bc
VR		 4068 case HV_X64_MSR_REFERENCE_TSC:
4069 env->msr_hv_tsc = msrs[i].data;
4070 break;
f2a53c9e
AS		 4071 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
4072 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
4073 break;
46eb8f98
AS		 4074 case HV_X64_MSR_VP_RUNTIME:
4075 env->msr_hv_runtime = msrs[i].data;
4076 break;
866eea9a
AS		 4077 case HV_X64_MSR_SCONTROL:
4078 env->msr_hv_synic_control = msrs[i].data;
4079 break;
866eea9a
AS		 4080 case HV_X64_MSR_SIEFP:
4081 env->msr_hv_synic_evt_page = msrs[i].data;
4082 break;
4083 case HV_X64_MSR_SIMP:
4084 env->msr_hv_synic_msg_page = msrs[i].data;
4085 break;
4086 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
4087 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 4088 break;
4089 case HV_X64_MSR_STIMER0_CONFIG:
4090 case HV_X64_MSR_STIMER1_CONFIG:
4091 case HV_X64_MSR_STIMER2_CONFIG:
4092 case HV_X64_MSR_STIMER3_CONFIG:
4093 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
4094 msrs[i].data;
4095 break;
4096 case HV_X64_MSR_STIMER0_COUNT:
4097 case HV_X64_MSR_STIMER1_COUNT:
4098 case HV_X64_MSR_STIMER2_COUNT:
4099 case HV_X64_MSR_STIMER3_COUNT:
4100 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
4101 msrs[i].data;
866eea9a 4102 break;
ba6a4fd9
VK		 4103 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
4104 env->msr_hv_reenlightenment_control = msrs[i].data;
4105 break;
4106 case HV_X64_MSR_TSC_EMULATION_CONTROL:
4107 env->msr_hv_tsc_emulation_control = msrs[i].data;
4108 break;
4109 case HV_X64_MSR_TSC_EMULATION_STATUS:
4110 env->msr_hv_tsc_emulation_status = msrs[i].data;
4111 break;
73d24074
JD		 4112 case HV_X64_MSR_SYNDBG_OPTIONS:
4113 env->msr_hv_syndbg_options = msrs[i].data;
4114 break;
d1ae67f6
AW		 4115 case MSR_MTRRdefType:
4116 env->mtrr_deftype = msrs[i].data;
4117 break;
4118 case MSR_MTRRfix64K_00000:
4119 env->mtrr_fixed[0] = msrs[i].data;
4120 break;
4121 case MSR_MTRRfix16K_80000:
4122 env->mtrr_fixed[1] = msrs[i].data;
4123 break;
4124 case MSR_MTRRfix16K_A0000:
4125 env->mtrr_fixed[2] = msrs[i].data;
4126 break;
4127 case MSR_MTRRfix4K_C0000:
4128 env->mtrr_fixed[3] = msrs[i].data;
4129 break;
4130 case MSR_MTRRfix4K_C8000:
4131 env->mtrr_fixed[4] = msrs[i].data;
4132 break;
4133 case MSR_MTRRfix4K_D0000:
4134 env->mtrr_fixed[5] = msrs[i].data;
4135 break;
4136 case MSR_MTRRfix4K_D8000:
4137 env->mtrr_fixed[6] = msrs[i].data;
4138 break;
4139 case MSR_MTRRfix4K_E0000:
4140 env->mtrr_fixed[7] = msrs[i].data;
4141 break;
4142 case MSR_MTRRfix4K_E8000:
4143 env->mtrr_fixed[8] = msrs[i].data;
4144 break;
4145 case MSR_MTRRfix4K_F0000:
4146 env->mtrr_fixed[9] = msrs[i].data;
4147 break;
4148 case MSR_MTRRfix4K_F8000:
4149 env->mtrr_fixed[10] = msrs[i].data;
4150 break;
4151 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
4152 if (index & 1) {
fcc35e7c
DDAG		 4153 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
4154 mtrr_top_bits;
d1ae67f6
AW		 4155 } else {
4156 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
4157 }
4158 break;
a33a2cfe
PB		 4159 case MSR_IA32_SPEC_CTRL:
4160 env->spec_ctrl = msrs[i].data;
4161 break;
cabf9862
ML		 4162 case MSR_AMD64_TSC_RATIO:
4163 env->amd_tsc_scale_msr = msrs[i].data;
4164 break;
2a9758c5
PB		 4165 case MSR_IA32_TSX_CTRL:
4166 env->tsx_ctrl = msrs[i].data;
4167 break;
cfeea0c0
KRW		 4168 case MSR_VIRT_SSBD:
4169 env->virt_ssbd = msrs[i].data;
4170 break;
b77146e9
CP		 4171 case MSR_IA32_RTIT_CTL:
4172 env->msr_rtit_ctrl = msrs[i].data;
4173 break;
4174 case MSR_IA32_RTIT_STATUS:
4175 env->msr_rtit_status = msrs[i].data;
4176 break;
4177 case MSR_IA32_RTIT_OUTPUT_BASE:
4178 env->msr_rtit_output_base = msrs[i].data;
4179 break;
4180 case MSR_IA32_RTIT_OUTPUT_MASK:
4181 env->msr_rtit_output_mask = msrs[i].data;
4182 break;
4183 case MSR_IA32_RTIT_CR3_MATCH:
4184 env->msr_rtit_cr3_match = msrs[i].data;
4185 break;
4186 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
4187 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
4188 break;
db888065
SC		 4189 case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3:
4190 env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] =
4191 msrs[i].data;
4192 break;
cdec2b75
ZG		 4193 case MSR_IA32_XFD:
4194 env->msr_xfd = msrs[i].data;
4195 break;
4196 case MSR_IA32_XFD_ERR:
4197 env->msr_xfd_err = msrs[i].data;
4198 break;
12703d4e
YW		 4199 case MSR_ARCH_LBR_CTL:
4200 env->msr_lbr_ctl = msrs[i].data;
4201 break;
4202 case MSR_ARCH_LBR_DEPTH:
4203 env->msr_lbr_depth = msrs[i].data;
4204 break;
4205 case MSR_ARCH_LBR_FROM_0 ... MSR_ARCH_LBR_FROM_0 + 31:
4206 env->lbr_records[index - MSR_ARCH_LBR_FROM_0].from = msrs[i].data;
4207 break;
4208 case MSR_ARCH_LBR_TO_0 ... MSR_ARCH_LBR_TO_0 + 31:
4209 env->lbr_records[index - MSR_ARCH_LBR_TO_0].to = msrs[i].data;
4210 break;
4211 case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31:
4212 env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info = msrs[i].data;
4213 break;
05330448
AL		 4214 }
4215 }
4216
4217 return 0;
4218}
4219
1bc22652 4220static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 4221{
1bc22652 4222 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 4223
1bc22652 4224 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 4225}
4226
23d02d9b 4227static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 4228{
259186a7 4229 CPUState *cs = CPU(cpu);
23d02d9b 4230 CPUX86State *env = &cpu->env;
9bdbe550
HB		 4231 struct kvm_mp_state mp_state;
4232 int ret;
4233
259186a7 4234 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 4235 if (ret < 0) {
4236 return ret;
4237 }
4238 env->mp_state = mp_state.mp_state;
c14750e8 4239 if (kvm_irqchip_in_kernel()) {
259186a7 4240 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 4241 }
9bdbe550
HB		 4242 return 0;
4243}
4244
1bc22652 4245static int kvm_get_apic(X86CPU *cpu)
680c1c6f 4246{
02e51483 4247 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 4248 struct kvm_lapic_state kapic;
4249 int ret;
4250
3d4b2649 4251 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 4252 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 4253 if (ret < 0) {
4254 return ret;
4255 }
4256
4257 kvm_get_apic_state(apic, &kapic);
4258 }
4259 return 0;
4260}
4261
1bc22652 4262static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 4263{
fc12d72e 4264 CPUState *cs = CPU(cpu);
1bc22652 4265 CPUX86State *env = &cpu->env;
076796f8 4266 struct kvm_vcpu_events events = {};
a0fb002c
JK		 4267
4268 if (!kvm_has_vcpu_events()) {
4269 return 0;
4270 }
4271
fd13f23b
LA		 4272 events.flags = 0;
4273
4274 if (has_exception_payload) {
4275 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
4276 events.exception.pending = env->exception_pending;
4277 events.exception_has_payload = env->exception_has_payload;
4278 events.exception_payload = env->exception_payload;
4279 }
4280 events.exception.nr = env->exception_nr;
4281 events.exception.injected = env->exception_injected;
a0fb002c
JK		 4282 events.exception.has_error_code = env->has_error_code;
4283 events.exception.error_code = env->error_code;
4284
4285 events.interrupt.injected = (env->interrupt_injected >= 0);
4286 events.interrupt.nr = env->interrupt_injected;
4287 events.interrupt.soft = env->soft_interrupt;
4288
4289 events.nmi.injected = env->nmi_injected;
4290 events.nmi.pending = env->nmi_pending;
4291 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
4292
4293 events.sipi_vector = env->sipi_vector;
4294
fc12d72e
PB		 4295 if (has_msr_smbase) {
4296 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
4297 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
4298 if (kvm_irqchip_in_kernel()) {
4299 /* As soon as these are moved to the kernel, remove them
4300 * from cs->interrupt_request.
4301 */
4302 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
4303 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
4304 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
4305 } else {
4306 /* Keep these in cs->interrupt_request. */
4307 events.smi.pending = 0;
4308 events.smi.latched_init = 0;
4309 }
fc3a1fd7
DDAG		 4310 /* Stop SMI delivery on old machine types to avoid a reboot
4311 * on an inward migration of an old VM.
4312 */
4313 if (!cpu->kvm_no_smi_migration) {
4314 events.flags |= KVM_VCPUEVENT_VALID_SMM;
4315 }
fc12d72e
PB		 4316 }
4317
ea643051 4318 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 4319 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
4320 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
4321 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
4322 }
ea643051 4323 }
aee028b9 4324
12f89a39
CQ		 4325 if (has_triple_fault_event) {
4326 events.flags |= KVM_VCPUEVENT_VALID_TRIPLE_FAULT;
4327 events.triple_fault.pending = env->triple_fault_pending;
4328 }
4329
1bc22652 4330 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 4331}
4332
1bc22652 4333static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 4334{
1bc22652 4335 CPUX86State *env = &cpu->env;
a0fb002c
JK		 4336 struct kvm_vcpu_events events;
4337 int ret;
4338
4339 if (!kvm_has_vcpu_events()) {
4340 return 0;
4341 }
4342
fc12d72e 4343 memset(&events, 0, sizeof(events));
1bc22652 4344 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 4345 if (ret < 0) {
4346 return ret;
4347 }
fd13f23b
LA		 4348
4349 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
4350 env->exception_pending = events.exception.pending;
4351 env->exception_has_payload = events.exception_has_payload;
4352 env->exception_payload = events.exception_payload;
4353 } else {
4354 env->exception_pending = 0;
4355 env->exception_has_payload = false;
4356 }
4357 env->exception_injected = events.exception.injected;
4358 env->exception_nr =
4359 (env->exception_pending || env->exception_injected) ?
4360 events.exception.nr : -1;
a0fb002c
JK		 4361 env->has_error_code = events.exception.has_error_code;
4362 env->error_code = events.exception.error_code;
4363
4364 env->interrupt_injected =
4365 events.interrupt.injected ? events.interrupt.nr : -1;
4366 env->soft_interrupt = events.interrupt.soft;
4367
4368 env->nmi_injected = events.nmi.injected;
4369 env->nmi_pending = events.nmi.pending;
4370 if (events.nmi.masked) {
4371 env->hflags2 |= HF2_NMI_MASK;
4372 } else {
4373 env->hflags2 &= ~HF2_NMI_MASK;
4374 }
4375
fc12d72e
PB		 4376 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
4377 if (events.smi.smm) {
4378 env->hflags |= HF_SMM_MASK;
4379 } else {
4380 env->hflags &= ~HF_SMM_MASK;
4381 }
4382 if (events.smi.pending) {
4383 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
4384 } else {
4385 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
4386 }
4387 if (events.smi.smm_inside_nmi) {
4388 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
4389 } else {
4390 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
4391 }
4392 if (events.smi.latched_init) {
4393 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
4394 } else {
4395 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
4396 }
4397 }
4398
12f89a39
CQ		 4399 if (events.flags & KVM_VCPUEVENT_VALID_TRIPLE_FAULT) {
4400 env->triple_fault_pending = events.triple_fault.pending;
4401 }
4402
a0fb002c 4403 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 4404
4405 return 0;
4406}
4407
1bc22652 4408static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 4409{
ed2803da 4410 CPUState *cs = CPU(cpu);
1bc22652 4411 CPUX86State *env = &cpu->env;
b0b1d690 4412 int ret = 0;
b0b1d690
JK		 4413 unsigned long reinject_trap = 0;
4414
4415 if (!kvm_has_vcpu_events()) {
fd13f23b 4416 if (env->exception_nr == EXCP01_DB) {
b0b1d690 4417 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 4418 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 4419 reinject_trap = KVM_GUESTDBG_INJECT_BP;
4420 }
fd13f23b 4421 kvm_reset_exception(env);
b0b1d690
JK		 4422 }
4423
4424 /*
4425 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
4426 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
4427 * by updating the debug state once again if single-stepping is on.
4428 * Another reason to call kvm_update_guest_debug here is a pending debug
4429 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
4430 * reinject them via SET_GUEST_DEBUG.
4431 */
4432 if (reinject_trap ||
ed2803da 4433 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 4434 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 4435 }
b0b1d690
JK		 4436 return ret;
4437}
4438
1bc22652 4439static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 4440{
1bc22652 4441 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 4442 struct kvm_debugregs dbgregs;
4443 int i;
4444
4445 if (!kvm_has_debugregs()) {
4446 return 0;
4447 }
4448
1f670a95 4449 memset(&dbgregs, 0, sizeof(dbgregs));
ff44f1a3
JK		 4450 for (i = 0; i < 4; i++) {
4451 dbgregs.db[i] = env->dr[i];
4452 }
4453 dbgregs.dr6 = env->dr[6];
4454 dbgregs.dr7 = env->dr[7];
4455 dbgregs.flags = 0;
4456
1bc22652 4457 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 4458}
4459
1bc22652 4460static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 4461{
1bc22652 4462 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 4463 struct kvm_debugregs dbgregs;
4464 int i, ret;
4465
4466 if (!kvm_has_debugregs()) {
4467 return 0;
4468 }
4469
1bc22652 4470 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 4471 if (ret < 0) {
b9bec74b 4472 return ret;
ff44f1a3
JK		 4473 }
4474 for (i = 0; i < 4; i++) {
4475 env->dr[i] = dbgregs.db[i];
4476 }
4477 env->dr[4] = env->dr[6] = dbgregs.dr6;
4478 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 4479
4480 return 0;
4481}
4482
ebbfef2f
LA		 4483static int kvm_put_nested_state(X86CPU *cpu)
4484{
4485 CPUX86State *env = &cpu->env;
4486 int max_nested_state_len = kvm_max_nested_state_length();
4487
1e44f3ab 4488 if (!env->nested_state) {
ebbfef2f
LA		 4489 return 0;
4490 }
4491
b16c0e20
PB		 4492 /*
4493 * Copy flags that are affected by reset from env->hflags and env->hflags2.
4494 */
4495 if (env->hflags & HF_GUEST_MASK) {
4496 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
4497 } else {
4498 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
4499 }
0baa4b44
VK		 4500
4501 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
4502 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
b16c0e20
PB		 4503 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
4504 } else {
4505 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
4506 }
4507
ebbfef2f
LA		 4508 assert(env->nested_state->size <= max_nested_state_len);
4509 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
4510}
4511
4512static int kvm_get_nested_state(X86CPU *cpu)
4513{
4514 CPUX86State *env = &cpu->env;
4515 int max_nested_state_len = kvm_max_nested_state_length();
4516 int ret;
4517
1e44f3ab 4518 if (!env->nested_state) {
ebbfef2f
LA		 4519 return 0;
4520 }
4521
4522 /*
4523 * It is possible that migration restored a smaller size into
4524 * nested_state->hdr.size than what our kernel support.
4525 * We preserve migration origin nested_state->hdr.size for
4526 * call to KVM_SET_NESTED_STATE but wish that our next call
4527 * to KVM_GET_NESTED_STATE will use max size our kernel support.
4528 */
4529 env->nested_state->size = max_nested_state_len;
4530
4531 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
4532 if (ret < 0) {
4533 return ret;
4534 }
4535
b16c0e20
PB		 4536 /*
4537 * Copy flags that are affected by reset to env->hflags and env->hflags2.
4538 */
ebbfef2f
LA		 4539 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
4540 env->hflags |= HF_GUEST_MASK;
4541 } else {
4542 env->hflags &= ~HF_GUEST_MASK;
4543 }
0baa4b44
VK		 4544
4545 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
4546 if (cpu_has_svm(env)) {
4547 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
4548 env->hflags2 |= HF2_GIF_MASK;
4549 } else {
4550 env->hflags2 &= ~HF2_GIF_MASK;
4551 }
b16c0e20 4552 }
ebbfef2f
LA		 4553
4554 return ret;
4555}
4556
20d695a9 4557int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 4558{
20d695a9 4559 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 4560 int ret;
4561
2fa45344 4562 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 4563
45ed68a1
VK		 4564 /*
4565 * Put MSR_IA32_FEATURE_CONTROL first, this ensures the VM gets out of VMX
4566 * root operation upon vCPU reset. kvm_put_msr_feature_control() should also
4567 * preceed kvm_put_nested_state() when 'real' nested state is set.
4568 */
4569 if (level >= KVM_PUT_RESET_STATE) {
4570 ret = kvm_put_msr_feature_control(x86_cpu);
4571 if (ret < 0) {
4572 return ret;
4573 }
4574 }
4575
b16c0e20 4576 /* must be before kvm_put_nested_state so that EFER.SVME is set */
8f515d38 4577 ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu);
b16c0e20
PB		 4578 if (ret < 0) {
4579 return ret;
4580 }
4581
48e1a45c 4582 if (level >= KVM_PUT_RESET_STATE) {
bec7156a
JK		 4583 ret = kvm_put_nested_state(x86_cpu);
4584 if (ret < 0) {
4585 return ret;
4586 }
6bdf863d
JK		 4587 }
4588
36f96c4b
HZ		 4589 if (level == KVM_PUT_FULL_STATE) {
4590 /* We don't check for kvm_arch_set_tsc_khz() errors here,
4591 * because TSC frequency mismatch shouldn't abort migration,
4592 * unless the user explicitly asked for a more strict TSC
4593 * setting (e.g. using an explicit "tsc-freq" option).
4594 */
4595 kvm_arch_set_tsc_khz(cpu);
4596 }
4597
1bc22652 4598 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 4599 if (ret < 0) {
05330448 4600 return ret;
b9bec74b 4601 }
1bc22652 4602 ret = kvm_put_xsave(x86_cpu);
b9bec74b 4603 if (ret < 0) {
f1665b21 4604 return ret;
b9bec74b 4605 }
1bc22652 4606 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 4607 if (ret < 0) {
05330448 4608 return ret;
b9bec74b 4609 }
ab443475 4610 /* must be before kvm_put_msrs */
1bc22652 4611 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 4612 if (ret < 0) {
4613 return ret;
4614 }
1bc22652 4615 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 4616 if (ret < 0) {
05330448 4617 return ret;
b9bec74b 4618 }
4fadfa00
PH		 4619 ret = kvm_put_vcpu_events(x86_cpu, level);
4620 if (ret < 0) {
4621 return ret;
4622 }
ea643051 4623 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 4624 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 4625 if (ret < 0) {
680c1c6f
JK		 4626 return ret;
4627 }
ea643051 4628 }
7477cd38
MT		 4629
4630 ret = kvm_put_tscdeadline_msr(x86_cpu);
4631 if (ret < 0) {
4632 return ret;
4633 }
1bc22652 4634 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 4635 if (ret < 0) {
b0b1d690 4636 return ret;
b9bec74b 4637 }
b0b1d690 4638 /* must be last */
1bc22652 4639 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 4640 if (ret < 0) {
ff44f1a3 4641 return ret;
b9bec74b 4642 }
05330448
AL		 4643 return 0;
4644}
4645
20d695a9 4646int kvm_arch_get_registers(CPUState *cs)
05330448 4647{
20d695a9 4648 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 4649 int ret;
4650
20d695a9 4651 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 4652
4fadfa00 4653 ret = kvm_get_vcpu_events(cpu);
b9bec74b 4654 if (ret < 0) {
f4f1110e 4655 goto out;
b9bec74b 4656 }
4fadfa00
PH		 4657 /*
4658 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4659 * KVM_GET_REGS and KVM_GET_SREGS.
4660 */
4661 ret = kvm_get_mp_state(cpu);
b9bec74b 4662 if (ret < 0) {
f4f1110e 4663 goto out;
b9bec74b 4664 }
4fadfa00 4665 ret = kvm_getput_regs(cpu, 0);
b9bec74b 4666 if (ret < 0) {
f4f1110e 4667 goto out;
b9bec74b 4668 }
4fadfa00 4669 ret = kvm_get_xsave(cpu);
b9bec74b 4670 if (ret < 0) {
f4f1110e 4671 goto out;
b9bec74b 4672 }
4fadfa00 4673 ret = kvm_get_xcrs(cpu);
b9bec74b 4674 if (ret < 0) {
f4f1110e 4675 goto out;
b9bec74b 4676 }
8f515d38 4677 ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu);
b9bec74b 4678 if (ret < 0) {
f4f1110e 4679 goto out;
b9bec74b 4680 }
4fadfa00 4681 ret = kvm_get_msrs(cpu);
680c1c6f 4682 if (ret < 0) {
f4f1110e 4683 goto out;
680c1c6f 4684 }
4fadfa00 4685 ret = kvm_get_apic(cpu);
b9bec74b 4686 if (ret < 0) {
f4f1110e 4687 goto out;
b9bec74b 4688 }
1bc22652 4689 ret = kvm_get_debugregs(cpu);
b9bec74b 4690 if (ret < 0) {
f4f1110e 4691 goto out;
b9bec74b 4692 }
ebbfef2f
LA		 4693 ret = kvm_get_nested_state(cpu);
4694 if (ret < 0) {
4695 goto out;
4696 }
f4f1110e
RH		 4697 ret = 0;
4698 out:
4699 cpu_sync_bndcs_hflags(&cpu->env);
4700 return ret;
05330448
AL		 4701}
4702
20d695a9 4703void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 4704{
20d695a9
AF		 4705 X86CPU *x86_cpu = X86_CPU(cpu);
4706 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 4707 int ret;
4708
276ce815 4709 /* Inject NMI */
fc12d72e
PB		 4710 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4711 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4712 qemu_mutex_lock_iothread();
4713 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4714 qemu_mutex_unlock_iothread();
4715 DPRINTF("injected NMI\n");
4716 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4717 if (ret < 0) {
4718 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4719 strerror(-ret));
4720 }
4721 }
4722 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4723 qemu_mutex_lock_iothread();
4724 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4725 qemu_mutex_unlock_iothread();
4726 DPRINTF("injected SMI\n");
4727 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4728 if (ret < 0) {
4729 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4730 strerror(-ret));
4731 }
ce377af3 4732 }
276ce815
LJ		 4733 }
4734
15eafc2e 4735 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 4736 qemu_mutex_lock_iothread();
4737 }
4738
e0723c45
PB		 4739 /* Force the VCPU out of its inner loop to process any INIT requests
4740 * or (for userspace APIC, but it is cheap to combine the checks here)
4741 * pending TPR access reports.
4742 */
4743 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 4744 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4745 !(env->hflags & HF_SMM_MASK)) {
4746 cpu->exit_request = 1;
4747 }
4748 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4749 cpu->exit_request = 1;
4750 }
e0723c45 4751 }
05330448 4752
15eafc2e 4753 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 4754 /* Try to inject an interrupt if the guest can accept it */
4755 if (run->ready_for_interrupt_injection &&
259186a7 4756 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 4757 (env->eflags & IF_MASK)) {
4758 int irq;
4759
259186a7 4760 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 4761 irq = cpu_get_pic_interrupt(env);
4762 if (irq >= 0) {
4763 struct kvm_interrupt intr;
4764
4765 intr.irq = irq;
db1669bc 4766 DPRINTF("injected interrupt %d\n", irq);
1bc22652 4767 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 4768 if (ret < 0) {
4769 fprintf(stderr,
4770 "KVM: injection failed, interrupt lost (%s)\n",
4771 strerror(-ret));
4772 }
db1669bc
JK		 4773 }
4774 }
05330448 4775
db1669bc
JK		 4776 /* If we have an interrupt but the guest is not ready to receive an
4777 * interrupt, request an interrupt window exit. This will
4778 * cause a return to userspace as soon as the guest is ready to
4779 * receive interrupts. */
259186a7 4780 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 4781 run->request_interrupt_window = 1;
4782 } else {
4783 run->request_interrupt_window = 0;
4784 }
4785
4786 DPRINTF("setting tpr\n");
02e51483 4787 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 4788
4789 qemu_mutex_unlock_iothread();
db1669bc 4790 }
05330448
AL		 4791}
4792
035d1ef2
CQ		 4793static void kvm_rate_limit_on_bus_lock(void)
4794{
4795 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
4796
4797 if (delay_ns) {
4798 g_usleep(delay_ns / SCALE_US);
4799 }
4800}
4801
4c663752 4802MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 4803{
20d695a9
AF		 4804 X86CPU *x86_cpu = X86_CPU(cpu);
4805 CPUX86State *env = &x86_cpu->env;
4806
fc12d72e
PB		 4807 if (run->flags & KVM_RUN_X86_SMM) {
4808 env->hflags |= HF_SMM_MASK;
4809 } else {
f5c052b9 4810 env->hflags &= ~HF_SMM_MASK;
fc12d72e 4811 }
b9bec74b 4812 if (run->if_flag) {
05330448 4813 env->eflags |= IF_MASK;
b9bec74b 4814 } else {
05330448 4815 env->eflags &= ~IF_MASK;
b9bec74b 4816 }
035d1ef2
CQ		 4817 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
4818 kvm_rate_limit_on_bus_lock();
4819 }
4b8523ee
JK		 4820
4821 /* We need to protect the apic state against concurrent accesses from
4822 * different threads in case the userspace irqchip is used. */
4823 if (!kvm_irqchip_in_kernel()) {
4824 qemu_mutex_lock_iothread();
4825 }
02e51483
CF		 4826 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4827 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 4828 if (!kvm_irqchip_in_kernel()) {
4829 qemu_mutex_unlock_iothread();
4830 }
f794aa4a 4831 return cpu_get_mem_attrs(env);
05330448
AL		 4832}
4833
20d695a9 4834int kvm_arch_process_async_events(CPUState *cs)
0af691d7 4835{
20d695a9
AF		 4836 X86CPU *cpu = X86_CPU(cs);
4837 CPUX86State *env = &cpu->env;
232fc23b 4838
259186a7 4839 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 4840 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4841 assert(env->mcg_cap);
4842
259186a7 4843 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 4844
dd1750d7 4845 kvm_cpu_synchronize_state(cs);
ab443475 4846
fd13f23b 4847 if (env->exception_nr == EXCP08_DBLE) {
ab443475 4848 /* this means triple fault */
cf83f140 4849 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 4850 cs->exit_request = 1;
ab443475
JK		 4851 return 0;
4852 }
fd13f23b 4853 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 4854 env->has_error_code = 0;
4855
259186a7 4856 cs->halted = 0;
ab443475
JK		 4857 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4858 env->mp_state = KVM_MP_STATE_RUNNABLE;
4859 }
4860 }
4861
fc12d72e
PB		 4862 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4863 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 4864 kvm_cpu_synchronize_state(cs);
4865 do_cpu_init(cpu);
4866 }
4867
db1669bc
JK		 4868 if (kvm_irqchip_in_kernel()) {
4869 return 0;
4870 }
4871
259186a7
AF		 4872 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4873 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 4874 apic_poll_irq(cpu->apic_state);
5d62c43a 4875 }
259186a7 4876 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 4877 (env->eflags & IF_MASK)) ||
259186a7
AF		 4878 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4879 cs->halted = 0;
6792a57b 4880 }
259186a7 4881 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 4882 kvm_cpu_synchronize_state(cs);
232fc23b 4883 do_cpu_sipi(cpu);
0af691d7 4884 }
259186a7
AF		 4885 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4886 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 4887 kvm_cpu_synchronize_state(cs);
02e51483 4888 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 4889 env->tpr_access_type);
4890 }
0af691d7 4891
259186a7 4892 return cs->halted;
0af691d7
MT		 4893}
4894
839b5630 4895static int kvm_handle_halt(X86CPU *cpu)
05330448 4896{
259186a7 4897 CPUState *cs = CPU(cpu);
839b5630
AF		 4898 CPUX86State *env = &cpu->env;
4899
259186a7 4900 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 4901 (env->eflags & IF_MASK)) &&
259186a7
AF		 4902 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4903 cs->halted = 1;
bb4ea393 4904 return EXCP_HLT;
05330448
AL		 4905 }
4906
bb4ea393 4907 return 0;
05330448
AL		 4908}
4909
f7575c96 4910static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 4911{
f7575c96
AF		 4912 CPUState *cs = CPU(cpu);
4913 struct kvm_run *run = cs->kvm_run;
d362e757 4914
02e51483 4915 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 4916 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4917 : TPR_ACCESS_READ);
4918 return 1;
4919}
4920
f17ec444 4921int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 4922{
38972938 4923 static const uint8_t int3 = 0xcc;
64bf3f4e 4924
f17ec444
AF		 4925 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4926 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 4927 return -EINVAL;
b9bec74b 4928 }
e22a25c9
AL		 4929 return 0;
4930}
4931
f17ec444 4932int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 4933{
4934 uint8_t int3;
4935
c6986f16
PB		 4936 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
4937 return -EINVAL;
4938 }
4939 if (int3 != 0xcc) {
4940 return 0;
4941 }
4942 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 4943 return -EINVAL;
b9bec74b 4944 }
e22a25c9
AL		 4945 return 0;
4946}
4947
4948static struct {
4949 target_ulong addr;
4950 int len;
4951 int type;
4952} hw_breakpoint[4];
4953
4954static int nb_hw_breakpoint;
4955
4956static int find_hw_breakpoint(target_ulong addr, int len, int type)
4957{
4958 int n;
4959
b9bec74b 4960 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 4961 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 4962 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 4963 return n;
b9bec74b
JK		 4964 }
4965 }
e22a25c9
AL		 4966 return -1;
4967}
4968
4969int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4970 target_ulong len, int type)
4971{
4972 switch (type) {
4973 case GDB_BREAKPOINT_HW:
4974 len = 1;
4975 break;
4976 case GDB_WATCHPOINT_WRITE:
4977 case GDB_WATCHPOINT_ACCESS:
4978 switch (len) {
4979 case 1:
4980 break;
4981 case 2:
4982 case 4:
4983 case 8:
b9bec74b 4984 if (addr & (len - 1)) {
e22a25c9 4985 return -EINVAL;
b9bec74b 4986 }
e22a25c9
AL		 4987 break;
4988 default:
4989 return -EINVAL;
4990 }
4991 break;
4992 default:
4993 return -ENOSYS;
4994 }
4995
b9bec74b 4996 if (nb_hw_breakpoint == 4) {
e22a25c9 4997 return -ENOBUFS;
b9bec74b
JK		 4998 }
4999 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 5000 return -EEXIST;
b9bec74b 5001 }
e22a25c9
AL		 5002 hw_breakpoint[nb_hw_breakpoint].addr = addr;
5003 hw_breakpoint[nb_hw_breakpoint].len = len;
5004 hw_breakpoint[nb_hw_breakpoint].type = type;
5005 nb_hw_breakpoint++;
5006
5007 return 0;
5008}
5009
5010int kvm_arch_remove_hw_breakpoint(target_ulong addr,
5011 target_ulong len, int type)
5012{
5013 int n;
5014
5015 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 5016 if (n < 0) {
e22a25c9 5017 return -ENOENT;
b9bec74b 5018 }
e22a25c9
AL		 5019 nb_hw_breakpoint--;
5020 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
5021
5022 return 0;
5023}
5024
5025void kvm_arch_remove_all_hw_breakpoints(void)
5026{
5027 nb_hw_breakpoint = 0;
5028}
5029
5030static CPUWatchpoint hw_watchpoint;
5031
a60f24b5 5032static int kvm_handle_debug(X86CPU *cpu,
48405526 5033 struct kvm_debug_exit_arch *arch_info)
e22a25c9 5034{
ed2803da 5035 CPUState *cs = CPU(cpu);
a60f24b5 5036 CPUX86State *env = &cpu->env;
f2574737 5037 int ret = 0;
e22a25c9
AL		 5038 int n;
5039
37936ac7
LA		 5040 if (arch_info->exception == EXCP01_DB) {
5041 if (arch_info->dr6 & DR6_BS) {
ed2803da 5042 if (cs->singlestep_enabled) {
f2574737 5043 ret = EXCP_DEBUG;
b9bec74b 5044 }
e22a25c9 5045 } else {
b9bec74b
JK		 5046 for (n = 0; n < 4; n++) {
5047 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 5048 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
5049 case 0x0:
f2574737 5050 ret = EXCP_DEBUG;
e22a25c9
AL		 5051 break;
5052 case 0x1:
f2574737 5053 ret = EXCP_DEBUG;
ff4700b0 5054 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 5055 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5056 hw_watchpoint.flags = BP_MEM_WRITE;
5057 break;
5058 case 0x3:
f2574737 5059 ret = EXCP_DEBUG;
ff4700b0 5060 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 5061 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
5062 hw_watchpoint.flags = BP_MEM_ACCESS;
5063 break;
5064 }
b9bec74b
JK		 5065 }
5066 }
e22a25c9 5067 }
ff4700b0 5068 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 5069 ret = EXCP_DEBUG;
b9bec74b 5070 }
f2574737 5071 if (ret == 0) {
ff4700b0 5072 cpu_synchronize_state(cs);
fd13f23b 5073 assert(env->exception_nr == -1);
b0b1d690 5074
f2574737 5075 /* pass to guest */
fd13f23b
LA		 5076 kvm_queue_exception(env, arch_info->exception,
5077 arch_info->exception == EXCP01_DB,
5078 arch_info->dr6);
48405526 5079 env->has_error_code = 0;
b0b1d690 5080 }
e22a25c9 5081
f2574737 5082 return ret;
e22a25c9
AL		 5083}
5084
20d695a9 5085void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 5086{
5087 const uint8_t type_code[] = {
5088 [GDB_BREAKPOINT_HW] = 0x0,
5089 [GDB_WATCHPOINT_WRITE] = 0x1,
5090 [GDB_WATCHPOINT_ACCESS] = 0x3
5091 };
5092 const uint8_t len_code[] = {
5093 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
5094 };
5095 int n;
5096
a60f24b5 5097 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 5098 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 5099 }
e22a25c9
AL		 5100 if (nb_hw_breakpoint > 0) {
5101 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
5102 dbg->arch.debugreg[7] = 0x0600;
5103 for (n = 0; n < nb_hw_breakpoint; n++) {
5104 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
5105 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
5106 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 5107 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 5108 }
5109 }
5110}
4513d923 5111
c22f5467
SC		 5112static bool has_sgx_provisioning;
5113
5114static bool __kvm_enable_sgx_provisioning(KVMState *s)
5115{
5116 int fd, ret;
5117
5118 if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) {
5119 return false;
5120 }
5121
5122 fd = qemu_open_old("/dev/sgx_provision", O_RDONLY);
5123 if (fd < 0) {
5124 return false;
5125 }
5126
5127 ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd);
5128 if (ret) {
5129 error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret));
5130 exit(1);
5131 }
5132 close(fd);
5133 return true;
5134}
5135
5136bool kvm_enable_sgx_provisioning(KVMState *s)
5137{
5138 return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning);
5139}
5140
2a4dac83
JK		 5141static bool host_supports_vmx(void)
5142{
5143 uint32_t ecx, unused;
5144
5145 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
5146 return ecx & CPUID_EXT_VMX;
5147}
5148
5149#define VMX_INVALID_GUEST_STATE 0x80000021
5150
20d695a9 5151int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 5152{
20d695a9 5153 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 5154 uint64_t code;
5155 int ret;
e2e69f6b
CQ		 5156 bool ctx_invalid;
5157 char str[256];
5158 KVMState *state;
2a4dac83
JK		 5159
5160 switch (run->exit_reason) {
5161 case KVM_EXIT_HLT:
5162 DPRINTF("handle_hlt\n");
4b8523ee 5163 qemu_mutex_lock_iothread();
839b5630 5164 ret = kvm_handle_halt(cpu);
4b8523ee 5165 qemu_mutex_unlock_iothread();
2a4dac83
JK		 5166 break;
5167 case KVM_EXIT_SET_TPR:
5168 ret = 0;
5169 break;
d362e757 5170 case KVM_EXIT_TPR_ACCESS:
4b8523ee 5171 qemu_mutex_lock_iothread();
f7575c96 5172 ret = kvm_handle_tpr_access(cpu);
4b8523ee 5173 qemu_mutex_unlock_iothread();
d362e757 5174 break;
2a4dac83
JK		 5175 case KVM_EXIT_FAIL_ENTRY:
5176 code = run->fail_entry.hardware_entry_failure_reason;
5177 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
5178 code);
5179 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
5180 fprintf(stderr,
12619721 5181 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 5182 "unrestricted mode\n"
5183 "support, the failure can be most likely due to the guest "
5184 "entering an invalid\n"
5185 "state for Intel VT. For example, the guest maybe running "
5186 "in big real mode\n"
5187 "which is not supported on less recent Intel processors."
5188 "\n\n");
5189 }
5190 ret = -1;
5191 break;
5192 case KVM_EXIT_EXCEPTION:
5193 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
5194 run->ex.exception, run->ex.error_code);
5195 ret = -1;
5196 break;
f2574737
JK		 5197 case KVM_EXIT_DEBUG:
5198 DPRINTF("kvm_exit_debug\n");
4b8523ee 5199 qemu_mutex_lock_iothread();
a60f24b5 5200 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 5201 qemu_mutex_unlock_iothread();
f2574737 5202 break;
50efe82c
AS		 5203 case KVM_EXIT_HYPERV:
5204 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
5205 break;
15eafc2e
PB		 5206 case KVM_EXIT_IOAPIC_EOI:
5207 ioapic_eoi_broadcast(run->eoi.vector);
5208 ret = 0;
5209 break;
035d1ef2
CQ		 5210 case KVM_EXIT_X86_BUS_LOCK:
5211 /* already handled in kvm_arch_post_run */
5212 ret = 0;
5213 break;
e2e69f6b
CQ		 5214 case KVM_EXIT_NOTIFY:
5215 ctx_invalid = !!(run->notify.flags & KVM_NOTIFY_CONTEXT_INVALID);
5216 state = KVM_STATE(current_accel());
5217 sprintf(str, "Encounter a notify exit with %svalid context in"
5218 " guest. There can be possible misbehaves in guest."
5219 " Please have a look.", ctx_invalid ? "in" : "");
5220 if (ctx_invalid ||
5221 state->notify_vmexit == NOTIFY_VMEXIT_OPTION_INTERNAL_ERROR) {
5222 warn_report("KVM internal error: %s", str);
5223 ret = -1;
5224 } else {
5225 warn_report_once("KVM: %s", str);
5226 ret = 0;
5227 }
5228 break;
2a4dac83
JK		 5229 default:
5230 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
5231 ret = -1;
5232 break;
5233 }
5234
5235 return ret;
5236}
5237
20d695a9 5238bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 5239{
20d695a9
AF		 5240 X86CPU *cpu = X86_CPU(cs);
5241 CPUX86State *env = &cpu->env;
5242
dd1750d7 5243 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 5244 return !(env->cr[0] & CR0_PE_MASK) ||
5245 ((env->segs[R_CS].selector & 3) != 3);
4513d923 5246}
84b058d7
JK		 5247
5248void kvm_arch_init_irq_routing(KVMState *s)
5249{
cc7e0ddf 5250 /* We know at this point that we're using the in-kernel
614e41bc 5251 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 5252 * we can use msi via irqfd and GSI routing.
cc7e0ddf 5253 */
614e41bc 5254 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 5255 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 5256
5257 if (kvm_irqchip_is_split()) {
def4c557 5258 KVMRouteChange c = kvm_irqchip_begin_route_changes(s);
15eafc2e
PB		 5259 int i;
5260
5261 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
5262 MSI routes for signaling interrupts to the local apics. */
5263 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
def4c557 5264 if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) {
15eafc2e
PB		 5265 error_report("Could not enable split IRQ mode.");
5266 exit(1);
5267 }
5268 }
def4c557 5269 kvm_irqchip_commit_route_changes(&c);
15eafc2e
PB		 5270 }
5271}
5272
4376c40d 5273int kvm_arch_irqchip_create(KVMState *s)
15eafc2e
PB		 5274{
5275 int ret;
4376c40d 5276 if (kvm_kernel_irqchip_split()) {
15eafc2e
PB		 5277 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
5278 if (ret) {
df3c286c 5279 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 5280 strerror(-ret));
5281 exit(1);
5282 } else {
5283 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
5284 kvm_split_irqchip = true;
5285 return 1;
5286 }
5287 } else {
5288 return 0;
5289 }
84b058d7 5290}
b139bd30 5291
c1bb5418
DW		 5292uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
5293{
5294 CPUX86State *env;
5295 uint64_t ext_id;
5296
5297 if (!first_cpu) {
5298 return address;
5299 }
5300 env = &X86_CPU(first_cpu)->env;
5301 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
5302 return address;
5303 }
5304
5305 /*
5306 * If the remappable format bit is set, or the upper bits are
5307 * already set in address_hi, or the low extended bits aren't
5308 * there anyway, do nothing.
5309 */
5310 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
5311 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
5312 return address;
5313 }
5314
5315 address &= ~ext_id;
5316 address |= ext_id << 35;
5317 return address;
5318}
5319
9e03a040 5320int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 5321 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 5322{
8b5ed7df
PX		 5323 X86IOMMUState *iommu = x86_iommu_get_default();
5324
5325 if (iommu) {
30c60f77 5326 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
8b5ed7df 5327
c1bb5418
DW		 5328 if (class->int_remap) {
5329 int ret;
5330 MSIMessage src, dst;
0ea1472d 5331
c1bb5418
DW		 5332 src.address = route->u.msi.address_hi;
5333 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
5334 src.address |= route->u.msi.address_lo;
5335 src.data = route->u.msi.data;
8b5ed7df 5336
c1bb5418
DW		 5337 ret = class->int_remap(iommu, &src, &dst, dev ? \
5338 pci_requester_id(dev) : \
5339 X86_IOMMU_SID_INVALID);
5340 if (ret) {
5341 trace_kvm_x86_fixup_msi_error(route->gsi);
5342 return 1;
5343 }
5344
5345 /*
5346 * Handled untranslated compatibilty format interrupt with
5347 * extended destination ID in the low bits 11-5. */
5348 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
8b5ed7df 5349
c1bb5418
DW		 5350 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
5351 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
5352 route->u.msi.data = dst.data;
5353 return 0;
5354 }
8b5ed7df
PX		 5355 }
5356
c1bb5418
DW		 5357 address = kvm_swizzle_msi_ext_dest_id(address);
5358 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
5359 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
9e03a040
FB		 5360 return 0;
5361}
1850b6b7 5362
38d87493
PX		 5363typedef struct MSIRouteEntry MSIRouteEntry;
5364
5365struct MSIRouteEntry {
5366 PCIDevice *dev; /* Device pointer */
5367 int vector; /* MSI/MSIX vector index */
5368 int virq; /* Virtual IRQ index */
5369 QLIST_ENTRY(MSIRouteEntry) list;
5370};
5371
5372/* List of used GSI routes */
5373static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
5374 QLIST_HEAD_INITIALIZER(msi_route_list);
5375
e1d4fb2d
PX		 5376static void kvm_update_msi_routes_all(void *private, bool global,
5377 uint32_t index, uint32_t mask)
5378{
a56de056 5379 int cnt = 0, vector;
e1d4fb2d
PX		 5380 MSIRouteEntry *entry;
5381 MSIMessage msg;
fd563564
PX		 5382 PCIDevice *dev;
5383
e1d4fb2d
PX		 5384 /* TODO: explicit route update */
5385 QLIST_FOREACH(entry, &msi_route_list, list) {
5386 cnt++;
a56de056 5387 vector = entry->vector;
fd563564 5388 dev = entry->dev;
a56de056
PX		 5389 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
5390 msg = msix_get_message(dev, vector);
5391 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
5392 msg = msi_get_message(dev, vector);
5393 } else {
5394 /*
5395 * Either MSI/MSIX is disabled for the device, or the
5396 * specific message was masked out. Skip this one.
5397 */
fd563564
PX		 5398 continue;
5399 }
fd563564 5400 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 5401 }
3f1fea0f 5402 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 5403 trace_kvm_x86_update_msi_routes(cnt);
5404}
5405
38d87493
PX		 5406int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
5407 int vector, PCIDevice *dev)
5408{
e1d4fb2d 5409 static bool notify_list_inited = false;
38d87493
PX		 5410 MSIRouteEntry *entry;
5411
5412 if (!dev) {
5413 /* These are (possibly) IOAPIC routes only used for split
5414 * kernel irqchip mode, while what we are housekeeping are
5415 * PCI devices only. */
5416 return 0;
5417 }
5418
5419 entry = g_new0(MSIRouteEntry, 1);
5420 entry->dev = dev;
5421 entry->vector = vector;
5422 entry->virq = route->gsi;
5423 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
5424
5425 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 5426
5427 if (!notify_list_inited) {
5428 /* For the first time we do add route, add ourselves into
5429 * IOMMU's IEC notify list if needed. */
5430 X86IOMMUState *iommu = x86_iommu_get_default();
5431 if (iommu) {
5432 x86_iommu_iec_register_notifier(iommu,
5433 kvm_update_msi_routes_all,
5434 NULL);
5435 }
5436 notify_list_inited = true;
5437 }
38d87493
PX		 5438 return 0;
5439}
5440
5441int kvm_arch_release_virq_post(int virq)
5442{
5443 MSIRouteEntry *entry, *next;
5444 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
5445 if (entry->virq == virq) {
5446 trace_kvm_x86_remove_msi_route(virq);
5447 QLIST_REMOVE(entry, list);
01960e6d 5448 g_free(entry);
38d87493
PX		 5449 break;
5450 }
5451 }
9e03a040
FB		 5452 return 0;
5453}
1850b6b7
EA		 5454
5455int kvm_arch_msi_data_to_gsi(uint32_t data)
5456{
5457 abort();
5458}
e1e43813
PB		 5459
5460bool kvm_has_waitpkg(void)
5461{
5462 return has_msr_umwait;
5463}
92a5199b
TL		 5464
5465bool kvm_arch_cpu_check_are_resettable(void)
5466{
5467 return !sev_es_enabled();
5468}
19db68ca
YZ		 5469
5470#define ARCH_REQ_XCOMP_GUEST_PERM 0x1025
5471
5472void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask)
5473{
5474 KVMState *s = kvm_state;
5475 uint64_t supported;
5476
5477 mask &= XSTATE_DYNAMIC_MASK;
5478 if (!mask) {
5479 return;
5480 }
5481 /*
5482 * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0].
5483 * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned
5484 * about them already because they are not supported features.
5485 */
5486 supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
5487 supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32;
5488 mask &= supported;
5489
5490 while (mask) {
5491 int bit = ctz64(mask);
5492 int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit);
5493 if (rc) {
5494 /*
5495 * Older kernel version (<5.17) do not support
5496 * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return
5497 * any dynamic feature from kvm_arch_get_supported_cpuid.
5498 */
5499 warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure "
5500 "for feature bit %d", bit);
5501 }
5502 mask &= ~BIT_ULL(bit);
5503 }
5504}
3dba0a33 5505
e2e69f6b
CQ		 5506static int kvm_arch_get_notify_vmexit(Object *obj, Error **errp)
5507{
5508 KVMState *s = KVM_STATE(obj);
5509 return s->notify_vmexit;
5510}
5511
5512static void kvm_arch_set_notify_vmexit(Object *obj, int value, Error **errp)
5513{
5514 KVMState *s = KVM_STATE(obj);
5515
5516 if (s->fd != -1) {
5517 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
5518 return;
5519 }
5520
5521 s->notify_vmexit = value;
5522}
5523
5524static void kvm_arch_get_notify_window(Object *obj, Visitor *v,
5525 const char *name, void *opaque,
5526 Error **errp)
5527{
5528 KVMState *s = KVM_STATE(obj);
5529 uint32_t value = s->notify_window;
5530
5531 visit_type_uint32(v, name, &value, errp);
5532}
5533
5534static void kvm_arch_set_notify_window(Object *obj, Visitor *v,
5535 const char *name, void *opaque,
5536 Error **errp)
5537{
5538 KVMState *s = KVM_STATE(obj);
5539 Error *error = NULL;
5540 uint32_t value;
5541
5542 if (s->fd != -1) {
5543 error_setg(errp, "Cannot set properties after the accelerator has been initialized");
5544 return;
5545 }
5546
5547 visit_type_uint32(v, name, &value, &error);
5548 if (error) {
5549 error_propagate(errp, error);
5550 return;
5551 }
5552
5553 s->notify_window = value;
5554}
5555
3dba0a33
PB		 5556void kvm_arch_accel_class_init(ObjectClass *oc)
5557{
e2e69f6b
CQ		 5558 object_class_property_add_enum(oc, "notify-vmexit", "NotifyVMexitOption",
5559 &NotifyVmexitOption_lookup,
5560 kvm_arch_get_notify_vmexit,
5561 kvm_arch_set_notify_vmexit);
5562 object_class_property_set_description(oc, "notify-vmexit",
5563 "Enable notify VM exit");
5564
5565 object_class_property_add(oc, "notify-window", "uint32",
5566 kvm_arch_get_notify_window,
5567 kvm_arch_set_notify_window,
5568 NULL, NULL);
5569 object_class_property_set_description(oc, "notify-window",
5570 "Clock cycles without an event window "
5571 "after which a notification VM exit occurs");
3dba0a33 5572}
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