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05330448 AL |
1 | /* |
2 | * QEMU KVM support | |
3 | * | |
4 | * Copyright (C) 2006-2008 Qumranet Technologies | |
5 | * Copyright IBM, Corp. 2008 | |
6 | * | |
7 | * Authors: | |
8 | * Anthony Liguori <aliguori@us.ibm.com> | |
9 | * | |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
11 | * See the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
b6a0aa05 | 15 | #include "qemu/osdep.h" |
8efc4e51 | 16 | #include "qapi/qapi-events-run-state.h" |
da34e65c | 17 | #include "qapi/error.h" |
05330448 | 18 | #include <sys/ioctl.h> |
25d2e361 | 19 | #include <sys/utsname.h> |
19db68ca | 20 | #include <sys/syscall.h> |
05330448 AL |
21 | |
22 | #include <linux/kvm.h> | |
1814eab6 | 23 | #include "standard-headers/asm-x86/kvm_para.h" |
05330448 | 24 | |
33c11879 | 25 | #include "cpu.h" |
f5cc5a5c | 26 | #include "host-cpu.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
b3946626 | 28 | #include "sysemu/hw_accel.h" |
6410848b | 29 | #include "sysemu/kvm_int.h" |
54d31236 | 30 | #include "sysemu/runstate.h" |
1d31f66b | 31 | #include "kvm_i386.h" |
93777de3 | 32 | #include "sev.h" |
50efe82c | 33 | #include "hyperv.h" |
5e953812 | 34 | #include "hyperv-proto.h" |
50efe82c | 35 | |
022c62cb | 36 | #include "exec/gdbstub.h" |
1de7afc9 | 37 | #include "qemu/host-utils.h" |
db725815 | 38 | #include "qemu/main-loop.h" |
1de7afc9 | 39 | #include "qemu/config-file.h" |
1c4a55db | 40 | #include "qemu/error-report.h" |
5df022cf | 41 | #include "qemu/memalign.h" |
89a289c7 | 42 | #include "hw/i386/x86.h" |
0d09e41a | 43 | #include "hw/i386/apic.h" |
e0723c45 PB |
44 | #include "hw/i386/apic_internal.h" |
45 | #include "hw/i386/apic-msidef.h" | |
8b5ed7df | 46 | #include "hw/i386/intel_iommu.h" |
e1d4fb2d | 47 | #include "hw/i386/x86-iommu.h" |
d6d059ca | 48 | #include "hw/i386/e820_memory_layout.h" |
50efe82c | 49 | |
a2cb15b0 | 50 | #include "hw/pci/pci.h" |
15eafc2e | 51 | #include "hw/pci/msi.h" |
fd563564 | 52 | #include "hw/pci/msix.h" |
795c40b8 | 53 | #include "migration/blocker.h" |
4c663752 | 54 | #include "exec/memattrs.h" |
8b5ed7df | 55 | #include "trace.h" |
05330448 AL |
56 | |
57 | //#define DEBUG_KVM | |
58 | ||
59 | #ifdef DEBUG_KVM | |
8c0d577e | 60 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
61 | do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0) |
62 | #else | |
8c0d577e | 63 | #define DPRINTF(fmt, ...) \ |
05330448 AL |
64 | do { } while (0) |
65 | #endif | |
66 | ||
73b994f6 LA |
67 | /* From arch/x86/kvm/lapic.h */ |
68 | #define KVM_APIC_BUS_CYCLE_NS 1 | |
69 | #define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS) | |
70 | ||
1a03675d GC |
71 | #define MSR_KVM_WALL_CLOCK 0x11 |
72 | #define MSR_KVM_SYSTEM_TIME 0x12 | |
73 | ||
d1138251 EH |
74 | /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus |
75 | * 255 kvm_msr_entry structs */ | |
76 | #define MSR_BUF_SIZE 4096 | |
d71b62a1 | 77 | |
420ae1fc PB |
78 | static void kvm_init_msrs(X86CPU *cpu); |
79 | ||
94a8d39a JK |
80 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
81 | KVM_CAP_INFO(SET_TSS_ADDR), | |
82 | KVM_CAP_INFO(EXT_CPUID), | |
83 | KVM_CAP_INFO(MP_STATE), | |
84 | KVM_CAP_LAST_INFO | |
85 | }; | |
25d2e361 | 86 | |
c3a3a7d3 JK |
87 | static bool has_msr_star; |
88 | static bool has_msr_hsave_pa; | |
c9b8f6b6 | 89 | static bool has_msr_tsc_aux; |
f28558d3 | 90 | static bool has_msr_tsc_adjust; |
aa82ba54 | 91 | static bool has_msr_tsc_deadline; |
df67696e | 92 | static bool has_msr_feature_control; |
21e87c46 | 93 | static bool has_msr_misc_enable; |
fc12d72e | 94 | static bool has_msr_smbase; |
79e9ebeb | 95 | static bool has_msr_bndcfgs; |
25d2e361 | 96 | static int lm_capable_kernel; |
7bc3d711 | 97 | static bool has_msr_hv_hypercall; |
f2a53c9e | 98 | static bool has_msr_hv_crash; |
744b8a94 | 99 | static bool has_msr_hv_reset; |
8c145d7c | 100 | static bool has_msr_hv_vpindex; |
e9688fab | 101 | static bool hv_vpindex_settable; |
46eb8f98 | 102 | static bool has_msr_hv_runtime; |
866eea9a | 103 | static bool has_msr_hv_synic; |
ff99aa64 | 104 | static bool has_msr_hv_stimer; |
d72bc7f6 | 105 | static bool has_msr_hv_frequencies; |
ba6a4fd9 | 106 | static bool has_msr_hv_reenlightenment; |
18cd2c17 | 107 | static bool has_msr_xss; |
65087997 | 108 | static bool has_msr_umwait; |
a33a2cfe | 109 | static bool has_msr_spec_ctrl; |
cabf9862 | 110 | static bool has_tsc_scale_msr; |
2a9758c5 | 111 | static bool has_msr_tsx_ctrl; |
cfeea0c0 | 112 | static bool has_msr_virt_ssbd; |
e13713db | 113 | static bool has_msr_smi_count; |
aec5e9c3 | 114 | static bool has_msr_arch_capabs; |
597360c0 | 115 | static bool has_msr_core_capabs; |
20a78b02 | 116 | static bool has_msr_vmx_vmfunc; |
67025148 | 117 | static bool has_msr_ucode_rev; |
4a910e1f | 118 | static bool has_msr_vmx_procbased_ctls2; |
ea39f9b6 | 119 | static bool has_msr_perf_capabs; |
6aa4228b | 120 | static bool has_msr_pkrs; |
b827df58 | 121 | |
0b368a10 JD |
122 | static uint32_t has_architectural_pmu_version; |
123 | static uint32_t num_architectural_pmu_gp_counters; | |
124 | static uint32_t num_architectural_pmu_fixed_counters; | |
0d894367 | 125 | |
28143b40 | 126 | static int has_xsave; |
e56dd3c7 | 127 | static int has_xsave2; |
28143b40 TH |
128 | static int has_xcrs; |
129 | static int has_pit_state2; | |
8f515d38 | 130 | static int has_sregs2; |
fd13f23b | 131 | static int has_exception_payload; |
28143b40 | 132 | |
87f8b626 AR |
133 | static bool has_msr_mcg_ext_ctl; |
134 | ||
494e95e9 | 135 | static struct kvm_cpuid2 *cpuid_cache; |
a8439be6 | 136 | static struct kvm_cpuid2 *hv_cpuid_cache; |
f57bceb6 | 137 | static struct kvm_msr_list *kvm_feature_msrs; |
494e95e9 | 138 | |
035d1ef2 CQ |
139 | #define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */ |
140 | static RateLimit bus_lock_ratelimit_ctrl; | |
141 | ||
28143b40 TH |
142 | int kvm_has_pit_state2(void) |
143 | { | |
144 | return has_pit_state2; | |
145 | } | |
146 | ||
355023f2 PB |
147 | bool kvm_has_smm(void) |
148 | { | |
23edf8b5 | 149 | return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM); |
355023f2 PB |
150 | } |
151 | ||
6053a86f MT |
152 | bool kvm_has_adjust_clock_stable(void) |
153 | { | |
154 | int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK); | |
155 | ||
156 | return (ret == KVM_CLOCK_TSC_STABLE); | |
157 | } | |
158 | ||
8700a984 VK |
159 | bool kvm_has_adjust_clock(void) |
160 | { | |
161 | return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK); | |
162 | } | |
163 | ||
79a197ab LA |
164 | bool kvm_has_exception_payload(void) |
165 | { | |
166 | return has_exception_payload; | |
167 | } | |
168 | ||
fb506e70 RK |
169 | static bool kvm_x2apic_api_set_flags(uint64_t flags) |
170 | { | |
4f7f5893 | 171 | KVMState *s = KVM_STATE(current_accel()); |
fb506e70 RK |
172 | |
173 | return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags); | |
174 | } | |
175 | ||
e391c009 | 176 | #define MEMORIZE(fn, _result) \ |
2a138ec3 | 177 | ({ \ |
2a138ec3 RK |
178 | static bool _memorized; \ |
179 | \ | |
180 | if (_memorized) { \ | |
181 | return _result; \ | |
182 | } \ | |
183 | _memorized = true; \ | |
184 | _result = fn; \ | |
185 | }) | |
186 | ||
e391c009 IM |
187 | static bool has_x2apic_api; |
188 | ||
189 | bool kvm_has_x2apic_api(void) | |
190 | { | |
191 | return has_x2apic_api; | |
192 | } | |
193 | ||
fb506e70 RK |
194 | bool kvm_enable_x2apic(void) |
195 | { | |
2a138ec3 RK |
196 | return MEMORIZE( |
197 | kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS | | |
e391c009 IM |
198 | KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK), |
199 | has_x2apic_api); | |
fb506e70 RK |
200 | } |
201 | ||
e9688fab RK |
202 | bool kvm_hv_vpindex_settable(void) |
203 | { | |
204 | return hv_vpindex_settable; | |
205 | } | |
206 | ||
0fd7e098 LL |
207 | static int kvm_get_tsc(CPUState *cs) |
208 | { | |
209 | X86CPU *cpu = X86_CPU(cs); | |
210 | CPUX86State *env = &cpu->env; | |
211 | struct { | |
212 | struct kvm_msrs info; | |
213 | struct kvm_msr_entry entries[1]; | |
a1834d97 | 214 | } msr_data = {}; |
0fd7e098 LL |
215 | int ret; |
216 | ||
217 | if (env->tsc_valid) { | |
218 | return 0; | |
219 | } | |
220 | ||
1f670a95 | 221 | memset(&msr_data, 0, sizeof(msr_data)); |
0fd7e098 LL |
222 | msr_data.info.nmsrs = 1; |
223 | msr_data.entries[0].index = MSR_IA32_TSC; | |
224 | env->tsc_valid = !runstate_is_running(); | |
225 | ||
226 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data); | |
227 | if (ret < 0) { | |
228 | return ret; | |
229 | } | |
230 | ||
48e1a45c | 231 | assert(ret == 1); |
0fd7e098 LL |
232 | env->tsc = msr_data.entries[0].data; |
233 | return 0; | |
234 | } | |
235 | ||
14e6fe12 | 236 | static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg) |
0fd7e098 | 237 | { |
0fd7e098 LL |
238 | kvm_get_tsc(cpu); |
239 | } | |
240 | ||
241 | void kvm_synchronize_all_tsc(void) | |
242 | { | |
243 | CPUState *cpu; | |
244 | ||
245 | if (kvm_enabled()) { | |
246 | CPU_FOREACH(cpu) { | |
14e6fe12 | 247 | run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL); |
0fd7e098 LL |
248 | } |
249 | } | |
250 | } | |
251 | ||
b827df58 AK |
252 | static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) |
253 | { | |
254 | struct kvm_cpuid2 *cpuid; | |
255 | int r, size; | |
256 | ||
257 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
e42a92ae | 258 | cpuid = g_malloc0(size); |
b827df58 AK |
259 | cpuid->nent = max; |
260 | r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid); | |
76ae317f MM |
261 | if (r == 0 && cpuid->nent >= max) { |
262 | r = -E2BIG; | |
263 | } | |
b827df58 AK |
264 | if (r < 0) { |
265 | if (r == -E2BIG) { | |
7267c094 | 266 | g_free(cpuid); |
b827df58 AK |
267 | return NULL; |
268 | } else { | |
269 | fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n", | |
270 | strerror(-r)); | |
271 | exit(1); | |
272 | } | |
273 | } | |
274 | return cpuid; | |
275 | } | |
276 | ||
dd87f8a6 EH |
277 | /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough |
278 | * for all entries. | |
279 | */ | |
280 | static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) | |
281 | { | |
282 | struct kvm_cpuid2 *cpuid; | |
283 | int max = 1; | |
494e95e9 CP |
284 | |
285 | if (cpuid_cache != NULL) { | |
286 | return cpuid_cache; | |
287 | } | |
dd87f8a6 EH |
288 | while ((cpuid = try_get_cpuid(s, max)) == NULL) { |
289 | max *= 2; | |
290 | } | |
494e95e9 | 291 | cpuid_cache = cpuid; |
dd87f8a6 EH |
292 | return cpuid; |
293 | } | |
294 | ||
b199c682 | 295 | static bool host_tsx_broken(void) |
40e80ee4 EH |
296 | { |
297 | int family, model, stepping;\ | |
298 | char vendor[CPUID_VENDOR_SZ + 1]; | |
299 | ||
f5cc5a5c | 300 | host_cpu_vendor_fms(vendor, &family, &model, &stepping); |
40e80ee4 EH |
301 | |
302 | /* Check if we are running on a Haswell host known to have broken TSX */ | |
303 | return !strcmp(vendor, CPUID_VENDOR_INTEL) && | |
304 | (family == 6) && | |
305 | ((model == 63 && stepping < 4) || | |
306 | model == 60 || model == 69 || model == 70); | |
307 | } | |
0c31b744 | 308 | |
829ae2f9 EH |
309 | /* Returns the value for a specific register on the cpuid entry |
310 | */ | |
311 | static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) | |
312 | { | |
313 | uint32_t ret = 0; | |
314 | switch (reg) { | |
315 | case R_EAX: | |
316 | ret = entry->eax; | |
317 | break; | |
318 | case R_EBX: | |
319 | ret = entry->ebx; | |
320 | break; | |
321 | case R_ECX: | |
322 | ret = entry->ecx; | |
323 | break; | |
324 | case R_EDX: | |
325 | ret = entry->edx; | |
326 | break; | |
327 | } | |
328 | return ret; | |
329 | } | |
330 | ||
4fb73f1d EH |
331 | /* Find matching entry for function/index on kvm_cpuid2 struct |
332 | */ | |
333 | static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, | |
334 | uint32_t function, | |
335 | uint32_t index) | |
336 | { | |
337 | int i; | |
338 | for (i = 0; i < cpuid->nent; ++i) { | |
339 | if (cpuid->entries[i].function == function && | |
340 | cpuid->entries[i].index == index) { | |
341 | return &cpuid->entries[i]; | |
342 | } | |
343 | } | |
344 | /* not found: */ | |
345 | return NULL; | |
346 | } | |
347 | ||
ba9bc59e | 348 | uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, |
c958a8bd | 349 | uint32_t index, int reg) |
b827df58 AK |
350 | { |
351 | struct kvm_cpuid2 *cpuid; | |
b827df58 AK |
352 | uint32_t ret = 0; |
353 | uint32_t cpuid_1_edx; | |
19db68ca | 354 | uint64_t bitmask; |
b827df58 | 355 | |
dd87f8a6 | 356 | cpuid = get_supported_cpuid(s); |
b827df58 | 357 | |
4fb73f1d EH |
358 | struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); |
359 | if (entry) { | |
4fb73f1d | 360 | ret = cpuid_entry_get_reg(entry, reg); |
b827df58 AK |
361 | } |
362 | ||
7b46e5ce EH |
363 | /* Fixups for the data returned by KVM, below */ |
364 | ||
c2acb022 EH |
365 | if (function == 1 && reg == R_EDX) { |
366 | /* KVM before 2.6.30 misreports the following features */ | |
367 | ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; | |
84bd945c EH |
368 | } else if (function == 1 && reg == R_ECX) { |
369 | /* We can set the hypervisor flag, even if KVM does not return it on | |
370 | * GET_SUPPORTED_CPUID | |
371 | */ | |
372 | ret |= CPUID_EXT_HYPERVISOR; | |
ac67ee26 EH |
373 | /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it |
374 | * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, | |
375 | * and the irqchip is in the kernel. | |
376 | */ | |
377 | if (kvm_irqchip_in_kernel() && | |
378 | kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { | |
379 | ret |= CPUID_EXT_TSC_DEADLINE_TIMER; | |
380 | } | |
41e5e76d EH |
381 | |
382 | /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled | |
383 | * without the in-kernel irqchip | |
384 | */ | |
385 | if (!kvm_irqchip_in_kernel()) { | |
386 | ret &= ~CPUID_EXT_X2APIC; | |
b827df58 | 387 | } |
2266d443 MT |
388 | |
389 | if (enable_cpu_pm) { | |
390 | int disable_exits = kvm_check_extension(s, | |
391 | KVM_CAP_X86_DISABLE_EXITS); | |
392 | ||
393 | if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) { | |
394 | ret |= CPUID_EXT_MONITOR; | |
395 | } | |
396 | } | |
28b8e4d0 JK |
397 | } else if (function == 6 && reg == R_EAX) { |
398 | ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */ | |
40e80ee4 | 399 | } else if (function == 7 && index == 0 && reg == R_EBX) { |
b199c682 | 400 | if (host_tsx_broken()) { |
40e80ee4 EH |
401 | ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE); |
402 | } | |
485b1d25 EH |
403 | } else if (function == 7 && index == 0 && reg == R_EDX) { |
404 | /* | |
405 | * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts. | |
406 | * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is | |
407 | * returned by KVM_GET_MSR_INDEX_LIST. | |
408 | */ | |
409 | if (!has_msr_arch_capabs) { | |
410 | ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES; | |
411 | } | |
19db68ca YZ |
412 | } else if (function == 0xd && index == 0 && |
413 | (reg == R_EAX || reg == R_EDX)) { | |
414 | struct kvm_device_attr attr = { | |
415 | .group = 0, | |
416 | .attr = KVM_X86_XCOMP_GUEST_SUPP, | |
417 | .addr = (unsigned long) &bitmask | |
418 | }; | |
419 | ||
420 | bool sys_attr = kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES); | |
421 | if (!sys_attr) { | |
422 | warn_report("cannot get sys attribute capabilities %d", sys_attr); | |
423 | } | |
424 | ||
425 | int rc = kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr); | |
426 | if (rc == -1 && (errno == ENXIO || errno == EINVAL)) { | |
427 | warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) " | |
428 | "error: %d", rc); | |
429 | } | |
430 | ret = (reg == R_EAX) ? bitmask : bitmask >> 32; | |
f98bbd83 BM |
431 | } else if (function == 0x80000001 && reg == R_ECX) { |
432 | /* | |
433 | * It's safe to enable TOPOEXT even if it's not returned by | |
434 | * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows | |
435 | * us to keep CPU models including TOPOEXT runnable on older kernels. | |
436 | */ | |
437 | ret |= CPUID_EXT3_TOPOEXT; | |
c2acb022 EH |
438 | } else if (function == 0x80000001 && reg == R_EDX) { |
439 | /* On Intel, kvm returns cpuid according to the Intel spec, | |
440 | * so add missing bits according to the AMD spec: | |
441 | */ | |
442 | cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); | |
443 | ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; | |
64877477 EH |
444 | } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) { |
445 | /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't | |
446 | * be enabled without the in-kernel irqchip | |
447 | */ | |
448 | if (!kvm_irqchip_in_kernel()) { | |
449 | ret &= ~(1U << KVM_FEATURE_PV_UNHALT); | |
450 | } | |
c1bb5418 DW |
451 | if (kvm_irqchip_is_split()) { |
452 | ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID; | |
453 | } | |
be777326 | 454 | } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) { |
2af1acad | 455 | ret |= 1U << KVM_HINTS_REALTIME; |
b9bec74b | 456 | } |
0c31b744 GC |
457 | |
458 | return ret; | |
bb0300dc | 459 | } |
bb0300dc | 460 | |
ede146c2 | 461 | uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index) |
f57bceb6 RH |
462 | { |
463 | struct { | |
464 | struct kvm_msrs info; | |
465 | struct kvm_msr_entry entries[1]; | |
a1834d97 | 466 | } msr_data = {}; |
20a78b02 PB |
467 | uint64_t value; |
468 | uint32_t ret, can_be_one, must_be_one; | |
f57bceb6 RH |
469 | |
470 | if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */ | |
471 | return 0; | |
472 | } | |
473 | ||
474 | /* Check if requested MSR is supported feature MSR */ | |
475 | int i; | |
476 | for (i = 0; i < kvm_feature_msrs->nmsrs; i++) | |
477 | if (kvm_feature_msrs->indices[i] == index) { | |
478 | break; | |
479 | } | |
480 | if (i == kvm_feature_msrs->nmsrs) { | |
481 | return 0; /* if the feature MSR is not supported, simply return 0 */ | |
482 | } | |
483 | ||
484 | msr_data.info.nmsrs = 1; | |
485 | msr_data.entries[0].index = index; | |
486 | ||
487 | ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data); | |
488 | if (ret != 1) { | |
489 | error_report("KVM get MSR (index=0x%x) feature failed, %s", | |
490 | index, strerror(-ret)); | |
491 | exit(1); | |
492 | } | |
493 | ||
20a78b02 PB |
494 | value = msr_data.entries[0].data; |
495 | switch (index) { | |
496 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
4a910e1f VK |
497 | if (!has_msr_vmx_procbased_ctls2) { |
498 | /* KVM forgot to add these bits for some time, do this ourselves. */ | |
499 | if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) & | |
500 | CPUID_XSAVE_XSAVES) { | |
501 | value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32; | |
502 | } | |
503 | if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) & | |
504 | CPUID_EXT_RDRAND) { | |
505 | value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32; | |
506 | } | |
507 | if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & | |
508 | CPUID_7_0_EBX_INVPCID) { | |
509 | value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32; | |
510 | } | |
511 | if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & | |
512 | CPUID_7_0_EBX_RDSEED) { | |
513 | value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32; | |
514 | } | |
515 | if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) & | |
516 | CPUID_EXT2_RDTSCP) { | |
517 | value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32; | |
518 | } | |
048c9516 PB |
519 | } |
520 | /* fall through */ | |
20a78b02 PB |
521 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: |
522 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
523 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
524 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
525 | /* | |
526 | * Return true for bits that can be one, but do not have to be one. | |
527 | * The SDM tells us which bits could have a "must be one" setting, | |
528 | * so we can do the opposite transformation in make_vmx_msr_value. | |
529 | */ | |
530 | must_be_one = (uint32_t)value; | |
531 | can_be_one = (uint32_t)(value >> 32); | |
532 | return can_be_one & ~must_be_one; | |
533 | ||
534 | default: | |
535 | return value; | |
536 | } | |
f57bceb6 RH |
537 | } |
538 | ||
e7701825 MT |
539 | static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, |
540 | int *max_banks) | |
541 | { | |
542 | int r; | |
543 | ||
14a09518 | 544 | r = kvm_check_extension(s, KVM_CAP_MCE); |
e7701825 MT |
545 | if (r > 0) { |
546 | *max_banks = r; | |
547 | return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap); | |
548 | } | |
549 | return -ENOSYS; | |
550 | } | |
551 | ||
bee615d4 | 552 | static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) |
e7701825 | 553 | { |
87f8b626 | 554 | CPUState *cs = CPU(cpu); |
bee615d4 | 555 | CPUX86State *env = &cpu->env; |
c34d440a JK |
556 | uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | |
557 | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; | |
558 | uint64_t mcg_status = MCG_STATUS_MCIP; | |
87f8b626 | 559 | int flags = 0; |
e7701825 | 560 | |
c34d440a JK |
561 | if (code == BUS_MCEERR_AR) { |
562 | status |= MCI_STATUS_AR | 0x134; | |
563 | mcg_status |= MCG_STATUS_EIPV; | |
564 | } else { | |
565 | status |= 0xc0; | |
566 | mcg_status |= MCG_STATUS_RIPV; | |
419fb20a | 567 | } |
87f8b626 AR |
568 | |
569 | flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0; | |
570 | /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the | |
571 | * guest kernel back into env->mcg_ext_ctl. | |
572 | */ | |
573 | cpu_synchronize_state(cs); | |
574 | if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) { | |
575 | mcg_status |= MCG_STATUS_LMCE; | |
576 | flags = 0; | |
577 | } | |
578 | ||
8c5cf3b6 | 579 | cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, |
87f8b626 | 580 | (MCM_ADDR_PHYS << 6) | 0xc, flags); |
419fb20a | 581 | } |
419fb20a | 582 | |
8efc4e51 ZP |
583 | static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar) |
584 | { | |
585 | MemoryFailureFlags mff = {.action_required = ar, .recursive = false}; | |
586 | ||
587 | qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action, | |
588 | &mff); | |
589 | } | |
590 | ||
73284563 | 591 | static void hardware_memory_error(void *host_addr) |
419fb20a | 592 | { |
8efc4e51 | 593 | emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true); |
73284563 | 594 | error_report("QEMU got Hardware memory error at addr %p", host_addr); |
419fb20a JK |
595 | exit(1); |
596 | } | |
597 | ||
2ae41db2 | 598 | void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) |
419fb20a | 599 | { |
20d695a9 AF |
600 | X86CPU *cpu = X86_CPU(c); |
601 | CPUX86State *env = &cpu->env; | |
419fb20a | 602 | ram_addr_t ram_addr; |
a8170e5e | 603 | hwaddr paddr; |
419fb20a | 604 | |
4d39892c PB |
605 | /* If we get an action required MCE, it has been injected by KVM |
606 | * while the VM was running. An action optional MCE instead should | |
607 | * be coming from the main thread, which qemu_init_sigbus identifies | |
608 | * as the "early kill" thread. | |
609 | */ | |
a16fc07e | 610 | assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); |
20e0ff59 | 611 | |
20e0ff59 | 612 | if ((env->mcg_cap & MCG_SER_P) && addr) { |
07bdaa41 | 613 | ram_addr = qemu_ram_addr_from_host(addr); |
20e0ff59 PB |
614 | if (ram_addr != RAM_ADDR_INVALID && |
615 | kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { | |
616 | kvm_hwpoison_page_add(ram_addr); | |
617 | kvm_mce_inject(cpu, paddr, code); | |
73284563 MS |
618 | |
619 | /* | |
620 | * Use different logging severity based on error type. | |
621 | * If there is additional MCE reporting on the hypervisor, QEMU VA | |
622 | * could be another source to identify the PA and MCE details. | |
623 | */ | |
624 | if (code == BUS_MCEERR_AR) { | |
625 | error_report("Guest MCE Memory Error at QEMU addr %p and " | |
626 | "GUEST addr 0x%" HWADDR_PRIx " of type %s injected", | |
627 | addr, paddr, "BUS_MCEERR_AR"); | |
628 | } else { | |
629 | warn_report("Guest MCE Memory Error at QEMU addr %p and " | |
630 | "GUEST addr 0x%" HWADDR_PRIx " of type %s injected", | |
631 | addr, paddr, "BUS_MCEERR_AO"); | |
632 | } | |
633 | ||
2ae41db2 | 634 | return; |
419fb20a | 635 | } |
20e0ff59 | 636 | |
73284563 MS |
637 | if (code == BUS_MCEERR_AO) { |
638 | warn_report("Hardware memory error at addr %p of type %s " | |
639 | "for memory used by QEMU itself instead of guest system!", | |
640 | addr, "BUS_MCEERR_AO"); | |
641 | } | |
419fb20a | 642 | } |
20e0ff59 PB |
643 | |
644 | if (code == BUS_MCEERR_AR) { | |
73284563 | 645 | hardware_memory_error(addr); |
20e0ff59 PB |
646 | } |
647 | ||
8efc4e51 ZP |
648 | /* Hope we are lucky for AO MCE, just notify a event */ |
649 | emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false); | |
419fb20a JK |
650 | } |
651 | ||
fd13f23b LA |
652 | static void kvm_reset_exception(CPUX86State *env) |
653 | { | |
654 | env->exception_nr = -1; | |
655 | env->exception_pending = 0; | |
656 | env->exception_injected = 0; | |
657 | env->exception_has_payload = false; | |
658 | env->exception_payload = 0; | |
659 | } | |
660 | ||
661 | static void kvm_queue_exception(CPUX86State *env, | |
662 | int32_t exception_nr, | |
663 | uint8_t exception_has_payload, | |
664 | uint64_t exception_payload) | |
665 | { | |
666 | assert(env->exception_nr == -1); | |
667 | assert(!env->exception_pending); | |
668 | assert(!env->exception_injected); | |
669 | assert(!env->exception_has_payload); | |
670 | ||
671 | env->exception_nr = exception_nr; | |
672 | ||
673 | if (has_exception_payload) { | |
674 | env->exception_pending = 1; | |
675 | ||
676 | env->exception_has_payload = exception_has_payload; | |
677 | env->exception_payload = exception_payload; | |
678 | } else { | |
679 | env->exception_injected = 1; | |
680 | ||
681 | if (exception_nr == EXCP01_DB) { | |
682 | assert(exception_has_payload); | |
683 | env->dr[6] = exception_payload; | |
684 | } else if (exception_nr == EXCP0E_PAGE) { | |
685 | assert(exception_has_payload); | |
686 | env->cr[2] = exception_payload; | |
687 | } else { | |
688 | assert(!exception_has_payload); | |
689 | } | |
690 | } | |
691 | } | |
692 | ||
1bc22652 | 693 | static int kvm_inject_mce_oldstyle(X86CPU *cpu) |
ab443475 | 694 | { |
1bc22652 AF |
695 | CPUX86State *env = &cpu->env; |
696 | ||
fd13f23b | 697 | if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) { |
ab443475 JK |
698 | unsigned int bank, bank_num = env->mcg_cap & 0xff; |
699 | struct kvm_x86_mce mce; | |
700 | ||
fd13f23b | 701 | kvm_reset_exception(env); |
ab443475 JK |
702 | |
703 | /* | |
704 | * There must be at least one bank in use if an MCE is pending. | |
705 | * Find it and use its values for the event injection. | |
706 | */ | |
707 | for (bank = 0; bank < bank_num; bank++) { | |
708 | if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) { | |
709 | break; | |
710 | } | |
711 | } | |
712 | assert(bank < bank_num); | |
713 | ||
714 | mce.bank = bank; | |
715 | mce.status = env->mce_banks[bank * 4 + 1]; | |
716 | mce.mcg_status = env->mcg_status; | |
717 | mce.addr = env->mce_banks[bank * 4 + 2]; | |
718 | mce.misc = env->mce_banks[bank * 4 + 3]; | |
719 | ||
1bc22652 | 720 | return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce); |
ab443475 | 721 | } |
ab443475 JK |
722 | return 0; |
723 | } | |
724 | ||
538f0497 | 725 | static void cpu_update_state(void *opaque, bool running, RunState state) |
b8cc45d6 | 726 | { |
317ac620 | 727 | CPUX86State *env = opaque; |
b8cc45d6 GC |
728 | |
729 | if (running) { | |
730 | env->tsc_valid = false; | |
731 | } | |
732 | } | |
733 | ||
83b17af5 | 734 | unsigned long kvm_arch_vcpu_id(CPUState *cs) |
b164e48e | 735 | { |
83b17af5 | 736 | X86CPU *cpu = X86_CPU(cs); |
7e72a45c | 737 | return cpu->apic_id; |
b164e48e EH |
738 | } |
739 | ||
92067bf4 IM |
740 | #ifndef KVM_CPUID_SIGNATURE_NEXT |
741 | #define KVM_CPUID_SIGNATURE_NEXT 0x40000100 | |
742 | #endif | |
743 | ||
92067bf4 IM |
744 | static bool hyperv_enabled(X86CPU *cpu) |
745 | { | |
5aa9ef5e | 746 | return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 && |
f701c082 | 747 | ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) || |
e48ddcc6 | 748 | cpu->hyperv_features || cpu->hyperv_passthrough); |
92067bf4 IM |
749 | } |
750 | ||
74aaddc6 MT |
751 | /* |
752 | * Check whether target_freq is within conservative | |
753 | * ntp correctable bounds (250ppm) of freq | |
754 | */ | |
755 | static inline bool freq_within_bounds(int freq, int target_freq) | |
756 | { | |
757 | int max_freq = freq + (freq * 250 / 1000000); | |
758 | int min_freq = freq - (freq * 250 / 1000000); | |
759 | ||
760 | if (target_freq >= min_freq && target_freq <= max_freq) { | |
761 | return true; | |
762 | } | |
763 | ||
764 | return false; | |
765 | } | |
766 | ||
5031283d HZ |
767 | static int kvm_arch_set_tsc_khz(CPUState *cs) |
768 | { | |
769 | X86CPU *cpu = X86_CPU(cs); | |
770 | CPUX86State *env = &cpu->env; | |
74aaddc6 MT |
771 | int r, cur_freq; |
772 | bool set_ioctl = false; | |
5031283d HZ |
773 | |
774 | if (!env->tsc_khz) { | |
775 | return 0; | |
776 | } | |
777 | ||
74aaddc6 MT |
778 | cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? |
779 | kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP; | |
780 | ||
781 | /* | |
782 | * If TSC scaling is supported, attempt to set TSC frequency. | |
783 | */ | |
784 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) { | |
785 | set_ioctl = true; | |
786 | } | |
787 | ||
788 | /* | |
789 | * If desired TSC frequency is within bounds of NTP correction, | |
790 | * attempt to set TSC frequency. | |
791 | */ | |
792 | if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) { | |
793 | set_ioctl = true; | |
794 | } | |
795 | ||
796 | r = set_ioctl ? | |
5031283d HZ |
797 | kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) : |
798 | -ENOTSUP; | |
74aaddc6 | 799 | |
5031283d HZ |
800 | if (r < 0) { |
801 | /* When KVM_SET_TSC_KHZ fails, it's an error only if the current | |
802 | * TSC frequency doesn't match the one we want. | |
803 | */ | |
74aaddc6 MT |
804 | cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? |
805 | kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : | |
806 | -ENOTSUP; | |
5031283d | 807 | if (cur_freq <= 0 || cur_freq != env->tsc_khz) { |
3dc6f869 AF |
808 | warn_report("TSC frequency mismatch between " |
809 | "VM (%" PRId64 " kHz) and host (%d kHz), " | |
810 | "and TSC scaling unavailable", | |
811 | env->tsc_khz, cur_freq); | |
5031283d HZ |
812 | return r; |
813 | } | |
814 | } | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
4bb95b82 LP |
819 | static bool tsc_is_stable_and_known(CPUX86State *env) |
820 | { | |
821 | if (!env->tsc_khz) { | |
822 | return false; | |
823 | } | |
824 | return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) | |
825 | || env->user_tsc_khz; | |
826 | } | |
827 | ||
6760bd20 VK |
828 | static struct { |
829 | const char *desc; | |
830 | struct { | |
061817a7 VK |
831 | uint32_t func; |
832 | int reg; | |
6760bd20 VK |
833 | uint32_t bits; |
834 | } flags[2]; | |
c6861930 | 835 | uint64_t dependencies; |
6760bd20 VK |
836 | } kvm_hyperv_properties[] = { |
837 | [HYPERV_FEAT_RELAXED] = { | |
838 | .desc = "relaxed timing (hv-relaxed)", | |
839 | .flags = { | |
061817a7 | 840 | {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, |
6760bd20 VK |
841 | .bits = HV_RELAXED_TIMING_RECOMMENDED} |
842 | } | |
843 | }, | |
844 | [HYPERV_FEAT_VAPIC] = { | |
845 | .desc = "virtual APIC (hv-vapic)", | |
846 | .flags = { | |
061817a7 | 847 | {.func = HV_CPUID_FEATURES, .reg = R_EAX, |
05071629 | 848 | .bits = HV_APIC_ACCESS_AVAILABLE} |
6760bd20 VK |
849 | } |
850 | }, | |
851 | [HYPERV_FEAT_TIME] = { | |
852 | .desc = "clocksources (hv-time)", | |
853 | .flags = { | |
061817a7 | 854 | {.func = HV_CPUID_FEATURES, .reg = R_EAX, |
b26f68c3 | 855 | .bits = HV_TIME_REF_COUNT_AVAILABLE | HV_REFERENCE_TSC_AVAILABLE} |
6760bd20 VK |
856 | } |
857 | }, | |
858 | [HYPERV_FEAT_CRASH] = { | |
859 | .desc = "crash MSRs (hv-crash)", | |
860 | .flags = { | |
061817a7 | 861 | {.func = HV_CPUID_FEATURES, .reg = R_EDX, |
6760bd20 VK |
862 | .bits = HV_GUEST_CRASH_MSR_AVAILABLE} |
863 | } | |
864 | }, | |
865 | [HYPERV_FEAT_RESET] = { | |
866 | .desc = "reset MSR (hv-reset)", | |
867 | .flags = { | |
061817a7 | 868 | {.func = HV_CPUID_FEATURES, .reg = R_EAX, |
6760bd20 VK |
869 | .bits = HV_RESET_AVAILABLE} |
870 | } | |
871 | }, | |
872 | [HYPERV_FEAT_VPINDEX] = { | |
873 | .desc = "VP_INDEX MSR (hv-vpindex)", | |
874 | .flags = { | |
061817a7 | 875 | {.func = HV_CPUID_FEATURES, .reg = R_EAX, |
6760bd20 VK |
876 | .bits = HV_VP_INDEX_AVAILABLE} |
877 | } | |
878 | }, | |
879 | [HYPERV_FEAT_RUNTIME] = { | |
880 | .desc = "VP_RUNTIME MSR (hv-runtime)", | |
881 | .flags = { | |
061817a7 | 882 | {.func = HV_CPUID_FEATURES, .reg = R_EAX, |
6760bd20 VK |
883 | .bits = HV_VP_RUNTIME_AVAILABLE} |
884 | } | |
885 | }, | |
886 | [HYPERV_FEAT_SYNIC] = { | |
887 | .desc = "synthetic interrupt controller (hv-synic)", | |
888 | .flags = { | |
061817a7 | 889 | {.func = HV_CPUID_FEATURES, .reg = R_EAX, |
6760bd20 VK |
890 | .bits = HV_SYNIC_AVAILABLE} |
891 | } | |
892 | }, | |
893 | [HYPERV_FEAT_STIMER] = { | |
894 | .desc = "synthetic timers (hv-stimer)", | |
895 | .flags = { | |
061817a7 | 896 | {.func = HV_CPUID_FEATURES, .reg = R_EAX, |
6760bd20 | 897 | .bits = HV_SYNTIMERS_AVAILABLE} |
c6861930 VK |
898 | }, |
899 | .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME) | |
6760bd20 VK |
900 | }, |
901 | [HYPERV_FEAT_FREQUENCIES] = { | |
902 | .desc = "frequency MSRs (hv-frequencies)", | |
903 | .flags = { | |
061817a7 | 904 | {.func = HV_CPUID_FEATURES, .reg = R_EAX, |
6760bd20 | 905 | .bits = HV_ACCESS_FREQUENCY_MSRS}, |
061817a7 | 906 | {.func = HV_CPUID_FEATURES, .reg = R_EDX, |
6760bd20 VK |
907 | .bits = HV_FREQUENCY_MSRS_AVAILABLE} |
908 | } | |
909 | }, | |
910 | [HYPERV_FEAT_REENLIGHTENMENT] = { | |
911 | .desc = "reenlightenment MSRs (hv-reenlightenment)", | |
912 | .flags = { | |
061817a7 | 913 | {.func = HV_CPUID_FEATURES, .reg = R_EAX, |
6760bd20 VK |
914 | .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL} |
915 | } | |
916 | }, | |
917 | [HYPERV_FEAT_TLBFLUSH] = { | |
918 | .desc = "paravirtualized TLB flush (hv-tlbflush)", | |
919 | .flags = { | |
061817a7 | 920 | {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, |
6760bd20 VK |
921 | .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED | |
922 | HV_EX_PROCESSOR_MASKS_RECOMMENDED} | |
bd59fbdf VK |
923 | }, |
924 | .dependencies = BIT(HYPERV_FEAT_VPINDEX) | |
6760bd20 VK |
925 | }, |
926 | [HYPERV_FEAT_EVMCS] = { | |
927 | .desc = "enlightened VMCS (hv-evmcs)", | |
928 | .flags = { | |
061817a7 | 929 | {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, |
6760bd20 | 930 | .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED} |
8caba36d VK |
931 | }, |
932 | .dependencies = BIT(HYPERV_FEAT_VAPIC) | |
6760bd20 VK |
933 | }, |
934 | [HYPERV_FEAT_IPI] = { | |
935 | .desc = "paravirtualized IPI (hv-ipi)", | |
936 | .flags = { | |
061817a7 | 937 | {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, |
6760bd20 VK |
938 | .bits = HV_CLUSTER_IPI_RECOMMENDED | |
939 | HV_EX_PROCESSOR_MASKS_RECOMMENDED} | |
bd59fbdf VK |
940 | }, |
941 | .dependencies = BIT(HYPERV_FEAT_VPINDEX) | |
6760bd20 | 942 | }, |
128531d9 VK |
943 | [HYPERV_FEAT_STIMER_DIRECT] = { |
944 | .desc = "direct mode synthetic timers (hv-stimer-direct)", | |
945 | .flags = { | |
061817a7 | 946 | {.func = HV_CPUID_FEATURES, .reg = R_EDX, |
128531d9 VK |
947 | .bits = HV_STIMER_DIRECT_MODE_AVAILABLE} |
948 | }, | |
949 | .dependencies = BIT(HYPERV_FEAT_STIMER) | |
950 | }, | |
e1f9a8e8 VK |
951 | [HYPERV_FEAT_AVIC] = { |
952 | .desc = "AVIC/APICv support (hv-avic/hv-apicv)", | |
953 | .flags = { | |
954 | {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX, | |
955 | .bits = HV_DEPRECATING_AEOI_RECOMMENDED} | |
956 | } | |
957 | }, | |
6760bd20 VK |
958 | }; |
959 | ||
2e905438 VK |
960 | static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max, |
961 | bool do_sys_ioctl) | |
6760bd20 VK |
962 | { |
963 | struct kvm_cpuid2 *cpuid; | |
964 | int r, size; | |
965 | ||
966 | size = sizeof(*cpuid) + max * sizeof(*cpuid->entries); | |
967 | cpuid = g_malloc0(size); | |
968 | cpuid->nent = max; | |
969 | ||
2e905438 VK |
970 | if (do_sys_ioctl) { |
971 | r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid); | |
972 | } else { | |
973 | r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid); | |
974 | } | |
6760bd20 VK |
975 | if (r == 0 && cpuid->nent >= max) { |
976 | r = -E2BIG; | |
977 | } | |
978 | if (r < 0) { | |
979 | if (r == -E2BIG) { | |
980 | g_free(cpuid); | |
981 | return NULL; | |
982 | } else { | |
983 | fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n", | |
984 | strerror(-r)); | |
985 | exit(1); | |
986 | } | |
987 | } | |
988 | return cpuid; | |
989 | } | |
990 | ||
991 | /* | |
992 | * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough | |
993 | * for all entries. | |
994 | */ | |
995 | static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs) | |
996 | { | |
997 | struct kvm_cpuid2 *cpuid; | |
05c900ce VK |
998 | /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000080 leaves */ |
999 | int max = 10; | |
decb4f20 | 1000 | int i; |
2e905438 VK |
1001 | bool do_sys_ioctl; |
1002 | ||
1003 | do_sys_ioctl = | |
1004 | kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0; | |
6760bd20 | 1005 | |
e4adb09f VK |
1006 | /* |
1007 | * Non-empty KVM context is needed when KVM_CAP_SYS_HYPERV_CPUID is | |
1008 | * unsupported, kvm_hyperv_expand_features() checks for that. | |
1009 | */ | |
1010 | assert(do_sys_ioctl || cs->kvm_state); | |
1011 | ||
6760bd20 VK |
1012 | /* |
1013 | * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with | |
1014 | * -E2BIG, however, it doesn't report back the right size. Keep increasing | |
1015 | * it and re-trying until we succeed. | |
1016 | */ | |
2e905438 | 1017 | while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) { |
6760bd20 VK |
1018 | max++; |
1019 | } | |
decb4f20 VK |
1020 | |
1021 | /* | |
1022 | * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before | |
1023 | * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the | |
1024 | * information early, just check for the capability and set the bit | |
1025 | * manually. | |
1026 | */ | |
2e905438 | 1027 | if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state, |
decb4f20 VK |
1028 | KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) { |
1029 | for (i = 0; i < cpuid->nent; i++) { | |
1030 | if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) { | |
1031 | cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED; | |
1032 | } | |
1033 | } | |
1034 | } | |
1035 | ||
6760bd20 VK |
1036 | return cpuid; |
1037 | } | |
1038 | ||
1039 | /* | |
1040 | * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature | |
1041 | * leaves from KVM_CAP_HYPERV* and present MSRs data. | |
1042 | */ | |
1043 | static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs) | |
c35bd19a EY |
1044 | { |
1045 | X86CPU *cpu = X86_CPU(cs); | |
6760bd20 VK |
1046 | struct kvm_cpuid2 *cpuid; |
1047 | struct kvm_cpuid_entry2 *entry_feat, *entry_recomm; | |
1048 | ||
1049 | /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */ | |
1050 | cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries)); | |
1051 | cpuid->nent = 2; | |
1052 | ||
1053 | /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */ | |
1054 | entry_feat = &cpuid->entries[0]; | |
1055 | entry_feat->function = HV_CPUID_FEATURES; | |
1056 | ||
1057 | entry_recomm = &cpuid->entries[1]; | |
1058 | entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO; | |
1059 | entry_recomm->ebx = cpu->hyperv_spinlock_attempts; | |
1060 | ||
1061 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) { | |
1062 | entry_feat->eax |= HV_HYPERCALL_AVAILABLE; | |
1063 | entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE; | |
1064 | entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE; | |
1065 | entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED; | |
1066 | entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED; | |
1067 | } | |
c35bd19a | 1068 | |
6760bd20 VK |
1069 | if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) { |
1070 | entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE; | |
1071 | entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE; | |
c35bd19a | 1072 | } |
6760bd20 VK |
1073 | |
1074 | if (has_msr_hv_frequencies) { | |
1075 | entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS; | |
1076 | entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE; | |
c35bd19a | 1077 | } |
6760bd20 VK |
1078 | |
1079 | if (has_msr_hv_crash) { | |
1080 | entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE; | |
9445597b | 1081 | } |
6760bd20 VK |
1082 | |
1083 | if (has_msr_hv_reenlightenment) { | |
1084 | entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL; | |
c35bd19a | 1085 | } |
6760bd20 VK |
1086 | |
1087 | if (has_msr_hv_reset) { | |
1088 | entry_feat->eax |= HV_RESET_AVAILABLE; | |
c35bd19a | 1089 | } |
6760bd20 VK |
1090 | |
1091 | if (has_msr_hv_vpindex) { | |
1092 | entry_feat->eax |= HV_VP_INDEX_AVAILABLE; | |
ba6a4fd9 | 1093 | } |
6760bd20 VK |
1094 | |
1095 | if (has_msr_hv_runtime) { | |
1096 | entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE; | |
c35bd19a | 1097 | } |
6760bd20 VK |
1098 | |
1099 | if (has_msr_hv_synic) { | |
1100 | unsigned int cap = cpu->hyperv_synic_kvm_only ? | |
1101 | KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; | |
1102 | ||
1103 | if (kvm_check_extension(cs->kvm_state, cap) > 0) { | |
1104 | entry_feat->eax |= HV_SYNIC_AVAILABLE; | |
1221f150 | 1105 | } |
c35bd19a | 1106 | } |
6760bd20 VK |
1107 | |
1108 | if (has_msr_hv_stimer) { | |
1109 | entry_feat->eax |= HV_SYNTIMERS_AVAILABLE; | |
c35bd19a | 1110 | } |
9b4cf107 | 1111 | |
6760bd20 VK |
1112 | if (kvm_check_extension(cs->kvm_state, |
1113 | KVM_CAP_HYPERV_TLBFLUSH) > 0) { | |
1114 | entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED; | |
1115 | entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED; | |
1116 | } | |
c35bd19a | 1117 | |
6760bd20 VK |
1118 | if (kvm_check_extension(cs->kvm_state, |
1119 | KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) { | |
1120 | entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED; | |
c35bd19a | 1121 | } |
6760bd20 VK |
1122 | |
1123 | if (kvm_check_extension(cs->kvm_state, | |
1124 | KVM_CAP_HYPERV_SEND_IPI) > 0) { | |
1125 | entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED; | |
1126 | entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED; | |
c35bd19a | 1127 | } |
6760bd20 VK |
1128 | |
1129 | return cpuid; | |
1130 | } | |
1131 | ||
a8439be6 | 1132 | static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg) |
e1a66a1e VK |
1133 | { |
1134 | struct kvm_cpuid_entry2 *entry; | |
a8439be6 VK |
1135 | struct kvm_cpuid2 *cpuid; |
1136 | ||
1137 | if (hv_cpuid_cache) { | |
1138 | cpuid = hv_cpuid_cache; | |
1139 | } else { | |
1140 | if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) { | |
1141 | cpuid = get_supported_hv_cpuid(cs); | |
1142 | } else { | |
e4adb09f VK |
1143 | /* |
1144 | * 'cs->kvm_state' may be NULL when Hyper-V features are expanded | |
1145 | * before KVM context is created but this is only done when | |
1146 | * KVM_CAP_SYS_HYPERV_CPUID is supported and it implies | |
1147 | * KVM_CAP_HYPERV_CPUID. | |
1148 | */ | |
1149 | assert(cs->kvm_state); | |
1150 | ||
a8439be6 VK |
1151 | cpuid = get_supported_hv_cpuid_legacy(cs); |
1152 | } | |
1153 | hv_cpuid_cache = cpuid; | |
1154 | } | |
1155 | ||
1156 | if (!cpuid) { | |
1157 | return 0; | |
1158 | } | |
e1a66a1e VK |
1159 | |
1160 | entry = cpuid_find_entry(cpuid, func, 0); | |
1161 | if (!entry) { | |
1162 | return 0; | |
1163 | } | |
1164 | ||
1165 | return cpuid_entry_get_reg(entry, reg); | |
1166 | } | |
1167 | ||
a8439be6 | 1168 | static bool hyperv_feature_supported(CPUState *cs, int feature) |
7682f857 | 1169 | { |
061817a7 VK |
1170 | uint32_t func, bits; |
1171 | int i, reg; | |
7682f857 VK |
1172 | |
1173 | for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) { | |
061817a7 VK |
1174 | |
1175 | func = kvm_hyperv_properties[feature].flags[i].func; | |
1176 | reg = kvm_hyperv_properties[feature].flags[i].reg; | |
7682f857 VK |
1177 | bits = kvm_hyperv_properties[feature].flags[i].bits; |
1178 | ||
061817a7 | 1179 | if (!func) { |
7682f857 VK |
1180 | continue; |
1181 | } | |
1182 | ||
a8439be6 | 1183 | if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) { |
7682f857 VK |
1184 | return false; |
1185 | } | |
1186 | } | |
1187 | ||
1188 | return true; | |
1189 | } | |
1190 | ||
5ce48fa3 VK |
1191 | /* Checks that all feature dependencies are enabled */ |
1192 | static bool hv_feature_check_deps(X86CPU *cpu, int feature, Error **errp) | |
6760bd20 | 1193 | { |
c6861930 | 1194 | uint64_t deps; |
7682f857 | 1195 | int dep_feat; |
6760bd20 | 1196 | |
c6861930 | 1197 | deps = kvm_hyperv_properties[feature].dependencies; |
9dc83cd9 HR |
1198 | while (deps) { |
1199 | dep_feat = ctz64(deps); | |
c6861930 | 1200 | if (!(hyperv_feat_enabled(cpu, dep_feat))) { |
f4a62495 VK |
1201 | error_setg(errp, "Hyper-V %s requires Hyper-V %s", |
1202 | kvm_hyperv_properties[feature].desc, | |
1203 | kvm_hyperv_properties[dep_feat].desc); | |
5ce48fa3 | 1204 | return false; |
c6861930 | 1205 | } |
9dc83cd9 | 1206 | deps &= ~(1ull << dep_feat); |
c6861930 VK |
1207 | } |
1208 | ||
5ce48fa3 | 1209 | return true; |
6760bd20 VK |
1210 | } |
1211 | ||
061817a7 | 1212 | static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg) |
c830015e VK |
1213 | { |
1214 | X86CPU *cpu = X86_CPU(cs); | |
1215 | uint32_t r = 0; | |
1216 | int i, j; | |
1217 | ||
1218 | for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) { | |
1219 | if (!hyperv_feat_enabled(cpu, i)) { | |
1220 | continue; | |
1221 | } | |
1222 | ||
1223 | for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) { | |
061817a7 VK |
1224 | if (kvm_hyperv_properties[i].flags[j].func != func) { |
1225 | continue; | |
1226 | } | |
1227 | if (kvm_hyperv_properties[i].flags[j].reg != reg) { | |
c830015e VK |
1228 | continue; |
1229 | } | |
1230 | ||
1231 | r |= kvm_hyperv_properties[i].flags[j].bits; | |
1232 | } | |
1233 | } | |
1234 | ||
1235 | return r; | |
1236 | } | |
1237 | ||
2344d22e | 1238 | /* |
f6e01ab5 VK |
1239 | * Expand Hyper-V CPU features. In partucular, check that all the requested |
1240 | * features are supported by the host and the sanity of the configuration | |
1241 | * (that all the required dependencies are included). Also, this takes care | |
1242 | * of 'hv_passthrough' mode and fills the environment with all supported | |
1243 | * Hyper-V features. | |
2344d22e | 1244 | */ |
071ce4b0 | 1245 | bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp) |
6760bd20 | 1246 | { |
071ce4b0 | 1247 | CPUState *cs = CPU(cpu); |
5ce48fa3 VK |
1248 | Error *local_err = NULL; |
1249 | int feat; | |
6760bd20 | 1250 | |
2344d22e | 1251 | if (!hyperv_enabled(cpu)) |
d7652b77 | 1252 | return true; |
2344d22e | 1253 | |
071ce4b0 VK |
1254 | /* |
1255 | * When kvm_hyperv_expand_features is called at CPU feature expansion | |
1256 | * time per-CPU kvm_state is not available yet so we can only proceed | |
1257 | * when KVM_CAP_SYS_HYPERV_CPUID is supported. | |
1258 | */ | |
1259 | if (!cs->kvm_state && | |
1260 | !kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID)) | |
1261 | return true; | |
1262 | ||
e48ddcc6 | 1263 | if (cpu->hyperv_passthrough) { |
e1a66a1e | 1264 | cpu->hyperv_vendor_id[0] = |
a8439be6 | 1265 | hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX); |
e1a66a1e | 1266 | cpu->hyperv_vendor_id[1] = |
a8439be6 | 1267 | hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX); |
e1a66a1e | 1268 | cpu->hyperv_vendor_id[2] = |
a8439be6 | 1269 | hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX); |
e1a66a1e VK |
1270 | cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor, |
1271 | sizeof(cpu->hyperv_vendor_id) + 1); | |
1272 | memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id, | |
1273 | sizeof(cpu->hyperv_vendor_id)); | |
1274 | cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0; | |
1275 | ||
1276 | cpu->hyperv_interface_id[0] = | |
a8439be6 | 1277 | hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX); |
e1a66a1e | 1278 | cpu->hyperv_interface_id[1] = |
a8439be6 | 1279 | hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX); |
e1a66a1e | 1280 | cpu->hyperv_interface_id[2] = |
a8439be6 | 1281 | hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX); |
e1a66a1e | 1282 | cpu->hyperv_interface_id[3] = |
a8439be6 | 1283 | hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX); |
e1a66a1e | 1284 | |
af7228b8 | 1285 | cpu->hyperv_ver_id_build = |
a8439be6 | 1286 | hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX); |
af7228b8 VK |
1287 | cpu->hyperv_ver_id_major = |
1288 | hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) >> 16; | |
1289 | cpu->hyperv_ver_id_minor = | |
1290 | hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX) & 0xffff; | |
1291 | cpu->hyperv_ver_id_sp = | |
a8439be6 | 1292 | hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX); |
af7228b8 VK |
1293 | cpu->hyperv_ver_id_sb = |
1294 | hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) >> 24; | |
1295 | cpu->hyperv_ver_id_sn = | |
1296 | hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX) & 0xffffff; | |
e1a66a1e | 1297 | |
a8439be6 | 1298 | cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, |
e1a66a1e VK |
1299 | R_EAX); |
1300 | cpu->hyperv_limits[0] = | |
a8439be6 | 1301 | hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX); |
e1a66a1e | 1302 | cpu->hyperv_limits[1] = |
a8439be6 | 1303 | hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX); |
e1a66a1e | 1304 | cpu->hyperv_limits[2] = |
a8439be6 | 1305 | hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX); |
e1a66a1e VK |
1306 | |
1307 | cpu->hyperv_spinlock_attempts = | |
a8439be6 | 1308 | hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX); |
30d6ff66 | 1309 | |
5ce48fa3 VK |
1310 | /* |
1311 | * Mark feature as enabled in 'cpu->hyperv_features' as | |
1312 | * hv_build_cpuid_leaf() uses this info to build guest CPUIDs. | |
1313 | */ | |
1314 | for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) { | |
1315 | if (hyperv_feature_supported(cs, feat)) { | |
1316 | cpu->hyperv_features |= BIT(feat); | |
1317 | } | |
1318 | } | |
1319 | } else { | |
1320 | /* Check features availability and dependencies */ | |
1321 | for (feat = 0; feat < ARRAY_SIZE(kvm_hyperv_properties); feat++) { | |
1322 | /* If the feature was not requested skip it. */ | |
1323 | if (!hyperv_feat_enabled(cpu, feat)) { | |
1324 | continue; | |
1325 | } | |
1326 | ||
1327 | /* Check if the feature is supported by KVM */ | |
1328 | if (!hyperv_feature_supported(cs, feat)) { | |
1329 | error_setg(errp, "Hyper-V %s is not supported by kernel", | |
1330 | kvm_hyperv_properties[feat].desc); | |
1331 | return false; | |
1332 | } | |
1333 | ||
1334 | /* Check dependencies */ | |
1335 | if (!hv_feature_check_deps(cpu, feat, &local_err)) { | |
1336 | error_propagate(errp, local_err); | |
1337 | return false; | |
1338 | } | |
1339 | } | |
f4a62495 | 1340 | } |
6760bd20 | 1341 | |
c6861930 | 1342 | /* Additional dependencies not covered by kvm_hyperv_properties[] */ |
6760bd20 VK |
1343 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && |
1344 | !cpu->hyperv_synic_kvm_only && | |
1345 | !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) { | |
f4a62495 VK |
1346 | error_setg(errp, "Hyper-V %s requires Hyper-V %s", |
1347 | kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc, | |
1348 | kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc); | |
d7652b77 | 1349 | return false; |
6760bd20 | 1350 | } |
d7652b77 VK |
1351 | |
1352 | return true; | |
f6e01ab5 VK |
1353 | } |
1354 | ||
1355 | /* | |
1356 | * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent. | |
1357 | */ | |
1358 | static int hyperv_fill_cpuids(CPUState *cs, | |
1359 | struct kvm_cpuid_entry2 *cpuid_ent) | |
1360 | { | |
1361 | X86CPU *cpu = X86_CPU(cs); | |
1362 | struct kvm_cpuid_entry2 *c; | |
1363 | uint32_t cpuid_i = 0; | |
1364 | ||
2344d22e VK |
1365 | c = &cpuid_ent[cpuid_i++]; |
1366 | c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; | |
2344d22e VK |
1367 | c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? |
1368 | HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; | |
08856771 VK |
1369 | c->ebx = cpu->hyperv_vendor_id[0]; |
1370 | c->ecx = cpu->hyperv_vendor_id[1]; | |
1371 | c->edx = cpu->hyperv_vendor_id[2]; | |
2344d22e VK |
1372 | |
1373 | c = &cpuid_ent[cpuid_i++]; | |
1374 | c->function = HV_CPUID_INTERFACE; | |
735db465 VK |
1375 | c->eax = cpu->hyperv_interface_id[0]; |
1376 | c->ebx = cpu->hyperv_interface_id[1]; | |
1377 | c->ecx = cpu->hyperv_interface_id[2]; | |
1378 | c->edx = cpu->hyperv_interface_id[3]; | |
2344d22e VK |
1379 | |
1380 | c = &cpuid_ent[cpuid_i++]; | |
1381 | c->function = HV_CPUID_VERSION; | |
af7228b8 VK |
1382 | c->eax = cpu->hyperv_ver_id_build; |
1383 | c->ebx = (uint32_t)cpu->hyperv_ver_id_major << 16 | | |
1384 | cpu->hyperv_ver_id_minor; | |
1385 | c->ecx = cpu->hyperv_ver_id_sp; | |
1386 | c->edx = (uint32_t)cpu->hyperv_ver_id_sb << 24 | | |
1387 | (cpu->hyperv_ver_id_sn & 0xffffff); | |
2344d22e VK |
1388 | |
1389 | c = &cpuid_ent[cpuid_i++]; | |
1390 | c->function = HV_CPUID_FEATURES; | |
061817a7 VK |
1391 | c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX); |
1392 | c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX); | |
1393 | c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX); | |
c830015e | 1394 | |
b26f68c3 VK |
1395 | /* Unconditionally required with any Hyper-V enlightenment */ |
1396 | c->eax |= HV_HYPERCALL_AVAILABLE; | |
1397 | ||
cce087f6 VK |
1398 | /* SynIC and Vmbus devices require messages/signals hypercalls */ |
1399 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) && | |
1400 | !cpu->hyperv_synic_kvm_only) { | |
1401 | c->ebx |= HV_POST_MESSAGES | HV_SIGNAL_EVENTS; | |
1402 | } | |
1403 | ||
05071629 | 1404 | |
c830015e VK |
1405 | /* Not exposed by KVM but needed to make CPU hotplug in Windows work */ |
1406 | c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE; | |
2344d22e VK |
1407 | |
1408 | c = &cpuid_ent[cpuid_i++]; | |
1409 | c->function = HV_CPUID_ENLIGHTMENT_INFO; | |
061817a7 | 1410 | c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX); |
2344d22e VK |
1411 | c->ebx = cpu->hyperv_spinlock_attempts; |
1412 | ||
e1f9a8e8 VK |
1413 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC) && |
1414 | !hyperv_feat_enabled(cpu, HYPERV_FEAT_AVIC)) { | |
05071629 VK |
1415 | c->eax |= HV_APIC_ACCESS_RECOMMENDED; |
1416 | } | |
1417 | ||
c830015e VK |
1418 | if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) { |
1419 | c->eax |= HV_NO_NONARCH_CORESHARING; | |
1420 | } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) { | |
a8439be6 | 1421 | c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) & |
e1a66a1e | 1422 | HV_NO_NONARCH_CORESHARING; |
c830015e VK |
1423 | } |
1424 | ||
2344d22e VK |
1425 | c = &cpuid_ent[cpuid_i++]; |
1426 | c->function = HV_CPUID_IMPLEMENT_LIMITS; | |
1427 | c->eax = cpu->hv_max_vps; | |
23eb5d03 VK |
1428 | c->ebx = cpu->hyperv_limits[0]; |
1429 | c->ecx = cpu->hyperv_limits[1]; | |
1430 | c->edx = cpu->hyperv_limits[2]; | |
2344d22e VK |
1431 | |
1432 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { | |
dc7d6caf | 1433 | uint32_t function; |
2344d22e VK |
1434 | |
1435 | /* Create zeroed 0x40000006..0x40000009 leaves */ | |
1436 | for (function = HV_CPUID_IMPLEMENT_LIMITS + 1; | |
1437 | function < HV_CPUID_NESTED_FEATURES; function++) { | |
1438 | c = &cpuid_ent[cpuid_i++]; | |
1439 | c->function = function; | |
1440 | } | |
1441 | ||
1442 | c = &cpuid_ent[cpuid_i++]; | |
1443 | c->function = HV_CPUID_NESTED_FEATURES; | |
c830015e | 1444 | c->eax = cpu->hyperv_nested[0]; |
2344d22e | 1445 | } |
6760bd20 | 1446 | |
a8439be6 | 1447 | return cpuid_i; |
c35bd19a EY |
1448 | } |
1449 | ||
e48ddcc6 | 1450 | static Error *hv_passthrough_mig_blocker; |
30d6ff66 | 1451 | static Error *hv_no_nonarch_cs_mig_blocker; |
e48ddcc6 | 1452 | |
07454e2e VK |
1453 | /* Checks that the exposed eVMCS version range is supported by KVM */ |
1454 | static bool evmcs_version_supported(uint16_t evmcs_version, | |
1455 | uint16_t supported_evmcs_version) | |
1456 | { | |
1457 | uint8_t min_version = evmcs_version & 0xff; | |
1458 | uint8_t max_version = evmcs_version >> 8; | |
1459 | uint8_t min_supported_version = supported_evmcs_version & 0xff; | |
1460 | uint8_t max_supported_version = supported_evmcs_version >> 8; | |
1461 | ||
1462 | return (min_version >= min_supported_version) && | |
1463 | (max_version <= max_supported_version); | |
1464 | } | |
1465 | ||
1466 | #define DEFAULT_EVMCS_VERSION ((1 << 8) | 1) | |
1467 | ||
e9688fab RK |
1468 | static int hyperv_init_vcpu(X86CPU *cpu) |
1469 | { | |
729ce7e1 | 1470 | CPUState *cs = CPU(cpu); |
e48ddcc6 | 1471 | Error *local_err = NULL; |
729ce7e1 RK |
1472 | int ret; |
1473 | ||
e48ddcc6 VK |
1474 | if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) { |
1475 | error_setg(&hv_passthrough_mig_blocker, | |
1476 | "'hv-passthrough' CPU flag prevents migration, use explicit" | |
1477 | " set of hv-* flags instead"); | |
1478 | ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err); | |
436c831a | 1479 | if (ret < 0) { |
e48ddcc6 | 1480 | error_report_err(local_err); |
e48ddcc6 VK |
1481 | return ret; |
1482 | } | |
1483 | } | |
1484 | ||
30d6ff66 VK |
1485 | if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO && |
1486 | hv_no_nonarch_cs_mig_blocker == NULL) { | |
1487 | error_setg(&hv_no_nonarch_cs_mig_blocker, | |
1488 | "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration" | |
1489 | " use explicit 'hv-no-nonarch-coresharing=on' instead (but" | |
1490 | " make sure SMT is disabled and/or that vCPUs are properly" | |
1491 | " pinned)"); | |
1492 | ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err); | |
436c831a | 1493 | if (ret < 0) { |
30d6ff66 | 1494 | error_report_err(local_err); |
30d6ff66 VK |
1495 | return ret; |
1496 | } | |
1497 | } | |
1498 | ||
2d384d7c | 1499 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) { |
e9688fab RK |
1500 | /* |
1501 | * the kernel doesn't support setting vp_index; assert that its value | |
1502 | * is in sync | |
1503 | */ | |
e9688fab RK |
1504 | struct { |
1505 | struct kvm_msrs info; | |
1506 | struct kvm_msr_entry entries[1]; | |
1507 | } msr_data = { | |
1508 | .info.nmsrs = 1, | |
1509 | .entries[0].index = HV_X64_MSR_VP_INDEX, | |
1510 | }; | |
1511 | ||
729ce7e1 | 1512 | ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data); |
e9688fab RK |
1513 | if (ret < 0) { |
1514 | return ret; | |
1515 | } | |
1516 | assert(ret == 1); | |
1517 | ||
701189e3 | 1518 | if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) { |
e9688fab RK |
1519 | error_report("kernel's vp_index != QEMU's vp_index"); |
1520 | return -ENXIO; | |
1521 | } | |
1522 | } | |
1523 | ||
2d384d7c | 1524 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { |
9b4cf107 RK |
1525 | uint32_t synic_cap = cpu->hyperv_synic_kvm_only ? |
1526 | KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2; | |
1527 | ret = kvm_vcpu_enable_cap(cs, synic_cap, 0); | |
729ce7e1 RK |
1528 | if (ret < 0) { |
1529 | error_report("failed to turn on HyperV SynIC in KVM: %s", | |
1530 | strerror(-ret)); | |
1531 | return ret; | |
1532 | } | |
606c34bf | 1533 | |
9b4cf107 RK |
1534 | if (!cpu->hyperv_synic_kvm_only) { |
1535 | ret = hyperv_x86_synic_add(cpu); | |
1536 | if (ret < 0) { | |
1537 | error_report("failed to create HyperV SynIC: %s", | |
1538 | strerror(-ret)); | |
1539 | return ret; | |
1540 | } | |
606c34bf | 1541 | } |
729ce7e1 RK |
1542 | } |
1543 | ||
decb4f20 | 1544 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { |
07454e2e VK |
1545 | uint16_t evmcs_version = DEFAULT_EVMCS_VERSION; |
1546 | uint16_t supported_evmcs_version; | |
decb4f20 VK |
1547 | |
1548 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0, | |
07454e2e | 1549 | (uintptr_t)&supported_evmcs_version); |
decb4f20 | 1550 | |
07454e2e VK |
1551 | /* |
1552 | * KVM is required to support EVMCS ver.1. as that's what 'hv-evmcs' | |
1553 | * option sets. Note: we hardcode the maximum supported eVMCS version | |
1554 | * to '1' as well so 'hv-evmcs' feature is migratable even when (and if) | |
1555 | * ver.2 is implemented. A new option (e.g. 'hv-evmcs=2') will then have | |
1556 | * to be added. | |
1557 | */ | |
decb4f20 | 1558 | if (ret < 0) { |
07454e2e VK |
1559 | error_report("Hyper-V %s is not supported by kernel", |
1560 | kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc); | |
decb4f20 VK |
1561 | return ret; |
1562 | } | |
1563 | ||
07454e2e VK |
1564 | if (!evmcs_version_supported(evmcs_version, supported_evmcs_version)) { |
1565 | error_report("eVMCS version range [%d..%d] is not supported by " | |
1566 | "kernel (supported: [%d..%d])", evmcs_version & 0xff, | |
1567 | evmcs_version >> 8, supported_evmcs_version & 0xff, | |
1568 | supported_evmcs_version >> 8); | |
1569 | return -ENOTSUP; | |
1570 | } | |
1571 | ||
decb4f20 VK |
1572 | cpu->hyperv_nested[0] = evmcs_version; |
1573 | } | |
1574 | ||
70367f09 VK |
1575 | if (cpu->hyperv_enforce_cpuid) { |
1576 | ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENFORCE_CPUID, 0, 1); | |
1577 | if (ret < 0) { | |
1578 | error_report("failed to enable KVM_CAP_HYPERV_ENFORCE_CPUID: %s", | |
1579 | strerror(-ret)); | |
1580 | return ret; | |
1581 | } | |
1582 | } | |
1583 | ||
e9688fab RK |
1584 | return 0; |
1585 | } | |
1586 | ||
68bfd0ad MT |
1587 | static Error *invtsc_mig_blocker; |
1588 | ||
f8bb0565 | 1589 | #define KVM_MAX_CPUID_ENTRIES 100 |
0893d460 | 1590 | |
e56dd3c7 JL |
1591 | static void kvm_init_xsave(CPUX86State *env) |
1592 | { | |
1593 | if (has_xsave2) { | |
1594 | env->xsave_buf_len = QEMU_ALIGN_UP(has_xsave2, 4096); | |
1595 | } else if (has_xsave) { | |
1596 | env->xsave_buf_len = sizeof(struct kvm_xsave); | |
1597 | } else { | |
1598 | return; | |
1599 | } | |
1600 | ||
1601 | env->xsave_buf = qemu_memalign(4096, env->xsave_buf_len); | |
1602 | memset(env->xsave_buf, 0, env->xsave_buf_len); | |
1603 | /* | |
1604 | * The allocated storage must be large enough for all of the | |
1605 | * possible XSAVE state components. | |
1606 | */ | |
1607 | assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <= | |
1608 | env->xsave_buf_len); | |
1609 | } | |
1610 | ||
20d695a9 | 1611 | int kvm_arch_init_vcpu(CPUState *cs) |
05330448 AL |
1612 | { |
1613 | struct { | |
486bd5a2 | 1614 | struct kvm_cpuid2 cpuid; |
f8bb0565 | 1615 | struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES]; |
9115bb12 PM |
1616 | } cpuid_data; |
1617 | /* | |
1618 | * The kernel defines these structs with padding fields so there | |
1619 | * should be no extra padding in our cpuid_data struct. | |
1620 | */ | |
1621 | QEMU_BUILD_BUG_ON(sizeof(cpuid_data) != | |
1622 | sizeof(struct kvm_cpuid2) + | |
1623 | sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES); | |
1624 | ||
20d695a9 AF |
1625 | X86CPU *cpu = X86_CPU(cs); |
1626 | CPUX86State *env = &cpu->env; | |
486bd5a2 | 1627 | uint32_t limit, i, j, cpuid_i; |
a33609ca | 1628 | uint32_t unused; |
bb0300dc | 1629 | struct kvm_cpuid_entry2 *c; |
bb0300dc | 1630 | uint32_t signature[3]; |
234cc647 | 1631 | int kvm_base = KVM_CPUID_SIGNATURE; |
ebbfef2f | 1632 | int max_nested_state_len; |
e7429073 | 1633 | int r; |
fe44dc91 | 1634 | Error *local_err = NULL; |
05330448 | 1635 | |
ef4cbe14 SW |
1636 | memset(&cpuid_data, 0, sizeof(cpuid_data)); |
1637 | ||
05330448 AL |
1638 | cpuid_i = 0; |
1639 | ||
e56dd3c7 JL |
1640 | has_xsave2 = kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2); |
1641 | ||
ddb98b5a LP |
1642 | r = kvm_arch_set_tsc_khz(cs); |
1643 | if (r < 0) { | |
6b2341ee | 1644 | return r; |
ddb98b5a LP |
1645 | } |
1646 | ||
1647 | /* vcpu's TSC frequency is either specified by user, or following | |
1648 | * the value used by KVM if the former is not present. In the | |
1649 | * latter case, we query it from KVM and record in env->tsc_khz, | |
1650 | * so that vcpu's TSC frequency can be migrated later via this field. | |
1651 | */ | |
1652 | if (!env->tsc_khz) { | |
1653 | r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ? | |
1654 | kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : | |
1655 | -ENOTSUP; | |
1656 | if (r > 0) { | |
1657 | env->tsc_khz = r; | |
1658 | } | |
1659 | } | |
1660 | ||
73b994f6 LA |
1661 | env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY; |
1662 | ||
071ce4b0 VK |
1663 | /* |
1664 | * kvm_hyperv_expand_features() is called here for the second time in case | |
1665 | * KVM_CAP_SYS_HYPERV_CPUID is not supported. While we can't possibly handle | |
1666 | * 'query-cpu-model-expansion' in this case as we don't have a KVM vCPU to | |
1667 | * check which Hyper-V enlightenments are supported and which are not, we | |
1668 | * can still proceed and check/expand Hyper-V enlightenments here so legacy | |
1669 | * behavior is preserved. | |
1670 | */ | |
1671 | if (!kvm_hyperv_expand_features(cpu, &local_err)) { | |
f4a62495 VK |
1672 | error_report_err(local_err); |
1673 | return -ENOSYS; | |
f6e01ab5 VK |
1674 | } |
1675 | ||
1676 | if (hyperv_enabled(cpu)) { | |
decb4f20 VK |
1677 | r = hyperv_init_vcpu(cpu); |
1678 | if (r) { | |
1679 | return r; | |
1680 | } | |
1681 | ||
f6e01ab5 | 1682 | cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries); |
234cc647 | 1683 | kvm_base = KVM_CPUID_SIGNATURE_NEXT; |
7bc3d711 | 1684 | has_msr_hv_hypercall = true; |
eab70139 VR |
1685 | } |
1686 | ||
f522d2ac AW |
1687 | if (cpu->expose_kvm) { |
1688 | memcpy(signature, "KVMKVMKVM\0\0\0", 12); | |
1689 | c = &cpuid_data.entries[cpuid_i++]; | |
1690 | c->function = KVM_CPUID_SIGNATURE | kvm_base; | |
79b6f2f6 | 1691 | c->eax = KVM_CPUID_FEATURES | kvm_base; |
f522d2ac AW |
1692 | c->ebx = signature[0]; |
1693 | c->ecx = signature[1]; | |
1694 | c->edx = signature[2]; | |
234cc647 | 1695 | |
f522d2ac AW |
1696 | c = &cpuid_data.entries[cpuid_i++]; |
1697 | c->function = KVM_CPUID_FEATURES | kvm_base; | |
1698 | c->eax = env->features[FEAT_KVM]; | |
be777326 | 1699 | c->edx = env->features[FEAT_KVM_HINTS]; |
f522d2ac | 1700 | } |
917367aa | 1701 | |
a33609ca | 1702 | cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused); |
05330448 | 1703 | |
988f7b8b VK |
1704 | if (cpu->kvm_pv_enforce_cpuid) { |
1705 | r = kvm_vcpu_enable_cap(cs, KVM_CAP_ENFORCE_PV_FEATURE_CPUID, 0, 1); | |
1706 | if (r < 0) { | |
1707 | fprintf(stderr, | |
1708 | "failed to enable KVM_CAP_ENFORCE_PV_FEATURE_CPUID: %s", | |
1709 | strerror(-r)); | |
1710 | abort(); | |
1711 | } | |
1712 | } | |
1713 | ||
05330448 | 1714 | for (i = 0; i <= limit; i++) { |
f8bb0565 IM |
1715 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
1716 | fprintf(stderr, "unsupported level value: 0x%x\n", limit); | |
1717 | abort(); | |
1718 | } | |
bb0300dc | 1719 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
1720 | |
1721 | switch (i) { | |
a36b1029 AL |
1722 | case 2: { |
1723 | /* Keep reading function 2 till all the input is received */ | |
1724 | int times; | |
1725 | ||
a36b1029 | 1726 | c->function = i; |
a33609ca AL |
1727 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC | |
1728 | KVM_CPUID_FLAG_STATE_READ_NEXT; | |
1729 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
1730 | times = c->eax & 0xff; | |
a36b1029 AL |
1731 | |
1732 | for (j = 1; j < times; ++j) { | |
f8bb0565 IM |
1733 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
1734 | fprintf(stderr, "cpuid_data is full, no space for " | |
1735 | "cpuid(eax:2):eax & 0xf = 0x%x\n", times); | |
1736 | abort(); | |
1737 | } | |
a33609ca | 1738 | c = &cpuid_data.entries[cpuid_i++]; |
a36b1029 | 1739 | c->function = i; |
a33609ca AL |
1740 | c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC; |
1741 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
a36b1029 AL |
1742 | } |
1743 | break; | |
1744 | } | |
a94e1428 LX |
1745 | case 0x1f: |
1746 | if (env->nr_dies < 2) { | |
1747 | break; | |
1748 | } | |
8821e214 | 1749 | /* fallthrough */ |
486bd5a2 AL |
1750 | case 4: |
1751 | case 0xb: | |
1752 | case 0xd: | |
1753 | for (j = 0; ; j++) { | |
31e8c696 AP |
1754 | if (i == 0xd && j == 64) { |
1755 | break; | |
1756 | } | |
a94e1428 LX |
1757 | |
1758 | if (i == 0x1f && j == 64) { | |
1759 | break; | |
1760 | } | |
1761 | ||
486bd5a2 AL |
1762 | c->function = i; |
1763 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1764 | c->index = j; | |
a33609ca | 1765 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); |
486bd5a2 | 1766 | |
b9bec74b | 1767 | if (i == 4 && c->eax == 0) { |
486bd5a2 | 1768 | break; |
b9bec74b JK |
1769 | } |
1770 | if (i == 0xb && !(c->ecx & 0xff00)) { | |
486bd5a2 | 1771 | break; |
b9bec74b | 1772 | } |
a94e1428 LX |
1773 | if (i == 0x1f && !(c->ecx & 0xff00)) { |
1774 | break; | |
1775 | } | |
b9bec74b | 1776 | if (i == 0xd && c->eax == 0) { |
31e8c696 | 1777 | continue; |
b9bec74b | 1778 | } |
f8bb0565 IM |
1779 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
1780 | fprintf(stderr, "cpuid_data is full, no space for " | |
1781 | "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); | |
1782 | abort(); | |
1783 | } | |
a33609ca | 1784 | c = &cpuid_data.entries[cpuid_i++]; |
486bd5a2 AL |
1785 | } |
1786 | break; | |
80db491d | 1787 | case 0x7: |
b9edbade SC |
1788 | case 0x12: |
1789 | for (j = 0; ; j++) { | |
1790 | c->function = i; | |
1791 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1792 | c->index = j; | |
1793 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
1794 | ||
1795 | if (j > 1 && (c->eax & 0xf) != 1) { | |
1796 | break; | |
1797 | } | |
1798 | ||
1799 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { | |
1800 | fprintf(stderr, "cpuid_data is full, no space for " | |
1801 | "cpuid(eax:0x12,ecx:0x%x)\n", j); | |
1802 | abort(); | |
1803 | } | |
1804 | c = &cpuid_data.entries[cpuid_i++]; | |
1805 | } | |
1806 | break; | |
f21a4817 JL |
1807 | case 0x14: |
1808 | case 0x1d: | |
1809 | case 0x1e: { | |
e37a5c7f CP |
1810 | uint32_t times; |
1811 | ||
1812 | c->function = i; | |
1813 | c->index = 0; | |
1814 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1815 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
1816 | times = c->eax; | |
1817 | ||
1818 | for (j = 1; j <= times; ++j) { | |
1819 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { | |
1820 | fprintf(stderr, "cpuid_data is full, no space for " | |
80db491d | 1821 | "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); |
e37a5c7f CP |
1822 | abort(); |
1823 | } | |
1824 | c = &cpuid_data.entries[cpuid_i++]; | |
1825 | c->function = i; | |
1826 | c->index = j; | |
1827 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1828 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
1829 | } | |
1830 | break; | |
1831 | } | |
486bd5a2 | 1832 | default: |
486bd5a2 | 1833 | c->function = i; |
a33609ca AL |
1834 | c->flags = 0; |
1835 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
af95cafb EH |
1836 | if (!c->eax && !c->ebx && !c->ecx && !c->edx) { |
1837 | /* | |
1838 | * KVM already returns all zeroes if a CPUID entry is missing, | |
1839 | * so we can omit it and avoid hitting KVM's 80-entry limit. | |
1840 | */ | |
1841 | cpuid_i--; | |
1842 | } | |
486bd5a2 AL |
1843 | break; |
1844 | } | |
05330448 | 1845 | } |
0d894367 PB |
1846 | |
1847 | if (limit >= 0x0a) { | |
0b368a10 | 1848 | uint32_t eax, edx; |
0d894367 | 1849 | |
0b368a10 JD |
1850 | cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx); |
1851 | ||
1852 | has_architectural_pmu_version = eax & 0xff; | |
1853 | if (has_architectural_pmu_version > 0) { | |
1854 | num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8; | |
0d894367 PB |
1855 | |
1856 | /* Shouldn't be more than 32, since that's the number of bits | |
1857 | * available in EBX to tell us _which_ counters are available. | |
1858 | * Play it safe. | |
1859 | */ | |
0b368a10 JD |
1860 | if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) { |
1861 | num_architectural_pmu_gp_counters = MAX_GP_COUNTERS; | |
1862 | } | |
1863 | ||
1864 | if (has_architectural_pmu_version > 1) { | |
1865 | num_architectural_pmu_fixed_counters = edx & 0x1f; | |
1866 | ||
1867 | if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) { | |
1868 | num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS; | |
1869 | } | |
0d894367 PB |
1870 | } |
1871 | } | |
1872 | } | |
1873 | ||
a33609ca | 1874 | cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused); |
05330448 AL |
1875 | |
1876 | for (i = 0x80000000; i <= limit; i++) { | |
f8bb0565 IM |
1877 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
1878 | fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit); | |
1879 | abort(); | |
1880 | } | |
bb0300dc | 1881 | c = &cpuid_data.entries[cpuid_i++]; |
05330448 | 1882 | |
8f4202fb BM |
1883 | switch (i) { |
1884 | case 0x8000001d: | |
1885 | /* Query for all AMD cache information leaves */ | |
1886 | for (j = 0; ; j++) { | |
1887 | c->function = i; | |
1888 | c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX; | |
1889 | c->index = j; | |
1890 | cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
1891 | ||
1892 | if (c->eax == 0) { | |
1893 | break; | |
1894 | } | |
1895 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { | |
1896 | fprintf(stderr, "cpuid_data is full, no space for " | |
1897 | "cpuid(eax:0x%x,ecx:0x%x)\n", i, j); | |
1898 | abort(); | |
1899 | } | |
1900 | c = &cpuid_data.entries[cpuid_i++]; | |
1901 | } | |
1902 | break; | |
1903 | default: | |
1904 | c->function = i; | |
1905 | c->flags = 0; | |
1906 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
af95cafb EH |
1907 | if (!c->eax && !c->ebx && !c->ecx && !c->edx) { |
1908 | /* | |
1909 | * KVM already returns all zeroes if a CPUID entry is missing, | |
1910 | * so we can omit it and avoid hitting KVM's 80-entry limit. | |
1911 | */ | |
1912 | cpuid_i--; | |
1913 | } | |
8f4202fb BM |
1914 | break; |
1915 | } | |
05330448 AL |
1916 | } |
1917 | ||
b3baa152 BW |
1918 | /* Call Centaur's CPUID instructions they are supported. */ |
1919 | if (env->cpuid_xlevel2 > 0) { | |
b3baa152 BW |
1920 | cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); |
1921 | ||
1922 | for (i = 0xC0000000; i <= limit; i++) { | |
f8bb0565 IM |
1923 | if (cpuid_i == KVM_MAX_CPUID_ENTRIES) { |
1924 | fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit); | |
1925 | abort(); | |
1926 | } | |
b3baa152 BW |
1927 | c = &cpuid_data.entries[cpuid_i++]; |
1928 | ||
1929 | c->function = i; | |
1930 | c->flags = 0; | |
1931 | cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx); | |
1932 | } | |
1933 | } | |
1934 | ||
05330448 AL |
1935 | cpuid_data.cpuid.nent = cpuid_i; |
1936 | ||
e7701825 | 1937 | if (((env->cpuid_version >> 8)&0xF) >= 6 |
0514ef2f | 1938 | && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) == |
fc7a504c | 1939 | (CPUID_MCE | CPUID_MCA) |
a60f24b5 | 1940 | && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) { |
5120901a | 1941 | uint64_t mcg_cap, unsupported_caps; |
e7701825 | 1942 | int banks; |
32a42024 | 1943 | int ret; |
e7701825 | 1944 | |
a60f24b5 | 1945 | ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks); |
75d49497 JK |
1946 | if (ret < 0) { |
1947 | fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret)); | |
1948 | return ret; | |
e7701825 | 1949 | } |
75d49497 | 1950 | |
2590f15b | 1951 | if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) { |
49b69cbf | 1952 | error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)", |
2590f15b | 1953 | (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks); |
49b69cbf | 1954 | return -ENOTSUP; |
75d49497 | 1955 | } |
49b69cbf | 1956 | |
5120901a EH |
1957 | unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK); |
1958 | if (unsupported_caps) { | |
87f8b626 AR |
1959 | if (unsupported_caps & MCG_LMCE_P) { |
1960 | error_report("kvm: LMCE not supported"); | |
1961 | return -ENOTSUP; | |
1962 | } | |
3dc6f869 AF |
1963 | warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64, |
1964 | unsupported_caps); | |
5120901a EH |
1965 | } |
1966 | ||
2590f15b EH |
1967 | env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK; |
1968 | ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap); | |
75d49497 JK |
1969 | if (ret < 0) { |
1970 | fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret)); | |
1971 | return ret; | |
1972 | } | |
e7701825 | 1973 | } |
e7701825 | 1974 | |
2a693142 | 1975 | cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env); |
b8cc45d6 | 1976 | |
df67696e LJ |
1977 | c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0); |
1978 | if (c) { | |
1979 | has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) || | |
1980 | !!(c->ecx & CPUID_EXT_SMX); | |
1981 | } | |
1982 | ||
a0483541 SC |
1983 | c = cpuid_find_entry(&cpuid_data.cpuid, 7, 0); |
1984 | if (c && (c->ebx & CPUID_7_0_EBX_SGX)) { | |
1985 | has_msr_feature_control = true; | |
1986 | } | |
1987 | ||
87f8b626 AR |
1988 | if (env->mcg_cap & MCG_LMCE_P) { |
1989 | has_msr_mcg_ext_ctl = has_msr_feature_control = true; | |
1990 | } | |
1991 | ||
d99569d9 EH |
1992 | if (!env->user_tsc_khz) { |
1993 | if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) && | |
1994 | invtsc_mig_blocker == NULL) { | |
d99569d9 EH |
1995 | error_setg(&invtsc_mig_blocker, |
1996 | "State blocked by non-migratable CPU device" | |
1997 | " (invtsc flag)"); | |
fe44dc91 | 1998 | r = migrate_add_blocker(invtsc_mig_blocker, &local_err); |
436c831a | 1999 | if (r < 0) { |
fe44dc91 | 2000 | error_report_err(local_err); |
79a197ab | 2001 | return r; |
fe44dc91 | 2002 | } |
d99569d9 | 2003 | } |
68bfd0ad MT |
2004 | } |
2005 | ||
9954a158 PDJ |
2006 | if (cpu->vmware_cpuid_freq |
2007 | /* Guests depend on 0x40000000 to detect this feature, so only expose | |
2008 | * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */ | |
2009 | && cpu->expose_kvm | |
2010 | && kvm_base == KVM_CPUID_SIGNATURE | |
2011 | /* TSC clock must be stable and known for this feature. */ | |
4bb95b82 | 2012 | && tsc_is_stable_and_known(env)) { |
9954a158 PDJ |
2013 | |
2014 | c = &cpuid_data.entries[cpuid_i++]; | |
2015 | c->function = KVM_CPUID_SIGNATURE | 0x10; | |
2016 | c->eax = env->tsc_khz; | |
73b994f6 | 2017 | c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */ |
9954a158 PDJ |
2018 | c->ecx = c->edx = 0; |
2019 | ||
2020 | c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0); | |
2021 | c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10); | |
2022 | } | |
2023 | ||
2024 | cpuid_data.cpuid.nent = cpuid_i; | |
2025 | ||
2026 | cpuid_data.cpuid.padding = 0; | |
2027 | r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data); | |
2028 | if (r) { | |
2029 | goto fail; | |
2030 | } | |
e56dd3c7 | 2031 | kvm_init_xsave(env); |
ebbfef2f LA |
2032 | |
2033 | max_nested_state_len = kvm_max_nested_state_length(); | |
2034 | if (max_nested_state_len > 0) { | |
2035 | assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data)); | |
ebbfef2f | 2036 | |
b16c0e20 | 2037 | if (cpu_has_vmx(env) || cpu_has_svm(env)) { |
1e44f3ab | 2038 | struct kvm_vmx_nested_state_hdr *vmx_hdr; |
ebbfef2f | 2039 | |
1e44f3ab PB |
2040 | env->nested_state = g_malloc0(max_nested_state_len); |
2041 | env->nested_state->size = max_nested_state_len; | |
1e44f3ab | 2042 | |
b16c0e20 | 2043 | if (cpu_has_vmx(env)) { |
2654ace1 TL |
2044 | env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX; |
2045 | vmx_hdr = &env->nested_state->hdr.vmx; | |
2046 | vmx_hdr->vmxon_pa = -1ull; | |
2047 | vmx_hdr->vmcs12_pa = -1ull; | |
2048 | } else { | |
2049 | env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM; | |
b16c0e20 | 2050 | } |
ebbfef2f LA |
2051 | } |
2052 | } | |
2053 | ||
d71b62a1 | 2054 | cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE); |
fabacc0f | 2055 | |
273c515c PB |
2056 | if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) { |
2057 | has_msr_tsc_aux = false; | |
2058 | } | |
d1ae67f6 | 2059 | |
420ae1fc PB |
2060 | kvm_init_msrs(cpu); |
2061 | ||
e7429073 | 2062 | return 0; |
fe44dc91 AA |
2063 | |
2064 | fail: | |
2065 | migrate_del_blocker(invtsc_mig_blocker); | |
6b2341ee | 2066 | |
fe44dc91 | 2067 | return r; |
05330448 AL |
2068 | } |
2069 | ||
b1115c99 LA |
2070 | int kvm_arch_destroy_vcpu(CPUState *cs) |
2071 | { | |
2072 | X86CPU *cpu = X86_CPU(cs); | |
ebbfef2f | 2073 | CPUX86State *env = &cpu->env; |
b1115c99 LA |
2074 | |
2075 | if (cpu->kvm_msr_buf) { | |
2076 | g_free(cpu->kvm_msr_buf); | |
2077 | cpu->kvm_msr_buf = NULL; | |
2078 | } | |
2079 | ||
ebbfef2f LA |
2080 | if (env->nested_state) { |
2081 | g_free(env->nested_state); | |
2082 | env->nested_state = NULL; | |
2083 | } | |
2084 | ||
2a693142 PN |
2085 | qemu_del_vm_change_state_handler(cpu->vmsentry); |
2086 | ||
b1115c99 LA |
2087 | return 0; |
2088 | } | |
2089 | ||
50a2c6e5 | 2090 | void kvm_arch_reset_vcpu(X86CPU *cpu) |
caa5af0f | 2091 | { |
20d695a9 | 2092 | CPUX86State *env = &cpu->env; |
dd673288 | 2093 | |
1a5e9d2f | 2094 | env->xcr0 = 1; |
ddced198 | 2095 | if (kvm_irqchip_in_kernel()) { |
dd673288 | 2096 | env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : |
ddced198 MT |
2097 | KVM_MP_STATE_UNINITIALIZED; |
2098 | } else { | |
2099 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
2100 | } | |
689141dd | 2101 | |
2d384d7c | 2102 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { |
689141dd RK |
2103 | int i; |
2104 | for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) { | |
2105 | env->msr_hv_synic_sint[i] = HV_SINT_MASKED; | |
2106 | } | |
606c34bf RK |
2107 | |
2108 | hyperv_x86_synic_reset(cpu); | |
689141dd | 2109 | } |
d645e132 MT |
2110 | /* enabled by default */ |
2111 | env->poll_control_msr = 1; | |
b2f73a07 PB |
2112 | |
2113 | sev_es_set_reset_vector(CPU(cpu)); | |
caa5af0f JK |
2114 | } |
2115 | ||
e0723c45 PB |
2116 | void kvm_arch_do_init_vcpu(X86CPU *cpu) |
2117 | { | |
2118 | CPUX86State *env = &cpu->env; | |
2119 | ||
2120 | /* APs get directly into wait-for-SIPI state. */ | |
2121 | if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) { | |
2122 | env->mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2123 | } | |
2124 | } | |
2125 | ||
f57bceb6 RH |
2126 | static int kvm_get_supported_feature_msrs(KVMState *s) |
2127 | { | |
2128 | int ret = 0; | |
2129 | ||
2130 | if (kvm_feature_msrs != NULL) { | |
2131 | return 0; | |
2132 | } | |
2133 | ||
2134 | if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) { | |
2135 | return 0; | |
2136 | } | |
2137 | ||
2138 | struct kvm_msr_list msr_list; | |
2139 | ||
2140 | msr_list.nmsrs = 0; | |
2141 | ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list); | |
2142 | if (ret < 0 && ret != -E2BIG) { | |
2143 | error_report("Fetch KVM feature MSR list failed: %s", | |
2144 | strerror(-ret)); | |
2145 | return ret; | |
2146 | } | |
2147 | ||
2148 | assert(msr_list.nmsrs > 0); | |
2149 | kvm_feature_msrs = (struct kvm_msr_list *) \ | |
2150 | g_malloc0(sizeof(msr_list) + | |
2151 | msr_list.nmsrs * sizeof(msr_list.indices[0])); | |
2152 | ||
2153 | kvm_feature_msrs->nmsrs = msr_list.nmsrs; | |
2154 | ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs); | |
2155 | ||
2156 | if (ret < 0) { | |
2157 | error_report("Fetch KVM feature MSR list failed: %s", | |
2158 | strerror(-ret)); | |
2159 | g_free(kvm_feature_msrs); | |
2160 | kvm_feature_msrs = NULL; | |
2161 | return ret; | |
2162 | } | |
2163 | ||
2164 | return 0; | |
2165 | } | |
2166 | ||
c3a3a7d3 | 2167 | static int kvm_get_supported_msrs(KVMState *s) |
05330448 | 2168 | { |
c3a3a7d3 | 2169 | int ret = 0; |
de428cea | 2170 | struct kvm_msr_list msr_list, *kvm_msr_list; |
05330448 | 2171 | |
de428cea LQ |
2172 | /* |
2173 | * Obtain MSR list from KVM. These are the MSRs that we must | |
2174 | * save/restore. | |
2175 | */ | |
2176 | msr_list.nmsrs = 0; | |
2177 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list); | |
2178 | if (ret < 0 && ret != -E2BIG) { | |
2179 | return ret; | |
2180 | } | |
2181 | /* | |
2182 | * Old kernel modules had a bug and could write beyond the provided | |
2183 | * memory. Allocate at least a safe amount of 1K. | |
2184 | */ | |
2185 | kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) + | |
2186 | msr_list.nmsrs * | |
2187 | sizeof(msr_list.indices[0]))); | |
05330448 | 2188 | |
de428cea LQ |
2189 | kvm_msr_list->nmsrs = msr_list.nmsrs; |
2190 | ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list); | |
2191 | if (ret >= 0) { | |
2192 | int i; | |
05330448 | 2193 | |
de428cea LQ |
2194 | for (i = 0; i < kvm_msr_list->nmsrs; i++) { |
2195 | switch (kvm_msr_list->indices[i]) { | |
2196 | case MSR_STAR: | |
2197 | has_msr_star = true; | |
2198 | break; | |
2199 | case MSR_VM_HSAVE_PA: | |
2200 | has_msr_hsave_pa = true; | |
2201 | break; | |
2202 | case MSR_TSC_AUX: | |
2203 | has_msr_tsc_aux = true; | |
2204 | break; | |
2205 | case MSR_TSC_ADJUST: | |
2206 | has_msr_tsc_adjust = true; | |
2207 | break; | |
2208 | case MSR_IA32_TSCDEADLINE: | |
2209 | has_msr_tsc_deadline = true; | |
2210 | break; | |
2211 | case MSR_IA32_SMBASE: | |
2212 | has_msr_smbase = true; | |
2213 | break; | |
2214 | case MSR_SMI_COUNT: | |
2215 | has_msr_smi_count = true; | |
2216 | break; | |
2217 | case MSR_IA32_MISC_ENABLE: | |
2218 | has_msr_misc_enable = true; | |
2219 | break; | |
2220 | case MSR_IA32_BNDCFGS: | |
2221 | has_msr_bndcfgs = true; | |
2222 | break; | |
2223 | case MSR_IA32_XSS: | |
2224 | has_msr_xss = true; | |
2225 | break; | |
65087997 TX |
2226 | case MSR_IA32_UMWAIT_CONTROL: |
2227 | has_msr_umwait = true; | |
2228 | break; | |
de428cea LQ |
2229 | case HV_X64_MSR_CRASH_CTL: |
2230 | has_msr_hv_crash = true; | |
2231 | break; | |
2232 | case HV_X64_MSR_RESET: | |
2233 | has_msr_hv_reset = true; | |
2234 | break; | |
2235 | case HV_X64_MSR_VP_INDEX: | |
2236 | has_msr_hv_vpindex = true; | |
2237 | break; | |
2238 | case HV_X64_MSR_VP_RUNTIME: | |
2239 | has_msr_hv_runtime = true; | |
2240 | break; | |
2241 | case HV_X64_MSR_SCONTROL: | |
2242 | has_msr_hv_synic = true; | |
2243 | break; | |
2244 | case HV_X64_MSR_STIMER0_CONFIG: | |
2245 | has_msr_hv_stimer = true; | |
2246 | break; | |
2247 | case HV_X64_MSR_TSC_FREQUENCY: | |
2248 | has_msr_hv_frequencies = true; | |
2249 | break; | |
2250 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: | |
2251 | has_msr_hv_reenlightenment = true; | |
2252 | break; | |
2253 | case MSR_IA32_SPEC_CTRL: | |
2254 | has_msr_spec_ctrl = true; | |
2255 | break; | |
cabf9862 ML |
2256 | case MSR_AMD64_TSC_RATIO: |
2257 | has_tsc_scale_msr = true; | |
2258 | break; | |
2a9758c5 PB |
2259 | case MSR_IA32_TSX_CTRL: |
2260 | has_msr_tsx_ctrl = true; | |
2261 | break; | |
de428cea LQ |
2262 | case MSR_VIRT_SSBD: |
2263 | has_msr_virt_ssbd = true; | |
2264 | break; | |
2265 | case MSR_IA32_ARCH_CAPABILITIES: | |
2266 | has_msr_arch_capabs = true; | |
2267 | break; | |
2268 | case MSR_IA32_CORE_CAPABILITY: | |
2269 | has_msr_core_capabs = true; | |
2270 | break; | |
ea39f9b6 LX |
2271 | case MSR_IA32_PERF_CAPABILITIES: |
2272 | has_msr_perf_capabs = true; | |
2273 | break; | |
20a78b02 PB |
2274 | case MSR_IA32_VMX_VMFUNC: |
2275 | has_msr_vmx_vmfunc = true; | |
2276 | break; | |
67025148 PB |
2277 | case MSR_IA32_UCODE_REV: |
2278 | has_msr_ucode_rev = true; | |
2279 | break; | |
4a910e1f VK |
2280 | case MSR_IA32_VMX_PROCBASED_CTLS2: |
2281 | has_msr_vmx_procbased_ctls2 = true; | |
2282 | break; | |
6aa4228b CQ |
2283 | case MSR_IA32_PKRS: |
2284 | has_msr_pkrs = true; | |
2285 | break; | |
05330448 AL |
2286 | } |
2287 | } | |
05330448 AL |
2288 | } |
2289 | ||
de428cea LQ |
2290 | g_free(kvm_msr_list); |
2291 | ||
c3a3a7d3 | 2292 | return ret; |
05330448 AL |
2293 | } |
2294 | ||
6410848b PB |
2295 | static Notifier smram_machine_done; |
2296 | static KVMMemoryListener smram_listener; | |
2297 | static AddressSpace smram_address_space; | |
2298 | static MemoryRegion smram_as_root; | |
2299 | static MemoryRegion smram_as_mem; | |
2300 | ||
2301 | static void register_smram_listener(Notifier *n, void *unused) | |
2302 | { | |
2303 | MemoryRegion *smram = | |
2304 | (MemoryRegion *) object_resolve_path("/machine/smram", NULL); | |
2305 | ||
2306 | /* Outer container... */ | |
2307 | memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull); | |
2308 | memory_region_set_enabled(&smram_as_root, true); | |
2309 | ||
2310 | /* ... with two regions inside: normal system memory with low | |
2311 | * priority, and... | |
2312 | */ | |
2313 | memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram", | |
2314 | get_system_memory(), 0, ~0ull); | |
2315 | memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0); | |
2316 | memory_region_set_enabled(&smram_as_mem, true); | |
2317 | ||
2318 | if (smram) { | |
2319 | /* ... SMRAM with higher priority */ | |
2320 | memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10); | |
2321 | memory_region_set_enabled(smram, true); | |
2322 | } | |
2323 | ||
2324 | address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM"); | |
2325 | kvm_memory_listener_register(kvm_state, &smram_listener, | |
142518bd | 2326 | &smram_address_space, 1, "kvm-smram"); |
6410848b PB |
2327 | } |
2328 | ||
b16565b3 | 2329 | int kvm_arch_init(MachineState *ms, KVMState *s) |
20420430 | 2330 | { |
11076198 | 2331 | uint64_t identity_base = 0xfffbc000; |
39d6960a | 2332 | uint64_t shadow_mem; |
20420430 | 2333 | int ret; |
25d2e361 | 2334 | struct utsname utsname; |
ec78e2cd DG |
2335 | Error *local_err = NULL; |
2336 | ||
2337 | /* | |
2338 | * Initialize SEV context, if required | |
2339 | * | |
2340 | * If no memory encryption is requested (ms->cgs == NULL) this is | |
2341 | * a no-op. | |
2342 | * | |
2343 | * It's also a no-op if a non-SEV confidential guest support | |
2344 | * mechanism is selected. SEV is the only mechanism available to | |
2345 | * select on x86 at present, so this doesn't arise, but if new | |
2346 | * mechanisms are supported in future (e.g. TDX), they'll need | |
2347 | * their own initialization either here or elsewhere. | |
2348 | */ | |
2349 | ret = sev_kvm_init(ms->cgs, &local_err); | |
2350 | if (ret < 0) { | |
2351 | error_report_err(local_err); | |
2352 | return ret; | |
2353 | } | |
20420430 | 2354 | |
1a6dff5f EH |
2355 | if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) { |
2356 | error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM"); | |
2357 | return -ENOTSUP; | |
2358 | } | |
2359 | ||
28143b40 | 2360 | has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE); |
28143b40 | 2361 | has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS); |
28143b40 | 2362 | has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2); |
8f515d38 | 2363 | has_sregs2 = kvm_check_extension(s, KVM_CAP_SREGS2) > 0; |
28143b40 | 2364 | |
e9688fab RK |
2365 | hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX); |
2366 | ||
fd13f23b LA |
2367 | has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD); |
2368 | if (has_exception_payload) { | |
2369 | ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true); | |
2370 | if (ret < 0) { | |
2371 | error_report("kvm: Failed to enable exception payload cap: %s", | |
2372 | strerror(-ret)); | |
2373 | return ret; | |
2374 | } | |
2375 | } | |
2376 | ||
c3a3a7d3 | 2377 | ret = kvm_get_supported_msrs(s); |
20420430 | 2378 | if (ret < 0) { |
20420430 SY |
2379 | return ret; |
2380 | } | |
25d2e361 | 2381 | |
f57bceb6 RH |
2382 | kvm_get_supported_feature_msrs(s); |
2383 | ||
25d2e361 MT |
2384 | uname(&utsname); |
2385 | lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0; | |
2386 | ||
4c5b10b7 | 2387 | /* |
11076198 JK |
2388 | * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly. |
2389 | * In order to use vm86 mode, an EPT identity map and a TSS are needed. | |
2390 | * Since these must be part of guest physical memory, we need to allocate | |
2391 | * them, both by setting their start addresses in the kernel and by | |
2392 | * creating a corresponding e820 entry. We need 4 pages before the BIOS. | |
2393 | * | |
2394 | * Older KVM versions may not support setting the identity map base. In | |
2395 | * that case we need to stick with the default, i.e. a 256K maximum BIOS | |
2396 | * size. | |
4c5b10b7 | 2397 | */ |
11076198 JK |
2398 | if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) { |
2399 | /* Allows up to 16M BIOSes. */ | |
2400 | identity_base = 0xfeffc000; | |
2401 | ||
2402 | ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base); | |
2403 | if (ret < 0) { | |
2404 | return ret; | |
2405 | } | |
4c5b10b7 | 2406 | } |
e56ff191 | 2407 | |
11076198 JK |
2408 | /* Set TSS base one page after EPT identity map. */ |
2409 | ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000); | |
20420430 SY |
2410 | if (ret < 0) { |
2411 | return ret; | |
2412 | } | |
2413 | ||
11076198 JK |
2414 | /* Tell fw_cfg to notify the BIOS to reserve the range. */ |
2415 | ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED); | |
20420430 | 2416 | if (ret < 0) { |
11076198 | 2417 | fprintf(stderr, "e820_add_entry() table is full\n"); |
20420430 SY |
2418 | return ret; |
2419 | } | |
2420 | ||
23b0898e | 2421 | shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort); |
36ad0e94 MA |
2422 | if (shadow_mem != -1) { |
2423 | shadow_mem /= 4096; | |
2424 | ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem); | |
2425 | if (ret < 0) { | |
2426 | return ret; | |
39d6960a JK |
2427 | } |
2428 | } | |
6410848b | 2429 | |
d870cfde | 2430 | if (kvm_check_extension(s, KVM_CAP_X86_SMM) && |
8f54bbd0 | 2431 | object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) && |
ed9e923c | 2432 | x86_machine_is_smm_enabled(X86_MACHINE(ms))) { |
6410848b PB |
2433 | smram_machine_done.notify = register_smram_listener; |
2434 | qemu_add_machine_init_done_notifier(&smram_machine_done); | |
2435 | } | |
6f131f13 MT |
2436 | |
2437 | if (enable_cpu_pm) { | |
2438 | int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS); | |
2439 | int ret; | |
2440 | ||
2441 | /* Work around for kernel header with a typo. TODO: fix header and drop. */ | |
2442 | #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT) | |
2443 | #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL | |
2444 | #endif | |
2445 | if (disable_exits) { | |
2446 | disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT | | |
2447 | KVM_X86_DISABLE_EXITS_HLT | | |
d38d201f WL |
2448 | KVM_X86_DISABLE_EXITS_PAUSE | |
2449 | KVM_X86_DISABLE_EXITS_CSTATE); | |
6f131f13 MT |
2450 | } |
2451 | ||
2452 | ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0, | |
2453 | disable_exits); | |
2454 | if (ret < 0) { | |
2455 | error_report("kvm: guest stopping CPU not supported: %s", | |
2456 | strerror(-ret)); | |
2457 | } | |
2458 | } | |
2459 | ||
035d1ef2 CQ |
2460 | if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) { |
2461 | X86MachineState *x86ms = X86_MACHINE(ms); | |
2462 | ||
2463 | if (x86ms->bus_lock_ratelimit > 0) { | |
2464 | ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT); | |
2465 | if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) { | |
2466 | error_report("kvm: bus lock detection unsupported"); | |
2467 | return -ENOTSUP; | |
2468 | } | |
2469 | ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0, | |
2470 | KVM_BUS_LOCK_DETECTION_EXIT); | |
2471 | if (ret < 0) { | |
2472 | error_report("kvm: Failed to enable bus lock detection cap: %s", | |
2473 | strerror(-ret)); | |
2474 | return ret; | |
2475 | } | |
2476 | ratelimit_init(&bus_lock_ratelimit_ctrl); | |
2477 | ratelimit_set_speed(&bus_lock_ratelimit_ctrl, | |
2478 | x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME); | |
2479 | } | |
2480 | } | |
2481 | ||
11076198 | 2482 | return 0; |
05330448 | 2483 | } |
b9bec74b | 2484 | |
05330448 AL |
2485 | static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs) |
2486 | { | |
2487 | lhs->selector = rhs->selector; | |
2488 | lhs->base = rhs->base; | |
2489 | lhs->limit = rhs->limit; | |
2490 | lhs->type = 3; | |
2491 | lhs->present = 1; | |
2492 | lhs->dpl = 3; | |
2493 | lhs->db = 0; | |
2494 | lhs->s = 1; | |
2495 | lhs->l = 0; | |
2496 | lhs->g = 0; | |
2497 | lhs->avl = 0; | |
2498 | lhs->unusable = 0; | |
2499 | } | |
2500 | ||
2501 | static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs) | |
2502 | { | |
2503 | unsigned flags = rhs->flags; | |
2504 | lhs->selector = rhs->selector; | |
2505 | lhs->base = rhs->base; | |
2506 | lhs->limit = rhs->limit; | |
2507 | lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; | |
2508 | lhs->present = (flags & DESC_P_MASK) != 0; | |
acaa7550 | 2509 | lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3; |
05330448 AL |
2510 | lhs->db = (flags >> DESC_B_SHIFT) & 1; |
2511 | lhs->s = (flags & DESC_S_MASK) != 0; | |
2512 | lhs->l = (flags >> DESC_L_SHIFT) & 1; | |
2513 | lhs->g = (flags & DESC_G_MASK) != 0; | |
2514 | lhs->avl = (flags & DESC_AVL_MASK) != 0; | |
4cae9c97 | 2515 | lhs->unusable = !lhs->present; |
7e680753 | 2516 | lhs->padding = 0; |
05330448 AL |
2517 | } |
2518 | ||
2519 | static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs) | |
2520 | { | |
2521 | lhs->selector = rhs->selector; | |
2522 | lhs->base = rhs->base; | |
2523 | lhs->limit = rhs->limit; | |
d45fc087 RP |
2524 | lhs->flags = (rhs->type << DESC_TYPE_SHIFT) | |
2525 | ((rhs->present && !rhs->unusable) * DESC_P_MASK) | | |
2526 | (rhs->dpl << DESC_DPL_SHIFT) | | |
2527 | (rhs->db << DESC_B_SHIFT) | | |
2528 | (rhs->s * DESC_S_MASK) | | |
2529 | (rhs->l << DESC_L_SHIFT) | | |
2530 | (rhs->g * DESC_G_MASK) | | |
2531 | (rhs->avl * DESC_AVL_MASK); | |
05330448 AL |
2532 | } |
2533 | ||
2534 | static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set) | |
2535 | { | |
b9bec74b | 2536 | if (set) { |
05330448 | 2537 | *kvm_reg = *qemu_reg; |
b9bec74b | 2538 | } else { |
05330448 | 2539 | *qemu_reg = *kvm_reg; |
b9bec74b | 2540 | } |
05330448 AL |
2541 | } |
2542 | ||
1bc22652 | 2543 | static int kvm_getput_regs(X86CPU *cpu, int set) |
05330448 | 2544 | { |
1bc22652 | 2545 | CPUX86State *env = &cpu->env; |
05330448 AL |
2546 | struct kvm_regs regs; |
2547 | int ret = 0; | |
2548 | ||
2549 | if (!set) { | |
1bc22652 | 2550 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, ®s); |
b9bec74b | 2551 | if (ret < 0) { |
05330448 | 2552 | return ret; |
b9bec74b | 2553 | } |
05330448 AL |
2554 | } |
2555 | ||
2556 | kvm_getput_reg(®s.rax, &env->regs[R_EAX], set); | |
2557 | kvm_getput_reg(®s.rbx, &env->regs[R_EBX], set); | |
2558 | kvm_getput_reg(®s.rcx, &env->regs[R_ECX], set); | |
2559 | kvm_getput_reg(®s.rdx, &env->regs[R_EDX], set); | |
2560 | kvm_getput_reg(®s.rsi, &env->regs[R_ESI], set); | |
2561 | kvm_getput_reg(®s.rdi, &env->regs[R_EDI], set); | |
2562 | kvm_getput_reg(®s.rsp, &env->regs[R_ESP], set); | |
2563 | kvm_getput_reg(®s.rbp, &env->regs[R_EBP], set); | |
2564 | #ifdef TARGET_X86_64 | |
2565 | kvm_getput_reg(®s.r8, &env->regs[8], set); | |
2566 | kvm_getput_reg(®s.r9, &env->regs[9], set); | |
2567 | kvm_getput_reg(®s.r10, &env->regs[10], set); | |
2568 | kvm_getput_reg(®s.r11, &env->regs[11], set); | |
2569 | kvm_getput_reg(®s.r12, &env->regs[12], set); | |
2570 | kvm_getput_reg(®s.r13, &env->regs[13], set); | |
2571 | kvm_getput_reg(®s.r14, &env->regs[14], set); | |
2572 | kvm_getput_reg(®s.r15, &env->regs[15], set); | |
2573 | #endif | |
2574 | ||
2575 | kvm_getput_reg(®s.rflags, &env->eflags, set); | |
2576 | kvm_getput_reg(®s.rip, &env->eip, set); | |
2577 | ||
b9bec74b | 2578 | if (set) { |
1bc22652 | 2579 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, ®s); |
b9bec74b | 2580 | } |
05330448 AL |
2581 | |
2582 | return ret; | |
2583 | } | |
2584 | ||
1bc22652 | 2585 | static int kvm_put_fpu(X86CPU *cpu) |
05330448 | 2586 | { |
1bc22652 | 2587 | CPUX86State *env = &cpu->env; |
05330448 AL |
2588 | struct kvm_fpu fpu; |
2589 | int i; | |
2590 | ||
2591 | memset(&fpu, 0, sizeof fpu); | |
2592 | fpu.fsw = env->fpus & ~(7 << 11); | |
2593 | fpu.fsw |= (env->fpstt & 7) << 11; | |
2594 | fpu.fcw = env->fpuc; | |
42cc8fa6 JK |
2595 | fpu.last_opcode = env->fpop; |
2596 | fpu.last_ip = env->fpip; | |
2597 | fpu.last_dp = env->fpdp; | |
b9bec74b JK |
2598 | for (i = 0; i < 8; ++i) { |
2599 | fpu.ftwx |= (!env->fptags[i]) << i; | |
2600 | } | |
05330448 | 2601 | memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs); |
bee81887 | 2602 | for (i = 0; i < CPU_NB_REGS; i++) { |
19cbd87c EH |
2603 | stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0)); |
2604 | stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1)); | |
bee81887 | 2605 | } |
05330448 AL |
2606 | fpu.mxcsr = env->mxcsr; |
2607 | ||
1bc22652 | 2608 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu); |
05330448 AL |
2609 | } |
2610 | ||
1bc22652 | 2611 | static int kvm_put_xsave(X86CPU *cpu) |
f1665b21 | 2612 | { |
1bc22652 | 2613 | CPUX86State *env = &cpu->env; |
c0198c5f | 2614 | void *xsave = env->xsave_buf; |
f1665b21 | 2615 | |
28143b40 | 2616 | if (!has_xsave) { |
1bc22652 | 2617 | return kvm_put_fpu(cpu); |
b9bec74b | 2618 | } |
c0198c5f | 2619 | x86_cpu_xsave_all_areas(cpu, xsave, env->xsave_buf_len); |
f1665b21 | 2620 | |
9be38598 | 2621 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave); |
f1665b21 SY |
2622 | } |
2623 | ||
1bc22652 | 2624 | static int kvm_put_xcrs(X86CPU *cpu) |
f1665b21 | 2625 | { |
1bc22652 | 2626 | CPUX86State *env = &cpu->env; |
bdfc8480 | 2627 | struct kvm_xcrs xcrs = {}; |
f1665b21 | 2628 | |
28143b40 | 2629 | if (!has_xcrs) { |
f1665b21 | 2630 | return 0; |
b9bec74b | 2631 | } |
f1665b21 SY |
2632 | |
2633 | xcrs.nr_xcrs = 1; | |
2634 | xcrs.flags = 0; | |
2635 | xcrs.xcrs[0].xcr = 0; | |
2636 | xcrs.xcrs[0].value = env->xcr0; | |
1bc22652 | 2637 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs); |
f1665b21 SY |
2638 | } |
2639 | ||
1bc22652 | 2640 | static int kvm_put_sregs(X86CPU *cpu) |
05330448 | 2641 | { |
1bc22652 | 2642 | CPUX86State *env = &cpu->env; |
05330448 AL |
2643 | struct kvm_sregs sregs; |
2644 | ||
1520f8bb PB |
2645 | /* |
2646 | * The interrupt_bitmap is ignored because KVM_SET_SREGS is | |
2647 | * always followed by KVM_SET_VCPU_EVENTS. | |
2648 | */ | |
0e607a80 | 2649 | memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap)); |
05330448 AL |
2650 | |
2651 | if ((env->eflags & VM_MASK)) { | |
b9bec74b JK |
2652 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); |
2653 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
2654 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
2655 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
2656 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
2657 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 | 2658 | } else { |
b9bec74b JK |
2659 | set_seg(&sregs.cs, &env->segs[R_CS]); |
2660 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
2661 | set_seg(&sregs.es, &env->segs[R_ES]); | |
2662 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
2663 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
2664 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
05330448 AL |
2665 | } |
2666 | ||
2667 | set_seg(&sregs.tr, &env->tr); | |
2668 | set_seg(&sregs.ldt, &env->ldt); | |
2669 | ||
2670 | sregs.idt.limit = env->idt.limit; | |
2671 | sregs.idt.base = env->idt.base; | |
7e680753 | 2672 | memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); |
05330448 AL |
2673 | sregs.gdt.limit = env->gdt.limit; |
2674 | sregs.gdt.base = env->gdt.base; | |
7e680753 | 2675 | memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); |
05330448 AL |
2676 | |
2677 | sregs.cr0 = env->cr[0]; | |
2678 | sregs.cr2 = env->cr[2]; | |
2679 | sregs.cr3 = env->cr[3]; | |
2680 | sregs.cr4 = env->cr[4]; | |
2681 | ||
02e51483 CF |
2682 | sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); |
2683 | sregs.apic_base = cpu_get_apic_base(cpu->apic_state); | |
05330448 AL |
2684 | |
2685 | sregs.efer = env->efer; | |
2686 | ||
1bc22652 | 2687 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); |
05330448 AL |
2688 | } |
2689 | ||
8f515d38 ML |
2690 | static int kvm_put_sregs2(X86CPU *cpu) |
2691 | { | |
2692 | CPUX86State *env = &cpu->env; | |
2693 | struct kvm_sregs2 sregs; | |
2694 | int i; | |
2695 | ||
2696 | sregs.flags = 0; | |
2697 | ||
2698 | if ((env->eflags & VM_MASK)) { | |
2699 | set_v8086_seg(&sregs.cs, &env->segs[R_CS]); | |
2700 | set_v8086_seg(&sregs.ds, &env->segs[R_DS]); | |
2701 | set_v8086_seg(&sregs.es, &env->segs[R_ES]); | |
2702 | set_v8086_seg(&sregs.fs, &env->segs[R_FS]); | |
2703 | set_v8086_seg(&sregs.gs, &env->segs[R_GS]); | |
2704 | set_v8086_seg(&sregs.ss, &env->segs[R_SS]); | |
2705 | } else { | |
2706 | set_seg(&sregs.cs, &env->segs[R_CS]); | |
2707 | set_seg(&sregs.ds, &env->segs[R_DS]); | |
2708 | set_seg(&sregs.es, &env->segs[R_ES]); | |
2709 | set_seg(&sregs.fs, &env->segs[R_FS]); | |
2710 | set_seg(&sregs.gs, &env->segs[R_GS]); | |
2711 | set_seg(&sregs.ss, &env->segs[R_SS]); | |
2712 | } | |
2713 | ||
2714 | set_seg(&sregs.tr, &env->tr); | |
2715 | set_seg(&sregs.ldt, &env->ldt); | |
2716 | ||
2717 | sregs.idt.limit = env->idt.limit; | |
2718 | sregs.idt.base = env->idt.base; | |
2719 | memset(sregs.idt.padding, 0, sizeof sregs.idt.padding); | |
2720 | sregs.gdt.limit = env->gdt.limit; | |
2721 | sregs.gdt.base = env->gdt.base; | |
2722 | memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding); | |
2723 | ||
2724 | sregs.cr0 = env->cr[0]; | |
2725 | sregs.cr2 = env->cr[2]; | |
2726 | sregs.cr3 = env->cr[3]; | |
2727 | sregs.cr4 = env->cr[4]; | |
2728 | ||
2729 | sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state); | |
2730 | sregs.apic_base = cpu_get_apic_base(cpu->apic_state); | |
2731 | ||
2732 | sregs.efer = env->efer; | |
2733 | ||
2734 | if (env->pdptrs_valid) { | |
2735 | for (i = 0; i < 4; i++) { | |
2736 | sregs.pdptrs[i] = env->pdptrs[i]; | |
2737 | } | |
2738 | sregs.flags |= KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
2739 | } | |
2740 | ||
2741 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS2, &sregs); | |
2742 | } | |
2743 | ||
2744 | ||
d71b62a1 EH |
2745 | static void kvm_msr_buf_reset(X86CPU *cpu) |
2746 | { | |
2747 | memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE); | |
2748 | } | |
2749 | ||
9c600a84 EH |
2750 | static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value) |
2751 | { | |
2752 | struct kvm_msrs *msrs = cpu->kvm_msr_buf; | |
2753 | void *limit = ((void *)msrs) + MSR_BUF_SIZE; | |
2754 | struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs]; | |
2755 | ||
2756 | assert((void *)(entry + 1) <= limit); | |
2757 | ||
1abc2cae EH |
2758 | entry->index = index; |
2759 | entry->reserved = 0; | |
2760 | entry->data = value; | |
9c600a84 EH |
2761 | msrs->nmsrs++; |
2762 | } | |
2763 | ||
73e1b8f2 PB |
2764 | static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value) |
2765 | { | |
2766 | kvm_msr_buf_reset(cpu); | |
2767 | kvm_msr_entry_add(cpu, index, value); | |
2768 | ||
2769 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); | |
2770 | } | |
2771 | ||
f8d9ccf8 DDAG |
2772 | void kvm_put_apicbase(X86CPU *cpu, uint64_t value) |
2773 | { | |
2774 | int ret; | |
2775 | ||
2776 | ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value); | |
2777 | assert(ret == 1); | |
2778 | } | |
2779 | ||
7477cd38 MT |
2780 | static int kvm_put_tscdeadline_msr(X86CPU *cpu) |
2781 | { | |
2782 | CPUX86State *env = &cpu->env; | |
48e1a45c | 2783 | int ret; |
7477cd38 MT |
2784 | |
2785 | if (!has_msr_tsc_deadline) { | |
2786 | return 0; | |
2787 | } | |
2788 | ||
73e1b8f2 | 2789 | ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline); |
48e1a45c PB |
2790 | if (ret < 0) { |
2791 | return ret; | |
2792 | } | |
2793 | ||
2794 | assert(ret == 1); | |
2795 | return 0; | |
7477cd38 MT |
2796 | } |
2797 | ||
6bdf863d JK |
2798 | /* |
2799 | * Provide a separate write service for the feature control MSR in order to | |
2800 | * kick the VCPU out of VMXON or even guest mode on reset. This has to be done | |
2801 | * before writing any other state because forcibly leaving nested mode | |
2802 | * invalidates the VCPU state. | |
2803 | */ | |
2804 | static int kvm_put_msr_feature_control(X86CPU *cpu) | |
2805 | { | |
48e1a45c PB |
2806 | int ret; |
2807 | ||
2808 | if (!has_msr_feature_control) { | |
2809 | return 0; | |
2810 | } | |
6bdf863d | 2811 | |
73e1b8f2 PB |
2812 | ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL, |
2813 | cpu->env.msr_ia32_feature_control); | |
48e1a45c PB |
2814 | if (ret < 0) { |
2815 | return ret; | |
2816 | } | |
2817 | ||
2818 | assert(ret == 1); | |
2819 | return 0; | |
6bdf863d JK |
2820 | } |
2821 | ||
20a78b02 PB |
2822 | static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features) |
2823 | { | |
2824 | uint32_t default1, can_be_one, can_be_zero; | |
2825 | uint32_t must_be_one; | |
2826 | ||
2827 | switch (index) { | |
2828 | case MSR_IA32_VMX_TRUE_PINBASED_CTLS: | |
2829 | default1 = 0x00000016; | |
2830 | break; | |
2831 | case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: | |
2832 | default1 = 0x0401e172; | |
2833 | break; | |
2834 | case MSR_IA32_VMX_TRUE_ENTRY_CTLS: | |
2835 | default1 = 0x000011ff; | |
2836 | break; | |
2837 | case MSR_IA32_VMX_TRUE_EXIT_CTLS: | |
2838 | default1 = 0x00036dff; | |
2839 | break; | |
2840 | case MSR_IA32_VMX_PROCBASED_CTLS2: | |
2841 | default1 = 0; | |
2842 | break; | |
2843 | default: | |
2844 | abort(); | |
2845 | } | |
2846 | ||
2847 | /* If a feature bit is set, the control can be either set or clear. | |
2848 | * Otherwise the value is limited to either 0 or 1 by default1. | |
2849 | */ | |
2850 | can_be_one = features | default1; | |
2851 | can_be_zero = features | ~default1; | |
2852 | must_be_one = ~can_be_zero; | |
2853 | ||
2854 | /* | |
2855 | * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one). | |
2856 | * Bit 32:63 -> 1 if the control bit can be one. | |
2857 | */ | |
2858 | return must_be_one | (((uint64_t)can_be_one) << 32); | |
2859 | } | |
2860 | ||
20a78b02 PB |
2861 | static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f) |
2862 | { | |
2863 | uint64_t kvm_vmx_basic = | |
2864 | kvm_arch_get_supported_msr_feature(kvm_state, | |
2865 | MSR_IA32_VMX_BASIC); | |
26051882 YZ |
2866 | |
2867 | if (!kvm_vmx_basic) { | |
2868 | /* If the kernel doesn't support VMX feature (kvm_intel.nested=0), | |
2869 | * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail. | |
2870 | */ | |
2871 | return; | |
2872 | } | |
2873 | ||
20a78b02 PB |
2874 | uint64_t kvm_vmx_misc = |
2875 | kvm_arch_get_supported_msr_feature(kvm_state, | |
2876 | MSR_IA32_VMX_MISC); | |
2877 | uint64_t kvm_vmx_ept_vpid = | |
2878 | kvm_arch_get_supported_msr_feature(kvm_state, | |
2879 | MSR_IA32_VMX_EPT_VPID_CAP); | |
2880 | ||
2881 | /* | |
2882 | * If the guest is 64-bit, a value of 1 is allowed for the host address | |
2883 | * space size vmexit control. | |
2884 | */ | |
2885 | uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM | |
2886 | ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0; | |
2887 | ||
2888 | /* | |
2889 | * Bits 0-30, 32-44 and 50-53 come from the host. KVM should | |
2890 | * not change them for backwards compatibility. | |
2891 | */ | |
2892 | uint64_t fixed_vmx_basic = kvm_vmx_basic & | |
2893 | (MSR_VMX_BASIC_VMCS_REVISION_MASK | | |
2894 | MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK | | |
2895 | MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK); | |
2896 | ||
2897 | /* | |
2898 | * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can | |
2899 | * change in the future but are always zero for now, clear them to be | |
2900 | * future proof. Bits 32-63 in theory could change, though KVM does | |
2901 | * not support dual-monitor treatment and probably never will; mask | |
2902 | * them out as well. | |
2903 | */ | |
2904 | uint64_t fixed_vmx_misc = kvm_vmx_misc & | |
2905 | (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK | | |
2906 | MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK); | |
2907 | ||
2908 | /* | |
2909 | * EPT memory types should not change either, so we do not bother | |
2910 | * adding features for them. | |
2911 | */ | |
2912 | uint64_t fixed_vmx_ept_mask = | |
2913 | (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ? | |
2914 | MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0); | |
2915 | uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask; | |
2916 | ||
2917 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
2918 | make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS, | |
2919 | f[FEAT_VMX_PROCBASED_CTLS])); | |
2920 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
2921 | make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS, | |
2922 | f[FEAT_VMX_PINBASED_CTLS])); | |
2923 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
2924 | make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS, | |
2925 | f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit); | |
2926 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
2927 | make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS, | |
2928 | f[FEAT_VMX_ENTRY_CTLS])); | |
2929 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2, | |
2930 | make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2, | |
2931 | f[FEAT_VMX_SECONDARY_CTLS])); | |
2932 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP, | |
2933 | f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid); | |
2934 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC, | |
2935 | f[FEAT_VMX_BASIC] | fixed_vmx_basic); | |
2936 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC, | |
2937 | f[FEAT_VMX_MISC] | fixed_vmx_misc); | |
2938 | if (has_msr_vmx_vmfunc) { | |
2939 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]); | |
2940 | } | |
2941 | ||
2942 | /* | |
2943 | * Just to be safe, write these with constant values. The CRn_FIXED1 | |
2944 | * MSRs are generated by KVM based on the vCPU's CPUID. | |
2945 | */ | |
2946 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0, | |
2947 | CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK); | |
2948 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0, | |
2949 | CR4_VMXE_MASK); | |
9ce8af4d PB |
2950 | |
2951 | if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) { | |
2952 | /* TSC multiplier (0x2032). */ | |
2953 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32); | |
2954 | } else { | |
2955 | /* Preemption timer (0x482E). */ | |
2956 | kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E); | |
2957 | } | |
20a78b02 PB |
2958 | } |
2959 | ||
ea39f9b6 LX |
2960 | static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f) |
2961 | { | |
2962 | uint64_t kvm_perf_cap = | |
2963 | kvm_arch_get_supported_msr_feature(kvm_state, | |
2964 | MSR_IA32_PERF_CAPABILITIES); | |
2965 | ||
2966 | if (kvm_perf_cap) { | |
2967 | kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES, | |
2968 | kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]); | |
2969 | } | |
2970 | } | |
2971 | ||
420ae1fc PB |
2972 | static int kvm_buf_set_msrs(X86CPU *cpu) |
2973 | { | |
2974 | int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf); | |
2975 | if (ret < 0) { | |
2976 | return ret; | |
2977 | } | |
2978 | ||
2979 | if (ret < cpu->kvm_msr_buf->nmsrs) { | |
2980 | struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; | |
2981 | error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64, | |
2982 | (uint32_t)e->index, (uint64_t)e->data); | |
2983 | } | |
2984 | ||
2985 | assert(ret == cpu->kvm_msr_buf->nmsrs); | |
2986 | return 0; | |
2987 | } | |
2988 | ||
2989 | static void kvm_init_msrs(X86CPU *cpu) | |
2990 | { | |
2991 | CPUX86State *env = &cpu->env; | |
2992 | ||
2993 | kvm_msr_buf_reset(cpu); | |
2994 | if (has_msr_arch_capabs) { | |
2995 | kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES, | |
2996 | env->features[FEAT_ARCH_CAPABILITIES]); | |
2997 | } | |
2998 | ||
2999 | if (has_msr_core_capabs) { | |
3000 | kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY, | |
3001 | env->features[FEAT_CORE_CAPABILITY]); | |
3002 | } | |
3003 | ||
ea39f9b6 LX |
3004 | if (has_msr_perf_capabs && cpu->enable_pmu) { |
3005 | kvm_msr_entry_add_perf(cpu, env->features); | |
3006 | } | |
3007 | ||
67025148 | 3008 | if (has_msr_ucode_rev) { |
32c87d70 PB |
3009 | kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev); |
3010 | } | |
3011 | ||
420ae1fc PB |
3012 | /* |
3013 | * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but | |
3014 | * all kernels with MSR features should have them. | |
3015 | */ | |
3016 | if (kvm_feature_msrs && cpu_has_vmx(env)) { | |
3017 | kvm_msr_entry_add_vmx(cpu, env->features); | |
3018 | } | |
3019 | ||
3020 | assert(kvm_buf_set_msrs(cpu) == 0); | |
3021 | } | |
3022 | ||
1bc22652 | 3023 | static int kvm_put_msrs(X86CPU *cpu, int level) |
05330448 | 3024 | { |
1bc22652 | 3025 | CPUX86State *env = &cpu->env; |
9c600a84 | 3026 | int i; |
05330448 | 3027 | |
d71b62a1 EH |
3028 | kvm_msr_buf_reset(cpu); |
3029 | ||
9c600a84 EH |
3030 | kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs); |
3031 | kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp); | |
3032 | kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip); | |
3033 | kvm_msr_entry_add(cpu, MSR_PAT, env->pat); | |
c3a3a7d3 | 3034 | if (has_msr_star) { |
9c600a84 | 3035 | kvm_msr_entry_add(cpu, MSR_STAR, env->star); |
b9bec74b | 3036 | } |
c3a3a7d3 | 3037 | if (has_msr_hsave_pa) { |
9c600a84 | 3038 | kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave); |
b9bec74b | 3039 | } |
c9b8f6b6 | 3040 | if (has_msr_tsc_aux) { |
9c600a84 | 3041 | kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux); |
c9b8f6b6 | 3042 | } |
f28558d3 | 3043 | if (has_msr_tsc_adjust) { |
9c600a84 | 3044 | kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust); |
f28558d3 | 3045 | } |
21e87c46 | 3046 | if (has_msr_misc_enable) { |
9c600a84 | 3047 | kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, |
21e87c46 AK |
3048 | env->msr_ia32_misc_enable); |
3049 | } | |
fc12d72e | 3050 | if (has_msr_smbase) { |
9c600a84 | 3051 | kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase); |
fc12d72e | 3052 | } |
e13713db LA |
3053 | if (has_msr_smi_count) { |
3054 | kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count); | |
3055 | } | |
6aa4228b CQ |
3056 | if (has_msr_pkrs) { |
3057 | kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs); | |
3058 | } | |
439d19f2 | 3059 | if (has_msr_bndcfgs) { |
9c600a84 | 3060 | kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs); |
439d19f2 | 3061 | } |
18cd2c17 | 3062 | if (has_msr_xss) { |
9c600a84 | 3063 | kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss); |
18cd2c17 | 3064 | } |
65087997 TX |
3065 | if (has_msr_umwait) { |
3066 | kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait); | |
3067 | } | |
a33a2cfe PB |
3068 | if (has_msr_spec_ctrl) { |
3069 | kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl); | |
3070 | } | |
cabf9862 ML |
3071 | if (has_tsc_scale_msr) { |
3072 | kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, env->amd_tsc_scale_msr); | |
3073 | } | |
3074 | ||
2a9758c5 PB |
3075 | if (has_msr_tsx_ctrl) { |
3076 | kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl); | |
3077 | } | |
cfeea0c0 KRW |
3078 | if (has_msr_virt_ssbd) { |
3079 | kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd); | |
3080 | } | |
3081 | ||
05330448 | 3082 | #ifdef TARGET_X86_64 |
25d2e361 | 3083 | if (lm_capable_kernel) { |
9c600a84 EH |
3084 | kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar); |
3085 | kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase); | |
3086 | kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask); | |
3087 | kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar); | |
25d2e361 | 3088 | } |
05330448 | 3089 | #endif |
a33a2cfe | 3090 | |
ff5c186b | 3091 | /* |
0d894367 PB |
3092 | * The following MSRs have side effects on the guest or are too heavy |
3093 | * for normal writeback. Limit them to reset or full state updates. | |
ff5c186b JK |
3094 | */ |
3095 | if (level >= KVM_PUT_RESET_STATE) { | |
9c600a84 EH |
3096 | kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc); |
3097 | kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr); | |
3098 | kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr); | |
6615be07 VK |
3099 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { |
3100 | kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr); | |
3101 | } | |
55c911a5 | 3102 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) { |
9c600a84 | 3103 | kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr); |
c5999bfc | 3104 | } |
55c911a5 | 3105 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) { |
9c600a84 | 3106 | kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr); |
bc9a839d | 3107 | } |
55c911a5 | 3108 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { |
9c600a84 | 3109 | kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr); |
917367aa | 3110 | } |
d645e132 MT |
3111 | |
3112 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { | |
3113 | kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr); | |
3114 | } | |
3115 | ||
0b368a10 JD |
3116 | if (has_architectural_pmu_version > 0) { |
3117 | if (has_architectural_pmu_version > 1) { | |
3118 | /* Stop the counter. */ | |
3119 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); | |
3120 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
3121 | } | |
0d894367 PB |
3122 | |
3123 | /* Set the counter values. */ | |
0b368a10 | 3124 | for (i = 0; i < num_architectural_pmu_fixed_counters; i++) { |
9c600a84 | 3125 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, |
0d894367 PB |
3126 | env->msr_fixed_counters[i]); |
3127 | } | |
0b368a10 | 3128 | for (i = 0; i < num_architectural_pmu_gp_counters; i++) { |
9c600a84 | 3129 | kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, |
0d894367 | 3130 | env->msr_gp_counters[i]); |
9c600a84 | 3131 | kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, |
0d894367 PB |
3132 | env->msr_gp_evtsel[i]); |
3133 | } | |
0b368a10 JD |
3134 | if (has_architectural_pmu_version > 1) { |
3135 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, | |
3136 | env->msr_global_status); | |
3137 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, | |
3138 | env->msr_global_ovf_ctrl); | |
3139 | ||
3140 | /* Now start the PMU. */ | |
3141 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, | |
3142 | env->msr_fixed_ctr_ctrl); | |
3143 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, | |
3144 | env->msr_global_ctrl); | |
3145 | } | |
0d894367 | 3146 | } |
da1cc323 EY |
3147 | /* |
3148 | * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add, | |
3149 | * only sync them to KVM on the first cpu | |
3150 | */ | |
3151 | if (current_cpu == first_cpu) { | |
3152 | if (has_msr_hv_hypercall) { | |
3153 | kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, | |
3154 | env->msr_hv_guest_os_id); | |
3155 | kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, | |
3156 | env->msr_hv_hypercall); | |
3157 | } | |
2d384d7c | 3158 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { |
da1cc323 EY |
3159 | kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, |
3160 | env->msr_hv_tsc); | |
3161 | } | |
2d384d7c | 3162 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { |
ba6a4fd9 VK |
3163 | kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, |
3164 | env->msr_hv_reenlightenment_control); | |
3165 | kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, | |
3166 | env->msr_hv_tsc_emulation_control); | |
3167 | kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, | |
3168 | env->msr_hv_tsc_emulation_status); | |
3169 | } | |
eab70139 | 3170 | } |
2d384d7c | 3171 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { |
9c600a84 | 3172 | kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, |
5ef68987 | 3173 | env->msr_hv_vapic); |
eab70139 | 3174 | } |
f2a53c9e AS |
3175 | if (has_msr_hv_crash) { |
3176 | int j; | |
3177 | ||
5e953812 | 3178 | for (j = 0; j < HV_CRASH_PARAMS; j++) |
9c600a84 | 3179 | kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, |
f2a53c9e AS |
3180 | env->msr_hv_crash_params[j]); |
3181 | ||
5e953812 | 3182 | kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY); |
f2a53c9e | 3183 | } |
46eb8f98 | 3184 | if (has_msr_hv_runtime) { |
9c600a84 | 3185 | kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime); |
46eb8f98 | 3186 | } |
2d384d7c VK |
3187 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) |
3188 | && hv_vpindex_settable) { | |
701189e3 RK |
3189 | kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX, |
3190 | hyperv_vp_index(CPU(cpu))); | |
e9688fab | 3191 | } |
2d384d7c | 3192 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { |
866eea9a AS |
3193 | int j; |
3194 | ||
09df29b6 RK |
3195 | kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION); |
3196 | ||
9c600a84 | 3197 | kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, |
866eea9a | 3198 | env->msr_hv_synic_control); |
9c600a84 | 3199 | kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, |
866eea9a | 3200 | env->msr_hv_synic_evt_page); |
9c600a84 | 3201 | kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, |
866eea9a AS |
3202 | env->msr_hv_synic_msg_page); |
3203 | ||
3204 | for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) { | |
9c600a84 | 3205 | kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j, |
866eea9a AS |
3206 | env->msr_hv_synic_sint[j]); |
3207 | } | |
3208 | } | |
ff99aa64 AS |
3209 | if (has_msr_hv_stimer) { |
3210 | int j; | |
3211 | ||
3212 | for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) { | |
9c600a84 | 3213 | kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2, |
ff99aa64 AS |
3214 | env->msr_hv_stimer_config[j]); |
3215 | } | |
3216 | ||
3217 | for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) { | |
9c600a84 | 3218 | kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2, |
ff99aa64 AS |
3219 | env->msr_hv_stimer_count[j]); |
3220 | } | |
3221 | } | |
1eabfce6 | 3222 | if (env->features[FEAT_1_EDX] & CPUID_MTRR) { |
112dad69 DDAG |
3223 | uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits); |
3224 | ||
9c600a84 EH |
3225 | kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype); |
3226 | kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]); | |
3227 | kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]); | |
3228 | kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]); | |
3229 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]); | |
3230 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]); | |
3231 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]); | |
3232 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]); | |
3233 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]); | |
3234 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]); | |
3235 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]); | |
3236 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]); | |
d1ae67f6 | 3237 | for (i = 0; i < MSR_MTRRcap_VCNT; i++) { |
112dad69 DDAG |
3238 | /* The CPU GPs if we write to a bit above the physical limit of |
3239 | * the host CPU (and KVM emulates that) | |
3240 | */ | |
3241 | uint64_t mask = env->mtrr_var[i].mask; | |
3242 | mask &= phys_mask; | |
3243 | ||
9c600a84 EH |
3244 | kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), |
3245 | env->mtrr_var[i].base); | |
112dad69 | 3246 | kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask); |
d1ae67f6 AW |
3247 | } |
3248 | } | |
b77146e9 CP |
3249 | if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { |
3250 | int addr_num = kvm_arch_get_supported_cpuid(kvm_state, | |
3251 | 0x14, 1, R_EAX) & 0x7; | |
3252 | ||
3253 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, | |
3254 | env->msr_rtit_ctrl); | |
3255 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, | |
3256 | env->msr_rtit_status); | |
3257 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, | |
3258 | env->msr_rtit_output_base); | |
3259 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, | |
3260 | env->msr_rtit_output_mask); | |
3261 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, | |
3262 | env->msr_rtit_cr3_match); | |
3263 | for (i = 0; i < addr_num; i++) { | |
3264 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, | |
3265 | env->msr_rtit_addrs[i]); | |
3266 | } | |
3267 | } | |
6bdf863d | 3268 | |
db888065 SC |
3269 | if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) { |
3270 | kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, | |
3271 | env->msr_ia32_sgxlepubkeyhash[0]); | |
3272 | kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, | |
3273 | env->msr_ia32_sgxlepubkeyhash[1]); | |
3274 | kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, | |
3275 | env->msr_ia32_sgxlepubkeyhash[2]); | |
3276 | kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, | |
3277 | env->msr_ia32_sgxlepubkeyhash[3]); | |
3278 | } | |
3279 | ||
6bdf863d JK |
3280 | /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see |
3281 | * kvm_put_msr_feature_control. */ | |
ea643051 | 3282 | } |
20a78b02 | 3283 | |
57780495 | 3284 | if (env->mcg_cap) { |
d8da8574 | 3285 | int i; |
b9bec74b | 3286 | |
9c600a84 EH |
3287 | kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status); |
3288 | kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl); | |
87f8b626 AR |
3289 | if (has_msr_mcg_ext_ctl) { |
3290 | kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl); | |
3291 | } | |
c34d440a | 3292 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
9c600a84 | 3293 | kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]); |
57780495 MT |
3294 | } |
3295 | } | |
1a03675d | 3296 | |
420ae1fc | 3297 | return kvm_buf_set_msrs(cpu); |
05330448 AL |
3298 | } |
3299 | ||
3300 | ||
1bc22652 | 3301 | static int kvm_get_fpu(X86CPU *cpu) |
05330448 | 3302 | { |
1bc22652 | 3303 | CPUX86State *env = &cpu->env; |
05330448 AL |
3304 | struct kvm_fpu fpu; |
3305 | int i, ret; | |
3306 | ||
1bc22652 | 3307 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu); |
b9bec74b | 3308 | if (ret < 0) { |
05330448 | 3309 | return ret; |
b9bec74b | 3310 | } |
05330448 AL |
3311 | |
3312 | env->fpstt = (fpu.fsw >> 11) & 7; | |
3313 | env->fpus = fpu.fsw; | |
3314 | env->fpuc = fpu.fcw; | |
42cc8fa6 JK |
3315 | env->fpop = fpu.last_opcode; |
3316 | env->fpip = fpu.last_ip; | |
3317 | env->fpdp = fpu.last_dp; | |
b9bec74b JK |
3318 | for (i = 0; i < 8; ++i) { |
3319 | env->fptags[i] = !((fpu.ftwx >> i) & 1); | |
3320 | } | |
05330448 | 3321 | memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs); |
bee81887 | 3322 | for (i = 0; i < CPU_NB_REGS; i++) { |
19cbd87c EH |
3323 | env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]); |
3324 | env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]); | |
bee81887 | 3325 | } |
05330448 AL |
3326 | env->mxcsr = fpu.mxcsr; |
3327 | ||
3328 | return 0; | |
3329 | } | |
3330 | ||
1bc22652 | 3331 | static int kvm_get_xsave(X86CPU *cpu) |
f1665b21 | 3332 | { |
1bc22652 | 3333 | CPUX86State *env = &cpu->env; |
c0198c5f | 3334 | void *xsave = env->xsave_buf; |
e56dd3c7 | 3335 | int type, ret; |
f1665b21 | 3336 | |
28143b40 | 3337 | if (!has_xsave) { |
1bc22652 | 3338 | return kvm_get_fpu(cpu); |
b9bec74b | 3339 | } |
f1665b21 | 3340 | |
e56dd3c7 JL |
3341 | type = has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE; |
3342 | ret = kvm_vcpu_ioctl(CPU(cpu), type, xsave); | |
0f53994f | 3343 | if (ret < 0) { |
f1665b21 | 3344 | return ret; |
0f53994f | 3345 | } |
c0198c5f | 3346 | x86_cpu_xrstor_all_areas(cpu, xsave, env->xsave_buf_len); |
f1665b21 | 3347 | |
f1665b21 | 3348 | return 0; |
f1665b21 SY |
3349 | } |
3350 | ||
1bc22652 | 3351 | static int kvm_get_xcrs(X86CPU *cpu) |
f1665b21 | 3352 | { |
1bc22652 | 3353 | CPUX86State *env = &cpu->env; |
f1665b21 SY |
3354 | int i, ret; |
3355 | struct kvm_xcrs xcrs; | |
3356 | ||
28143b40 | 3357 | if (!has_xcrs) { |
f1665b21 | 3358 | return 0; |
b9bec74b | 3359 | } |
f1665b21 | 3360 | |
1bc22652 | 3361 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs); |
b9bec74b | 3362 | if (ret < 0) { |
f1665b21 | 3363 | return ret; |
b9bec74b | 3364 | } |
f1665b21 | 3365 | |
b9bec74b | 3366 | for (i = 0; i < xcrs.nr_xcrs; i++) { |
f1665b21 | 3367 | /* Only support xcr0 now */ |
0fd53fec PB |
3368 | if (xcrs.xcrs[i].xcr == 0) { |
3369 | env->xcr0 = xcrs.xcrs[i].value; | |
f1665b21 SY |
3370 | break; |
3371 | } | |
b9bec74b | 3372 | } |
f1665b21 | 3373 | return 0; |
f1665b21 SY |
3374 | } |
3375 | ||
1bc22652 | 3376 | static int kvm_get_sregs(X86CPU *cpu) |
05330448 | 3377 | { |
1bc22652 | 3378 | CPUX86State *env = &cpu->env; |
05330448 | 3379 | struct kvm_sregs sregs; |
1520f8bb | 3380 | int ret; |
05330448 | 3381 | |
1bc22652 | 3382 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); |
b9bec74b | 3383 | if (ret < 0) { |
05330448 | 3384 | return ret; |
b9bec74b | 3385 | } |
05330448 | 3386 | |
1520f8bb PB |
3387 | /* |
3388 | * The interrupt_bitmap is ignored because KVM_GET_SREGS is | |
3389 | * always preceded by KVM_GET_VCPU_EVENTS. | |
3390 | */ | |
05330448 AL |
3391 | |
3392 | get_seg(&env->segs[R_CS], &sregs.cs); | |
3393 | get_seg(&env->segs[R_DS], &sregs.ds); | |
3394 | get_seg(&env->segs[R_ES], &sregs.es); | |
3395 | get_seg(&env->segs[R_FS], &sregs.fs); | |
3396 | get_seg(&env->segs[R_GS], &sregs.gs); | |
3397 | get_seg(&env->segs[R_SS], &sregs.ss); | |
3398 | ||
3399 | get_seg(&env->tr, &sregs.tr); | |
3400 | get_seg(&env->ldt, &sregs.ldt); | |
3401 | ||
3402 | env->idt.limit = sregs.idt.limit; | |
3403 | env->idt.base = sregs.idt.base; | |
3404 | env->gdt.limit = sregs.gdt.limit; | |
3405 | env->gdt.base = sregs.gdt.base; | |
3406 | ||
3407 | env->cr[0] = sregs.cr0; | |
3408 | env->cr[2] = sregs.cr2; | |
3409 | env->cr[3] = sregs.cr3; | |
3410 | env->cr[4] = sregs.cr4; | |
3411 | ||
05330448 | 3412 | env->efer = sregs.efer; |
cce47516 JK |
3413 | |
3414 | /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ | |
35b1b927 | 3415 | x86_update_hflags(env); |
05330448 AL |
3416 | |
3417 | return 0; | |
3418 | } | |
3419 | ||
8f515d38 ML |
3420 | static int kvm_get_sregs2(X86CPU *cpu) |
3421 | { | |
3422 | CPUX86State *env = &cpu->env; | |
3423 | struct kvm_sregs2 sregs; | |
3424 | int i, ret; | |
3425 | ||
3426 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS2, &sregs); | |
3427 | if (ret < 0) { | |
3428 | return ret; | |
3429 | } | |
3430 | ||
3431 | get_seg(&env->segs[R_CS], &sregs.cs); | |
3432 | get_seg(&env->segs[R_DS], &sregs.ds); | |
3433 | get_seg(&env->segs[R_ES], &sregs.es); | |
3434 | get_seg(&env->segs[R_FS], &sregs.fs); | |
3435 | get_seg(&env->segs[R_GS], &sregs.gs); | |
3436 | get_seg(&env->segs[R_SS], &sregs.ss); | |
3437 | ||
3438 | get_seg(&env->tr, &sregs.tr); | |
3439 | get_seg(&env->ldt, &sregs.ldt); | |
3440 | ||
3441 | env->idt.limit = sregs.idt.limit; | |
3442 | env->idt.base = sregs.idt.base; | |
3443 | env->gdt.limit = sregs.gdt.limit; | |
3444 | env->gdt.base = sregs.gdt.base; | |
3445 | ||
3446 | env->cr[0] = sregs.cr0; | |
3447 | env->cr[2] = sregs.cr2; | |
3448 | env->cr[3] = sregs.cr3; | |
3449 | env->cr[4] = sregs.cr4; | |
3450 | ||
3451 | env->efer = sregs.efer; | |
3452 | ||
3453 | env->pdptrs_valid = sregs.flags & KVM_SREGS2_FLAGS_PDPTRS_VALID; | |
3454 | ||
3455 | if (env->pdptrs_valid) { | |
3456 | for (i = 0; i < 4; i++) { | |
3457 | env->pdptrs[i] = sregs.pdptrs[i]; | |
3458 | } | |
3459 | } | |
3460 | ||
3461 | /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */ | |
3462 | x86_update_hflags(env); | |
3463 | ||
3464 | return 0; | |
3465 | } | |
3466 | ||
1bc22652 | 3467 | static int kvm_get_msrs(X86CPU *cpu) |
05330448 | 3468 | { |
1bc22652 | 3469 | CPUX86State *env = &cpu->env; |
d71b62a1 | 3470 | struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries; |
9c600a84 | 3471 | int ret, i; |
fcc35e7c | 3472 | uint64_t mtrr_top_bits; |
05330448 | 3473 | |
d71b62a1 EH |
3474 | kvm_msr_buf_reset(cpu); |
3475 | ||
9c600a84 EH |
3476 | kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0); |
3477 | kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0); | |
3478 | kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0); | |
3479 | kvm_msr_entry_add(cpu, MSR_PAT, 0); | |
c3a3a7d3 | 3480 | if (has_msr_star) { |
9c600a84 | 3481 | kvm_msr_entry_add(cpu, MSR_STAR, 0); |
b9bec74b | 3482 | } |
c3a3a7d3 | 3483 | if (has_msr_hsave_pa) { |
9c600a84 | 3484 | kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0); |
b9bec74b | 3485 | } |
c9b8f6b6 | 3486 | if (has_msr_tsc_aux) { |
9c600a84 | 3487 | kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0); |
c9b8f6b6 | 3488 | } |
f28558d3 | 3489 | if (has_msr_tsc_adjust) { |
9c600a84 | 3490 | kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0); |
f28558d3 | 3491 | } |
aa82ba54 | 3492 | if (has_msr_tsc_deadline) { |
9c600a84 | 3493 | kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0); |
aa82ba54 | 3494 | } |
21e87c46 | 3495 | if (has_msr_misc_enable) { |
9c600a84 | 3496 | kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0); |
21e87c46 | 3497 | } |
fc12d72e | 3498 | if (has_msr_smbase) { |
9c600a84 | 3499 | kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0); |
fc12d72e | 3500 | } |
e13713db LA |
3501 | if (has_msr_smi_count) { |
3502 | kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0); | |
3503 | } | |
df67696e | 3504 | if (has_msr_feature_control) { |
9c600a84 | 3505 | kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0); |
df67696e | 3506 | } |
6aa4228b CQ |
3507 | if (has_msr_pkrs) { |
3508 | kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0); | |
3509 | } | |
79e9ebeb | 3510 | if (has_msr_bndcfgs) { |
9c600a84 | 3511 | kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0); |
79e9ebeb | 3512 | } |
18cd2c17 | 3513 | if (has_msr_xss) { |
9c600a84 | 3514 | kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0); |
18cd2c17 | 3515 | } |
65087997 TX |
3516 | if (has_msr_umwait) { |
3517 | kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0); | |
3518 | } | |
a33a2cfe PB |
3519 | if (has_msr_spec_ctrl) { |
3520 | kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0); | |
3521 | } | |
cabf9862 ML |
3522 | if (has_tsc_scale_msr) { |
3523 | kvm_msr_entry_add(cpu, MSR_AMD64_TSC_RATIO, 0); | |
3524 | } | |
3525 | ||
2a9758c5 PB |
3526 | if (has_msr_tsx_ctrl) { |
3527 | kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0); | |
3528 | } | |
cfeea0c0 KRW |
3529 | if (has_msr_virt_ssbd) { |
3530 | kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0); | |
3531 | } | |
b8cc45d6 | 3532 | if (!env->tsc_valid) { |
9c600a84 | 3533 | kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); |
1354869c | 3534 | env->tsc_valid = !runstate_is_running(); |
b8cc45d6 GC |
3535 | } |
3536 | ||
05330448 | 3537 | #ifdef TARGET_X86_64 |
25d2e361 | 3538 | if (lm_capable_kernel) { |
9c600a84 EH |
3539 | kvm_msr_entry_add(cpu, MSR_CSTAR, 0); |
3540 | kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0); | |
3541 | kvm_msr_entry_add(cpu, MSR_FMASK, 0); | |
3542 | kvm_msr_entry_add(cpu, MSR_LSTAR, 0); | |
25d2e361 | 3543 | } |
05330448 | 3544 | #endif |
9c600a84 EH |
3545 | kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0); |
3546 | kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0); | |
db5daafa VK |
3547 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) { |
3548 | kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0); | |
3549 | } | |
6615be07 VK |
3550 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) { |
3551 | kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0); | |
3552 | } | |
55c911a5 | 3553 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) { |
9c600a84 | 3554 | kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0); |
bc9a839d | 3555 | } |
55c911a5 | 3556 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) { |
9c600a84 | 3557 | kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0); |
917367aa | 3558 | } |
d645e132 MT |
3559 | if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) { |
3560 | kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1); | |
3561 | } | |
0b368a10 JD |
3562 | if (has_architectural_pmu_version > 0) { |
3563 | if (has_architectural_pmu_version > 1) { | |
3564 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); | |
3565 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); | |
3566 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0); | |
3567 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0); | |
3568 | } | |
3569 | for (i = 0; i < num_architectural_pmu_fixed_counters; i++) { | |
9c600a84 | 3570 | kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); |
0d894367 | 3571 | } |
0b368a10 | 3572 | for (i = 0; i < num_architectural_pmu_gp_counters; i++) { |
9c600a84 EH |
3573 | kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); |
3574 | kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); | |
0d894367 PB |
3575 | } |
3576 | } | |
1a03675d | 3577 | |
57780495 | 3578 | if (env->mcg_cap) { |
9c600a84 EH |
3579 | kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0); |
3580 | kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0); | |
87f8b626 AR |
3581 | if (has_msr_mcg_ext_ctl) { |
3582 | kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0); | |
3583 | } | |
b9bec74b | 3584 | for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) { |
9c600a84 | 3585 | kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0); |
b9bec74b | 3586 | } |
57780495 | 3587 | } |
57780495 | 3588 | |
1c90ef26 | 3589 | if (has_msr_hv_hypercall) { |
9c600a84 EH |
3590 | kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0); |
3591 | kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0); | |
1c90ef26 | 3592 | } |
2d384d7c | 3593 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) { |
9c600a84 | 3594 | kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0); |
5ef68987 | 3595 | } |
2d384d7c | 3596 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) { |
9c600a84 | 3597 | kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0); |
48a5f3bc | 3598 | } |
2d384d7c | 3599 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) { |
ba6a4fd9 VK |
3600 | kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0); |
3601 | kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0); | |
3602 | kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0); | |
3603 | } | |
f2a53c9e AS |
3604 | if (has_msr_hv_crash) { |
3605 | int j; | |
3606 | ||
5e953812 | 3607 | for (j = 0; j < HV_CRASH_PARAMS; j++) { |
9c600a84 | 3608 | kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0); |
f2a53c9e AS |
3609 | } |
3610 | } | |
46eb8f98 | 3611 | if (has_msr_hv_runtime) { |
9c600a84 | 3612 | kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0); |
46eb8f98 | 3613 | } |
2d384d7c | 3614 | if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) { |
866eea9a AS |
3615 | uint32_t msr; |
3616 | ||
9c600a84 | 3617 | kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0); |
9c600a84 EH |
3618 | kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0); |
3619 | kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0); | |
866eea9a | 3620 | for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) { |
9c600a84 | 3621 | kvm_msr_entry_add(cpu, msr, 0); |
866eea9a AS |
3622 | } |
3623 | } | |
ff99aa64 AS |
3624 | if (has_msr_hv_stimer) { |
3625 | uint32_t msr; | |
3626 | ||
3627 | for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT; | |
3628 | msr++) { | |
9c600a84 | 3629 | kvm_msr_entry_add(cpu, msr, 0); |
ff99aa64 AS |
3630 | } |
3631 | } | |
1eabfce6 | 3632 | if (env->features[FEAT_1_EDX] & CPUID_MTRR) { |
9c600a84 EH |
3633 | kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0); |
3634 | kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0); | |
3635 | kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0); | |
3636 | kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0); | |
3637 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0); | |
3638 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0); | |
3639 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0); | |
3640 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0); | |
3641 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0); | |
3642 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0); | |
3643 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0); | |
3644 | kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0); | |
d1ae67f6 | 3645 | for (i = 0; i < MSR_MTRRcap_VCNT; i++) { |
9c600a84 EH |
3646 | kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0); |
3647 | kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0); | |
d1ae67f6 AW |
3648 | } |
3649 | } | |
5ef68987 | 3650 | |
b77146e9 CP |
3651 | if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) { |
3652 | int addr_num = | |
3653 | kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7; | |
3654 | ||
3655 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0); | |
3656 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0); | |
3657 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0); | |
3658 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0); | |
3659 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0); | |
3660 | for (i = 0; i < addr_num; i++) { | |
3661 | kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0); | |
3662 | } | |
3663 | } | |
3664 | ||
db888065 SC |
3665 | if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_SGX_LC) { |
3666 | kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH0, 0); | |
3667 | kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH1, 0); | |
3668 | kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH2, 0); | |
3669 | kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0); | |
3670 | } | |
3671 | ||
d71b62a1 | 3672 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); |
b9bec74b | 3673 | if (ret < 0) { |
05330448 | 3674 | return ret; |
b9bec74b | 3675 | } |
05330448 | 3676 | |
c70b11d1 EH |
3677 | if (ret < cpu->kvm_msr_buf->nmsrs) { |
3678 | struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret]; | |
3679 | error_report("error: failed to get MSR 0x%" PRIx32, | |
3680 | (uint32_t)e->index); | |
3681 | } | |
3682 | ||
9c600a84 | 3683 | assert(ret == cpu->kvm_msr_buf->nmsrs); |
fcc35e7c DDAG |
3684 | /* |
3685 | * MTRR masks: Each mask consists of 5 parts | |
3686 | * a 10..0: must be zero | |
3687 | * b 11 : valid bit | |
3688 | * c n-1.12: actual mask bits | |
3689 | * d 51..n: reserved must be zero | |
3690 | * e 63.52: reserved must be zero | |
3691 | * | |
3692 | * 'n' is the number of physical bits supported by the CPU and is | |
3693 | * apparently always <= 52. We know our 'n' but don't know what | |
3694 | * the destinations 'n' is; it might be smaller, in which case | |
3695 | * it masks (c) on loading. It might be larger, in which case | |
3696 | * we fill 'd' so that d..c is consistent irrespetive of the 'n' | |
3697 | * we're migrating to. | |
3698 | */ | |
3699 | ||
3700 | if (cpu->fill_mtrr_mask) { | |
3701 | QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52); | |
3702 | assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS); | |
3703 | mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); | |
3704 | } else { | |
3705 | mtrr_top_bits = 0; | |
3706 | } | |
3707 | ||
05330448 | 3708 | for (i = 0; i < ret; i++) { |
0d894367 PB |
3709 | uint32_t index = msrs[i].index; |
3710 | switch (index) { | |
05330448 AL |
3711 | case MSR_IA32_SYSENTER_CS: |
3712 | env->sysenter_cs = msrs[i].data; | |
3713 | break; | |
3714 | case MSR_IA32_SYSENTER_ESP: | |
3715 | env->sysenter_esp = msrs[i].data; | |
3716 | break; | |
3717 | case MSR_IA32_SYSENTER_EIP: | |
3718 | env->sysenter_eip = msrs[i].data; | |
3719 | break; | |
0c03266a JK |
3720 | case MSR_PAT: |
3721 | env->pat = msrs[i].data; | |
3722 | break; | |
05330448 AL |
3723 | case MSR_STAR: |
3724 | env->star = msrs[i].data; | |
3725 | break; | |
3726 | #ifdef TARGET_X86_64 | |
3727 | case MSR_CSTAR: | |
3728 | env->cstar = msrs[i].data; | |
3729 | break; | |
3730 | case MSR_KERNELGSBASE: | |
3731 | env->kernelgsbase = msrs[i].data; | |
3732 | break; | |
3733 | case MSR_FMASK: | |
3734 | env->fmask = msrs[i].data; | |
3735 | break; | |
3736 | case MSR_LSTAR: | |
3737 | env->lstar = msrs[i].data; | |
3738 | break; | |
3739 | #endif | |
3740 | case MSR_IA32_TSC: | |
3741 | env->tsc = msrs[i].data; | |
3742 | break; | |
c9b8f6b6 AS |
3743 | case MSR_TSC_AUX: |
3744 | env->tsc_aux = msrs[i].data; | |
3745 | break; | |
f28558d3 WA |
3746 | case MSR_TSC_ADJUST: |
3747 | env->tsc_adjust = msrs[i].data; | |
3748 | break; | |
aa82ba54 LJ |
3749 | case MSR_IA32_TSCDEADLINE: |
3750 | env->tsc_deadline = msrs[i].data; | |
3751 | break; | |
aa851e36 MT |
3752 | case MSR_VM_HSAVE_PA: |
3753 | env->vm_hsave = msrs[i].data; | |
3754 | break; | |
1a03675d GC |
3755 | case MSR_KVM_SYSTEM_TIME: |
3756 | env->system_time_msr = msrs[i].data; | |
3757 | break; | |
3758 | case MSR_KVM_WALL_CLOCK: | |
3759 | env->wall_clock_msr = msrs[i].data; | |
3760 | break; | |
57780495 MT |
3761 | case MSR_MCG_STATUS: |
3762 | env->mcg_status = msrs[i].data; | |
3763 | break; | |
3764 | case MSR_MCG_CTL: | |
3765 | env->mcg_ctl = msrs[i].data; | |
3766 | break; | |
87f8b626 AR |
3767 | case MSR_MCG_EXT_CTL: |
3768 | env->mcg_ext_ctl = msrs[i].data; | |
3769 | break; | |
21e87c46 AK |
3770 | case MSR_IA32_MISC_ENABLE: |
3771 | env->msr_ia32_misc_enable = msrs[i].data; | |
3772 | break; | |
fc12d72e PB |
3773 | case MSR_IA32_SMBASE: |
3774 | env->smbase = msrs[i].data; | |
3775 | break; | |
e13713db LA |
3776 | case MSR_SMI_COUNT: |
3777 | env->msr_smi_count = msrs[i].data; | |
3778 | break; | |
0779caeb ACL |
3779 | case MSR_IA32_FEATURE_CONTROL: |
3780 | env->msr_ia32_feature_control = msrs[i].data; | |
df67696e | 3781 | break; |
79e9ebeb LJ |
3782 | case MSR_IA32_BNDCFGS: |
3783 | env->msr_bndcfgs = msrs[i].data; | |
3784 | break; | |
18cd2c17 WL |
3785 | case MSR_IA32_XSS: |
3786 | env->xss = msrs[i].data; | |
3787 | break; | |
65087997 TX |
3788 | case MSR_IA32_UMWAIT_CONTROL: |
3789 | env->umwait = msrs[i].data; | |
3790 | break; | |
6aa4228b CQ |
3791 | case MSR_IA32_PKRS: |
3792 | env->pkrs = msrs[i].data; | |
3793 | break; | |
57780495 | 3794 | default: |
57780495 MT |
3795 | if (msrs[i].index >= MSR_MC0_CTL && |
3796 | msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) { | |
3797 | env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data; | |
57780495 | 3798 | } |
d8da8574 | 3799 | break; |
f6584ee2 GN |
3800 | case MSR_KVM_ASYNC_PF_EN: |
3801 | env->async_pf_en_msr = msrs[i].data; | |
3802 | break; | |
db5daafa VK |
3803 | case MSR_KVM_ASYNC_PF_INT: |
3804 | env->async_pf_int_msr = msrs[i].data; | |
3805 | break; | |
bc9a839d MT |
3806 | case MSR_KVM_PV_EOI_EN: |
3807 | env->pv_eoi_en_msr = msrs[i].data; | |
3808 | break; | |
917367aa MT |
3809 | case MSR_KVM_STEAL_TIME: |
3810 | env->steal_time_msr = msrs[i].data; | |
3811 | break; | |
d645e132 MT |
3812 | case MSR_KVM_POLL_CONTROL: { |
3813 | env->poll_control_msr = msrs[i].data; | |
3814 | break; | |
3815 | } | |
0d894367 PB |
3816 | case MSR_CORE_PERF_FIXED_CTR_CTRL: |
3817 | env->msr_fixed_ctr_ctrl = msrs[i].data; | |
3818 | break; | |
3819 | case MSR_CORE_PERF_GLOBAL_CTRL: | |
3820 | env->msr_global_ctrl = msrs[i].data; | |
3821 | break; | |
3822 | case MSR_CORE_PERF_GLOBAL_STATUS: | |
3823 | env->msr_global_status = msrs[i].data; | |
3824 | break; | |
3825 | case MSR_CORE_PERF_GLOBAL_OVF_CTRL: | |
3826 | env->msr_global_ovf_ctrl = msrs[i].data; | |
3827 | break; | |
3828 | case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1: | |
3829 | env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data; | |
3830 | break; | |
3831 | case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: | |
3832 | env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data; | |
3833 | break; | |
3834 | case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: | |
3835 | env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; | |
3836 | break; | |
1c90ef26 VR |
3837 | case HV_X64_MSR_HYPERCALL: |
3838 | env->msr_hv_hypercall = msrs[i].data; | |
3839 | break; | |
3840 | case HV_X64_MSR_GUEST_OS_ID: | |
3841 | env->msr_hv_guest_os_id = msrs[i].data; | |
3842 | break; | |
5ef68987 VR |
3843 | case HV_X64_MSR_APIC_ASSIST_PAGE: |
3844 | env->msr_hv_vapic = msrs[i].data; | |
3845 | break; | |
48a5f3bc VR |
3846 | case HV_X64_MSR_REFERENCE_TSC: |
3847 | env->msr_hv_tsc = msrs[i].data; | |
3848 | break; | |
f2a53c9e AS |
3849 | case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4: |
3850 | env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data; | |
3851 | break; | |
46eb8f98 AS |
3852 | case HV_X64_MSR_VP_RUNTIME: |
3853 | env->msr_hv_runtime = msrs[i].data; | |
3854 | break; | |
866eea9a AS |
3855 | case HV_X64_MSR_SCONTROL: |
3856 | env->msr_hv_synic_control = msrs[i].data; | |
3857 | break; | |
866eea9a AS |
3858 | case HV_X64_MSR_SIEFP: |
3859 | env->msr_hv_synic_evt_page = msrs[i].data; | |
3860 | break; | |
3861 | case HV_X64_MSR_SIMP: | |
3862 | env->msr_hv_synic_msg_page = msrs[i].data; | |
3863 | break; | |
3864 | case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15: | |
3865 | env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data; | |
ff99aa64 AS |
3866 | break; |
3867 | case HV_X64_MSR_STIMER0_CONFIG: | |
3868 | case HV_X64_MSR_STIMER1_CONFIG: | |
3869 | case HV_X64_MSR_STIMER2_CONFIG: | |
3870 | case HV_X64_MSR_STIMER3_CONFIG: | |
3871 | env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] = | |
3872 | msrs[i].data; | |
3873 | break; | |
3874 | case HV_X64_MSR_STIMER0_COUNT: | |
3875 | case HV_X64_MSR_STIMER1_COUNT: | |
3876 | case HV_X64_MSR_STIMER2_COUNT: | |
3877 | case HV_X64_MSR_STIMER3_COUNT: | |
3878 | env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] = | |
3879 | msrs[i].data; | |
866eea9a | 3880 | break; |
ba6a4fd9 VK |
3881 | case HV_X64_MSR_REENLIGHTENMENT_CONTROL: |
3882 | env->msr_hv_reenlightenment_control = msrs[i].data; | |
3883 | break; | |
3884 | case HV_X64_MSR_TSC_EMULATION_CONTROL: | |
3885 | env->msr_hv_tsc_emulation_control = msrs[i].data; | |
3886 | break; | |
3887 | case HV_X64_MSR_TSC_EMULATION_STATUS: | |
3888 | env->msr_hv_tsc_emulation_status = msrs[i].data; | |
3889 | break; | |
d1ae67f6 AW |
3890 | case MSR_MTRRdefType: |
3891 | env->mtrr_deftype = msrs[i].data; | |
3892 | break; | |
3893 | case MSR_MTRRfix64K_00000: | |
3894 | env->mtrr_fixed[0] = msrs[i].data; | |
3895 | break; | |
3896 | case MSR_MTRRfix16K_80000: | |
3897 | env->mtrr_fixed[1] = msrs[i].data; | |
3898 | break; | |
3899 | case MSR_MTRRfix16K_A0000: | |
3900 | env->mtrr_fixed[2] = msrs[i].data; | |
3901 | break; | |
3902 | case MSR_MTRRfix4K_C0000: | |
3903 | env->mtrr_fixed[3] = msrs[i].data; | |
3904 | break; | |
3905 | case MSR_MTRRfix4K_C8000: | |
3906 | env->mtrr_fixed[4] = msrs[i].data; | |
3907 | break; | |
3908 | case MSR_MTRRfix4K_D0000: | |
3909 | env->mtrr_fixed[5] = msrs[i].data; | |
3910 | break; | |
3911 | case MSR_MTRRfix4K_D8000: | |
3912 | env->mtrr_fixed[6] = msrs[i].data; | |
3913 | break; | |
3914 | case MSR_MTRRfix4K_E0000: | |
3915 | env->mtrr_fixed[7] = msrs[i].data; | |
3916 | break; | |
3917 | case MSR_MTRRfix4K_E8000: | |
3918 | env->mtrr_fixed[8] = msrs[i].data; | |
3919 | break; | |
3920 | case MSR_MTRRfix4K_F0000: | |
3921 | env->mtrr_fixed[9] = msrs[i].data; | |
3922 | break; | |
3923 | case MSR_MTRRfix4K_F8000: | |
3924 | env->mtrr_fixed[10] = msrs[i].data; | |
3925 | break; | |
3926 | case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): | |
3927 | if (index & 1) { | |
fcc35e7c DDAG |
3928 | env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data | |
3929 | mtrr_top_bits; | |
d1ae67f6 AW |
3930 | } else { |
3931 | env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; | |
3932 | } | |
3933 | break; | |
a33a2cfe PB |
3934 | case MSR_IA32_SPEC_CTRL: |
3935 | env->spec_ctrl = msrs[i].data; | |
3936 | break; | |
cabf9862 ML |
3937 | case MSR_AMD64_TSC_RATIO: |
3938 | env->amd_tsc_scale_msr = msrs[i].data; | |
3939 | break; | |
2a9758c5 PB |
3940 | case MSR_IA32_TSX_CTRL: |
3941 | env->tsx_ctrl = msrs[i].data; | |
3942 | break; | |
cfeea0c0 KRW |
3943 | case MSR_VIRT_SSBD: |
3944 | env->virt_ssbd = msrs[i].data; | |
3945 | break; | |
b77146e9 CP |
3946 | case MSR_IA32_RTIT_CTL: |
3947 | env->msr_rtit_ctrl = msrs[i].data; | |
3948 | break; | |
3949 | case MSR_IA32_RTIT_STATUS: | |
3950 | env->msr_rtit_status = msrs[i].data; | |
3951 | break; | |
3952 | case MSR_IA32_RTIT_OUTPUT_BASE: | |
3953 | env->msr_rtit_output_base = msrs[i].data; | |
3954 | break; | |
3955 | case MSR_IA32_RTIT_OUTPUT_MASK: | |
3956 | env->msr_rtit_output_mask = msrs[i].data; | |
3957 | break; | |
3958 | case MSR_IA32_RTIT_CR3_MATCH: | |
3959 | env->msr_rtit_cr3_match = msrs[i].data; | |
3960 | break; | |
3961 | case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: | |
3962 | env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data; | |
3963 | break; | |
db888065 SC |
3964 | case MSR_IA32_SGXLEPUBKEYHASH0 ... MSR_IA32_SGXLEPUBKEYHASH3: |
3965 | env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH0] = | |
3966 | msrs[i].data; | |
3967 | break; | |
05330448 AL |
3968 | } |
3969 | } | |
3970 | ||
3971 | return 0; | |
3972 | } | |
3973 | ||
1bc22652 | 3974 | static int kvm_put_mp_state(X86CPU *cpu) |
9bdbe550 | 3975 | { |
1bc22652 | 3976 | struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state }; |
9bdbe550 | 3977 | |
1bc22652 | 3978 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state); |
9bdbe550 HB |
3979 | } |
3980 | ||
23d02d9b | 3981 | static int kvm_get_mp_state(X86CPU *cpu) |
9bdbe550 | 3982 | { |
259186a7 | 3983 | CPUState *cs = CPU(cpu); |
23d02d9b | 3984 | CPUX86State *env = &cpu->env; |
9bdbe550 HB |
3985 | struct kvm_mp_state mp_state; |
3986 | int ret; | |
3987 | ||
259186a7 | 3988 | ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state); |
9bdbe550 HB |
3989 | if (ret < 0) { |
3990 | return ret; | |
3991 | } | |
3992 | env->mp_state = mp_state.mp_state; | |
c14750e8 | 3993 | if (kvm_irqchip_in_kernel()) { |
259186a7 | 3994 | cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED); |
c14750e8 | 3995 | } |
9bdbe550 HB |
3996 | return 0; |
3997 | } | |
3998 | ||
1bc22652 | 3999 | static int kvm_get_apic(X86CPU *cpu) |
680c1c6f | 4000 | { |
02e51483 | 4001 | DeviceState *apic = cpu->apic_state; |
680c1c6f JK |
4002 | struct kvm_lapic_state kapic; |
4003 | int ret; | |
4004 | ||
3d4b2649 | 4005 | if (apic && kvm_irqchip_in_kernel()) { |
1bc22652 | 4006 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic); |
680c1c6f JK |
4007 | if (ret < 0) { |
4008 | return ret; | |
4009 | } | |
4010 | ||
4011 | kvm_get_apic_state(apic, &kapic); | |
4012 | } | |
4013 | return 0; | |
4014 | } | |
4015 | ||
1bc22652 | 4016 | static int kvm_put_vcpu_events(X86CPU *cpu, int level) |
a0fb002c | 4017 | { |
fc12d72e | 4018 | CPUState *cs = CPU(cpu); |
1bc22652 | 4019 | CPUX86State *env = &cpu->env; |
076796f8 | 4020 | struct kvm_vcpu_events events = {}; |
a0fb002c JK |
4021 | |
4022 | if (!kvm_has_vcpu_events()) { | |
4023 | return 0; | |
4024 | } | |
4025 | ||
fd13f23b LA |
4026 | events.flags = 0; |
4027 | ||
4028 | if (has_exception_payload) { | |
4029 | events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD; | |
4030 | events.exception.pending = env->exception_pending; | |
4031 | events.exception_has_payload = env->exception_has_payload; | |
4032 | events.exception_payload = env->exception_payload; | |
4033 | } | |
4034 | events.exception.nr = env->exception_nr; | |
4035 | events.exception.injected = env->exception_injected; | |
a0fb002c JK |
4036 | events.exception.has_error_code = env->has_error_code; |
4037 | events.exception.error_code = env->error_code; | |
4038 | ||
4039 | events.interrupt.injected = (env->interrupt_injected >= 0); | |
4040 | events.interrupt.nr = env->interrupt_injected; | |
4041 | events.interrupt.soft = env->soft_interrupt; | |
4042 | ||
4043 | events.nmi.injected = env->nmi_injected; | |
4044 | events.nmi.pending = env->nmi_pending; | |
4045 | events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK); | |
4046 | ||
4047 | events.sipi_vector = env->sipi_vector; | |
4048 | ||
fc12d72e PB |
4049 | if (has_msr_smbase) { |
4050 | events.smi.smm = !!(env->hflags & HF_SMM_MASK); | |
4051 | events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK); | |
4052 | if (kvm_irqchip_in_kernel()) { | |
4053 | /* As soon as these are moved to the kernel, remove them | |
4054 | * from cs->interrupt_request. | |
4055 | */ | |
4056 | events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI; | |
4057 | events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT; | |
4058 | cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI); | |
4059 | } else { | |
4060 | /* Keep these in cs->interrupt_request. */ | |
4061 | events.smi.pending = 0; | |
4062 | events.smi.latched_init = 0; | |
4063 | } | |
fc3a1fd7 DDAG |
4064 | /* Stop SMI delivery on old machine types to avoid a reboot |
4065 | * on an inward migration of an old VM. | |
4066 | */ | |
4067 | if (!cpu->kvm_no_smi_migration) { | |
4068 | events.flags |= KVM_VCPUEVENT_VALID_SMM; | |
4069 | } | |
fc12d72e PB |
4070 | } |
4071 | ||
ea643051 | 4072 | if (level >= KVM_PUT_RESET_STATE) { |
4fadfa00 PH |
4073 | events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING; |
4074 | if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) { | |
4075 | events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR; | |
4076 | } | |
ea643051 | 4077 | } |
aee028b9 | 4078 | |
1bc22652 | 4079 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events); |
a0fb002c JK |
4080 | } |
4081 | ||
1bc22652 | 4082 | static int kvm_get_vcpu_events(X86CPU *cpu) |
a0fb002c | 4083 | { |
1bc22652 | 4084 | CPUX86State *env = &cpu->env; |
a0fb002c JK |
4085 | struct kvm_vcpu_events events; |
4086 | int ret; | |
4087 | ||
4088 | if (!kvm_has_vcpu_events()) { | |
4089 | return 0; | |
4090 | } | |
4091 | ||
fc12d72e | 4092 | memset(&events, 0, sizeof(events)); |
1bc22652 | 4093 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events); |
a0fb002c JK |
4094 | if (ret < 0) { |
4095 | return ret; | |
4096 | } | |
fd13f23b LA |
4097 | |
4098 | if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) { | |
4099 | env->exception_pending = events.exception.pending; | |
4100 | env->exception_has_payload = events.exception_has_payload; | |
4101 | env->exception_payload = events.exception_payload; | |
4102 | } else { | |
4103 | env->exception_pending = 0; | |
4104 | env->exception_has_payload = false; | |
4105 | } | |
4106 | env->exception_injected = events.exception.injected; | |
4107 | env->exception_nr = | |
4108 | (env->exception_pending || env->exception_injected) ? | |
4109 | events.exception.nr : -1; | |
a0fb002c JK |
4110 | env->has_error_code = events.exception.has_error_code; |
4111 | env->error_code = events.exception.error_code; | |
4112 | ||
4113 | env->interrupt_injected = | |
4114 | events.interrupt.injected ? events.interrupt.nr : -1; | |
4115 | env->soft_interrupt = events.interrupt.soft; | |
4116 | ||
4117 | env->nmi_injected = events.nmi.injected; | |
4118 | env->nmi_pending = events.nmi.pending; | |
4119 | if (events.nmi.masked) { | |
4120 | env->hflags2 |= HF2_NMI_MASK; | |
4121 | } else { | |
4122 | env->hflags2 &= ~HF2_NMI_MASK; | |
4123 | } | |
4124 | ||
fc12d72e PB |
4125 | if (events.flags & KVM_VCPUEVENT_VALID_SMM) { |
4126 | if (events.smi.smm) { | |
4127 | env->hflags |= HF_SMM_MASK; | |
4128 | } else { | |
4129 | env->hflags &= ~HF_SMM_MASK; | |
4130 | } | |
4131 | if (events.smi.pending) { | |
4132 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); | |
4133 | } else { | |
4134 | cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI); | |
4135 | } | |
4136 | if (events.smi.smm_inside_nmi) { | |
4137 | env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK; | |
4138 | } else { | |
4139 | env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK; | |
4140 | } | |
4141 | if (events.smi.latched_init) { | |
4142 | cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); | |
4143 | } else { | |
4144 | cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT); | |
4145 | } | |
4146 | } | |
4147 | ||
a0fb002c | 4148 | env->sipi_vector = events.sipi_vector; |
a0fb002c JK |
4149 | |
4150 | return 0; | |
4151 | } | |
4152 | ||
1bc22652 | 4153 | static int kvm_guest_debug_workarounds(X86CPU *cpu) |
b0b1d690 | 4154 | { |
ed2803da | 4155 | CPUState *cs = CPU(cpu); |
1bc22652 | 4156 | CPUX86State *env = &cpu->env; |
b0b1d690 | 4157 | int ret = 0; |
b0b1d690 JK |
4158 | unsigned long reinject_trap = 0; |
4159 | ||
4160 | if (!kvm_has_vcpu_events()) { | |
fd13f23b | 4161 | if (env->exception_nr == EXCP01_DB) { |
b0b1d690 | 4162 | reinject_trap = KVM_GUESTDBG_INJECT_DB; |
37936ac7 | 4163 | } else if (env->exception_injected == EXCP03_INT3) { |
b0b1d690 JK |
4164 | reinject_trap = KVM_GUESTDBG_INJECT_BP; |
4165 | } | |
fd13f23b | 4166 | kvm_reset_exception(env); |
b0b1d690 JK |
4167 | } |
4168 | ||
4169 | /* | |
4170 | * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF | |
4171 | * injected via SET_GUEST_DEBUG while updating GP regs. Work around this | |
4172 | * by updating the debug state once again if single-stepping is on. | |
4173 | * Another reason to call kvm_update_guest_debug here is a pending debug | |
4174 | * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to | |
4175 | * reinject them via SET_GUEST_DEBUG. | |
4176 | */ | |
4177 | if (reinject_trap || | |
ed2803da | 4178 | (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) { |
38e478ec | 4179 | ret = kvm_update_guest_debug(cs, reinject_trap); |
b0b1d690 | 4180 | } |
b0b1d690 JK |
4181 | return ret; |
4182 | } | |
4183 | ||
1bc22652 | 4184 | static int kvm_put_debugregs(X86CPU *cpu) |
ff44f1a3 | 4185 | { |
1bc22652 | 4186 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
4187 | struct kvm_debugregs dbgregs; |
4188 | int i; | |
4189 | ||
4190 | if (!kvm_has_debugregs()) { | |
4191 | return 0; | |
4192 | } | |
4193 | ||
1f670a95 | 4194 | memset(&dbgregs, 0, sizeof(dbgregs)); |
ff44f1a3 JK |
4195 | for (i = 0; i < 4; i++) { |
4196 | dbgregs.db[i] = env->dr[i]; | |
4197 | } | |
4198 | dbgregs.dr6 = env->dr[6]; | |
4199 | dbgregs.dr7 = env->dr[7]; | |
4200 | dbgregs.flags = 0; | |
4201 | ||
1bc22652 | 4202 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs); |
ff44f1a3 JK |
4203 | } |
4204 | ||
1bc22652 | 4205 | static int kvm_get_debugregs(X86CPU *cpu) |
ff44f1a3 | 4206 | { |
1bc22652 | 4207 | CPUX86State *env = &cpu->env; |
ff44f1a3 JK |
4208 | struct kvm_debugregs dbgregs; |
4209 | int i, ret; | |
4210 | ||
4211 | if (!kvm_has_debugregs()) { | |
4212 | return 0; | |
4213 | } | |
4214 | ||
1bc22652 | 4215 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs); |
ff44f1a3 | 4216 | if (ret < 0) { |
b9bec74b | 4217 | return ret; |
ff44f1a3 JK |
4218 | } |
4219 | for (i = 0; i < 4; i++) { | |
4220 | env->dr[i] = dbgregs.db[i]; | |
4221 | } | |
4222 | env->dr[4] = env->dr[6] = dbgregs.dr6; | |
4223 | env->dr[5] = env->dr[7] = dbgregs.dr7; | |
ff44f1a3 JK |
4224 | |
4225 | return 0; | |
4226 | } | |
4227 | ||
ebbfef2f LA |
4228 | static int kvm_put_nested_state(X86CPU *cpu) |
4229 | { | |
4230 | CPUX86State *env = &cpu->env; | |
4231 | int max_nested_state_len = kvm_max_nested_state_length(); | |
4232 | ||
1e44f3ab | 4233 | if (!env->nested_state) { |
ebbfef2f LA |
4234 | return 0; |
4235 | } | |
4236 | ||
b16c0e20 PB |
4237 | /* |
4238 | * Copy flags that are affected by reset from env->hflags and env->hflags2. | |
4239 | */ | |
4240 | if (env->hflags & HF_GUEST_MASK) { | |
4241 | env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE; | |
4242 | } else { | |
4243 | env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE; | |
4244 | } | |
0baa4b44 VK |
4245 | |
4246 | /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */ | |
4247 | if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) { | |
b16c0e20 PB |
4248 | env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET; |
4249 | } else { | |
4250 | env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET; | |
4251 | } | |
4252 | ||
ebbfef2f LA |
4253 | assert(env->nested_state->size <= max_nested_state_len); |
4254 | return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state); | |
4255 | } | |
4256 | ||
4257 | static int kvm_get_nested_state(X86CPU *cpu) | |
4258 | { | |
4259 | CPUX86State *env = &cpu->env; | |
4260 | int max_nested_state_len = kvm_max_nested_state_length(); | |
4261 | int ret; | |
4262 | ||
1e44f3ab | 4263 | if (!env->nested_state) { |
ebbfef2f LA |
4264 | return 0; |
4265 | } | |
4266 | ||
4267 | /* | |
4268 | * It is possible that migration restored a smaller size into | |
4269 | * nested_state->hdr.size than what our kernel support. | |
4270 | * We preserve migration origin nested_state->hdr.size for | |
4271 | * call to KVM_SET_NESTED_STATE but wish that our next call | |
4272 | * to KVM_GET_NESTED_STATE will use max size our kernel support. | |
4273 | */ | |
4274 | env->nested_state->size = max_nested_state_len; | |
4275 | ||
4276 | ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state); | |
4277 | if (ret < 0) { | |
4278 | return ret; | |
4279 | } | |
4280 | ||
b16c0e20 PB |
4281 | /* |
4282 | * Copy flags that are affected by reset to env->hflags and env->hflags2. | |
4283 | */ | |
ebbfef2f LA |
4284 | if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) { |
4285 | env->hflags |= HF_GUEST_MASK; | |
4286 | } else { | |
4287 | env->hflags &= ~HF_GUEST_MASK; | |
4288 | } | |
0baa4b44 VK |
4289 | |
4290 | /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */ | |
4291 | if (cpu_has_svm(env)) { | |
4292 | if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) { | |
4293 | env->hflags2 |= HF2_GIF_MASK; | |
4294 | } else { | |
4295 | env->hflags2 &= ~HF2_GIF_MASK; | |
4296 | } | |
b16c0e20 | 4297 | } |
ebbfef2f LA |
4298 | |
4299 | return ret; | |
4300 | } | |
4301 | ||
20d695a9 | 4302 | int kvm_arch_put_registers(CPUState *cpu, int level) |
05330448 | 4303 | { |
20d695a9 | 4304 | X86CPU *x86_cpu = X86_CPU(cpu); |
05330448 AL |
4305 | int ret; |
4306 | ||
2fa45344 | 4307 | assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); |
dbaa07c4 | 4308 | |
b16c0e20 | 4309 | /* must be before kvm_put_nested_state so that EFER.SVME is set */ |
8f515d38 | 4310 | ret = has_sregs2 ? kvm_put_sregs2(x86_cpu) : kvm_put_sregs(x86_cpu); |
b16c0e20 PB |
4311 | if (ret < 0) { |
4312 | return ret; | |
4313 | } | |
4314 | ||
48e1a45c | 4315 | if (level >= KVM_PUT_RESET_STATE) { |
bec7156a JK |
4316 | ret = kvm_put_nested_state(x86_cpu); |
4317 | if (ret < 0) { | |
4318 | return ret; | |
4319 | } | |
4320 | ||
6bdf863d JK |
4321 | ret = kvm_put_msr_feature_control(x86_cpu); |
4322 | if (ret < 0) { | |
4323 | return ret; | |
4324 | } | |
4325 | } | |
4326 | ||
36f96c4b HZ |
4327 | if (level == KVM_PUT_FULL_STATE) { |
4328 | /* We don't check for kvm_arch_set_tsc_khz() errors here, | |
4329 | * because TSC frequency mismatch shouldn't abort migration, | |
4330 | * unless the user explicitly asked for a more strict TSC | |
4331 | * setting (e.g. using an explicit "tsc-freq" option). | |
4332 | */ | |
4333 | kvm_arch_set_tsc_khz(cpu); | |
4334 | } | |
4335 | ||
1bc22652 | 4336 | ret = kvm_getput_regs(x86_cpu, 1); |
b9bec74b | 4337 | if (ret < 0) { |
05330448 | 4338 | return ret; |
b9bec74b | 4339 | } |
1bc22652 | 4340 | ret = kvm_put_xsave(x86_cpu); |
b9bec74b | 4341 | if (ret < 0) { |
f1665b21 | 4342 | return ret; |
b9bec74b | 4343 | } |
1bc22652 | 4344 | ret = kvm_put_xcrs(x86_cpu); |
b9bec74b | 4345 | if (ret < 0) { |
05330448 | 4346 | return ret; |
b9bec74b | 4347 | } |
ab443475 | 4348 | /* must be before kvm_put_msrs */ |
1bc22652 | 4349 | ret = kvm_inject_mce_oldstyle(x86_cpu); |
ab443475 JK |
4350 | if (ret < 0) { |
4351 | return ret; | |
4352 | } | |
1bc22652 | 4353 | ret = kvm_put_msrs(x86_cpu, level); |
b9bec74b | 4354 | if (ret < 0) { |
05330448 | 4355 | return ret; |
b9bec74b | 4356 | } |
4fadfa00 PH |
4357 | ret = kvm_put_vcpu_events(x86_cpu, level); |
4358 | if (ret < 0) { | |
4359 | return ret; | |
4360 | } | |
ea643051 | 4361 | if (level >= KVM_PUT_RESET_STATE) { |
1bc22652 | 4362 | ret = kvm_put_mp_state(x86_cpu); |
b9bec74b | 4363 | if (ret < 0) { |
680c1c6f JK |
4364 | return ret; |
4365 | } | |
ea643051 | 4366 | } |
7477cd38 MT |
4367 | |
4368 | ret = kvm_put_tscdeadline_msr(x86_cpu); | |
4369 | if (ret < 0) { | |
4370 | return ret; | |
4371 | } | |
1bc22652 | 4372 | ret = kvm_put_debugregs(x86_cpu); |
b9bec74b | 4373 | if (ret < 0) { |
b0b1d690 | 4374 | return ret; |
b9bec74b | 4375 | } |
b0b1d690 | 4376 | /* must be last */ |
1bc22652 | 4377 | ret = kvm_guest_debug_workarounds(x86_cpu); |
b9bec74b | 4378 | if (ret < 0) { |
ff44f1a3 | 4379 | return ret; |
b9bec74b | 4380 | } |
05330448 AL |
4381 | return 0; |
4382 | } | |
4383 | ||
20d695a9 | 4384 | int kvm_arch_get_registers(CPUState *cs) |
05330448 | 4385 | { |
20d695a9 | 4386 | X86CPU *cpu = X86_CPU(cs); |
05330448 AL |
4387 | int ret; |
4388 | ||
20d695a9 | 4389 | assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs)); |
dbaa07c4 | 4390 | |
4fadfa00 | 4391 | ret = kvm_get_vcpu_events(cpu); |
b9bec74b | 4392 | if (ret < 0) { |
f4f1110e | 4393 | goto out; |
b9bec74b | 4394 | } |
4fadfa00 PH |
4395 | /* |
4396 | * KVM_GET_MPSTATE can modify CS and RIP, call it before | |
4397 | * KVM_GET_REGS and KVM_GET_SREGS. | |
4398 | */ | |
4399 | ret = kvm_get_mp_state(cpu); | |
b9bec74b | 4400 | if (ret < 0) { |
f4f1110e | 4401 | goto out; |
b9bec74b | 4402 | } |
4fadfa00 | 4403 | ret = kvm_getput_regs(cpu, 0); |
b9bec74b | 4404 | if (ret < 0) { |
f4f1110e | 4405 | goto out; |
b9bec74b | 4406 | } |
4fadfa00 | 4407 | ret = kvm_get_xsave(cpu); |
b9bec74b | 4408 | if (ret < 0) { |
f4f1110e | 4409 | goto out; |
b9bec74b | 4410 | } |
4fadfa00 | 4411 | ret = kvm_get_xcrs(cpu); |
b9bec74b | 4412 | if (ret < 0) { |
f4f1110e | 4413 | goto out; |
b9bec74b | 4414 | } |
8f515d38 | 4415 | ret = has_sregs2 ? kvm_get_sregs2(cpu) : kvm_get_sregs(cpu); |
b9bec74b | 4416 | if (ret < 0) { |
f4f1110e | 4417 | goto out; |
b9bec74b | 4418 | } |
4fadfa00 | 4419 | ret = kvm_get_msrs(cpu); |
680c1c6f | 4420 | if (ret < 0) { |
f4f1110e | 4421 | goto out; |
680c1c6f | 4422 | } |
4fadfa00 | 4423 | ret = kvm_get_apic(cpu); |
b9bec74b | 4424 | if (ret < 0) { |
f4f1110e | 4425 | goto out; |
b9bec74b | 4426 | } |
1bc22652 | 4427 | ret = kvm_get_debugregs(cpu); |
b9bec74b | 4428 | if (ret < 0) { |
f4f1110e | 4429 | goto out; |
b9bec74b | 4430 | } |
ebbfef2f LA |
4431 | ret = kvm_get_nested_state(cpu); |
4432 | if (ret < 0) { | |
4433 | goto out; | |
4434 | } | |
f4f1110e RH |
4435 | ret = 0; |
4436 | out: | |
4437 | cpu_sync_bndcs_hflags(&cpu->env); | |
4438 | return ret; | |
05330448 AL |
4439 | } |
4440 | ||
20d695a9 | 4441 | void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 4442 | { |
20d695a9 AF |
4443 | X86CPU *x86_cpu = X86_CPU(cpu); |
4444 | CPUX86State *env = &x86_cpu->env; | |
ce377af3 JK |
4445 | int ret; |
4446 | ||
276ce815 | 4447 | /* Inject NMI */ |
fc12d72e PB |
4448 | if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { |
4449 | if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { | |
4450 | qemu_mutex_lock_iothread(); | |
4451 | cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; | |
4452 | qemu_mutex_unlock_iothread(); | |
4453 | DPRINTF("injected NMI\n"); | |
4454 | ret = kvm_vcpu_ioctl(cpu, KVM_NMI); | |
4455 | if (ret < 0) { | |
4456 | fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n", | |
4457 | strerror(-ret)); | |
4458 | } | |
4459 | } | |
4460 | if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { | |
4461 | qemu_mutex_lock_iothread(); | |
4462 | cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; | |
4463 | qemu_mutex_unlock_iothread(); | |
4464 | DPRINTF("injected SMI\n"); | |
4465 | ret = kvm_vcpu_ioctl(cpu, KVM_SMI); | |
4466 | if (ret < 0) { | |
4467 | fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n", | |
4468 | strerror(-ret)); | |
4469 | } | |
ce377af3 | 4470 | } |
276ce815 LJ |
4471 | } |
4472 | ||
15eafc2e | 4473 | if (!kvm_pic_in_kernel()) { |
4b8523ee JK |
4474 | qemu_mutex_lock_iothread(); |
4475 | } | |
4476 | ||
e0723c45 PB |
4477 | /* Force the VCPU out of its inner loop to process any INIT requests |
4478 | * or (for userspace APIC, but it is cheap to combine the checks here) | |
4479 | * pending TPR access reports. | |
4480 | */ | |
4481 | if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { | |
fc12d72e PB |
4482 | if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && |
4483 | !(env->hflags & HF_SMM_MASK)) { | |
4484 | cpu->exit_request = 1; | |
4485 | } | |
4486 | if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { | |
4487 | cpu->exit_request = 1; | |
4488 | } | |
e0723c45 | 4489 | } |
05330448 | 4490 | |
15eafc2e | 4491 | if (!kvm_pic_in_kernel()) { |
db1669bc JK |
4492 | /* Try to inject an interrupt if the guest can accept it */ |
4493 | if (run->ready_for_interrupt_injection && | |
259186a7 | 4494 | (cpu->interrupt_request & CPU_INTERRUPT_HARD) && |
db1669bc JK |
4495 | (env->eflags & IF_MASK)) { |
4496 | int irq; | |
4497 | ||
259186a7 | 4498 | cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; |
db1669bc JK |
4499 | irq = cpu_get_pic_interrupt(env); |
4500 | if (irq >= 0) { | |
4501 | struct kvm_interrupt intr; | |
4502 | ||
4503 | intr.irq = irq; | |
db1669bc | 4504 | DPRINTF("injected interrupt %d\n", irq); |
1bc22652 | 4505 | ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr); |
ce377af3 JK |
4506 | if (ret < 0) { |
4507 | fprintf(stderr, | |
4508 | "KVM: injection failed, interrupt lost (%s)\n", | |
4509 | strerror(-ret)); | |
4510 | } | |
db1669bc JK |
4511 | } |
4512 | } | |
05330448 | 4513 | |
db1669bc JK |
4514 | /* If we have an interrupt but the guest is not ready to receive an |
4515 | * interrupt, request an interrupt window exit. This will | |
4516 | * cause a return to userspace as soon as the guest is ready to | |
4517 | * receive interrupts. */ | |
259186a7 | 4518 | if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { |
db1669bc JK |
4519 | run->request_interrupt_window = 1; |
4520 | } else { | |
4521 | run->request_interrupt_window = 0; | |
4522 | } | |
4523 | ||
4524 | DPRINTF("setting tpr\n"); | |
02e51483 | 4525 | run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state); |
4b8523ee JK |
4526 | |
4527 | qemu_mutex_unlock_iothread(); | |
db1669bc | 4528 | } |
05330448 AL |
4529 | } |
4530 | ||
035d1ef2 CQ |
4531 | static void kvm_rate_limit_on_bus_lock(void) |
4532 | { | |
4533 | uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1); | |
4534 | ||
4535 | if (delay_ns) { | |
4536 | g_usleep(delay_ns / SCALE_US); | |
4537 | } | |
4538 | } | |
4539 | ||
4c663752 | 4540 | MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run) |
05330448 | 4541 | { |
20d695a9 AF |
4542 | X86CPU *x86_cpu = X86_CPU(cpu); |
4543 | CPUX86State *env = &x86_cpu->env; | |
4544 | ||
fc12d72e PB |
4545 | if (run->flags & KVM_RUN_X86_SMM) { |
4546 | env->hflags |= HF_SMM_MASK; | |
4547 | } else { | |
f5c052b9 | 4548 | env->hflags &= ~HF_SMM_MASK; |
fc12d72e | 4549 | } |
b9bec74b | 4550 | if (run->if_flag) { |
05330448 | 4551 | env->eflags |= IF_MASK; |
b9bec74b | 4552 | } else { |
05330448 | 4553 | env->eflags &= ~IF_MASK; |
b9bec74b | 4554 | } |
035d1ef2 CQ |
4555 | if (run->flags & KVM_RUN_X86_BUS_LOCK) { |
4556 | kvm_rate_limit_on_bus_lock(); | |
4557 | } | |
4b8523ee JK |
4558 | |
4559 | /* We need to protect the apic state against concurrent accesses from | |
4560 | * different threads in case the userspace irqchip is used. */ | |
4561 | if (!kvm_irqchip_in_kernel()) { | |
4562 | qemu_mutex_lock_iothread(); | |
4563 | } | |
02e51483 CF |
4564 | cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8); |
4565 | cpu_set_apic_base(x86_cpu->apic_state, run->apic_base); | |
4b8523ee JK |
4566 | if (!kvm_irqchip_in_kernel()) { |
4567 | qemu_mutex_unlock_iothread(); | |
4568 | } | |
f794aa4a | 4569 | return cpu_get_mem_attrs(env); |
05330448 AL |
4570 | } |
4571 | ||
20d695a9 | 4572 | int kvm_arch_process_async_events(CPUState *cs) |
0af691d7 | 4573 | { |
20d695a9 AF |
4574 | X86CPU *cpu = X86_CPU(cs); |
4575 | CPUX86State *env = &cpu->env; | |
232fc23b | 4576 | |
259186a7 | 4577 | if (cs->interrupt_request & CPU_INTERRUPT_MCE) { |
ab443475 JK |
4578 | /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ |
4579 | assert(env->mcg_cap); | |
4580 | ||
259186a7 | 4581 | cs->interrupt_request &= ~CPU_INTERRUPT_MCE; |
ab443475 | 4582 | |
dd1750d7 | 4583 | kvm_cpu_synchronize_state(cs); |
ab443475 | 4584 | |
fd13f23b | 4585 | if (env->exception_nr == EXCP08_DBLE) { |
ab443475 | 4586 | /* this means triple fault */ |
cf83f140 | 4587 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
fcd7d003 | 4588 | cs->exit_request = 1; |
ab443475 JK |
4589 | return 0; |
4590 | } | |
fd13f23b | 4591 | kvm_queue_exception(env, EXCP12_MCHK, 0, 0); |
ab443475 JK |
4592 | env->has_error_code = 0; |
4593 | ||
259186a7 | 4594 | cs->halted = 0; |
ab443475 JK |
4595 | if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) { |
4596 | env->mp_state = KVM_MP_STATE_RUNNABLE; | |
4597 | } | |
4598 | } | |
4599 | ||
fc12d72e PB |
4600 | if ((cs->interrupt_request & CPU_INTERRUPT_INIT) && |
4601 | !(env->hflags & HF_SMM_MASK)) { | |
e0723c45 PB |
4602 | kvm_cpu_synchronize_state(cs); |
4603 | do_cpu_init(cpu); | |
4604 | } | |
4605 | ||
db1669bc JK |
4606 | if (kvm_irqchip_in_kernel()) { |
4607 | return 0; | |
4608 | } | |
4609 | ||
259186a7 AF |
4610 | if (cs->interrupt_request & CPU_INTERRUPT_POLL) { |
4611 | cs->interrupt_request &= ~CPU_INTERRUPT_POLL; | |
02e51483 | 4612 | apic_poll_irq(cpu->apic_state); |
5d62c43a | 4613 | } |
259186a7 | 4614 | if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
4601f7b0 | 4615 | (env->eflags & IF_MASK)) || |
259186a7 AF |
4616 | (cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
4617 | cs->halted = 0; | |
6792a57b | 4618 | } |
259186a7 | 4619 | if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { |
dd1750d7 | 4620 | kvm_cpu_synchronize_state(cs); |
232fc23b | 4621 | do_cpu_sipi(cpu); |
0af691d7 | 4622 | } |
259186a7 AF |
4623 | if (cs->interrupt_request & CPU_INTERRUPT_TPR) { |
4624 | cs->interrupt_request &= ~CPU_INTERRUPT_TPR; | |
dd1750d7 | 4625 | kvm_cpu_synchronize_state(cs); |
02e51483 | 4626 | apic_handle_tpr_access_report(cpu->apic_state, env->eip, |
d362e757 JK |
4627 | env->tpr_access_type); |
4628 | } | |
0af691d7 | 4629 | |
259186a7 | 4630 | return cs->halted; |
0af691d7 MT |
4631 | } |
4632 | ||
839b5630 | 4633 | static int kvm_handle_halt(X86CPU *cpu) |
05330448 | 4634 | { |
259186a7 | 4635 | CPUState *cs = CPU(cpu); |
839b5630 AF |
4636 | CPUX86State *env = &cpu->env; |
4637 | ||
259186a7 | 4638 | if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && |
05330448 | 4639 | (env->eflags & IF_MASK)) && |
259186a7 AF |
4640 | !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { |
4641 | cs->halted = 1; | |
bb4ea393 | 4642 | return EXCP_HLT; |
05330448 AL |
4643 | } |
4644 | ||
bb4ea393 | 4645 | return 0; |
05330448 AL |
4646 | } |
4647 | ||
f7575c96 | 4648 | static int kvm_handle_tpr_access(X86CPU *cpu) |
d362e757 | 4649 | { |
f7575c96 AF |
4650 | CPUState *cs = CPU(cpu); |
4651 | struct kvm_run *run = cs->kvm_run; | |
d362e757 | 4652 | |
02e51483 | 4653 | apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip, |
d362e757 JK |
4654 | run->tpr_access.is_write ? TPR_ACCESS_WRITE |
4655 | : TPR_ACCESS_READ); | |
4656 | return 1; | |
4657 | } | |
4658 | ||
f17ec444 | 4659 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 | 4660 | { |
38972938 | 4661 | static const uint8_t int3 = 0xcc; |
64bf3f4e | 4662 | |
f17ec444 AF |
4663 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) || |
4664 | cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) { | |
e22a25c9 | 4665 | return -EINVAL; |
b9bec74b | 4666 | } |
e22a25c9 AL |
4667 | return 0; |
4668 | } | |
4669 | ||
f17ec444 | 4670 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp) |
e22a25c9 AL |
4671 | { |
4672 | uint8_t int3; | |
4673 | ||
c6986f16 PB |
4674 | if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) { |
4675 | return -EINVAL; | |
4676 | } | |
4677 | if (int3 != 0xcc) { | |
4678 | return 0; | |
4679 | } | |
4680 | if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) { | |
e22a25c9 | 4681 | return -EINVAL; |
b9bec74b | 4682 | } |
e22a25c9 AL |
4683 | return 0; |
4684 | } | |
4685 | ||
4686 | static struct { | |
4687 | target_ulong addr; | |
4688 | int len; | |
4689 | int type; | |
4690 | } hw_breakpoint[4]; | |
4691 | ||
4692 | static int nb_hw_breakpoint; | |
4693 | ||
4694 | static int find_hw_breakpoint(target_ulong addr, int len, int type) | |
4695 | { | |
4696 | int n; | |
4697 | ||
b9bec74b | 4698 | for (n = 0; n < nb_hw_breakpoint; n++) { |
e22a25c9 | 4699 | if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type && |
b9bec74b | 4700 | (hw_breakpoint[n].len == len || len == -1)) { |
e22a25c9 | 4701 | return n; |
b9bec74b JK |
4702 | } |
4703 | } | |
e22a25c9 AL |
4704 | return -1; |
4705 | } | |
4706 | ||
4707 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
4708 | target_ulong len, int type) | |
4709 | { | |
4710 | switch (type) { | |
4711 | case GDB_BREAKPOINT_HW: | |
4712 | len = 1; | |
4713 | break; | |
4714 | case GDB_WATCHPOINT_WRITE: | |
4715 | case GDB_WATCHPOINT_ACCESS: | |
4716 | switch (len) { | |
4717 | case 1: | |
4718 | break; | |
4719 | case 2: | |
4720 | case 4: | |
4721 | case 8: | |
b9bec74b | 4722 | if (addr & (len - 1)) { |
e22a25c9 | 4723 | return -EINVAL; |
b9bec74b | 4724 | } |
e22a25c9 AL |
4725 | break; |
4726 | default: | |
4727 | return -EINVAL; | |
4728 | } | |
4729 | break; | |
4730 | default: | |
4731 | return -ENOSYS; | |
4732 | } | |
4733 | ||
b9bec74b | 4734 | if (nb_hw_breakpoint == 4) { |
e22a25c9 | 4735 | return -ENOBUFS; |
b9bec74b JK |
4736 | } |
4737 | if (find_hw_breakpoint(addr, len, type) >= 0) { | |
e22a25c9 | 4738 | return -EEXIST; |
b9bec74b | 4739 | } |
e22a25c9 AL |
4740 | hw_breakpoint[nb_hw_breakpoint].addr = addr; |
4741 | hw_breakpoint[nb_hw_breakpoint].len = len; | |
4742 | hw_breakpoint[nb_hw_breakpoint].type = type; | |
4743 | nb_hw_breakpoint++; | |
4744 | ||
4745 | return 0; | |
4746 | } | |
4747 | ||
4748 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
4749 | target_ulong len, int type) | |
4750 | { | |
4751 | int n; | |
4752 | ||
4753 | n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type); | |
b9bec74b | 4754 | if (n < 0) { |
e22a25c9 | 4755 | return -ENOENT; |
b9bec74b | 4756 | } |
e22a25c9 AL |
4757 | nb_hw_breakpoint--; |
4758 | hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint]; | |
4759 | ||
4760 | return 0; | |
4761 | } | |
4762 | ||
4763 | void kvm_arch_remove_all_hw_breakpoints(void) | |
4764 | { | |
4765 | nb_hw_breakpoint = 0; | |
4766 | } | |
4767 | ||
4768 | static CPUWatchpoint hw_watchpoint; | |
4769 | ||
a60f24b5 | 4770 | static int kvm_handle_debug(X86CPU *cpu, |
48405526 | 4771 | struct kvm_debug_exit_arch *arch_info) |
e22a25c9 | 4772 | { |
ed2803da | 4773 | CPUState *cs = CPU(cpu); |
a60f24b5 | 4774 | CPUX86State *env = &cpu->env; |
f2574737 | 4775 | int ret = 0; |
e22a25c9 AL |
4776 | int n; |
4777 | ||
37936ac7 LA |
4778 | if (arch_info->exception == EXCP01_DB) { |
4779 | if (arch_info->dr6 & DR6_BS) { | |
ed2803da | 4780 | if (cs->singlestep_enabled) { |
f2574737 | 4781 | ret = EXCP_DEBUG; |
b9bec74b | 4782 | } |
e22a25c9 | 4783 | } else { |
b9bec74b JK |
4784 | for (n = 0; n < 4; n++) { |
4785 | if (arch_info->dr6 & (1 << n)) { | |
e22a25c9 AL |
4786 | switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) { |
4787 | case 0x0: | |
f2574737 | 4788 | ret = EXCP_DEBUG; |
e22a25c9 AL |
4789 | break; |
4790 | case 0x1: | |
f2574737 | 4791 | ret = EXCP_DEBUG; |
ff4700b0 | 4792 | cs->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
4793 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
4794 | hw_watchpoint.flags = BP_MEM_WRITE; | |
4795 | break; | |
4796 | case 0x3: | |
f2574737 | 4797 | ret = EXCP_DEBUG; |
ff4700b0 | 4798 | cs->watchpoint_hit = &hw_watchpoint; |
e22a25c9 AL |
4799 | hw_watchpoint.vaddr = hw_breakpoint[n].addr; |
4800 | hw_watchpoint.flags = BP_MEM_ACCESS; | |
4801 | break; | |
4802 | } | |
b9bec74b JK |
4803 | } |
4804 | } | |
e22a25c9 | 4805 | } |
ff4700b0 | 4806 | } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) { |
f2574737 | 4807 | ret = EXCP_DEBUG; |
b9bec74b | 4808 | } |
f2574737 | 4809 | if (ret == 0) { |
ff4700b0 | 4810 | cpu_synchronize_state(cs); |
fd13f23b | 4811 | assert(env->exception_nr == -1); |
b0b1d690 | 4812 | |
f2574737 | 4813 | /* pass to guest */ |
fd13f23b LA |
4814 | kvm_queue_exception(env, arch_info->exception, |
4815 | arch_info->exception == EXCP01_DB, | |
4816 | arch_info->dr6); | |
48405526 | 4817 | env->has_error_code = 0; |
b0b1d690 | 4818 | } |
e22a25c9 | 4819 | |
f2574737 | 4820 | return ret; |
e22a25c9 AL |
4821 | } |
4822 | ||
20d695a9 | 4823 | void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg) |
e22a25c9 AL |
4824 | { |
4825 | const uint8_t type_code[] = { | |
4826 | [GDB_BREAKPOINT_HW] = 0x0, | |
4827 | [GDB_WATCHPOINT_WRITE] = 0x1, | |
4828 | [GDB_WATCHPOINT_ACCESS] = 0x3 | |
4829 | }; | |
4830 | const uint8_t len_code[] = { | |
4831 | [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2 | |
4832 | }; | |
4833 | int n; | |
4834 | ||
a60f24b5 | 4835 | if (kvm_sw_breakpoints_active(cpu)) { |
e22a25c9 | 4836 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; |
b9bec74b | 4837 | } |
e22a25c9 AL |
4838 | if (nb_hw_breakpoint > 0) { |
4839 | dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP; | |
4840 | dbg->arch.debugreg[7] = 0x0600; | |
4841 | for (n = 0; n < nb_hw_breakpoint; n++) { | |
4842 | dbg->arch.debugreg[n] = hw_breakpoint[n].addr; | |
4843 | dbg->arch.debugreg[7] |= (2 << (n * 2)) | | |
4844 | (type_code[hw_breakpoint[n].type] << (16 + n*4)) | | |
95c077c9 | 4845 | ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4)); |
e22a25c9 AL |
4846 | } |
4847 | } | |
4848 | } | |
4513d923 | 4849 | |
c22f5467 SC |
4850 | static bool has_sgx_provisioning; |
4851 | ||
4852 | static bool __kvm_enable_sgx_provisioning(KVMState *s) | |
4853 | { | |
4854 | int fd, ret; | |
4855 | ||
4856 | if (!kvm_vm_check_extension(s, KVM_CAP_SGX_ATTRIBUTE)) { | |
4857 | return false; | |
4858 | } | |
4859 | ||
4860 | fd = qemu_open_old("/dev/sgx_provision", O_RDONLY); | |
4861 | if (fd < 0) { | |
4862 | return false; | |
4863 | } | |
4864 | ||
4865 | ret = kvm_vm_enable_cap(s, KVM_CAP_SGX_ATTRIBUTE, 0, fd); | |
4866 | if (ret) { | |
4867 | error_report("Could not enable SGX PROVISIONKEY: %s", strerror(-ret)); | |
4868 | exit(1); | |
4869 | } | |
4870 | close(fd); | |
4871 | return true; | |
4872 | } | |
4873 | ||
4874 | bool kvm_enable_sgx_provisioning(KVMState *s) | |
4875 | { | |
4876 | return MEMORIZE(__kvm_enable_sgx_provisioning(s), has_sgx_provisioning); | |
4877 | } | |
4878 | ||
2a4dac83 JK |
4879 | static bool host_supports_vmx(void) |
4880 | { | |
4881 | uint32_t ecx, unused; | |
4882 | ||
4883 | host_cpuid(1, 0, &unused, &unused, &ecx, &unused); | |
4884 | return ecx & CPUID_EXT_VMX; | |
4885 | } | |
4886 | ||
4887 | #define VMX_INVALID_GUEST_STATE 0x80000021 | |
4888 | ||
20d695a9 | 4889 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) |
2a4dac83 | 4890 | { |
20d695a9 | 4891 | X86CPU *cpu = X86_CPU(cs); |
2a4dac83 JK |
4892 | uint64_t code; |
4893 | int ret; | |
4894 | ||
4895 | switch (run->exit_reason) { | |
4896 | case KVM_EXIT_HLT: | |
4897 | DPRINTF("handle_hlt\n"); | |
4b8523ee | 4898 | qemu_mutex_lock_iothread(); |
839b5630 | 4899 | ret = kvm_handle_halt(cpu); |
4b8523ee | 4900 | qemu_mutex_unlock_iothread(); |
2a4dac83 JK |
4901 | break; |
4902 | case KVM_EXIT_SET_TPR: | |
4903 | ret = 0; | |
4904 | break; | |
d362e757 | 4905 | case KVM_EXIT_TPR_ACCESS: |
4b8523ee | 4906 | qemu_mutex_lock_iothread(); |
f7575c96 | 4907 | ret = kvm_handle_tpr_access(cpu); |
4b8523ee | 4908 | qemu_mutex_unlock_iothread(); |
d362e757 | 4909 | break; |
2a4dac83 JK |
4910 | case KVM_EXIT_FAIL_ENTRY: |
4911 | code = run->fail_entry.hardware_entry_failure_reason; | |
4912 | fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n", | |
4913 | code); | |
4914 | if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) { | |
4915 | fprintf(stderr, | |
12619721 | 4916 | "\nIf you're running a guest on an Intel machine without " |
2a4dac83 JK |
4917 | "unrestricted mode\n" |
4918 | "support, the failure can be most likely due to the guest " | |
4919 | "entering an invalid\n" | |
4920 | "state for Intel VT. For example, the guest maybe running " | |
4921 | "in big real mode\n" | |
4922 | "which is not supported on less recent Intel processors." | |
4923 | "\n\n"); | |
4924 | } | |
4925 | ret = -1; | |
4926 | break; | |
4927 | case KVM_EXIT_EXCEPTION: | |
4928 | fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n", | |
4929 | run->ex.exception, run->ex.error_code); | |
4930 | ret = -1; | |
4931 | break; | |
f2574737 JK |
4932 | case KVM_EXIT_DEBUG: |
4933 | DPRINTF("kvm_exit_debug\n"); | |
4b8523ee | 4934 | qemu_mutex_lock_iothread(); |
a60f24b5 | 4935 | ret = kvm_handle_debug(cpu, &run->debug.arch); |
4b8523ee | 4936 | qemu_mutex_unlock_iothread(); |
f2574737 | 4937 | break; |
50efe82c AS |
4938 | case KVM_EXIT_HYPERV: |
4939 | ret = kvm_hv_handle_exit(cpu, &run->hyperv); | |
4940 | break; | |
15eafc2e PB |
4941 | case KVM_EXIT_IOAPIC_EOI: |
4942 | ioapic_eoi_broadcast(run->eoi.vector); | |
4943 | ret = 0; | |
4944 | break; | |
035d1ef2 CQ |
4945 | case KVM_EXIT_X86_BUS_LOCK: |
4946 | /* already handled in kvm_arch_post_run */ | |
4947 | ret = 0; | |
4948 | break; | |
2a4dac83 JK |
4949 | default: |
4950 | fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); | |
4951 | ret = -1; | |
4952 | break; | |
4953 | } | |
4954 | ||
4955 | return ret; | |
4956 | } | |
4957 | ||
20d695a9 | 4958 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) |
4513d923 | 4959 | { |
20d695a9 AF |
4960 | X86CPU *cpu = X86_CPU(cs); |
4961 | CPUX86State *env = &cpu->env; | |
4962 | ||
dd1750d7 | 4963 | kvm_cpu_synchronize_state(cs); |
b9bec74b JK |
4964 | return !(env->cr[0] & CR0_PE_MASK) || |
4965 | ((env->segs[R_CS].selector & 3) != 3); | |
4513d923 | 4966 | } |
84b058d7 JK |
4967 | |
4968 | void kvm_arch_init_irq_routing(KVMState *s) | |
4969 | { | |
cc7e0ddf | 4970 | /* We know at this point that we're using the in-kernel |
614e41bc | 4971 | * irqchip, so we can use irqfds, and on x86 we know |
f3e1bed8 | 4972 | * we can use msi via irqfd and GSI routing. |
cc7e0ddf | 4973 | */ |
614e41bc | 4974 | kvm_msi_via_irqfd_allowed = true; |
f3e1bed8 | 4975 | kvm_gsi_routing_allowed = true; |
15eafc2e PB |
4976 | |
4977 | if (kvm_irqchip_is_split()) { | |
def4c557 | 4978 | KVMRouteChange c = kvm_irqchip_begin_route_changes(s); |
15eafc2e PB |
4979 | int i; |
4980 | ||
4981 | /* If the ioapic is in QEMU and the lapics are in KVM, reserve | |
4982 | MSI routes for signaling interrupts to the local apics. */ | |
4983 | for (i = 0; i < IOAPIC_NUM_PINS; i++) { | |
def4c557 | 4984 | if (kvm_irqchip_add_msi_route(&c, 0, NULL) < 0) { |
15eafc2e PB |
4985 | error_report("Could not enable split IRQ mode."); |
4986 | exit(1); | |
4987 | } | |
4988 | } | |
def4c557 | 4989 | kvm_irqchip_commit_route_changes(&c); |
15eafc2e PB |
4990 | } |
4991 | } | |
4992 | ||
4376c40d | 4993 | int kvm_arch_irqchip_create(KVMState *s) |
15eafc2e PB |
4994 | { |
4995 | int ret; | |
4376c40d | 4996 | if (kvm_kernel_irqchip_split()) { |
15eafc2e PB |
4997 | ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24); |
4998 | if (ret) { | |
df3c286c | 4999 | error_report("Could not enable split irqchip mode: %s", |
15eafc2e PB |
5000 | strerror(-ret)); |
5001 | exit(1); | |
5002 | } else { | |
5003 | DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n"); | |
5004 | kvm_split_irqchip = true; | |
5005 | return 1; | |
5006 | } | |
5007 | } else { | |
5008 | return 0; | |
5009 | } | |
84b058d7 | 5010 | } |
b139bd30 | 5011 | |
c1bb5418 DW |
5012 | uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address) |
5013 | { | |
5014 | CPUX86State *env; | |
5015 | uint64_t ext_id; | |
5016 | ||
5017 | if (!first_cpu) { | |
5018 | return address; | |
5019 | } | |
5020 | env = &X86_CPU(first_cpu)->env; | |
5021 | if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) { | |
5022 | return address; | |
5023 | } | |
5024 | ||
5025 | /* | |
5026 | * If the remappable format bit is set, or the upper bits are | |
5027 | * already set in address_hi, or the low extended bits aren't | |
5028 | * there anyway, do nothing. | |
5029 | */ | |
5030 | ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT); | |
5031 | if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) { | |
5032 | return address; | |
5033 | } | |
5034 | ||
5035 | address &= ~ext_id; | |
5036 | address |= ext_id << 35; | |
5037 | return address; | |
5038 | } | |
5039 | ||
9e03a040 | 5040 | int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, |
dc9f06ca | 5041 | uint64_t address, uint32_t data, PCIDevice *dev) |
9e03a040 | 5042 | { |
8b5ed7df PX |
5043 | X86IOMMUState *iommu = x86_iommu_get_default(); |
5044 | ||
5045 | if (iommu) { | |
30c60f77 | 5046 | X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu); |
8b5ed7df | 5047 | |
c1bb5418 DW |
5048 | if (class->int_remap) { |
5049 | int ret; | |
5050 | MSIMessage src, dst; | |
0ea1472d | 5051 | |
c1bb5418 DW |
5052 | src.address = route->u.msi.address_hi; |
5053 | src.address <<= VTD_MSI_ADDR_HI_SHIFT; | |
5054 | src.address |= route->u.msi.address_lo; | |
5055 | src.data = route->u.msi.data; | |
8b5ed7df | 5056 | |
c1bb5418 DW |
5057 | ret = class->int_remap(iommu, &src, &dst, dev ? \ |
5058 | pci_requester_id(dev) : \ | |
5059 | X86_IOMMU_SID_INVALID); | |
5060 | if (ret) { | |
5061 | trace_kvm_x86_fixup_msi_error(route->gsi); | |
5062 | return 1; | |
5063 | } | |
5064 | ||
5065 | /* | |
5066 | * Handled untranslated compatibilty format interrupt with | |
5067 | * extended destination ID in the low bits 11-5. */ | |
5068 | dst.address = kvm_swizzle_msi_ext_dest_id(dst.address); | |
8b5ed7df | 5069 | |
c1bb5418 DW |
5070 | route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT; |
5071 | route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK; | |
5072 | route->u.msi.data = dst.data; | |
5073 | return 0; | |
5074 | } | |
8b5ed7df PX |
5075 | } |
5076 | ||
c1bb5418 DW |
5077 | address = kvm_swizzle_msi_ext_dest_id(address); |
5078 | route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT; | |
5079 | route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK; | |
9e03a040 FB |
5080 | return 0; |
5081 | } | |
1850b6b7 | 5082 | |
38d87493 PX |
5083 | typedef struct MSIRouteEntry MSIRouteEntry; |
5084 | ||
5085 | struct MSIRouteEntry { | |
5086 | PCIDevice *dev; /* Device pointer */ | |
5087 | int vector; /* MSI/MSIX vector index */ | |
5088 | int virq; /* Virtual IRQ index */ | |
5089 | QLIST_ENTRY(MSIRouteEntry) list; | |
5090 | }; | |
5091 | ||
5092 | /* List of used GSI routes */ | |
5093 | static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \ | |
5094 | QLIST_HEAD_INITIALIZER(msi_route_list); | |
5095 | ||
e1d4fb2d PX |
5096 | static void kvm_update_msi_routes_all(void *private, bool global, |
5097 | uint32_t index, uint32_t mask) | |
5098 | { | |
a56de056 | 5099 | int cnt = 0, vector; |
e1d4fb2d PX |
5100 | MSIRouteEntry *entry; |
5101 | MSIMessage msg; | |
fd563564 PX |
5102 | PCIDevice *dev; |
5103 | ||
e1d4fb2d PX |
5104 | /* TODO: explicit route update */ |
5105 | QLIST_FOREACH(entry, &msi_route_list, list) { | |
5106 | cnt++; | |
a56de056 | 5107 | vector = entry->vector; |
fd563564 | 5108 | dev = entry->dev; |
a56de056 PX |
5109 | if (msix_enabled(dev) && !msix_is_masked(dev, vector)) { |
5110 | msg = msix_get_message(dev, vector); | |
5111 | } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) { | |
5112 | msg = msi_get_message(dev, vector); | |
5113 | } else { | |
5114 | /* | |
5115 | * Either MSI/MSIX is disabled for the device, or the | |
5116 | * specific message was masked out. Skip this one. | |
5117 | */ | |
fd563564 PX |
5118 | continue; |
5119 | } | |
fd563564 | 5120 | kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev); |
e1d4fb2d | 5121 | } |
3f1fea0f | 5122 | kvm_irqchip_commit_routes(kvm_state); |
e1d4fb2d PX |
5123 | trace_kvm_x86_update_msi_routes(cnt); |
5124 | } | |
5125 | ||
38d87493 PX |
5126 | int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, |
5127 | int vector, PCIDevice *dev) | |
5128 | { | |
e1d4fb2d | 5129 | static bool notify_list_inited = false; |
38d87493 PX |
5130 | MSIRouteEntry *entry; |
5131 | ||
5132 | if (!dev) { | |
5133 | /* These are (possibly) IOAPIC routes only used for split | |
5134 | * kernel irqchip mode, while what we are housekeeping are | |
5135 | * PCI devices only. */ | |
5136 | return 0; | |
5137 | } | |
5138 | ||
5139 | entry = g_new0(MSIRouteEntry, 1); | |
5140 | entry->dev = dev; | |
5141 | entry->vector = vector; | |
5142 | entry->virq = route->gsi; | |
5143 | QLIST_INSERT_HEAD(&msi_route_list, entry, list); | |
5144 | ||
5145 | trace_kvm_x86_add_msi_route(route->gsi); | |
e1d4fb2d PX |
5146 | |
5147 | if (!notify_list_inited) { | |
5148 | /* For the first time we do add route, add ourselves into | |
5149 | * IOMMU's IEC notify list if needed. */ | |
5150 | X86IOMMUState *iommu = x86_iommu_get_default(); | |
5151 | if (iommu) { | |
5152 | x86_iommu_iec_register_notifier(iommu, | |
5153 | kvm_update_msi_routes_all, | |
5154 | NULL); | |
5155 | } | |
5156 | notify_list_inited = true; | |
5157 | } | |
38d87493 PX |
5158 | return 0; |
5159 | } | |
5160 | ||
5161 | int kvm_arch_release_virq_post(int virq) | |
5162 | { | |
5163 | MSIRouteEntry *entry, *next; | |
5164 | QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) { | |
5165 | if (entry->virq == virq) { | |
5166 | trace_kvm_x86_remove_msi_route(virq); | |
5167 | QLIST_REMOVE(entry, list); | |
01960e6d | 5168 | g_free(entry); |
38d87493 PX |
5169 | break; |
5170 | } | |
5171 | } | |
9e03a040 FB |
5172 | return 0; |
5173 | } | |
1850b6b7 EA |
5174 | |
5175 | int kvm_arch_msi_data_to_gsi(uint32_t data) | |
5176 | { | |
5177 | abort(); | |
5178 | } | |
e1e43813 PB |
5179 | |
5180 | bool kvm_has_waitpkg(void) | |
5181 | { | |
5182 | return has_msr_umwait; | |
5183 | } | |
92a5199b TL |
5184 | |
5185 | bool kvm_arch_cpu_check_are_resettable(void) | |
5186 | { | |
5187 | return !sev_es_enabled(); | |
5188 | } | |
19db68ca YZ |
5189 | |
5190 | #define ARCH_REQ_XCOMP_GUEST_PERM 0x1025 | |
5191 | ||
5192 | void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask) | |
5193 | { | |
5194 | KVMState *s = kvm_state; | |
5195 | uint64_t supported; | |
5196 | ||
5197 | mask &= XSTATE_DYNAMIC_MASK; | |
5198 | if (!mask) { | |
5199 | return; | |
5200 | } | |
5201 | /* | |
5202 | * Just ignore bits that are not in CPUID[EAX=0xD,ECX=0]. | |
5203 | * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned | |
5204 | * about them already because they are not supported features. | |
5205 | */ | |
5206 | supported = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX); | |
5207 | supported |= (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32; | |
5208 | mask &= supported; | |
5209 | ||
5210 | while (mask) { | |
5211 | int bit = ctz64(mask); | |
5212 | int rc = syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit); | |
5213 | if (rc) { | |
5214 | /* | |
5215 | * Older kernel version (<5.17) do not support | |
5216 | * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return | |
5217 | * any dynamic feature from kvm_arch_get_supported_cpuid. | |
5218 | */ | |
5219 | warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure " | |
5220 | "for feature bit %d", bit); | |
5221 | } | |
5222 | mask &= ~BIT_ULL(bit); | |
5223 | } | |
5224 | } |