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i386: split hyperv_handle_properties() into hyperv_expand_features()/hyperv_fill_cpuids()
[mirror_qemu.git] / target / i386 / kvm / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
8efc4e51 16#include "qapi/qapi-events-run-state.h"
da34e65c 17#include "qapi/error.h"
05330448 18#include <sys/ioctl.h>
25d2e361 19#include <sys/utsname.h>
05330448
AL		 20
21#include <linux/kvm.h>
1814eab6 22#include "standard-headers/asm-x86/kvm_para.h"
05330448 23
33c11879 24#include "cpu.h"
f5cc5a5c 25#include "host-cpu.h"
9c17d615 26#include "sysemu/sysemu.h"
b3946626 27#include "sysemu/hw_accel.h"
6410848b 28#include "sysemu/kvm_int.h"
54d31236 29#include "sysemu/runstate.h"
1d31f66b 30#include "kvm_i386.h"
92a5199b 31#include "sev_i386.h"
50efe82c 32#include "hyperv.h"
5e953812 33#include "hyperv-proto.h"
50efe82c 34
022c62cb 35#include "exec/gdbstub.h"
1de7afc9 36#include "qemu/host-utils.h"
db725815 37#include "qemu/main-loop.h"
1de7afc9 38#include "qemu/config-file.h"
1c4a55db 39#include "qemu/error-report.h"
89a289c7 40#include "hw/i386/x86.h"
0d09e41a 41#include "hw/i386/apic.h"
e0723c45
PB		 42#include "hw/i386/apic_internal.h"
43#include "hw/i386/apic-msidef.h"
8b5ed7df 44#include "hw/i386/intel_iommu.h"
e1d4fb2d 45#include "hw/i386/x86-iommu.h"
d6d059ca 46#include "hw/i386/e820_memory_layout.h"
ec78e2cd 47#include "sysemu/sev.h"
50efe82c 48
a2cb15b0 49#include "hw/pci/pci.h"
15eafc2e 50#include "hw/pci/msi.h"
fd563564 51#include "hw/pci/msix.h"
795c40b8 52#include "migration/blocker.h"
4c663752 53#include "exec/memattrs.h"
8b5ed7df 54#include "trace.h"
05330448
AL		 55
56//#define DEBUG_KVM
57
58#ifdef DEBUG_KVM
8c0d577e 59#define DPRINTF(fmt, ...) \
05330448
AL		 60 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
61#else
8c0d577e 62#define DPRINTF(fmt, ...) \
05330448
AL		 63 do { } while (0)
64#endif
65
73b994f6
LA		 66/* From arch/x86/kvm/lapic.h */
67#define KVM_APIC_BUS_CYCLE_NS 1
68#define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
69
1a03675d
GC		 70#define MSR_KVM_WALL_CLOCK 0x11
71#define MSR_KVM_SYSTEM_TIME 0x12
72
d1138251
EH		 73/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
74 * 255 kvm_msr_entry structs */
75#define MSR_BUF_SIZE 4096
d71b62a1 76
420ae1fc
PB		 77static void kvm_init_msrs(X86CPU *cpu);
78
94a8d39a
JK		 79const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
80 KVM_CAP_INFO(SET_TSS_ADDR),
81 KVM_CAP_INFO(EXT_CPUID),
82 KVM_CAP_INFO(MP_STATE),
83 KVM_CAP_LAST_INFO
84};
25d2e361 85
c3a3a7d3
JK		 86static bool has_msr_star;
87static bool has_msr_hsave_pa;
c9b8f6b6 88static bool has_msr_tsc_aux;
f28558d3 89static bool has_msr_tsc_adjust;
aa82ba54 90static bool has_msr_tsc_deadline;
df67696e 91static bool has_msr_feature_control;
21e87c46 92static bool has_msr_misc_enable;
fc12d72e 93static bool has_msr_smbase;
79e9ebeb 94static bool has_msr_bndcfgs;
25d2e361 95static int lm_capable_kernel;
7bc3d711 96static bool has_msr_hv_hypercall;
f2a53c9e 97static bool has_msr_hv_crash;
744b8a94 98static bool has_msr_hv_reset;
8c145d7c 99static bool has_msr_hv_vpindex;
e9688fab 100static bool hv_vpindex_settable;
46eb8f98 101static bool has_msr_hv_runtime;
866eea9a 102static bool has_msr_hv_synic;
ff99aa64 103static bool has_msr_hv_stimer;
d72bc7f6 104static bool has_msr_hv_frequencies;
ba6a4fd9 105static bool has_msr_hv_reenlightenment;
18cd2c17 106static bool has_msr_xss;
65087997 107static bool has_msr_umwait;
a33a2cfe 108static bool has_msr_spec_ctrl;
2a9758c5 109static bool has_msr_tsx_ctrl;
cfeea0c0 110static bool has_msr_virt_ssbd;
e13713db 111static bool has_msr_smi_count;
aec5e9c3 112static bool has_msr_arch_capabs;
597360c0 113static bool has_msr_core_capabs;
20a78b02 114static bool has_msr_vmx_vmfunc;
67025148 115static bool has_msr_ucode_rev;
4a910e1f 116static bool has_msr_vmx_procbased_ctls2;
ea39f9b6 117static bool has_msr_perf_capabs;
6aa4228b 118static bool has_msr_pkrs;
b827df58 119
0b368a10
JD		 120static uint32_t has_architectural_pmu_version;
121static uint32_t num_architectural_pmu_gp_counters;
122static uint32_t num_architectural_pmu_fixed_counters;
0d894367 123
28143b40
TH		 124static int has_xsave;
125static int has_xcrs;
126static int has_pit_state2;
fd13f23b 127static int has_exception_payload;
28143b40 128
87f8b626
AR		 129static bool has_msr_mcg_ext_ctl;
130
494e95e9 131static struct kvm_cpuid2 *cpuid_cache;
a8439be6 132static struct kvm_cpuid2 *hv_cpuid_cache;
f57bceb6 133static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 134
28143b40
TH		 135int kvm_has_pit_state2(void)
136{
137 return has_pit_state2;
138}
139
355023f2
PB		 140bool kvm_has_smm(void)
141{
23edf8b5 142 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
355023f2
PB		 143}
144
6053a86f
MT		 145bool kvm_has_adjust_clock_stable(void)
146{
147 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
148
149 return (ret == KVM_CLOCK_TSC_STABLE);
150}
151
8700a984
VK		 152bool kvm_has_adjust_clock(void)
153{
154 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
155}
156
79a197ab
LA		 157bool kvm_has_exception_payload(void)
158{
159 return has_exception_payload;
160}
161
fb506e70
RK		 162static bool kvm_x2apic_api_set_flags(uint64_t flags)
163{
4f7f5893 164 KVMState *s = KVM_STATE(current_accel());
fb506e70
RK		 165
166 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
167}
168
e391c009 169#define MEMORIZE(fn, _result) \
2a138ec3 170 ({ \
2a138ec3
RK		 171 static bool _memorized; \
172 \
173 if (_memorized) { \
174 return _result; \
175 } \
176 _memorized = true; \
177 _result = fn; \
178 })
179
e391c009
IM		 180static bool has_x2apic_api;
181
182bool kvm_has_x2apic_api(void)
183{
184 return has_x2apic_api;
185}
186
fb506e70
RK		 187bool kvm_enable_x2apic(void)
188{
2a138ec3
RK		 189 return MEMORIZE(
190 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 191 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
192 has_x2apic_api);
fb506e70
RK		 193}
194
e9688fab
RK		 195bool kvm_hv_vpindex_settable(void)
196{
197 return hv_vpindex_settable;
198}
199
0fd7e098
LL		 200static int kvm_get_tsc(CPUState *cs)
201{
202 X86CPU *cpu = X86_CPU(cs);
203 CPUX86State *env = &cpu->env;
204 struct {
205 struct kvm_msrs info;
206 struct kvm_msr_entry entries[1];
a1834d97 207 } msr_data = {};
0fd7e098
LL		 208 int ret;
209
210 if (env->tsc_valid) {
211 return 0;
212 }
213
1f670a95 214 memset(&msr_data, 0, sizeof(msr_data));
0fd7e098
LL		 215 msr_data.info.nmsrs = 1;
216 msr_data.entries[0].index = MSR_IA32_TSC;
217 env->tsc_valid = !runstate_is_running();
218
219 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
220 if (ret < 0) {
221 return ret;
222 }
223
48e1a45c 224 assert(ret == 1);
0fd7e098
LL		 225 env->tsc = msr_data.entries[0].data;
226 return 0;
227}
228
14e6fe12 229static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 230{
0fd7e098
LL		 231 kvm_get_tsc(cpu);
232}
233
234void kvm_synchronize_all_tsc(void)
235{
236 CPUState *cpu;
237
238 if (kvm_enabled()) {
239 CPU_FOREACH(cpu) {
14e6fe12 240 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 241 }
242 }
243}
244
b827df58
AK		 245static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
246{
247 struct kvm_cpuid2 *cpuid;
248 int r, size;
249
250 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 251 cpuid = g_malloc0(size);
b827df58
AK		 252 cpuid->nent = max;
253 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 254 if (r == 0 && cpuid->nent >= max) {
255 r = -E2BIG;
256 }
b827df58
AK		 257 if (r < 0) {
258 if (r == -E2BIG) {
7267c094 259 g_free(cpuid);
b827df58
AK		 260 return NULL;
261 } else {
262 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
263 strerror(-r));
264 exit(1);
265 }
266 }
267 return cpuid;
268}
269
dd87f8a6
EH		 270/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
271 * for all entries.
272 */
273static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
274{
275 struct kvm_cpuid2 *cpuid;
276 int max = 1;
494e95e9
CP		 277
278 if (cpuid_cache != NULL) {
279 return cpuid_cache;
280 }
dd87f8a6
EH		 281 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
282 max *= 2;
283 }
494e95e9 284 cpuid_cache = cpuid;
dd87f8a6
EH		 285 return cpuid;
286}
287
b199c682 288static bool host_tsx_broken(void)
40e80ee4
EH		 289{
290 int family, model, stepping;\
291 char vendor[CPUID_VENDOR_SZ + 1];
292
f5cc5a5c 293 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
40e80ee4
EH		 294
295 /* Check if we are running on a Haswell host known to have broken TSX */
296 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
297 (family == 6) &&
298 ((model == 63 && stepping < 4) ||
299 model == 60 || model == 69 || model == 70);
300}
0c31b744 301
829ae2f9
EH		 302/* Returns the value for a specific register on the cpuid entry
303 */
304static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
305{
306 uint32_t ret = 0;
307 switch (reg) {
308 case R_EAX:
309 ret = entry->eax;
310 break;
311 case R_EBX:
312 ret = entry->ebx;
313 break;
314 case R_ECX:
315 ret = entry->ecx;
316 break;
317 case R_EDX:
318 ret = entry->edx;
319 break;
320 }
321 return ret;
322}
323
4fb73f1d
EH		 324/* Find matching entry for function/index on kvm_cpuid2 struct
325 */
326static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
327 uint32_t function,
328 uint32_t index)
329{
330 int i;
331 for (i = 0; i < cpuid->nent; ++i) {
332 if (cpuid->entries[i].function == function &&
333 cpuid->entries[i].index == index) {
334 return &cpuid->entries[i];
335 }
336 }
337 /* not found: */
338 return NULL;
339}
340
ba9bc59e 341uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 342 uint32_t index, int reg)
b827df58
AK		 343{
344 struct kvm_cpuid2 *cpuid;
b827df58
AK		 345 uint32_t ret = 0;
346 uint32_t cpuid_1_edx;
347
dd87f8a6 348 cpuid = get_supported_cpuid(s);
b827df58 349
4fb73f1d
EH		 350 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
351 if (entry) {
4fb73f1d 352 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 353 }
354
7b46e5ce
EH		 355 /* Fixups for the data returned by KVM, below */
356
c2acb022
EH		 357 if (function == 1 && reg == R_EDX) {
358 /* KVM before 2.6.30 misreports the following features */
359 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 360 } else if (function == 1 && reg == R_ECX) {
361 /* We can set the hypervisor flag, even if KVM does not return it on
362 * GET_SUPPORTED_CPUID
363 */
364 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 365 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
366 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
367 * and the irqchip is in the kernel.
368 */
369 if (kvm_irqchip_in_kernel() &&
370 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
371 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
372 }
41e5e76d
EH		 373
374 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
375 * without the in-kernel irqchip
376 */
377 if (!kvm_irqchip_in_kernel()) {
378 ret &= ~CPUID_EXT_X2APIC;
b827df58 379 }
2266d443
MT		 380
381 if (enable_cpu_pm) {
382 int disable_exits = kvm_check_extension(s,
383 KVM_CAP_X86_DISABLE_EXITS);
384
385 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
386 ret |= CPUID_EXT_MONITOR;
387 }
388 }
28b8e4d0
JK		 389 } else if (function == 6 && reg == R_EAX) {
390 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4 391 } else if (function == 7 && index == 0 && reg == R_EBX) {
b199c682 392 if (host_tsx_broken()) {
40e80ee4
EH		 393 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
394 }
485b1d25
EH		 395 } else if (function == 7 && index == 0 && reg == R_EDX) {
396 /*
397 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
398 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
399 * returned by KVM_GET_MSR_INDEX_LIST.
400 */
401 if (!has_msr_arch_capabs) {
402 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
403 }
f98bbd83
BM		 404 } else if (function == 0x80000001 && reg == R_ECX) {
405 /*
406 * It's safe to enable TOPOEXT even if it's not returned by
407 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
408 * us to keep CPU models including TOPOEXT runnable on older kernels.
409 */
410 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 411 } else if (function == 0x80000001 && reg == R_EDX) {
412 /* On Intel, kvm returns cpuid according to the Intel spec,
413 * so add missing bits according to the AMD spec:
414 */
415 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
416 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 417 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
418 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
419 * be enabled without the in-kernel irqchip
420 */
421 if (!kvm_irqchip_in_kernel()) {
422 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
423 }
c1bb5418
DW		 424 if (kvm_irqchip_is_split()) {
425 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
426 }
be777326 427 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 428 ret |= 1U << KVM_HINTS_REALTIME;
b9bec74b 429 }
0c31b744
GC		 430
431 return ret;
bb0300dc 432}
bb0300dc 433
ede146c2 434uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
f57bceb6
RH		 435{
436 struct {
437 struct kvm_msrs info;
438 struct kvm_msr_entry entries[1];
a1834d97 439 } msr_data = {};
20a78b02
PB		 440 uint64_t value;
441 uint32_t ret, can_be_one, must_be_one;
f57bceb6
RH		 442
443 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
444 return 0;
445 }
446
447 /* Check if requested MSR is supported feature MSR */
448 int i;
449 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
450 if (kvm_feature_msrs->indices[i] == index) {
451 break;
452 }
453 if (i == kvm_feature_msrs->nmsrs) {
454 return 0; /* if the feature MSR is not supported, simply return 0 */
455 }
456
457 msr_data.info.nmsrs = 1;
458 msr_data.entries[0].index = index;
459
460 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
461 if (ret != 1) {
462 error_report("KVM get MSR (index=0x%x) feature failed, %s",
463 index, strerror(-ret));
464 exit(1);
465 }
466
20a78b02
PB		 467 value = msr_data.entries[0].data;
468 switch (index) {
469 case MSR_IA32_VMX_PROCBASED_CTLS2:
4a910e1f
VK		 470 if (!has_msr_vmx_procbased_ctls2) {
471 /* KVM forgot to add these bits for some time, do this ourselves. */
472 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
473 CPUID_XSAVE_XSAVES) {
474 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
475 }
476 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
477 CPUID_EXT_RDRAND) {
478 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
479 }
480 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
481 CPUID_7_0_EBX_INVPCID) {
482 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
483 }
484 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
485 CPUID_7_0_EBX_RDSEED) {
486 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
487 }
488 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
489 CPUID_EXT2_RDTSCP) {
490 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
491 }
048c9516
PB		 492 }
493 /* fall through */
20a78b02
PB		 494 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
495 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
496 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
497 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
498 /*
499 * Return true for bits that can be one, but do not have to be one.
500 * The SDM tells us which bits could have a "must be one" setting,
501 * so we can do the opposite transformation in make_vmx_msr_value.
502 */
503 must_be_one = (uint32_t)value;
504 can_be_one = (uint32_t)(value >> 32);
505 return can_be_one & ~must_be_one;
506
507 default:
508 return value;
509 }
f57bceb6
RH		 510}
511
e7701825
MT		 512static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
513 int *max_banks)
514{
515 int r;
516
14a09518 517 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 518 if (r > 0) {
519 *max_banks = r;
520 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
521 }
522 return -ENOSYS;
523}
524
bee615d4 525static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 526{
87f8b626 527 CPUState *cs = CPU(cpu);
bee615d4 528 CPUX86State *env = &cpu->env;
c34d440a
JK		 529 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
530 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
531 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 532 int flags = 0;
e7701825 533
c34d440a
JK		 534 if (code == BUS_MCEERR_AR) {
535 status |= MCI_STATUS_AR | 0x134;
536 mcg_status |= MCG_STATUS_EIPV;
537 } else {
538 status |= 0xc0;
539 mcg_status |= MCG_STATUS_RIPV;
419fb20a 540 }
87f8b626
AR		 541
542 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
543 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
544 * guest kernel back into env->mcg_ext_ctl.
545 */
546 cpu_synchronize_state(cs);
547 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
548 mcg_status |= MCG_STATUS_LMCE;
549 flags = 0;
550 }
551
8c5cf3b6 552 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 553 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 554}
419fb20a 555
8efc4e51
ZP		 556static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
557{
558 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
559
560 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
561 &mff);
562}
563
73284563 564static void hardware_memory_error(void *host_addr)
419fb20a 565{
8efc4e51 566 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
73284563 567 error_report("QEMU got Hardware memory error at addr %p", host_addr);
419fb20a
JK		 568 exit(1);
569}
570
2ae41db2 571void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 572{
20d695a9
AF		 573 X86CPU *cpu = X86_CPU(c);
574 CPUX86State *env = &cpu->env;
419fb20a 575 ram_addr_t ram_addr;
a8170e5e 576 hwaddr paddr;
419fb20a 577
4d39892c
PB		 578 /* If we get an action required MCE, it has been injected by KVM
579 * while the VM was running. An action optional MCE instead should
580 * be coming from the main thread, which qemu_init_sigbus identifies
581 * as the "early kill" thread.
582 */
a16fc07e 583 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 584
20e0ff59 585 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 586 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 587 if (ram_addr != RAM_ADDR_INVALID &&
588 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
589 kvm_hwpoison_page_add(ram_addr);
590 kvm_mce_inject(cpu, paddr, code);
73284563
MS		 591
592 /*
593 * Use different logging severity based on error type.
594 * If there is additional MCE reporting on the hypervisor, QEMU VA
595 * could be another source to identify the PA and MCE details.
596 */
597 if (code == BUS_MCEERR_AR) {
598 error_report("Guest MCE Memory Error at QEMU addr %p and "
599 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
600 addr, paddr, "BUS_MCEERR_AR");
601 } else {
602 warn_report("Guest MCE Memory Error at QEMU addr %p and "
603 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
604 addr, paddr, "BUS_MCEERR_AO");
605 }
606
2ae41db2 607 return;
419fb20a 608 }
20e0ff59 609
73284563
MS		 610 if (code == BUS_MCEERR_AO) {
611 warn_report("Hardware memory error at addr %p of type %s "
612 "for memory used by QEMU itself instead of guest system!",
613 addr, "BUS_MCEERR_AO");
614 }
419fb20a 615 }
20e0ff59
PB		 616
617 if (code == BUS_MCEERR_AR) {
73284563 618 hardware_memory_error(addr);
20e0ff59
PB		 619 }
620
8efc4e51
ZP		 621 /* Hope we are lucky for AO MCE, just notify a event */
622 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
419fb20a
JK		 623}
624
fd13f23b
LA		 625static void kvm_reset_exception(CPUX86State *env)
626{
627 env->exception_nr = -1;
628 env->exception_pending = 0;
629 env->exception_injected = 0;
630 env->exception_has_payload = false;
631 env->exception_payload = 0;
632}
633
634static void kvm_queue_exception(CPUX86State *env,
635 int32_t exception_nr,
636 uint8_t exception_has_payload,
637 uint64_t exception_payload)
638{
639 assert(env->exception_nr == -1);
640 assert(!env->exception_pending);
641 assert(!env->exception_injected);
642 assert(!env->exception_has_payload);
643
644 env->exception_nr = exception_nr;
645
646 if (has_exception_payload) {
647 env->exception_pending = 1;
648
649 env->exception_has_payload = exception_has_payload;
650 env->exception_payload = exception_payload;
651 } else {
652 env->exception_injected = 1;
653
654 if (exception_nr == EXCP01_DB) {
655 assert(exception_has_payload);
656 env->dr[6] = exception_payload;
657 } else if (exception_nr == EXCP0E_PAGE) {
658 assert(exception_has_payload);
659 env->cr[2] = exception_payload;
660 } else {
661 assert(!exception_has_payload);
662 }
663 }
664}
665
1bc22652 666static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 667{
1bc22652
AF		 668 CPUX86State *env = &cpu->env;
669
fd13f23b 670 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 671 unsigned int bank, bank_num = env->mcg_cap & 0xff;
672 struct kvm_x86_mce mce;
673
fd13f23b 674 kvm_reset_exception(env);
ab443475
JK		 675
676 /*
677 * There must be at least one bank in use if an MCE is pending.
678 * Find it and use its values for the event injection.
679 */
680 for (bank = 0; bank < bank_num; bank++) {
681 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
682 break;
683 }
684 }
685 assert(bank < bank_num);
686
687 mce.bank = bank;
688 mce.status = env->mce_banks[bank * 4 + 1];
689 mce.mcg_status = env->mcg_status;
690 mce.addr = env->mce_banks[bank * 4 + 2];
691 mce.misc = env->mce_banks[bank * 4 + 3];
692
1bc22652 693 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 694 }
ab443475
JK		 695 return 0;
696}
697
538f0497 698static void cpu_update_state(void *opaque, bool running, RunState state)
b8cc45d6 699{
317ac620 700 CPUX86State *env = opaque;
b8cc45d6
GC		 701
702 if (running) {
703 env->tsc_valid = false;
704 }
705}
706
83b17af5 707unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 708{
83b17af5 709 X86CPU *cpu = X86_CPU(cs);
7e72a45c 710 return cpu->apic_id;
b164e48e
EH		 711}
712
92067bf4
IM		 713#ifndef KVM_CPUID_SIGNATURE_NEXT
714#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
715#endif
716
92067bf4
IM		 717static bool hyperv_enabled(X86CPU *cpu)
718{
7bc3d711
PB		 719 CPUState *cs = CPU(cpu);
720 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
f701c082 721 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
e48ddcc6 722 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 723}
724
74aaddc6
MT		 725/*
726 * Check whether target_freq is within conservative
727 * ntp correctable bounds (250ppm) of freq
728 */
729static inline bool freq_within_bounds(int freq, int target_freq)
730{
731 int max_freq = freq + (freq * 250 / 1000000);
732 int min_freq = freq - (freq * 250 / 1000000);
733
734 if (target_freq >= min_freq && target_freq <= max_freq) {
735 return true;
736 }
737
738 return false;
739}
740
5031283d
HZ		 741static int kvm_arch_set_tsc_khz(CPUState *cs)
742{
743 X86CPU *cpu = X86_CPU(cs);
744 CPUX86State *env = &cpu->env;
74aaddc6
MT		 745 int r, cur_freq;
746 bool set_ioctl = false;
5031283d
HZ		 747
748 if (!env->tsc_khz) {
749 return 0;
750 }
751
74aaddc6
MT		 752 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
753 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
754
755 /*
756 * If TSC scaling is supported, attempt to set TSC frequency.
757 */
758 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
759 set_ioctl = true;
760 }
761
762 /*
763 * If desired TSC frequency is within bounds of NTP correction,
764 * attempt to set TSC frequency.
765 */
766 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
767 set_ioctl = true;
768 }
769
770 r = set_ioctl ?
5031283d
HZ		 771 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
772 -ENOTSUP;
74aaddc6 773
5031283d
HZ		 774 if (r < 0) {
775 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
776 * TSC frequency doesn't match the one we want.
777 */
74aaddc6
MT		 778 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
779 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
780 -ENOTSUP;
5031283d 781 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 782 warn_report("TSC frequency mismatch between "
783 "VM (%" PRId64 " kHz) and host (%d kHz), "
784 "and TSC scaling unavailable",
785 env->tsc_khz, cur_freq);
5031283d
HZ		 786 return r;
787 }
788 }
789
790 return 0;
791}
792
4bb95b82
LP		 793static bool tsc_is_stable_and_known(CPUX86State *env)
794{
795 if (!env->tsc_khz) {
796 return false;
797 }
798 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
799 || env->user_tsc_khz;
800}
801
6760bd20
VK		 802static struct {
803 const char *desc;
804 struct {
061817a7
VK		 805 uint32_t func;
806 int reg;
6760bd20
VK		 807 uint32_t bits;
808 } flags[2];
c6861930 809 uint64_t dependencies;
6760bd20
VK		 810} kvm_hyperv_properties[] = {
811 [HYPERV_FEAT_RELAXED] = {
812 .desc = "relaxed timing (hv-relaxed)",
813 .flags = {
061817a7 814 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 815 .bits = HV_HYPERCALL_AVAILABLE},
061817a7 816 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 817 .bits = HV_RELAXED_TIMING_RECOMMENDED}
818 }
819 },
820 [HYPERV_FEAT_VAPIC] = {
821 .desc = "virtual APIC (hv-vapic)",
822 .flags = {
061817a7 823 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 824 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
061817a7 825 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 826 .bits = HV_APIC_ACCESS_RECOMMENDED}
827 }
828 },
829 [HYPERV_FEAT_TIME] = {
830 .desc = "clocksources (hv-time)",
831 .flags = {
061817a7 832 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 833 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
834 HV_REFERENCE_TSC_AVAILABLE}
835 }
836 },
837 [HYPERV_FEAT_CRASH] = {
838 .desc = "crash MSRs (hv-crash)",
839 .flags = {
061817a7 840 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 841 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
842 }
843 },
844 [HYPERV_FEAT_RESET] = {
845 .desc = "reset MSR (hv-reset)",
846 .flags = {
061817a7 847 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 848 .bits = HV_RESET_AVAILABLE}
849 }
850 },
851 [HYPERV_FEAT_VPINDEX] = {
852 .desc = "VP_INDEX MSR (hv-vpindex)",
853 .flags = {
061817a7 854 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 855 .bits = HV_VP_INDEX_AVAILABLE}
856 }
857 },
858 [HYPERV_FEAT_RUNTIME] = {
859 .desc = "VP_RUNTIME MSR (hv-runtime)",
860 .flags = {
061817a7 861 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 862 .bits = HV_VP_RUNTIME_AVAILABLE}
863 }
864 },
865 [HYPERV_FEAT_SYNIC] = {
866 .desc = "synthetic interrupt controller (hv-synic)",
867 .flags = {
061817a7 868 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 869 .bits = HV_SYNIC_AVAILABLE}
870 }
871 },
872 [HYPERV_FEAT_STIMER] = {
873 .desc = "synthetic timers (hv-stimer)",
874 .flags = {
061817a7 875 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 876 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 877 },
878 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 879 },
880 [HYPERV_FEAT_FREQUENCIES] = {
881 .desc = "frequency MSRs (hv-frequencies)",
882 .flags = {
061817a7 883 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 884 .bits = HV_ACCESS_FREQUENCY_MSRS},
061817a7 885 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 886 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
887 }
888 },
889 [HYPERV_FEAT_REENLIGHTENMENT] = {
890 .desc = "reenlightenment MSRs (hv-reenlightenment)",
891 .flags = {
061817a7 892 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 893 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
894 }
895 },
896 [HYPERV_FEAT_TLBFLUSH] = {
897 .desc = "paravirtualized TLB flush (hv-tlbflush)",
898 .flags = {
061817a7 899 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 900 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
901 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 902 },
903 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 904 },
905 [HYPERV_FEAT_EVMCS] = {
906 .desc = "enlightened VMCS (hv-evmcs)",
907 .flags = {
061817a7 908 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20 909 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 910 },
911 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 912 },
913 [HYPERV_FEAT_IPI] = {
914 .desc = "paravirtualized IPI (hv-ipi)",
915 .flags = {
061817a7 916 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 917 .bits = HV_CLUSTER_IPI_RECOMMENDED |
918 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 919 },
920 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 921 },
128531d9
VK		 922 [HYPERV_FEAT_STIMER_DIRECT] = {
923 .desc = "direct mode synthetic timers (hv-stimer-direct)",
924 .flags = {
061817a7 925 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
128531d9
VK		 926 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
927 },
928 .dependencies = BIT(HYPERV_FEAT_STIMER)
929 },
6760bd20
VK		 930};
931
932static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
933{
934 struct kvm_cpuid2 *cpuid;
935 int r, size;
936
937 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
938 cpuid = g_malloc0(size);
939 cpuid->nent = max;
940
941 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
942 if (r == 0 && cpuid->nent >= max) {
943 r = -E2BIG;
944 }
945 if (r < 0) {
946 if (r == -E2BIG) {
947 g_free(cpuid);
948 return NULL;
949 } else {
950 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
951 strerror(-r));
952 exit(1);
953 }
954 }
955 return cpuid;
956}
957
958/*
959 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
960 * for all entries.
961 */
962static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
963{
964 struct kvm_cpuid2 *cpuid;
965 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
966
967 /*
968 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
969 * -E2BIG, however, it doesn't report back the right size. Keep increasing
970 * it and re-trying until we succeed.
971 */
972 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
973 max++;
974 }
975 return cpuid;
976}
977
978/*
979 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
980 * leaves from KVM_CAP_HYPERV* and present MSRs data.
981 */
982static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 983{
984 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 985 struct kvm_cpuid2 *cpuid;
986 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
987
988 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
989 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
990 cpuid->nent = 2;
991
992 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
993 entry_feat = &cpuid->entries[0];
994 entry_feat->function = HV_CPUID_FEATURES;
995
996 entry_recomm = &cpuid->entries[1];
997 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
998 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
999
1000 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1001 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1002 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1003 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1004 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1005 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1006 }
c35bd19a 1007
6760bd20
VK		 1008 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1009 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1010 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 1011 }
6760bd20
VK		 1012
1013 if (has_msr_hv_frequencies) {
1014 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1015 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 1016 }
6760bd20
VK		 1017
1018 if (has_msr_hv_crash) {
1019 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 1020 }
6760bd20
VK		 1021
1022 if (has_msr_hv_reenlightenment) {
1023 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 1024 }
6760bd20
VK		 1025
1026 if (has_msr_hv_reset) {
1027 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 1028 }
6760bd20
VK		 1029
1030 if (has_msr_hv_vpindex) {
1031 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 1032 }
6760bd20
VK		 1033
1034 if (has_msr_hv_runtime) {
1035 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 1036 }
6760bd20
VK		 1037
1038 if (has_msr_hv_synic) {
1039 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1040 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1041
1042 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1043 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 1044 }
c35bd19a 1045 }
6760bd20
VK		 1046
1047 if (has_msr_hv_stimer) {
1048 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 1049 }
9b4cf107 1050
6760bd20
VK		 1051 if (kvm_check_extension(cs->kvm_state,
1052 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1053 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1054 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1055 }
c35bd19a 1056
6760bd20
VK		 1057 if (kvm_check_extension(cs->kvm_state,
1058 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1059 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 1060 }
6760bd20
VK		 1061
1062 if (kvm_check_extension(cs->kvm_state,
1063 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1064 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1065 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 1066 }
6760bd20
VK		 1067
1068 return cpuid;
1069}
1070
a8439be6 1071static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
e1a66a1e
VK		 1072{
1073 struct kvm_cpuid_entry2 *entry;
a8439be6
VK		 1074 struct kvm_cpuid2 *cpuid;
1075
1076 if (hv_cpuid_cache) {
1077 cpuid = hv_cpuid_cache;
1078 } else {
1079 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1080 cpuid = get_supported_hv_cpuid(cs);
1081 } else {
1082 cpuid = get_supported_hv_cpuid_legacy(cs);
1083 }
1084 hv_cpuid_cache = cpuid;
1085 }
1086
1087 if (!cpuid) {
1088 return 0;
1089 }
e1a66a1e
VK		 1090
1091 entry = cpuid_find_entry(cpuid, func, 0);
1092 if (!entry) {
1093 return 0;
1094 }
1095
1096 return cpuid_entry_get_reg(entry, reg);
1097}
1098
a8439be6 1099static bool hyperv_feature_supported(CPUState *cs, int feature)
7682f857 1100{
061817a7
VK		 1101 uint32_t func, bits;
1102 int i, reg;
7682f857
VK		 1103
1104 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
061817a7
VK		 1105
1106 func = kvm_hyperv_properties[feature].flags[i].func;
1107 reg = kvm_hyperv_properties[feature].flags[i].reg;
7682f857
VK		 1108 bits = kvm_hyperv_properties[feature].flags[i].bits;
1109
061817a7 1110 if (!func) {
7682f857
VK		 1111 continue;
1112 }
1113
a8439be6 1114 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
7682f857
VK		 1115 return false;
1116 }
1117 }
1118
1119 return true;
1120}
1121
a8439be6 1122static int hv_cpuid_check_and_set(CPUState *cs, int feature)
6760bd20
VK		 1123{
1124 X86CPU *cpu = X86_CPU(cs);
c6861930 1125 uint64_t deps;
7682f857 1126 int dep_feat;
6760bd20 1127
e48ddcc6 1128 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1129 return 0;
1130 }
1131
c6861930 1132 deps = kvm_hyperv_properties[feature].dependencies;
9dc83cd9
HR		 1133 while (deps) {
1134 dep_feat = ctz64(deps);
c6861930
VK		 1135 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1136 fprintf(stderr,
1137 "Hyper-V %s requires Hyper-V %s\n",
1138 kvm_hyperv_properties[feature].desc,
1139 kvm_hyperv_properties[dep_feat].desc);
1140 return 1;
1141 }
9dc83cd9 1142 deps &= ~(1ull << dep_feat);
c6861930
VK		 1143 }
1144
a8439be6 1145 if (!hyperv_feature_supported(cs, feature)) {
7682f857
VK		 1146 if (hyperv_feat_enabled(cpu, feature)) {
1147 fprintf(stderr,
1148 "Hyper-V %s is not supported by kernel\n",
1149 kvm_hyperv_properties[feature].desc);
1150 return 1;
1151 } else {
1152 return 0;
6760bd20 1153 }
a2b107db 1154 }
6760bd20 1155
e48ddcc6
VK		 1156 if (cpu->hyperv_passthrough) {
1157 cpu->hyperv_features |= BIT(feature);
1158 }
1159
6760bd20
VK		 1160 return 0;
1161}
1162
061817a7 1163static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
c830015e
VK		 1164{
1165 X86CPU *cpu = X86_CPU(cs);
1166 uint32_t r = 0;
1167 int i, j;
1168
1169 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1170 if (!hyperv_feat_enabled(cpu, i)) {
1171 continue;
1172 }
1173
1174 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
061817a7
VK		 1175 if (kvm_hyperv_properties[i].flags[j].func != func) {
1176 continue;
1177 }
1178 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
c830015e
VK		 1179 continue;
1180 }
1181
1182 r |= kvm_hyperv_properties[i].flags[j].bits;
1183 }
1184 }
1185
1186 return r;
1187}
1188
2344d22e 1189/*
f6e01ab5
VK		 1190 * Expand Hyper-V CPU features. In partucular, check that all the requested
1191 * features are supported by the host and the sanity of the configuration
1192 * (that all the required dependencies are included). Also, this takes care
1193 * of 'hv_passthrough' mode and fills the environment with all supported
1194 * Hyper-V features.
2344d22e 1195 */
f6e01ab5 1196static int hyperv_expand_features(CPUState *cs)
6760bd20
VK		 1197{
1198 X86CPU *cpu = X86_CPU(cs);
e48ddcc6 1199 int r;
6760bd20 1200
2344d22e
VK		 1201 if (!hyperv_enabled(cpu))
1202 return 0;
1203
e48ddcc6
VK		 1204 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1205 cpu->hyperv_passthrough) {
a2b107db
VK		 1206 uint16_t evmcs_version;
1207
e48ddcc6
VK		 1208 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1209 (uintptr_t)&evmcs_version);
1210
1211 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1212 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1213 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1214 return -ENOSYS;
1215 }
e48ddcc6
VK		 1216
1217 if (!r) {
c830015e 1218 cpu->hyperv_nested[0] = evmcs_version;
e48ddcc6 1219 }
a2b107db
VK		 1220 }
1221
e48ddcc6 1222 if (cpu->hyperv_passthrough) {
e1a66a1e 1223 cpu->hyperv_vendor_id[0] =
a8439be6 1224 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
e1a66a1e 1225 cpu->hyperv_vendor_id[1] =
a8439be6 1226 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
e1a66a1e 1227 cpu->hyperv_vendor_id[2] =
a8439be6 1228 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
e1a66a1e
VK		 1229 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1230 sizeof(cpu->hyperv_vendor_id) + 1);
1231 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1232 sizeof(cpu->hyperv_vendor_id));
1233 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1234
1235 cpu->hyperv_interface_id[0] =
a8439be6 1236 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
e1a66a1e 1237 cpu->hyperv_interface_id[1] =
a8439be6 1238 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
e1a66a1e 1239 cpu->hyperv_interface_id[2] =
a8439be6 1240 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
e1a66a1e 1241 cpu->hyperv_interface_id[3] =
a8439be6 1242 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
e1a66a1e
VK		 1243
1244 cpu->hyperv_version_id[0] =
a8439be6 1245 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
e1a66a1e 1246 cpu->hyperv_version_id[1] =
a8439be6 1247 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX);
e1a66a1e 1248 cpu->hyperv_version_id[2] =
a8439be6 1249 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
e1a66a1e 1250 cpu->hyperv_version_id[3] =
a8439be6 1251 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX);
e1a66a1e 1252
a8439be6 1253 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
e1a66a1e
VK		 1254 R_EAX);
1255 cpu->hyperv_limits[0] =
a8439be6 1256 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
e1a66a1e 1257 cpu->hyperv_limits[1] =
a8439be6 1258 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
e1a66a1e 1259 cpu->hyperv_limits[2] =
a8439be6 1260 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
e1a66a1e
VK		 1261
1262 cpu->hyperv_spinlock_attempts =
a8439be6 1263 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
30d6ff66
VK		 1264 }
1265
6760bd20 1266 /* Features */
a8439be6
VK		 1267 r = hv_cpuid_check_and_set(cs, HYPERV_FEAT_RELAXED);
1268 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_VAPIC);
1269 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_TIME);
1270 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_CRASH);
1271 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_RESET);
1272 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_VPINDEX);
1273 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_RUNTIME);
1274 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_SYNIC);
1275 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER);
1276 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_FREQUENCIES);
1277 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_REENLIGHTENMENT);
1278 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_TLBFLUSH);
1279 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_EVMCS);
1280 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_IPI);
1281 r |= hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER_DIRECT);
6760bd20 1282
c6861930 1283 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1284 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1285 !cpu->hyperv_synic_kvm_only &&
1286 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1287 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1288 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1289 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1290 r |= 1;
1291 }
1292
2344d22e 1293 if (r) {
a8439be6 1294 return -ENOSYS;
2344d22e
VK		 1295 }
1296
f6e01ab5
VK		 1297 return 0;
1298}
1299
1300/*
1301 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1302 */
1303static int hyperv_fill_cpuids(CPUState *cs,
1304 struct kvm_cpuid_entry2 *cpuid_ent)
1305{
1306 X86CPU *cpu = X86_CPU(cs);
1307 struct kvm_cpuid_entry2 *c;
1308 uint32_t cpuid_i = 0;
1309
2344d22e
VK		 1310 c = &cpuid_ent[cpuid_i++];
1311 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
2344d22e
VK		 1312 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1313 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
08856771
VK		 1314 c->ebx = cpu->hyperv_vendor_id[0];
1315 c->ecx = cpu->hyperv_vendor_id[1];
1316 c->edx = cpu->hyperv_vendor_id[2];
2344d22e
VK		 1317
1318 c = &cpuid_ent[cpuid_i++];
1319 c->function = HV_CPUID_INTERFACE;
735db465
VK		 1320 c->eax = cpu->hyperv_interface_id[0];
1321 c->ebx = cpu->hyperv_interface_id[1];
1322 c->ecx = cpu->hyperv_interface_id[2];
1323 c->edx = cpu->hyperv_interface_id[3];
2344d22e
VK		 1324
1325 c = &cpuid_ent[cpuid_i++];
1326 c->function = HV_CPUID_VERSION;
fb7e31aa
VK		 1327 c->eax = cpu->hyperv_version_id[0];
1328 c->ebx = cpu->hyperv_version_id[1];
1329 c->ecx = cpu->hyperv_version_id[2];
1330 c->edx = cpu->hyperv_version_id[3];
2344d22e
VK		 1331
1332 c = &cpuid_ent[cpuid_i++];
1333 c->function = HV_CPUID_FEATURES;
061817a7
VK		 1334 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1335 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1336 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
c830015e
VK		 1337
1338 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1339 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
2344d22e
VK		 1340
1341 c = &cpuid_ent[cpuid_i++];
1342 c->function = HV_CPUID_ENLIGHTMENT_INFO;
061817a7 1343 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
2344d22e
VK		 1344 c->ebx = cpu->hyperv_spinlock_attempts;
1345
c830015e
VK		 1346 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1347 c->eax |= HV_NO_NONARCH_CORESHARING;
1348 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
a8439be6 1349 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
e1a66a1e 1350 HV_NO_NONARCH_CORESHARING;
c830015e
VK		 1351 }
1352
2344d22e
VK		 1353 c = &cpuid_ent[cpuid_i++];
1354 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1355 c->eax = cpu->hv_max_vps;
23eb5d03
VK		 1356 c->ebx = cpu->hyperv_limits[0];
1357 c->ecx = cpu->hyperv_limits[1];
1358 c->edx = cpu->hyperv_limits[2];
2344d22e
VK		 1359
1360 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1361 __u32 function;
1362
1363 /* Create zeroed 0x40000006..0x40000009 leaves */
1364 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1365 function < HV_CPUID_NESTED_FEATURES; function++) {
1366 c = &cpuid_ent[cpuid_i++];
1367 c->function = function;
1368 }
1369
1370 c = &cpuid_ent[cpuid_i++];
1371 c->function = HV_CPUID_NESTED_FEATURES;
c830015e 1372 c->eax = cpu->hyperv_nested[0];
2344d22e 1373 }
6760bd20 1374
a8439be6 1375 return cpuid_i;
c35bd19a
EY		 1376}
1377
e48ddcc6 1378static Error *hv_passthrough_mig_blocker;
30d6ff66 1379static Error *hv_no_nonarch_cs_mig_blocker;
e48ddcc6 1380
e9688fab
RK		 1381static int hyperv_init_vcpu(X86CPU *cpu)
1382{
729ce7e1 1383 CPUState *cs = CPU(cpu);
e48ddcc6 1384 Error *local_err = NULL;
729ce7e1
RK		 1385 int ret;
1386
e48ddcc6
VK		 1387 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1388 error_setg(&hv_passthrough_mig_blocker,
1389 "'hv-passthrough' CPU flag prevents migration, use explicit"
1390 " set of hv-* flags instead");
1391 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1392 if (local_err) {
1393 error_report_err(local_err);
1394 error_free(hv_passthrough_mig_blocker);
1395 return ret;
1396 }
1397 }
1398
30d6ff66
VK		 1399 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1400 hv_no_nonarch_cs_mig_blocker == NULL) {
1401 error_setg(&hv_no_nonarch_cs_mig_blocker,
1402 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1403 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1404 " make sure SMT is disabled and/or that vCPUs are properly"
1405 " pinned)");
1406 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
1407 if (local_err) {
1408 error_report_err(local_err);
1409 error_free(hv_no_nonarch_cs_mig_blocker);
1410 return ret;
1411 }
1412 }
1413
2d384d7c 1414 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1415 /*
1416 * the kernel doesn't support setting vp_index; assert that its value
1417 * is in sync
1418 */
e9688fab
RK		 1419 struct {
1420 struct kvm_msrs info;
1421 struct kvm_msr_entry entries[1];
1422 } msr_data = {
1423 .info.nmsrs = 1,
1424 .entries[0].index = HV_X64_MSR_VP_INDEX,
1425 };
1426
729ce7e1 1427 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1428 if (ret < 0) {
1429 return ret;
1430 }
1431 assert(ret == 1);
1432
701189e3 1433 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1434 error_report("kernel's vp_index != QEMU's vp_index");
1435 return -ENXIO;
1436 }
1437 }
1438
2d384d7c 1439 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1440 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1441 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1442 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1443 if (ret < 0) {
1444 error_report("failed to turn on HyperV SynIC in KVM: %s",
1445 strerror(-ret));
1446 return ret;
1447 }
606c34bf 1448
9b4cf107
RK		 1449 if (!cpu->hyperv_synic_kvm_only) {
1450 ret = hyperv_x86_synic_add(cpu);
1451 if (ret < 0) {
1452 error_report("failed to create HyperV SynIC: %s",
1453 strerror(-ret));
1454 return ret;
1455 }
606c34bf 1456 }
729ce7e1
RK		 1457 }
1458
e9688fab
RK		 1459 return 0;
1460}
1461
68bfd0ad
MT		 1462static Error *invtsc_mig_blocker;
1463
f8bb0565 1464#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1465
20d695a9 1466int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1467{
1468 struct {
486bd5a2 1469 struct kvm_cpuid2 cpuid;
f8bb0565 1470 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1471 } cpuid_data;
1472 /*
1473 * The kernel defines these structs with padding fields so there
1474 * should be no extra padding in our cpuid_data struct.
1475 */
1476 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1477 sizeof(struct kvm_cpuid2) +
1478 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1479
20d695a9
AF		 1480 X86CPU *cpu = X86_CPU(cs);
1481 CPUX86State *env = &cpu->env;
486bd5a2 1482 uint32_t limit, i, j, cpuid_i;
a33609ca 1483 uint32_t unused;
bb0300dc 1484 struct kvm_cpuid_entry2 *c;
bb0300dc 1485 uint32_t signature[3];
234cc647 1486 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1487 int max_nested_state_len;
e7429073 1488 int r;
fe44dc91 1489 Error *local_err = NULL;
05330448 1490
ef4cbe14
SW		 1491 memset(&cpuid_data, 0, sizeof(cpuid_data));
1492
05330448
AL		 1493 cpuid_i = 0;
1494
ddb98b5a
LP		 1495 r = kvm_arch_set_tsc_khz(cs);
1496 if (r < 0) {
6b2341ee 1497 return r;
ddb98b5a
LP		 1498 }
1499
1500 /* vcpu's TSC frequency is either specified by user, or following
1501 * the value used by KVM if the former is not present. In the
1502 * latter case, we query it from KVM and record in env->tsc_khz,
1503 * so that vcpu's TSC frequency can be migrated later via this field.
1504 */
1505 if (!env->tsc_khz) {
1506 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1507 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1508 -ENOTSUP;
1509 if (r > 0) {
1510 env->tsc_khz = r;
1511 }
1512 }
1513
73b994f6
LA		 1514 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1515
bb0300dc 1516 /* Paravirtualization CPUIDs */
f6e01ab5 1517 r = hyperv_expand_features(cs);
2344d22e
VK		 1518 if (r < 0) {
1519 return r;
f6e01ab5
VK		 1520 }
1521
1522 if (hyperv_enabled(cpu)) {
1523 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
234cc647 1524 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1525 has_msr_hv_hypercall = true;
eab70139
VR		 1526 }
1527
f522d2ac
AW		 1528 if (cpu->expose_kvm) {
1529 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1530 c = &cpuid_data.entries[cpuid_i++];
1531 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1532 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1533 c->ebx = signature[0];
1534 c->ecx = signature[1];
1535 c->edx = signature[2];
234cc647 1536
f522d2ac
AW		 1537 c = &cpuid_data.entries[cpuid_i++];
1538 c->function = KVM_CPUID_FEATURES | kvm_base;
1539 c->eax = env->features[FEAT_KVM];
be777326 1540 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1541 }
917367aa 1542
a33609ca 1543 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1544
1545 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1546 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1547 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1548 abort();
1549 }
bb0300dc 1550 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1551
1552 switch (i) {
a36b1029
AL		 1553 case 2: {
1554 /* Keep reading function 2 till all the input is received */
1555 int times;
1556
a36b1029 1557 c->function = i;
a33609ca
AL		 1558 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1559 KVM_CPUID_FLAG_STATE_READ_NEXT;
1560 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1561 times = c->eax & 0xff;
a36b1029
AL		 1562
1563 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1564 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1565 fprintf(stderr, "cpuid_data is full, no space for "
1566 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1567 abort();
1568 }
a33609ca 1569 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1570 c->function = i;
a33609ca
AL		 1571 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1572 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1573 }
1574 break;
1575 }
a94e1428
LX		 1576 case 0x1f:
1577 if (env->nr_dies < 2) {
1578 break;
1579 }
8821e214 1580 /* fallthrough */
486bd5a2
AL		 1581 case 4:
1582 case 0xb:
1583 case 0xd:
1584 for (j = 0; ; j++) {
31e8c696
AP		 1585 if (i == 0xd && j == 64) {
1586 break;
1587 }
a94e1428
LX		 1588
1589 if (i == 0x1f && j == 64) {
1590 break;
1591 }
1592
486bd5a2
AL		 1593 c->function = i;
1594 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1595 c->index = j;
a33609ca 1596 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1597
b9bec74b 1598 if (i == 4 && c->eax == 0) {
486bd5a2 1599 break;
b9bec74b
JK		 1600 }
1601 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1602 break;
b9bec74b 1603 }
a94e1428
LX		 1604 if (i == 0x1f && !(c->ecx & 0xff00)) {
1605 break;
1606 }
b9bec74b 1607 if (i == 0xd && c->eax == 0) {
31e8c696 1608 continue;
b9bec74b 1609 }
f8bb0565
IM		 1610 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1611 fprintf(stderr, "cpuid_data is full, no space for "
1612 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1613 abort();
1614 }
a33609ca 1615 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1616 }
1617 break;
80db491d 1618 case 0x7:
e37a5c7f
CP		 1619 case 0x14: {
1620 uint32_t times;
1621
1622 c->function = i;
1623 c->index = 0;
1624 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1625 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1626 times = c->eax;
1627
1628 for (j = 1; j <= times; ++j) {
1629 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1630 fprintf(stderr, "cpuid_data is full, no space for "
80db491d 1631 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
e37a5c7f
CP		 1632 abort();
1633 }
1634 c = &cpuid_data.entries[cpuid_i++];
1635 c->function = i;
1636 c->index = j;
1637 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1638 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1639 }
1640 break;
1641 }
486bd5a2 1642 default:
486bd5a2 1643 c->function = i;
a33609ca
AL		 1644 c->flags = 0;
1645 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1646 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1647 /*
1648 * KVM already returns all zeroes if a CPUID entry is missing,
1649 * so we can omit it and avoid hitting KVM's 80-entry limit.
1650 */
1651 cpuid_i--;
1652 }
486bd5a2
AL		 1653 break;
1654 }
05330448 1655 }
0d894367
PB		 1656
1657 if (limit >= 0x0a) {
0b368a10 1658 uint32_t eax, edx;
0d894367 1659
0b368a10
JD		 1660 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1661
1662 has_architectural_pmu_version = eax & 0xff;
1663 if (has_architectural_pmu_version > 0) {
1664 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1665
1666 /* Shouldn't be more than 32, since that's the number of bits
1667 * available in EBX to tell us _which_ counters are available.
1668 * Play it safe.
1669 */
0b368a10
JD		 1670 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1671 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1672 }
1673
1674 if (has_architectural_pmu_version > 1) {
1675 num_architectural_pmu_fixed_counters = edx & 0x1f;
1676
1677 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1678 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1679 }
0d894367
PB		 1680 }
1681 }
1682 }
1683
a33609ca 1684 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1685
1686 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1687 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1688 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1689 abort();
1690 }
bb0300dc 1691 c = &cpuid_data.entries[cpuid_i++];
05330448 1692
8f4202fb
BM		 1693 switch (i) {
1694 case 0x8000001d:
1695 /* Query for all AMD cache information leaves */
1696 for (j = 0; ; j++) {
1697 c->function = i;
1698 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1699 c->index = j;
1700 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1701
1702 if (c->eax == 0) {
1703 break;
1704 }
1705 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1706 fprintf(stderr, "cpuid_data is full, no space for "
1707 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1708 abort();
1709 }
1710 c = &cpuid_data.entries[cpuid_i++];
1711 }
1712 break;
1713 default:
1714 c->function = i;
1715 c->flags = 0;
1716 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1717 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1718 /*
1719 * KVM already returns all zeroes if a CPUID entry is missing,
1720 * so we can omit it and avoid hitting KVM's 80-entry limit.
1721 */
1722 cpuid_i--;
1723 }
8f4202fb
BM		 1724 break;
1725 }
05330448
AL		 1726 }
1727
b3baa152
BW		 1728 /* Call Centaur's CPUID instructions they are supported. */
1729 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1730 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1731
1732 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1733 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1734 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1735 abort();
1736 }
b3baa152
BW		 1737 c = &cpuid_data.entries[cpuid_i++];
1738
1739 c->function = i;
1740 c->flags = 0;
1741 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1742 }
1743 }
1744
05330448
AL		 1745 cpuid_data.cpuid.nent = cpuid_i;
1746
e7701825 1747 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1748 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1749 (CPUID_MCE | CPUID_MCA)
a60f24b5 1750 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1751 uint64_t mcg_cap, unsupported_caps;
e7701825 1752 int banks;
32a42024 1753 int ret;
e7701825 1754
a60f24b5 1755 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1756 if (ret < 0) {
1757 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1758 return ret;
e7701825 1759 }
75d49497 1760
2590f15b 1761 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1762 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1763 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1764 return -ENOTSUP;
75d49497 1765 }
49b69cbf 1766
5120901a
EH		 1767 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1768 if (unsupported_caps) {
87f8b626
AR		 1769 if (unsupported_caps & MCG_LMCE_P) {
1770 error_report("kvm: LMCE not supported");
1771 return -ENOTSUP;
1772 }
3dc6f869
AF		 1773 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1774 unsupported_caps);
5120901a
EH		 1775 }
1776
2590f15b
EH		 1777 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1778 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1779 if (ret < 0) {
1780 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1781 return ret;
1782 }
e7701825 1783 }
e7701825 1784
2a693142 1785 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
b8cc45d6 1786
df67696e
LJ		 1787 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1788 if (c) {
1789 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1790 !!(c->ecx & CPUID_EXT_SMX);
1791 }
1792
87f8b626
AR		 1793 if (env->mcg_cap & MCG_LMCE_P) {
1794 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1795 }
1796
d99569d9
EH		 1797 if (!env->user_tsc_khz) {
1798 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1799 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1800 error_setg(&invtsc_mig_blocker,
1801 "State blocked by non-migratable CPU device"
1802 " (invtsc flag)");
fe44dc91
AA		 1803 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1804 if (local_err) {
1805 error_report_err(local_err);
1806 error_free(invtsc_mig_blocker);
79a197ab 1807 return r;
fe44dc91 1808 }
d99569d9 1809 }
68bfd0ad
MT		 1810 }
1811
9954a158
PDJ		 1812 if (cpu->vmware_cpuid_freq
1813 /* Guests depend on 0x40000000 to detect this feature, so only expose
1814 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1815 && cpu->expose_kvm
1816 && kvm_base == KVM_CPUID_SIGNATURE
1817 /* TSC clock must be stable and known for this feature. */
4bb95b82 1818 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1819
1820 c = &cpuid_data.entries[cpuid_i++];
1821 c->function = KVM_CPUID_SIGNATURE | 0x10;
1822 c->eax = env->tsc_khz;
73b994f6 1823 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
9954a158
PDJ		 1824 c->ecx = c->edx = 0;
1825
1826 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1827 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1828 }
1829
1830 cpuid_data.cpuid.nent = cpuid_i;
1831
1832 cpuid_data.cpuid.padding = 0;
1833 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1834 if (r) {
1835 goto fail;
1836 }
1837
28143b40 1838 if (has_xsave) {
5b8063c4 1839 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1f670a95 1840 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
fabacc0f 1841 }
ebbfef2f
LA		 1842
1843 max_nested_state_len = kvm_max_nested_state_length();
1844 if (max_nested_state_len > 0) {
1845 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
ebbfef2f 1846
b16c0e20 1847 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
1e44f3ab 1848 struct kvm_vmx_nested_state_hdr *vmx_hdr;
ebbfef2f 1849
1e44f3ab
PB		 1850 env->nested_state = g_malloc0(max_nested_state_len);
1851 env->nested_state->size = max_nested_state_len;
1e44f3ab 1852
b16c0e20 1853 if (cpu_has_vmx(env)) {
2654ace1
TL		 1854 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1855 vmx_hdr = &env->nested_state->hdr.vmx;
1856 vmx_hdr->vmxon_pa = -1ull;
1857 vmx_hdr->vmcs12_pa = -1ull;
1858 } else {
1859 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
b16c0e20 1860 }
ebbfef2f
LA		 1861 }
1862 }
1863
d71b62a1 1864 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1865
273c515c
PB		 1866 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1867 has_msr_tsc_aux = false;
1868 }
d1ae67f6 1869
420ae1fc
PB		 1870 kvm_init_msrs(cpu);
1871
e9688fab
RK		 1872 r = hyperv_init_vcpu(cpu);
1873 if (r) {
1874 goto fail;
1875 }
1876
e7429073 1877 return 0;
fe44dc91
AA		 1878
1879 fail:
1880 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 1881
fe44dc91 1882 return r;
05330448
AL		 1883}
1884
b1115c99
LA		 1885int kvm_arch_destroy_vcpu(CPUState *cs)
1886{
1887 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 1888 CPUX86State *env = &cpu->env;
b1115c99
LA		 1889
1890 if (cpu->kvm_msr_buf) {
1891 g_free(cpu->kvm_msr_buf);
1892 cpu->kvm_msr_buf = NULL;
1893 }
1894
ebbfef2f
LA		 1895 if (env->nested_state) {
1896 g_free(env->nested_state);
1897 env->nested_state = NULL;
1898 }
1899
2a693142
PN		 1900 qemu_del_vm_change_state_handler(cpu->vmsentry);
1901
b1115c99
LA		 1902 return 0;
1903}
1904
50a2c6e5 1905void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1906{
20d695a9 1907 CPUX86State *env = &cpu->env;
dd673288 1908
1a5e9d2f 1909 env->xcr0 = 1;
ddced198 1910 if (kvm_irqchip_in_kernel()) {
dd673288 1911 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1912 KVM_MP_STATE_UNINITIALIZED;
1913 } else {
1914 env->mp_state = KVM_MP_STATE_RUNNABLE;
1915 }
689141dd 1916
2d384d7c 1917 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1918 int i;
1919 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1920 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1921 }
606c34bf
RK		 1922
1923 hyperv_x86_synic_reset(cpu);
689141dd 1924 }
d645e132
MT		 1925 /* enabled by default */
1926 env->poll_control_msr = 1;
b2f73a07
PB		 1927
1928 sev_es_set_reset_vector(CPU(cpu));
caa5af0f
JK		 1929}
1930
e0723c45
PB		 1931void kvm_arch_do_init_vcpu(X86CPU *cpu)
1932{
1933 CPUX86State *env = &cpu->env;
1934
1935 /* APs get directly into wait-for-SIPI state. */
1936 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1937 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1938 }
1939}
1940
f57bceb6
RH		 1941static int kvm_get_supported_feature_msrs(KVMState *s)
1942{
1943 int ret = 0;
1944
1945 if (kvm_feature_msrs != NULL) {
1946 return 0;
1947 }
1948
1949 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1950 return 0;
1951 }
1952
1953 struct kvm_msr_list msr_list;
1954
1955 msr_list.nmsrs = 0;
1956 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1957 if (ret < 0 && ret != -E2BIG) {
1958 error_report("Fetch KVM feature MSR list failed: %s",
1959 strerror(-ret));
1960 return ret;
1961 }
1962
1963 assert(msr_list.nmsrs > 0);
1964 kvm_feature_msrs = (struct kvm_msr_list *) \
1965 g_malloc0(sizeof(msr_list) +
1966 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1967
1968 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1969 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1970
1971 if (ret < 0) {
1972 error_report("Fetch KVM feature MSR list failed: %s",
1973 strerror(-ret));
1974 g_free(kvm_feature_msrs);
1975 kvm_feature_msrs = NULL;
1976 return ret;
1977 }
1978
1979 return 0;
1980}
1981
c3a3a7d3 1982static int kvm_get_supported_msrs(KVMState *s)
05330448 1983{
c3a3a7d3 1984 int ret = 0;
de428cea 1985 struct kvm_msr_list msr_list, *kvm_msr_list;
05330448 1986
de428cea
LQ		 1987 /*
1988 * Obtain MSR list from KVM. These are the MSRs that we must
1989 * save/restore.
1990 */
1991 msr_list.nmsrs = 0;
1992 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1993 if (ret < 0 && ret != -E2BIG) {
1994 return ret;
1995 }
1996 /*
1997 * Old kernel modules had a bug and could write beyond the provided
1998 * memory. Allocate at least a safe amount of 1K.
1999 */
2000 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2001 msr_list.nmsrs *
2002 sizeof(msr_list.indices[0])));
05330448 2003
de428cea
LQ		 2004 kvm_msr_list->nmsrs = msr_list.nmsrs;
2005 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2006 if (ret >= 0) {
2007 int i;
05330448 2008
de428cea
LQ		 2009 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2010 switch (kvm_msr_list->indices[i]) {
2011 case MSR_STAR:
2012 has_msr_star = true;
2013 break;
2014 case MSR_VM_HSAVE_PA:
2015 has_msr_hsave_pa = true;
2016 break;
2017 case MSR_TSC_AUX:
2018 has_msr_tsc_aux = true;
2019 break;
2020 case MSR_TSC_ADJUST:
2021 has_msr_tsc_adjust = true;
2022 break;
2023 case MSR_IA32_TSCDEADLINE:
2024 has_msr_tsc_deadline = true;
2025 break;
2026 case MSR_IA32_SMBASE:
2027 has_msr_smbase = true;
2028 break;
2029 case MSR_SMI_COUNT:
2030 has_msr_smi_count = true;
2031 break;
2032 case MSR_IA32_MISC_ENABLE:
2033 has_msr_misc_enable = true;
2034 break;
2035 case MSR_IA32_BNDCFGS:
2036 has_msr_bndcfgs = true;
2037 break;
2038 case MSR_IA32_XSS:
2039 has_msr_xss = true;
2040 break;
65087997
TX		 2041 case MSR_IA32_UMWAIT_CONTROL:
2042 has_msr_umwait = true;
2043 break;
de428cea
LQ		 2044 case HV_X64_MSR_CRASH_CTL:
2045 has_msr_hv_crash = true;
2046 break;
2047 case HV_X64_MSR_RESET:
2048 has_msr_hv_reset = true;
2049 break;
2050 case HV_X64_MSR_VP_INDEX:
2051 has_msr_hv_vpindex = true;
2052 break;
2053 case HV_X64_MSR_VP_RUNTIME:
2054 has_msr_hv_runtime = true;
2055 break;
2056 case HV_X64_MSR_SCONTROL:
2057 has_msr_hv_synic = true;
2058 break;
2059 case HV_X64_MSR_STIMER0_CONFIG:
2060 has_msr_hv_stimer = true;
2061 break;
2062 case HV_X64_MSR_TSC_FREQUENCY:
2063 has_msr_hv_frequencies = true;
2064 break;
2065 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2066 has_msr_hv_reenlightenment = true;
2067 break;
2068 case MSR_IA32_SPEC_CTRL:
2069 has_msr_spec_ctrl = true;
2070 break;
2a9758c5
PB		 2071 case MSR_IA32_TSX_CTRL:
2072 has_msr_tsx_ctrl = true;
2073 break;
de428cea
LQ		 2074 case MSR_VIRT_SSBD:
2075 has_msr_virt_ssbd = true;
2076 break;
2077 case MSR_IA32_ARCH_CAPABILITIES:
2078 has_msr_arch_capabs = true;
2079 break;
2080 case MSR_IA32_CORE_CAPABILITY:
2081 has_msr_core_capabs = true;
2082 break;
ea39f9b6
LX		 2083 case MSR_IA32_PERF_CAPABILITIES:
2084 has_msr_perf_capabs = true;
2085 break;
20a78b02
PB		 2086 case MSR_IA32_VMX_VMFUNC:
2087 has_msr_vmx_vmfunc = true;
2088 break;
67025148
PB		 2089 case MSR_IA32_UCODE_REV:
2090 has_msr_ucode_rev = true;
2091 break;
4a910e1f
VK		 2092 case MSR_IA32_VMX_PROCBASED_CTLS2:
2093 has_msr_vmx_procbased_ctls2 = true;
2094 break;
6aa4228b
CQ		 2095 case MSR_IA32_PKRS:
2096 has_msr_pkrs = true;
2097 break;
05330448
AL		 2098 }
2099 }
05330448
AL		 2100 }
2101
de428cea
LQ		 2102 g_free(kvm_msr_list);
2103
c3a3a7d3 2104 return ret;
05330448
AL		 2105}
2106
6410848b
PB		 2107static Notifier smram_machine_done;
2108static KVMMemoryListener smram_listener;
2109static AddressSpace smram_address_space;
2110static MemoryRegion smram_as_root;
2111static MemoryRegion smram_as_mem;
2112
2113static void register_smram_listener(Notifier *n, void *unused)
2114{
2115 MemoryRegion *smram =
2116 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2117
2118 /* Outer container... */
2119 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2120 memory_region_set_enabled(&smram_as_root, true);
2121
2122 /* ... with two regions inside: normal system memory with low
2123 * priority, and...
2124 */
2125 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2126 get_system_memory(), 0, ~0ull);
2127 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2128 memory_region_set_enabled(&smram_as_mem, true);
2129
2130 if (smram) {
2131 /* ... SMRAM with higher priority */
2132 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2133 memory_region_set_enabled(smram, true);
2134 }
2135
2136 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2137 kvm_memory_listener_register(kvm_state, &smram_listener,
2138 &smram_address_space, 1);
2139}
2140
b16565b3 2141int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 2142{
11076198 2143 uint64_t identity_base = 0xfffbc000;
39d6960a 2144 uint64_t shadow_mem;
20420430 2145 int ret;
25d2e361 2146 struct utsname utsname;
ec78e2cd
DG		 2147 Error *local_err = NULL;
2148
2149 /*
2150 * Initialize SEV context, if required
2151 *
2152 * If no memory encryption is requested (ms->cgs == NULL) this is
2153 * a no-op.
2154 *
2155 * It's also a no-op if a non-SEV confidential guest support
2156 * mechanism is selected. SEV is the only mechanism available to
2157 * select on x86 at present, so this doesn't arise, but if new
2158 * mechanisms are supported in future (e.g. TDX), they'll need
2159 * their own initialization either here or elsewhere.
2160 */
2161 ret = sev_kvm_init(ms->cgs, &local_err);
2162 if (ret < 0) {
2163 error_report_err(local_err);
2164 return ret;
2165 }
20420430 2166
1a6dff5f
EH		 2167 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2168 error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM");
2169 return -ENOTSUP;
2170 }
2171
28143b40 2172 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 2173 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 2174 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 2175
e9688fab
RK		 2176 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2177
fd13f23b
LA		 2178 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2179 if (has_exception_payload) {
2180 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2181 if (ret < 0) {
2182 error_report("kvm: Failed to enable exception payload cap: %s",
2183 strerror(-ret));
2184 return ret;
2185 }
2186 }
2187
c3a3a7d3 2188 ret = kvm_get_supported_msrs(s);
20420430 2189 if (ret < 0) {
20420430
SY		 2190 return ret;
2191 }
25d2e361 2192
f57bceb6
RH		 2193 kvm_get_supported_feature_msrs(s);
2194
25d2e361
MT		 2195 uname(&utsname);
2196 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2197
4c5b10b7 2198 /*
11076198
JK		 2199 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2200 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2201 * Since these must be part of guest physical memory, we need to allocate
2202 * them, both by setting their start addresses in the kernel and by
2203 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2204 *
2205 * Older KVM versions may not support setting the identity map base. In
2206 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2207 * size.
4c5b10b7 2208 */
11076198
JK		 2209 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2210 /* Allows up to 16M BIOSes. */
2211 identity_base = 0xfeffc000;
2212
2213 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2214 if (ret < 0) {
2215 return ret;
2216 }
4c5b10b7 2217 }
e56ff191 2218
11076198
JK		 2219 /* Set TSS base one page after EPT identity map. */
2220 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2221 if (ret < 0) {
2222 return ret;
2223 }
2224
11076198
JK		 2225 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2226 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2227 if (ret < 0) {
11076198 2228 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2229 return ret;
2230 }
2231
23b0898e 2232 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
36ad0e94
MA		 2233 if (shadow_mem != -1) {
2234 shadow_mem /= 4096;
2235 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2236 if (ret < 0) {
2237 return ret;
39d6960a
JK		 2238 }
2239 }
6410848b 2240
d870cfde 2241 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
8f54bbd0 2242 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
ed9e923c 2243 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
6410848b
PB		 2244 smram_machine_done.notify = register_smram_listener;
2245 qemu_add_machine_init_done_notifier(&smram_machine_done);
2246 }
6f131f13
MT		 2247
2248 if (enable_cpu_pm) {
2249 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2250 int ret;
2251
2252/* Work around for kernel header with a typo. TODO: fix header and drop. */
2253#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2254#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2255#endif
2256 if (disable_exits) {
2257 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2258 KVM_X86_DISABLE_EXITS_HLT |
d38d201f
WL		 2259 KVM_X86_DISABLE_EXITS_PAUSE |
2260 KVM_X86_DISABLE_EXITS_CSTATE);
6f131f13
MT		 2261 }
2262
2263 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2264 disable_exits);
2265 if (ret < 0) {
2266 error_report("kvm: guest stopping CPU not supported: %s",
2267 strerror(-ret));
2268 }
2269 }
2270
11076198 2271 return 0;
05330448 2272}
b9bec74b 2273
05330448
AL		 2274static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2275{
2276 lhs->selector = rhs->selector;
2277 lhs->base = rhs->base;
2278 lhs->limit = rhs->limit;
2279 lhs->type = 3;
2280 lhs->present = 1;
2281 lhs->dpl = 3;
2282 lhs->db = 0;
2283 lhs->s = 1;
2284 lhs->l = 0;
2285 lhs->g = 0;
2286 lhs->avl = 0;
2287 lhs->unusable = 0;
2288}
2289
2290static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2291{
2292 unsigned flags = rhs->flags;
2293 lhs->selector = rhs->selector;
2294 lhs->base = rhs->base;
2295 lhs->limit = rhs->limit;
2296 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2297 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2298 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2299 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2300 lhs->s = (flags & DESC_S_MASK) != 0;
2301 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2302 lhs->g = (flags & DESC_G_MASK) != 0;
2303 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2304 lhs->unusable = !lhs->present;
7e680753 2305 lhs->padding = 0;
05330448
AL		 2306}
2307
2308static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2309{
2310 lhs->selector = rhs->selector;
2311 lhs->base = rhs->base;
2312 lhs->limit = rhs->limit;
d45fc087
RP		 2313 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2314 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2315 (rhs->dpl << DESC_DPL_SHIFT) |
2316 (rhs->db << DESC_B_SHIFT) |
2317 (rhs->s * DESC_S_MASK) |
2318 (rhs->l << DESC_L_SHIFT) |
2319 (rhs->g * DESC_G_MASK) |
2320 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2321}
2322
2323static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2324{
b9bec74b 2325 if (set) {
05330448 2326 *kvm_reg = *qemu_reg;
b9bec74b 2327 } else {
05330448 2328 *qemu_reg = *kvm_reg;
b9bec74b 2329 }
05330448
AL		 2330}
2331
1bc22652 2332static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2333{
1bc22652 2334 CPUX86State *env = &cpu->env;
05330448
AL		 2335 struct kvm_regs regs;
2336 int ret = 0;
2337
2338 if (!set) {
1bc22652 2339 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2340 if (ret < 0) {
05330448 2341 return ret;
b9bec74b 2342 }
05330448
AL		 2343 }
2344
2345 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2346 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2347 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2348 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2349 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2350 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2351 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2352 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2353#ifdef TARGET_X86_64
2354 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2355 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2356 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2357 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2358 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2359 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2360 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2361 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2362#endif
2363
2364 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2365 kvm_getput_reg(&regs.rip, &env->eip, set);
2366
b9bec74b 2367 if (set) {
1bc22652 2368 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2369 }
05330448
AL		 2370
2371 return ret;
2372}
2373
1bc22652 2374static int kvm_put_fpu(X86CPU *cpu)
05330448 2375{
1bc22652 2376 CPUX86State *env = &cpu->env;
05330448
AL		 2377 struct kvm_fpu fpu;
2378 int i;
2379
2380 memset(&fpu, 0, sizeof fpu);
2381 fpu.fsw = env->fpus & ~(7 << 11);
2382 fpu.fsw |= (env->fpstt & 7) << 11;
2383 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2384 fpu.last_opcode = env->fpop;
2385 fpu.last_ip = env->fpip;
2386 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2387 for (i = 0; i < 8; ++i) {
2388 fpu.ftwx |= (!env->fptags[i]) << i;
2389 }
05330448 2390 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2391 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2392 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2393 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2394 }
05330448
AL		 2395 fpu.mxcsr = env->mxcsr;
2396
1bc22652 2397 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2398}
2399
6b42494b
JK		 2400#define XSAVE_FCW_FSW 0
2401#define XSAVE_FTW_FOP 1
f1665b21
SY		 2402#define XSAVE_CWD_RIP 2
2403#define XSAVE_CWD_RDP 4
2404#define XSAVE_MXCSR 6
2405#define XSAVE_ST_SPACE 8
2406#define XSAVE_XMM_SPACE 40
2407#define XSAVE_XSTATE_BV 128
2408#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2409#define XSAVE_BNDREGS 240
2410#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2411#define XSAVE_OPMASK 272
2412#define XSAVE_ZMM_Hi256 288
2413#define XSAVE_Hi16_ZMM 416
f74eefe0 2414#define XSAVE_PKRU 672
f1665b21 2415
b503717d 2416#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2417 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2418
2419#define ASSERT_OFFSET(word_offset, field) \
2420 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2421 offsetof(X86XSaveArea, field))
2422
2423ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2424ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2425ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2426ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2427ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2428ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2429ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2430ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2431ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2432ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2433ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2434ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2435ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2436ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2437ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2438
1bc22652 2439static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2440{
1bc22652 2441 CPUX86State *env = &cpu->env;
5b8063c4 2442 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2443
28143b40 2444 if (!has_xsave) {
1bc22652 2445 return kvm_put_fpu(cpu);
b9bec74b 2446 }
86a57621 2447 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2448
9be38598 2449 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2450}
2451
1bc22652 2452static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2453{
1bc22652 2454 CPUX86State *env = &cpu->env;
bdfc8480 2455 struct kvm_xcrs xcrs = {};
f1665b21 2456
28143b40 2457 if (!has_xcrs) {
f1665b21 2458 return 0;
b9bec74b 2459 }
f1665b21
SY		 2460
2461 xcrs.nr_xcrs = 1;
2462 xcrs.flags = 0;
2463 xcrs.xcrs[0].xcr = 0;
2464 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2465 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2466}
2467
1bc22652 2468static int kvm_put_sregs(X86CPU *cpu)
05330448 2469{
1bc22652 2470 CPUX86State *env = &cpu->env;
05330448
AL		 2471 struct kvm_sregs sregs;
2472
0e607a80
JK		 2473 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2474 if (env->interrupt_injected >= 0) {
2475 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2476 (uint64_t)1 << (env->interrupt_injected % 64);
2477 }
05330448
AL		 2478
2479 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2480 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2481 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2482 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2483 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2484 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2485 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2486 } else {
b9bec74b
JK		 2487 set_seg(&sregs.cs, &env->segs[R_CS]);
2488 set_seg(&sregs.ds, &env->segs[R_DS]);
2489 set_seg(&sregs.es, &env->segs[R_ES]);
2490 set_seg(&sregs.fs, &env->segs[R_FS]);
2491 set_seg(&sregs.gs, &env->segs[R_GS]);
2492 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2493 }
2494
2495 set_seg(&sregs.tr, &env->tr);
2496 set_seg(&sregs.ldt, &env->ldt);
2497
2498 sregs.idt.limit = env->idt.limit;
2499 sregs.idt.base = env->idt.base;
7e680753 2500 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2501 sregs.gdt.limit = env->gdt.limit;
2502 sregs.gdt.base = env->gdt.base;
7e680753 2503 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2504
2505 sregs.cr0 = env->cr[0];
2506 sregs.cr2 = env->cr[2];
2507 sregs.cr3 = env->cr[3];
2508 sregs.cr4 = env->cr[4];
2509
02e51483
CF		 2510 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2511 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2512
2513 sregs.efer = env->efer;
2514
1bc22652 2515 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2516}
2517
d71b62a1
EH		 2518static void kvm_msr_buf_reset(X86CPU *cpu)
2519{
2520 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2521}
2522
9c600a84
EH		 2523static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2524{
2525 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2526 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2527 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2528
2529 assert((void *)(entry + 1) <= limit);
2530
1abc2cae
EH		 2531 entry->index = index;
2532 entry->reserved = 0;
2533 entry->data = value;
9c600a84
EH		 2534 msrs->nmsrs++;
2535}
2536
73e1b8f2
PB		 2537static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2538{
2539 kvm_msr_buf_reset(cpu);
2540 kvm_msr_entry_add(cpu, index, value);
2541
2542 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2543}
2544
f8d9ccf8
DDAG		 2545void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2546{
2547 int ret;
2548
2549 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2550 assert(ret == 1);
2551}
2552
7477cd38
MT		 2553static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2554{
2555 CPUX86State *env = &cpu->env;
48e1a45c 2556 int ret;
7477cd38
MT		 2557
2558 if (!has_msr_tsc_deadline) {
2559 return 0;
2560 }
2561
73e1b8f2 2562 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2563 if (ret < 0) {
2564 return ret;
2565 }
2566
2567 assert(ret == 1);
2568 return 0;
7477cd38
MT		 2569}
2570
6bdf863d
JK		 2571/*
2572 * Provide a separate write service for the feature control MSR in order to
2573 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2574 * before writing any other state because forcibly leaving nested mode
2575 * invalidates the VCPU state.
2576 */
2577static int kvm_put_msr_feature_control(X86CPU *cpu)
2578{
48e1a45c
PB		 2579 int ret;
2580
2581 if (!has_msr_feature_control) {
2582 return 0;
2583 }
6bdf863d 2584
73e1b8f2
PB		 2585 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2586 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2587 if (ret < 0) {
2588 return ret;
2589 }
2590
2591 assert(ret == 1);
2592 return 0;
6bdf863d
JK		 2593}
2594
20a78b02
PB		 2595static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2596{
2597 uint32_t default1, can_be_one, can_be_zero;
2598 uint32_t must_be_one;
2599
2600 switch (index) {
2601 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2602 default1 = 0x00000016;
2603 break;
2604 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2605 default1 = 0x0401e172;
2606 break;
2607 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2608 default1 = 0x000011ff;
2609 break;
2610 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2611 default1 = 0x00036dff;
2612 break;
2613 case MSR_IA32_VMX_PROCBASED_CTLS2:
2614 default1 = 0;
2615 break;
2616 default:
2617 abort();
2618 }
2619
2620 /* If a feature bit is set, the control can be either set or clear.
2621 * Otherwise the value is limited to either 0 or 1 by default1.
2622 */
2623 can_be_one = features | default1;
2624 can_be_zero = features | ~default1;
2625 must_be_one = ~can_be_zero;
2626
2627 /*
2628 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2629 * Bit 32:63 -> 1 if the control bit can be one.
2630 */
2631 return must_be_one | (((uint64_t)can_be_one) << 32);
2632}
2633
2634#define VMCS12_MAX_FIELD_INDEX (0x17)
2635
2636static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2637{
2638 uint64_t kvm_vmx_basic =
2639 kvm_arch_get_supported_msr_feature(kvm_state,
2640 MSR_IA32_VMX_BASIC);
26051882
YZ		 2641
2642 if (!kvm_vmx_basic) {
2643 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2644 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2645 */
2646 return;
2647 }
2648
20a78b02
PB		 2649 uint64_t kvm_vmx_misc =
2650 kvm_arch_get_supported_msr_feature(kvm_state,
2651 MSR_IA32_VMX_MISC);
2652 uint64_t kvm_vmx_ept_vpid =
2653 kvm_arch_get_supported_msr_feature(kvm_state,
2654 MSR_IA32_VMX_EPT_VPID_CAP);
2655
2656 /*
2657 * If the guest is 64-bit, a value of 1 is allowed for the host address
2658 * space size vmexit control.
2659 */
2660 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2661 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2662
2663 /*
2664 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2665 * not change them for backwards compatibility.
2666 */
2667 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2668 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2669 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2670 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2671
2672 /*
2673 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2674 * change in the future but are always zero for now, clear them to be
2675 * future proof. Bits 32-63 in theory could change, though KVM does
2676 * not support dual-monitor treatment and probably never will; mask
2677 * them out as well.
2678 */
2679 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2680 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2681 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2682
2683 /*
2684 * EPT memory types should not change either, so we do not bother
2685 * adding features for them.
2686 */
2687 uint64_t fixed_vmx_ept_mask =
2688 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2689 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2690 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2691
2692 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2693 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2694 f[FEAT_VMX_PROCBASED_CTLS]));
2695 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2696 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2697 f[FEAT_VMX_PINBASED_CTLS]));
2698 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2699 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2700 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2701 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2702 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2703 f[FEAT_VMX_ENTRY_CTLS]));
2704 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2705 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2706 f[FEAT_VMX_SECONDARY_CTLS]));
2707 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2708 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2709 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2710 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2711 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2712 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2713 if (has_msr_vmx_vmfunc) {
2714 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2715 }
2716
2717 /*
2718 * Just to be safe, write these with constant values. The CRn_FIXED1
2719 * MSRs are generated by KVM based on the vCPU's CPUID.
2720 */
2721 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2722 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2723 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2724 CR4_VMXE_MASK);
2725 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM,
2726 VMCS12_MAX_FIELD_INDEX << 1);
2727}
2728
ea39f9b6
LX		 2729static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
2730{
2731 uint64_t kvm_perf_cap =
2732 kvm_arch_get_supported_msr_feature(kvm_state,
2733 MSR_IA32_PERF_CAPABILITIES);
2734
2735 if (kvm_perf_cap) {
2736 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
2737 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
2738 }
2739}
2740
420ae1fc
PB		 2741static int kvm_buf_set_msrs(X86CPU *cpu)
2742{
2743 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2744 if (ret < 0) {
2745 return ret;
2746 }
2747
2748 if (ret < cpu->kvm_msr_buf->nmsrs) {
2749 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2750 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2751 (uint32_t)e->index, (uint64_t)e->data);
2752 }
2753
2754 assert(ret == cpu->kvm_msr_buf->nmsrs);
2755 return 0;
2756}
2757
2758static void kvm_init_msrs(X86CPU *cpu)
2759{
2760 CPUX86State *env = &cpu->env;
2761
2762 kvm_msr_buf_reset(cpu);
2763 if (has_msr_arch_capabs) {
2764 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2765 env->features[FEAT_ARCH_CAPABILITIES]);
2766 }
2767
2768 if (has_msr_core_capabs) {
2769 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2770 env->features[FEAT_CORE_CAPABILITY]);
2771 }
2772
ea39f9b6
LX		 2773 if (has_msr_perf_capabs && cpu->enable_pmu) {
2774 kvm_msr_entry_add_perf(cpu, env->features);
2775 }
2776
67025148 2777 if (has_msr_ucode_rev) {
32c87d70
PB		 2778 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
2779 }
2780
420ae1fc
PB		 2781 /*
2782 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2783 * all kernels with MSR features should have them.
2784 */
2785 if (kvm_feature_msrs && cpu_has_vmx(env)) {
2786 kvm_msr_entry_add_vmx(cpu, env->features);
2787 }
2788
2789 assert(kvm_buf_set_msrs(cpu) == 0);
2790}
2791
1bc22652 2792static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2793{
1bc22652 2794 CPUX86State *env = &cpu->env;
9c600a84 2795 int i;
05330448 2796
d71b62a1
EH		 2797 kvm_msr_buf_reset(cpu);
2798
9c600a84
EH		 2799 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2800 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2801 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2802 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2803 if (has_msr_star) {
9c600a84 2804 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2805 }
c3a3a7d3 2806 if (has_msr_hsave_pa) {
9c600a84 2807 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2808 }
c9b8f6b6 2809 if (has_msr_tsc_aux) {
9c600a84 2810 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2811 }
f28558d3 2812 if (has_msr_tsc_adjust) {
9c600a84 2813 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2814 }
21e87c46 2815 if (has_msr_misc_enable) {
9c600a84 2816 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2817 env->msr_ia32_misc_enable);
2818 }
fc12d72e 2819 if (has_msr_smbase) {
9c600a84 2820 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2821 }
e13713db
LA		 2822 if (has_msr_smi_count) {
2823 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2824 }
6aa4228b
CQ		 2825 if (has_msr_pkrs) {
2826 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
2827 }
439d19f2 2828 if (has_msr_bndcfgs) {
9c600a84 2829 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2830 }
18cd2c17 2831 if (has_msr_xss) {
9c600a84 2832 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2833 }
65087997
TX		 2834 if (has_msr_umwait) {
2835 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
2836 }
a33a2cfe
PB		 2837 if (has_msr_spec_ctrl) {
2838 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2839 }
2a9758c5
PB		 2840 if (has_msr_tsx_ctrl) {
2841 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
2842 }
cfeea0c0
KRW		 2843 if (has_msr_virt_ssbd) {
2844 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2845 }
2846
05330448 2847#ifdef TARGET_X86_64
25d2e361 2848 if (lm_capable_kernel) {
9c600a84
EH		 2849 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2850 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2851 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2852 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2853 }
05330448 2854#endif
a33a2cfe 2855
ff5c186b 2856 /*
0d894367
PB		 2857 * The following MSRs have side effects on the guest or are too heavy
2858 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2859 */
2860 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2861 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2862 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2863 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
6615be07
VK		 2864 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
2865 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
2866 }
55c911a5 2867 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2868 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2869 }
55c911a5 2870 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2871 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2872 }
55c911a5 2873 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2874 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2875 }
d645e132
MT		 2876
2877 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2878 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2879 }
2880
0b368a10
JD		 2881 if (has_architectural_pmu_version > 0) {
2882 if (has_architectural_pmu_version > 1) {
2883 /* Stop the counter. */
2884 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2885 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2886 }
0d894367
PB		 2887
2888 /* Set the counter values. */
0b368a10 2889 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2890 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2891 env->msr_fixed_counters[i]);
2892 }
0b368a10 2893 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2894 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2895 env->msr_gp_counters[i]);
9c600a84 2896 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2897 env->msr_gp_evtsel[i]);
2898 }
0b368a10
JD		 2899 if (has_architectural_pmu_version > 1) {
2900 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2901 env->msr_global_status);
2902 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2903 env->msr_global_ovf_ctrl);
2904
2905 /* Now start the PMU. */
2906 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2907 env->msr_fixed_ctr_ctrl);
2908 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2909 env->msr_global_ctrl);
2910 }
0d894367 2911 }
da1cc323
EY		 2912 /*
2913 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2914 * only sync them to KVM on the first cpu
2915 */
2916 if (current_cpu == first_cpu) {
2917 if (has_msr_hv_hypercall) {
2918 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2919 env->msr_hv_guest_os_id);
2920 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2921 env->msr_hv_hypercall);
2922 }
2d384d7c 2923 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2924 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2925 env->msr_hv_tsc);
2926 }
2d384d7c 2927 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2928 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2929 env->msr_hv_reenlightenment_control);
2930 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2931 env->msr_hv_tsc_emulation_control);
2932 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2933 env->msr_hv_tsc_emulation_status);
2934 }
eab70139 2935 }
2d384d7c 2936 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2937 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2938 env->msr_hv_vapic);
eab70139 2939 }
f2a53c9e
AS		 2940 if (has_msr_hv_crash) {
2941 int j;
2942
5e953812 2943 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2944 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2945 env->msr_hv_crash_params[j]);
2946
5e953812 2947 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2948 }
46eb8f98 2949 if (has_msr_hv_runtime) {
9c600a84 2950 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2951 }
2d384d7c
VK		 2952 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2953 && hv_vpindex_settable) {
701189e3
RK		 2954 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2955 hyperv_vp_index(CPU(cpu)));
e9688fab 2956 }
2d384d7c 2957 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2958 int j;
2959
09df29b6
RK		 2960 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2961
9c600a84 2962 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2963 env->msr_hv_synic_control);
9c600a84 2964 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2965 env->msr_hv_synic_evt_page);
9c600a84 2966 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2967 env->msr_hv_synic_msg_page);
2968
2969 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2970 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2971 env->msr_hv_synic_sint[j]);
2972 }
2973 }
ff99aa64
AS		 2974 if (has_msr_hv_stimer) {
2975 int j;
2976
2977 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2978 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2979 env->msr_hv_stimer_config[j]);
2980 }
2981
2982 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2983 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2984 env->msr_hv_stimer_count[j]);
2985 }
2986 }
1eabfce6 2987 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2988 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2989
9c600a84
EH		 2990 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2991 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2992 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2993 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2994 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2995 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2996 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2997 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2998 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2999 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
3000 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
3001 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 3002 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 3003 /* The CPU GPs if we write to a bit above the physical limit of
3004 * the host CPU (and KVM emulates that)
3005 */
3006 uint64_t mask = env->mtrr_var[i].mask;
3007 mask &= phys_mask;
3008
9c600a84
EH		 3009 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
3010 env->mtrr_var[i].base);
112dad69 3011 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 3012 }
3013 }
b77146e9
CP		 3014 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3015 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
3016 0x14, 1, R_EAX) & 0x7;
3017
3018 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
3019 env->msr_rtit_ctrl);
3020 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
3021 env->msr_rtit_status);
3022 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
3023 env->msr_rtit_output_base);
3024 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
3025 env->msr_rtit_output_mask);
3026 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
3027 env->msr_rtit_cr3_match);
3028 for (i = 0; i < addr_num; i++) {
3029 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
3030 env->msr_rtit_addrs[i]);
3031 }
3032 }
6bdf863d
JK		 3033
3034 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
3035 * kvm_put_msr_feature_control. */
ea643051 3036 }
20a78b02 3037
57780495 3038 if (env->mcg_cap) {
d8da8574 3039 int i;
b9bec74b 3040
9c600a84
EH		 3041 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
3042 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 3043 if (has_msr_mcg_ext_ctl) {
3044 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3045 }
c34d440a 3046 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3047 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 3048 }
3049 }
1a03675d 3050
420ae1fc 3051 return kvm_buf_set_msrs(cpu);
05330448
AL		 3052}
3053
3054
1bc22652 3055static int kvm_get_fpu(X86CPU *cpu)
05330448 3056{
1bc22652 3057 CPUX86State *env = &cpu->env;
05330448
AL		 3058 struct kvm_fpu fpu;
3059 int i, ret;
3060
1bc22652 3061 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 3062 if (ret < 0) {
05330448 3063 return ret;
b9bec74b 3064 }
05330448
AL		 3065
3066 env->fpstt = (fpu.fsw >> 11) & 7;
3067 env->fpus = fpu.fsw;
3068 env->fpuc = fpu.fcw;
42cc8fa6
JK		 3069 env->fpop = fpu.last_opcode;
3070 env->fpip = fpu.last_ip;
3071 env->fpdp = fpu.last_dp;
b9bec74b
JK		 3072 for (i = 0; i < 8; ++i) {
3073 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3074 }
05330448 3075 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 3076 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 3077 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3078 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 3079 }
05330448
AL		 3080 env->mxcsr = fpu.mxcsr;
3081
3082 return 0;
3083}
3084
1bc22652 3085static int kvm_get_xsave(X86CPU *cpu)
f1665b21 3086{
1bc22652 3087 CPUX86State *env = &cpu->env;
5b8063c4 3088 X86XSaveArea *xsave = env->xsave_buf;
86a57621 3089 int ret;
f1665b21 3090
28143b40 3091 if (!has_xsave) {
1bc22652 3092 return kvm_get_fpu(cpu);
b9bec74b 3093 }
f1665b21 3094
1bc22652 3095 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 3096 if (ret < 0) {
f1665b21 3097 return ret;
0f53994f 3098 }
86a57621 3099 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 3100
f1665b21 3101 return 0;
f1665b21
SY		 3102}
3103
1bc22652 3104static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 3105{
1bc22652 3106 CPUX86State *env = &cpu->env;
f1665b21
SY		 3107 int i, ret;
3108 struct kvm_xcrs xcrs;
3109
28143b40 3110 if (!has_xcrs) {
f1665b21 3111 return 0;
b9bec74b 3112 }
f1665b21 3113
1bc22652 3114 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 3115 if (ret < 0) {
f1665b21 3116 return ret;
b9bec74b 3117 }
f1665b21 3118
b9bec74b 3119 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 3120 /* Only support xcr0 now */
0fd53fec
PB		 3121 if (xcrs.xcrs[i].xcr == 0) {
3122 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 3123 break;
3124 }
b9bec74b 3125 }
f1665b21 3126 return 0;
f1665b21
SY		 3127}
3128
1bc22652 3129static int kvm_get_sregs(X86CPU *cpu)
05330448 3130{
1bc22652 3131 CPUX86State *env = &cpu->env;
05330448 3132 struct kvm_sregs sregs;
0e607a80 3133 int bit, i, ret;
05330448 3134
1bc22652 3135 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 3136 if (ret < 0) {
05330448 3137 return ret;
b9bec74b 3138 }
05330448 3139
0e607a80
JK		 3140 /* There can only be one pending IRQ set in the bitmap at a time, so try
3141 to find it and save its number instead (-1 for none). */
3142 env->interrupt_injected = -1;
3143 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
3144 if (sregs.interrupt_bitmap[i]) {
3145 bit = ctz64(sregs.interrupt_bitmap[i]);
3146 env->interrupt_injected = i * 64 + bit;
3147 break;
3148 }
3149 }
05330448
AL		 3150
3151 get_seg(&env->segs[R_CS], &sregs.cs);
3152 get_seg(&env->segs[R_DS], &sregs.ds);
3153 get_seg(&env->segs[R_ES], &sregs.es);
3154 get_seg(&env->segs[R_FS], &sregs.fs);
3155 get_seg(&env->segs[R_GS], &sregs.gs);
3156 get_seg(&env->segs[R_SS], &sregs.ss);
3157
3158 get_seg(&env->tr, &sregs.tr);
3159 get_seg(&env->ldt, &sregs.ldt);
3160
3161 env->idt.limit = sregs.idt.limit;
3162 env->idt.base = sregs.idt.base;
3163 env->gdt.limit = sregs.gdt.limit;
3164 env->gdt.base = sregs.gdt.base;
3165
3166 env->cr[0] = sregs.cr0;
3167 env->cr[2] = sregs.cr2;
3168 env->cr[3] = sregs.cr3;
3169 env->cr[4] = sregs.cr4;
3170
05330448 3171 env->efer = sregs.efer;
cce47516
JK		 3172
3173 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 3174 x86_update_hflags(env);
05330448
AL		 3175
3176 return 0;
3177}
3178
1bc22652 3179static int kvm_get_msrs(X86CPU *cpu)
05330448 3180{
1bc22652 3181 CPUX86State *env = &cpu->env;
d71b62a1 3182 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 3183 int ret, i;
fcc35e7c 3184 uint64_t mtrr_top_bits;
05330448 3185
d71b62a1
EH		 3186 kvm_msr_buf_reset(cpu);
3187
9c600a84
EH		 3188 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3189 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3190 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3191 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 3192 if (has_msr_star) {
9c600a84 3193 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 3194 }
c3a3a7d3 3195 if (has_msr_hsave_pa) {
9c600a84 3196 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 3197 }
c9b8f6b6 3198 if (has_msr_tsc_aux) {
9c600a84 3199 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 3200 }
f28558d3 3201 if (has_msr_tsc_adjust) {
9c600a84 3202 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 3203 }
aa82ba54 3204 if (has_msr_tsc_deadline) {
9c600a84 3205 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 3206 }
21e87c46 3207 if (has_msr_misc_enable) {
9c600a84 3208 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 3209 }
fc12d72e 3210 if (has_msr_smbase) {
9c600a84 3211 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 3212 }
e13713db
LA		 3213 if (has_msr_smi_count) {
3214 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3215 }
df67696e 3216 if (has_msr_feature_control) {
9c600a84 3217 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 3218 }
6aa4228b
CQ		 3219 if (has_msr_pkrs) {
3220 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
3221 }
79e9ebeb 3222 if (has_msr_bndcfgs) {
9c600a84 3223 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 3224 }
18cd2c17 3225 if (has_msr_xss) {
9c600a84 3226 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 3227 }
65087997
TX		 3228 if (has_msr_umwait) {
3229 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3230 }
a33a2cfe
PB		 3231 if (has_msr_spec_ctrl) {
3232 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3233 }
2a9758c5
PB		 3234 if (has_msr_tsx_ctrl) {
3235 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3236 }
cfeea0c0
KRW		 3237 if (has_msr_virt_ssbd) {
3238 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3239 }
b8cc45d6 3240 if (!env->tsc_valid) {
9c600a84 3241 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 3242 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 3243 }
3244
05330448 3245#ifdef TARGET_X86_64
25d2e361 3246 if (lm_capable_kernel) {
9c600a84
EH		 3247 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3248 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3249 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3250 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 3251 }
05330448 3252#endif
9c600a84
EH		 3253 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3254 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
db5daafa
VK		 3255 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3256 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3257 }
6615be07
VK		 3258 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3259 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3260 }
55c911a5 3261 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3262 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 3263 }
55c911a5 3264 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3265 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 3266 }
d645e132
MT		 3267 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3268 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3269 }
0b368a10
JD		 3270 if (has_architectural_pmu_version > 0) {
3271 if (has_architectural_pmu_version > 1) {
3272 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3273 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3274 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3275 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3276 }
3277 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3278 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 3279 }
0b368a10 3280 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 3281 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3282 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 3283 }
3284 }
1a03675d 3285
57780495 3286 if (env->mcg_cap) {
9c600a84
EH		 3287 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3288 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 3289 if (has_msr_mcg_ext_ctl) {
3290 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3291 }
b9bec74b 3292 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3293 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 3294 }
57780495 3295 }
57780495 3296
1c90ef26 3297 if (has_msr_hv_hypercall) {
9c600a84
EH		 3298 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3299 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 3300 }
2d384d7c 3301 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3302 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 3303 }
2d384d7c 3304 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 3305 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 3306 }
2d384d7c 3307 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3308 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3309 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3310 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3311 }
f2a53c9e
AS		 3312 if (has_msr_hv_crash) {
3313 int j;
3314
5e953812 3315 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 3316 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 3317 }
3318 }
46eb8f98 3319 if (has_msr_hv_runtime) {
9c600a84 3320 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 3321 }
2d384d7c 3322 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3323 uint32_t msr;
3324
9c600a84 3325 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 3326 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3327 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 3328 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 3329 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 3330 }
3331 }
ff99aa64
AS		 3332 if (has_msr_hv_stimer) {
3333 uint32_t msr;
3334
3335 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3336 msr++) {
9c600a84 3337 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 3338 }
3339 }
1eabfce6 3340 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 3341 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3342 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3343 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3344 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3345 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3346 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3347 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3348 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3349 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3350 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3351 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3352 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 3353 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 3354 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3355 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 3356 }
3357 }
5ef68987 3358
b77146e9
CP		 3359 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3360 int addr_num =
3361 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3362
3363 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3364 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3365 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3366 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3367 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3368 for (i = 0; i < addr_num; i++) {
3369 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3370 }
3371 }
3372
d71b62a1 3373 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 3374 if (ret < 0) {
05330448 3375 return ret;
b9bec74b 3376 }
05330448 3377
c70b11d1
EH		 3378 if (ret < cpu->kvm_msr_buf->nmsrs) {
3379 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3380 error_report("error: failed to get MSR 0x%" PRIx32,
3381 (uint32_t)e->index);
3382 }
3383
9c600a84 3384 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 3385 /*
3386 * MTRR masks: Each mask consists of 5 parts
3387 * a 10..0: must be zero
3388 * b 11 : valid bit
3389 * c n-1.12: actual mask bits
3390 * d 51..n: reserved must be zero
3391 * e 63.52: reserved must be zero
3392 *
3393 * 'n' is the number of physical bits supported by the CPU and is
3394 * apparently always <= 52. We know our 'n' but don't know what
3395 * the destinations 'n' is; it might be smaller, in which case
3396 * it masks (c) on loading. It might be larger, in which case
3397 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3398 * we're migrating to.
3399 */
3400
3401 if (cpu->fill_mtrr_mask) {
3402 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3403 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3404 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3405 } else {
3406 mtrr_top_bits = 0;
3407 }
3408
05330448 3409 for (i = 0; i < ret; i++) {
0d894367
PB		 3410 uint32_t index = msrs[i].index;
3411 switch (index) {
05330448
AL		 3412 case MSR_IA32_SYSENTER_CS:
3413 env->sysenter_cs = msrs[i].data;
3414 break;
3415 case MSR_IA32_SYSENTER_ESP:
3416 env->sysenter_esp = msrs[i].data;
3417 break;
3418 case MSR_IA32_SYSENTER_EIP:
3419 env->sysenter_eip = msrs[i].data;
3420 break;
0c03266a
JK		 3421 case MSR_PAT:
3422 env->pat = msrs[i].data;
3423 break;
05330448
AL		 3424 case MSR_STAR:
3425 env->star = msrs[i].data;
3426 break;
3427#ifdef TARGET_X86_64
3428 case MSR_CSTAR:
3429 env->cstar = msrs[i].data;
3430 break;
3431 case MSR_KERNELGSBASE:
3432 env->kernelgsbase = msrs[i].data;
3433 break;
3434 case MSR_FMASK:
3435 env->fmask = msrs[i].data;
3436 break;
3437 case MSR_LSTAR:
3438 env->lstar = msrs[i].data;
3439 break;
3440#endif
3441 case MSR_IA32_TSC:
3442 env->tsc = msrs[i].data;
3443 break;
c9b8f6b6
AS		 3444 case MSR_TSC_AUX:
3445 env->tsc_aux = msrs[i].data;
3446 break;
f28558d3
WA		 3447 case MSR_TSC_ADJUST:
3448 env->tsc_adjust = msrs[i].data;
3449 break;
aa82ba54
LJ		 3450 case MSR_IA32_TSCDEADLINE:
3451 env->tsc_deadline = msrs[i].data;
3452 break;
aa851e36
MT		 3453 case MSR_VM_HSAVE_PA:
3454 env->vm_hsave = msrs[i].data;
3455 break;
1a03675d
GC		 3456 case MSR_KVM_SYSTEM_TIME:
3457 env->system_time_msr = msrs[i].data;
3458 break;
3459 case MSR_KVM_WALL_CLOCK:
3460 env->wall_clock_msr = msrs[i].data;
3461 break;
57780495
MT		 3462 case MSR_MCG_STATUS:
3463 env->mcg_status = msrs[i].data;
3464 break;
3465 case MSR_MCG_CTL:
3466 env->mcg_ctl = msrs[i].data;
3467 break;
87f8b626
AR		 3468 case MSR_MCG_EXT_CTL:
3469 env->mcg_ext_ctl = msrs[i].data;
3470 break;
21e87c46
AK		 3471 case MSR_IA32_MISC_ENABLE:
3472 env->msr_ia32_misc_enable = msrs[i].data;
3473 break;
fc12d72e
PB		 3474 case MSR_IA32_SMBASE:
3475 env->smbase = msrs[i].data;
3476 break;
e13713db
LA		 3477 case MSR_SMI_COUNT:
3478 env->msr_smi_count = msrs[i].data;
3479 break;
0779caeb
ACL		 3480 case MSR_IA32_FEATURE_CONTROL:
3481 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3482 break;
79e9ebeb
LJ		 3483 case MSR_IA32_BNDCFGS:
3484 env->msr_bndcfgs = msrs[i].data;
3485 break;
18cd2c17
WL		 3486 case MSR_IA32_XSS:
3487 env->xss = msrs[i].data;
3488 break;
65087997
TX		 3489 case MSR_IA32_UMWAIT_CONTROL:
3490 env->umwait = msrs[i].data;
3491 break;
6aa4228b
CQ		 3492 case MSR_IA32_PKRS:
3493 env->pkrs = msrs[i].data;
3494 break;
57780495 3495 default:
57780495
MT		 3496 if (msrs[i].index >= MSR_MC0_CTL &&
3497 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3498 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3499 }
d8da8574 3500 break;
f6584ee2
GN		 3501 case MSR_KVM_ASYNC_PF_EN:
3502 env->async_pf_en_msr = msrs[i].data;
3503 break;
db5daafa
VK		 3504 case MSR_KVM_ASYNC_PF_INT:
3505 env->async_pf_int_msr = msrs[i].data;
3506 break;
bc9a839d
MT		 3507 case MSR_KVM_PV_EOI_EN:
3508 env->pv_eoi_en_msr = msrs[i].data;
3509 break;
917367aa
MT		 3510 case MSR_KVM_STEAL_TIME:
3511 env->steal_time_msr = msrs[i].data;
3512 break;
d645e132
MT		 3513 case MSR_KVM_POLL_CONTROL: {
3514 env->poll_control_msr = msrs[i].data;
3515 break;
3516 }
0d894367
PB		 3517 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3518 env->msr_fixed_ctr_ctrl = msrs[i].data;
3519 break;
3520 case MSR_CORE_PERF_GLOBAL_CTRL:
3521 env->msr_global_ctrl = msrs[i].data;
3522 break;
3523 case MSR_CORE_PERF_GLOBAL_STATUS:
3524 env->msr_global_status = msrs[i].data;
3525 break;
3526 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3527 env->msr_global_ovf_ctrl = msrs[i].data;
3528 break;
3529 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3530 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3531 break;
3532 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3533 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3534 break;
3535 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3536 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3537 break;
1c90ef26
VR		 3538 case HV_X64_MSR_HYPERCALL:
3539 env->msr_hv_hypercall = msrs[i].data;
3540 break;
3541 case HV_X64_MSR_GUEST_OS_ID:
3542 env->msr_hv_guest_os_id = msrs[i].data;
3543 break;
5ef68987
VR		 3544 case HV_X64_MSR_APIC_ASSIST_PAGE:
3545 env->msr_hv_vapic = msrs[i].data;
3546 break;
48a5f3bc
VR		 3547 case HV_X64_MSR_REFERENCE_TSC:
3548 env->msr_hv_tsc = msrs[i].data;
3549 break;
f2a53c9e
AS		 3550 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3551 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3552 break;
46eb8f98
AS		 3553 case HV_X64_MSR_VP_RUNTIME:
3554 env->msr_hv_runtime = msrs[i].data;
3555 break;
866eea9a
AS		 3556 case HV_X64_MSR_SCONTROL:
3557 env->msr_hv_synic_control = msrs[i].data;
3558 break;
866eea9a
AS		 3559 case HV_X64_MSR_SIEFP:
3560 env->msr_hv_synic_evt_page = msrs[i].data;
3561 break;
3562 case HV_X64_MSR_SIMP:
3563 env->msr_hv_synic_msg_page = msrs[i].data;
3564 break;
3565 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3566 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3567 break;
3568 case HV_X64_MSR_STIMER0_CONFIG:
3569 case HV_X64_MSR_STIMER1_CONFIG:
3570 case HV_X64_MSR_STIMER2_CONFIG:
3571 case HV_X64_MSR_STIMER3_CONFIG:
3572 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3573 msrs[i].data;
3574 break;
3575 case HV_X64_MSR_STIMER0_COUNT:
3576 case HV_X64_MSR_STIMER1_COUNT:
3577 case HV_X64_MSR_STIMER2_COUNT:
3578 case HV_X64_MSR_STIMER3_COUNT:
3579 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3580 msrs[i].data;
866eea9a 3581 break;
ba6a4fd9
VK		 3582 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3583 env->msr_hv_reenlightenment_control = msrs[i].data;
3584 break;
3585 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3586 env->msr_hv_tsc_emulation_control = msrs[i].data;
3587 break;
3588 case HV_X64_MSR_TSC_EMULATION_STATUS:
3589 env->msr_hv_tsc_emulation_status = msrs[i].data;
3590 break;
d1ae67f6
AW		 3591 case MSR_MTRRdefType:
3592 env->mtrr_deftype = msrs[i].data;
3593 break;
3594 case MSR_MTRRfix64K_00000:
3595 env->mtrr_fixed[0] = msrs[i].data;
3596 break;
3597 case MSR_MTRRfix16K_80000:
3598 env->mtrr_fixed[1] = msrs[i].data;
3599 break;
3600 case MSR_MTRRfix16K_A0000:
3601 env->mtrr_fixed[2] = msrs[i].data;
3602 break;
3603 case MSR_MTRRfix4K_C0000:
3604 env->mtrr_fixed[3] = msrs[i].data;
3605 break;
3606 case MSR_MTRRfix4K_C8000:
3607 env->mtrr_fixed[4] = msrs[i].data;
3608 break;
3609 case MSR_MTRRfix4K_D0000:
3610 env->mtrr_fixed[5] = msrs[i].data;
3611 break;
3612 case MSR_MTRRfix4K_D8000:
3613 env->mtrr_fixed[6] = msrs[i].data;
3614 break;
3615 case MSR_MTRRfix4K_E0000:
3616 env->mtrr_fixed[7] = msrs[i].data;
3617 break;
3618 case MSR_MTRRfix4K_E8000:
3619 env->mtrr_fixed[8] = msrs[i].data;
3620 break;
3621 case MSR_MTRRfix4K_F0000:
3622 env->mtrr_fixed[9] = msrs[i].data;
3623 break;
3624 case MSR_MTRRfix4K_F8000:
3625 env->mtrr_fixed[10] = msrs[i].data;
3626 break;
3627 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3628 if (index & 1) {
fcc35e7c
DDAG		 3629 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3630 mtrr_top_bits;
d1ae67f6
AW		 3631 } else {
3632 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3633 }
3634 break;
a33a2cfe
PB		 3635 case MSR_IA32_SPEC_CTRL:
3636 env->spec_ctrl = msrs[i].data;
3637 break;
2a9758c5
PB		 3638 case MSR_IA32_TSX_CTRL:
3639 env->tsx_ctrl = msrs[i].data;
3640 break;
cfeea0c0
KRW		 3641 case MSR_VIRT_SSBD:
3642 env->virt_ssbd = msrs[i].data;
3643 break;
b77146e9
CP		 3644 case MSR_IA32_RTIT_CTL:
3645 env->msr_rtit_ctrl = msrs[i].data;
3646 break;
3647 case MSR_IA32_RTIT_STATUS:
3648 env->msr_rtit_status = msrs[i].data;
3649 break;
3650 case MSR_IA32_RTIT_OUTPUT_BASE:
3651 env->msr_rtit_output_base = msrs[i].data;
3652 break;
3653 case MSR_IA32_RTIT_OUTPUT_MASK:
3654 env->msr_rtit_output_mask = msrs[i].data;
3655 break;
3656 case MSR_IA32_RTIT_CR3_MATCH:
3657 env->msr_rtit_cr3_match = msrs[i].data;
3658 break;
3659 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3660 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3661 break;
05330448
AL		 3662 }
3663 }
3664
3665 return 0;
3666}
3667
1bc22652 3668static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3669{
1bc22652 3670 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3671
1bc22652 3672 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3673}
3674
23d02d9b 3675static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3676{
259186a7 3677 CPUState *cs = CPU(cpu);
23d02d9b 3678 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3679 struct kvm_mp_state mp_state;
3680 int ret;
3681
259186a7 3682 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3683 if (ret < 0) {
3684 return ret;
3685 }
3686 env->mp_state = mp_state.mp_state;
c14750e8 3687 if (kvm_irqchip_in_kernel()) {
259186a7 3688 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3689 }
9bdbe550
HB		 3690 return 0;
3691}
3692
1bc22652 3693static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3694{
02e51483 3695 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3696 struct kvm_lapic_state kapic;
3697 int ret;
3698
3d4b2649 3699 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3700 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3701 if (ret < 0) {
3702 return ret;
3703 }
3704
3705 kvm_get_apic_state(apic, &kapic);
3706 }
3707 return 0;
3708}
3709
1bc22652 3710static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3711{
fc12d72e 3712 CPUState *cs = CPU(cpu);
1bc22652 3713 CPUX86State *env = &cpu->env;
076796f8 3714 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3715
3716 if (!kvm_has_vcpu_events()) {
3717 return 0;
3718 }
3719
fd13f23b
LA		 3720 events.flags = 0;
3721
3722 if (has_exception_payload) {
3723 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3724 events.exception.pending = env->exception_pending;
3725 events.exception_has_payload = env->exception_has_payload;
3726 events.exception_payload = env->exception_payload;
3727 }
3728 events.exception.nr = env->exception_nr;
3729 events.exception.injected = env->exception_injected;
a0fb002c
JK		 3730 events.exception.has_error_code = env->has_error_code;
3731 events.exception.error_code = env->error_code;
3732
3733 events.interrupt.injected = (env->interrupt_injected >= 0);
3734 events.interrupt.nr = env->interrupt_injected;
3735 events.interrupt.soft = env->soft_interrupt;
3736
3737 events.nmi.injected = env->nmi_injected;
3738 events.nmi.pending = env->nmi_pending;
3739 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3740
3741 events.sipi_vector = env->sipi_vector;
3742
fc12d72e
PB		 3743 if (has_msr_smbase) {
3744 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3745 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3746 if (kvm_irqchip_in_kernel()) {
3747 /* As soon as these are moved to the kernel, remove them
3748 * from cs->interrupt_request.
3749 */
3750 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3751 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3752 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3753 } else {
3754 /* Keep these in cs->interrupt_request. */
3755 events.smi.pending = 0;
3756 events.smi.latched_init = 0;
3757 }
fc3a1fd7
DDAG		 3758 /* Stop SMI delivery on old machine types to avoid a reboot
3759 * on an inward migration of an old VM.
3760 */
3761 if (!cpu->kvm_no_smi_migration) {
3762 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3763 }
fc12d72e
PB		 3764 }
3765
ea643051 3766 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3767 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3768 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3769 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3770 }
ea643051 3771 }
aee028b9 3772
1bc22652 3773 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3774}
3775
1bc22652 3776static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3777{
1bc22652 3778 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3779 struct kvm_vcpu_events events;
3780 int ret;
3781
3782 if (!kvm_has_vcpu_events()) {
3783 return 0;
3784 }
3785
fc12d72e 3786 memset(&events, 0, sizeof(events));
1bc22652 3787 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3788 if (ret < 0) {
3789 return ret;
3790 }
fd13f23b
LA		 3791
3792 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3793 env->exception_pending = events.exception.pending;
3794 env->exception_has_payload = events.exception_has_payload;
3795 env->exception_payload = events.exception_payload;
3796 } else {
3797 env->exception_pending = 0;
3798 env->exception_has_payload = false;
3799 }
3800 env->exception_injected = events.exception.injected;
3801 env->exception_nr =
3802 (env->exception_pending || env->exception_injected) ?
3803 events.exception.nr : -1;
a0fb002c
JK		 3804 env->has_error_code = events.exception.has_error_code;
3805 env->error_code = events.exception.error_code;
3806
3807 env->interrupt_injected =
3808 events.interrupt.injected ? events.interrupt.nr : -1;
3809 env->soft_interrupt = events.interrupt.soft;
3810
3811 env->nmi_injected = events.nmi.injected;
3812 env->nmi_pending = events.nmi.pending;
3813 if (events.nmi.masked) {
3814 env->hflags2 |= HF2_NMI_MASK;
3815 } else {
3816 env->hflags2 &= ~HF2_NMI_MASK;
3817 }
3818
fc12d72e
PB		 3819 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3820 if (events.smi.smm) {
3821 env->hflags |= HF_SMM_MASK;
3822 } else {
3823 env->hflags &= ~HF_SMM_MASK;
3824 }
3825 if (events.smi.pending) {
3826 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3827 } else {
3828 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3829 }
3830 if (events.smi.smm_inside_nmi) {
3831 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3832 } else {
3833 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3834 }
3835 if (events.smi.latched_init) {
3836 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3837 } else {
3838 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3839 }
3840 }
3841
a0fb002c 3842 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3843
3844 return 0;
3845}
3846
1bc22652 3847static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3848{
ed2803da 3849 CPUState *cs = CPU(cpu);
1bc22652 3850 CPUX86State *env = &cpu->env;
b0b1d690 3851 int ret = 0;
b0b1d690
JK		 3852 unsigned long reinject_trap = 0;
3853
3854 if (!kvm_has_vcpu_events()) {
fd13f23b 3855 if (env->exception_nr == EXCP01_DB) {
b0b1d690 3856 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 3857 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 3858 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3859 }
fd13f23b 3860 kvm_reset_exception(env);
b0b1d690
JK		 3861 }
3862
3863 /*
3864 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3865 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3866 * by updating the debug state once again if single-stepping is on.
3867 * Another reason to call kvm_update_guest_debug here is a pending debug
3868 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3869 * reinject them via SET_GUEST_DEBUG.
3870 */
3871 if (reinject_trap ||
ed2803da 3872 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3873 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3874 }
b0b1d690
JK		 3875 return ret;
3876}
3877
1bc22652 3878static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3879{
1bc22652 3880 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3881 struct kvm_debugregs dbgregs;
3882 int i;
3883
3884 if (!kvm_has_debugregs()) {
3885 return 0;
3886 }
3887
1f670a95 3888 memset(&dbgregs, 0, sizeof(dbgregs));
ff44f1a3
JK		 3889 for (i = 0; i < 4; i++) {
3890 dbgregs.db[i] = env->dr[i];
3891 }
3892 dbgregs.dr6 = env->dr[6];
3893 dbgregs.dr7 = env->dr[7];
3894 dbgregs.flags = 0;
3895
1bc22652 3896 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3897}
3898
1bc22652 3899static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3900{
1bc22652 3901 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3902 struct kvm_debugregs dbgregs;
3903 int i, ret;
3904
3905 if (!kvm_has_debugregs()) {
3906 return 0;
3907 }
3908
1bc22652 3909 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3910 if (ret < 0) {
b9bec74b 3911 return ret;
ff44f1a3
JK		 3912 }
3913 for (i = 0; i < 4; i++) {
3914 env->dr[i] = dbgregs.db[i];
3915 }
3916 env->dr[4] = env->dr[6] = dbgregs.dr6;
3917 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3918
3919 return 0;
3920}
3921
ebbfef2f
LA		 3922static int kvm_put_nested_state(X86CPU *cpu)
3923{
3924 CPUX86State *env = &cpu->env;
3925 int max_nested_state_len = kvm_max_nested_state_length();
3926
1e44f3ab 3927 if (!env->nested_state) {
ebbfef2f
LA		 3928 return 0;
3929 }
3930
b16c0e20
PB		 3931 /*
3932 * Copy flags that are affected by reset from env->hflags and env->hflags2.
3933 */
3934 if (env->hflags & HF_GUEST_MASK) {
3935 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
3936 } else {
3937 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
3938 }
0baa4b44
VK		 3939
3940 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
3941 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
b16c0e20
PB		 3942 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
3943 } else {
3944 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
3945 }
3946
ebbfef2f
LA		 3947 assert(env->nested_state->size <= max_nested_state_len);
3948 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3949}
3950
3951static int kvm_get_nested_state(X86CPU *cpu)
3952{
3953 CPUX86State *env = &cpu->env;
3954 int max_nested_state_len = kvm_max_nested_state_length();
3955 int ret;
3956
1e44f3ab 3957 if (!env->nested_state) {
ebbfef2f
LA		 3958 return 0;
3959 }
3960
3961 /*
3962 * It is possible that migration restored a smaller size into
3963 * nested_state->hdr.size than what our kernel support.
3964 * We preserve migration origin nested_state->hdr.size for
3965 * call to KVM_SET_NESTED_STATE but wish that our next call
3966 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3967 */
3968 env->nested_state->size = max_nested_state_len;
3969
3970 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3971 if (ret < 0) {
3972 return ret;
3973 }
3974
b16c0e20
PB		 3975 /*
3976 * Copy flags that are affected by reset to env->hflags and env->hflags2.
3977 */
ebbfef2f
LA		 3978 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3979 env->hflags |= HF_GUEST_MASK;
3980 } else {
3981 env->hflags &= ~HF_GUEST_MASK;
3982 }
0baa4b44
VK		 3983
3984 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
3985 if (cpu_has_svm(env)) {
3986 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
3987 env->hflags2 |= HF2_GIF_MASK;
3988 } else {
3989 env->hflags2 &= ~HF2_GIF_MASK;
3990 }
b16c0e20 3991 }
ebbfef2f
LA		 3992
3993 return ret;
3994}
3995
20d695a9 3996int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3997{
20d695a9 3998 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3999 int ret;
4000
2fa45344 4001 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 4002
b16c0e20
PB		 4003 /* must be before kvm_put_nested_state so that EFER.SVME is set */
4004 ret = kvm_put_sregs(x86_cpu);
4005 if (ret < 0) {
4006 return ret;
4007 }
4008
48e1a45c 4009 if (level >= KVM_PUT_RESET_STATE) {
bec7156a
JK		 4010 ret = kvm_put_nested_state(x86_cpu);
4011 if (ret < 0) {
4012 return ret;
4013 }
4014
6bdf863d
JK		 4015 ret = kvm_put_msr_feature_control(x86_cpu);
4016 if (ret < 0) {
4017 return ret;
4018 }
4019 }
4020
36f96c4b
HZ		 4021 if (level == KVM_PUT_FULL_STATE) {
4022 /* We don't check for kvm_arch_set_tsc_khz() errors here,
4023 * because TSC frequency mismatch shouldn't abort migration,
4024 * unless the user explicitly asked for a more strict TSC
4025 * setting (e.g. using an explicit "tsc-freq" option).
4026 */
4027 kvm_arch_set_tsc_khz(cpu);
4028 }
4029
1bc22652 4030 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 4031 if (ret < 0) {
05330448 4032 return ret;
b9bec74b 4033 }
1bc22652 4034 ret = kvm_put_xsave(x86_cpu);
b9bec74b 4035 if (ret < 0) {
f1665b21 4036 return ret;
b9bec74b 4037 }
1bc22652 4038 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 4039 if (ret < 0) {
05330448 4040 return ret;
b9bec74b 4041 }
ab443475 4042 /* must be before kvm_put_msrs */
1bc22652 4043 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 4044 if (ret < 0) {
4045 return ret;
4046 }
1bc22652 4047 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 4048 if (ret < 0) {
05330448 4049 return ret;
b9bec74b 4050 }
4fadfa00
PH		 4051 ret = kvm_put_vcpu_events(x86_cpu, level);
4052 if (ret < 0) {
4053 return ret;
4054 }
ea643051 4055 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 4056 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 4057 if (ret < 0) {
680c1c6f
JK		 4058 return ret;
4059 }
ea643051 4060 }
7477cd38
MT		 4061
4062 ret = kvm_put_tscdeadline_msr(x86_cpu);
4063 if (ret < 0) {
4064 return ret;
4065 }
1bc22652 4066 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 4067 if (ret < 0) {
b0b1d690 4068 return ret;
b9bec74b 4069 }
b0b1d690 4070 /* must be last */
1bc22652 4071 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 4072 if (ret < 0) {
ff44f1a3 4073 return ret;
b9bec74b 4074 }
05330448
AL		 4075 return 0;
4076}
4077
20d695a9 4078int kvm_arch_get_registers(CPUState *cs)
05330448 4079{
20d695a9 4080 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 4081 int ret;
4082
20d695a9 4083 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 4084
4fadfa00 4085 ret = kvm_get_vcpu_events(cpu);
b9bec74b 4086 if (ret < 0) {
f4f1110e 4087 goto out;
b9bec74b 4088 }
4fadfa00
PH		 4089 /*
4090 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4091 * KVM_GET_REGS and KVM_GET_SREGS.
4092 */
4093 ret = kvm_get_mp_state(cpu);
b9bec74b 4094 if (ret < 0) {
f4f1110e 4095 goto out;
b9bec74b 4096 }
4fadfa00 4097 ret = kvm_getput_regs(cpu, 0);
b9bec74b 4098 if (ret < 0) {
f4f1110e 4099 goto out;
b9bec74b 4100 }
4fadfa00 4101 ret = kvm_get_xsave(cpu);
b9bec74b 4102 if (ret < 0) {
f4f1110e 4103 goto out;
b9bec74b 4104 }
4fadfa00 4105 ret = kvm_get_xcrs(cpu);
b9bec74b 4106 if (ret < 0) {
f4f1110e 4107 goto out;
b9bec74b 4108 }
4fadfa00 4109 ret = kvm_get_sregs(cpu);
b9bec74b 4110 if (ret < 0) {
f4f1110e 4111 goto out;
b9bec74b 4112 }
4fadfa00 4113 ret = kvm_get_msrs(cpu);
680c1c6f 4114 if (ret < 0) {
f4f1110e 4115 goto out;
680c1c6f 4116 }
4fadfa00 4117 ret = kvm_get_apic(cpu);
b9bec74b 4118 if (ret < 0) {
f4f1110e 4119 goto out;
b9bec74b 4120 }
1bc22652 4121 ret = kvm_get_debugregs(cpu);
b9bec74b 4122 if (ret < 0) {
f4f1110e 4123 goto out;
b9bec74b 4124 }
ebbfef2f
LA		 4125 ret = kvm_get_nested_state(cpu);
4126 if (ret < 0) {
4127 goto out;
4128 }
f4f1110e
RH		 4129 ret = 0;
4130 out:
4131 cpu_sync_bndcs_hflags(&cpu->env);
4132 return ret;
05330448
AL		 4133}
4134
20d695a9 4135void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 4136{
20d695a9
AF		 4137 X86CPU *x86_cpu = X86_CPU(cpu);
4138 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 4139 int ret;
4140
276ce815 4141 /* Inject NMI */
fc12d72e
PB		 4142 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4143 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4144 qemu_mutex_lock_iothread();
4145 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4146 qemu_mutex_unlock_iothread();
4147 DPRINTF("injected NMI\n");
4148 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4149 if (ret < 0) {
4150 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4151 strerror(-ret));
4152 }
4153 }
4154 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4155 qemu_mutex_lock_iothread();
4156 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4157 qemu_mutex_unlock_iothread();
4158 DPRINTF("injected SMI\n");
4159 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4160 if (ret < 0) {
4161 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4162 strerror(-ret));
4163 }
ce377af3 4164 }
276ce815
LJ		 4165 }
4166
15eafc2e 4167 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 4168 qemu_mutex_lock_iothread();
4169 }
4170
e0723c45
PB		 4171 /* Force the VCPU out of its inner loop to process any INIT requests
4172 * or (for userspace APIC, but it is cheap to combine the checks here)
4173 * pending TPR access reports.
4174 */
4175 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 4176 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4177 !(env->hflags & HF_SMM_MASK)) {
4178 cpu->exit_request = 1;
4179 }
4180 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4181 cpu->exit_request = 1;
4182 }
e0723c45 4183 }
05330448 4184
15eafc2e 4185 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 4186 /* Try to inject an interrupt if the guest can accept it */
4187 if (run->ready_for_interrupt_injection &&
259186a7 4188 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 4189 (env->eflags & IF_MASK)) {
4190 int irq;
4191
259186a7 4192 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 4193 irq = cpu_get_pic_interrupt(env);
4194 if (irq >= 0) {
4195 struct kvm_interrupt intr;
4196
4197 intr.irq = irq;
db1669bc 4198 DPRINTF("injected interrupt %d\n", irq);
1bc22652 4199 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 4200 if (ret < 0) {
4201 fprintf(stderr,
4202 "KVM: injection failed, interrupt lost (%s)\n",
4203 strerror(-ret));
4204 }
db1669bc
JK		 4205 }
4206 }
05330448 4207
db1669bc
JK		 4208 /* If we have an interrupt but the guest is not ready to receive an
4209 * interrupt, request an interrupt window exit. This will
4210 * cause a return to userspace as soon as the guest is ready to
4211 * receive interrupts. */
259186a7 4212 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 4213 run->request_interrupt_window = 1;
4214 } else {
4215 run->request_interrupt_window = 0;
4216 }
4217
4218 DPRINTF("setting tpr\n");
02e51483 4219 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 4220
4221 qemu_mutex_unlock_iothread();
db1669bc 4222 }
05330448
AL		 4223}
4224
4c663752 4225MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 4226{
20d695a9
AF		 4227 X86CPU *x86_cpu = X86_CPU(cpu);
4228 CPUX86State *env = &x86_cpu->env;
4229
fc12d72e
PB		 4230 if (run->flags & KVM_RUN_X86_SMM) {
4231 env->hflags |= HF_SMM_MASK;
4232 } else {
f5c052b9 4233 env->hflags &= ~HF_SMM_MASK;
fc12d72e 4234 }
b9bec74b 4235 if (run->if_flag) {
05330448 4236 env->eflags |= IF_MASK;
b9bec74b 4237 } else {
05330448 4238 env->eflags &= ~IF_MASK;
b9bec74b 4239 }
4b8523ee
JK		 4240
4241 /* We need to protect the apic state against concurrent accesses from
4242 * different threads in case the userspace irqchip is used. */
4243 if (!kvm_irqchip_in_kernel()) {
4244 qemu_mutex_lock_iothread();
4245 }
02e51483
CF		 4246 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4247 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 4248 if (!kvm_irqchip_in_kernel()) {
4249 qemu_mutex_unlock_iothread();
4250 }
f794aa4a 4251 return cpu_get_mem_attrs(env);
05330448
AL		 4252}
4253
20d695a9 4254int kvm_arch_process_async_events(CPUState *cs)
0af691d7 4255{
20d695a9
AF		 4256 X86CPU *cpu = X86_CPU(cs);
4257 CPUX86State *env = &cpu->env;
232fc23b 4258
259186a7 4259 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 4260 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4261 assert(env->mcg_cap);
4262
259186a7 4263 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 4264
dd1750d7 4265 kvm_cpu_synchronize_state(cs);
ab443475 4266
fd13f23b 4267 if (env->exception_nr == EXCP08_DBLE) {
ab443475 4268 /* this means triple fault */
cf83f140 4269 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 4270 cs->exit_request = 1;
ab443475
JK		 4271 return 0;
4272 }
fd13f23b 4273 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 4274 env->has_error_code = 0;
4275
259186a7 4276 cs->halted = 0;
ab443475
JK		 4277 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4278 env->mp_state = KVM_MP_STATE_RUNNABLE;
4279 }
4280 }
4281
fc12d72e
PB		 4282 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4283 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 4284 kvm_cpu_synchronize_state(cs);
4285 do_cpu_init(cpu);
4286 }
4287
db1669bc
JK		 4288 if (kvm_irqchip_in_kernel()) {
4289 return 0;
4290 }
4291
259186a7
AF		 4292 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4293 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 4294 apic_poll_irq(cpu->apic_state);
5d62c43a 4295 }
259186a7 4296 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 4297 (env->eflags & IF_MASK)) ||
259186a7
AF		 4298 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4299 cs->halted = 0;
6792a57b 4300 }
259186a7 4301 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 4302 kvm_cpu_synchronize_state(cs);
232fc23b 4303 do_cpu_sipi(cpu);
0af691d7 4304 }
259186a7
AF		 4305 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4306 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 4307 kvm_cpu_synchronize_state(cs);
02e51483 4308 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 4309 env->tpr_access_type);
4310 }
0af691d7 4311
259186a7 4312 return cs->halted;
0af691d7
MT		 4313}
4314
839b5630 4315static int kvm_handle_halt(X86CPU *cpu)
05330448 4316{
259186a7 4317 CPUState *cs = CPU(cpu);
839b5630
AF		 4318 CPUX86State *env = &cpu->env;
4319
259186a7 4320 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 4321 (env->eflags & IF_MASK)) &&
259186a7
AF		 4322 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4323 cs->halted = 1;
bb4ea393 4324 return EXCP_HLT;
05330448
AL		 4325 }
4326
bb4ea393 4327 return 0;
05330448
AL		 4328}
4329
f7575c96 4330static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 4331{
f7575c96
AF		 4332 CPUState *cs = CPU(cpu);
4333 struct kvm_run *run = cs->kvm_run;
d362e757 4334
02e51483 4335 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 4336 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4337 : TPR_ACCESS_READ);
4338 return 1;
4339}
4340
f17ec444 4341int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 4342{
38972938 4343 static const uint8_t int3 = 0xcc;
64bf3f4e 4344
f17ec444
AF		 4345 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4346 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 4347 return -EINVAL;
b9bec74b 4348 }
e22a25c9
AL		 4349 return 0;
4350}
4351
f17ec444 4352int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 4353{
4354 uint8_t int3;
4355
c6986f16
PB		 4356 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
4357 return -EINVAL;
4358 }
4359 if (int3 != 0xcc) {
4360 return 0;
4361 }
4362 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 4363 return -EINVAL;
b9bec74b 4364 }
e22a25c9
AL		 4365 return 0;
4366}
4367
4368static struct {
4369 target_ulong addr;
4370 int len;
4371 int type;
4372} hw_breakpoint[4];
4373
4374static int nb_hw_breakpoint;
4375
4376static int find_hw_breakpoint(target_ulong addr, int len, int type)
4377{
4378 int n;
4379
b9bec74b 4380 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 4381 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 4382 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 4383 return n;
b9bec74b
JK		 4384 }
4385 }
e22a25c9
AL		 4386 return -1;
4387}
4388
4389int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4390 target_ulong len, int type)
4391{
4392 switch (type) {
4393 case GDB_BREAKPOINT_HW:
4394 len = 1;
4395 break;
4396 case GDB_WATCHPOINT_WRITE:
4397 case GDB_WATCHPOINT_ACCESS:
4398 switch (len) {
4399 case 1:
4400 break;
4401 case 2:
4402 case 4:
4403 case 8:
b9bec74b 4404 if (addr & (len - 1)) {
e22a25c9 4405 return -EINVAL;
b9bec74b 4406 }
e22a25c9
AL		 4407 break;
4408 default:
4409 return -EINVAL;
4410 }
4411 break;
4412 default:
4413 return -ENOSYS;
4414 }
4415
b9bec74b 4416 if (nb_hw_breakpoint == 4) {
e22a25c9 4417 return -ENOBUFS;
b9bec74b
JK		 4418 }
4419 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 4420 return -EEXIST;
b9bec74b 4421 }
e22a25c9
AL		 4422 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4423 hw_breakpoint[nb_hw_breakpoint].len = len;
4424 hw_breakpoint[nb_hw_breakpoint].type = type;
4425 nb_hw_breakpoint++;
4426
4427 return 0;
4428}
4429
4430int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4431 target_ulong len, int type)
4432{
4433 int n;
4434
4435 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 4436 if (n < 0) {
e22a25c9 4437 return -ENOENT;
b9bec74b 4438 }
e22a25c9
AL		 4439 nb_hw_breakpoint--;
4440 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4441
4442 return 0;
4443}
4444
4445void kvm_arch_remove_all_hw_breakpoints(void)
4446{
4447 nb_hw_breakpoint = 0;
4448}
4449
4450static CPUWatchpoint hw_watchpoint;
4451
a60f24b5 4452static int kvm_handle_debug(X86CPU *cpu,
48405526 4453 struct kvm_debug_exit_arch *arch_info)
e22a25c9 4454{
ed2803da 4455 CPUState *cs = CPU(cpu);
a60f24b5 4456 CPUX86State *env = &cpu->env;
f2574737 4457 int ret = 0;
e22a25c9
AL		 4458 int n;
4459
37936ac7
LA		 4460 if (arch_info->exception == EXCP01_DB) {
4461 if (arch_info->dr6 & DR6_BS) {
ed2803da 4462 if (cs->singlestep_enabled) {
f2574737 4463 ret = EXCP_DEBUG;
b9bec74b 4464 }
e22a25c9 4465 } else {
b9bec74b
JK		 4466 for (n = 0; n < 4; n++) {
4467 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 4468 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4469 case 0x0:
f2574737 4470 ret = EXCP_DEBUG;
e22a25c9
AL		 4471 break;
4472 case 0x1:
f2574737 4473 ret = EXCP_DEBUG;
ff4700b0 4474 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4475 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4476 hw_watchpoint.flags = BP_MEM_WRITE;
4477 break;
4478 case 0x3:
f2574737 4479 ret = EXCP_DEBUG;
ff4700b0 4480 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4481 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4482 hw_watchpoint.flags = BP_MEM_ACCESS;
4483 break;
4484 }
b9bec74b
JK		 4485 }
4486 }
e22a25c9 4487 }
ff4700b0 4488 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 4489 ret = EXCP_DEBUG;
b9bec74b 4490 }
f2574737 4491 if (ret == 0) {
ff4700b0 4492 cpu_synchronize_state(cs);
fd13f23b 4493 assert(env->exception_nr == -1);
b0b1d690 4494
f2574737 4495 /* pass to guest */
fd13f23b
LA		 4496 kvm_queue_exception(env, arch_info->exception,
4497 arch_info->exception == EXCP01_DB,
4498 arch_info->dr6);
48405526 4499 env->has_error_code = 0;
b0b1d690 4500 }
e22a25c9 4501
f2574737 4502 return ret;
e22a25c9
AL		 4503}
4504
20d695a9 4505void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 4506{
4507 const uint8_t type_code[] = {
4508 [GDB_BREAKPOINT_HW] = 0x0,
4509 [GDB_WATCHPOINT_WRITE] = 0x1,
4510 [GDB_WATCHPOINT_ACCESS] = 0x3
4511 };
4512 const uint8_t len_code[] = {
4513 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4514 };
4515 int n;
4516
a60f24b5 4517 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 4518 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 4519 }
e22a25c9
AL		 4520 if (nb_hw_breakpoint > 0) {
4521 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4522 dbg->arch.debugreg[7] = 0x0600;
4523 for (n = 0; n < nb_hw_breakpoint; n++) {
4524 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4525 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4526 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 4527 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 4528 }
4529 }
4530}
4513d923 4531
2a4dac83
JK		 4532static bool host_supports_vmx(void)
4533{
4534 uint32_t ecx, unused;
4535
4536 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4537 return ecx & CPUID_EXT_VMX;
4538}
4539
4540#define VMX_INVALID_GUEST_STATE 0x80000021
4541
20d695a9 4542int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 4543{
20d695a9 4544 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 4545 uint64_t code;
4546 int ret;
4547
4548 switch (run->exit_reason) {
4549 case KVM_EXIT_HLT:
4550 DPRINTF("handle_hlt\n");
4b8523ee 4551 qemu_mutex_lock_iothread();
839b5630 4552 ret = kvm_handle_halt(cpu);
4b8523ee 4553 qemu_mutex_unlock_iothread();
2a4dac83
JK		 4554 break;
4555 case KVM_EXIT_SET_TPR:
4556 ret = 0;
4557 break;
d362e757 4558 case KVM_EXIT_TPR_ACCESS:
4b8523ee 4559 qemu_mutex_lock_iothread();
f7575c96 4560 ret = kvm_handle_tpr_access(cpu);
4b8523ee 4561 qemu_mutex_unlock_iothread();
d362e757 4562 break;
2a4dac83
JK		 4563 case KVM_EXIT_FAIL_ENTRY:
4564 code = run->fail_entry.hardware_entry_failure_reason;
4565 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4566 code);
4567 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4568 fprintf(stderr,
12619721 4569 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 4570 "unrestricted mode\n"
4571 "support, the failure can be most likely due to the guest "
4572 "entering an invalid\n"
4573 "state for Intel VT. For example, the guest maybe running "
4574 "in big real mode\n"
4575 "which is not supported on less recent Intel processors."
4576 "\n\n");
4577 }
4578 ret = -1;
4579 break;
4580 case KVM_EXIT_EXCEPTION:
4581 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4582 run->ex.exception, run->ex.error_code);
4583 ret = -1;
4584 break;
f2574737
JK		 4585 case KVM_EXIT_DEBUG:
4586 DPRINTF("kvm_exit_debug\n");
4b8523ee 4587 qemu_mutex_lock_iothread();
a60f24b5 4588 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 4589 qemu_mutex_unlock_iothread();
f2574737 4590 break;
50efe82c
AS		 4591 case KVM_EXIT_HYPERV:
4592 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4593 break;
15eafc2e
PB		 4594 case KVM_EXIT_IOAPIC_EOI:
4595 ioapic_eoi_broadcast(run->eoi.vector);
4596 ret = 0;
4597 break;
2a4dac83
JK		 4598 default:
4599 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4600 ret = -1;
4601 break;
4602 }
4603
4604 return ret;
4605}
4606
20d695a9 4607bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4608{
20d695a9
AF		 4609 X86CPU *cpu = X86_CPU(cs);
4610 CPUX86State *env = &cpu->env;
4611
dd1750d7 4612 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4613 return !(env->cr[0] & CR0_PE_MASK) ||
4614 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4615}
84b058d7
JK		 4616
4617void kvm_arch_init_irq_routing(KVMState *s)
4618{
cc7e0ddf 4619 /* We know at this point that we're using the in-kernel
614e41bc 4620 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4621 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4622 */
614e41bc 4623 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4624 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4625
4626 if (kvm_irqchip_is_split()) {
4627 int i;
4628
4629 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4630 MSI routes for signaling interrupts to the local apics. */
4631 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4632 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4633 error_report("Could not enable split IRQ mode.");
4634 exit(1);
4635 }
4636 }
4637 }
4638}
4639
4376c40d 4640int kvm_arch_irqchip_create(KVMState *s)
15eafc2e
PB		 4641{
4642 int ret;
4376c40d 4643 if (kvm_kernel_irqchip_split()) {
15eafc2e
PB		 4644 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4645 if (ret) {
df3c286c 4646 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4647 strerror(-ret));
4648 exit(1);
4649 } else {
4650 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4651 kvm_split_irqchip = true;
4652 return 1;
4653 }
4654 } else {
4655 return 0;
4656 }
84b058d7 4657}
b139bd30 4658
c1bb5418
DW		 4659uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
4660{
4661 CPUX86State *env;
4662 uint64_t ext_id;
4663
4664 if (!first_cpu) {
4665 return address;
4666 }
4667 env = &X86_CPU(first_cpu)->env;
4668 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
4669 return address;
4670 }
4671
4672 /*
4673 * If the remappable format bit is set, or the upper bits are
4674 * already set in address_hi, or the low extended bits aren't
4675 * there anyway, do nothing.
4676 */
4677 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
4678 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
4679 return address;
4680 }
4681
4682 address &= ~ext_id;
4683 address |= ext_id << 35;
4684 return address;
4685}
4686
9e03a040 4687int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4688 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4689{
8b5ed7df
PX		 4690 X86IOMMUState *iommu = x86_iommu_get_default();
4691
4692 if (iommu) {
30c60f77 4693 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
8b5ed7df 4694
c1bb5418
DW		 4695 if (class->int_remap) {
4696 int ret;
4697 MSIMessage src, dst;
0ea1472d 4698
c1bb5418
DW		 4699 src.address = route->u.msi.address_hi;
4700 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4701 src.address |= route->u.msi.address_lo;
4702 src.data = route->u.msi.data;
8b5ed7df 4703
c1bb5418
DW		 4704 ret = class->int_remap(iommu, &src, &dst, dev ? \
4705 pci_requester_id(dev) : \
4706 X86_IOMMU_SID_INVALID);
4707 if (ret) {
4708 trace_kvm_x86_fixup_msi_error(route->gsi);
4709 return 1;
4710 }
4711
4712 /*
4713 * Handled untranslated compatibilty format interrupt with
4714 * extended destination ID in the low bits 11-5. */
4715 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
8b5ed7df 4716
c1bb5418
DW		 4717 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4718 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4719 route->u.msi.data = dst.data;
4720 return 0;
4721 }
8b5ed7df
PX		 4722 }
4723
c1bb5418
DW		 4724 address = kvm_swizzle_msi_ext_dest_id(address);
4725 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
4726 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
9e03a040
FB		 4727 return 0;
4728}
1850b6b7 4729
38d87493
PX		 4730typedef struct MSIRouteEntry MSIRouteEntry;
4731
4732struct MSIRouteEntry {
4733 PCIDevice *dev; /* Device pointer */
4734 int vector; /* MSI/MSIX vector index */
4735 int virq; /* Virtual IRQ index */
4736 QLIST_ENTRY(MSIRouteEntry) list;
4737};
4738
4739/* List of used GSI routes */
4740static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4741 QLIST_HEAD_INITIALIZER(msi_route_list);
4742
e1d4fb2d
PX		 4743static void kvm_update_msi_routes_all(void *private, bool global,
4744 uint32_t index, uint32_t mask)
4745{
a56de056 4746 int cnt = 0, vector;
e1d4fb2d
PX		 4747 MSIRouteEntry *entry;
4748 MSIMessage msg;
fd563564
PX		 4749 PCIDevice *dev;
4750
e1d4fb2d
PX		 4751 /* TODO: explicit route update */
4752 QLIST_FOREACH(entry, &msi_route_list, list) {
4753 cnt++;
a56de056 4754 vector = entry->vector;
fd563564 4755 dev = entry->dev;
a56de056
PX		 4756 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4757 msg = msix_get_message(dev, vector);
4758 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4759 msg = msi_get_message(dev, vector);
4760 } else {
4761 /*
4762 * Either MSI/MSIX is disabled for the device, or the
4763 * specific message was masked out. Skip this one.
4764 */
fd563564
PX		 4765 continue;
4766 }
fd563564 4767 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4768 }
3f1fea0f 4769 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4770 trace_kvm_x86_update_msi_routes(cnt);
4771}
4772
38d87493
PX		 4773int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4774 int vector, PCIDevice *dev)
4775{
e1d4fb2d 4776 static bool notify_list_inited = false;
38d87493
PX		 4777 MSIRouteEntry *entry;
4778
4779 if (!dev) {
4780 /* These are (possibly) IOAPIC routes only used for split
4781 * kernel irqchip mode, while what we are housekeeping are
4782 * PCI devices only. */
4783 return 0;
4784 }
4785
4786 entry = g_new0(MSIRouteEntry, 1);
4787 entry->dev = dev;
4788 entry->vector = vector;
4789 entry->virq = route->gsi;
4790 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4791
4792 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4793
4794 if (!notify_list_inited) {
4795 /* For the first time we do add route, add ourselves into
4796 * IOMMU's IEC notify list if needed. */
4797 X86IOMMUState *iommu = x86_iommu_get_default();
4798 if (iommu) {
4799 x86_iommu_iec_register_notifier(iommu,
4800 kvm_update_msi_routes_all,
4801 NULL);
4802 }
4803 notify_list_inited = true;
4804 }
38d87493
PX		 4805 return 0;
4806}
4807
4808int kvm_arch_release_virq_post(int virq)
4809{
4810 MSIRouteEntry *entry, *next;
4811 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4812 if (entry->virq == virq) {
4813 trace_kvm_x86_remove_msi_route(virq);
4814 QLIST_REMOVE(entry, list);
01960e6d 4815 g_free(entry);
38d87493
PX		 4816 break;
4817 }
4818 }
9e03a040
FB		 4819 return 0;
4820}
1850b6b7
EA		 4821
4822int kvm_arch_msi_data_to_gsi(uint32_t data)
4823{
4824 abort();
4825}
e1e43813
PB		 4826
4827bool kvm_has_waitpkg(void)
4828{
4829 return has_msr_umwait;
4830}
92a5199b
TL		 4831
4832bool kvm_arch_cpu_check_are_resettable(void)
4833{
4834 return !sev_es_enabled();
4835}
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