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target/i386: Clarify the padding requirements of X86XSaveArea
[mirror_qemu.git] / target / i386 / kvm / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
8efc4e51 16#include "qapi/qapi-events-run-state.h"
da34e65c 17#include "qapi/error.h"
05330448 18#include <sys/ioctl.h>
25d2e361 19#include <sys/utsname.h>
05330448
AL		 20
21#include <linux/kvm.h>
1814eab6 22#include "standard-headers/asm-x86/kvm_para.h"
05330448 23
33c11879 24#include "cpu.h"
f5cc5a5c 25#include "host-cpu.h"
9c17d615 26#include "sysemu/sysemu.h"
b3946626 27#include "sysemu/hw_accel.h"
6410848b 28#include "sysemu/kvm_int.h"
54d31236 29#include "sysemu/runstate.h"
1d31f66b 30#include "kvm_i386.h"
92a5199b 31#include "sev_i386.h"
50efe82c 32#include "hyperv.h"
5e953812 33#include "hyperv-proto.h"
50efe82c 34
022c62cb 35#include "exec/gdbstub.h"
1de7afc9 36#include "qemu/host-utils.h"
db725815 37#include "qemu/main-loop.h"
1de7afc9 38#include "qemu/config-file.h"
1c4a55db 39#include "qemu/error-report.h"
89a289c7 40#include "hw/i386/x86.h"
0d09e41a 41#include "hw/i386/apic.h"
e0723c45
PB		 42#include "hw/i386/apic_internal.h"
43#include "hw/i386/apic-msidef.h"
8b5ed7df 44#include "hw/i386/intel_iommu.h"
e1d4fb2d 45#include "hw/i386/x86-iommu.h"
d6d059ca 46#include "hw/i386/e820_memory_layout.h"
ec78e2cd 47#include "sysemu/sev.h"
50efe82c 48
a2cb15b0 49#include "hw/pci/pci.h"
15eafc2e 50#include "hw/pci/msi.h"
fd563564 51#include "hw/pci/msix.h"
795c40b8 52#include "migration/blocker.h"
4c663752 53#include "exec/memattrs.h"
8b5ed7df 54#include "trace.h"
05330448
AL		 55
56//#define DEBUG_KVM
57
58#ifdef DEBUG_KVM
8c0d577e 59#define DPRINTF(fmt, ...) \
05330448
AL		 60 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
61#else
8c0d577e 62#define DPRINTF(fmt, ...) \
05330448
AL		 63 do { } while (0)
64#endif
65
73b994f6
LA		 66/* From arch/x86/kvm/lapic.h */
67#define KVM_APIC_BUS_CYCLE_NS 1
68#define KVM_APIC_BUS_FREQUENCY (1000000000ULL / KVM_APIC_BUS_CYCLE_NS)
69
1a03675d
GC		 70#define MSR_KVM_WALL_CLOCK 0x11
71#define MSR_KVM_SYSTEM_TIME 0x12
72
d1138251
EH		 73/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
74 * 255 kvm_msr_entry structs */
75#define MSR_BUF_SIZE 4096
d71b62a1 76
420ae1fc
PB		 77static void kvm_init_msrs(X86CPU *cpu);
78
94a8d39a
JK		 79const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
80 KVM_CAP_INFO(SET_TSS_ADDR),
81 KVM_CAP_INFO(EXT_CPUID),
82 KVM_CAP_INFO(MP_STATE),
83 KVM_CAP_LAST_INFO
84};
25d2e361 85
c3a3a7d3
JK		 86static bool has_msr_star;
87static bool has_msr_hsave_pa;
c9b8f6b6 88static bool has_msr_tsc_aux;
f28558d3 89static bool has_msr_tsc_adjust;
aa82ba54 90static bool has_msr_tsc_deadline;
df67696e 91static bool has_msr_feature_control;
21e87c46 92static bool has_msr_misc_enable;
fc12d72e 93static bool has_msr_smbase;
79e9ebeb 94static bool has_msr_bndcfgs;
25d2e361 95static int lm_capable_kernel;
7bc3d711 96static bool has_msr_hv_hypercall;
f2a53c9e 97static bool has_msr_hv_crash;
744b8a94 98static bool has_msr_hv_reset;
8c145d7c 99static bool has_msr_hv_vpindex;
e9688fab 100static bool hv_vpindex_settable;
46eb8f98 101static bool has_msr_hv_runtime;
866eea9a 102static bool has_msr_hv_synic;
ff99aa64 103static bool has_msr_hv_stimer;
d72bc7f6 104static bool has_msr_hv_frequencies;
ba6a4fd9 105static bool has_msr_hv_reenlightenment;
18cd2c17 106static bool has_msr_xss;
65087997 107static bool has_msr_umwait;
a33a2cfe 108static bool has_msr_spec_ctrl;
2a9758c5 109static bool has_msr_tsx_ctrl;
cfeea0c0 110static bool has_msr_virt_ssbd;
e13713db 111static bool has_msr_smi_count;
aec5e9c3 112static bool has_msr_arch_capabs;
597360c0 113static bool has_msr_core_capabs;
20a78b02 114static bool has_msr_vmx_vmfunc;
67025148 115static bool has_msr_ucode_rev;
4a910e1f 116static bool has_msr_vmx_procbased_ctls2;
ea39f9b6 117static bool has_msr_perf_capabs;
6aa4228b 118static bool has_msr_pkrs;
b827df58 119
0b368a10
JD		 120static uint32_t has_architectural_pmu_version;
121static uint32_t num_architectural_pmu_gp_counters;
122static uint32_t num_architectural_pmu_fixed_counters;
0d894367 123
28143b40
TH		 124static int has_xsave;
125static int has_xcrs;
126static int has_pit_state2;
fd13f23b 127static int has_exception_payload;
28143b40 128
87f8b626
AR		 129static bool has_msr_mcg_ext_ctl;
130
494e95e9 131static struct kvm_cpuid2 *cpuid_cache;
a8439be6 132static struct kvm_cpuid2 *hv_cpuid_cache;
f57bceb6 133static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 134
035d1ef2
CQ		 135#define BUS_LOCK_SLICE_TIME 1000000000ULL /* ns */
136static RateLimit bus_lock_ratelimit_ctrl;
137
28143b40
TH		 138int kvm_has_pit_state2(void)
139{
140 return has_pit_state2;
141}
142
355023f2
PB		 143bool kvm_has_smm(void)
144{
23edf8b5 145 return kvm_vm_check_extension(kvm_state, KVM_CAP_X86_SMM);
355023f2
PB		 146}
147
6053a86f
MT		 148bool kvm_has_adjust_clock_stable(void)
149{
150 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
151
152 return (ret == KVM_CLOCK_TSC_STABLE);
153}
154
8700a984
VK		 155bool kvm_has_adjust_clock(void)
156{
157 return kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
158}
159
79a197ab
LA		 160bool kvm_has_exception_payload(void)
161{
162 return has_exception_payload;
163}
164
fb506e70
RK		 165static bool kvm_x2apic_api_set_flags(uint64_t flags)
166{
4f7f5893 167 KVMState *s = KVM_STATE(current_accel());
fb506e70
RK		 168
169 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
170}
171
e391c009 172#define MEMORIZE(fn, _result) \
2a138ec3 173 ({ \
2a138ec3
RK		 174 static bool _memorized; \
175 \
176 if (_memorized) { \
177 return _result; \
178 } \
179 _memorized = true; \
180 _result = fn; \
181 })
182
e391c009
IM		 183static bool has_x2apic_api;
184
185bool kvm_has_x2apic_api(void)
186{
187 return has_x2apic_api;
188}
189
fb506e70
RK		 190bool kvm_enable_x2apic(void)
191{
2a138ec3
RK		 192 return MEMORIZE(
193 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 194 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
195 has_x2apic_api);
fb506e70
RK		 196}
197
e9688fab
RK		 198bool kvm_hv_vpindex_settable(void)
199{
200 return hv_vpindex_settable;
201}
202
0fd7e098
LL		 203static int kvm_get_tsc(CPUState *cs)
204{
205 X86CPU *cpu = X86_CPU(cs);
206 CPUX86State *env = &cpu->env;
207 struct {
208 struct kvm_msrs info;
209 struct kvm_msr_entry entries[1];
a1834d97 210 } msr_data = {};
0fd7e098
LL		 211 int ret;
212
213 if (env->tsc_valid) {
214 return 0;
215 }
216
1f670a95 217 memset(&msr_data, 0, sizeof(msr_data));
0fd7e098
LL		 218 msr_data.info.nmsrs = 1;
219 msr_data.entries[0].index = MSR_IA32_TSC;
220 env->tsc_valid = !runstate_is_running();
221
222 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
223 if (ret < 0) {
224 return ret;
225 }
226
48e1a45c 227 assert(ret == 1);
0fd7e098
LL		 228 env->tsc = msr_data.entries[0].data;
229 return 0;
230}
231
14e6fe12 232static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 233{
0fd7e098
LL		 234 kvm_get_tsc(cpu);
235}
236
237void kvm_synchronize_all_tsc(void)
238{
239 CPUState *cpu;
240
241 if (kvm_enabled()) {
242 CPU_FOREACH(cpu) {
14e6fe12 243 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 244 }
245 }
246}
247
b827df58
AK		 248static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
249{
250 struct kvm_cpuid2 *cpuid;
251 int r, size;
252
253 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 254 cpuid = g_malloc0(size);
b827df58
AK		 255 cpuid->nent = max;
256 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 257 if (r == 0 && cpuid->nent >= max) {
258 r = -E2BIG;
259 }
b827df58
AK		 260 if (r < 0) {
261 if (r == -E2BIG) {
7267c094 262 g_free(cpuid);
b827df58
AK		 263 return NULL;
264 } else {
265 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
266 strerror(-r));
267 exit(1);
268 }
269 }
270 return cpuid;
271}
272
dd87f8a6
EH		 273/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
274 * for all entries.
275 */
276static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
277{
278 struct kvm_cpuid2 *cpuid;
279 int max = 1;
494e95e9
CP		 280
281 if (cpuid_cache != NULL) {
282 return cpuid_cache;
283 }
dd87f8a6
EH		 284 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
285 max *= 2;
286 }
494e95e9 287 cpuid_cache = cpuid;
dd87f8a6
EH		 288 return cpuid;
289}
290
b199c682 291static bool host_tsx_broken(void)
40e80ee4
EH		 292{
293 int family, model, stepping;\
294 char vendor[CPUID_VENDOR_SZ + 1];
295
f5cc5a5c 296 host_cpu_vendor_fms(vendor, &family, &model, &stepping);
40e80ee4
EH		 297
298 /* Check if we are running on a Haswell host known to have broken TSX */
299 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
300 (family == 6) &&
301 ((model == 63 && stepping < 4) ||
302 model == 60 || model == 69 || model == 70);
303}
0c31b744 304
829ae2f9
EH		 305/* Returns the value for a specific register on the cpuid entry
306 */
307static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
308{
309 uint32_t ret = 0;
310 switch (reg) {
311 case R_EAX:
312 ret = entry->eax;
313 break;
314 case R_EBX:
315 ret = entry->ebx;
316 break;
317 case R_ECX:
318 ret = entry->ecx;
319 break;
320 case R_EDX:
321 ret = entry->edx;
322 break;
323 }
324 return ret;
325}
326
4fb73f1d
EH		 327/* Find matching entry for function/index on kvm_cpuid2 struct
328 */
329static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
330 uint32_t function,
331 uint32_t index)
332{
333 int i;
334 for (i = 0; i < cpuid->nent; ++i) {
335 if (cpuid->entries[i].function == function &&
336 cpuid->entries[i].index == index) {
337 return &cpuid->entries[i];
338 }
339 }
340 /* not found: */
341 return NULL;
342}
343
ba9bc59e 344uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 345 uint32_t index, int reg)
b827df58
AK		 346{
347 struct kvm_cpuid2 *cpuid;
b827df58
AK		 348 uint32_t ret = 0;
349 uint32_t cpuid_1_edx;
350
dd87f8a6 351 cpuid = get_supported_cpuid(s);
b827df58 352
4fb73f1d
EH		 353 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
354 if (entry) {
4fb73f1d 355 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 356 }
357
7b46e5ce
EH		 358 /* Fixups for the data returned by KVM, below */
359
c2acb022
EH		 360 if (function == 1 && reg == R_EDX) {
361 /* KVM before 2.6.30 misreports the following features */
362 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 363 } else if (function == 1 && reg == R_ECX) {
364 /* We can set the hypervisor flag, even if KVM does not return it on
365 * GET_SUPPORTED_CPUID
366 */
367 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 368 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
369 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
370 * and the irqchip is in the kernel.
371 */
372 if (kvm_irqchip_in_kernel() &&
373 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
374 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
375 }
41e5e76d
EH		 376
377 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
378 * without the in-kernel irqchip
379 */
380 if (!kvm_irqchip_in_kernel()) {
381 ret &= ~CPUID_EXT_X2APIC;
b827df58 382 }
2266d443
MT		 383
384 if (enable_cpu_pm) {
385 int disable_exits = kvm_check_extension(s,
386 KVM_CAP_X86_DISABLE_EXITS);
387
388 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
389 ret |= CPUID_EXT_MONITOR;
390 }
391 }
28b8e4d0
JK		 392 } else if (function == 6 && reg == R_EAX) {
393 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4 394 } else if (function == 7 && index == 0 && reg == R_EBX) {
b199c682 395 if (host_tsx_broken()) {
40e80ee4
EH		 396 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
397 }
485b1d25
EH		 398 } else if (function == 7 && index == 0 && reg == R_EDX) {
399 /*
400 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
401 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
402 * returned by KVM_GET_MSR_INDEX_LIST.
403 */
404 if (!has_msr_arch_capabs) {
405 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
406 }
f98bbd83
BM		 407 } else if (function == 0x80000001 && reg == R_ECX) {
408 /*
409 * It's safe to enable TOPOEXT even if it's not returned by
410 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
411 * us to keep CPU models including TOPOEXT runnable on older kernels.
412 */
413 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 414 } else if (function == 0x80000001 && reg == R_EDX) {
415 /* On Intel, kvm returns cpuid according to the Intel spec,
416 * so add missing bits according to the AMD spec:
417 */
418 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
419 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 420 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
421 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
422 * be enabled without the in-kernel irqchip
423 */
424 if (!kvm_irqchip_in_kernel()) {
425 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
426 }
c1bb5418
DW		 427 if (kvm_irqchip_is_split()) {
428 ret |= 1U << KVM_FEATURE_MSI_EXT_DEST_ID;
429 }
be777326 430 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 431 ret |= 1U << KVM_HINTS_REALTIME;
b9bec74b 432 }
0c31b744
GC		 433
434 return ret;
bb0300dc 435}
bb0300dc 436
ede146c2 437uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
f57bceb6
RH		 438{
439 struct {
440 struct kvm_msrs info;
441 struct kvm_msr_entry entries[1];
a1834d97 442 } msr_data = {};
20a78b02
PB		 443 uint64_t value;
444 uint32_t ret, can_be_one, must_be_one;
f57bceb6
RH		 445
446 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
447 return 0;
448 }
449
450 /* Check if requested MSR is supported feature MSR */
451 int i;
452 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
453 if (kvm_feature_msrs->indices[i] == index) {
454 break;
455 }
456 if (i == kvm_feature_msrs->nmsrs) {
457 return 0; /* if the feature MSR is not supported, simply return 0 */
458 }
459
460 msr_data.info.nmsrs = 1;
461 msr_data.entries[0].index = index;
462
463 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
464 if (ret != 1) {
465 error_report("KVM get MSR (index=0x%x) feature failed, %s",
466 index, strerror(-ret));
467 exit(1);
468 }
469
20a78b02
PB		 470 value = msr_data.entries[0].data;
471 switch (index) {
472 case MSR_IA32_VMX_PROCBASED_CTLS2:
4a910e1f
VK		 473 if (!has_msr_vmx_procbased_ctls2) {
474 /* KVM forgot to add these bits for some time, do this ourselves. */
475 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) &
476 CPUID_XSAVE_XSAVES) {
477 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
478 }
479 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) &
480 CPUID_EXT_RDRAND) {
481 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
482 }
483 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
484 CPUID_7_0_EBX_INVPCID) {
485 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
486 }
487 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) &
488 CPUID_7_0_EBX_RDSEED) {
489 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
490 }
491 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) &
492 CPUID_EXT2_RDTSCP) {
493 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
494 }
048c9516
PB		 495 }
496 /* fall through */
20a78b02
PB		 497 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
498 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
499 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
500 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
501 /*
502 * Return true for bits that can be one, but do not have to be one.
503 * The SDM tells us which bits could have a "must be one" setting,
504 * so we can do the opposite transformation in make_vmx_msr_value.
505 */
506 must_be_one = (uint32_t)value;
507 can_be_one = (uint32_t)(value >> 32);
508 return can_be_one & ~must_be_one;
509
510 default:
511 return value;
512 }
f57bceb6
RH		 513}
514
e7701825
MT		 515static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
516 int *max_banks)
517{
518 int r;
519
14a09518 520 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 521 if (r > 0) {
522 *max_banks = r;
523 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
524 }
525 return -ENOSYS;
526}
527
bee615d4 528static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 529{
87f8b626 530 CPUState *cs = CPU(cpu);
bee615d4 531 CPUX86State *env = &cpu->env;
c34d440a
JK		 532 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
533 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
534 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 535 int flags = 0;
e7701825 536
c34d440a
JK		 537 if (code == BUS_MCEERR_AR) {
538 status |= MCI_STATUS_AR | 0x134;
539 mcg_status |= MCG_STATUS_EIPV;
540 } else {
541 status |= 0xc0;
542 mcg_status |= MCG_STATUS_RIPV;
419fb20a 543 }
87f8b626
AR		 544
545 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
546 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
547 * guest kernel back into env->mcg_ext_ctl.
548 */
549 cpu_synchronize_state(cs);
550 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
551 mcg_status |= MCG_STATUS_LMCE;
552 flags = 0;
553 }
554
8c5cf3b6 555 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 556 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 557}
419fb20a 558
8efc4e51
ZP		 559static void emit_hypervisor_memory_failure(MemoryFailureAction action, bool ar)
560{
561 MemoryFailureFlags mff = {.action_required = ar, .recursive = false};
562
563 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_HYPERVISOR, action,
564 &mff);
565}
566
73284563 567static void hardware_memory_error(void *host_addr)
419fb20a 568{
8efc4e51 569 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_FATAL, true);
73284563 570 error_report("QEMU got Hardware memory error at addr %p", host_addr);
419fb20a
JK		 571 exit(1);
572}
573
2ae41db2 574void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 575{
20d695a9
AF		 576 X86CPU *cpu = X86_CPU(c);
577 CPUX86State *env = &cpu->env;
419fb20a 578 ram_addr_t ram_addr;
a8170e5e 579 hwaddr paddr;
419fb20a 580
4d39892c
PB		 581 /* If we get an action required MCE, it has been injected by KVM
582 * while the VM was running. An action optional MCE instead should
583 * be coming from the main thread, which qemu_init_sigbus identifies
584 * as the "early kill" thread.
585 */
a16fc07e 586 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 587
20e0ff59 588 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 589 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 590 if (ram_addr != RAM_ADDR_INVALID &&
591 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
592 kvm_hwpoison_page_add(ram_addr);
593 kvm_mce_inject(cpu, paddr, code);
73284563
MS		 594
595 /*
596 * Use different logging severity based on error type.
597 * If there is additional MCE reporting on the hypervisor, QEMU VA
598 * could be another source to identify the PA and MCE details.
599 */
600 if (code == BUS_MCEERR_AR) {
601 error_report("Guest MCE Memory Error at QEMU addr %p and "
602 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
603 addr, paddr, "BUS_MCEERR_AR");
604 } else {
605 warn_report("Guest MCE Memory Error at QEMU addr %p and "
606 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
607 addr, paddr, "BUS_MCEERR_AO");
608 }
609
2ae41db2 610 return;
419fb20a 611 }
20e0ff59 612
73284563
MS		 613 if (code == BUS_MCEERR_AO) {
614 warn_report("Hardware memory error at addr %p of type %s "
615 "for memory used by QEMU itself instead of guest system!",
616 addr, "BUS_MCEERR_AO");
617 }
419fb20a 618 }
20e0ff59
PB		 619
620 if (code == BUS_MCEERR_AR) {
73284563 621 hardware_memory_error(addr);
20e0ff59
PB		 622 }
623
8efc4e51
ZP		 624 /* Hope we are lucky for AO MCE, just notify a event */
625 emit_hypervisor_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, false);
419fb20a
JK		 626}
627
fd13f23b
LA		 628static void kvm_reset_exception(CPUX86State *env)
629{
630 env->exception_nr = -1;
631 env->exception_pending = 0;
632 env->exception_injected = 0;
633 env->exception_has_payload = false;
634 env->exception_payload = 0;
635}
636
637static void kvm_queue_exception(CPUX86State *env,
638 int32_t exception_nr,
639 uint8_t exception_has_payload,
640 uint64_t exception_payload)
641{
642 assert(env->exception_nr == -1);
643 assert(!env->exception_pending);
644 assert(!env->exception_injected);
645 assert(!env->exception_has_payload);
646
647 env->exception_nr = exception_nr;
648
649 if (has_exception_payload) {
650 env->exception_pending = 1;
651
652 env->exception_has_payload = exception_has_payload;
653 env->exception_payload = exception_payload;
654 } else {
655 env->exception_injected = 1;
656
657 if (exception_nr == EXCP01_DB) {
658 assert(exception_has_payload);
659 env->dr[6] = exception_payload;
660 } else if (exception_nr == EXCP0E_PAGE) {
661 assert(exception_has_payload);
662 env->cr[2] = exception_payload;
663 } else {
664 assert(!exception_has_payload);
665 }
666 }
667}
668
1bc22652 669static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 670{
1bc22652
AF		 671 CPUX86State *env = &cpu->env;
672
fd13f23b 673 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 674 unsigned int bank, bank_num = env->mcg_cap & 0xff;
675 struct kvm_x86_mce mce;
676
fd13f23b 677 kvm_reset_exception(env);
ab443475
JK		 678
679 /*
680 * There must be at least one bank in use if an MCE is pending.
681 * Find it and use its values for the event injection.
682 */
683 for (bank = 0; bank < bank_num; bank++) {
684 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
685 break;
686 }
687 }
688 assert(bank < bank_num);
689
690 mce.bank = bank;
691 mce.status = env->mce_banks[bank * 4 + 1];
692 mce.mcg_status = env->mcg_status;
693 mce.addr = env->mce_banks[bank * 4 + 2];
694 mce.misc = env->mce_banks[bank * 4 + 3];
695
1bc22652 696 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 697 }
ab443475
JK		 698 return 0;
699}
700
538f0497 701static void cpu_update_state(void *opaque, bool running, RunState state)
b8cc45d6 702{
317ac620 703 CPUX86State *env = opaque;
b8cc45d6
GC		 704
705 if (running) {
706 env->tsc_valid = false;
707 }
708}
709
83b17af5 710unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 711{
83b17af5 712 X86CPU *cpu = X86_CPU(cs);
7e72a45c 713 return cpu->apic_id;
b164e48e
EH		 714}
715
92067bf4
IM		 716#ifndef KVM_CPUID_SIGNATURE_NEXT
717#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
718#endif
719
92067bf4
IM		 720static bool hyperv_enabled(X86CPU *cpu)
721{
5aa9ef5e 722 return kvm_check_extension(kvm_state, KVM_CAP_HYPERV) > 0 &&
f701c082 723 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_NOTIFY) ||
e48ddcc6 724 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 725}
726
74aaddc6
MT		 727/*
728 * Check whether target_freq is within conservative
729 * ntp correctable bounds (250ppm) of freq
730 */
731static inline bool freq_within_bounds(int freq, int target_freq)
732{
733 int max_freq = freq + (freq * 250 / 1000000);
734 int min_freq = freq - (freq * 250 / 1000000);
735
736 if (target_freq >= min_freq && target_freq <= max_freq) {
737 return true;
738 }
739
740 return false;
741}
742
5031283d
HZ		 743static int kvm_arch_set_tsc_khz(CPUState *cs)
744{
745 X86CPU *cpu = X86_CPU(cs);
746 CPUX86State *env = &cpu->env;
74aaddc6
MT		 747 int r, cur_freq;
748 bool set_ioctl = false;
5031283d
HZ		 749
750 if (!env->tsc_khz) {
751 return 0;
752 }
753
74aaddc6
MT		 754 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
755 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) : -ENOTSUP;
756
757 /*
758 * If TSC scaling is supported, attempt to set TSC frequency.
759 */
760 if (kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL)) {
761 set_ioctl = true;
762 }
763
764 /*
765 * If desired TSC frequency is within bounds of NTP correction,
766 * attempt to set TSC frequency.
767 */
768 if (cur_freq != -ENOTSUP && freq_within_bounds(cur_freq, env->tsc_khz)) {
769 set_ioctl = true;
770 }
771
772 r = set_ioctl ?
5031283d
HZ		 773 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
774 -ENOTSUP;
74aaddc6 775
5031283d
HZ		 776 if (r < 0) {
777 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
778 * TSC frequency doesn't match the one we want.
779 */
74aaddc6
MT		 780 cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
781 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
782 -ENOTSUP;
5031283d 783 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 784 warn_report("TSC frequency mismatch between "
785 "VM (%" PRId64 " kHz) and host (%d kHz), "
786 "and TSC scaling unavailable",
787 env->tsc_khz, cur_freq);
5031283d
HZ		 788 return r;
789 }
790 }
791
792 return 0;
793}
794
4bb95b82
LP		 795static bool tsc_is_stable_and_known(CPUX86State *env)
796{
797 if (!env->tsc_khz) {
798 return false;
799 }
800 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
801 || env->user_tsc_khz;
802}
803
6760bd20
VK		 804static struct {
805 const char *desc;
806 struct {
061817a7
VK		 807 uint32_t func;
808 int reg;
6760bd20
VK		 809 uint32_t bits;
810 } flags[2];
c6861930 811 uint64_t dependencies;
6760bd20
VK		 812} kvm_hyperv_properties[] = {
813 [HYPERV_FEAT_RELAXED] = {
814 .desc = "relaxed timing (hv-relaxed)",
815 .flags = {
061817a7 816 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 817 .bits = HV_HYPERCALL_AVAILABLE},
061817a7 818 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 819 .bits = HV_RELAXED_TIMING_RECOMMENDED}
820 }
821 },
822 [HYPERV_FEAT_VAPIC] = {
823 .desc = "virtual APIC (hv-vapic)",
824 .flags = {
061817a7 825 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 826 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
061817a7 827 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 828 .bits = HV_APIC_ACCESS_RECOMMENDED}
829 }
830 },
831 [HYPERV_FEAT_TIME] = {
832 .desc = "clocksources (hv-time)",
833 .flags = {
061817a7 834 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 835 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
836 HV_REFERENCE_TSC_AVAILABLE}
837 }
838 },
839 [HYPERV_FEAT_CRASH] = {
840 .desc = "crash MSRs (hv-crash)",
841 .flags = {
061817a7 842 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 843 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
844 }
845 },
846 [HYPERV_FEAT_RESET] = {
847 .desc = "reset MSR (hv-reset)",
848 .flags = {
061817a7 849 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 850 .bits = HV_RESET_AVAILABLE}
851 }
852 },
853 [HYPERV_FEAT_VPINDEX] = {
854 .desc = "VP_INDEX MSR (hv-vpindex)",
855 .flags = {
061817a7 856 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 857 .bits = HV_VP_INDEX_AVAILABLE}
858 }
859 },
860 [HYPERV_FEAT_RUNTIME] = {
861 .desc = "VP_RUNTIME MSR (hv-runtime)",
862 .flags = {
061817a7 863 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 864 .bits = HV_VP_RUNTIME_AVAILABLE}
865 }
866 },
867 [HYPERV_FEAT_SYNIC] = {
868 .desc = "synthetic interrupt controller (hv-synic)",
869 .flags = {
061817a7 870 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 871 .bits = HV_SYNIC_AVAILABLE}
872 }
873 },
874 [HYPERV_FEAT_STIMER] = {
875 .desc = "synthetic timers (hv-stimer)",
876 .flags = {
061817a7 877 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 878 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 879 },
880 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 881 },
882 [HYPERV_FEAT_FREQUENCIES] = {
883 .desc = "frequency MSRs (hv-frequencies)",
884 .flags = {
061817a7 885 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20 886 .bits = HV_ACCESS_FREQUENCY_MSRS},
061817a7 887 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
6760bd20
VK		 888 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
889 }
890 },
891 [HYPERV_FEAT_REENLIGHTENMENT] = {
892 .desc = "reenlightenment MSRs (hv-reenlightenment)",
893 .flags = {
061817a7 894 {.func = HV_CPUID_FEATURES, .reg = R_EAX,
6760bd20
VK		 895 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
896 }
897 },
898 [HYPERV_FEAT_TLBFLUSH] = {
899 .desc = "paravirtualized TLB flush (hv-tlbflush)",
900 .flags = {
061817a7 901 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 902 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
903 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 904 },
905 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 906 },
907 [HYPERV_FEAT_EVMCS] = {
908 .desc = "enlightened VMCS (hv-evmcs)",
909 .flags = {
061817a7 910 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20 911 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 912 },
913 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 914 },
915 [HYPERV_FEAT_IPI] = {
916 .desc = "paravirtualized IPI (hv-ipi)",
917 .flags = {
061817a7 918 {.func = HV_CPUID_ENLIGHTMENT_INFO, .reg = R_EAX,
6760bd20
VK		 919 .bits = HV_CLUSTER_IPI_RECOMMENDED |
920 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 921 },
922 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 923 },
128531d9
VK		 924 [HYPERV_FEAT_STIMER_DIRECT] = {
925 .desc = "direct mode synthetic timers (hv-stimer-direct)",
926 .flags = {
061817a7 927 {.func = HV_CPUID_FEATURES, .reg = R_EDX,
128531d9
VK		 928 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
929 },
930 .dependencies = BIT(HYPERV_FEAT_STIMER)
931 },
6760bd20
VK		 932};
933
2e905438
VK		 934static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max,
935 bool do_sys_ioctl)
6760bd20
VK		 936{
937 struct kvm_cpuid2 *cpuid;
938 int r, size;
939
940 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
941 cpuid = g_malloc0(size);
942 cpuid->nent = max;
943
2e905438
VK		 944 if (do_sys_ioctl) {
945 r = kvm_ioctl(kvm_state, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
946 } else {
947 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
948 }
6760bd20
VK		 949 if (r == 0 && cpuid->nent >= max) {
950 r = -E2BIG;
951 }
952 if (r < 0) {
953 if (r == -E2BIG) {
954 g_free(cpuid);
955 return NULL;
956 } else {
957 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
958 strerror(-r));
959 exit(1);
960 }
961 }
962 return cpuid;
963}
964
965/*
966 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
967 * for all entries.
968 */
969static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
970{
971 struct kvm_cpuid2 *cpuid;
05c900ce
VK		 972 /* 0x40000000..0x40000005, 0x4000000A, 0x40000080..0x40000080 leaves */
973 int max = 10;
decb4f20 974 int i;
2e905438
VK		 975 bool do_sys_ioctl;
976
977 do_sys_ioctl =
978 kvm_check_extension(kvm_state, KVM_CAP_SYS_HYPERV_CPUID) > 0;
6760bd20
VK		 979
980 /*
981 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
982 * -E2BIG, however, it doesn't report back the right size. Keep increasing
983 * it and re-trying until we succeed.
984 */
2e905438 985 while ((cpuid = try_get_hv_cpuid(cs, max, do_sys_ioctl)) == NULL) {
6760bd20
VK		 986 max++;
987 }
decb4f20
VK		 988
989 /*
990 * KVM_GET_SUPPORTED_HV_CPUID does not set EVMCS CPUID bit before
991 * KVM_CAP_HYPERV_ENLIGHTENED_VMCS is enabled but we want to get the
992 * information early, just check for the capability and set the bit
993 * manually.
994 */
2e905438 995 if (!do_sys_ioctl && kvm_check_extension(cs->kvm_state,
decb4f20
VK		 996 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
997 for (i = 0; i < cpuid->nent; i++) {
998 if (cpuid->entries[i].function == HV_CPUID_ENLIGHTMENT_INFO) {
999 cpuid->entries[i].eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
1000 }
1001 }
1002 }
1003
6760bd20
VK		 1004 return cpuid;
1005}
1006
1007/*
1008 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
1009 * leaves from KVM_CAP_HYPERV* and present MSRs data.
1010 */
1011static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 1012{
1013 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 1014 struct kvm_cpuid2 *cpuid;
1015 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
1016
1017 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
1018 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
1019 cpuid->nent = 2;
1020
1021 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
1022 entry_feat = &cpuid->entries[0];
1023 entry_feat->function = HV_CPUID_FEATURES;
1024
1025 entry_recomm = &cpuid->entries[1];
1026 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
1027 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
1028
1029 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1030 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1031 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1032 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1033 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1034 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1035 }
c35bd19a 1036
6760bd20
VK		 1037 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1038 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1039 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 1040 }
6760bd20
VK		 1041
1042 if (has_msr_hv_frequencies) {
1043 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1044 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 1045 }
6760bd20
VK		 1046
1047 if (has_msr_hv_crash) {
1048 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 1049 }
6760bd20
VK		 1050
1051 if (has_msr_hv_reenlightenment) {
1052 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 1053 }
6760bd20
VK		 1054
1055 if (has_msr_hv_reset) {
1056 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 1057 }
6760bd20
VK		 1058
1059 if (has_msr_hv_vpindex) {
1060 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 1061 }
6760bd20
VK		 1062
1063 if (has_msr_hv_runtime) {
1064 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 1065 }
6760bd20
VK		 1066
1067 if (has_msr_hv_synic) {
1068 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1069 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1070
1071 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1072 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 1073 }
c35bd19a 1074 }
6760bd20
VK		 1075
1076 if (has_msr_hv_stimer) {
1077 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 1078 }
9b4cf107 1079
6760bd20
VK		 1080 if (kvm_check_extension(cs->kvm_state,
1081 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1082 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1083 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1084 }
c35bd19a 1085
6760bd20
VK		 1086 if (kvm_check_extension(cs->kvm_state,
1087 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1088 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 1089 }
6760bd20
VK		 1090
1091 if (kvm_check_extension(cs->kvm_state,
1092 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1093 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1094 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 1095 }
6760bd20
VK		 1096
1097 return cpuid;
1098}
1099
a8439be6 1100static uint32_t hv_cpuid_get_host(CPUState *cs, uint32_t func, int reg)
e1a66a1e
VK		 1101{
1102 struct kvm_cpuid_entry2 *entry;
a8439be6
VK		 1103 struct kvm_cpuid2 *cpuid;
1104
1105 if (hv_cpuid_cache) {
1106 cpuid = hv_cpuid_cache;
1107 } else {
1108 if (kvm_check_extension(kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1109 cpuid = get_supported_hv_cpuid(cs);
1110 } else {
1111 cpuid = get_supported_hv_cpuid_legacy(cs);
1112 }
1113 hv_cpuid_cache = cpuid;
1114 }
1115
1116 if (!cpuid) {
1117 return 0;
1118 }
e1a66a1e
VK		 1119
1120 entry = cpuid_find_entry(cpuid, func, 0);
1121 if (!entry) {
1122 return 0;
1123 }
1124
1125 return cpuid_entry_get_reg(entry, reg);
1126}
1127
a8439be6 1128static bool hyperv_feature_supported(CPUState *cs, int feature)
7682f857 1129{
061817a7
VK		 1130 uint32_t func, bits;
1131 int i, reg;
7682f857
VK		 1132
1133 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
061817a7
VK		 1134
1135 func = kvm_hyperv_properties[feature].flags[i].func;
1136 reg = kvm_hyperv_properties[feature].flags[i].reg;
7682f857
VK		 1137 bits = kvm_hyperv_properties[feature].flags[i].bits;
1138
061817a7 1139 if (!func) {
7682f857
VK		 1140 continue;
1141 }
1142
a8439be6 1143 if ((hv_cpuid_get_host(cs, func, reg) & bits) != bits) {
7682f857
VK		 1144 return false;
1145 }
1146 }
1147
1148 return true;
1149}
1150
f4a62495 1151static int hv_cpuid_check_and_set(CPUState *cs, int feature, Error **errp)
6760bd20
VK		 1152{
1153 X86CPU *cpu = X86_CPU(cs);
c6861930 1154 uint64_t deps;
7682f857 1155 int dep_feat;
6760bd20 1156
e48ddcc6 1157 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1158 return 0;
1159 }
1160
c6861930 1161 deps = kvm_hyperv_properties[feature].dependencies;
9dc83cd9
HR		 1162 while (deps) {
1163 dep_feat = ctz64(deps);
c6861930 1164 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
f4a62495
VK		 1165 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1166 kvm_hyperv_properties[feature].desc,
1167 kvm_hyperv_properties[dep_feat].desc);
1168 return 1;
c6861930 1169 }
9dc83cd9 1170 deps &= ~(1ull << dep_feat);
c6861930
VK		 1171 }
1172
a8439be6 1173 if (!hyperv_feature_supported(cs, feature)) {
7682f857 1174 if (hyperv_feat_enabled(cpu, feature)) {
f4a62495
VK		 1175 error_setg(errp, "Hyper-V %s is not supported by kernel",
1176 kvm_hyperv_properties[feature].desc);
7682f857
VK		 1177 return 1;
1178 } else {
1179 return 0;
6760bd20 1180 }
a2b107db 1181 }
6760bd20 1182
e48ddcc6
VK		 1183 if (cpu->hyperv_passthrough) {
1184 cpu->hyperv_features |= BIT(feature);
1185 }
1186
6760bd20
VK		 1187 return 0;
1188}
1189
061817a7 1190static uint32_t hv_build_cpuid_leaf(CPUState *cs, uint32_t func, int reg)
c830015e
VK		 1191{
1192 X86CPU *cpu = X86_CPU(cs);
1193 uint32_t r = 0;
1194 int i, j;
1195
1196 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties); i++) {
1197 if (!hyperv_feat_enabled(cpu, i)) {
1198 continue;
1199 }
1200
1201 for (j = 0; j < ARRAY_SIZE(kvm_hyperv_properties[i].flags); j++) {
061817a7
VK		 1202 if (kvm_hyperv_properties[i].flags[j].func != func) {
1203 continue;
1204 }
1205 if (kvm_hyperv_properties[i].flags[j].reg != reg) {
c830015e
VK		 1206 continue;
1207 }
1208
1209 r |= kvm_hyperv_properties[i].flags[j].bits;
1210 }
1211 }
1212
1213 return r;
1214}
1215
2344d22e 1216/*
f6e01ab5
VK		 1217 * Expand Hyper-V CPU features. In partucular, check that all the requested
1218 * features are supported by the host and the sanity of the configuration
1219 * (that all the required dependencies are included). Also, this takes care
1220 * of 'hv_passthrough' mode and fills the environment with all supported
1221 * Hyper-V features.
2344d22e 1222 */
f4a62495 1223static void hyperv_expand_features(CPUState *cs, Error **errp)
6760bd20
VK		 1224{
1225 X86CPU *cpu = X86_CPU(cs);
6760bd20 1226
2344d22e 1227 if (!hyperv_enabled(cpu))
f4a62495 1228 return;
2344d22e 1229
e48ddcc6 1230 if (cpu->hyperv_passthrough) {
e1a66a1e 1231 cpu->hyperv_vendor_id[0] =
a8439be6 1232 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EBX);
e1a66a1e 1233 cpu->hyperv_vendor_id[1] =
a8439be6 1234 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_ECX);
e1a66a1e 1235 cpu->hyperv_vendor_id[2] =
a8439be6 1236 hv_cpuid_get_host(cs, HV_CPUID_VENDOR_AND_MAX_FUNCTIONS, R_EDX);
e1a66a1e
VK		 1237 cpu->hyperv_vendor = g_realloc(cpu->hyperv_vendor,
1238 sizeof(cpu->hyperv_vendor_id) + 1);
1239 memcpy(cpu->hyperv_vendor, cpu->hyperv_vendor_id,
1240 sizeof(cpu->hyperv_vendor_id));
1241 cpu->hyperv_vendor[sizeof(cpu->hyperv_vendor_id)] = 0;
1242
1243 cpu->hyperv_interface_id[0] =
a8439be6 1244 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EAX);
e1a66a1e 1245 cpu->hyperv_interface_id[1] =
a8439be6 1246 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EBX);
e1a66a1e 1247 cpu->hyperv_interface_id[2] =
a8439be6 1248 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_ECX);
e1a66a1e 1249 cpu->hyperv_interface_id[3] =
a8439be6 1250 hv_cpuid_get_host(cs, HV_CPUID_INTERFACE, R_EDX);
e1a66a1e
VK		 1251
1252 cpu->hyperv_version_id[0] =
a8439be6 1253 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EAX);
e1a66a1e 1254 cpu->hyperv_version_id[1] =
a8439be6 1255 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EBX);
e1a66a1e 1256 cpu->hyperv_version_id[2] =
a8439be6 1257 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_ECX);
e1a66a1e 1258 cpu->hyperv_version_id[3] =
a8439be6 1259 hv_cpuid_get_host(cs, HV_CPUID_VERSION, R_EDX);
e1a66a1e 1260
a8439be6 1261 cpu->hv_max_vps = hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS,
e1a66a1e
VK		 1262 R_EAX);
1263 cpu->hyperv_limits[0] =
a8439be6 1264 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EBX);
e1a66a1e 1265 cpu->hyperv_limits[1] =
a8439be6 1266 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_ECX);
e1a66a1e 1267 cpu->hyperv_limits[2] =
a8439be6 1268 hv_cpuid_get_host(cs, HV_CPUID_IMPLEMENT_LIMITS, R_EDX);
e1a66a1e
VK		 1269
1270 cpu->hyperv_spinlock_attempts =
a8439be6 1271 hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EBX);
30d6ff66
VK		 1272 }
1273
6760bd20 1274 /* Features */
f4a62495
VK		 1275 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_RELAXED, errp)) {
1276 return;
1277 }
1278 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_VAPIC, errp)) {
1279 return;
1280 }
1281 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_TIME, errp)) {
1282 return;
1283 }
1284 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_CRASH, errp)) {
1285 return;
1286 }
1287 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_RESET, errp)) {
1288 return;
1289 }
1290 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_VPINDEX, errp)) {
1291 return;
1292 }
1293 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_RUNTIME, errp)) {
1294 return;
1295 }
1296 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_SYNIC, errp)) {
1297 return;
1298 }
1299 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER, errp)) {
1300 return;
1301 }
1302 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_FREQUENCIES, errp)) {
1303 return;
1304 }
1305 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_REENLIGHTENMENT, errp)) {
1306 return;
1307 }
1308 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_TLBFLUSH, errp)) {
1309 return;
1310 }
1311 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_EVMCS, errp)) {
1312 return;
1313 }
1314 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_IPI, errp)) {
1315 return;
1316 }
1317 if (hv_cpuid_check_and_set(cs, HYPERV_FEAT_STIMER_DIRECT, errp)) {
1318 return;
1319 }
6760bd20 1320
c6861930 1321 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1322 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1323 !cpu->hyperv_synic_kvm_only &&
1324 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
f4a62495
VK		 1325 error_setg(errp, "Hyper-V %s requires Hyper-V %s",
1326 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1327 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
6760bd20 1328 }
f6e01ab5
VK		 1329}
1330
1331/*
1332 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent.
1333 */
1334static int hyperv_fill_cpuids(CPUState *cs,
1335 struct kvm_cpuid_entry2 *cpuid_ent)
1336{
1337 X86CPU *cpu = X86_CPU(cs);
1338 struct kvm_cpuid_entry2 *c;
1339 uint32_t cpuid_i = 0;
1340
2344d22e
VK		 1341 c = &cpuid_ent[cpuid_i++];
1342 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
2344d22e
VK		 1343 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1344 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
08856771
VK		 1345 c->ebx = cpu->hyperv_vendor_id[0];
1346 c->ecx = cpu->hyperv_vendor_id[1];
1347 c->edx = cpu->hyperv_vendor_id[2];
2344d22e
VK		 1348
1349 c = &cpuid_ent[cpuid_i++];
1350 c->function = HV_CPUID_INTERFACE;
735db465
VK		 1351 c->eax = cpu->hyperv_interface_id[0];
1352 c->ebx = cpu->hyperv_interface_id[1];
1353 c->ecx = cpu->hyperv_interface_id[2];
1354 c->edx = cpu->hyperv_interface_id[3];
2344d22e
VK		 1355
1356 c = &cpuid_ent[cpuid_i++];
1357 c->function = HV_CPUID_VERSION;
fb7e31aa
VK		 1358 c->eax = cpu->hyperv_version_id[0];
1359 c->ebx = cpu->hyperv_version_id[1];
1360 c->ecx = cpu->hyperv_version_id[2];
1361 c->edx = cpu->hyperv_version_id[3];
2344d22e
VK		 1362
1363 c = &cpuid_ent[cpuid_i++];
1364 c->function = HV_CPUID_FEATURES;
061817a7
VK		 1365 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EAX);
1366 c->ebx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EBX);
1367 c->edx = hv_build_cpuid_leaf(cs, HV_CPUID_FEATURES, R_EDX);
c830015e
VK		 1368
1369 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1370 c->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
2344d22e
VK		 1371
1372 c = &cpuid_ent[cpuid_i++];
1373 c->function = HV_CPUID_ENLIGHTMENT_INFO;
061817a7 1374 c->eax = hv_build_cpuid_leaf(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX);
2344d22e
VK		 1375 c->ebx = cpu->hyperv_spinlock_attempts;
1376
c830015e
VK		 1377 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1378 c->eax |= HV_NO_NONARCH_CORESHARING;
1379 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
a8439be6 1380 c->eax |= hv_cpuid_get_host(cs, HV_CPUID_ENLIGHTMENT_INFO, R_EAX) &
e1a66a1e 1381 HV_NO_NONARCH_CORESHARING;
c830015e
VK		 1382 }
1383
2344d22e
VK		 1384 c = &cpuid_ent[cpuid_i++];
1385 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1386 c->eax = cpu->hv_max_vps;
23eb5d03
VK		 1387 c->ebx = cpu->hyperv_limits[0];
1388 c->ecx = cpu->hyperv_limits[1];
1389 c->edx = cpu->hyperv_limits[2];
2344d22e
VK		 1390
1391 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1392 __u32 function;
1393
1394 /* Create zeroed 0x40000006..0x40000009 leaves */
1395 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1396 function < HV_CPUID_NESTED_FEATURES; function++) {
1397 c = &cpuid_ent[cpuid_i++];
1398 c->function = function;
1399 }
1400
1401 c = &cpuid_ent[cpuid_i++];
1402 c->function = HV_CPUID_NESTED_FEATURES;
c830015e 1403 c->eax = cpu->hyperv_nested[0];
2344d22e 1404 }
6760bd20 1405
a8439be6 1406 return cpuid_i;
c35bd19a
EY		 1407}
1408
e48ddcc6 1409static Error *hv_passthrough_mig_blocker;
30d6ff66 1410static Error *hv_no_nonarch_cs_mig_blocker;
e48ddcc6 1411
e9688fab
RK		 1412static int hyperv_init_vcpu(X86CPU *cpu)
1413{
729ce7e1 1414 CPUState *cs = CPU(cpu);
e48ddcc6 1415 Error *local_err = NULL;
729ce7e1
RK		 1416 int ret;
1417
e48ddcc6
VK		 1418 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1419 error_setg(&hv_passthrough_mig_blocker,
1420 "'hv-passthrough' CPU flag prevents migration, use explicit"
1421 " set of hv-* flags instead");
1422 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1423 if (local_err) {
1424 error_report_err(local_err);
1425 error_free(hv_passthrough_mig_blocker);
1426 return ret;
1427 }
1428 }
1429
30d6ff66
VK		 1430 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1431 hv_no_nonarch_cs_mig_blocker == NULL) {
1432 error_setg(&hv_no_nonarch_cs_mig_blocker,
1433 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1434 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1435 " make sure SMT is disabled and/or that vCPUs are properly"
1436 " pinned)");
1437 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
1438 if (local_err) {
1439 error_report_err(local_err);
1440 error_free(hv_no_nonarch_cs_mig_blocker);
1441 return ret;
1442 }
1443 }
1444
2d384d7c 1445 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1446 /*
1447 * the kernel doesn't support setting vp_index; assert that its value
1448 * is in sync
1449 */
e9688fab
RK		 1450 struct {
1451 struct kvm_msrs info;
1452 struct kvm_msr_entry entries[1];
1453 } msr_data = {
1454 .info.nmsrs = 1,
1455 .entries[0].index = HV_X64_MSR_VP_INDEX,
1456 };
1457
729ce7e1 1458 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1459 if (ret < 0) {
1460 return ret;
1461 }
1462 assert(ret == 1);
1463
701189e3 1464 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1465 error_report("kernel's vp_index != QEMU's vp_index");
1466 return -ENXIO;
1467 }
1468 }
1469
2d384d7c 1470 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1471 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1472 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1473 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1474 if (ret < 0) {
1475 error_report("failed to turn on HyperV SynIC in KVM: %s",
1476 strerror(-ret));
1477 return ret;
1478 }
606c34bf 1479
9b4cf107
RK		 1480 if (!cpu->hyperv_synic_kvm_only) {
1481 ret = hyperv_x86_synic_add(cpu);
1482 if (ret < 0) {
1483 error_report("failed to create HyperV SynIC: %s",
1484 strerror(-ret));
1485 return ret;
1486 }
606c34bf 1487 }
729ce7e1
RK		 1488 }
1489
decb4f20
VK		 1490 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1491 uint16_t evmcs_version;
1492
1493 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1494 (uintptr_t)&evmcs_version);
1495
1496 if (ret < 0) {
1497 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1498 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
1499 return ret;
1500 }
1501
1502 cpu->hyperv_nested[0] = evmcs_version;
1503 }
1504
e9688fab
RK		 1505 return 0;
1506}
1507
68bfd0ad
MT		 1508static Error *invtsc_mig_blocker;
1509
f8bb0565 1510#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1511
20d695a9 1512int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1513{
1514 struct {
486bd5a2 1515 struct kvm_cpuid2 cpuid;
f8bb0565 1516 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1517 } cpuid_data;
1518 /*
1519 * The kernel defines these structs with padding fields so there
1520 * should be no extra padding in our cpuid_data struct.
1521 */
1522 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1523 sizeof(struct kvm_cpuid2) +
1524 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1525
20d695a9
AF		 1526 X86CPU *cpu = X86_CPU(cs);
1527 CPUX86State *env = &cpu->env;
486bd5a2 1528 uint32_t limit, i, j, cpuid_i;
a33609ca 1529 uint32_t unused;
bb0300dc 1530 struct kvm_cpuid_entry2 *c;
bb0300dc 1531 uint32_t signature[3];
234cc647 1532 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1533 int max_nested_state_len;
e7429073 1534 int r;
fe44dc91 1535 Error *local_err = NULL;
05330448 1536
ef4cbe14
SW		 1537 memset(&cpuid_data, 0, sizeof(cpuid_data));
1538
05330448
AL		 1539 cpuid_i = 0;
1540
ddb98b5a
LP		 1541 r = kvm_arch_set_tsc_khz(cs);
1542 if (r < 0) {
6b2341ee 1543 return r;
ddb98b5a
LP		 1544 }
1545
1546 /* vcpu's TSC frequency is either specified by user, or following
1547 * the value used by KVM if the former is not present. In the
1548 * latter case, we query it from KVM and record in env->tsc_khz,
1549 * so that vcpu's TSC frequency can be migrated later via this field.
1550 */
1551 if (!env->tsc_khz) {
1552 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1553 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1554 -ENOTSUP;
1555 if (r > 0) {
1556 env->tsc_khz = r;
1557 }
1558 }
1559
73b994f6
LA		 1560 env->apic_bus_freq = KVM_APIC_BUS_FREQUENCY;
1561
bb0300dc 1562 /* Paravirtualization CPUIDs */
f4a62495
VK		 1563 hyperv_expand_features(cs, &local_err);
1564 if (local_err) {
1565 error_report_err(local_err);
1566 return -ENOSYS;
f6e01ab5
VK		 1567 }
1568
1569 if (hyperv_enabled(cpu)) {
decb4f20
VK		 1570 r = hyperv_init_vcpu(cpu);
1571 if (r) {
1572 return r;
1573 }
1574
f6e01ab5 1575 cpuid_i = hyperv_fill_cpuids(cs, cpuid_data.entries);
234cc647 1576 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1577 has_msr_hv_hypercall = true;
eab70139
VR		 1578 }
1579
f522d2ac
AW		 1580 if (cpu->expose_kvm) {
1581 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1582 c = &cpuid_data.entries[cpuid_i++];
1583 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1584 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1585 c->ebx = signature[0];
1586 c->ecx = signature[1];
1587 c->edx = signature[2];
234cc647 1588
f522d2ac
AW		 1589 c = &cpuid_data.entries[cpuid_i++];
1590 c->function = KVM_CPUID_FEATURES | kvm_base;
1591 c->eax = env->features[FEAT_KVM];
be777326 1592 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1593 }
917367aa 1594
a33609ca 1595 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1596
1597 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1598 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1599 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1600 abort();
1601 }
bb0300dc 1602 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1603
1604 switch (i) {
a36b1029
AL		 1605 case 2: {
1606 /* Keep reading function 2 till all the input is received */
1607 int times;
1608
a36b1029 1609 c->function = i;
a33609ca
AL		 1610 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1611 KVM_CPUID_FLAG_STATE_READ_NEXT;
1612 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1613 times = c->eax & 0xff;
a36b1029
AL		 1614
1615 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1616 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1617 fprintf(stderr, "cpuid_data is full, no space for "
1618 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1619 abort();
1620 }
a33609ca 1621 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1622 c->function = i;
a33609ca
AL		 1623 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1624 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1625 }
1626 break;
1627 }
a94e1428
LX		 1628 case 0x1f:
1629 if (env->nr_dies < 2) {
1630 break;
1631 }
8821e214 1632 /* fallthrough */
486bd5a2
AL		 1633 case 4:
1634 case 0xb:
1635 case 0xd:
1636 for (j = 0; ; j++) {
31e8c696
AP		 1637 if (i == 0xd && j == 64) {
1638 break;
1639 }
a94e1428
LX		 1640
1641 if (i == 0x1f && j == 64) {
1642 break;
1643 }
1644
486bd5a2
AL		 1645 c->function = i;
1646 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1647 c->index = j;
a33609ca 1648 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1649
b9bec74b 1650 if (i == 4 && c->eax == 0) {
486bd5a2 1651 break;
b9bec74b
JK		 1652 }
1653 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1654 break;
b9bec74b 1655 }
a94e1428
LX		 1656 if (i == 0x1f && !(c->ecx & 0xff00)) {
1657 break;
1658 }
b9bec74b 1659 if (i == 0xd && c->eax == 0) {
31e8c696 1660 continue;
b9bec74b 1661 }
f8bb0565
IM		 1662 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1663 fprintf(stderr, "cpuid_data is full, no space for "
1664 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1665 abort();
1666 }
a33609ca 1667 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1668 }
1669 break;
80db491d 1670 case 0x7:
e37a5c7f
CP		 1671 case 0x14: {
1672 uint32_t times;
1673
1674 c->function = i;
1675 c->index = 0;
1676 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1677 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1678 times = c->eax;
1679
1680 for (j = 1; j <= times; ++j) {
1681 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1682 fprintf(stderr, "cpuid_data is full, no space for "
80db491d 1683 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
e37a5c7f
CP		 1684 abort();
1685 }
1686 c = &cpuid_data.entries[cpuid_i++];
1687 c->function = i;
1688 c->index = j;
1689 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1690 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1691 }
1692 break;
1693 }
486bd5a2 1694 default:
486bd5a2 1695 c->function = i;
a33609ca
AL		 1696 c->flags = 0;
1697 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1698 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1699 /*
1700 * KVM already returns all zeroes if a CPUID entry is missing,
1701 * so we can omit it and avoid hitting KVM's 80-entry limit.
1702 */
1703 cpuid_i--;
1704 }
486bd5a2
AL		 1705 break;
1706 }
05330448 1707 }
0d894367
PB		 1708
1709 if (limit >= 0x0a) {
0b368a10 1710 uint32_t eax, edx;
0d894367 1711
0b368a10
JD		 1712 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1713
1714 has_architectural_pmu_version = eax & 0xff;
1715 if (has_architectural_pmu_version > 0) {
1716 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1717
1718 /* Shouldn't be more than 32, since that's the number of bits
1719 * available in EBX to tell us _which_ counters are available.
1720 * Play it safe.
1721 */
0b368a10
JD		 1722 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1723 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1724 }
1725
1726 if (has_architectural_pmu_version > 1) {
1727 num_architectural_pmu_fixed_counters = edx & 0x1f;
1728
1729 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1730 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1731 }
0d894367
PB		 1732 }
1733 }
1734 }
1735
a33609ca 1736 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1737
1738 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1739 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1740 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1741 abort();
1742 }
bb0300dc 1743 c = &cpuid_data.entries[cpuid_i++];
05330448 1744
8f4202fb
BM		 1745 switch (i) {
1746 case 0x8000001d:
1747 /* Query for all AMD cache information leaves */
1748 for (j = 0; ; j++) {
1749 c->function = i;
1750 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1751 c->index = j;
1752 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1753
1754 if (c->eax == 0) {
1755 break;
1756 }
1757 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1758 fprintf(stderr, "cpuid_data is full, no space for "
1759 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1760 abort();
1761 }
1762 c = &cpuid_data.entries[cpuid_i++];
1763 }
1764 break;
1765 default:
1766 c->function = i;
1767 c->flags = 0;
1768 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1769 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1770 /*
1771 * KVM already returns all zeroes if a CPUID entry is missing,
1772 * so we can omit it and avoid hitting KVM's 80-entry limit.
1773 */
1774 cpuid_i--;
1775 }
8f4202fb
BM		 1776 break;
1777 }
05330448
AL		 1778 }
1779
b3baa152
BW		 1780 /* Call Centaur's CPUID instructions they are supported. */
1781 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1782 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1783
1784 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1785 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1786 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1787 abort();
1788 }
b3baa152
BW		 1789 c = &cpuid_data.entries[cpuid_i++];
1790
1791 c->function = i;
1792 c->flags = 0;
1793 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1794 }
1795 }
1796
05330448
AL		 1797 cpuid_data.cpuid.nent = cpuid_i;
1798
e7701825 1799 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1800 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1801 (CPUID_MCE | CPUID_MCA)
a60f24b5 1802 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1803 uint64_t mcg_cap, unsupported_caps;
e7701825 1804 int banks;
32a42024 1805 int ret;
e7701825 1806
a60f24b5 1807 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1808 if (ret < 0) {
1809 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1810 return ret;
e7701825 1811 }
75d49497 1812
2590f15b 1813 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1814 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1815 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1816 return -ENOTSUP;
75d49497 1817 }
49b69cbf 1818
5120901a
EH		 1819 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1820 if (unsupported_caps) {
87f8b626
AR		 1821 if (unsupported_caps & MCG_LMCE_P) {
1822 error_report("kvm: LMCE not supported");
1823 return -ENOTSUP;
1824 }
3dc6f869
AF		 1825 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1826 unsupported_caps);
5120901a
EH		 1827 }
1828
2590f15b
EH		 1829 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1830 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1831 if (ret < 0) {
1832 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1833 return ret;
1834 }
e7701825 1835 }
e7701825 1836
2a693142 1837 cpu->vmsentry = qemu_add_vm_change_state_handler(cpu_update_state, env);
b8cc45d6 1838
df67696e
LJ		 1839 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1840 if (c) {
1841 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1842 !!(c->ecx & CPUID_EXT_SMX);
1843 }
1844
87f8b626
AR		 1845 if (env->mcg_cap & MCG_LMCE_P) {
1846 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1847 }
1848
d99569d9
EH		 1849 if (!env->user_tsc_khz) {
1850 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1851 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1852 error_setg(&invtsc_mig_blocker,
1853 "State blocked by non-migratable CPU device"
1854 " (invtsc flag)");
fe44dc91
AA		 1855 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1856 if (local_err) {
1857 error_report_err(local_err);
1858 error_free(invtsc_mig_blocker);
79a197ab 1859 return r;
fe44dc91 1860 }
d99569d9 1861 }
68bfd0ad
MT		 1862 }
1863
9954a158
PDJ		 1864 if (cpu->vmware_cpuid_freq
1865 /* Guests depend on 0x40000000 to detect this feature, so only expose
1866 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1867 && cpu->expose_kvm
1868 && kvm_base == KVM_CPUID_SIGNATURE
1869 /* TSC clock must be stable and known for this feature. */
4bb95b82 1870 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1871
1872 c = &cpuid_data.entries[cpuid_i++];
1873 c->function = KVM_CPUID_SIGNATURE | 0x10;
1874 c->eax = env->tsc_khz;
73b994f6 1875 c->ebx = env->apic_bus_freq / 1000; /* Hz to KHz */
9954a158
PDJ		 1876 c->ecx = c->edx = 0;
1877
1878 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1879 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1880 }
1881
1882 cpuid_data.cpuid.nent = cpuid_i;
1883
1884 cpuid_data.cpuid.padding = 0;
1885 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1886 if (r) {
1887 goto fail;
1888 }
1889
28143b40 1890 if (has_xsave) {
5b8063c4 1891 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1f670a95 1892 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
fabacc0f 1893 }
ebbfef2f
LA		 1894
1895 max_nested_state_len = kvm_max_nested_state_length();
1896 if (max_nested_state_len > 0) {
1897 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
ebbfef2f 1898
b16c0e20 1899 if (cpu_has_vmx(env) || cpu_has_svm(env)) {
1e44f3ab 1900 struct kvm_vmx_nested_state_hdr *vmx_hdr;
ebbfef2f 1901
1e44f3ab
PB		 1902 env->nested_state = g_malloc0(max_nested_state_len);
1903 env->nested_state->size = max_nested_state_len;
1e44f3ab 1904
b16c0e20 1905 if (cpu_has_vmx(env)) {
2654ace1
TL		 1906 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1907 vmx_hdr = &env->nested_state->hdr.vmx;
1908 vmx_hdr->vmxon_pa = -1ull;
1909 vmx_hdr->vmcs12_pa = -1ull;
1910 } else {
1911 env->nested_state->format = KVM_STATE_NESTED_FORMAT_SVM;
b16c0e20 1912 }
ebbfef2f
LA		 1913 }
1914 }
1915
d71b62a1 1916 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1917
273c515c
PB		 1918 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1919 has_msr_tsc_aux = false;
1920 }
d1ae67f6 1921
420ae1fc
PB		 1922 kvm_init_msrs(cpu);
1923
e7429073 1924 return 0;
fe44dc91
AA		 1925
1926 fail:
1927 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 1928
fe44dc91 1929 return r;
05330448
AL		 1930}
1931
b1115c99
LA		 1932int kvm_arch_destroy_vcpu(CPUState *cs)
1933{
1934 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 1935 CPUX86State *env = &cpu->env;
b1115c99
LA		 1936
1937 if (cpu->kvm_msr_buf) {
1938 g_free(cpu->kvm_msr_buf);
1939 cpu->kvm_msr_buf = NULL;
1940 }
1941
ebbfef2f
LA		 1942 if (env->nested_state) {
1943 g_free(env->nested_state);
1944 env->nested_state = NULL;
1945 }
1946
2a693142
PN		 1947 qemu_del_vm_change_state_handler(cpu->vmsentry);
1948
b1115c99
LA		 1949 return 0;
1950}
1951
50a2c6e5 1952void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1953{
20d695a9 1954 CPUX86State *env = &cpu->env;
dd673288 1955
1a5e9d2f 1956 env->xcr0 = 1;
ddced198 1957 if (kvm_irqchip_in_kernel()) {
dd673288 1958 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1959 KVM_MP_STATE_UNINITIALIZED;
1960 } else {
1961 env->mp_state = KVM_MP_STATE_RUNNABLE;
1962 }
689141dd 1963
2d384d7c 1964 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1965 int i;
1966 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1967 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1968 }
606c34bf
RK		 1969
1970 hyperv_x86_synic_reset(cpu);
689141dd 1971 }
d645e132
MT		 1972 /* enabled by default */
1973 env->poll_control_msr = 1;
b2f73a07
PB		 1974
1975 sev_es_set_reset_vector(CPU(cpu));
caa5af0f
JK		 1976}
1977
e0723c45
PB		 1978void kvm_arch_do_init_vcpu(X86CPU *cpu)
1979{
1980 CPUX86State *env = &cpu->env;
1981
1982 /* APs get directly into wait-for-SIPI state. */
1983 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1984 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1985 }
1986}
1987
f57bceb6
RH		 1988static int kvm_get_supported_feature_msrs(KVMState *s)
1989{
1990 int ret = 0;
1991
1992 if (kvm_feature_msrs != NULL) {
1993 return 0;
1994 }
1995
1996 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1997 return 0;
1998 }
1999
2000 struct kvm_msr_list msr_list;
2001
2002 msr_list.nmsrs = 0;
2003 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
2004 if (ret < 0 && ret != -E2BIG) {
2005 error_report("Fetch KVM feature MSR list failed: %s",
2006 strerror(-ret));
2007 return ret;
2008 }
2009
2010 assert(msr_list.nmsrs > 0);
2011 kvm_feature_msrs = (struct kvm_msr_list *) \
2012 g_malloc0(sizeof(msr_list) +
2013 msr_list.nmsrs * sizeof(msr_list.indices[0]));
2014
2015 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
2016 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
2017
2018 if (ret < 0) {
2019 error_report("Fetch KVM feature MSR list failed: %s",
2020 strerror(-ret));
2021 g_free(kvm_feature_msrs);
2022 kvm_feature_msrs = NULL;
2023 return ret;
2024 }
2025
2026 return 0;
2027}
2028
c3a3a7d3 2029static int kvm_get_supported_msrs(KVMState *s)
05330448 2030{
c3a3a7d3 2031 int ret = 0;
de428cea 2032 struct kvm_msr_list msr_list, *kvm_msr_list;
05330448 2033
de428cea
LQ		 2034 /*
2035 * Obtain MSR list from KVM. These are the MSRs that we must
2036 * save/restore.
2037 */
2038 msr_list.nmsrs = 0;
2039 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
2040 if (ret < 0 && ret != -E2BIG) {
2041 return ret;
2042 }
2043 /*
2044 * Old kernel modules had a bug and could write beyond the provided
2045 * memory. Allocate at least a safe amount of 1K.
2046 */
2047 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
2048 msr_list.nmsrs *
2049 sizeof(msr_list.indices[0])));
05330448 2050
de428cea
LQ		 2051 kvm_msr_list->nmsrs = msr_list.nmsrs;
2052 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
2053 if (ret >= 0) {
2054 int i;
05330448 2055
de428cea
LQ		 2056 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
2057 switch (kvm_msr_list->indices[i]) {
2058 case MSR_STAR:
2059 has_msr_star = true;
2060 break;
2061 case MSR_VM_HSAVE_PA:
2062 has_msr_hsave_pa = true;
2063 break;
2064 case MSR_TSC_AUX:
2065 has_msr_tsc_aux = true;
2066 break;
2067 case MSR_TSC_ADJUST:
2068 has_msr_tsc_adjust = true;
2069 break;
2070 case MSR_IA32_TSCDEADLINE:
2071 has_msr_tsc_deadline = true;
2072 break;
2073 case MSR_IA32_SMBASE:
2074 has_msr_smbase = true;
2075 break;
2076 case MSR_SMI_COUNT:
2077 has_msr_smi_count = true;
2078 break;
2079 case MSR_IA32_MISC_ENABLE:
2080 has_msr_misc_enable = true;
2081 break;
2082 case MSR_IA32_BNDCFGS:
2083 has_msr_bndcfgs = true;
2084 break;
2085 case MSR_IA32_XSS:
2086 has_msr_xss = true;
2087 break;
65087997
TX		 2088 case MSR_IA32_UMWAIT_CONTROL:
2089 has_msr_umwait = true;
2090 break;
de428cea
LQ		 2091 case HV_X64_MSR_CRASH_CTL:
2092 has_msr_hv_crash = true;
2093 break;
2094 case HV_X64_MSR_RESET:
2095 has_msr_hv_reset = true;
2096 break;
2097 case HV_X64_MSR_VP_INDEX:
2098 has_msr_hv_vpindex = true;
2099 break;
2100 case HV_X64_MSR_VP_RUNTIME:
2101 has_msr_hv_runtime = true;
2102 break;
2103 case HV_X64_MSR_SCONTROL:
2104 has_msr_hv_synic = true;
2105 break;
2106 case HV_X64_MSR_STIMER0_CONFIG:
2107 has_msr_hv_stimer = true;
2108 break;
2109 case HV_X64_MSR_TSC_FREQUENCY:
2110 has_msr_hv_frequencies = true;
2111 break;
2112 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2113 has_msr_hv_reenlightenment = true;
2114 break;
2115 case MSR_IA32_SPEC_CTRL:
2116 has_msr_spec_ctrl = true;
2117 break;
2a9758c5
PB		 2118 case MSR_IA32_TSX_CTRL:
2119 has_msr_tsx_ctrl = true;
2120 break;
de428cea
LQ		 2121 case MSR_VIRT_SSBD:
2122 has_msr_virt_ssbd = true;
2123 break;
2124 case MSR_IA32_ARCH_CAPABILITIES:
2125 has_msr_arch_capabs = true;
2126 break;
2127 case MSR_IA32_CORE_CAPABILITY:
2128 has_msr_core_capabs = true;
2129 break;
ea39f9b6
LX		 2130 case MSR_IA32_PERF_CAPABILITIES:
2131 has_msr_perf_capabs = true;
2132 break;
20a78b02
PB		 2133 case MSR_IA32_VMX_VMFUNC:
2134 has_msr_vmx_vmfunc = true;
2135 break;
67025148
PB		 2136 case MSR_IA32_UCODE_REV:
2137 has_msr_ucode_rev = true;
2138 break;
4a910e1f
VK		 2139 case MSR_IA32_VMX_PROCBASED_CTLS2:
2140 has_msr_vmx_procbased_ctls2 = true;
2141 break;
6aa4228b
CQ		 2142 case MSR_IA32_PKRS:
2143 has_msr_pkrs = true;
2144 break;
05330448
AL		 2145 }
2146 }
05330448
AL		 2147 }
2148
de428cea
LQ		 2149 g_free(kvm_msr_list);
2150
c3a3a7d3 2151 return ret;
05330448
AL		 2152}
2153
6410848b
PB		 2154static Notifier smram_machine_done;
2155static KVMMemoryListener smram_listener;
2156static AddressSpace smram_address_space;
2157static MemoryRegion smram_as_root;
2158static MemoryRegion smram_as_mem;
2159
2160static void register_smram_listener(Notifier *n, void *unused)
2161{
2162 MemoryRegion *smram =
2163 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2164
2165 /* Outer container... */
2166 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2167 memory_region_set_enabled(&smram_as_root, true);
2168
2169 /* ... with two regions inside: normal system memory with low
2170 * priority, and...
2171 */
2172 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2173 get_system_memory(), 0, ~0ull);
2174 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2175 memory_region_set_enabled(&smram_as_mem, true);
2176
2177 if (smram) {
2178 /* ... SMRAM with higher priority */
2179 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2180 memory_region_set_enabled(smram, true);
2181 }
2182
2183 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2184 kvm_memory_listener_register(kvm_state, &smram_listener,
2185 &smram_address_space, 1);
2186}
2187
b16565b3 2188int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 2189{
11076198 2190 uint64_t identity_base = 0xfffbc000;
39d6960a 2191 uint64_t shadow_mem;
20420430 2192 int ret;
25d2e361 2193 struct utsname utsname;
ec78e2cd
DG		 2194 Error *local_err = NULL;
2195
2196 /*
2197 * Initialize SEV context, if required
2198 *
2199 * If no memory encryption is requested (ms->cgs == NULL) this is
2200 * a no-op.
2201 *
2202 * It's also a no-op if a non-SEV confidential guest support
2203 * mechanism is selected. SEV is the only mechanism available to
2204 * select on x86 at present, so this doesn't arise, but if new
2205 * mechanisms are supported in future (e.g. TDX), they'll need
2206 * their own initialization either here or elsewhere.
2207 */
2208 ret = sev_kvm_init(ms->cgs, &local_err);
2209 if (ret < 0) {
2210 error_report_err(local_err);
2211 return ret;
2212 }
20420430 2213
1a6dff5f
EH		 2214 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
2215 error_report("kvm: KVM_CAP_IRQ_ROUTING not supported by KVM");
2216 return -ENOTSUP;
2217 }
2218
28143b40 2219 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 2220 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 2221 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 2222
e9688fab
RK		 2223 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2224
fd13f23b
LA		 2225 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2226 if (has_exception_payload) {
2227 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2228 if (ret < 0) {
2229 error_report("kvm: Failed to enable exception payload cap: %s",
2230 strerror(-ret));
2231 return ret;
2232 }
2233 }
2234
c3a3a7d3 2235 ret = kvm_get_supported_msrs(s);
20420430 2236 if (ret < 0) {
20420430
SY		 2237 return ret;
2238 }
25d2e361 2239
f57bceb6
RH		 2240 kvm_get_supported_feature_msrs(s);
2241
25d2e361
MT		 2242 uname(&utsname);
2243 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2244
4c5b10b7 2245 /*
11076198
JK		 2246 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2247 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2248 * Since these must be part of guest physical memory, we need to allocate
2249 * them, both by setting their start addresses in the kernel and by
2250 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2251 *
2252 * Older KVM versions may not support setting the identity map base. In
2253 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2254 * size.
4c5b10b7 2255 */
11076198
JK		 2256 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2257 /* Allows up to 16M BIOSes. */
2258 identity_base = 0xfeffc000;
2259
2260 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2261 if (ret < 0) {
2262 return ret;
2263 }
4c5b10b7 2264 }
e56ff191 2265
11076198
JK		 2266 /* Set TSS base one page after EPT identity map. */
2267 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2268 if (ret < 0) {
2269 return ret;
2270 }
2271
11076198
JK		 2272 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2273 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2274 if (ret < 0) {
11076198 2275 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2276 return ret;
2277 }
2278
23b0898e 2279 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
36ad0e94
MA		 2280 if (shadow_mem != -1) {
2281 shadow_mem /= 4096;
2282 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2283 if (ret < 0) {
2284 return ret;
39d6960a
JK		 2285 }
2286 }
6410848b 2287
d870cfde 2288 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
8f54bbd0 2289 object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE) &&
ed9e923c 2290 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
6410848b
PB		 2291 smram_machine_done.notify = register_smram_listener;
2292 qemu_add_machine_init_done_notifier(&smram_machine_done);
2293 }
6f131f13
MT		 2294
2295 if (enable_cpu_pm) {
2296 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2297 int ret;
2298
2299/* Work around for kernel header with a typo. TODO: fix header and drop. */
2300#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2301#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2302#endif
2303 if (disable_exits) {
2304 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2305 KVM_X86_DISABLE_EXITS_HLT |
d38d201f
WL		 2306 KVM_X86_DISABLE_EXITS_PAUSE |
2307 KVM_X86_DISABLE_EXITS_CSTATE);
6f131f13
MT		 2308 }
2309
2310 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2311 disable_exits);
2312 if (ret < 0) {
2313 error_report("kvm: guest stopping CPU not supported: %s",
2314 strerror(-ret));
2315 }
2316 }
2317
035d1ef2
CQ		 2318 if (object_dynamic_cast(OBJECT(ms), TYPE_X86_MACHINE)) {
2319 X86MachineState *x86ms = X86_MACHINE(ms);
2320
2321 if (x86ms->bus_lock_ratelimit > 0) {
2322 ret = kvm_check_extension(s, KVM_CAP_X86_BUS_LOCK_EXIT);
2323 if (!(ret & KVM_BUS_LOCK_DETECTION_EXIT)) {
2324 error_report("kvm: bus lock detection unsupported");
2325 return -ENOTSUP;
2326 }
2327 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_BUS_LOCK_EXIT, 0,
2328 KVM_BUS_LOCK_DETECTION_EXIT);
2329 if (ret < 0) {
2330 error_report("kvm: Failed to enable bus lock detection cap: %s",
2331 strerror(-ret));
2332 return ret;
2333 }
2334 ratelimit_init(&bus_lock_ratelimit_ctrl);
2335 ratelimit_set_speed(&bus_lock_ratelimit_ctrl,
2336 x86ms->bus_lock_ratelimit, BUS_LOCK_SLICE_TIME);
2337 }
2338 }
2339
11076198 2340 return 0;
05330448 2341}
b9bec74b 2342
05330448
AL		 2343static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2344{
2345 lhs->selector = rhs->selector;
2346 lhs->base = rhs->base;
2347 lhs->limit = rhs->limit;
2348 lhs->type = 3;
2349 lhs->present = 1;
2350 lhs->dpl = 3;
2351 lhs->db = 0;
2352 lhs->s = 1;
2353 lhs->l = 0;
2354 lhs->g = 0;
2355 lhs->avl = 0;
2356 lhs->unusable = 0;
2357}
2358
2359static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2360{
2361 unsigned flags = rhs->flags;
2362 lhs->selector = rhs->selector;
2363 lhs->base = rhs->base;
2364 lhs->limit = rhs->limit;
2365 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2366 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2367 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2368 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2369 lhs->s = (flags & DESC_S_MASK) != 0;
2370 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2371 lhs->g = (flags & DESC_G_MASK) != 0;
2372 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2373 lhs->unusable = !lhs->present;
7e680753 2374 lhs->padding = 0;
05330448
AL		 2375}
2376
2377static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2378{
2379 lhs->selector = rhs->selector;
2380 lhs->base = rhs->base;
2381 lhs->limit = rhs->limit;
d45fc087
RP		 2382 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2383 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2384 (rhs->dpl << DESC_DPL_SHIFT) |
2385 (rhs->db << DESC_B_SHIFT) |
2386 (rhs->s * DESC_S_MASK) |
2387 (rhs->l << DESC_L_SHIFT) |
2388 (rhs->g * DESC_G_MASK) |
2389 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2390}
2391
2392static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2393{
b9bec74b 2394 if (set) {
05330448 2395 *kvm_reg = *qemu_reg;
b9bec74b 2396 } else {
05330448 2397 *qemu_reg = *kvm_reg;
b9bec74b 2398 }
05330448
AL		 2399}
2400
1bc22652 2401static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2402{
1bc22652 2403 CPUX86State *env = &cpu->env;
05330448
AL		 2404 struct kvm_regs regs;
2405 int ret = 0;
2406
2407 if (!set) {
1bc22652 2408 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2409 if (ret < 0) {
05330448 2410 return ret;
b9bec74b 2411 }
05330448
AL		 2412 }
2413
2414 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2415 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2416 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2417 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2418 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2419 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2420 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2421 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2422#ifdef TARGET_X86_64
2423 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2424 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2425 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2426 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2427 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2428 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2429 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2430 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2431#endif
2432
2433 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2434 kvm_getput_reg(&regs.rip, &env->eip, set);
2435
b9bec74b 2436 if (set) {
1bc22652 2437 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2438 }
05330448
AL		 2439
2440 return ret;
2441}
2442
1bc22652 2443static int kvm_put_fpu(X86CPU *cpu)
05330448 2444{
1bc22652 2445 CPUX86State *env = &cpu->env;
05330448
AL		 2446 struct kvm_fpu fpu;
2447 int i;
2448
2449 memset(&fpu, 0, sizeof fpu);
2450 fpu.fsw = env->fpus & ~(7 << 11);
2451 fpu.fsw |= (env->fpstt & 7) << 11;
2452 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2453 fpu.last_opcode = env->fpop;
2454 fpu.last_ip = env->fpip;
2455 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2456 for (i = 0; i < 8; ++i) {
2457 fpu.ftwx |= (!env->fptags[i]) << i;
2458 }
05330448 2459 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2460 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2461 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2462 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2463 }
05330448
AL		 2464 fpu.mxcsr = env->mxcsr;
2465
1bc22652 2466 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2467}
2468
1bc22652 2469static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2470{
1bc22652 2471 CPUX86State *env = &cpu->env;
5b8063c4 2472 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2473
28143b40 2474 if (!has_xsave) {
1bc22652 2475 return kvm_put_fpu(cpu);
b9bec74b 2476 }
86a57621 2477 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2478
9be38598 2479 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2480}
2481
1bc22652 2482static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2483{
1bc22652 2484 CPUX86State *env = &cpu->env;
bdfc8480 2485 struct kvm_xcrs xcrs = {};
f1665b21 2486
28143b40 2487 if (!has_xcrs) {
f1665b21 2488 return 0;
b9bec74b 2489 }
f1665b21
SY		 2490
2491 xcrs.nr_xcrs = 1;
2492 xcrs.flags = 0;
2493 xcrs.xcrs[0].xcr = 0;
2494 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2495 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2496}
2497
1bc22652 2498static int kvm_put_sregs(X86CPU *cpu)
05330448 2499{
1bc22652 2500 CPUX86State *env = &cpu->env;
05330448
AL		 2501 struct kvm_sregs sregs;
2502
0e607a80
JK		 2503 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2504 if (env->interrupt_injected >= 0) {
2505 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2506 (uint64_t)1 << (env->interrupt_injected % 64);
2507 }
05330448
AL		 2508
2509 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2510 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2511 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2512 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2513 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2514 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2515 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2516 } else {
b9bec74b
JK		 2517 set_seg(&sregs.cs, &env->segs[R_CS]);
2518 set_seg(&sregs.ds, &env->segs[R_DS]);
2519 set_seg(&sregs.es, &env->segs[R_ES]);
2520 set_seg(&sregs.fs, &env->segs[R_FS]);
2521 set_seg(&sregs.gs, &env->segs[R_GS]);
2522 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2523 }
2524
2525 set_seg(&sregs.tr, &env->tr);
2526 set_seg(&sregs.ldt, &env->ldt);
2527
2528 sregs.idt.limit = env->idt.limit;
2529 sregs.idt.base = env->idt.base;
7e680753 2530 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2531 sregs.gdt.limit = env->gdt.limit;
2532 sregs.gdt.base = env->gdt.base;
7e680753 2533 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2534
2535 sregs.cr0 = env->cr[0];
2536 sregs.cr2 = env->cr[2];
2537 sregs.cr3 = env->cr[3];
2538 sregs.cr4 = env->cr[4];
2539
02e51483
CF		 2540 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2541 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2542
2543 sregs.efer = env->efer;
2544
1bc22652 2545 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2546}
2547
d71b62a1
EH		 2548static void kvm_msr_buf_reset(X86CPU *cpu)
2549{
2550 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2551}
2552
9c600a84
EH		 2553static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2554{
2555 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2556 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2557 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2558
2559 assert((void *)(entry + 1) <= limit);
2560
1abc2cae
EH		 2561 entry->index = index;
2562 entry->reserved = 0;
2563 entry->data = value;
9c600a84
EH		 2564 msrs->nmsrs++;
2565}
2566
73e1b8f2
PB		 2567static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2568{
2569 kvm_msr_buf_reset(cpu);
2570 kvm_msr_entry_add(cpu, index, value);
2571
2572 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2573}
2574
f8d9ccf8
DDAG		 2575void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2576{
2577 int ret;
2578
2579 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2580 assert(ret == 1);
2581}
2582
7477cd38
MT		 2583static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2584{
2585 CPUX86State *env = &cpu->env;
48e1a45c 2586 int ret;
7477cd38
MT		 2587
2588 if (!has_msr_tsc_deadline) {
2589 return 0;
2590 }
2591
73e1b8f2 2592 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2593 if (ret < 0) {
2594 return ret;
2595 }
2596
2597 assert(ret == 1);
2598 return 0;
7477cd38
MT		 2599}
2600
6bdf863d
JK		 2601/*
2602 * Provide a separate write service for the feature control MSR in order to
2603 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2604 * before writing any other state because forcibly leaving nested mode
2605 * invalidates the VCPU state.
2606 */
2607static int kvm_put_msr_feature_control(X86CPU *cpu)
2608{
48e1a45c
PB		 2609 int ret;
2610
2611 if (!has_msr_feature_control) {
2612 return 0;
2613 }
6bdf863d 2614
73e1b8f2
PB		 2615 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2616 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2617 if (ret < 0) {
2618 return ret;
2619 }
2620
2621 assert(ret == 1);
2622 return 0;
6bdf863d
JK		 2623}
2624
20a78b02
PB		 2625static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2626{
2627 uint32_t default1, can_be_one, can_be_zero;
2628 uint32_t must_be_one;
2629
2630 switch (index) {
2631 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2632 default1 = 0x00000016;
2633 break;
2634 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2635 default1 = 0x0401e172;
2636 break;
2637 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2638 default1 = 0x000011ff;
2639 break;
2640 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2641 default1 = 0x00036dff;
2642 break;
2643 case MSR_IA32_VMX_PROCBASED_CTLS2:
2644 default1 = 0;
2645 break;
2646 default:
2647 abort();
2648 }
2649
2650 /* If a feature bit is set, the control can be either set or clear.
2651 * Otherwise the value is limited to either 0 or 1 by default1.
2652 */
2653 can_be_one = features | default1;
2654 can_be_zero = features | ~default1;
2655 must_be_one = ~can_be_zero;
2656
2657 /*
2658 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2659 * Bit 32:63 -> 1 if the control bit can be one.
2660 */
2661 return must_be_one | (((uint64_t)can_be_one) << 32);
2662}
2663
20a78b02
PB		 2664static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2665{
2666 uint64_t kvm_vmx_basic =
2667 kvm_arch_get_supported_msr_feature(kvm_state,
2668 MSR_IA32_VMX_BASIC);
26051882
YZ		 2669
2670 if (!kvm_vmx_basic) {
2671 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2672 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2673 */
2674 return;
2675 }
2676
20a78b02
PB		 2677 uint64_t kvm_vmx_misc =
2678 kvm_arch_get_supported_msr_feature(kvm_state,
2679 MSR_IA32_VMX_MISC);
2680 uint64_t kvm_vmx_ept_vpid =
2681 kvm_arch_get_supported_msr_feature(kvm_state,
2682 MSR_IA32_VMX_EPT_VPID_CAP);
2683
2684 /*
2685 * If the guest is 64-bit, a value of 1 is allowed for the host address
2686 * space size vmexit control.
2687 */
2688 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2689 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2690
2691 /*
2692 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2693 * not change them for backwards compatibility.
2694 */
2695 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2696 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2697 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2698 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2699
2700 /*
2701 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2702 * change in the future but are always zero for now, clear them to be
2703 * future proof. Bits 32-63 in theory could change, though KVM does
2704 * not support dual-monitor treatment and probably never will; mask
2705 * them out as well.
2706 */
2707 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2708 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2709 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2710
2711 /*
2712 * EPT memory types should not change either, so we do not bother
2713 * adding features for them.
2714 */
2715 uint64_t fixed_vmx_ept_mask =
2716 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2717 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2718 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2719
2720 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2721 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2722 f[FEAT_VMX_PROCBASED_CTLS]));
2723 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2724 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2725 f[FEAT_VMX_PINBASED_CTLS]));
2726 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2727 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2728 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2729 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2730 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2731 f[FEAT_VMX_ENTRY_CTLS]));
2732 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2733 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2734 f[FEAT_VMX_SECONDARY_CTLS]));
2735 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2736 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2737 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2738 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2739 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2740 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2741 if (has_msr_vmx_vmfunc) {
2742 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2743 }
2744
2745 /*
2746 * Just to be safe, write these with constant values. The CRn_FIXED1
2747 * MSRs are generated by KVM based on the vCPU's CPUID.
2748 */
2749 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2750 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2751 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2752 CR4_VMXE_MASK);
9ce8af4d
PB		 2753
2754 if (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_TSC_SCALING) {
2755 /* TSC multiplier (0x2032). */
2756 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x32);
2757 } else {
2758 /* Preemption timer (0x482E). */
2759 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM, 0x2E);
2760 }
20a78b02
PB		 2761}
2762
ea39f9b6
LX		 2763static void kvm_msr_entry_add_perf(X86CPU *cpu, FeatureWordArray f)
2764{
2765 uint64_t kvm_perf_cap =
2766 kvm_arch_get_supported_msr_feature(kvm_state,
2767 MSR_IA32_PERF_CAPABILITIES);
2768
2769 if (kvm_perf_cap) {
2770 kvm_msr_entry_add(cpu, MSR_IA32_PERF_CAPABILITIES,
2771 kvm_perf_cap & f[FEAT_PERF_CAPABILITIES]);
2772 }
2773}
2774
420ae1fc
PB		 2775static int kvm_buf_set_msrs(X86CPU *cpu)
2776{
2777 int ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2778 if (ret < 0) {
2779 return ret;
2780 }
2781
2782 if (ret < cpu->kvm_msr_buf->nmsrs) {
2783 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2784 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2785 (uint32_t)e->index, (uint64_t)e->data);
2786 }
2787
2788 assert(ret == cpu->kvm_msr_buf->nmsrs);
2789 return 0;
2790}
2791
2792static void kvm_init_msrs(X86CPU *cpu)
2793{
2794 CPUX86State *env = &cpu->env;
2795
2796 kvm_msr_buf_reset(cpu);
2797 if (has_msr_arch_capabs) {
2798 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2799 env->features[FEAT_ARCH_CAPABILITIES]);
2800 }
2801
2802 if (has_msr_core_capabs) {
2803 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2804 env->features[FEAT_CORE_CAPABILITY]);
2805 }
2806
ea39f9b6
LX		 2807 if (has_msr_perf_capabs && cpu->enable_pmu) {
2808 kvm_msr_entry_add_perf(cpu, env->features);
2809 }
2810
67025148 2811 if (has_msr_ucode_rev) {
32c87d70
PB		 2812 kvm_msr_entry_add(cpu, MSR_IA32_UCODE_REV, cpu->ucode_rev);
2813 }
2814
420ae1fc
PB		 2815 /*
2816 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2817 * all kernels with MSR features should have them.
2818 */
2819 if (kvm_feature_msrs && cpu_has_vmx(env)) {
2820 kvm_msr_entry_add_vmx(cpu, env->features);
2821 }
2822
2823 assert(kvm_buf_set_msrs(cpu) == 0);
2824}
2825
1bc22652 2826static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2827{
1bc22652 2828 CPUX86State *env = &cpu->env;
9c600a84 2829 int i;
05330448 2830
d71b62a1
EH		 2831 kvm_msr_buf_reset(cpu);
2832
9c600a84
EH		 2833 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2834 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2835 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2836 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2837 if (has_msr_star) {
9c600a84 2838 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2839 }
c3a3a7d3 2840 if (has_msr_hsave_pa) {
9c600a84 2841 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2842 }
c9b8f6b6 2843 if (has_msr_tsc_aux) {
9c600a84 2844 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2845 }
f28558d3 2846 if (has_msr_tsc_adjust) {
9c600a84 2847 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2848 }
21e87c46 2849 if (has_msr_misc_enable) {
9c600a84 2850 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2851 env->msr_ia32_misc_enable);
2852 }
fc12d72e 2853 if (has_msr_smbase) {
9c600a84 2854 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2855 }
e13713db
LA		 2856 if (has_msr_smi_count) {
2857 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2858 }
6aa4228b
CQ		 2859 if (has_msr_pkrs) {
2860 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, env->pkrs);
2861 }
439d19f2 2862 if (has_msr_bndcfgs) {
9c600a84 2863 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2864 }
18cd2c17 2865 if (has_msr_xss) {
9c600a84 2866 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2867 }
65087997
TX		 2868 if (has_msr_umwait) {
2869 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
2870 }
a33a2cfe
PB		 2871 if (has_msr_spec_ctrl) {
2872 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2873 }
2a9758c5
PB		 2874 if (has_msr_tsx_ctrl) {
2875 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
2876 }
cfeea0c0
KRW		 2877 if (has_msr_virt_ssbd) {
2878 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2879 }
2880
05330448 2881#ifdef TARGET_X86_64
25d2e361 2882 if (lm_capable_kernel) {
9c600a84
EH		 2883 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2884 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2885 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2886 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2887 }
05330448 2888#endif
a33a2cfe 2889
ff5c186b 2890 /*
0d894367
PB		 2891 * The following MSRs have side effects on the guest or are too heavy
2892 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2893 */
2894 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2895 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2896 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2897 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
6615be07
VK		 2898 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
2899 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, env->async_pf_int_msr);
2900 }
55c911a5 2901 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2902 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2903 }
55c911a5 2904 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2905 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2906 }
55c911a5 2907 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2908 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2909 }
d645e132
MT		 2910
2911 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2912 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2913 }
2914
0b368a10
JD		 2915 if (has_architectural_pmu_version > 0) {
2916 if (has_architectural_pmu_version > 1) {
2917 /* Stop the counter. */
2918 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2919 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2920 }
0d894367
PB		 2921
2922 /* Set the counter values. */
0b368a10 2923 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2924 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2925 env->msr_fixed_counters[i]);
2926 }
0b368a10 2927 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2928 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2929 env->msr_gp_counters[i]);
9c600a84 2930 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2931 env->msr_gp_evtsel[i]);
2932 }
0b368a10
JD		 2933 if (has_architectural_pmu_version > 1) {
2934 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2935 env->msr_global_status);
2936 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2937 env->msr_global_ovf_ctrl);
2938
2939 /* Now start the PMU. */
2940 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2941 env->msr_fixed_ctr_ctrl);
2942 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2943 env->msr_global_ctrl);
2944 }
0d894367 2945 }
da1cc323
EY		 2946 /*
2947 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2948 * only sync them to KVM on the first cpu
2949 */
2950 if (current_cpu == first_cpu) {
2951 if (has_msr_hv_hypercall) {
2952 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2953 env->msr_hv_guest_os_id);
2954 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2955 env->msr_hv_hypercall);
2956 }
2d384d7c 2957 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2958 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2959 env->msr_hv_tsc);
2960 }
2d384d7c 2961 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2962 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2963 env->msr_hv_reenlightenment_control);
2964 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2965 env->msr_hv_tsc_emulation_control);
2966 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2967 env->msr_hv_tsc_emulation_status);
2968 }
eab70139 2969 }
2d384d7c 2970 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2971 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2972 env->msr_hv_vapic);
eab70139 2973 }
f2a53c9e
AS		 2974 if (has_msr_hv_crash) {
2975 int j;
2976
5e953812 2977 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2978 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2979 env->msr_hv_crash_params[j]);
2980
5e953812 2981 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2982 }
46eb8f98 2983 if (has_msr_hv_runtime) {
9c600a84 2984 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2985 }
2d384d7c
VK		 2986 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2987 && hv_vpindex_settable) {
701189e3
RK		 2988 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2989 hyperv_vp_index(CPU(cpu)));
e9688fab 2990 }
2d384d7c 2991 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2992 int j;
2993
09df29b6
RK		 2994 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2995
9c600a84 2996 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2997 env->msr_hv_synic_control);
9c600a84 2998 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2999 env->msr_hv_synic_evt_page);
9c600a84 3000 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 3001 env->msr_hv_synic_msg_page);
3002
3003 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 3004 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 3005 env->msr_hv_synic_sint[j]);
3006 }
3007 }
ff99aa64
AS		 3008 if (has_msr_hv_stimer) {
3009 int j;
3010
3011 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 3012 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 3013 env->msr_hv_stimer_config[j]);
3014 }
3015
3016 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 3017 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 3018 env->msr_hv_stimer_count[j]);
3019 }
3020 }
1eabfce6 3021 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 3022 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
3023
9c600a84
EH		 3024 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
3025 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
3026 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
3027 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
3028 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
3029 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
3030 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
3031 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
3032 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
3033 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
3034 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
3035 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 3036 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 3037 /* The CPU GPs if we write to a bit above the physical limit of
3038 * the host CPU (and KVM emulates that)
3039 */
3040 uint64_t mask = env->mtrr_var[i].mask;
3041 mask &= phys_mask;
3042
9c600a84
EH		 3043 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
3044 env->mtrr_var[i].base);
112dad69 3045 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 3046 }
3047 }
b77146e9
CP		 3048 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3049 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
3050 0x14, 1, R_EAX) & 0x7;
3051
3052 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
3053 env->msr_rtit_ctrl);
3054 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
3055 env->msr_rtit_status);
3056 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
3057 env->msr_rtit_output_base);
3058 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
3059 env->msr_rtit_output_mask);
3060 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
3061 env->msr_rtit_cr3_match);
3062 for (i = 0; i < addr_num; i++) {
3063 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
3064 env->msr_rtit_addrs[i]);
3065 }
3066 }
6bdf863d
JK		 3067
3068 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
3069 * kvm_put_msr_feature_control. */
ea643051 3070 }
20a78b02 3071
57780495 3072 if (env->mcg_cap) {
d8da8574 3073 int i;
b9bec74b 3074
9c600a84
EH		 3075 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
3076 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 3077 if (has_msr_mcg_ext_ctl) {
3078 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
3079 }
c34d440a 3080 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3081 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 3082 }
3083 }
1a03675d 3084
420ae1fc 3085 return kvm_buf_set_msrs(cpu);
05330448
AL		 3086}
3087
3088
1bc22652 3089static int kvm_get_fpu(X86CPU *cpu)
05330448 3090{
1bc22652 3091 CPUX86State *env = &cpu->env;
05330448
AL		 3092 struct kvm_fpu fpu;
3093 int i, ret;
3094
1bc22652 3095 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 3096 if (ret < 0) {
05330448 3097 return ret;
b9bec74b 3098 }
05330448
AL		 3099
3100 env->fpstt = (fpu.fsw >> 11) & 7;
3101 env->fpus = fpu.fsw;
3102 env->fpuc = fpu.fcw;
42cc8fa6
JK		 3103 env->fpop = fpu.last_opcode;
3104 env->fpip = fpu.last_ip;
3105 env->fpdp = fpu.last_dp;
b9bec74b
JK		 3106 for (i = 0; i < 8; ++i) {
3107 env->fptags[i] = !((fpu.ftwx >> i) & 1);
3108 }
05330448 3109 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 3110 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 3111 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
3112 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 3113 }
05330448
AL		 3114 env->mxcsr = fpu.mxcsr;
3115
3116 return 0;
3117}
3118
1bc22652 3119static int kvm_get_xsave(X86CPU *cpu)
f1665b21 3120{
1bc22652 3121 CPUX86State *env = &cpu->env;
5b8063c4 3122 X86XSaveArea *xsave = env->xsave_buf;
86a57621 3123 int ret;
f1665b21 3124
28143b40 3125 if (!has_xsave) {
1bc22652 3126 return kvm_get_fpu(cpu);
b9bec74b 3127 }
f1665b21 3128
1bc22652 3129 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 3130 if (ret < 0) {
f1665b21 3131 return ret;
0f53994f 3132 }
86a57621 3133 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 3134
f1665b21 3135 return 0;
f1665b21
SY		 3136}
3137
1bc22652 3138static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 3139{
1bc22652 3140 CPUX86State *env = &cpu->env;
f1665b21
SY		 3141 int i, ret;
3142 struct kvm_xcrs xcrs;
3143
28143b40 3144 if (!has_xcrs) {
f1665b21 3145 return 0;
b9bec74b 3146 }
f1665b21 3147
1bc22652 3148 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 3149 if (ret < 0) {
f1665b21 3150 return ret;
b9bec74b 3151 }
f1665b21 3152
b9bec74b 3153 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 3154 /* Only support xcr0 now */
0fd53fec
PB		 3155 if (xcrs.xcrs[i].xcr == 0) {
3156 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 3157 break;
3158 }
b9bec74b 3159 }
f1665b21 3160 return 0;
f1665b21
SY		 3161}
3162
1bc22652 3163static int kvm_get_sregs(X86CPU *cpu)
05330448 3164{
1bc22652 3165 CPUX86State *env = &cpu->env;
05330448 3166 struct kvm_sregs sregs;
0e607a80 3167 int bit, i, ret;
05330448 3168
1bc22652 3169 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 3170 if (ret < 0) {
05330448 3171 return ret;
b9bec74b 3172 }
05330448 3173
0e607a80
JK		 3174 /* There can only be one pending IRQ set in the bitmap at a time, so try
3175 to find it and save its number instead (-1 for none). */
3176 env->interrupt_injected = -1;
3177 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
3178 if (sregs.interrupt_bitmap[i]) {
3179 bit = ctz64(sregs.interrupt_bitmap[i]);
3180 env->interrupt_injected = i * 64 + bit;
3181 break;
3182 }
3183 }
05330448
AL		 3184
3185 get_seg(&env->segs[R_CS], &sregs.cs);
3186 get_seg(&env->segs[R_DS], &sregs.ds);
3187 get_seg(&env->segs[R_ES], &sregs.es);
3188 get_seg(&env->segs[R_FS], &sregs.fs);
3189 get_seg(&env->segs[R_GS], &sregs.gs);
3190 get_seg(&env->segs[R_SS], &sregs.ss);
3191
3192 get_seg(&env->tr, &sregs.tr);
3193 get_seg(&env->ldt, &sregs.ldt);
3194
3195 env->idt.limit = sregs.idt.limit;
3196 env->idt.base = sregs.idt.base;
3197 env->gdt.limit = sregs.gdt.limit;
3198 env->gdt.base = sregs.gdt.base;
3199
3200 env->cr[0] = sregs.cr0;
3201 env->cr[2] = sregs.cr2;
3202 env->cr[3] = sregs.cr3;
3203 env->cr[4] = sregs.cr4;
3204
05330448 3205 env->efer = sregs.efer;
cce47516
JK		 3206
3207 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 3208 x86_update_hflags(env);
05330448
AL		 3209
3210 return 0;
3211}
3212
1bc22652 3213static int kvm_get_msrs(X86CPU *cpu)
05330448 3214{
1bc22652 3215 CPUX86State *env = &cpu->env;
d71b62a1 3216 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 3217 int ret, i;
fcc35e7c 3218 uint64_t mtrr_top_bits;
05330448 3219
d71b62a1
EH		 3220 kvm_msr_buf_reset(cpu);
3221
9c600a84
EH		 3222 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3223 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3224 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3225 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 3226 if (has_msr_star) {
9c600a84 3227 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 3228 }
c3a3a7d3 3229 if (has_msr_hsave_pa) {
9c600a84 3230 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 3231 }
c9b8f6b6 3232 if (has_msr_tsc_aux) {
9c600a84 3233 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 3234 }
f28558d3 3235 if (has_msr_tsc_adjust) {
9c600a84 3236 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 3237 }
aa82ba54 3238 if (has_msr_tsc_deadline) {
9c600a84 3239 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 3240 }
21e87c46 3241 if (has_msr_misc_enable) {
9c600a84 3242 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 3243 }
fc12d72e 3244 if (has_msr_smbase) {
9c600a84 3245 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 3246 }
e13713db
LA		 3247 if (has_msr_smi_count) {
3248 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3249 }
df67696e 3250 if (has_msr_feature_control) {
9c600a84 3251 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 3252 }
6aa4228b
CQ		 3253 if (has_msr_pkrs) {
3254 kvm_msr_entry_add(cpu, MSR_IA32_PKRS, 0);
3255 }
79e9ebeb 3256 if (has_msr_bndcfgs) {
9c600a84 3257 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 3258 }
18cd2c17 3259 if (has_msr_xss) {
9c600a84 3260 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 3261 }
65087997
TX		 3262 if (has_msr_umwait) {
3263 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3264 }
a33a2cfe
PB		 3265 if (has_msr_spec_ctrl) {
3266 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3267 }
2a9758c5
PB		 3268 if (has_msr_tsx_ctrl) {
3269 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3270 }
cfeea0c0
KRW		 3271 if (has_msr_virt_ssbd) {
3272 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3273 }
b8cc45d6 3274 if (!env->tsc_valid) {
9c600a84 3275 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 3276 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 3277 }
3278
05330448 3279#ifdef TARGET_X86_64
25d2e361 3280 if (lm_capable_kernel) {
9c600a84
EH		 3281 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3282 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3283 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3284 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 3285 }
05330448 3286#endif
9c600a84
EH		 3287 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3288 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
db5daafa
VK		 3289 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF_INT)) {
3290 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_INT, 0);
3291 }
6615be07
VK		 3292 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
3293 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
3294 }
55c911a5 3295 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3296 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 3297 }
55c911a5 3298 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3299 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 3300 }
d645e132
MT		 3301 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3302 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3303 }
0b368a10
JD		 3304 if (has_architectural_pmu_version > 0) {
3305 if (has_architectural_pmu_version > 1) {
3306 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3307 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3308 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3309 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3310 }
3311 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3312 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 3313 }
0b368a10 3314 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 3315 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3316 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 3317 }
3318 }
1a03675d 3319
57780495 3320 if (env->mcg_cap) {
9c600a84
EH		 3321 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3322 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 3323 if (has_msr_mcg_ext_ctl) {
3324 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3325 }
b9bec74b 3326 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3327 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 3328 }
57780495 3329 }
57780495 3330
1c90ef26 3331 if (has_msr_hv_hypercall) {
9c600a84
EH		 3332 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3333 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 3334 }
2d384d7c 3335 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3336 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 3337 }
2d384d7c 3338 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 3339 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 3340 }
2d384d7c 3341 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3342 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3343 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3344 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3345 }
f2a53c9e
AS		 3346 if (has_msr_hv_crash) {
3347 int j;
3348
5e953812 3349 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 3350 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 3351 }
3352 }
46eb8f98 3353 if (has_msr_hv_runtime) {
9c600a84 3354 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 3355 }
2d384d7c 3356 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3357 uint32_t msr;
3358
9c600a84 3359 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 3360 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3361 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 3362 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 3363 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 3364 }
3365 }
ff99aa64
AS		 3366 if (has_msr_hv_stimer) {
3367 uint32_t msr;
3368
3369 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3370 msr++) {
9c600a84 3371 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 3372 }
3373 }
1eabfce6 3374 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 3375 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3376 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3377 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3378 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3379 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3380 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3381 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3382 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3383 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3384 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3385 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3386 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 3387 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 3388 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3389 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 3390 }
3391 }
5ef68987 3392
b77146e9
CP		 3393 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3394 int addr_num =
3395 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3396
3397 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3398 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3399 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3400 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3401 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3402 for (i = 0; i < addr_num; i++) {
3403 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3404 }
3405 }
3406
d71b62a1 3407 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 3408 if (ret < 0) {
05330448 3409 return ret;
b9bec74b 3410 }
05330448 3411
c70b11d1
EH		 3412 if (ret < cpu->kvm_msr_buf->nmsrs) {
3413 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3414 error_report("error: failed to get MSR 0x%" PRIx32,
3415 (uint32_t)e->index);
3416 }
3417
9c600a84 3418 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 3419 /*
3420 * MTRR masks: Each mask consists of 5 parts
3421 * a 10..0: must be zero
3422 * b 11 : valid bit
3423 * c n-1.12: actual mask bits
3424 * d 51..n: reserved must be zero
3425 * e 63.52: reserved must be zero
3426 *
3427 * 'n' is the number of physical bits supported by the CPU and is
3428 * apparently always <= 52. We know our 'n' but don't know what
3429 * the destinations 'n' is; it might be smaller, in which case
3430 * it masks (c) on loading. It might be larger, in which case
3431 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3432 * we're migrating to.
3433 */
3434
3435 if (cpu->fill_mtrr_mask) {
3436 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3437 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3438 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3439 } else {
3440 mtrr_top_bits = 0;
3441 }
3442
05330448 3443 for (i = 0; i < ret; i++) {
0d894367
PB		 3444 uint32_t index = msrs[i].index;
3445 switch (index) {
05330448
AL		 3446 case MSR_IA32_SYSENTER_CS:
3447 env->sysenter_cs = msrs[i].data;
3448 break;
3449 case MSR_IA32_SYSENTER_ESP:
3450 env->sysenter_esp = msrs[i].data;
3451 break;
3452 case MSR_IA32_SYSENTER_EIP:
3453 env->sysenter_eip = msrs[i].data;
3454 break;
0c03266a
JK		 3455 case MSR_PAT:
3456 env->pat = msrs[i].data;
3457 break;
05330448
AL		 3458 case MSR_STAR:
3459 env->star = msrs[i].data;
3460 break;
3461#ifdef TARGET_X86_64
3462 case MSR_CSTAR:
3463 env->cstar = msrs[i].data;
3464 break;
3465 case MSR_KERNELGSBASE:
3466 env->kernelgsbase = msrs[i].data;
3467 break;
3468 case MSR_FMASK:
3469 env->fmask = msrs[i].data;
3470 break;
3471 case MSR_LSTAR:
3472 env->lstar = msrs[i].data;
3473 break;
3474#endif
3475 case MSR_IA32_TSC:
3476 env->tsc = msrs[i].data;
3477 break;
c9b8f6b6
AS		 3478 case MSR_TSC_AUX:
3479 env->tsc_aux = msrs[i].data;
3480 break;
f28558d3
WA		 3481 case MSR_TSC_ADJUST:
3482 env->tsc_adjust = msrs[i].data;
3483 break;
aa82ba54
LJ		 3484 case MSR_IA32_TSCDEADLINE:
3485 env->tsc_deadline = msrs[i].data;
3486 break;
aa851e36
MT		 3487 case MSR_VM_HSAVE_PA:
3488 env->vm_hsave = msrs[i].data;
3489 break;
1a03675d
GC		 3490 case MSR_KVM_SYSTEM_TIME:
3491 env->system_time_msr = msrs[i].data;
3492 break;
3493 case MSR_KVM_WALL_CLOCK:
3494 env->wall_clock_msr = msrs[i].data;
3495 break;
57780495
MT		 3496 case MSR_MCG_STATUS:
3497 env->mcg_status = msrs[i].data;
3498 break;
3499 case MSR_MCG_CTL:
3500 env->mcg_ctl = msrs[i].data;
3501 break;
87f8b626
AR		 3502 case MSR_MCG_EXT_CTL:
3503 env->mcg_ext_ctl = msrs[i].data;
3504 break;
21e87c46
AK		 3505 case MSR_IA32_MISC_ENABLE:
3506 env->msr_ia32_misc_enable = msrs[i].data;
3507 break;
fc12d72e
PB		 3508 case MSR_IA32_SMBASE:
3509 env->smbase = msrs[i].data;
3510 break;
e13713db
LA		 3511 case MSR_SMI_COUNT:
3512 env->msr_smi_count = msrs[i].data;
3513 break;
0779caeb
ACL		 3514 case MSR_IA32_FEATURE_CONTROL:
3515 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3516 break;
79e9ebeb
LJ		 3517 case MSR_IA32_BNDCFGS:
3518 env->msr_bndcfgs = msrs[i].data;
3519 break;
18cd2c17
WL		 3520 case MSR_IA32_XSS:
3521 env->xss = msrs[i].data;
3522 break;
65087997
TX		 3523 case MSR_IA32_UMWAIT_CONTROL:
3524 env->umwait = msrs[i].data;
3525 break;
6aa4228b
CQ		 3526 case MSR_IA32_PKRS:
3527 env->pkrs = msrs[i].data;
3528 break;
57780495 3529 default:
57780495
MT		 3530 if (msrs[i].index >= MSR_MC0_CTL &&
3531 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3532 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3533 }
d8da8574 3534 break;
f6584ee2
GN		 3535 case MSR_KVM_ASYNC_PF_EN:
3536 env->async_pf_en_msr = msrs[i].data;
3537 break;
db5daafa
VK		 3538 case MSR_KVM_ASYNC_PF_INT:
3539 env->async_pf_int_msr = msrs[i].data;
3540 break;
bc9a839d
MT		 3541 case MSR_KVM_PV_EOI_EN:
3542 env->pv_eoi_en_msr = msrs[i].data;
3543 break;
917367aa
MT		 3544 case MSR_KVM_STEAL_TIME:
3545 env->steal_time_msr = msrs[i].data;
3546 break;
d645e132
MT		 3547 case MSR_KVM_POLL_CONTROL: {
3548 env->poll_control_msr = msrs[i].data;
3549 break;
3550 }
0d894367
PB		 3551 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3552 env->msr_fixed_ctr_ctrl = msrs[i].data;
3553 break;
3554 case MSR_CORE_PERF_GLOBAL_CTRL:
3555 env->msr_global_ctrl = msrs[i].data;
3556 break;
3557 case MSR_CORE_PERF_GLOBAL_STATUS:
3558 env->msr_global_status = msrs[i].data;
3559 break;
3560 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3561 env->msr_global_ovf_ctrl = msrs[i].data;
3562 break;
3563 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3564 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3565 break;
3566 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3567 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3568 break;
3569 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3570 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3571 break;
1c90ef26
VR		 3572 case HV_X64_MSR_HYPERCALL:
3573 env->msr_hv_hypercall = msrs[i].data;
3574 break;
3575 case HV_X64_MSR_GUEST_OS_ID:
3576 env->msr_hv_guest_os_id = msrs[i].data;
3577 break;
5ef68987
VR		 3578 case HV_X64_MSR_APIC_ASSIST_PAGE:
3579 env->msr_hv_vapic = msrs[i].data;
3580 break;
48a5f3bc
VR		 3581 case HV_X64_MSR_REFERENCE_TSC:
3582 env->msr_hv_tsc = msrs[i].data;
3583 break;
f2a53c9e
AS		 3584 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3585 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3586 break;
46eb8f98
AS		 3587 case HV_X64_MSR_VP_RUNTIME:
3588 env->msr_hv_runtime = msrs[i].data;
3589 break;
866eea9a
AS		 3590 case HV_X64_MSR_SCONTROL:
3591 env->msr_hv_synic_control = msrs[i].data;
3592 break;
866eea9a
AS		 3593 case HV_X64_MSR_SIEFP:
3594 env->msr_hv_synic_evt_page = msrs[i].data;
3595 break;
3596 case HV_X64_MSR_SIMP:
3597 env->msr_hv_synic_msg_page = msrs[i].data;
3598 break;
3599 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3600 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3601 break;
3602 case HV_X64_MSR_STIMER0_CONFIG:
3603 case HV_X64_MSR_STIMER1_CONFIG:
3604 case HV_X64_MSR_STIMER2_CONFIG:
3605 case HV_X64_MSR_STIMER3_CONFIG:
3606 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3607 msrs[i].data;
3608 break;
3609 case HV_X64_MSR_STIMER0_COUNT:
3610 case HV_X64_MSR_STIMER1_COUNT:
3611 case HV_X64_MSR_STIMER2_COUNT:
3612 case HV_X64_MSR_STIMER3_COUNT:
3613 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3614 msrs[i].data;
866eea9a 3615 break;
ba6a4fd9
VK		 3616 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3617 env->msr_hv_reenlightenment_control = msrs[i].data;
3618 break;
3619 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3620 env->msr_hv_tsc_emulation_control = msrs[i].data;
3621 break;
3622 case HV_X64_MSR_TSC_EMULATION_STATUS:
3623 env->msr_hv_tsc_emulation_status = msrs[i].data;
3624 break;
d1ae67f6
AW		 3625 case MSR_MTRRdefType:
3626 env->mtrr_deftype = msrs[i].data;
3627 break;
3628 case MSR_MTRRfix64K_00000:
3629 env->mtrr_fixed[0] = msrs[i].data;
3630 break;
3631 case MSR_MTRRfix16K_80000:
3632 env->mtrr_fixed[1] = msrs[i].data;
3633 break;
3634 case MSR_MTRRfix16K_A0000:
3635 env->mtrr_fixed[2] = msrs[i].data;
3636 break;
3637 case MSR_MTRRfix4K_C0000:
3638 env->mtrr_fixed[3] = msrs[i].data;
3639 break;
3640 case MSR_MTRRfix4K_C8000:
3641 env->mtrr_fixed[4] = msrs[i].data;
3642 break;
3643 case MSR_MTRRfix4K_D0000:
3644 env->mtrr_fixed[5] = msrs[i].data;
3645 break;
3646 case MSR_MTRRfix4K_D8000:
3647 env->mtrr_fixed[6] = msrs[i].data;
3648 break;
3649 case MSR_MTRRfix4K_E0000:
3650 env->mtrr_fixed[7] = msrs[i].data;
3651 break;
3652 case MSR_MTRRfix4K_E8000:
3653 env->mtrr_fixed[8] = msrs[i].data;
3654 break;
3655 case MSR_MTRRfix4K_F0000:
3656 env->mtrr_fixed[9] = msrs[i].data;
3657 break;
3658 case MSR_MTRRfix4K_F8000:
3659 env->mtrr_fixed[10] = msrs[i].data;
3660 break;
3661 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3662 if (index & 1) {
fcc35e7c
DDAG		 3663 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3664 mtrr_top_bits;
d1ae67f6
AW		 3665 } else {
3666 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3667 }
3668 break;
a33a2cfe
PB		 3669 case MSR_IA32_SPEC_CTRL:
3670 env->spec_ctrl = msrs[i].data;
3671 break;
2a9758c5
PB		 3672 case MSR_IA32_TSX_CTRL:
3673 env->tsx_ctrl = msrs[i].data;
3674 break;
cfeea0c0
KRW		 3675 case MSR_VIRT_SSBD:
3676 env->virt_ssbd = msrs[i].data;
3677 break;
b77146e9
CP		 3678 case MSR_IA32_RTIT_CTL:
3679 env->msr_rtit_ctrl = msrs[i].data;
3680 break;
3681 case MSR_IA32_RTIT_STATUS:
3682 env->msr_rtit_status = msrs[i].data;
3683 break;
3684 case MSR_IA32_RTIT_OUTPUT_BASE:
3685 env->msr_rtit_output_base = msrs[i].data;
3686 break;
3687 case MSR_IA32_RTIT_OUTPUT_MASK:
3688 env->msr_rtit_output_mask = msrs[i].data;
3689 break;
3690 case MSR_IA32_RTIT_CR3_MATCH:
3691 env->msr_rtit_cr3_match = msrs[i].data;
3692 break;
3693 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3694 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3695 break;
05330448
AL		 3696 }
3697 }
3698
3699 return 0;
3700}
3701
1bc22652 3702static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3703{
1bc22652 3704 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3705
1bc22652 3706 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3707}
3708
23d02d9b 3709static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3710{
259186a7 3711 CPUState *cs = CPU(cpu);
23d02d9b 3712 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3713 struct kvm_mp_state mp_state;
3714 int ret;
3715
259186a7 3716 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3717 if (ret < 0) {
3718 return ret;
3719 }
3720 env->mp_state = mp_state.mp_state;
c14750e8 3721 if (kvm_irqchip_in_kernel()) {
259186a7 3722 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3723 }
9bdbe550
HB		 3724 return 0;
3725}
3726
1bc22652 3727static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3728{
02e51483 3729 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3730 struct kvm_lapic_state kapic;
3731 int ret;
3732
3d4b2649 3733 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3734 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3735 if (ret < 0) {
3736 return ret;
3737 }
3738
3739 kvm_get_apic_state(apic, &kapic);
3740 }
3741 return 0;
3742}
3743
1bc22652 3744static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3745{
fc12d72e 3746 CPUState *cs = CPU(cpu);
1bc22652 3747 CPUX86State *env = &cpu->env;
076796f8 3748 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3749
3750 if (!kvm_has_vcpu_events()) {
3751 return 0;
3752 }
3753
fd13f23b
LA		 3754 events.flags = 0;
3755
3756 if (has_exception_payload) {
3757 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3758 events.exception.pending = env->exception_pending;
3759 events.exception_has_payload = env->exception_has_payload;
3760 events.exception_payload = env->exception_payload;
3761 }
3762 events.exception.nr = env->exception_nr;
3763 events.exception.injected = env->exception_injected;
a0fb002c
JK		 3764 events.exception.has_error_code = env->has_error_code;
3765 events.exception.error_code = env->error_code;
3766
3767 events.interrupt.injected = (env->interrupt_injected >= 0);
3768 events.interrupt.nr = env->interrupt_injected;
3769 events.interrupt.soft = env->soft_interrupt;
3770
3771 events.nmi.injected = env->nmi_injected;
3772 events.nmi.pending = env->nmi_pending;
3773 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3774
3775 events.sipi_vector = env->sipi_vector;
3776
fc12d72e
PB		 3777 if (has_msr_smbase) {
3778 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3779 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3780 if (kvm_irqchip_in_kernel()) {
3781 /* As soon as these are moved to the kernel, remove them
3782 * from cs->interrupt_request.
3783 */
3784 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3785 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3786 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3787 } else {
3788 /* Keep these in cs->interrupt_request. */
3789 events.smi.pending = 0;
3790 events.smi.latched_init = 0;
3791 }
fc3a1fd7
DDAG		 3792 /* Stop SMI delivery on old machine types to avoid a reboot
3793 * on an inward migration of an old VM.
3794 */
3795 if (!cpu->kvm_no_smi_migration) {
3796 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3797 }
fc12d72e
PB		 3798 }
3799
ea643051 3800 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3801 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3802 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3803 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3804 }
ea643051 3805 }
aee028b9 3806
1bc22652 3807 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3808}
3809
1bc22652 3810static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3811{
1bc22652 3812 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3813 struct kvm_vcpu_events events;
3814 int ret;
3815
3816 if (!kvm_has_vcpu_events()) {
3817 return 0;
3818 }
3819
fc12d72e 3820 memset(&events, 0, sizeof(events));
1bc22652 3821 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3822 if (ret < 0) {
3823 return ret;
3824 }
fd13f23b
LA		 3825
3826 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3827 env->exception_pending = events.exception.pending;
3828 env->exception_has_payload = events.exception_has_payload;
3829 env->exception_payload = events.exception_payload;
3830 } else {
3831 env->exception_pending = 0;
3832 env->exception_has_payload = false;
3833 }
3834 env->exception_injected = events.exception.injected;
3835 env->exception_nr =
3836 (env->exception_pending || env->exception_injected) ?
3837 events.exception.nr : -1;
a0fb002c
JK		 3838 env->has_error_code = events.exception.has_error_code;
3839 env->error_code = events.exception.error_code;
3840
3841 env->interrupt_injected =
3842 events.interrupt.injected ? events.interrupt.nr : -1;
3843 env->soft_interrupt = events.interrupt.soft;
3844
3845 env->nmi_injected = events.nmi.injected;
3846 env->nmi_pending = events.nmi.pending;
3847 if (events.nmi.masked) {
3848 env->hflags2 |= HF2_NMI_MASK;
3849 } else {
3850 env->hflags2 &= ~HF2_NMI_MASK;
3851 }
3852
fc12d72e
PB		 3853 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3854 if (events.smi.smm) {
3855 env->hflags |= HF_SMM_MASK;
3856 } else {
3857 env->hflags &= ~HF_SMM_MASK;
3858 }
3859 if (events.smi.pending) {
3860 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3861 } else {
3862 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3863 }
3864 if (events.smi.smm_inside_nmi) {
3865 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3866 } else {
3867 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3868 }
3869 if (events.smi.latched_init) {
3870 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3871 } else {
3872 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3873 }
3874 }
3875
a0fb002c 3876 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3877
3878 return 0;
3879}
3880
1bc22652 3881static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3882{
ed2803da 3883 CPUState *cs = CPU(cpu);
1bc22652 3884 CPUX86State *env = &cpu->env;
b0b1d690 3885 int ret = 0;
b0b1d690
JK		 3886 unsigned long reinject_trap = 0;
3887
3888 if (!kvm_has_vcpu_events()) {
fd13f23b 3889 if (env->exception_nr == EXCP01_DB) {
b0b1d690 3890 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 3891 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 3892 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3893 }
fd13f23b 3894 kvm_reset_exception(env);
b0b1d690
JK		 3895 }
3896
3897 /*
3898 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3899 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3900 * by updating the debug state once again if single-stepping is on.
3901 * Another reason to call kvm_update_guest_debug here is a pending debug
3902 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3903 * reinject them via SET_GUEST_DEBUG.
3904 */
3905 if (reinject_trap ||
ed2803da 3906 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3907 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3908 }
b0b1d690
JK		 3909 return ret;
3910}
3911
1bc22652 3912static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3913{
1bc22652 3914 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3915 struct kvm_debugregs dbgregs;
3916 int i;
3917
3918 if (!kvm_has_debugregs()) {
3919 return 0;
3920 }
3921
1f670a95 3922 memset(&dbgregs, 0, sizeof(dbgregs));
ff44f1a3
JK		 3923 for (i = 0; i < 4; i++) {
3924 dbgregs.db[i] = env->dr[i];
3925 }
3926 dbgregs.dr6 = env->dr[6];
3927 dbgregs.dr7 = env->dr[7];
3928 dbgregs.flags = 0;
3929
1bc22652 3930 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3931}
3932
1bc22652 3933static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3934{
1bc22652 3935 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3936 struct kvm_debugregs dbgregs;
3937 int i, ret;
3938
3939 if (!kvm_has_debugregs()) {
3940 return 0;
3941 }
3942
1bc22652 3943 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3944 if (ret < 0) {
b9bec74b 3945 return ret;
ff44f1a3
JK		 3946 }
3947 for (i = 0; i < 4; i++) {
3948 env->dr[i] = dbgregs.db[i];
3949 }
3950 env->dr[4] = env->dr[6] = dbgregs.dr6;
3951 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3952
3953 return 0;
3954}
3955
ebbfef2f
LA		 3956static int kvm_put_nested_state(X86CPU *cpu)
3957{
3958 CPUX86State *env = &cpu->env;
3959 int max_nested_state_len = kvm_max_nested_state_length();
3960
1e44f3ab 3961 if (!env->nested_state) {
ebbfef2f
LA		 3962 return 0;
3963 }
3964
b16c0e20
PB		 3965 /*
3966 * Copy flags that are affected by reset from env->hflags and env->hflags2.
3967 */
3968 if (env->hflags & HF_GUEST_MASK) {
3969 env->nested_state->flags |= KVM_STATE_NESTED_GUEST_MODE;
3970 } else {
3971 env->nested_state->flags &= ~KVM_STATE_NESTED_GUEST_MODE;
3972 }
0baa4b44
VK		 3973
3974 /* Don't set KVM_STATE_NESTED_GIF_SET on VMX as it is illegal */
3975 if (cpu_has_svm(env) && (env->hflags2 & HF2_GIF_MASK)) {
b16c0e20
PB		 3976 env->nested_state->flags |= KVM_STATE_NESTED_GIF_SET;
3977 } else {
3978 env->nested_state->flags &= ~KVM_STATE_NESTED_GIF_SET;
3979 }
3980
ebbfef2f
LA		 3981 assert(env->nested_state->size <= max_nested_state_len);
3982 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3983}
3984
3985static int kvm_get_nested_state(X86CPU *cpu)
3986{
3987 CPUX86State *env = &cpu->env;
3988 int max_nested_state_len = kvm_max_nested_state_length();
3989 int ret;
3990
1e44f3ab 3991 if (!env->nested_state) {
ebbfef2f
LA		 3992 return 0;
3993 }
3994
3995 /*
3996 * It is possible that migration restored a smaller size into
3997 * nested_state->hdr.size than what our kernel support.
3998 * We preserve migration origin nested_state->hdr.size for
3999 * call to KVM_SET_NESTED_STATE but wish that our next call
4000 * to KVM_GET_NESTED_STATE will use max size our kernel support.
4001 */
4002 env->nested_state->size = max_nested_state_len;
4003
4004 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
4005 if (ret < 0) {
4006 return ret;
4007 }
4008
b16c0e20
PB		 4009 /*
4010 * Copy flags that are affected by reset to env->hflags and env->hflags2.
4011 */
ebbfef2f
LA		 4012 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
4013 env->hflags |= HF_GUEST_MASK;
4014 } else {
4015 env->hflags &= ~HF_GUEST_MASK;
4016 }
0baa4b44
VK		 4017
4018 /* Keep HF2_GIF_MASK set on !SVM as x86_cpu_pending_interrupt() needs it */
4019 if (cpu_has_svm(env)) {
4020 if (env->nested_state->flags & KVM_STATE_NESTED_GIF_SET) {
4021 env->hflags2 |= HF2_GIF_MASK;
4022 } else {
4023 env->hflags2 &= ~HF2_GIF_MASK;
4024 }
b16c0e20 4025 }
ebbfef2f
LA		 4026
4027 return ret;
4028}
4029
20d695a9 4030int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 4031{
20d695a9 4032 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 4033 int ret;
4034
2fa45344 4035 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 4036
b16c0e20
PB		 4037 /* must be before kvm_put_nested_state so that EFER.SVME is set */
4038 ret = kvm_put_sregs(x86_cpu);
4039 if (ret < 0) {
4040 return ret;
4041 }
4042
48e1a45c 4043 if (level >= KVM_PUT_RESET_STATE) {
bec7156a
JK		 4044 ret = kvm_put_nested_state(x86_cpu);
4045 if (ret < 0) {
4046 return ret;
4047 }
4048
6bdf863d
JK		 4049 ret = kvm_put_msr_feature_control(x86_cpu);
4050 if (ret < 0) {
4051 return ret;
4052 }
4053 }
4054
36f96c4b
HZ		 4055 if (level == KVM_PUT_FULL_STATE) {
4056 /* We don't check for kvm_arch_set_tsc_khz() errors here,
4057 * because TSC frequency mismatch shouldn't abort migration,
4058 * unless the user explicitly asked for a more strict TSC
4059 * setting (e.g. using an explicit "tsc-freq" option).
4060 */
4061 kvm_arch_set_tsc_khz(cpu);
4062 }
4063
1bc22652 4064 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 4065 if (ret < 0) {
05330448 4066 return ret;
b9bec74b 4067 }
1bc22652 4068 ret = kvm_put_xsave(x86_cpu);
b9bec74b 4069 if (ret < 0) {
f1665b21 4070 return ret;
b9bec74b 4071 }
1bc22652 4072 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 4073 if (ret < 0) {
05330448 4074 return ret;
b9bec74b 4075 }
ab443475 4076 /* must be before kvm_put_msrs */
1bc22652 4077 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 4078 if (ret < 0) {
4079 return ret;
4080 }
1bc22652 4081 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 4082 if (ret < 0) {
05330448 4083 return ret;
b9bec74b 4084 }
4fadfa00
PH		 4085 ret = kvm_put_vcpu_events(x86_cpu, level);
4086 if (ret < 0) {
4087 return ret;
4088 }
ea643051 4089 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 4090 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 4091 if (ret < 0) {
680c1c6f
JK		 4092 return ret;
4093 }
ea643051 4094 }
7477cd38
MT		 4095
4096 ret = kvm_put_tscdeadline_msr(x86_cpu);
4097 if (ret < 0) {
4098 return ret;
4099 }
1bc22652 4100 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 4101 if (ret < 0) {
b0b1d690 4102 return ret;
b9bec74b 4103 }
b0b1d690 4104 /* must be last */
1bc22652 4105 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 4106 if (ret < 0) {
ff44f1a3 4107 return ret;
b9bec74b 4108 }
05330448
AL		 4109 return 0;
4110}
4111
20d695a9 4112int kvm_arch_get_registers(CPUState *cs)
05330448 4113{
20d695a9 4114 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 4115 int ret;
4116
20d695a9 4117 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 4118
4fadfa00 4119 ret = kvm_get_vcpu_events(cpu);
b9bec74b 4120 if (ret < 0) {
f4f1110e 4121 goto out;
b9bec74b 4122 }
4fadfa00
PH		 4123 /*
4124 * KVM_GET_MPSTATE can modify CS and RIP, call it before
4125 * KVM_GET_REGS and KVM_GET_SREGS.
4126 */
4127 ret = kvm_get_mp_state(cpu);
b9bec74b 4128 if (ret < 0) {
f4f1110e 4129 goto out;
b9bec74b 4130 }
4fadfa00 4131 ret = kvm_getput_regs(cpu, 0);
b9bec74b 4132 if (ret < 0) {
f4f1110e 4133 goto out;
b9bec74b 4134 }
4fadfa00 4135 ret = kvm_get_xsave(cpu);
b9bec74b 4136 if (ret < 0) {
f4f1110e 4137 goto out;
b9bec74b 4138 }
4fadfa00 4139 ret = kvm_get_xcrs(cpu);
b9bec74b 4140 if (ret < 0) {
f4f1110e 4141 goto out;
b9bec74b 4142 }
4fadfa00 4143 ret = kvm_get_sregs(cpu);
b9bec74b 4144 if (ret < 0) {
f4f1110e 4145 goto out;
b9bec74b 4146 }
4fadfa00 4147 ret = kvm_get_msrs(cpu);
680c1c6f 4148 if (ret < 0) {
f4f1110e 4149 goto out;
680c1c6f 4150 }
4fadfa00 4151 ret = kvm_get_apic(cpu);
b9bec74b 4152 if (ret < 0) {
f4f1110e 4153 goto out;
b9bec74b 4154 }
1bc22652 4155 ret = kvm_get_debugregs(cpu);
b9bec74b 4156 if (ret < 0) {
f4f1110e 4157 goto out;
b9bec74b 4158 }
ebbfef2f
LA		 4159 ret = kvm_get_nested_state(cpu);
4160 if (ret < 0) {
4161 goto out;
4162 }
f4f1110e
RH		 4163 ret = 0;
4164 out:
4165 cpu_sync_bndcs_hflags(&cpu->env);
4166 return ret;
05330448
AL		 4167}
4168
20d695a9 4169void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 4170{
20d695a9
AF		 4171 X86CPU *x86_cpu = X86_CPU(cpu);
4172 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 4173 int ret;
4174
276ce815 4175 /* Inject NMI */
fc12d72e
PB		 4176 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
4177 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
4178 qemu_mutex_lock_iothread();
4179 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4180 qemu_mutex_unlock_iothread();
4181 DPRINTF("injected NMI\n");
4182 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4183 if (ret < 0) {
4184 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4185 strerror(-ret));
4186 }
4187 }
4188 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4189 qemu_mutex_lock_iothread();
4190 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4191 qemu_mutex_unlock_iothread();
4192 DPRINTF("injected SMI\n");
4193 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4194 if (ret < 0) {
4195 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4196 strerror(-ret));
4197 }
ce377af3 4198 }
276ce815
LJ		 4199 }
4200
15eafc2e 4201 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 4202 qemu_mutex_lock_iothread();
4203 }
4204
e0723c45
PB		 4205 /* Force the VCPU out of its inner loop to process any INIT requests
4206 * or (for userspace APIC, but it is cheap to combine the checks here)
4207 * pending TPR access reports.
4208 */
4209 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 4210 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4211 !(env->hflags & HF_SMM_MASK)) {
4212 cpu->exit_request = 1;
4213 }
4214 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4215 cpu->exit_request = 1;
4216 }
e0723c45 4217 }
05330448 4218
15eafc2e 4219 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 4220 /* Try to inject an interrupt if the guest can accept it */
4221 if (run->ready_for_interrupt_injection &&
259186a7 4222 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 4223 (env->eflags & IF_MASK)) {
4224 int irq;
4225
259186a7 4226 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 4227 irq = cpu_get_pic_interrupt(env);
4228 if (irq >= 0) {
4229 struct kvm_interrupt intr;
4230
4231 intr.irq = irq;
db1669bc 4232 DPRINTF("injected interrupt %d\n", irq);
1bc22652 4233 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 4234 if (ret < 0) {
4235 fprintf(stderr,
4236 "KVM: injection failed, interrupt lost (%s)\n",
4237 strerror(-ret));
4238 }
db1669bc
JK		 4239 }
4240 }
05330448 4241
db1669bc
JK		 4242 /* If we have an interrupt but the guest is not ready to receive an
4243 * interrupt, request an interrupt window exit. This will
4244 * cause a return to userspace as soon as the guest is ready to
4245 * receive interrupts. */
259186a7 4246 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 4247 run->request_interrupt_window = 1;
4248 } else {
4249 run->request_interrupt_window = 0;
4250 }
4251
4252 DPRINTF("setting tpr\n");
02e51483 4253 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 4254
4255 qemu_mutex_unlock_iothread();
db1669bc 4256 }
05330448
AL		 4257}
4258
035d1ef2
CQ		 4259static void kvm_rate_limit_on_bus_lock(void)
4260{
4261 uint64_t delay_ns = ratelimit_calculate_delay(&bus_lock_ratelimit_ctrl, 1);
4262
4263 if (delay_ns) {
4264 g_usleep(delay_ns / SCALE_US);
4265 }
4266}
4267
4c663752 4268MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 4269{
20d695a9
AF		 4270 X86CPU *x86_cpu = X86_CPU(cpu);
4271 CPUX86State *env = &x86_cpu->env;
4272
fc12d72e
PB		 4273 if (run->flags & KVM_RUN_X86_SMM) {
4274 env->hflags |= HF_SMM_MASK;
4275 } else {
f5c052b9 4276 env->hflags &= ~HF_SMM_MASK;
fc12d72e 4277 }
b9bec74b 4278 if (run->if_flag) {
05330448 4279 env->eflags |= IF_MASK;
b9bec74b 4280 } else {
05330448 4281 env->eflags &= ~IF_MASK;
b9bec74b 4282 }
035d1ef2
CQ		 4283 if (run->flags & KVM_RUN_X86_BUS_LOCK) {
4284 kvm_rate_limit_on_bus_lock();
4285 }
4b8523ee
JK		 4286
4287 /* We need to protect the apic state against concurrent accesses from
4288 * different threads in case the userspace irqchip is used. */
4289 if (!kvm_irqchip_in_kernel()) {
4290 qemu_mutex_lock_iothread();
4291 }
02e51483
CF		 4292 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4293 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 4294 if (!kvm_irqchip_in_kernel()) {
4295 qemu_mutex_unlock_iothread();
4296 }
f794aa4a 4297 return cpu_get_mem_attrs(env);
05330448
AL		 4298}
4299
20d695a9 4300int kvm_arch_process_async_events(CPUState *cs)
0af691d7 4301{
20d695a9
AF		 4302 X86CPU *cpu = X86_CPU(cs);
4303 CPUX86State *env = &cpu->env;
232fc23b 4304
259186a7 4305 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 4306 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4307 assert(env->mcg_cap);
4308
259186a7 4309 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 4310
dd1750d7 4311 kvm_cpu_synchronize_state(cs);
ab443475 4312
fd13f23b 4313 if (env->exception_nr == EXCP08_DBLE) {
ab443475 4314 /* this means triple fault */
cf83f140 4315 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 4316 cs->exit_request = 1;
ab443475
JK		 4317 return 0;
4318 }
fd13f23b 4319 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 4320 env->has_error_code = 0;
4321
259186a7 4322 cs->halted = 0;
ab443475
JK		 4323 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4324 env->mp_state = KVM_MP_STATE_RUNNABLE;
4325 }
4326 }
4327
fc12d72e
PB		 4328 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4329 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 4330 kvm_cpu_synchronize_state(cs);
4331 do_cpu_init(cpu);
4332 }
4333
db1669bc
JK		 4334 if (kvm_irqchip_in_kernel()) {
4335 return 0;
4336 }
4337
259186a7
AF		 4338 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4339 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 4340 apic_poll_irq(cpu->apic_state);
5d62c43a 4341 }
259186a7 4342 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 4343 (env->eflags & IF_MASK)) ||
259186a7
AF		 4344 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4345 cs->halted = 0;
6792a57b 4346 }
259186a7 4347 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 4348 kvm_cpu_synchronize_state(cs);
232fc23b 4349 do_cpu_sipi(cpu);
0af691d7 4350 }
259186a7
AF		 4351 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4352 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 4353 kvm_cpu_synchronize_state(cs);
02e51483 4354 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 4355 env->tpr_access_type);
4356 }
0af691d7 4357
259186a7 4358 return cs->halted;
0af691d7
MT		 4359}
4360
839b5630 4361static int kvm_handle_halt(X86CPU *cpu)
05330448 4362{
259186a7 4363 CPUState *cs = CPU(cpu);
839b5630
AF		 4364 CPUX86State *env = &cpu->env;
4365
259186a7 4366 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 4367 (env->eflags & IF_MASK)) &&
259186a7
AF		 4368 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4369 cs->halted = 1;
bb4ea393 4370 return EXCP_HLT;
05330448
AL		 4371 }
4372
bb4ea393 4373 return 0;
05330448
AL		 4374}
4375
f7575c96 4376static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 4377{
f7575c96
AF		 4378 CPUState *cs = CPU(cpu);
4379 struct kvm_run *run = cs->kvm_run;
d362e757 4380
02e51483 4381 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 4382 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4383 : TPR_ACCESS_READ);
4384 return 1;
4385}
4386
f17ec444 4387int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 4388{
38972938 4389 static const uint8_t int3 = 0xcc;
64bf3f4e 4390
f17ec444
AF		 4391 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4392 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 4393 return -EINVAL;
b9bec74b 4394 }
e22a25c9
AL		 4395 return 0;
4396}
4397
f17ec444 4398int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 4399{
4400 uint8_t int3;
4401
c6986f16
PB		 4402 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0)) {
4403 return -EINVAL;
4404 }
4405 if (int3 != 0xcc) {
4406 return 0;
4407 }
4408 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 4409 return -EINVAL;
b9bec74b 4410 }
e22a25c9
AL		 4411 return 0;
4412}
4413
4414static struct {
4415 target_ulong addr;
4416 int len;
4417 int type;
4418} hw_breakpoint[4];
4419
4420static int nb_hw_breakpoint;
4421
4422static int find_hw_breakpoint(target_ulong addr, int len, int type)
4423{
4424 int n;
4425
b9bec74b 4426 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 4427 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 4428 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 4429 return n;
b9bec74b
JK		 4430 }
4431 }
e22a25c9
AL		 4432 return -1;
4433}
4434
4435int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4436 target_ulong len, int type)
4437{
4438 switch (type) {
4439 case GDB_BREAKPOINT_HW:
4440 len = 1;
4441 break;
4442 case GDB_WATCHPOINT_WRITE:
4443 case GDB_WATCHPOINT_ACCESS:
4444 switch (len) {
4445 case 1:
4446 break;
4447 case 2:
4448 case 4:
4449 case 8:
b9bec74b 4450 if (addr & (len - 1)) {
e22a25c9 4451 return -EINVAL;
b9bec74b 4452 }
e22a25c9
AL		 4453 break;
4454 default:
4455 return -EINVAL;
4456 }
4457 break;
4458 default:
4459 return -ENOSYS;
4460 }
4461
b9bec74b 4462 if (nb_hw_breakpoint == 4) {
e22a25c9 4463 return -ENOBUFS;
b9bec74b
JK		 4464 }
4465 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 4466 return -EEXIST;
b9bec74b 4467 }
e22a25c9
AL		 4468 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4469 hw_breakpoint[nb_hw_breakpoint].len = len;
4470 hw_breakpoint[nb_hw_breakpoint].type = type;
4471 nb_hw_breakpoint++;
4472
4473 return 0;
4474}
4475
4476int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4477 target_ulong len, int type)
4478{
4479 int n;
4480
4481 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 4482 if (n < 0) {
e22a25c9 4483 return -ENOENT;
b9bec74b 4484 }
e22a25c9
AL		 4485 nb_hw_breakpoint--;
4486 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4487
4488 return 0;
4489}
4490
4491void kvm_arch_remove_all_hw_breakpoints(void)
4492{
4493 nb_hw_breakpoint = 0;
4494}
4495
4496static CPUWatchpoint hw_watchpoint;
4497
a60f24b5 4498static int kvm_handle_debug(X86CPU *cpu,
48405526 4499 struct kvm_debug_exit_arch *arch_info)
e22a25c9 4500{
ed2803da 4501 CPUState *cs = CPU(cpu);
a60f24b5 4502 CPUX86State *env = &cpu->env;
f2574737 4503 int ret = 0;
e22a25c9
AL		 4504 int n;
4505
37936ac7
LA		 4506 if (arch_info->exception == EXCP01_DB) {
4507 if (arch_info->dr6 & DR6_BS) {
ed2803da 4508 if (cs->singlestep_enabled) {
f2574737 4509 ret = EXCP_DEBUG;
b9bec74b 4510 }
e22a25c9 4511 } else {
b9bec74b
JK		 4512 for (n = 0; n < 4; n++) {
4513 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 4514 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4515 case 0x0:
f2574737 4516 ret = EXCP_DEBUG;
e22a25c9
AL		 4517 break;
4518 case 0x1:
f2574737 4519 ret = EXCP_DEBUG;
ff4700b0 4520 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4521 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4522 hw_watchpoint.flags = BP_MEM_WRITE;
4523 break;
4524 case 0x3:
f2574737 4525 ret = EXCP_DEBUG;
ff4700b0 4526 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4527 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4528 hw_watchpoint.flags = BP_MEM_ACCESS;
4529 break;
4530 }
b9bec74b
JK		 4531 }
4532 }
e22a25c9 4533 }
ff4700b0 4534 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 4535 ret = EXCP_DEBUG;
b9bec74b 4536 }
f2574737 4537 if (ret == 0) {
ff4700b0 4538 cpu_synchronize_state(cs);
fd13f23b 4539 assert(env->exception_nr == -1);
b0b1d690 4540
f2574737 4541 /* pass to guest */
fd13f23b
LA		 4542 kvm_queue_exception(env, arch_info->exception,
4543 arch_info->exception == EXCP01_DB,
4544 arch_info->dr6);
48405526 4545 env->has_error_code = 0;
b0b1d690 4546 }
e22a25c9 4547
f2574737 4548 return ret;
e22a25c9
AL		 4549}
4550
20d695a9 4551void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 4552{
4553 const uint8_t type_code[] = {
4554 [GDB_BREAKPOINT_HW] = 0x0,
4555 [GDB_WATCHPOINT_WRITE] = 0x1,
4556 [GDB_WATCHPOINT_ACCESS] = 0x3
4557 };
4558 const uint8_t len_code[] = {
4559 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4560 };
4561 int n;
4562
a60f24b5 4563 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 4564 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 4565 }
e22a25c9
AL		 4566 if (nb_hw_breakpoint > 0) {
4567 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4568 dbg->arch.debugreg[7] = 0x0600;
4569 for (n = 0; n < nb_hw_breakpoint; n++) {
4570 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4571 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4572 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 4573 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 4574 }
4575 }
4576}
4513d923 4577
2a4dac83
JK		 4578static bool host_supports_vmx(void)
4579{
4580 uint32_t ecx, unused;
4581
4582 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4583 return ecx & CPUID_EXT_VMX;
4584}
4585
4586#define VMX_INVALID_GUEST_STATE 0x80000021
4587
20d695a9 4588int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 4589{
20d695a9 4590 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 4591 uint64_t code;
4592 int ret;
4593
4594 switch (run->exit_reason) {
4595 case KVM_EXIT_HLT:
4596 DPRINTF("handle_hlt\n");
4b8523ee 4597 qemu_mutex_lock_iothread();
839b5630 4598 ret = kvm_handle_halt(cpu);
4b8523ee 4599 qemu_mutex_unlock_iothread();
2a4dac83
JK		 4600 break;
4601 case KVM_EXIT_SET_TPR:
4602 ret = 0;
4603 break;
d362e757 4604 case KVM_EXIT_TPR_ACCESS:
4b8523ee 4605 qemu_mutex_lock_iothread();
f7575c96 4606 ret = kvm_handle_tpr_access(cpu);
4b8523ee 4607 qemu_mutex_unlock_iothread();
d362e757 4608 break;
2a4dac83
JK		 4609 case KVM_EXIT_FAIL_ENTRY:
4610 code = run->fail_entry.hardware_entry_failure_reason;
4611 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4612 code);
4613 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4614 fprintf(stderr,
12619721 4615 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 4616 "unrestricted mode\n"
4617 "support, the failure can be most likely due to the guest "
4618 "entering an invalid\n"
4619 "state for Intel VT. For example, the guest maybe running "
4620 "in big real mode\n"
4621 "which is not supported on less recent Intel processors."
4622 "\n\n");
4623 }
4624 ret = -1;
4625 break;
4626 case KVM_EXIT_EXCEPTION:
4627 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4628 run->ex.exception, run->ex.error_code);
4629 ret = -1;
4630 break;
f2574737
JK		 4631 case KVM_EXIT_DEBUG:
4632 DPRINTF("kvm_exit_debug\n");
4b8523ee 4633 qemu_mutex_lock_iothread();
a60f24b5 4634 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 4635 qemu_mutex_unlock_iothread();
f2574737 4636 break;
50efe82c
AS		 4637 case KVM_EXIT_HYPERV:
4638 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4639 break;
15eafc2e
PB		 4640 case KVM_EXIT_IOAPIC_EOI:
4641 ioapic_eoi_broadcast(run->eoi.vector);
4642 ret = 0;
4643 break;
035d1ef2
CQ		 4644 case KVM_EXIT_X86_BUS_LOCK:
4645 /* already handled in kvm_arch_post_run */
4646 ret = 0;
4647 break;
2a4dac83
JK		 4648 default:
4649 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4650 ret = -1;
4651 break;
4652 }
4653
4654 return ret;
4655}
4656
20d695a9 4657bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4658{
20d695a9
AF		 4659 X86CPU *cpu = X86_CPU(cs);
4660 CPUX86State *env = &cpu->env;
4661
dd1750d7 4662 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4663 return !(env->cr[0] & CR0_PE_MASK) ||
4664 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4665}
84b058d7
JK		 4666
4667void kvm_arch_init_irq_routing(KVMState *s)
4668{
cc7e0ddf 4669 /* We know at this point that we're using the in-kernel
614e41bc 4670 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4671 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4672 */
614e41bc 4673 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4674 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4675
4676 if (kvm_irqchip_is_split()) {
4677 int i;
4678
4679 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4680 MSI routes for signaling interrupts to the local apics. */
4681 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4682 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4683 error_report("Could not enable split IRQ mode.");
4684 exit(1);
4685 }
4686 }
4687 }
4688}
4689
4376c40d 4690int kvm_arch_irqchip_create(KVMState *s)
15eafc2e
PB		 4691{
4692 int ret;
4376c40d 4693 if (kvm_kernel_irqchip_split()) {
15eafc2e
PB		 4694 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4695 if (ret) {
df3c286c 4696 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4697 strerror(-ret));
4698 exit(1);
4699 } else {
4700 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4701 kvm_split_irqchip = true;
4702 return 1;
4703 }
4704 } else {
4705 return 0;
4706 }
84b058d7 4707}
b139bd30 4708
c1bb5418
DW		 4709uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address)
4710{
4711 CPUX86State *env;
4712 uint64_t ext_id;
4713
4714 if (!first_cpu) {
4715 return address;
4716 }
4717 env = &X86_CPU(first_cpu)->env;
4718 if (!(env->features[FEAT_KVM] & (1 << KVM_FEATURE_MSI_EXT_DEST_ID))) {
4719 return address;
4720 }
4721
4722 /*
4723 * If the remappable format bit is set, or the upper bits are
4724 * already set in address_hi, or the low extended bits aren't
4725 * there anyway, do nothing.
4726 */
4727 ext_id = address & (0xff << MSI_ADDR_DEST_IDX_SHIFT);
4728 if (!ext_id || (ext_id & (1 << MSI_ADDR_DEST_IDX_SHIFT)) || (address >> 32)) {
4729 return address;
4730 }
4731
4732 address &= ~ext_id;
4733 address |= ext_id << 35;
4734 return address;
4735}
4736
9e03a040 4737int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4738 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4739{
8b5ed7df
PX		 4740 X86IOMMUState *iommu = x86_iommu_get_default();
4741
4742 if (iommu) {
30c60f77 4743 X86IOMMUClass *class = X86_IOMMU_DEVICE_GET_CLASS(iommu);
8b5ed7df 4744
c1bb5418
DW		 4745 if (class->int_remap) {
4746 int ret;
4747 MSIMessage src, dst;
0ea1472d 4748
c1bb5418
DW		 4749 src.address = route->u.msi.address_hi;
4750 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4751 src.address |= route->u.msi.address_lo;
4752 src.data = route->u.msi.data;
8b5ed7df 4753
c1bb5418
DW		 4754 ret = class->int_remap(iommu, &src, &dst, dev ? \
4755 pci_requester_id(dev) : \
4756 X86_IOMMU_SID_INVALID);
4757 if (ret) {
4758 trace_kvm_x86_fixup_msi_error(route->gsi);
4759 return 1;
4760 }
4761
4762 /*
4763 * Handled untranslated compatibilty format interrupt with
4764 * extended destination ID in the low bits 11-5. */
4765 dst.address = kvm_swizzle_msi_ext_dest_id(dst.address);
8b5ed7df 4766
c1bb5418
DW		 4767 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4768 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4769 route->u.msi.data = dst.data;
4770 return 0;
4771 }
8b5ed7df
PX		 4772 }
4773
c1bb5418
DW		 4774 address = kvm_swizzle_msi_ext_dest_id(address);
4775 route->u.msi.address_hi = address >> VTD_MSI_ADDR_HI_SHIFT;
4776 route->u.msi.address_lo = address & VTD_MSI_ADDR_LO_MASK;
9e03a040
FB		 4777 return 0;
4778}
1850b6b7 4779
38d87493
PX		 4780typedef struct MSIRouteEntry MSIRouteEntry;
4781
4782struct MSIRouteEntry {
4783 PCIDevice *dev; /* Device pointer */
4784 int vector; /* MSI/MSIX vector index */
4785 int virq; /* Virtual IRQ index */
4786 QLIST_ENTRY(MSIRouteEntry) list;
4787};
4788
4789/* List of used GSI routes */
4790static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4791 QLIST_HEAD_INITIALIZER(msi_route_list);
4792
e1d4fb2d
PX		 4793static void kvm_update_msi_routes_all(void *private, bool global,
4794 uint32_t index, uint32_t mask)
4795{
a56de056 4796 int cnt = 0, vector;
e1d4fb2d
PX		 4797 MSIRouteEntry *entry;
4798 MSIMessage msg;
fd563564
PX		 4799 PCIDevice *dev;
4800
e1d4fb2d
PX		 4801 /* TODO: explicit route update */
4802 QLIST_FOREACH(entry, &msi_route_list, list) {
4803 cnt++;
a56de056 4804 vector = entry->vector;
fd563564 4805 dev = entry->dev;
a56de056
PX		 4806 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4807 msg = msix_get_message(dev, vector);
4808 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4809 msg = msi_get_message(dev, vector);
4810 } else {
4811 /*
4812 * Either MSI/MSIX is disabled for the device, or the
4813 * specific message was masked out. Skip this one.
4814 */
fd563564
PX		 4815 continue;
4816 }
fd563564 4817 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4818 }
3f1fea0f 4819 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4820 trace_kvm_x86_update_msi_routes(cnt);
4821}
4822
38d87493
PX		 4823int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4824 int vector, PCIDevice *dev)
4825{
e1d4fb2d 4826 static bool notify_list_inited = false;
38d87493
PX		 4827 MSIRouteEntry *entry;
4828
4829 if (!dev) {
4830 /* These are (possibly) IOAPIC routes only used for split
4831 * kernel irqchip mode, while what we are housekeeping are
4832 * PCI devices only. */
4833 return 0;
4834 }
4835
4836 entry = g_new0(MSIRouteEntry, 1);
4837 entry->dev = dev;
4838 entry->vector = vector;
4839 entry->virq = route->gsi;
4840 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4841
4842 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4843
4844 if (!notify_list_inited) {
4845 /* For the first time we do add route, add ourselves into
4846 * IOMMU's IEC notify list if needed. */
4847 X86IOMMUState *iommu = x86_iommu_get_default();
4848 if (iommu) {
4849 x86_iommu_iec_register_notifier(iommu,
4850 kvm_update_msi_routes_all,
4851 NULL);
4852 }
4853 notify_list_inited = true;
4854 }
38d87493
PX		 4855 return 0;
4856}
4857
4858int kvm_arch_release_virq_post(int virq)
4859{
4860 MSIRouteEntry *entry, *next;
4861 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4862 if (entry->virq == virq) {
4863 trace_kvm_x86_remove_msi_route(virq);
4864 QLIST_REMOVE(entry, list);
01960e6d 4865 g_free(entry);
38d87493
PX		 4866 break;
4867 }
4868 }
9e03a040
FB		 4869 return 0;
4870}
1850b6b7
EA		 4871
4872int kvm_arch_msi_data_to_gsi(uint32_t data)
4873{
4874 abort();
4875}
e1e43813
PB		 4876
4877bool kvm_has_waitpkg(void)
4878{
4879 return has_msr_umwait;
4880}
92a5199b
TL		 4881
4882bool kvm_arch_cpu_check_are_resettable(void)
4883{
4884 return !sev_es_enabled();
4885}
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