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Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180626' into...
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
a2cb15b0 43#include "hw/pci/pci.h"
15eafc2e 44#include "hw/pci/msi.h"
fd563564 45#include "hw/pci/msix.h"
795c40b8 46#include "migration/blocker.h"
4c663752 47#include "exec/memattrs.h"
8b5ed7df 48#include "trace.h"
05330448
AL		 49
50//#define DEBUG_KVM
51
52#ifdef DEBUG_KVM
8c0d577e 53#define DPRINTF(fmt, ...) \
05330448
AL		 54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55#else
8c0d577e 56#define DPRINTF(fmt, ...) \
05330448
AL		 57 do { } while (0)
58#endif
59
1a03675d
GC		 60#define MSR_KVM_WALL_CLOCK 0x11
61#define MSR_KVM_SYSTEM_TIME 0x12
62
d1138251
EH		 63/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65#define MSR_BUF_SIZE 4096
d71b62a1 66
94a8d39a
JK		 67const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72};
25d2e361 73
c3a3a7d3
JK		 74static bool has_msr_star;
75static bool has_msr_hsave_pa;
c9b8f6b6 76static bool has_msr_tsc_aux;
f28558d3 77static bool has_msr_tsc_adjust;
aa82ba54 78static bool has_msr_tsc_deadline;
df67696e 79static bool has_msr_feature_control;
21e87c46 80static bool has_msr_misc_enable;
fc12d72e 81static bool has_msr_smbase;
79e9ebeb 82static bool has_msr_bndcfgs;
25d2e361 83static int lm_capable_kernel;
7bc3d711 84static bool has_msr_hv_hypercall;
f2a53c9e 85static bool has_msr_hv_crash;
744b8a94 86static bool has_msr_hv_reset;
8c145d7c 87static bool has_msr_hv_vpindex;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
b827df58 97
0b368a10
JD		 98static uint32_t has_architectural_pmu_version;
99static uint32_t num_architectural_pmu_gp_counters;
100static uint32_t num_architectural_pmu_fixed_counters;
0d894367 101
28143b40
TH		 102static int has_xsave;
103static int has_xcrs;
104static int has_pit_state2;
105
87f8b626
AR		 106static bool has_msr_mcg_ext_ctl;
107
494e95e9
CP		 108static struct kvm_cpuid2 *cpuid_cache;
109
28143b40
TH		 110int kvm_has_pit_state2(void)
111{
112 return has_pit_state2;
113}
114
355023f2
PB		 115bool kvm_has_smm(void)
116{
117 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
118}
119
6053a86f
MT		 120bool kvm_has_adjust_clock_stable(void)
121{
122 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
123
124 return (ret == KVM_CLOCK_TSC_STABLE);
125}
126
1d31f66b
PM		 127bool kvm_allows_irq0_override(void)
128{
129 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
130}
131
fb506e70
RK		 132static bool kvm_x2apic_api_set_flags(uint64_t flags)
133{
134 KVMState *s = KVM_STATE(current_machine->accelerator);
135
136 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
137}
138
e391c009 139#define MEMORIZE(fn, _result) \
2a138ec3 140 ({ \
2a138ec3
RK		 141 static bool _memorized; \
142 \
143 if (_memorized) { \
144 return _result; \
145 } \
146 _memorized = true; \
147 _result = fn; \
148 })
149
e391c009
IM		 150static bool has_x2apic_api;
151
152bool kvm_has_x2apic_api(void)
153{
154 return has_x2apic_api;
155}
156
fb506e70
RK		 157bool kvm_enable_x2apic(void)
158{
2a138ec3
RK		 159 return MEMORIZE(
160 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 161 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
162 has_x2apic_api);
fb506e70
RK		 163}
164
0fd7e098
LL		 165static int kvm_get_tsc(CPUState *cs)
166{
167 X86CPU *cpu = X86_CPU(cs);
168 CPUX86State *env = &cpu->env;
169 struct {
170 struct kvm_msrs info;
171 struct kvm_msr_entry entries[1];
172 } msr_data;
173 int ret;
174
175 if (env->tsc_valid) {
176 return 0;
177 }
178
179 msr_data.info.nmsrs = 1;
180 msr_data.entries[0].index = MSR_IA32_TSC;
181 env->tsc_valid = !runstate_is_running();
182
183 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
184 if (ret < 0) {
185 return ret;
186 }
187
48e1a45c 188 assert(ret == 1);
0fd7e098
LL		 189 env->tsc = msr_data.entries[0].data;
190 return 0;
191}
192
14e6fe12 193static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 194{
0fd7e098
LL		 195 kvm_get_tsc(cpu);
196}
197
198void kvm_synchronize_all_tsc(void)
199{
200 CPUState *cpu;
201
202 if (kvm_enabled()) {
203 CPU_FOREACH(cpu) {
14e6fe12 204 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 205 }
206 }
207}
208
b827df58
AK		 209static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
210{
211 struct kvm_cpuid2 *cpuid;
212 int r, size;
213
214 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 215 cpuid = g_malloc0(size);
b827df58
AK		 216 cpuid->nent = max;
217 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 218 if (r == 0 && cpuid->nent >= max) {
219 r = -E2BIG;
220 }
b827df58
AK		 221 if (r < 0) {
222 if (r == -E2BIG) {
7267c094 223 g_free(cpuid);
b827df58
AK		 224 return NULL;
225 } else {
226 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
227 strerror(-r));
228 exit(1);
229 }
230 }
231 return cpuid;
232}
233
dd87f8a6
EH		 234/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
235 * for all entries.
236 */
237static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
238{
239 struct kvm_cpuid2 *cpuid;
240 int max = 1;
494e95e9
CP		 241
242 if (cpuid_cache != NULL) {
243 return cpuid_cache;
244 }
dd87f8a6
EH		 245 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
246 max *= 2;
247 }
494e95e9 248 cpuid_cache = cpuid;
dd87f8a6
EH		 249 return cpuid;
250}
251
a443bc34 252static const struct kvm_para_features {
0c31b744
GC		 253 int cap;
254 int feature;
255} para_features[] = {
256 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
257 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
258 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 259 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 260};
261
ba9bc59e 262static int get_para_features(KVMState *s)
0c31b744
GC		 263{
264 int i, features = 0;
265
8e03c100 266 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 267 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 268 features |= (1 << para_features[i].feature);
269 }
270 }
271
272 return features;
273}
0c31b744 274
40e80ee4
EH		 275static bool host_tsx_blacklisted(void)
276{
277 int family, model, stepping;\
278 char vendor[CPUID_VENDOR_SZ + 1];
279
280 host_vendor_fms(vendor, &family, &model, &stepping);
281
282 /* Check if we are running on a Haswell host known to have broken TSX */
283 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
284 (family == 6) &&
285 ((model == 63 && stepping < 4) ||
286 model == 60 || model == 69 || model == 70);
287}
0c31b744 288
829ae2f9
EH		 289/* Returns the value for a specific register on the cpuid entry
290 */
291static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
292{
293 uint32_t ret = 0;
294 switch (reg) {
295 case R_EAX:
296 ret = entry->eax;
297 break;
298 case R_EBX:
299 ret = entry->ebx;
300 break;
301 case R_ECX:
302 ret = entry->ecx;
303 break;
304 case R_EDX:
305 ret = entry->edx;
306 break;
307 }
308 return ret;
309}
310
4fb73f1d
EH		 311/* Find matching entry for function/index on kvm_cpuid2 struct
312 */
313static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
314 uint32_t function,
315 uint32_t index)
316{
317 int i;
318 for (i = 0; i < cpuid->nent; ++i) {
319 if (cpuid->entries[i].function == function &&
320 cpuid->entries[i].index == index) {
321 return &cpuid->entries[i];
322 }
323 }
324 /* not found: */
325 return NULL;
326}
327
ba9bc59e 328uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 329 uint32_t index, int reg)
b827df58
AK		 330{
331 struct kvm_cpuid2 *cpuid;
b827df58
AK		 332 uint32_t ret = 0;
333 uint32_t cpuid_1_edx;
8c723b79 334 bool found = false;
b827df58 335
dd87f8a6 336 cpuid = get_supported_cpuid(s);
b827df58 337
4fb73f1d
EH		 338 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
339 if (entry) {
340 found = true;
341 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 342 }
343
7b46e5ce
EH		 344 /* Fixups for the data returned by KVM, below */
345
c2acb022
EH		 346 if (function == 1 && reg == R_EDX) {
347 /* KVM before 2.6.30 misreports the following features */
348 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 349 } else if (function == 1 && reg == R_ECX) {
350 /* We can set the hypervisor flag, even if KVM does not return it on
351 * GET_SUPPORTED_CPUID
352 */
353 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 354 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
355 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
356 * and the irqchip is in the kernel.
357 */
358 if (kvm_irqchip_in_kernel() &&
359 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
360 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
361 }
41e5e76d
EH		 362
363 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
364 * without the in-kernel irqchip
365 */
366 if (!kvm_irqchip_in_kernel()) {
367 ret &= ~CPUID_EXT_X2APIC;
b827df58 368 }
28b8e4d0
JK		 369 } else if (function == 6 && reg == R_EAX) {
370 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 371 } else if (function == 7 && index == 0 && reg == R_EBX) {
372 if (host_tsx_blacklisted()) {
373 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
374 }
f98bbd83
BM		 375 } else if (function == 0x80000001 && reg == R_ECX) {
376 /*
377 * It's safe to enable TOPOEXT even if it's not returned by
378 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
379 * us to keep CPU models including TOPOEXT runnable on older kernels.
380 */
381 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 382 } else if (function == 0x80000001 && reg == R_EDX) {
383 /* On Intel, kvm returns cpuid according to the Intel spec,
384 * so add missing bits according to the AMD spec:
385 */
386 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
387 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 388 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
389 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
390 * be enabled without the in-kernel irqchip
391 */
392 if (!kvm_irqchip_in_kernel()) {
393 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
394 }
be777326 395 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 396 ret |= 1U << KVM_HINTS_REALTIME;
be777326 397 found = 1;
b827df58
AK		 398 }
399
0c31b744 400 /* fallback for older kernels */
8c723b79 401 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 402 ret = get_para_features(s);
b9bec74b 403 }
0c31b744
GC		 404
405 return ret;
bb0300dc 406}
bb0300dc 407
3c85e74f
HY		 408typedef struct HWPoisonPage {
409 ram_addr_t ram_addr;
410 QLIST_ENTRY(HWPoisonPage) list;
411} HWPoisonPage;
412
413static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
414 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
415
416static void kvm_unpoison_all(void *param)
417{
418 HWPoisonPage *page, *next_page;
419
420 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
421 QLIST_REMOVE(page, list);
422 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 423 g_free(page);
3c85e74f
HY		 424 }
425}
426
3c85e74f
HY		 427static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
428{
429 HWPoisonPage *page;
430
431 QLIST_FOREACH(page, &hwpoison_page_list, list) {
432 if (page->ram_addr == ram_addr) {
433 return;
434 }
435 }
ab3ad07f 436 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 437 page->ram_addr = ram_addr;
438 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
439}
440
e7701825
MT		 441static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
442 int *max_banks)
443{
444 int r;
445
14a09518 446 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 447 if (r > 0) {
448 *max_banks = r;
449 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
450 }
451 return -ENOSYS;
452}
453
bee615d4 454static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 455{
87f8b626 456 CPUState *cs = CPU(cpu);
bee615d4 457 CPUX86State *env = &cpu->env;
c34d440a
JK		 458 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
459 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
460 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 461 int flags = 0;
e7701825 462
c34d440a
JK		 463 if (code == BUS_MCEERR_AR) {
464 status |= MCI_STATUS_AR | 0x134;
465 mcg_status |= MCG_STATUS_EIPV;
466 } else {
467 status |= 0xc0;
468 mcg_status |= MCG_STATUS_RIPV;
419fb20a 469 }
87f8b626
AR		 470
471 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
472 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
473 * guest kernel back into env->mcg_ext_ctl.
474 */
475 cpu_synchronize_state(cs);
476 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
477 mcg_status |= MCG_STATUS_LMCE;
478 flags = 0;
479 }
480
8c5cf3b6 481 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 482 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 483}
419fb20a
JK		 484
485static void hardware_memory_error(void)
486{
487 fprintf(stderr, "Hardware memory error!\n");
488 exit(1);
489}
490
2ae41db2 491void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 492{
20d695a9
AF		 493 X86CPU *cpu = X86_CPU(c);
494 CPUX86State *env = &cpu->env;
419fb20a 495 ram_addr_t ram_addr;
a8170e5e 496 hwaddr paddr;
419fb20a 497
4d39892c
PB		 498 /* If we get an action required MCE, it has been injected by KVM
499 * while the VM was running. An action optional MCE instead should
500 * be coming from the main thread, which qemu_init_sigbus identifies
501 * as the "early kill" thread.
502 */
a16fc07e 503 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 504
20e0ff59 505 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 506 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 507 if (ram_addr != RAM_ADDR_INVALID &&
508 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
509 kvm_hwpoison_page_add(ram_addr);
510 kvm_mce_inject(cpu, paddr, code);
2ae41db2 511 return;
419fb20a 512 }
20e0ff59
PB		 513
514 fprintf(stderr, "Hardware memory error for memory used by "
515 "QEMU itself instead of guest system!\n");
419fb20a 516 }
20e0ff59
PB		 517
518 if (code == BUS_MCEERR_AR) {
519 hardware_memory_error();
520 }
521
522 /* Hope we are lucky for AO MCE */
419fb20a
JK		 523}
524
1bc22652 525static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 526{
1bc22652
AF		 527 CPUX86State *env = &cpu->env;
528
ab443475
JK		 529 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
530 unsigned int bank, bank_num = env->mcg_cap & 0xff;
531 struct kvm_x86_mce mce;
532
533 env->exception_injected = -1;
534
535 /*
536 * There must be at least one bank in use if an MCE is pending.
537 * Find it and use its values for the event injection.
538 */
539 for (bank = 0; bank < bank_num; bank++) {
540 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
541 break;
542 }
543 }
544 assert(bank < bank_num);
545
546 mce.bank = bank;
547 mce.status = env->mce_banks[bank * 4 + 1];
548 mce.mcg_status = env->mcg_status;
549 mce.addr = env->mce_banks[bank * 4 + 2];
550 mce.misc = env->mce_banks[bank * 4 + 3];
551
1bc22652 552 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 553 }
ab443475
JK		 554 return 0;
555}
556
1dfb4dd9 557static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 558{
317ac620 559 CPUX86State *env = opaque;
b8cc45d6
GC		 560
561 if (running) {
562 env->tsc_valid = false;
563 }
564}
565
83b17af5 566unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 567{
83b17af5 568 X86CPU *cpu = X86_CPU(cs);
7e72a45c 569 return cpu->apic_id;
b164e48e
EH		 570}
571
92067bf4
IM		 572#ifndef KVM_CPUID_SIGNATURE_NEXT
573#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
574#endif
575
576static bool hyperv_hypercall_available(X86CPU *cpu)
577{
578 return cpu->hyperv_vapic ||
579 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
580}
581
582static bool hyperv_enabled(X86CPU *cpu)
583{
7bc3d711
PB		 584 CPUState *cs = CPU(cpu);
585 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
586 (hyperv_hypercall_available(cpu) ||
48a5f3bc 587 cpu->hyperv_time ||
f2a53c9e 588 cpu->hyperv_relaxed_timing ||
744b8a94 589 cpu->hyperv_crash ||
8c145d7c 590 cpu->hyperv_reset ||
46eb8f98 591 cpu->hyperv_vpindex ||
866eea9a 592 cpu->hyperv_runtime ||
ff99aa64 593 cpu->hyperv_synic ||
ba6a4fd9
VK		 594 cpu->hyperv_stimer ||
595 cpu->hyperv_reenlightenment);
92067bf4
IM		 596}
597
5031283d
HZ		 598static int kvm_arch_set_tsc_khz(CPUState *cs)
599{
600 X86CPU *cpu = X86_CPU(cs);
601 CPUX86State *env = &cpu->env;
602 int r;
603
604 if (!env->tsc_khz) {
605 return 0;
606 }
607
608 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
609 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
610 -ENOTSUP;
611 if (r < 0) {
612 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
613 * TSC frequency doesn't match the one we want.
614 */
615 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
616 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
617 -ENOTSUP;
618 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 619 warn_report("TSC frequency mismatch between "
620 "VM (%" PRId64 " kHz) and host (%d kHz), "
621 "and TSC scaling unavailable",
622 env->tsc_khz, cur_freq);
5031283d
HZ		 623 return r;
624 }
625 }
626
627 return 0;
628}
629
4bb95b82
LP		 630static bool tsc_is_stable_and_known(CPUX86State *env)
631{
632 if (!env->tsc_khz) {
633 return false;
634 }
635 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
636 || env->user_tsc_khz;
637}
638
c35bd19a
EY		 639static int hyperv_handle_properties(CPUState *cs)
640{
641 X86CPU *cpu = X86_CPU(cs);
642 CPUX86State *env = &cpu->env;
643
644 if (cpu->hyperv_relaxed_timing) {
5e953812 645 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 646 }
647 if (cpu->hyperv_vapic) {
5e953812
RK		 648 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
649 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 650 }
3ddcd2ed 651 if (cpu->hyperv_time) {
1221f150
RK		 652 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
653 fprintf(stderr, "Hyper-V clocksources "
654 "(requested by 'hv-time' cpu flag) "
655 "are not supported by kernel\n");
656 return -ENOSYS;
657 }
5e953812
RK		 658 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
659 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
660 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
9445597b
RK		 661 }
662 if (cpu->hyperv_frequencies) {
663 if (!has_msr_hv_frequencies) {
664 fprintf(stderr, "Hyper-V frequency MSRs "
665 "(requested by 'hv-frequencies' cpu flag) "
666 "are not supported by kernel\n");
667 return -ENOSYS;
d72bc7f6 668 }
9445597b
RK		 669 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
670 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 671 }
1221f150
RK		 672 if (cpu->hyperv_crash) {
673 if (!has_msr_hv_crash) {
674 fprintf(stderr, "Hyper-V crash MSRs "
675 "(requested by 'hv-crash' cpu flag) "
676 "are not supported by kernel\n");
677 return -ENOSYS;
678 }
5e953812 679 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 680 }
ba6a4fd9
VK		 681 if (cpu->hyperv_reenlightenment) {
682 if (!has_msr_hv_reenlightenment) {
683 fprintf(stderr,
684 "Hyper-V Reenlightenment MSRs "
685 "(requested by 'hv-reenlightenment' cpu flag) "
686 "are not supported by kernel\n");
687 return -ENOSYS;
688 }
689 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
690 }
5e953812 691 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1221f150
RK		 692 if (cpu->hyperv_reset) {
693 if (!has_msr_hv_reset) {
694 fprintf(stderr, "Hyper-V reset MSR "
695 "(requested by 'hv-reset' cpu flag) "
696 "is not supported by kernel\n");
697 return -ENOSYS;
698 }
5e953812 699 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a 700 }
1221f150
RK		 701 if (cpu->hyperv_vpindex) {
702 if (!has_msr_hv_vpindex) {
703 fprintf(stderr, "Hyper-V VP_INDEX MSR "
704 "(requested by 'hv-vpindex' cpu flag) "
705 "is not supported by kernel\n");
706 return -ENOSYS;
707 }
5e953812 708 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a 709 }
1221f150
RK		 710 if (cpu->hyperv_runtime) {
711 if (!has_msr_hv_runtime) {
712 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
713 "(requested by 'hv-runtime' cpu flag) "
714 "is not supported by kernel\n");
715 return -ENOSYS;
716 }
5e953812 717 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 718 }
719 if (cpu->hyperv_synic) {
c35bd19a
EY		 720 if (!has_msr_hv_synic ||
721 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
722 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
723 return -ENOSYS;
724 }
725
5e953812 726 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a
EY		 727 }
728 if (cpu->hyperv_stimer) {
729 if (!has_msr_hv_stimer) {
730 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
731 return -ENOSYS;
732 }
5e953812 733 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a
EY		 734 }
735 return 0;
736}
737
68bfd0ad
MT		 738static Error *invtsc_mig_blocker;
739
f8bb0565 740#define KVM_MAX_CPUID_ENTRIES 100
0893d460 741
20d695a9 742int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 743{
744 struct {
486bd5a2 745 struct kvm_cpuid2 cpuid;
f8bb0565 746 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 747 } QEMU_PACKED cpuid_data;
20d695a9
AF		 748 X86CPU *cpu = X86_CPU(cs);
749 CPUX86State *env = &cpu->env;
486bd5a2 750 uint32_t limit, i, j, cpuid_i;
a33609ca 751 uint32_t unused;
bb0300dc 752 struct kvm_cpuid_entry2 *c;
bb0300dc 753 uint32_t signature[3];
234cc647 754 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 755 int r;
fe44dc91 756 Error *local_err = NULL;
05330448 757
ef4cbe14
SW		 758 memset(&cpuid_data, 0, sizeof(cpuid_data));
759
05330448
AL		 760 cpuid_i = 0;
761
ddb98b5a
LP		 762 r = kvm_arch_set_tsc_khz(cs);
763 if (r < 0) {
764 goto fail;
765 }
766
767 /* vcpu's TSC frequency is either specified by user, or following
768 * the value used by KVM if the former is not present. In the
769 * latter case, we query it from KVM and record in env->tsc_khz,
770 * so that vcpu's TSC frequency can be migrated later via this field.
771 */
772 if (!env->tsc_khz) {
773 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
774 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
775 -ENOTSUP;
776 if (r > 0) {
777 env->tsc_khz = r;
778 }
779 }
780
bb0300dc 781 /* Paravirtualization CPUIDs */
234cc647
PB		 782 if (hyperv_enabled(cpu)) {
783 c = &cpuid_data.entries[cpuid_i++];
5e953812 784 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 785 if (!cpu->hyperv_vendor_id) {
786 memcpy(signature, "Microsoft Hv", 12);
787 } else {
788 size_t len = strlen(cpu->hyperv_vendor_id);
789
790 if (len > 12) {
791 error_report("hv-vendor-id truncated to 12 characters");
792 len = 12;
793 }
794 memset(signature, 0, 12);
795 memcpy(signature, cpu->hyperv_vendor_id, len);
796 }
5e953812 797 c->eax = HV_CPUID_MIN;
234cc647
PB		 798 c->ebx = signature[0];
799 c->ecx = signature[1];
800 c->edx = signature[2];
0c31b744 801
234cc647 802 c = &cpuid_data.entries[cpuid_i++];
5e953812 803 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 804 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
805 c->eax = signature[0];
234cc647
PB		 806 c->ebx = 0;
807 c->ecx = 0;
808 c->edx = 0;
eab70139
VR		 809
810 c = &cpuid_data.entries[cpuid_i++];
5e953812 811 c->function = HV_CPUID_VERSION;
eab70139
VR		 812 c->eax = 0x00001bbc;
813 c->ebx = 0x00060001;
814
815 c = &cpuid_data.entries[cpuid_i++];
5e953812 816 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 817 r = hyperv_handle_properties(cs);
818 if (r) {
819 return r;
46eb8f98 820 }
c35bd19a
EY		 821 c->eax = env->features[FEAT_HYPERV_EAX];
822 c->ebx = env->features[FEAT_HYPERV_EBX];
823 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 824
eab70139 825 c = &cpuid_data.entries[cpuid_i++];
5e953812 826 c->function = HV_CPUID_ENLIGHTMENT_INFO;
92067bf4 827 if (cpu->hyperv_relaxed_timing) {
5e953812 828 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
eab70139 829 }
2d5aa872 830 if (cpu->hyperv_vapic) {
5e953812 831 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
eab70139 832 }
92067bf4 833 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 834
835 c = &cpuid_data.entries[cpuid_i++];
5e953812 836 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 837
838 c->eax = cpu->hv_max_vps;
eab70139
VR		 839 c->ebx = 0x40;
840
234cc647 841 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 842 has_msr_hv_hypercall = true;
eab70139
VR		 843 }
844
f522d2ac
AW		 845 if (cpu->expose_kvm) {
846 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
847 c = &cpuid_data.entries[cpuid_i++];
848 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 849 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 850 c->ebx = signature[0];
851 c->ecx = signature[1];
852 c->edx = signature[2];
234cc647 853
f522d2ac
AW		 854 c = &cpuid_data.entries[cpuid_i++];
855 c->function = KVM_CPUID_FEATURES | kvm_base;
856 c->eax = env->features[FEAT_KVM];
be777326 857 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 858 }
917367aa 859
a33609ca 860 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 861
862 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 863 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
864 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
865 abort();
866 }
bb0300dc 867 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 868
869 switch (i) {
a36b1029
AL		 870 case 2: {
871 /* Keep reading function 2 till all the input is received */
872 int times;
873
a36b1029 874 c->function = i;
a33609ca
AL		 875 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
876 KVM_CPUID_FLAG_STATE_READ_NEXT;
877 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
878 times = c->eax & 0xff;
a36b1029
AL		 879
880 for (j = 1; j < times; ++j) {
f8bb0565
IM		 881 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
882 fprintf(stderr, "cpuid_data is full, no space for "
883 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
884 abort();
885 }
a33609ca 886 c = &cpuid_data.entries[cpuid_i++];
a36b1029 887 c->function = i;
a33609ca
AL		 888 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
889 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 890 }
891 break;
892 }
486bd5a2
AL		 893 case 4:
894 case 0xb:
895 case 0xd:
896 for (j = 0; ; j++) {
31e8c696
AP		 897 if (i == 0xd && j == 64) {
898 break;
899 }
486bd5a2
AL		 900 c->function = i;
901 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
902 c->index = j;
a33609ca 903 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 904
b9bec74b 905 if (i == 4 && c->eax == 0) {
486bd5a2 906 break;
b9bec74b
JK		 907 }
908 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 909 break;
b9bec74b
JK		 910 }
911 if (i == 0xd && c->eax == 0) {
31e8c696 912 continue;
b9bec74b 913 }
f8bb0565
IM		 914 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
915 fprintf(stderr, "cpuid_data is full, no space for "
916 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
917 abort();
918 }
a33609ca 919 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 920 }
921 break;
e37a5c7f
CP		 922 case 0x14: {
923 uint32_t times;
924
925 c->function = i;
926 c->index = 0;
927 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
928 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
929 times = c->eax;
930
931 for (j = 1; j <= times; ++j) {
932 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
933 fprintf(stderr, "cpuid_data is full, no space for "
934 "cpuid(eax:0x14,ecx:0x%x)\n", j);
935 abort();
936 }
937 c = &cpuid_data.entries[cpuid_i++];
938 c->function = i;
939 c->index = j;
940 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
941 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
942 }
943 break;
944 }
486bd5a2 945 default:
486bd5a2 946 c->function = i;
a33609ca
AL		 947 c->flags = 0;
948 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 949 break;
950 }
05330448 951 }
0d894367
PB		 952
953 if (limit >= 0x0a) {
0b368a10 954 uint32_t eax, edx;
0d894367 955
0b368a10
JD		 956 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
957
958 has_architectural_pmu_version = eax & 0xff;
959 if (has_architectural_pmu_version > 0) {
960 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 961
962 /* Shouldn't be more than 32, since that's the number of bits
963 * available in EBX to tell us _which_ counters are available.
964 * Play it safe.
965 */
0b368a10
JD		 966 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
967 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
968 }
969
970 if (has_architectural_pmu_version > 1) {
971 num_architectural_pmu_fixed_counters = edx & 0x1f;
972
973 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
974 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
975 }
0d894367
PB		 976 }
977 }
978 }
979
a33609ca 980 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 981
982 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 983 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
984 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
985 abort();
986 }
bb0300dc 987 c = &cpuid_data.entries[cpuid_i++];
05330448 988
8f4202fb
BM		 989 switch (i) {
990 case 0x8000001d:
991 /* Query for all AMD cache information leaves */
992 for (j = 0; ; j++) {
993 c->function = i;
994 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
995 c->index = j;
996 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
997
998 if (c->eax == 0) {
999 break;
1000 }
1001 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1002 fprintf(stderr, "cpuid_data is full, no space for "
1003 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1004 abort();
1005 }
1006 c = &cpuid_data.entries[cpuid_i++];
1007 }
1008 break;
1009 default:
1010 c->function = i;
1011 c->flags = 0;
1012 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1013 break;
1014 }
05330448
AL		 1015 }
1016
b3baa152
BW		 1017 /* Call Centaur's CPUID instructions they are supported. */
1018 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1019 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1020
1021 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1022 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1023 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1024 abort();
1025 }
b3baa152
BW		 1026 c = &cpuid_data.entries[cpuid_i++];
1027
1028 c->function = i;
1029 c->flags = 0;
1030 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1031 }
1032 }
1033
05330448
AL		 1034 cpuid_data.cpuid.nent = cpuid_i;
1035
e7701825 1036 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1037 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1038 (CPUID_MCE | CPUID_MCA)
a60f24b5 1039 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1040 uint64_t mcg_cap, unsupported_caps;
e7701825 1041 int banks;
32a42024 1042 int ret;
e7701825 1043
a60f24b5 1044 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1045 if (ret < 0) {
1046 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1047 return ret;
e7701825 1048 }
75d49497 1049
2590f15b 1050 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1051 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1052 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1053 return -ENOTSUP;
75d49497 1054 }
49b69cbf 1055
5120901a
EH		 1056 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1057 if (unsupported_caps) {
87f8b626
AR		 1058 if (unsupported_caps & MCG_LMCE_P) {
1059 error_report("kvm: LMCE not supported");
1060 return -ENOTSUP;
1061 }
3dc6f869
AF		 1062 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1063 unsupported_caps);
5120901a
EH		 1064 }
1065
2590f15b
EH		 1066 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1067 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1068 if (ret < 0) {
1069 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1070 return ret;
1071 }
e7701825 1072 }
e7701825 1073
b8cc45d6
GC		 1074 qemu_add_vm_change_state_handler(cpu_update_state, env);
1075
df67696e
LJ		 1076 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1077 if (c) {
1078 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1079 !!(c->ecx & CPUID_EXT_SMX);
1080 }
1081
87f8b626
AR		 1082 if (env->mcg_cap & MCG_LMCE_P) {
1083 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1084 }
1085
d99569d9
EH		 1086 if (!env->user_tsc_khz) {
1087 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1088 invtsc_mig_blocker == NULL) {
1089 /* for migration */
1090 error_setg(&invtsc_mig_blocker,
1091 "State blocked by non-migratable CPU device"
1092 " (invtsc flag)");
fe44dc91
AA		 1093 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1094 if (local_err) {
1095 error_report_err(local_err);
1096 error_free(invtsc_mig_blocker);
1097 goto fail;
1098 }
d99569d9
EH		 1099 /* for savevm */
1100 vmstate_x86_cpu.unmigratable = 1;
1101 }
68bfd0ad
MT		 1102 }
1103
9954a158
PDJ		 1104 if (cpu->vmware_cpuid_freq
1105 /* Guests depend on 0x40000000 to detect this feature, so only expose
1106 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1107 && cpu->expose_kvm
1108 && kvm_base == KVM_CPUID_SIGNATURE
1109 /* TSC clock must be stable and known for this feature. */
4bb95b82 1110 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1111
1112 c = &cpuid_data.entries[cpuid_i++];
1113 c->function = KVM_CPUID_SIGNATURE | 0x10;
1114 c->eax = env->tsc_khz;
1115 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1116 * APIC_BUS_CYCLE_NS */
1117 c->ebx = 1000000;
1118 c->ecx = c->edx = 0;
1119
1120 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1121 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1122 }
1123
1124 cpuid_data.cpuid.nent = cpuid_i;
1125
1126 cpuid_data.cpuid.padding = 0;
1127 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1128 if (r) {
1129 goto fail;
1130 }
1131
28143b40 1132 if (has_xsave) {
fabacc0f
JK		 1133 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1134 }
d71b62a1 1135 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1136
273c515c
PB		 1137 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1138 has_msr_tsc_aux = false;
1139 }
d1ae67f6 1140
e7429073 1141 return 0;
fe44dc91
AA		 1142
1143 fail:
1144 migrate_del_blocker(invtsc_mig_blocker);
1145 return r;
05330448
AL		 1146}
1147
50a2c6e5 1148void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1149{
20d695a9 1150 CPUX86State *env = &cpu->env;
dd673288 1151
1a5e9d2f 1152 env->xcr0 = 1;
ddced198 1153 if (kvm_irqchip_in_kernel()) {
dd673288 1154 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1155 KVM_MP_STATE_UNINITIALIZED;
1156 } else {
1157 env->mp_state = KVM_MP_STATE_RUNNABLE;
1158 }
689141dd
RK		 1159
1160 if (cpu->hyperv_synic) {
1161 int i;
1162 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1163 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1164 }
1165 }
caa5af0f
JK		 1166}
1167
e0723c45
PB		 1168void kvm_arch_do_init_vcpu(X86CPU *cpu)
1169{
1170 CPUX86State *env = &cpu->env;
1171
1172 /* APs get directly into wait-for-SIPI state. */
1173 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1174 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1175 }
1176}
1177
c3a3a7d3 1178static int kvm_get_supported_msrs(KVMState *s)
05330448 1179{
75b10c43 1180 static int kvm_supported_msrs;
c3a3a7d3 1181 int ret = 0;
05330448
AL		 1182
1183 /* first time */
75b10c43 1184 if (kvm_supported_msrs == 0) {
05330448
AL		 1185 struct kvm_msr_list msr_list, *kvm_msr_list;
1186
75b10c43 1187 kvm_supported_msrs = -1;
05330448
AL		 1188
1189 /* Obtain MSR list from KVM. These are the MSRs that we must
1190 * save/restore */
4c9f7372 1191 msr_list.nmsrs = 0;
c3a3a7d3 1192 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1193 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1194 return ret;
6fb6d245 1195 }
d9db889f
JK		 1196 /* Old kernel modules had a bug and could write beyond the provided
1197 memory. Allocate at least a safe amount of 1K. */
7267c094 1198 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1199 msr_list.nmsrs *
1200 sizeof(msr_list.indices[0])));
05330448 1201
55308450 1202 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1203 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1204 if (ret >= 0) {
1205 int i;
1206
1207 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1208 switch (kvm_msr_list->indices[i]) {
1209 case MSR_STAR:
c3a3a7d3 1210 has_msr_star = true;
1d268dec
LP		 1211 break;
1212 case MSR_VM_HSAVE_PA:
c3a3a7d3 1213 has_msr_hsave_pa = true;
1d268dec
LP		 1214 break;
1215 case MSR_TSC_AUX:
c9b8f6b6 1216 has_msr_tsc_aux = true;
1d268dec
LP		 1217 break;
1218 case MSR_TSC_ADJUST:
f28558d3 1219 has_msr_tsc_adjust = true;
1d268dec
LP		 1220 break;
1221 case MSR_IA32_TSCDEADLINE:
aa82ba54 1222 has_msr_tsc_deadline = true;
1d268dec
LP		 1223 break;
1224 case MSR_IA32_SMBASE:
fc12d72e 1225 has_msr_smbase = true;
1d268dec 1226 break;
e13713db
LA		 1227 case MSR_SMI_COUNT:
1228 has_msr_smi_count = true;
1229 break;
1d268dec 1230 case MSR_IA32_MISC_ENABLE:
21e87c46 1231 has_msr_misc_enable = true;
1d268dec
LP		 1232 break;
1233 case MSR_IA32_BNDCFGS:
79e9ebeb 1234 has_msr_bndcfgs = true;
1d268dec
LP		 1235 break;
1236 case MSR_IA32_XSS:
18cd2c17 1237 has_msr_xss = true;
3c254ab8 1238 break;
1d268dec 1239 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1240 has_msr_hv_crash = true;
1d268dec
LP		 1241 break;
1242 case HV_X64_MSR_RESET:
744b8a94 1243 has_msr_hv_reset = true;
1d268dec
LP		 1244 break;
1245 case HV_X64_MSR_VP_INDEX:
8c145d7c 1246 has_msr_hv_vpindex = true;
1d268dec
LP		 1247 break;
1248 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1249 has_msr_hv_runtime = true;
1d268dec
LP		 1250 break;
1251 case HV_X64_MSR_SCONTROL:
866eea9a 1252 has_msr_hv_synic = true;
1d268dec
LP		 1253 break;
1254 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1255 has_msr_hv_stimer = true;
1d268dec 1256 break;
d72bc7f6
LP		 1257 case HV_X64_MSR_TSC_FREQUENCY:
1258 has_msr_hv_frequencies = true;
1259 break;
ba6a4fd9
VK		 1260 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1261 has_msr_hv_reenlightenment = true;
1262 break;
a33a2cfe
PB		 1263 case MSR_IA32_SPEC_CTRL:
1264 has_msr_spec_ctrl = true;
1265 break;
cfeea0c0
KRW		 1266 case MSR_VIRT_SSBD:
1267 has_msr_virt_ssbd = true;
1268 break;
ff99aa64 1269 }
05330448
AL		 1270 }
1271 }
1272
7267c094 1273 g_free(kvm_msr_list);
05330448
AL		 1274 }
1275
c3a3a7d3 1276 return ret;
05330448
AL		 1277}
1278
6410848b
PB		 1279static Notifier smram_machine_done;
1280static KVMMemoryListener smram_listener;
1281static AddressSpace smram_address_space;
1282static MemoryRegion smram_as_root;
1283static MemoryRegion smram_as_mem;
1284
1285static void register_smram_listener(Notifier *n, void *unused)
1286{
1287 MemoryRegion *smram =
1288 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1289
1290 /* Outer container... */
1291 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1292 memory_region_set_enabled(&smram_as_root, true);
1293
1294 /* ... with two regions inside: normal system memory with low
1295 * priority, and...
1296 */
1297 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1298 get_system_memory(), 0, ~0ull);
1299 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1300 memory_region_set_enabled(&smram_as_mem, true);
1301
1302 if (smram) {
1303 /* ... SMRAM with higher priority */
1304 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1305 memory_region_set_enabled(smram, true);
1306 }
1307
1308 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1309 kvm_memory_listener_register(kvm_state, &smram_listener,
1310 &smram_address_space, 1);
1311}
1312
b16565b3 1313int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1314{
11076198 1315 uint64_t identity_base = 0xfffbc000;
39d6960a 1316 uint64_t shadow_mem;
20420430 1317 int ret;
25d2e361 1318 struct utsname utsname;
20420430 1319
28143b40
TH		 1320#ifdef KVM_CAP_XSAVE
1321 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1322#endif
1323
1324#ifdef KVM_CAP_XCRS
1325 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1326#endif
1327
1328#ifdef KVM_CAP_PIT_STATE2
1329 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1330#endif
1331
c3a3a7d3 1332 ret = kvm_get_supported_msrs(s);
20420430 1333 if (ret < 0) {
20420430
SY		 1334 return ret;
1335 }
25d2e361
MT		 1336
1337 uname(&utsname);
1338 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1339
4c5b10b7 1340 /*
11076198
JK		 1341 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1342 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1343 * Since these must be part of guest physical memory, we need to allocate
1344 * them, both by setting their start addresses in the kernel and by
1345 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1346 *
1347 * Older KVM versions may not support setting the identity map base. In
1348 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1349 * size.
4c5b10b7 1350 */
11076198
JK		 1351 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1352 /* Allows up to 16M BIOSes. */
1353 identity_base = 0xfeffc000;
1354
1355 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1356 if (ret < 0) {
1357 return ret;
1358 }
4c5b10b7 1359 }
e56ff191 1360
11076198
JK		 1361 /* Set TSS base one page after EPT identity map. */
1362 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1363 if (ret < 0) {
1364 return ret;
1365 }
1366
11076198
JK		 1367 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1368 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1369 if (ret < 0) {
11076198 1370 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1371 return ret;
1372 }
3c85e74f 1373 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1374
4689b77b 1375 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1376 if (shadow_mem != -1) {
1377 shadow_mem /= 4096;
1378 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1379 if (ret < 0) {
1380 return ret;
39d6960a
JK		 1381 }
1382 }
6410848b 1383
d870cfde
GA		 1384 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1385 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1386 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1387 smram_machine_done.notify = register_smram_listener;
1388 qemu_add_machine_init_done_notifier(&smram_machine_done);
1389 }
11076198 1390 return 0;
05330448 1391}
b9bec74b 1392
05330448
AL		 1393static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1394{
1395 lhs->selector = rhs->selector;
1396 lhs->base = rhs->base;
1397 lhs->limit = rhs->limit;
1398 lhs->type = 3;
1399 lhs->present = 1;
1400 lhs->dpl = 3;
1401 lhs->db = 0;
1402 lhs->s = 1;
1403 lhs->l = 0;
1404 lhs->g = 0;
1405 lhs->avl = 0;
1406 lhs->unusable = 0;
1407}
1408
1409static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1410{
1411 unsigned flags = rhs->flags;
1412 lhs->selector = rhs->selector;
1413 lhs->base = rhs->base;
1414 lhs->limit = rhs->limit;
1415 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1416 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1417 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1418 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1419 lhs->s = (flags & DESC_S_MASK) != 0;
1420 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1421 lhs->g = (flags & DESC_G_MASK) != 0;
1422 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1423 lhs->unusable = !lhs->present;
7e680753 1424 lhs->padding = 0;
05330448
AL		 1425}
1426
1427static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1428{
1429 lhs->selector = rhs->selector;
1430 lhs->base = rhs->base;
1431 lhs->limit = rhs->limit;
d45fc087
RP		 1432 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1433 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1434 (rhs->dpl << DESC_DPL_SHIFT) |
1435 (rhs->db << DESC_B_SHIFT) |
1436 (rhs->s * DESC_S_MASK) |
1437 (rhs->l << DESC_L_SHIFT) |
1438 (rhs->g * DESC_G_MASK) |
1439 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1440}
1441
1442static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1443{
b9bec74b 1444 if (set) {
05330448 1445 *kvm_reg = *qemu_reg;
b9bec74b 1446 } else {
05330448 1447 *qemu_reg = *kvm_reg;
b9bec74b 1448 }
05330448
AL		 1449}
1450
1bc22652 1451static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1452{
1bc22652 1453 CPUX86State *env = &cpu->env;
05330448
AL		 1454 struct kvm_regs regs;
1455 int ret = 0;
1456
1457 if (!set) {
1bc22652 1458 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1459 if (ret < 0) {
05330448 1460 return ret;
b9bec74b 1461 }
05330448
AL		 1462 }
1463
1464 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1465 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1466 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1467 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1468 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1469 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1470 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1471 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1472#ifdef TARGET_X86_64
1473 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1474 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1475 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1476 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1477 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1478 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1479 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1480 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1481#endif
1482
1483 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1484 kvm_getput_reg(&regs.rip, &env->eip, set);
1485
b9bec74b 1486 if (set) {
1bc22652 1487 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1488 }
05330448
AL		 1489
1490 return ret;
1491}
1492
1bc22652 1493static int kvm_put_fpu(X86CPU *cpu)
05330448 1494{
1bc22652 1495 CPUX86State *env = &cpu->env;
05330448
AL		 1496 struct kvm_fpu fpu;
1497 int i;
1498
1499 memset(&fpu, 0, sizeof fpu);
1500 fpu.fsw = env->fpus & ~(7 << 11);
1501 fpu.fsw |= (env->fpstt & 7) << 11;
1502 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1503 fpu.last_opcode = env->fpop;
1504 fpu.last_ip = env->fpip;
1505 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1506 for (i = 0; i < 8; ++i) {
1507 fpu.ftwx |= (!env->fptags[i]) << i;
1508 }
05330448 1509 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1510 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1511 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1512 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1513 }
05330448
AL		 1514 fpu.mxcsr = env->mxcsr;
1515
1bc22652 1516 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1517}
1518
6b42494b
JK		 1519#define XSAVE_FCW_FSW 0
1520#define XSAVE_FTW_FOP 1
f1665b21
SY		 1521#define XSAVE_CWD_RIP 2
1522#define XSAVE_CWD_RDP 4
1523#define XSAVE_MXCSR 6
1524#define XSAVE_ST_SPACE 8
1525#define XSAVE_XMM_SPACE 40
1526#define XSAVE_XSTATE_BV 128
1527#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1528#define XSAVE_BNDREGS 240
1529#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1530#define XSAVE_OPMASK 272
1531#define XSAVE_ZMM_Hi256 288
1532#define XSAVE_Hi16_ZMM 416
f74eefe0 1533#define XSAVE_PKRU 672
f1665b21 1534
b503717d
EH		 1535#define XSAVE_BYTE_OFFSET(word_offset) \
1536 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1537
1538#define ASSERT_OFFSET(word_offset, field) \
1539 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1540 offsetof(X86XSaveArea, field))
1541
1542ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1543ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1544ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1545ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1546ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1547ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1548ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1549ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1550ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1551ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1552ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1553ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1554ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1555ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1556ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1557
1bc22652 1558static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1559{
1bc22652 1560 CPUX86State *env = &cpu->env;
86cd2ea0 1561 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1562
28143b40 1563 if (!has_xsave) {
1bc22652 1564 return kvm_put_fpu(cpu);
b9bec74b 1565 }
86a57621 1566 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1567
9be38598 1568 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1569}
1570
1bc22652 1571static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1572{
1bc22652 1573 CPUX86State *env = &cpu->env;
bdfc8480 1574 struct kvm_xcrs xcrs = {};
f1665b21 1575
28143b40 1576 if (!has_xcrs) {
f1665b21 1577 return 0;
b9bec74b 1578 }
f1665b21
SY		 1579
1580 xcrs.nr_xcrs = 1;
1581 xcrs.flags = 0;
1582 xcrs.xcrs[0].xcr = 0;
1583 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1584 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1585}
1586
1bc22652 1587static int kvm_put_sregs(X86CPU *cpu)
05330448 1588{
1bc22652 1589 CPUX86State *env = &cpu->env;
05330448
AL		 1590 struct kvm_sregs sregs;
1591
0e607a80
JK		 1592 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1593 if (env->interrupt_injected >= 0) {
1594 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1595 (uint64_t)1 << (env->interrupt_injected % 64);
1596 }
05330448
AL		 1597
1598 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1599 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1600 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1601 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1602 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1603 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1604 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1605 } else {
b9bec74b
JK		 1606 set_seg(&sregs.cs, &env->segs[R_CS]);
1607 set_seg(&sregs.ds, &env->segs[R_DS]);
1608 set_seg(&sregs.es, &env->segs[R_ES]);
1609 set_seg(&sregs.fs, &env->segs[R_FS]);
1610 set_seg(&sregs.gs, &env->segs[R_GS]);
1611 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1612 }
1613
1614 set_seg(&sregs.tr, &env->tr);
1615 set_seg(&sregs.ldt, &env->ldt);
1616
1617 sregs.idt.limit = env->idt.limit;
1618 sregs.idt.base = env->idt.base;
7e680753 1619 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1620 sregs.gdt.limit = env->gdt.limit;
1621 sregs.gdt.base = env->gdt.base;
7e680753 1622 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1623
1624 sregs.cr0 = env->cr[0];
1625 sregs.cr2 = env->cr[2];
1626 sregs.cr3 = env->cr[3];
1627 sregs.cr4 = env->cr[4];
1628
02e51483
CF		 1629 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1630 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1631
1632 sregs.efer = env->efer;
1633
1bc22652 1634 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1635}
1636
d71b62a1
EH		 1637static void kvm_msr_buf_reset(X86CPU *cpu)
1638{
1639 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1640}
1641
9c600a84
EH		 1642static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1643{
1644 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1645 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1646 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1647
1648 assert((void *)(entry + 1) <= limit);
1649
1abc2cae
EH		 1650 entry->index = index;
1651 entry->reserved = 0;
1652 entry->data = value;
9c600a84
EH		 1653 msrs->nmsrs++;
1654}
1655
73e1b8f2
PB		 1656static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1657{
1658 kvm_msr_buf_reset(cpu);
1659 kvm_msr_entry_add(cpu, index, value);
1660
1661 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1662}
1663
f8d9ccf8
DDAG		 1664void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1665{
1666 int ret;
1667
1668 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1669 assert(ret == 1);
1670}
1671
7477cd38
MT		 1672static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1673{
1674 CPUX86State *env = &cpu->env;
48e1a45c 1675 int ret;
7477cd38
MT		 1676
1677 if (!has_msr_tsc_deadline) {
1678 return 0;
1679 }
1680
73e1b8f2 1681 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1682 if (ret < 0) {
1683 return ret;
1684 }
1685
1686 assert(ret == 1);
1687 return 0;
7477cd38
MT		 1688}
1689
6bdf863d
JK		 1690/*
1691 * Provide a separate write service for the feature control MSR in order to
1692 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1693 * before writing any other state because forcibly leaving nested mode
1694 * invalidates the VCPU state.
1695 */
1696static int kvm_put_msr_feature_control(X86CPU *cpu)
1697{
48e1a45c
PB		 1698 int ret;
1699
1700 if (!has_msr_feature_control) {
1701 return 0;
1702 }
6bdf863d 1703
73e1b8f2
PB		 1704 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1705 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1706 if (ret < 0) {
1707 return ret;
1708 }
1709
1710 assert(ret == 1);
1711 return 0;
6bdf863d
JK		 1712}
1713
1bc22652 1714static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1715{
1bc22652 1716 CPUX86State *env = &cpu->env;
9c600a84 1717 int i;
48e1a45c 1718 int ret;
05330448 1719
d71b62a1
EH		 1720 kvm_msr_buf_reset(cpu);
1721
9c600a84
EH		 1722 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1723 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1724 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1725 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1726 if (has_msr_star) {
9c600a84 1727 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1728 }
c3a3a7d3 1729 if (has_msr_hsave_pa) {
9c600a84 1730 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1731 }
c9b8f6b6 1732 if (has_msr_tsc_aux) {
9c600a84 1733 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1734 }
f28558d3 1735 if (has_msr_tsc_adjust) {
9c600a84 1736 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1737 }
21e87c46 1738 if (has_msr_misc_enable) {
9c600a84 1739 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1740 env->msr_ia32_misc_enable);
1741 }
fc12d72e 1742 if (has_msr_smbase) {
9c600a84 1743 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1744 }
e13713db
LA		 1745 if (has_msr_smi_count) {
1746 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1747 }
439d19f2 1748 if (has_msr_bndcfgs) {
9c600a84 1749 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1750 }
18cd2c17 1751 if (has_msr_xss) {
9c600a84 1752 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1753 }
a33a2cfe
PB		 1754 if (has_msr_spec_ctrl) {
1755 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1756 }
cfeea0c0
KRW		 1757 if (has_msr_virt_ssbd) {
1758 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1759 }
1760
05330448 1761#ifdef TARGET_X86_64
25d2e361 1762 if (lm_capable_kernel) {
9c600a84
EH		 1763 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1764 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1765 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1766 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1767 }
05330448 1768#endif
a33a2cfe 1769
ff5c186b 1770 /*
0d894367
PB		 1771 * The following MSRs have side effects on the guest or are too heavy
1772 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1773 */
1774 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1775 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1776 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1777 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1778 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1779 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1780 }
55c911a5 1781 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1782 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1783 }
55c911a5 1784 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1785 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1786 }
0b368a10
JD		 1787 if (has_architectural_pmu_version > 0) {
1788 if (has_architectural_pmu_version > 1) {
1789 /* Stop the counter. */
1790 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1791 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1792 }
0d894367
PB		 1793
1794 /* Set the counter values. */
0b368a10 1795 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 1796 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1797 env->msr_fixed_counters[i]);
1798 }
0b368a10 1799 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 1800 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1801 env->msr_gp_counters[i]);
9c600a84 1802 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1803 env->msr_gp_evtsel[i]);
1804 }
0b368a10
JD		 1805 if (has_architectural_pmu_version > 1) {
1806 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1807 env->msr_global_status);
1808 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1809 env->msr_global_ovf_ctrl);
1810
1811 /* Now start the PMU. */
1812 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1813 env->msr_fixed_ctr_ctrl);
1814 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1815 env->msr_global_ctrl);
1816 }
0d894367 1817 }
da1cc323
EY		 1818 /*
1819 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1820 * only sync them to KVM on the first cpu
1821 */
1822 if (current_cpu == first_cpu) {
1823 if (has_msr_hv_hypercall) {
1824 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1825 env->msr_hv_guest_os_id);
1826 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1827 env->msr_hv_hypercall);
1828 }
1829 if (cpu->hyperv_time) {
1830 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1831 env->msr_hv_tsc);
1832 }
ba6a4fd9
VK		 1833 if (cpu->hyperv_reenlightenment) {
1834 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
1835 env->msr_hv_reenlightenment_control);
1836 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
1837 env->msr_hv_tsc_emulation_control);
1838 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
1839 env->msr_hv_tsc_emulation_status);
1840 }
eab70139 1841 }
2d5aa872 1842 if (cpu->hyperv_vapic) {
9c600a84 1843 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1844 env->msr_hv_vapic);
eab70139 1845 }
f2a53c9e
AS		 1846 if (has_msr_hv_crash) {
1847 int j;
1848
5e953812 1849 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 1850 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1851 env->msr_hv_crash_params[j]);
1852
5e953812 1853 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 1854 }
46eb8f98 1855 if (has_msr_hv_runtime) {
9c600a84 1856 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1857 }
866eea9a
AS		 1858 if (cpu->hyperv_synic) {
1859 int j;
1860
09df29b6
RK		 1861 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1862
9c600a84 1863 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1864 env->msr_hv_synic_control);
9c600a84 1865 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1866 env->msr_hv_synic_evt_page);
9c600a84 1867 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1868 env->msr_hv_synic_msg_page);
1869
1870 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1871 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1872 env->msr_hv_synic_sint[j]);
1873 }
1874 }
ff99aa64
AS		 1875 if (has_msr_hv_stimer) {
1876 int j;
1877
1878 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1879 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1880 env->msr_hv_stimer_config[j]);
1881 }
1882
1883 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1884 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1885 env->msr_hv_stimer_count[j]);
1886 }
1887 }
1eabfce6 1888 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1889 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1890
9c600a84
EH		 1891 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1892 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1893 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1894 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1895 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1896 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1897 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1898 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1899 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1900 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1901 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1902 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1903 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1904 /* The CPU GPs if we write to a bit above the physical limit of
1905 * the host CPU (and KVM emulates that)
1906 */
1907 uint64_t mask = env->mtrr_var[i].mask;
1908 mask &= phys_mask;
1909
9c600a84
EH		 1910 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1911 env->mtrr_var[i].base);
112dad69 1912 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1913 }
1914 }
b77146e9
CP		 1915 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
1916 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
1917 0x14, 1, R_EAX) & 0x7;
1918
1919 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
1920 env->msr_rtit_ctrl);
1921 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
1922 env->msr_rtit_status);
1923 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
1924 env->msr_rtit_output_base);
1925 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
1926 env->msr_rtit_output_mask);
1927 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
1928 env->msr_rtit_cr3_match);
1929 for (i = 0; i < addr_num; i++) {
1930 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
1931 env->msr_rtit_addrs[i]);
1932 }
1933 }
6bdf863d
JK		 1934
1935 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1936 * kvm_put_msr_feature_control. */
ea643051 1937 }
57780495 1938 if (env->mcg_cap) {
d8da8574 1939 int i;
b9bec74b 1940
9c600a84
EH		 1941 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1942 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1943 if (has_msr_mcg_ext_ctl) {
1944 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1945 }
c34d440a 1946 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1947 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1948 }
1949 }
1a03675d 1950
d71b62a1 1951 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1952 if (ret < 0) {
1953 return ret;
1954 }
05330448 1955
c70b11d1
EH		 1956 if (ret < cpu->kvm_msr_buf->nmsrs) {
1957 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1958 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1959 (uint32_t)e->index, (uint64_t)e->data);
1960 }
1961
9c600a84 1962 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1963 return 0;
05330448
AL		 1964}
1965
1966
1bc22652 1967static int kvm_get_fpu(X86CPU *cpu)
05330448 1968{
1bc22652 1969 CPUX86State *env = &cpu->env;
05330448
AL		 1970 struct kvm_fpu fpu;
1971 int i, ret;
1972
1bc22652 1973 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1974 if (ret < 0) {
05330448 1975 return ret;
b9bec74b 1976 }
05330448
AL		 1977
1978 env->fpstt = (fpu.fsw >> 11) & 7;
1979 env->fpus = fpu.fsw;
1980 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1981 env->fpop = fpu.last_opcode;
1982 env->fpip = fpu.last_ip;
1983 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1984 for (i = 0; i < 8; ++i) {
1985 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1986 }
05330448 1987 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1988 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1989 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1990 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1991 }
05330448
AL		 1992 env->mxcsr = fpu.mxcsr;
1993
1994 return 0;
1995}
1996
1bc22652 1997static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1998{
1bc22652 1999 CPUX86State *env = &cpu->env;
86cd2ea0 2000 X86XSaveArea *xsave = env->kvm_xsave_buf;
86a57621 2001 int ret;
f1665b21 2002
28143b40 2003 if (!has_xsave) {
1bc22652 2004 return kvm_get_fpu(cpu);
b9bec74b 2005 }
f1665b21 2006
1bc22652 2007 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2008 if (ret < 0) {
f1665b21 2009 return ret;
0f53994f 2010 }
86a57621 2011 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2012
f1665b21 2013 return 0;
f1665b21
SY		 2014}
2015
1bc22652 2016static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2017{
1bc22652 2018 CPUX86State *env = &cpu->env;
f1665b21
SY		 2019 int i, ret;
2020 struct kvm_xcrs xcrs;
2021
28143b40 2022 if (!has_xcrs) {
f1665b21 2023 return 0;
b9bec74b 2024 }
f1665b21 2025
1bc22652 2026 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2027 if (ret < 0) {
f1665b21 2028 return ret;
b9bec74b 2029 }
f1665b21 2030
b9bec74b 2031 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2032 /* Only support xcr0 now */
0fd53fec
PB		 2033 if (xcrs.xcrs[i].xcr == 0) {
2034 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2035 break;
2036 }
b9bec74b 2037 }
f1665b21 2038 return 0;
f1665b21
SY		 2039}
2040
1bc22652 2041static int kvm_get_sregs(X86CPU *cpu)
05330448 2042{
1bc22652 2043 CPUX86State *env = &cpu->env;
05330448 2044 struct kvm_sregs sregs;
0e607a80 2045 int bit, i, ret;
05330448 2046
1bc22652 2047 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2048 if (ret < 0) {
05330448 2049 return ret;
b9bec74b 2050 }
05330448 2051
0e607a80
JK		 2052 /* There can only be one pending IRQ set in the bitmap at a time, so try
2053 to find it and save its number instead (-1 for none). */
2054 env->interrupt_injected = -1;
2055 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2056 if (sregs.interrupt_bitmap[i]) {
2057 bit = ctz64(sregs.interrupt_bitmap[i]);
2058 env->interrupt_injected = i * 64 + bit;
2059 break;
2060 }
2061 }
05330448
AL		 2062
2063 get_seg(&env->segs[R_CS], &sregs.cs);
2064 get_seg(&env->segs[R_DS], &sregs.ds);
2065 get_seg(&env->segs[R_ES], &sregs.es);
2066 get_seg(&env->segs[R_FS], &sregs.fs);
2067 get_seg(&env->segs[R_GS], &sregs.gs);
2068 get_seg(&env->segs[R_SS], &sregs.ss);
2069
2070 get_seg(&env->tr, &sregs.tr);
2071 get_seg(&env->ldt, &sregs.ldt);
2072
2073 env->idt.limit = sregs.idt.limit;
2074 env->idt.base = sregs.idt.base;
2075 env->gdt.limit = sregs.gdt.limit;
2076 env->gdt.base = sregs.gdt.base;
2077
2078 env->cr[0] = sregs.cr0;
2079 env->cr[2] = sregs.cr2;
2080 env->cr[3] = sregs.cr3;
2081 env->cr[4] = sregs.cr4;
2082
05330448 2083 env->efer = sregs.efer;
cce47516
JK		 2084
2085 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2086 x86_update_hflags(env);
05330448
AL		 2087
2088 return 0;
2089}
2090
1bc22652 2091static int kvm_get_msrs(X86CPU *cpu)
05330448 2092{
1bc22652 2093 CPUX86State *env = &cpu->env;
d71b62a1 2094 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2095 int ret, i;
fcc35e7c 2096 uint64_t mtrr_top_bits;
05330448 2097
d71b62a1
EH		 2098 kvm_msr_buf_reset(cpu);
2099
9c600a84
EH		 2100 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2101 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2102 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2103 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2104 if (has_msr_star) {
9c600a84 2105 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2106 }
c3a3a7d3 2107 if (has_msr_hsave_pa) {
9c600a84 2108 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2109 }
c9b8f6b6 2110 if (has_msr_tsc_aux) {
9c600a84 2111 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2112 }
f28558d3 2113 if (has_msr_tsc_adjust) {
9c600a84 2114 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2115 }
aa82ba54 2116 if (has_msr_tsc_deadline) {
9c600a84 2117 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2118 }
21e87c46 2119 if (has_msr_misc_enable) {
9c600a84 2120 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2121 }
fc12d72e 2122 if (has_msr_smbase) {
9c600a84 2123 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2124 }
e13713db
LA		 2125 if (has_msr_smi_count) {
2126 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2127 }
df67696e 2128 if (has_msr_feature_control) {
9c600a84 2129 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2130 }
79e9ebeb 2131 if (has_msr_bndcfgs) {
9c600a84 2132 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2133 }
18cd2c17 2134 if (has_msr_xss) {
9c600a84 2135 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2136 }
a33a2cfe
PB		 2137 if (has_msr_spec_ctrl) {
2138 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2139 }
cfeea0c0
KRW		 2140 if (has_msr_virt_ssbd) {
2141 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2142 }
b8cc45d6 2143 if (!env->tsc_valid) {
9c600a84 2144 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2145 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2146 }
2147
05330448 2148#ifdef TARGET_X86_64
25d2e361 2149 if (lm_capable_kernel) {
9c600a84
EH		 2150 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2151 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2152 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2153 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2154 }
05330448 2155#endif
9c600a84
EH		 2156 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2157 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2158 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2159 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2160 }
55c911a5 2161 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2162 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2163 }
55c911a5 2164 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2165 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2166 }
0b368a10
JD		 2167 if (has_architectural_pmu_version > 0) {
2168 if (has_architectural_pmu_version > 1) {
2169 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2170 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2171 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2172 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2173 }
2174 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2175 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2176 }
0b368a10 2177 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2178 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2179 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2180 }
2181 }
1a03675d 2182
57780495 2183 if (env->mcg_cap) {
9c600a84
EH		 2184 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2185 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2186 if (has_msr_mcg_ext_ctl) {
2187 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2188 }
b9bec74b 2189 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2190 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2191 }
57780495 2192 }
57780495 2193
1c90ef26 2194 if (has_msr_hv_hypercall) {
9c600a84
EH		 2195 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2196 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2197 }
2d5aa872 2198 if (cpu->hyperv_vapic) {
9c600a84 2199 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2200 }
3ddcd2ed 2201 if (cpu->hyperv_time) {
9c600a84 2202 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2203 }
ba6a4fd9
VK		 2204 if (cpu->hyperv_reenlightenment) {
2205 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2206 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2207 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2208 }
f2a53c9e
AS		 2209 if (has_msr_hv_crash) {
2210 int j;
2211
5e953812 2212 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2213 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2214 }
2215 }
46eb8f98 2216 if (has_msr_hv_runtime) {
9c600a84 2217 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2218 }
866eea9a
AS		 2219 if (cpu->hyperv_synic) {
2220 uint32_t msr;
2221
9c600a84 2222 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2223 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2224 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2225 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2226 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2227 }
2228 }
ff99aa64
AS		 2229 if (has_msr_hv_stimer) {
2230 uint32_t msr;
2231
2232 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2233 msr++) {
9c600a84 2234 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2235 }
2236 }
1eabfce6 2237 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2238 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2239 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2240 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2241 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2242 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2243 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2244 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2245 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2246 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2247 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2248 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2249 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2250 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2251 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2252 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2253 }
2254 }
5ef68987 2255
b77146e9
CP		 2256 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2257 int addr_num =
2258 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2259
2260 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2261 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2262 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2263 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2264 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2265 for (i = 0; i < addr_num; i++) {
2266 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2267 }
2268 }
2269
d71b62a1 2270 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2271 if (ret < 0) {
05330448 2272 return ret;
b9bec74b 2273 }
05330448 2274
c70b11d1
EH		 2275 if (ret < cpu->kvm_msr_buf->nmsrs) {
2276 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2277 error_report("error: failed to get MSR 0x%" PRIx32,
2278 (uint32_t)e->index);
2279 }
2280
9c600a84 2281 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2282 /*
2283 * MTRR masks: Each mask consists of 5 parts
2284 * a 10..0: must be zero
2285 * b 11 : valid bit
2286 * c n-1.12: actual mask bits
2287 * d 51..n: reserved must be zero
2288 * e 63.52: reserved must be zero
2289 *
2290 * 'n' is the number of physical bits supported by the CPU and is
2291 * apparently always <= 52. We know our 'n' but don't know what
2292 * the destinations 'n' is; it might be smaller, in which case
2293 * it masks (c) on loading. It might be larger, in which case
2294 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2295 * we're migrating to.
2296 */
2297
2298 if (cpu->fill_mtrr_mask) {
2299 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2300 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2301 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2302 } else {
2303 mtrr_top_bits = 0;
2304 }
2305
05330448 2306 for (i = 0; i < ret; i++) {
0d894367
PB		 2307 uint32_t index = msrs[i].index;
2308 switch (index) {
05330448
AL		 2309 case MSR_IA32_SYSENTER_CS:
2310 env->sysenter_cs = msrs[i].data;
2311 break;
2312 case MSR_IA32_SYSENTER_ESP:
2313 env->sysenter_esp = msrs[i].data;
2314 break;
2315 case MSR_IA32_SYSENTER_EIP:
2316 env->sysenter_eip = msrs[i].data;
2317 break;
0c03266a
JK		 2318 case MSR_PAT:
2319 env->pat = msrs[i].data;
2320 break;
05330448
AL		 2321 case MSR_STAR:
2322 env->star = msrs[i].data;
2323 break;
2324#ifdef TARGET_X86_64
2325 case MSR_CSTAR:
2326 env->cstar = msrs[i].data;
2327 break;
2328 case MSR_KERNELGSBASE:
2329 env->kernelgsbase = msrs[i].data;
2330 break;
2331 case MSR_FMASK:
2332 env->fmask = msrs[i].data;
2333 break;
2334 case MSR_LSTAR:
2335 env->lstar = msrs[i].data;
2336 break;
2337#endif
2338 case MSR_IA32_TSC:
2339 env->tsc = msrs[i].data;
2340 break;
c9b8f6b6
AS		 2341 case MSR_TSC_AUX:
2342 env->tsc_aux = msrs[i].data;
2343 break;
f28558d3
WA		 2344 case MSR_TSC_ADJUST:
2345 env->tsc_adjust = msrs[i].data;
2346 break;
aa82ba54
LJ		 2347 case MSR_IA32_TSCDEADLINE:
2348 env->tsc_deadline = msrs[i].data;
2349 break;
aa851e36
MT		 2350 case MSR_VM_HSAVE_PA:
2351 env->vm_hsave = msrs[i].data;
2352 break;
1a03675d
GC		 2353 case MSR_KVM_SYSTEM_TIME:
2354 env->system_time_msr = msrs[i].data;
2355 break;
2356 case MSR_KVM_WALL_CLOCK:
2357 env->wall_clock_msr = msrs[i].data;
2358 break;
57780495
MT		 2359 case MSR_MCG_STATUS:
2360 env->mcg_status = msrs[i].data;
2361 break;
2362 case MSR_MCG_CTL:
2363 env->mcg_ctl = msrs[i].data;
2364 break;
87f8b626
AR		 2365 case MSR_MCG_EXT_CTL:
2366 env->mcg_ext_ctl = msrs[i].data;
2367 break;
21e87c46
AK		 2368 case MSR_IA32_MISC_ENABLE:
2369 env->msr_ia32_misc_enable = msrs[i].data;
2370 break;
fc12d72e
PB		 2371 case MSR_IA32_SMBASE:
2372 env->smbase = msrs[i].data;
2373 break;
e13713db
LA		 2374 case MSR_SMI_COUNT:
2375 env->msr_smi_count = msrs[i].data;
2376 break;
0779caeb
ACL		 2377 case MSR_IA32_FEATURE_CONTROL:
2378 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2379 break;
79e9ebeb
LJ		 2380 case MSR_IA32_BNDCFGS:
2381 env->msr_bndcfgs = msrs[i].data;
2382 break;
18cd2c17
WL		 2383 case MSR_IA32_XSS:
2384 env->xss = msrs[i].data;
2385 break;
57780495 2386 default:
57780495
MT		 2387 if (msrs[i].index >= MSR_MC0_CTL &&
2388 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2389 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2390 }
d8da8574 2391 break;
f6584ee2
GN		 2392 case MSR_KVM_ASYNC_PF_EN:
2393 env->async_pf_en_msr = msrs[i].data;
2394 break;
bc9a839d
MT		 2395 case MSR_KVM_PV_EOI_EN:
2396 env->pv_eoi_en_msr = msrs[i].data;
2397 break;
917367aa
MT		 2398 case MSR_KVM_STEAL_TIME:
2399 env->steal_time_msr = msrs[i].data;
2400 break;
0d894367
PB		 2401 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2402 env->msr_fixed_ctr_ctrl = msrs[i].data;
2403 break;
2404 case MSR_CORE_PERF_GLOBAL_CTRL:
2405 env->msr_global_ctrl = msrs[i].data;
2406 break;
2407 case MSR_CORE_PERF_GLOBAL_STATUS:
2408 env->msr_global_status = msrs[i].data;
2409 break;
2410 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2411 env->msr_global_ovf_ctrl = msrs[i].data;
2412 break;
2413 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2414 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2415 break;
2416 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2417 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2418 break;
2419 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2420 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2421 break;
1c90ef26
VR		 2422 case HV_X64_MSR_HYPERCALL:
2423 env->msr_hv_hypercall = msrs[i].data;
2424 break;
2425 case HV_X64_MSR_GUEST_OS_ID:
2426 env->msr_hv_guest_os_id = msrs[i].data;
2427 break;
5ef68987
VR		 2428 case HV_X64_MSR_APIC_ASSIST_PAGE:
2429 env->msr_hv_vapic = msrs[i].data;
2430 break;
48a5f3bc
VR		 2431 case HV_X64_MSR_REFERENCE_TSC:
2432 env->msr_hv_tsc = msrs[i].data;
2433 break;
f2a53c9e
AS		 2434 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2435 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2436 break;
46eb8f98
AS		 2437 case HV_X64_MSR_VP_RUNTIME:
2438 env->msr_hv_runtime = msrs[i].data;
2439 break;
866eea9a
AS		 2440 case HV_X64_MSR_SCONTROL:
2441 env->msr_hv_synic_control = msrs[i].data;
2442 break;
866eea9a
AS		 2443 case HV_X64_MSR_SIEFP:
2444 env->msr_hv_synic_evt_page = msrs[i].data;
2445 break;
2446 case HV_X64_MSR_SIMP:
2447 env->msr_hv_synic_msg_page = msrs[i].data;
2448 break;
2449 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2450 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2451 break;
2452 case HV_X64_MSR_STIMER0_CONFIG:
2453 case HV_X64_MSR_STIMER1_CONFIG:
2454 case HV_X64_MSR_STIMER2_CONFIG:
2455 case HV_X64_MSR_STIMER3_CONFIG:
2456 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2457 msrs[i].data;
2458 break;
2459 case HV_X64_MSR_STIMER0_COUNT:
2460 case HV_X64_MSR_STIMER1_COUNT:
2461 case HV_X64_MSR_STIMER2_COUNT:
2462 case HV_X64_MSR_STIMER3_COUNT:
2463 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2464 msrs[i].data;
866eea9a 2465 break;
ba6a4fd9
VK		 2466 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2467 env->msr_hv_reenlightenment_control = msrs[i].data;
2468 break;
2469 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2470 env->msr_hv_tsc_emulation_control = msrs[i].data;
2471 break;
2472 case HV_X64_MSR_TSC_EMULATION_STATUS:
2473 env->msr_hv_tsc_emulation_status = msrs[i].data;
2474 break;
d1ae67f6
AW		 2475 case MSR_MTRRdefType:
2476 env->mtrr_deftype = msrs[i].data;
2477 break;
2478 case MSR_MTRRfix64K_00000:
2479 env->mtrr_fixed[0] = msrs[i].data;
2480 break;
2481 case MSR_MTRRfix16K_80000:
2482 env->mtrr_fixed[1] = msrs[i].data;
2483 break;
2484 case MSR_MTRRfix16K_A0000:
2485 env->mtrr_fixed[2] = msrs[i].data;
2486 break;
2487 case MSR_MTRRfix4K_C0000:
2488 env->mtrr_fixed[3] = msrs[i].data;
2489 break;
2490 case MSR_MTRRfix4K_C8000:
2491 env->mtrr_fixed[4] = msrs[i].data;
2492 break;
2493 case MSR_MTRRfix4K_D0000:
2494 env->mtrr_fixed[5] = msrs[i].data;
2495 break;
2496 case MSR_MTRRfix4K_D8000:
2497 env->mtrr_fixed[6] = msrs[i].data;
2498 break;
2499 case MSR_MTRRfix4K_E0000:
2500 env->mtrr_fixed[7] = msrs[i].data;
2501 break;
2502 case MSR_MTRRfix4K_E8000:
2503 env->mtrr_fixed[8] = msrs[i].data;
2504 break;
2505 case MSR_MTRRfix4K_F0000:
2506 env->mtrr_fixed[9] = msrs[i].data;
2507 break;
2508 case MSR_MTRRfix4K_F8000:
2509 env->mtrr_fixed[10] = msrs[i].data;
2510 break;
2511 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2512 if (index & 1) {
fcc35e7c
DDAG		 2513 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2514 mtrr_top_bits;
d1ae67f6
AW		 2515 } else {
2516 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2517 }
2518 break;
a33a2cfe
PB		 2519 case MSR_IA32_SPEC_CTRL:
2520 env->spec_ctrl = msrs[i].data;
2521 break;
cfeea0c0
KRW		 2522 case MSR_VIRT_SSBD:
2523 env->virt_ssbd = msrs[i].data;
2524 break;
b77146e9
CP		 2525 case MSR_IA32_RTIT_CTL:
2526 env->msr_rtit_ctrl = msrs[i].data;
2527 break;
2528 case MSR_IA32_RTIT_STATUS:
2529 env->msr_rtit_status = msrs[i].data;
2530 break;
2531 case MSR_IA32_RTIT_OUTPUT_BASE:
2532 env->msr_rtit_output_base = msrs[i].data;
2533 break;
2534 case MSR_IA32_RTIT_OUTPUT_MASK:
2535 env->msr_rtit_output_mask = msrs[i].data;
2536 break;
2537 case MSR_IA32_RTIT_CR3_MATCH:
2538 env->msr_rtit_cr3_match = msrs[i].data;
2539 break;
2540 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2541 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2542 break;
05330448
AL		 2543 }
2544 }
2545
2546 return 0;
2547}
2548
1bc22652 2549static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2550{
1bc22652 2551 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2552
1bc22652 2553 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2554}
2555
23d02d9b 2556static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2557{
259186a7 2558 CPUState *cs = CPU(cpu);
23d02d9b 2559 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2560 struct kvm_mp_state mp_state;
2561 int ret;
2562
259186a7 2563 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2564 if (ret < 0) {
2565 return ret;
2566 }
2567 env->mp_state = mp_state.mp_state;
c14750e8 2568 if (kvm_irqchip_in_kernel()) {
259186a7 2569 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2570 }
9bdbe550
HB		 2571 return 0;
2572}
2573
1bc22652 2574static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2575{
02e51483 2576 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2577 struct kvm_lapic_state kapic;
2578 int ret;
2579
3d4b2649 2580 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2581 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2582 if (ret < 0) {
2583 return ret;
2584 }
2585
2586 kvm_get_apic_state(apic, &kapic);
2587 }
2588 return 0;
2589}
2590
1bc22652 2591static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2592{
fc12d72e 2593 CPUState *cs = CPU(cpu);
1bc22652 2594 CPUX86State *env = &cpu->env;
076796f8 2595 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2596
2597 if (!kvm_has_vcpu_events()) {
2598 return 0;
2599 }
2600
31827373
JK		 2601 events.exception.injected = (env->exception_injected >= 0);
2602 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2603 events.exception.has_error_code = env->has_error_code;
2604 events.exception.error_code = env->error_code;
7e680753 2605 events.exception.pad = 0;
a0fb002c
JK		 2606
2607 events.interrupt.injected = (env->interrupt_injected >= 0);
2608 events.interrupt.nr = env->interrupt_injected;
2609 events.interrupt.soft = env->soft_interrupt;
2610
2611 events.nmi.injected = env->nmi_injected;
2612 events.nmi.pending = env->nmi_pending;
2613 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2614 events.nmi.pad = 0;
a0fb002c
JK		 2615
2616 events.sipi_vector = env->sipi_vector;
68c6efe0 2617 events.flags = 0;
a0fb002c 2618
fc12d72e
PB		 2619 if (has_msr_smbase) {
2620 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2621 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2622 if (kvm_irqchip_in_kernel()) {
2623 /* As soon as these are moved to the kernel, remove them
2624 * from cs->interrupt_request.
2625 */
2626 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2627 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2628 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2629 } else {
2630 /* Keep these in cs->interrupt_request. */
2631 events.smi.pending = 0;
2632 events.smi.latched_init = 0;
2633 }
fc3a1fd7
DDAG		 2634 /* Stop SMI delivery on old machine types to avoid a reboot
2635 * on an inward migration of an old VM.
2636 */
2637 if (!cpu->kvm_no_smi_migration) {
2638 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2639 }
fc12d72e
PB		 2640 }
2641
ea643051 2642 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2643 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2644 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2645 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2646 }
ea643051 2647 }
aee028b9 2648
1bc22652 2649 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2650}
2651
1bc22652 2652static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2653{
1bc22652 2654 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2655 struct kvm_vcpu_events events;
2656 int ret;
2657
2658 if (!kvm_has_vcpu_events()) {
2659 return 0;
2660 }
2661
fc12d72e 2662 memset(&events, 0, sizeof(events));
1bc22652 2663 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2664 if (ret < 0) {
2665 return ret;
2666 }
31827373 2667 env->exception_injected =
a0fb002c
JK		 2668 events.exception.injected ? events.exception.nr : -1;
2669 env->has_error_code = events.exception.has_error_code;
2670 env->error_code = events.exception.error_code;
2671
2672 env->interrupt_injected =
2673 events.interrupt.injected ? events.interrupt.nr : -1;
2674 env->soft_interrupt = events.interrupt.soft;
2675
2676 env->nmi_injected = events.nmi.injected;
2677 env->nmi_pending = events.nmi.pending;
2678 if (events.nmi.masked) {
2679 env->hflags2 |= HF2_NMI_MASK;
2680 } else {
2681 env->hflags2 &= ~HF2_NMI_MASK;
2682 }
2683
fc12d72e
PB		 2684 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2685 if (events.smi.smm) {
2686 env->hflags |= HF_SMM_MASK;
2687 } else {
2688 env->hflags &= ~HF_SMM_MASK;
2689 }
2690 if (events.smi.pending) {
2691 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2692 } else {
2693 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2694 }
2695 if (events.smi.smm_inside_nmi) {
2696 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2697 } else {
2698 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2699 }
2700 if (events.smi.latched_init) {
2701 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2702 } else {
2703 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2704 }
2705 }
2706
a0fb002c 2707 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2708
2709 return 0;
2710}
2711
1bc22652 2712static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2713{
ed2803da 2714 CPUState *cs = CPU(cpu);
1bc22652 2715 CPUX86State *env = &cpu->env;
b0b1d690 2716 int ret = 0;
b0b1d690
JK		 2717 unsigned long reinject_trap = 0;
2718
2719 if (!kvm_has_vcpu_events()) {
2720 if (env->exception_injected == 1) {
2721 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2722 } else if (env->exception_injected == 3) {
2723 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2724 }
2725 env->exception_injected = -1;
2726 }
2727
2728 /*
2729 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2730 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2731 * by updating the debug state once again if single-stepping is on.
2732 * Another reason to call kvm_update_guest_debug here is a pending debug
2733 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2734 * reinject them via SET_GUEST_DEBUG.
2735 */
2736 if (reinject_trap ||
ed2803da 2737 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2738 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2739 }
b0b1d690
JK		 2740 return ret;
2741}
2742
1bc22652 2743static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2744{
1bc22652 2745 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2746 struct kvm_debugregs dbgregs;
2747 int i;
2748
2749 if (!kvm_has_debugregs()) {
2750 return 0;
2751 }
2752
2753 for (i = 0; i < 4; i++) {
2754 dbgregs.db[i] = env->dr[i];
2755 }
2756 dbgregs.dr6 = env->dr[6];
2757 dbgregs.dr7 = env->dr[7];
2758 dbgregs.flags = 0;
2759
1bc22652 2760 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2761}
2762
1bc22652 2763static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2764{
1bc22652 2765 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2766 struct kvm_debugregs dbgregs;
2767 int i, ret;
2768
2769 if (!kvm_has_debugregs()) {
2770 return 0;
2771 }
2772
1bc22652 2773 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2774 if (ret < 0) {
b9bec74b 2775 return ret;
ff44f1a3
JK		 2776 }
2777 for (i = 0; i < 4; i++) {
2778 env->dr[i] = dbgregs.db[i];
2779 }
2780 env->dr[4] = env->dr[6] = dbgregs.dr6;
2781 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2782
2783 return 0;
2784}
2785
20d695a9 2786int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2787{
20d695a9 2788 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2789 int ret;
2790
2fa45344 2791 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2792
48e1a45c 2793 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2794 ret = kvm_put_msr_feature_control(x86_cpu);
2795 if (ret < 0) {
2796 return ret;
2797 }
2798 }
2799
36f96c4b
HZ		 2800 if (level == KVM_PUT_FULL_STATE) {
2801 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2802 * because TSC frequency mismatch shouldn't abort migration,
2803 * unless the user explicitly asked for a more strict TSC
2804 * setting (e.g. using an explicit "tsc-freq" option).
2805 */
2806 kvm_arch_set_tsc_khz(cpu);
2807 }
2808
1bc22652 2809 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2810 if (ret < 0) {
05330448 2811 return ret;
b9bec74b 2812 }
1bc22652 2813 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2814 if (ret < 0) {
f1665b21 2815 return ret;
b9bec74b 2816 }
1bc22652 2817 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2818 if (ret < 0) {
05330448 2819 return ret;
b9bec74b 2820 }
1bc22652 2821 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2822 if (ret < 0) {
05330448 2823 return ret;
b9bec74b 2824 }
ab443475 2825 /* must be before kvm_put_msrs */
1bc22652 2826 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2827 if (ret < 0) {
2828 return ret;
2829 }
1bc22652 2830 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2831 if (ret < 0) {
05330448 2832 return ret;
b9bec74b 2833 }
4fadfa00
PH		 2834 ret = kvm_put_vcpu_events(x86_cpu, level);
2835 if (ret < 0) {
2836 return ret;
2837 }
ea643051 2838 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2839 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2840 if (ret < 0) {
680c1c6f
JK		 2841 return ret;
2842 }
ea643051 2843 }
7477cd38
MT		 2844
2845 ret = kvm_put_tscdeadline_msr(x86_cpu);
2846 if (ret < 0) {
2847 return ret;
2848 }
1bc22652 2849 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2850 if (ret < 0) {
b0b1d690 2851 return ret;
b9bec74b 2852 }
b0b1d690 2853 /* must be last */
1bc22652 2854 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2855 if (ret < 0) {
ff44f1a3 2856 return ret;
b9bec74b 2857 }
05330448
AL		 2858 return 0;
2859}
2860
20d695a9 2861int kvm_arch_get_registers(CPUState *cs)
05330448 2862{
20d695a9 2863 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2864 int ret;
2865
20d695a9 2866 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2867
4fadfa00 2868 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2869 if (ret < 0) {
f4f1110e 2870 goto out;
b9bec74b 2871 }
4fadfa00
PH		 2872 /*
2873 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2874 * KVM_GET_REGS and KVM_GET_SREGS.
2875 */
2876 ret = kvm_get_mp_state(cpu);
b9bec74b 2877 if (ret < 0) {
f4f1110e 2878 goto out;
b9bec74b 2879 }
4fadfa00 2880 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2881 if (ret < 0) {
f4f1110e 2882 goto out;
b9bec74b 2883 }
4fadfa00 2884 ret = kvm_get_xsave(cpu);
b9bec74b 2885 if (ret < 0) {
f4f1110e 2886 goto out;
b9bec74b 2887 }
4fadfa00 2888 ret = kvm_get_xcrs(cpu);
b9bec74b 2889 if (ret < 0) {
f4f1110e 2890 goto out;
b9bec74b 2891 }
4fadfa00 2892 ret = kvm_get_sregs(cpu);
b9bec74b 2893 if (ret < 0) {
f4f1110e 2894 goto out;
b9bec74b 2895 }
4fadfa00 2896 ret = kvm_get_msrs(cpu);
680c1c6f 2897 if (ret < 0) {
f4f1110e 2898 goto out;
680c1c6f 2899 }
4fadfa00 2900 ret = kvm_get_apic(cpu);
b9bec74b 2901 if (ret < 0) {
f4f1110e 2902 goto out;
b9bec74b 2903 }
1bc22652 2904 ret = kvm_get_debugregs(cpu);
b9bec74b 2905 if (ret < 0) {
f4f1110e 2906 goto out;
b9bec74b 2907 }
f4f1110e
RH		 2908 ret = 0;
2909 out:
2910 cpu_sync_bndcs_hflags(&cpu->env);
2911 return ret;
05330448
AL		 2912}
2913
20d695a9 2914void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2915{
20d695a9
AF		 2916 X86CPU *x86_cpu = X86_CPU(cpu);
2917 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2918 int ret;
2919
276ce815 2920 /* Inject NMI */
fc12d72e
PB		 2921 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2922 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2923 qemu_mutex_lock_iothread();
2924 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2925 qemu_mutex_unlock_iothread();
2926 DPRINTF("injected NMI\n");
2927 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2928 if (ret < 0) {
2929 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2930 strerror(-ret));
2931 }
2932 }
2933 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2934 qemu_mutex_lock_iothread();
2935 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2936 qemu_mutex_unlock_iothread();
2937 DPRINTF("injected SMI\n");
2938 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2939 if (ret < 0) {
2940 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2941 strerror(-ret));
2942 }
ce377af3 2943 }
276ce815
LJ		 2944 }
2945
15eafc2e 2946 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2947 qemu_mutex_lock_iothread();
2948 }
2949
e0723c45
PB		 2950 /* Force the VCPU out of its inner loop to process any INIT requests
2951 * or (for userspace APIC, but it is cheap to combine the checks here)
2952 * pending TPR access reports.
2953 */
2954 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2955 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2956 !(env->hflags & HF_SMM_MASK)) {
2957 cpu->exit_request = 1;
2958 }
2959 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2960 cpu->exit_request = 1;
2961 }
e0723c45 2962 }
05330448 2963
15eafc2e 2964 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2965 /* Try to inject an interrupt if the guest can accept it */
2966 if (run->ready_for_interrupt_injection &&
259186a7 2967 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2968 (env->eflags & IF_MASK)) {
2969 int irq;
2970
259186a7 2971 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2972 irq = cpu_get_pic_interrupt(env);
2973 if (irq >= 0) {
2974 struct kvm_interrupt intr;
2975
2976 intr.irq = irq;
db1669bc 2977 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2978 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2979 if (ret < 0) {
2980 fprintf(stderr,
2981 "KVM: injection failed, interrupt lost (%s)\n",
2982 strerror(-ret));
2983 }
db1669bc
JK		 2984 }
2985 }
05330448 2986
db1669bc
JK		 2987 /* If we have an interrupt but the guest is not ready to receive an
2988 * interrupt, request an interrupt window exit. This will
2989 * cause a return to userspace as soon as the guest is ready to
2990 * receive interrupts. */
259186a7 2991 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2992 run->request_interrupt_window = 1;
2993 } else {
2994 run->request_interrupt_window = 0;
2995 }
2996
2997 DPRINTF("setting tpr\n");
02e51483 2998 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2999
3000 qemu_mutex_unlock_iothread();
db1669bc 3001 }
05330448
AL		 3002}
3003
4c663752 3004MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3005{
20d695a9
AF		 3006 X86CPU *x86_cpu = X86_CPU(cpu);
3007 CPUX86State *env = &x86_cpu->env;
3008
fc12d72e
PB		 3009 if (run->flags & KVM_RUN_X86_SMM) {
3010 env->hflags |= HF_SMM_MASK;
3011 } else {
f5c052b9 3012 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3013 }
b9bec74b 3014 if (run->if_flag) {
05330448 3015 env->eflags |= IF_MASK;
b9bec74b 3016 } else {
05330448 3017 env->eflags &= ~IF_MASK;
b9bec74b 3018 }
4b8523ee
JK		 3019
3020 /* We need to protect the apic state against concurrent accesses from
3021 * different threads in case the userspace irqchip is used. */
3022 if (!kvm_irqchip_in_kernel()) {
3023 qemu_mutex_lock_iothread();
3024 }
02e51483
CF		 3025 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3026 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3027 if (!kvm_irqchip_in_kernel()) {
3028 qemu_mutex_unlock_iothread();
3029 }
f794aa4a 3030 return cpu_get_mem_attrs(env);
05330448
AL		 3031}
3032
20d695a9 3033int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3034{
20d695a9
AF		 3035 X86CPU *cpu = X86_CPU(cs);
3036 CPUX86State *env = &cpu->env;
232fc23b 3037
259186a7 3038 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3039 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3040 assert(env->mcg_cap);
3041
259186a7 3042 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3043
dd1750d7 3044 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3045
3046 if (env->exception_injected == EXCP08_DBLE) {
3047 /* this means triple fault */
cf83f140 3048 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3049 cs->exit_request = 1;
ab443475
JK		 3050 return 0;
3051 }
3052 env->exception_injected = EXCP12_MCHK;
3053 env->has_error_code = 0;
3054
259186a7 3055 cs->halted = 0;
ab443475
JK		 3056 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3057 env->mp_state = KVM_MP_STATE_RUNNABLE;
3058 }
3059 }
3060
fc12d72e
PB		 3061 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3062 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3063 kvm_cpu_synchronize_state(cs);
3064 do_cpu_init(cpu);
3065 }
3066
db1669bc
JK		 3067 if (kvm_irqchip_in_kernel()) {
3068 return 0;
3069 }
3070
259186a7
AF		 3071 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3072 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3073 apic_poll_irq(cpu->apic_state);
5d62c43a 3074 }
259186a7 3075 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3076 (env->eflags & IF_MASK)) ||
259186a7
AF		 3077 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3078 cs->halted = 0;
6792a57b 3079 }
259186a7 3080 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3081 kvm_cpu_synchronize_state(cs);
232fc23b 3082 do_cpu_sipi(cpu);
0af691d7 3083 }
259186a7
AF		 3084 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3085 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3086 kvm_cpu_synchronize_state(cs);
02e51483 3087 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3088 env->tpr_access_type);
3089 }
0af691d7 3090
259186a7 3091 return cs->halted;
0af691d7
MT		 3092}
3093
839b5630 3094static int kvm_handle_halt(X86CPU *cpu)
05330448 3095{
259186a7 3096 CPUState *cs = CPU(cpu);
839b5630
AF		 3097 CPUX86State *env = &cpu->env;
3098
259186a7 3099 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3100 (env->eflags & IF_MASK)) &&
259186a7
AF		 3101 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3102 cs->halted = 1;
bb4ea393 3103 return EXCP_HLT;
05330448
AL		 3104 }
3105
bb4ea393 3106 return 0;
05330448
AL		 3107}
3108
f7575c96 3109static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3110{
f7575c96
AF		 3111 CPUState *cs = CPU(cpu);
3112 struct kvm_run *run = cs->kvm_run;
d362e757 3113
02e51483 3114 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3115 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3116 : TPR_ACCESS_READ);
3117 return 1;
3118}
3119
f17ec444 3120int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3121{
38972938 3122 static const uint8_t int3 = 0xcc;
64bf3f4e 3123
f17ec444
AF		 3124 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3125 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3126 return -EINVAL;
b9bec74b 3127 }
e22a25c9
AL		 3128 return 0;
3129}
3130
f17ec444 3131int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3132{
3133 uint8_t int3;
3134
f17ec444
AF		 3135 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3136 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3137 return -EINVAL;
b9bec74b 3138 }
e22a25c9
AL		 3139 return 0;
3140}
3141
3142static struct {
3143 target_ulong addr;
3144 int len;
3145 int type;
3146} hw_breakpoint[4];
3147
3148static int nb_hw_breakpoint;
3149
3150static int find_hw_breakpoint(target_ulong addr, int len, int type)
3151{
3152 int n;
3153
b9bec74b 3154 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3155 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3156 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3157 return n;
b9bec74b
JK		 3158 }
3159 }
e22a25c9
AL		 3160 return -1;
3161}
3162
3163int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3164 target_ulong len, int type)
3165{
3166 switch (type) {
3167 case GDB_BREAKPOINT_HW:
3168 len = 1;
3169 break;
3170 case GDB_WATCHPOINT_WRITE:
3171 case GDB_WATCHPOINT_ACCESS:
3172 switch (len) {
3173 case 1:
3174 break;
3175 case 2:
3176 case 4:
3177 case 8:
b9bec74b 3178 if (addr & (len - 1)) {
e22a25c9 3179 return -EINVAL;
b9bec74b 3180 }
e22a25c9
AL		 3181 break;
3182 default:
3183 return -EINVAL;
3184 }
3185 break;
3186 default:
3187 return -ENOSYS;
3188 }
3189
b9bec74b 3190 if (nb_hw_breakpoint == 4) {
e22a25c9 3191 return -ENOBUFS;
b9bec74b
JK		 3192 }
3193 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3194 return -EEXIST;
b9bec74b 3195 }
e22a25c9
AL		 3196 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3197 hw_breakpoint[nb_hw_breakpoint].len = len;
3198 hw_breakpoint[nb_hw_breakpoint].type = type;
3199 nb_hw_breakpoint++;
3200
3201 return 0;
3202}
3203
3204int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3205 target_ulong len, int type)
3206{
3207 int n;
3208
3209 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3210 if (n < 0) {
e22a25c9 3211 return -ENOENT;
b9bec74b 3212 }
e22a25c9
AL		 3213 nb_hw_breakpoint--;
3214 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3215
3216 return 0;
3217}
3218
3219void kvm_arch_remove_all_hw_breakpoints(void)
3220{
3221 nb_hw_breakpoint = 0;
3222}
3223
3224static CPUWatchpoint hw_watchpoint;
3225
a60f24b5 3226static int kvm_handle_debug(X86CPU *cpu,
48405526 3227 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3228{
ed2803da 3229 CPUState *cs = CPU(cpu);
a60f24b5 3230 CPUX86State *env = &cpu->env;
f2574737 3231 int ret = 0;
e22a25c9
AL		 3232 int n;
3233
3234 if (arch_info->exception == 1) {
3235 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3236 if (cs->singlestep_enabled) {
f2574737 3237 ret = EXCP_DEBUG;
b9bec74b 3238 }
e22a25c9 3239 } else {
b9bec74b
JK		 3240 for (n = 0; n < 4; n++) {
3241 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3242 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3243 case 0x0:
f2574737 3244 ret = EXCP_DEBUG;
e22a25c9
AL		 3245 break;
3246 case 0x1:
f2574737 3247 ret = EXCP_DEBUG;
ff4700b0 3248 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3249 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3250 hw_watchpoint.flags = BP_MEM_WRITE;
3251 break;
3252 case 0x3:
f2574737 3253 ret = EXCP_DEBUG;
ff4700b0 3254 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3255 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3256 hw_watchpoint.flags = BP_MEM_ACCESS;
3257 break;
3258 }
b9bec74b
JK		 3259 }
3260 }
e22a25c9 3261 }
ff4700b0 3262 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3263 ret = EXCP_DEBUG;
b9bec74b 3264 }
f2574737 3265 if (ret == 0) {
ff4700b0 3266 cpu_synchronize_state(cs);
48405526 3267 assert(env->exception_injected == -1);
b0b1d690 3268
f2574737 3269 /* pass to guest */
48405526
BS		 3270 env->exception_injected = arch_info->exception;
3271 env->has_error_code = 0;
b0b1d690 3272 }
e22a25c9 3273
f2574737 3274 return ret;
e22a25c9
AL		 3275}
3276
20d695a9 3277void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3278{
3279 const uint8_t type_code[] = {
3280 [GDB_BREAKPOINT_HW] = 0x0,
3281 [GDB_WATCHPOINT_WRITE] = 0x1,
3282 [GDB_WATCHPOINT_ACCESS] = 0x3
3283 };
3284 const uint8_t len_code[] = {
3285 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3286 };
3287 int n;
3288
a60f24b5 3289 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3290 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3291 }
e22a25c9
AL		 3292 if (nb_hw_breakpoint > 0) {
3293 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3294 dbg->arch.debugreg[7] = 0x0600;
3295 for (n = 0; n < nb_hw_breakpoint; n++) {
3296 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3297 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3298 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3299 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3300 }
3301 }
3302}
4513d923 3303
2a4dac83
JK		 3304static bool host_supports_vmx(void)
3305{
3306 uint32_t ecx, unused;
3307
3308 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3309 return ecx & CPUID_EXT_VMX;
3310}
3311
3312#define VMX_INVALID_GUEST_STATE 0x80000021
3313
20d695a9 3314int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3315{
20d695a9 3316 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3317 uint64_t code;
3318 int ret;
3319
3320 switch (run->exit_reason) {
3321 case KVM_EXIT_HLT:
3322 DPRINTF("handle_hlt\n");
4b8523ee 3323 qemu_mutex_lock_iothread();
839b5630 3324 ret = kvm_handle_halt(cpu);
4b8523ee 3325 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3326 break;
3327 case KVM_EXIT_SET_TPR:
3328 ret = 0;
3329 break;
d362e757 3330 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3331 qemu_mutex_lock_iothread();
f7575c96 3332 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3333 qemu_mutex_unlock_iothread();
d362e757 3334 break;
2a4dac83
JK		 3335 case KVM_EXIT_FAIL_ENTRY:
3336 code = run->fail_entry.hardware_entry_failure_reason;
3337 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3338 code);
3339 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3340 fprintf(stderr,
12619721 3341 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3342 "unrestricted mode\n"
3343 "support, the failure can be most likely due to the guest "
3344 "entering an invalid\n"
3345 "state for Intel VT. For example, the guest maybe running "
3346 "in big real mode\n"
3347 "which is not supported on less recent Intel processors."
3348 "\n\n");
3349 }
3350 ret = -1;
3351 break;
3352 case KVM_EXIT_EXCEPTION:
3353 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3354 run->ex.exception, run->ex.error_code);
3355 ret = -1;
3356 break;
f2574737
JK		 3357 case KVM_EXIT_DEBUG:
3358 DPRINTF("kvm_exit_debug\n");
4b8523ee 3359 qemu_mutex_lock_iothread();
a60f24b5 3360 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3361 qemu_mutex_unlock_iothread();
f2574737 3362 break;
50efe82c
AS		 3363 case KVM_EXIT_HYPERV:
3364 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3365 break;
15eafc2e
PB		 3366 case KVM_EXIT_IOAPIC_EOI:
3367 ioapic_eoi_broadcast(run->eoi.vector);
3368 ret = 0;
3369 break;
2a4dac83
JK		 3370 default:
3371 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3372 ret = -1;
3373 break;
3374 }
3375
3376 return ret;
3377}
3378
20d695a9 3379bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3380{
20d695a9
AF		 3381 X86CPU *cpu = X86_CPU(cs);
3382 CPUX86State *env = &cpu->env;
3383
dd1750d7 3384 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3385 return !(env->cr[0] & CR0_PE_MASK) ||
3386 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3387}
84b058d7
JK		 3388
3389void kvm_arch_init_irq_routing(KVMState *s)
3390{
3391 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3392 /* If kernel can't do irq routing, interrupt source
3393 * override 0->2 cannot be set up as required by HPET.
3394 * So we have to disable it.
3395 */
3396 no_hpet = 1;
3397 }
cc7e0ddf 3398 /* We know at this point that we're using the in-kernel
614e41bc 3399 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3400 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3401 */
614e41bc 3402 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3403 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3404
3405 if (kvm_irqchip_is_split()) {
3406 int i;
3407
3408 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3409 MSI routes for signaling interrupts to the local apics. */
3410 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3411 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3412 error_report("Could not enable split IRQ mode.");
3413 exit(1);
3414 }
3415 }
3416 }
3417}
3418
3419int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3420{
3421 int ret;
3422 if (machine_kernel_irqchip_split(ms)) {
3423 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3424 if (ret) {
df3c286c 3425 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3426 strerror(-ret));
3427 exit(1);
3428 } else {
3429 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3430 kvm_split_irqchip = true;
3431 return 1;
3432 }
3433 } else {
3434 return 0;
3435 }
84b058d7 3436}
b139bd30
JK		 3437
3438/* Classic KVM device assignment interface. Will remain x86 only. */
3439int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3440 uint32_t flags, uint32_t *dev_id)
3441{
3442 struct kvm_assigned_pci_dev dev_data = {
3443 .segnr = dev_addr->domain,
3444 .busnr = dev_addr->bus,
3445 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3446 .flags = flags,
3447 };
3448 int ret;
3449
3450 dev_data.assigned_dev_id =
3451 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3452
3453 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3454 if (ret < 0) {
3455 return ret;
3456 }
3457
3458 *dev_id = dev_data.assigned_dev_id;
3459
3460 return 0;
3461}
3462
3463int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3464{
3465 struct kvm_assigned_pci_dev dev_data = {
3466 .assigned_dev_id = dev_id,
3467 };
3468
3469 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3470}
3471
3472static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3473 uint32_t irq_type, uint32_t guest_irq)
3474{
3475 struct kvm_assigned_irq assigned_irq = {
3476 .assigned_dev_id = dev_id,
3477 .guest_irq = guest_irq,
3478 .flags = irq_type,
3479 };
3480
3481 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3482 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3483 } else {
3484 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3485 }
3486}
3487
3488int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3489 uint32_t guest_irq)
3490{
3491 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3492 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3493
3494 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3495}
3496
3497int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3498{
3499 struct kvm_assigned_pci_dev dev_data = {
3500 .assigned_dev_id = dev_id,
3501 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3502 };
3503
3504 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3505}
3506
3507static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3508 uint32_t type)
3509{
3510 struct kvm_assigned_irq assigned_irq = {
3511 .assigned_dev_id = dev_id,
3512 .flags = type,
3513 };
3514
3515 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3516}
3517
3518int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3519{
3520 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3521 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3522}
3523
3524int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3525{
3526 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3527 KVM_DEV_IRQ_GUEST_MSI, virq);
3528}
3529
3530int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3531{
3532 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3533 KVM_DEV_IRQ_HOST_MSI);
3534}
3535
3536bool kvm_device_msix_supported(KVMState *s)
3537{
3538 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3539 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3540 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3541}
3542
3543int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3544 uint32_t nr_vectors)
3545{
3546 struct kvm_assigned_msix_nr msix_nr = {
3547 .assigned_dev_id = dev_id,
3548 .entry_nr = nr_vectors,
3549 };
3550
3551 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3552}
3553
3554int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3555 int virq)
3556{
3557 struct kvm_assigned_msix_entry msix_entry = {
3558 .assigned_dev_id = dev_id,
3559 .gsi = virq,
3560 .entry = vector,
3561 };
3562
3563 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3564}
3565
3566int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3567{
3568 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3569 KVM_DEV_IRQ_GUEST_MSIX, 0);
3570}
3571
3572int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3573{
3574 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3575 KVM_DEV_IRQ_HOST_MSIX);
3576}
9e03a040
FB		 3577
3578int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3579 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3580{
8b5ed7df
PX		 3581 X86IOMMUState *iommu = x86_iommu_get_default();
3582
3583 if (iommu) {
3584 int ret;
3585 MSIMessage src, dst;
3586 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3587
3588 src.address = route->u.msi.address_hi;
3589 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3590 src.address |= route->u.msi.address_lo;
3591 src.data = route->u.msi.data;
3592
3593 ret = class->int_remap(iommu, &src, &dst, dev ? \
3594 pci_requester_id(dev) : \
3595 X86_IOMMU_SID_INVALID);
3596 if (ret) {
3597 trace_kvm_x86_fixup_msi_error(route->gsi);
3598 return 1;
3599 }
3600
3601 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3602 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3603 route->u.msi.data = dst.data;
3604 }
3605
9e03a040
FB		 3606 return 0;
3607}
1850b6b7 3608
38d87493
PX		 3609typedef struct MSIRouteEntry MSIRouteEntry;
3610
3611struct MSIRouteEntry {
3612 PCIDevice *dev; /* Device pointer */
3613 int vector; /* MSI/MSIX vector index */
3614 int virq; /* Virtual IRQ index */
3615 QLIST_ENTRY(MSIRouteEntry) list;
3616};
3617
3618/* List of used GSI routes */
3619static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3620 QLIST_HEAD_INITIALIZER(msi_route_list);
3621
e1d4fb2d
PX		 3622static void kvm_update_msi_routes_all(void *private, bool global,
3623 uint32_t index, uint32_t mask)
3624{
3625 int cnt = 0;
3626 MSIRouteEntry *entry;
3627 MSIMessage msg;
fd563564
PX		 3628 PCIDevice *dev;
3629
e1d4fb2d
PX		 3630 /* TODO: explicit route update */
3631 QLIST_FOREACH(entry, &msi_route_list, list) {
3632 cnt++;
fd563564
PX		 3633 dev = entry->dev;
3634 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3635 continue;
3636 }
3637 msg = pci_get_msi_message(dev, entry->vector);
3638 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3639 }
3f1fea0f 3640 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3641 trace_kvm_x86_update_msi_routes(cnt);
3642}
3643
38d87493
PX		 3644int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3645 int vector, PCIDevice *dev)
3646{
e1d4fb2d 3647 static bool notify_list_inited = false;
38d87493
PX		 3648 MSIRouteEntry *entry;
3649
3650 if (!dev) {
3651 /* These are (possibly) IOAPIC routes only used for split
3652 * kernel irqchip mode, while what we are housekeeping are
3653 * PCI devices only. */
3654 return 0;
3655 }
3656
3657 entry = g_new0(MSIRouteEntry, 1);
3658 entry->dev = dev;
3659 entry->vector = vector;
3660 entry->virq = route->gsi;
3661 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3662
3663 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3664
3665 if (!notify_list_inited) {
3666 /* For the first time we do add route, add ourselves into
3667 * IOMMU's IEC notify list if needed. */
3668 X86IOMMUState *iommu = x86_iommu_get_default();
3669 if (iommu) {
3670 x86_iommu_iec_register_notifier(iommu,
3671 kvm_update_msi_routes_all,
3672 NULL);
3673 }
3674 notify_list_inited = true;
3675 }
38d87493
PX		 3676 return 0;
3677}
3678
3679int kvm_arch_release_virq_post(int virq)
3680{
3681 MSIRouteEntry *entry, *next;
3682 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3683 if (entry->virq == virq) {
3684 trace_kvm_x86_remove_msi_route(virq);
3685 QLIST_REMOVE(entry, list);
01960e6d 3686 g_free(entry);
38d87493
PX		 3687 break;
3688 }
3689 }
9e03a040
FB		 3690 return 0;
3691}
1850b6b7
EA		 3692
3693int kvm_arch_msi_data_to_gsi(uint32_t data)
3694{
3695 abort();
3696}
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