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hyperv: rename vcpu_id to vp_index
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
a2cb15b0 43#include "hw/pci/pci.h"
15eafc2e 44#include "hw/pci/msi.h"
fd563564 45#include "hw/pci/msix.h"
795c40b8 46#include "migration/blocker.h"
4c663752 47#include "exec/memattrs.h"
8b5ed7df 48#include "trace.h"
05330448
AL		 49
50//#define DEBUG_KVM
51
52#ifdef DEBUG_KVM
8c0d577e 53#define DPRINTF(fmt, ...) \
05330448
AL		 54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55#else
8c0d577e 56#define DPRINTF(fmt, ...) \
05330448
AL		 57 do { } while (0)
58#endif
59
1a03675d
GC		 60#define MSR_KVM_WALL_CLOCK 0x11
61#define MSR_KVM_SYSTEM_TIME 0x12
62
d1138251
EH		 63/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65#define MSR_BUF_SIZE 4096
d71b62a1 66
94a8d39a
JK		 67const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72};
25d2e361 73
c3a3a7d3
JK		 74static bool has_msr_star;
75static bool has_msr_hsave_pa;
c9b8f6b6 76static bool has_msr_tsc_aux;
f28558d3 77static bool has_msr_tsc_adjust;
aa82ba54 78static bool has_msr_tsc_deadline;
df67696e 79static bool has_msr_feature_control;
21e87c46 80static bool has_msr_misc_enable;
fc12d72e 81static bool has_msr_smbase;
79e9ebeb 82static bool has_msr_bndcfgs;
25d2e361 83static int lm_capable_kernel;
7bc3d711 84static bool has_msr_hv_hypercall;
f2a53c9e 85static bool has_msr_hv_crash;
744b8a94 86static bool has_msr_hv_reset;
8c145d7c 87static bool has_msr_hv_vpindex;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
b827df58 97
0b368a10
JD		 98static uint32_t has_architectural_pmu_version;
99static uint32_t num_architectural_pmu_gp_counters;
100static uint32_t num_architectural_pmu_fixed_counters;
0d894367 101
28143b40
TH		 102static int has_xsave;
103static int has_xcrs;
104static int has_pit_state2;
105
87f8b626
AR		 106static bool has_msr_mcg_ext_ctl;
107
494e95e9
CP		 108static struct kvm_cpuid2 *cpuid_cache;
109
28143b40
TH		 110int kvm_has_pit_state2(void)
111{
112 return has_pit_state2;
113}
114
355023f2
PB		 115bool kvm_has_smm(void)
116{
117 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
118}
119
6053a86f
MT		 120bool kvm_has_adjust_clock_stable(void)
121{
122 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
123
124 return (ret == KVM_CLOCK_TSC_STABLE);
125}
126
1d31f66b
PM		 127bool kvm_allows_irq0_override(void)
128{
129 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
130}
131
fb506e70
RK		 132static bool kvm_x2apic_api_set_flags(uint64_t flags)
133{
134 KVMState *s = KVM_STATE(current_machine->accelerator);
135
136 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
137}
138
e391c009 139#define MEMORIZE(fn, _result) \
2a138ec3 140 ({ \
2a138ec3
RK		 141 static bool _memorized; \
142 \
143 if (_memorized) { \
144 return _result; \
145 } \
146 _memorized = true; \
147 _result = fn; \
148 })
149
e391c009
IM		 150static bool has_x2apic_api;
151
152bool kvm_has_x2apic_api(void)
153{
154 return has_x2apic_api;
155}
156
fb506e70
RK		 157bool kvm_enable_x2apic(void)
158{
2a138ec3
RK		 159 return MEMORIZE(
160 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 161 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
162 has_x2apic_api);
fb506e70
RK		 163}
164
0fd7e098
LL		 165static int kvm_get_tsc(CPUState *cs)
166{
167 X86CPU *cpu = X86_CPU(cs);
168 CPUX86State *env = &cpu->env;
169 struct {
170 struct kvm_msrs info;
171 struct kvm_msr_entry entries[1];
172 } msr_data;
173 int ret;
174
175 if (env->tsc_valid) {
176 return 0;
177 }
178
179 msr_data.info.nmsrs = 1;
180 msr_data.entries[0].index = MSR_IA32_TSC;
181 env->tsc_valid = !runstate_is_running();
182
183 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
184 if (ret < 0) {
185 return ret;
186 }
187
48e1a45c 188 assert(ret == 1);
0fd7e098
LL		 189 env->tsc = msr_data.entries[0].data;
190 return 0;
191}
192
14e6fe12 193static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 194{
0fd7e098
LL		 195 kvm_get_tsc(cpu);
196}
197
198void kvm_synchronize_all_tsc(void)
199{
200 CPUState *cpu;
201
202 if (kvm_enabled()) {
203 CPU_FOREACH(cpu) {
14e6fe12 204 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 205 }
206 }
207}
208
b827df58
AK		 209static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
210{
211 struct kvm_cpuid2 *cpuid;
212 int r, size;
213
214 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 215 cpuid = g_malloc0(size);
b827df58
AK		 216 cpuid->nent = max;
217 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 218 if (r == 0 && cpuid->nent >= max) {
219 r = -E2BIG;
220 }
b827df58
AK		 221 if (r < 0) {
222 if (r == -E2BIG) {
7267c094 223 g_free(cpuid);
b827df58
AK		 224 return NULL;
225 } else {
226 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
227 strerror(-r));
228 exit(1);
229 }
230 }
231 return cpuid;
232}
233
dd87f8a6
EH		 234/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
235 * for all entries.
236 */
237static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
238{
239 struct kvm_cpuid2 *cpuid;
240 int max = 1;
494e95e9
CP		 241
242 if (cpuid_cache != NULL) {
243 return cpuid_cache;
244 }
dd87f8a6
EH		 245 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
246 max *= 2;
247 }
494e95e9 248 cpuid_cache = cpuid;
dd87f8a6
EH		 249 return cpuid;
250}
251
a443bc34 252static const struct kvm_para_features {
0c31b744
GC		 253 int cap;
254 int feature;
255} para_features[] = {
256 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
257 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
258 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 259 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 260};
261
ba9bc59e 262static int get_para_features(KVMState *s)
0c31b744
GC		 263{
264 int i, features = 0;
265
8e03c100 266 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 267 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 268 features |= (1 << para_features[i].feature);
269 }
270 }
271
272 return features;
273}
0c31b744 274
40e80ee4
EH		 275static bool host_tsx_blacklisted(void)
276{
277 int family, model, stepping;\
278 char vendor[CPUID_VENDOR_SZ + 1];
279
280 host_vendor_fms(vendor, &family, &model, &stepping);
281
282 /* Check if we are running on a Haswell host known to have broken TSX */
283 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
284 (family == 6) &&
285 ((model == 63 && stepping < 4) ||
286 model == 60 || model == 69 || model == 70);
287}
0c31b744 288
829ae2f9
EH		 289/* Returns the value for a specific register on the cpuid entry
290 */
291static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
292{
293 uint32_t ret = 0;
294 switch (reg) {
295 case R_EAX:
296 ret = entry->eax;
297 break;
298 case R_EBX:
299 ret = entry->ebx;
300 break;
301 case R_ECX:
302 ret = entry->ecx;
303 break;
304 case R_EDX:
305 ret = entry->edx;
306 break;
307 }
308 return ret;
309}
310
4fb73f1d
EH		 311/* Find matching entry for function/index on kvm_cpuid2 struct
312 */
313static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
314 uint32_t function,
315 uint32_t index)
316{
317 int i;
318 for (i = 0; i < cpuid->nent; ++i) {
319 if (cpuid->entries[i].function == function &&
320 cpuid->entries[i].index == index) {
321 return &cpuid->entries[i];
322 }
323 }
324 /* not found: */
325 return NULL;
326}
327
ba9bc59e 328uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 329 uint32_t index, int reg)
b827df58
AK		 330{
331 struct kvm_cpuid2 *cpuid;
b827df58
AK		 332 uint32_t ret = 0;
333 uint32_t cpuid_1_edx;
8c723b79 334 bool found = false;
b827df58 335
dd87f8a6 336 cpuid = get_supported_cpuid(s);
b827df58 337
4fb73f1d
EH		 338 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
339 if (entry) {
340 found = true;
341 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 342 }
343
7b46e5ce
EH		 344 /* Fixups for the data returned by KVM, below */
345
c2acb022
EH		 346 if (function == 1 && reg == R_EDX) {
347 /* KVM before 2.6.30 misreports the following features */
348 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 349 } else if (function == 1 && reg == R_ECX) {
350 /* We can set the hypervisor flag, even if KVM does not return it on
351 * GET_SUPPORTED_CPUID
352 */
353 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 354 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
355 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
356 * and the irqchip is in the kernel.
357 */
358 if (kvm_irqchip_in_kernel() &&
359 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
360 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
361 }
41e5e76d
EH		 362
363 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
364 * without the in-kernel irqchip
365 */
366 if (!kvm_irqchip_in_kernel()) {
367 ret &= ~CPUID_EXT_X2APIC;
b827df58 368 }
2266d443
MT		 369
370 if (enable_cpu_pm) {
371 int disable_exits = kvm_check_extension(s,
372 KVM_CAP_X86_DISABLE_EXITS);
373
374 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
375 ret |= CPUID_EXT_MONITOR;
376 }
377 }
28b8e4d0
JK		 378 } else if (function == 6 && reg == R_EAX) {
379 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 380 } else if (function == 7 && index == 0 && reg == R_EBX) {
381 if (host_tsx_blacklisted()) {
382 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
383 }
f98bbd83
BM		 384 } else if (function == 0x80000001 && reg == R_ECX) {
385 /*
386 * It's safe to enable TOPOEXT even if it's not returned by
387 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
388 * us to keep CPU models including TOPOEXT runnable on older kernels.
389 */
390 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 391 } else if (function == 0x80000001 && reg == R_EDX) {
392 /* On Intel, kvm returns cpuid according to the Intel spec,
393 * so add missing bits according to the AMD spec:
394 */
395 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
396 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 397 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
398 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
399 * be enabled without the in-kernel irqchip
400 */
401 if (!kvm_irqchip_in_kernel()) {
402 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
403 }
be777326 404 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 405 ret |= 1U << KVM_HINTS_REALTIME;
be777326 406 found = 1;
b827df58
AK		 407 }
408
0c31b744 409 /* fallback for older kernels */
8c723b79 410 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 411 ret = get_para_features(s);
b9bec74b 412 }
0c31b744
GC		 413
414 return ret;
bb0300dc 415}
bb0300dc 416
3c85e74f
HY		 417typedef struct HWPoisonPage {
418 ram_addr_t ram_addr;
419 QLIST_ENTRY(HWPoisonPage) list;
420} HWPoisonPage;
421
422static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
423 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
424
425static void kvm_unpoison_all(void *param)
426{
427 HWPoisonPage *page, *next_page;
428
429 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
430 QLIST_REMOVE(page, list);
431 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 432 g_free(page);
3c85e74f
HY		 433 }
434}
435
3c85e74f
HY		 436static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
437{
438 HWPoisonPage *page;
439
440 QLIST_FOREACH(page, &hwpoison_page_list, list) {
441 if (page->ram_addr == ram_addr) {
442 return;
443 }
444 }
ab3ad07f 445 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 446 page->ram_addr = ram_addr;
447 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
448}
449
e7701825
MT		 450static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
451 int *max_banks)
452{
453 int r;
454
14a09518 455 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 456 if (r > 0) {
457 *max_banks = r;
458 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
459 }
460 return -ENOSYS;
461}
462
bee615d4 463static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 464{
87f8b626 465 CPUState *cs = CPU(cpu);
bee615d4 466 CPUX86State *env = &cpu->env;
c34d440a
JK		 467 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
468 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
469 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 470 int flags = 0;
e7701825 471
c34d440a
JK		 472 if (code == BUS_MCEERR_AR) {
473 status |= MCI_STATUS_AR | 0x134;
474 mcg_status |= MCG_STATUS_EIPV;
475 } else {
476 status |= 0xc0;
477 mcg_status |= MCG_STATUS_RIPV;
419fb20a 478 }
87f8b626
AR		 479
480 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
481 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
482 * guest kernel back into env->mcg_ext_ctl.
483 */
484 cpu_synchronize_state(cs);
485 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
486 mcg_status |= MCG_STATUS_LMCE;
487 flags = 0;
488 }
489
8c5cf3b6 490 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 491 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 492}
419fb20a
JK		 493
494static void hardware_memory_error(void)
495{
496 fprintf(stderr, "Hardware memory error!\n");
497 exit(1);
498}
499
2ae41db2 500void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 501{
20d695a9
AF		 502 X86CPU *cpu = X86_CPU(c);
503 CPUX86State *env = &cpu->env;
419fb20a 504 ram_addr_t ram_addr;
a8170e5e 505 hwaddr paddr;
419fb20a 506
4d39892c
PB		 507 /* If we get an action required MCE, it has been injected by KVM
508 * while the VM was running. An action optional MCE instead should
509 * be coming from the main thread, which qemu_init_sigbus identifies
510 * as the "early kill" thread.
511 */
a16fc07e 512 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 513
20e0ff59 514 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 515 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 516 if (ram_addr != RAM_ADDR_INVALID &&
517 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
518 kvm_hwpoison_page_add(ram_addr);
519 kvm_mce_inject(cpu, paddr, code);
2ae41db2 520 return;
419fb20a 521 }
20e0ff59
PB		 522
523 fprintf(stderr, "Hardware memory error for memory used by "
524 "QEMU itself instead of guest system!\n");
419fb20a 525 }
20e0ff59
PB		 526
527 if (code == BUS_MCEERR_AR) {
528 hardware_memory_error();
529 }
530
531 /* Hope we are lucky for AO MCE */
419fb20a
JK		 532}
533
1bc22652 534static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 535{
1bc22652
AF		 536 CPUX86State *env = &cpu->env;
537
ab443475
JK		 538 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
539 unsigned int bank, bank_num = env->mcg_cap & 0xff;
540 struct kvm_x86_mce mce;
541
542 env->exception_injected = -1;
543
544 /*
545 * There must be at least one bank in use if an MCE is pending.
546 * Find it and use its values for the event injection.
547 */
548 for (bank = 0; bank < bank_num; bank++) {
549 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
550 break;
551 }
552 }
553 assert(bank < bank_num);
554
555 mce.bank = bank;
556 mce.status = env->mce_banks[bank * 4 + 1];
557 mce.mcg_status = env->mcg_status;
558 mce.addr = env->mce_banks[bank * 4 + 2];
559 mce.misc = env->mce_banks[bank * 4 + 3];
560
1bc22652 561 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 562 }
ab443475
JK		 563 return 0;
564}
565
1dfb4dd9 566static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 567{
317ac620 568 CPUX86State *env = opaque;
b8cc45d6
GC		 569
570 if (running) {
571 env->tsc_valid = false;
572 }
573}
574
83b17af5 575unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 576{
83b17af5 577 X86CPU *cpu = X86_CPU(cs);
7e72a45c 578 return cpu->apic_id;
b164e48e
EH		 579}
580
92067bf4
IM		 581#ifndef KVM_CPUID_SIGNATURE_NEXT
582#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
583#endif
584
585static bool hyperv_hypercall_available(X86CPU *cpu)
586{
587 return cpu->hyperv_vapic ||
588 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
589}
590
591static bool hyperv_enabled(X86CPU *cpu)
592{
7bc3d711
PB		 593 CPUState *cs = CPU(cpu);
594 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
595 (hyperv_hypercall_available(cpu) ||
48a5f3bc 596 cpu->hyperv_time ||
f2a53c9e 597 cpu->hyperv_relaxed_timing ||
744b8a94 598 cpu->hyperv_crash ||
8c145d7c 599 cpu->hyperv_reset ||
46eb8f98 600 cpu->hyperv_vpindex ||
866eea9a 601 cpu->hyperv_runtime ||
ff99aa64 602 cpu->hyperv_synic ||
ba6a4fd9 603 cpu->hyperv_stimer ||
47512009
VK		 604 cpu->hyperv_reenlightenment ||
605 cpu->hyperv_tlbflush);
92067bf4
IM		 606}
607
5031283d
HZ		 608static int kvm_arch_set_tsc_khz(CPUState *cs)
609{
610 X86CPU *cpu = X86_CPU(cs);
611 CPUX86State *env = &cpu->env;
612 int r;
613
614 if (!env->tsc_khz) {
615 return 0;
616 }
617
618 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
619 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
620 -ENOTSUP;
621 if (r < 0) {
622 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
623 * TSC frequency doesn't match the one we want.
624 */
625 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
626 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
627 -ENOTSUP;
628 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 629 warn_report("TSC frequency mismatch between "
630 "VM (%" PRId64 " kHz) and host (%d kHz), "
631 "and TSC scaling unavailable",
632 env->tsc_khz, cur_freq);
5031283d
HZ		 633 return r;
634 }
635 }
636
637 return 0;
638}
639
4bb95b82
LP		 640static bool tsc_is_stable_and_known(CPUX86State *env)
641{
642 if (!env->tsc_khz) {
643 return false;
644 }
645 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
646 || env->user_tsc_khz;
647}
648
c35bd19a
EY		 649static int hyperv_handle_properties(CPUState *cs)
650{
651 X86CPU *cpu = X86_CPU(cs);
652 CPUX86State *env = &cpu->env;
653
654 if (cpu->hyperv_relaxed_timing) {
5e953812 655 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 656 }
657 if (cpu->hyperv_vapic) {
5e953812
RK		 658 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
659 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 660 }
3ddcd2ed 661 if (cpu->hyperv_time) {
1221f150
RK		 662 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
663 fprintf(stderr, "Hyper-V clocksources "
664 "(requested by 'hv-time' cpu flag) "
665 "are not supported by kernel\n");
666 return -ENOSYS;
667 }
5e953812
RK		 668 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
669 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
670 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
9445597b
RK		 671 }
672 if (cpu->hyperv_frequencies) {
673 if (!has_msr_hv_frequencies) {
674 fprintf(stderr, "Hyper-V frequency MSRs "
675 "(requested by 'hv-frequencies' cpu flag) "
676 "are not supported by kernel\n");
677 return -ENOSYS;
d72bc7f6 678 }
9445597b
RK		 679 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
680 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 681 }
1221f150
RK		 682 if (cpu->hyperv_crash) {
683 if (!has_msr_hv_crash) {
684 fprintf(stderr, "Hyper-V crash MSRs "
685 "(requested by 'hv-crash' cpu flag) "
686 "are not supported by kernel\n");
687 return -ENOSYS;
688 }
5e953812 689 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 690 }
ba6a4fd9
VK		 691 if (cpu->hyperv_reenlightenment) {
692 if (!has_msr_hv_reenlightenment) {
693 fprintf(stderr,
694 "Hyper-V Reenlightenment MSRs "
695 "(requested by 'hv-reenlightenment' cpu flag) "
696 "are not supported by kernel\n");
697 return -ENOSYS;
698 }
699 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
700 }
5e953812 701 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1221f150
RK		 702 if (cpu->hyperv_reset) {
703 if (!has_msr_hv_reset) {
704 fprintf(stderr, "Hyper-V reset MSR "
705 "(requested by 'hv-reset' cpu flag) "
706 "is not supported by kernel\n");
707 return -ENOSYS;
708 }
5e953812 709 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a 710 }
1221f150
RK		 711 if (cpu->hyperv_vpindex) {
712 if (!has_msr_hv_vpindex) {
713 fprintf(stderr, "Hyper-V VP_INDEX MSR "
714 "(requested by 'hv-vpindex' cpu flag) "
715 "is not supported by kernel\n");
716 return -ENOSYS;
717 }
5e953812 718 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a 719 }
1221f150
RK		 720 if (cpu->hyperv_runtime) {
721 if (!has_msr_hv_runtime) {
722 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
723 "(requested by 'hv-runtime' cpu flag) "
724 "is not supported by kernel\n");
725 return -ENOSYS;
726 }
5e953812 727 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 728 }
729 if (cpu->hyperv_synic) {
c35bd19a
EY		 730 if (!has_msr_hv_synic ||
731 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
732 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
733 return -ENOSYS;
734 }
735
5e953812 736 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a
EY		 737 }
738 if (cpu->hyperv_stimer) {
739 if (!has_msr_hv_stimer) {
740 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
741 return -ENOSYS;
742 }
5e953812 743 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a
EY		 744 }
745 return 0;
746}
747
68bfd0ad
MT		 748static Error *invtsc_mig_blocker;
749
f8bb0565 750#define KVM_MAX_CPUID_ENTRIES 100
0893d460 751
20d695a9 752int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 753{
754 struct {
486bd5a2 755 struct kvm_cpuid2 cpuid;
f8bb0565 756 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 757 } QEMU_PACKED cpuid_data;
20d695a9
AF		 758 X86CPU *cpu = X86_CPU(cs);
759 CPUX86State *env = &cpu->env;
486bd5a2 760 uint32_t limit, i, j, cpuid_i;
a33609ca 761 uint32_t unused;
bb0300dc 762 struct kvm_cpuid_entry2 *c;
bb0300dc 763 uint32_t signature[3];
234cc647 764 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 765 int r;
fe44dc91 766 Error *local_err = NULL;
05330448 767
ef4cbe14
SW		 768 memset(&cpuid_data, 0, sizeof(cpuid_data));
769
05330448
AL		 770 cpuid_i = 0;
771
ddb98b5a
LP		 772 r = kvm_arch_set_tsc_khz(cs);
773 if (r < 0) {
774 goto fail;
775 }
776
777 /* vcpu's TSC frequency is either specified by user, or following
778 * the value used by KVM if the former is not present. In the
779 * latter case, we query it from KVM and record in env->tsc_khz,
780 * so that vcpu's TSC frequency can be migrated later via this field.
781 */
782 if (!env->tsc_khz) {
783 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
784 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
785 -ENOTSUP;
786 if (r > 0) {
787 env->tsc_khz = r;
788 }
789 }
790
bb0300dc 791 /* Paravirtualization CPUIDs */
234cc647
PB		 792 if (hyperv_enabled(cpu)) {
793 c = &cpuid_data.entries[cpuid_i++];
5e953812 794 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 795 if (!cpu->hyperv_vendor_id) {
796 memcpy(signature, "Microsoft Hv", 12);
797 } else {
798 size_t len = strlen(cpu->hyperv_vendor_id);
799
800 if (len > 12) {
801 error_report("hv-vendor-id truncated to 12 characters");
802 len = 12;
803 }
804 memset(signature, 0, 12);
805 memcpy(signature, cpu->hyperv_vendor_id, len);
806 }
5e953812 807 c->eax = HV_CPUID_MIN;
234cc647
PB		 808 c->ebx = signature[0];
809 c->ecx = signature[1];
810 c->edx = signature[2];
0c31b744 811
234cc647 812 c = &cpuid_data.entries[cpuid_i++];
5e953812 813 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 814 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
815 c->eax = signature[0];
234cc647
PB		 816 c->ebx = 0;
817 c->ecx = 0;
818 c->edx = 0;
eab70139
VR		 819
820 c = &cpuid_data.entries[cpuid_i++];
5e953812 821 c->function = HV_CPUID_VERSION;
eab70139
VR		 822 c->eax = 0x00001bbc;
823 c->ebx = 0x00060001;
824
825 c = &cpuid_data.entries[cpuid_i++];
5e953812 826 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 827 r = hyperv_handle_properties(cs);
828 if (r) {
829 return r;
46eb8f98 830 }
c35bd19a
EY		 831 c->eax = env->features[FEAT_HYPERV_EAX];
832 c->ebx = env->features[FEAT_HYPERV_EBX];
833 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 834
eab70139 835 c = &cpuid_data.entries[cpuid_i++];
5e953812 836 c->function = HV_CPUID_ENLIGHTMENT_INFO;
92067bf4 837 if (cpu->hyperv_relaxed_timing) {
5e953812 838 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
eab70139 839 }
2d5aa872 840 if (cpu->hyperv_vapic) {
5e953812 841 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
eab70139 842 }
47512009
VK		 843 if (cpu->hyperv_tlbflush) {
844 if (kvm_check_extension(cs->kvm_state,
845 KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
846 fprintf(stderr, "Hyper-V TLB flush support "
847 "(requested by 'hv-tlbflush' cpu flag) "
848 " is not supported by kernel\n");
849 return -ENOSYS;
850 }
851 c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
852 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
853 }
854
92067bf4 855 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 856
857 c = &cpuid_data.entries[cpuid_i++];
5e953812 858 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 859
860 c->eax = cpu->hv_max_vps;
eab70139
VR		 861 c->ebx = 0x40;
862
234cc647 863 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 864 has_msr_hv_hypercall = true;
eab70139
VR		 865 }
866
f522d2ac
AW		 867 if (cpu->expose_kvm) {
868 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
869 c = &cpuid_data.entries[cpuid_i++];
870 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 871 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 872 c->ebx = signature[0];
873 c->ecx = signature[1];
874 c->edx = signature[2];
234cc647 875
f522d2ac
AW		 876 c = &cpuid_data.entries[cpuid_i++];
877 c->function = KVM_CPUID_FEATURES | kvm_base;
878 c->eax = env->features[FEAT_KVM];
be777326 879 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 880 }
917367aa 881
a33609ca 882 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 883
884 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 885 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
886 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
887 abort();
888 }
bb0300dc 889 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 890
891 switch (i) {
a36b1029
AL		 892 case 2: {
893 /* Keep reading function 2 till all the input is received */
894 int times;
895
a36b1029 896 c->function = i;
a33609ca
AL		 897 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
898 KVM_CPUID_FLAG_STATE_READ_NEXT;
899 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
900 times = c->eax & 0xff;
a36b1029
AL		 901
902 for (j = 1; j < times; ++j) {
f8bb0565
IM		 903 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
904 fprintf(stderr, "cpuid_data is full, no space for "
905 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
906 abort();
907 }
a33609ca 908 c = &cpuid_data.entries[cpuid_i++];
a36b1029 909 c->function = i;
a33609ca
AL		 910 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
911 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 912 }
913 break;
914 }
486bd5a2
AL		 915 case 4:
916 case 0xb:
917 case 0xd:
918 for (j = 0; ; j++) {
31e8c696
AP		 919 if (i == 0xd && j == 64) {
920 break;
921 }
486bd5a2
AL		 922 c->function = i;
923 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
924 c->index = j;
a33609ca 925 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 926
b9bec74b 927 if (i == 4 && c->eax == 0) {
486bd5a2 928 break;
b9bec74b
JK		 929 }
930 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 931 break;
b9bec74b
JK		 932 }
933 if (i == 0xd && c->eax == 0) {
31e8c696 934 continue;
b9bec74b 935 }
f8bb0565
IM		 936 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
937 fprintf(stderr, "cpuid_data is full, no space for "
938 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
939 abort();
940 }
a33609ca 941 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 942 }
943 break;
e37a5c7f
CP		 944 case 0x14: {
945 uint32_t times;
946
947 c->function = i;
948 c->index = 0;
949 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
950 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
951 times = c->eax;
952
953 for (j = 1; j <= times; ++j) {
954 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
955 fprintf(stderr, "cpuid_data is full, no space for "
956 "cpuid(eax:0x14,ecx:0x%x)\n", j);
957 abort();
958 }
959 c = &cpuid_data.entries[cpuid_i++];
960 c->function = i;
961 c->index = j;
962 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
963 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
964 }
965 break;
966 }
486bd5a2 967 default:
486bd5a2 968 c->function = i;
a33609ca
AL		 969 c->flags = 0;
970 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 971 break;
972 }
05330448 973 }
0d894367
PB		 974
975 if (limit >= 0x0a) {
0b368a10 976 uint32_t eax, edx;
0d894367 977
0b368a10
JD		 978 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
979
980 has_architectural_pmu_version = eax & 0xff;
981 if (has_architectural_pmu_version > 0) {
982 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 983
984 /* Shouldn't be more than 32, since that's the number of bits
985 * available in EBX to tell us _which_ counters are available.
986 * Play it safe.
987 */
0b368a10
JD		 988 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
989 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
990 }
991
992 if (has_architectural_pmu_version > 1) {
993 num_architectural_pmu_fixed_counters = edx & 0x1f;
994
995 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
996 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
997 }
0d894367
PB		 998 }
999 }
1000 }
1001
a33609ca 1002 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1003
1004 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1005 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1006 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1007 abort();
1008 }
bb0300dc 1009 c = &cpuid_data.entries[cpuid_i++];
05330448 1010
8f4202fb
BM		 1011 switch (i) {
1012 case 0x8000001d:
1013 /* Query for all AMD cache information leaves */
1014 for (j = 0; ; j++) {
1015 c->function = i;
1016 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1017 c->index = j;
1018 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1019
1020 if (c->eax == 0) {
1021 break;
1022 }
1023 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1024 fprintf(stderr, "cpuid_data is full, no space for "
1025 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1026 abort();
1027 }
1028 c = &cpuid_data.entries[cpuid_i++];
1029 }
1030 break;
1031 default:
1032 c->function = i;
1033 c->flags = 0;
1034 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1035 break;
1036 }
05330448
AL		 1037 }
1038
b3baa152
BW		 1039 /* Call Centaur's CPUID instructions they are supported. */
1040 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1041 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1042
1043 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1044 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1045 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1046 abort();
1047 }
b3baa152
BW		 1048 c = &cpuid_data.entries[cpuid_i++];
1049
1050 c->function = i;
1051 c->flags = 0;
1052 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1053 }
1054 }
1055
05330448
AL		 1056 cpuid_data.cpuid.nent = cpuid_i;
1057
e7701825 1058 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1059 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1060 (CPUID_MCE | CPUID_MCA)
a60f24b5 1061 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1062 uint64_t mcg_cap, unsupported_caps;
e7701825 1063 int banks;
32a42024 1064 int ret;
e7701825 1065
a60f24b5 1066 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1067 if (ret < 0) {
1068 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1069 return ret;
e7701825 1070 }
75d49497 1071
2590f15b 1072 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1073 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1074 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1075 return -ENOTSUP;
75d49497 1076 }
49b69cbf 1077
5120901a
EH		 1078 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1079 if (unsupported_caps) {
87f8b626
AR		 1080 if (unsupported_caps & MCG_LMCE_P) {
1081 error_report("kvm: LMCE not supported");
1082 return -ENOTSUP;
1083 }
3dc6f869
AF		 1084 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1085 unsupported_caps);
5120901a
EH		 1086 }
1087
2590f15b
EH		 1088 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1089 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1090 if (ret < 0) {
1091 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1092 return ret;
1093 }
e7701825 1094 }
e7701825 1095
b8cc45d6
GC		 1096 qemu_add_vm_change_state_handler(cpu_update_state, env);
1097
df67696e
LJ		 1098 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1099 if (c) {
1100 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1101 !!(c->ecx & CPUID_EXT_SMX);
1102 }
1103
87f8b626
AR		 1104 if (env->mcg_cap & MCG_LMCE_P) {
1105 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1106 }
1107
d99569d9
EH		 1108 if (!env->user_tsc_khz) {
1109 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1110 invtsc_mig_blocker == NULL) {
1111 /* for migration */
1112 error_setg(&invtsc_mig_blocker,
1113 "State blocked by non-migratable CPU device"
1114 " (invtsc flag)");
fe44dc91
AA		 1115 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1116 if (local_err) {
1117 error_report_err(local_err);
1118 error_free(invtsc_mig_blocker);
1119 goto fail;
1120 }
d99569d9
EH		 1121 /* for savevm */
1122 vmstate_x86_cpu.unmigratable = 1;
1123 }
68bfd0ad
MT		 1124 }
1125
9954a158
PDJ		 1126 if (cpu->vmware_cpuid_freq
1127 /* Guests depend on 0x40000000 to detect this feature, so only expose
1128 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1129 && cpu->expose_kvm
1130 && kvm_base == KVM_CPUID_SIGNATURE
1131 /* TSC clock must be stable and known for this feature. */
4bb95b82 1132 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1133
1134 c = &cpuid_data.entries[cpuid_i++];
1135 c->function = KVM_CPUID_SIGNATURE | 0x10;
1136 c->eax = env->tsc_khz;
1137 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1138 * APIC_BUS_CYCLE_NS */
1139 c->ebx = 1000000;
1140 c->ecx = c->edx = 0;
1141
1142 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1143 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1144 }
1145
1146 cpuid_data.cpuid.nent = cpuid_i;
1147
1148 cpuid_data.cpuid.padding = 0;
1149 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1150 if (r) {
1151 goto fail;
1152 }
1153
28143b40 1154 if (has_xsave) {
fabacc0f
JK		 1155 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1156 }
d71b62a1 1157 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1158
273c515c
PB		 1159 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1160 has_msr_tsc_aux = false;
1161 }
d1ae67f6 1162
e7429073 1163 return 0;
fe44dc91
AA		 1164
1165 fail:
1166 migrate_del_blocker(invtsc_mig_blocker);
1167 return r;
05330448
AL		 1168}
1169
50a2c6e5 1170void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1171{
20d695a9 1172 CPUX86State *env = &cpu->env;
dd673288 1173
1a5e9d2f 1174 env->xcr0 = 1;
ddced198 1175 if (kvm_irqchip_in_kernel()) {
dd673288 1176 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1177 KVM_MP_STATE_UNINITIALIZED;
1178 } else {
1179 env->mp_state = KVM_MP_STATE_RUNNABLE;
1180 }
689141dd
RK		 1181
1182 if (cpu->hyperv_synic) {
1183 int i;
1184 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1185 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1186 }
1187 }
caa5af0f
JK		 1188}
1189
e0723c45
PB		 1190void kvm_arch_do_init_vcpu(X86CPU *cpu)
1191{
1192 CPUX86State *env = &cpu->env;
1193
1194 /* APs get directly into wait-for-SIPI state. */
1195 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1196 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1197 }
1198}
1199
c3a3a7d3 1200static int kvm_get_supported_msrs(KVMState *s)
05330448 1201{
75b10c43 1202 static int kvm_supported_msrs;
c3a3a7d3 1203 int ret = 0;
05330448
AL		 1204
1205 /* first time */
75b10c43 1206 if (kvm_supported_msrs == 0) {
05330448
AL		 1207 struct kvm_msr_list msr_list, *kvm_msr_list;
1208
75b10c43 1209 kvm_supported_msrs = -1;
05330448
AL		 1210
1211 /* Obtain MSR list from KVM. These are the MSRs that we must
1212 * save/restore */
4c9f7372 1213 msr_list.nmsrs = 0;
c3a3a7d3 1214 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1215 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1216 return ret;
6fb6d245 1217 }
d9db889f
JK		 1218 /* Old kernel modules had a bug and could write beyond the provided
1219 memory. Allocate at least a safe amount of 1K. */
7267c094 1220 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1221 msr_list.nmsrs *
1222 sizeof(msr_list.indices[0])));
05330448 1223
55308450 1224 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1225 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1226 if (ret >= 0) {
1227 int i;
1228
1229 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1230 switch (kvm_msr_list->indices[i]) {
1231 case MSR_STAR:
c3a3a7d3 1232 has_msr_star = true;
1d268dec
LP		 1233 break;
1234 case MSR_VM_HSAVE_PA:
c3a3a7d3 1235 has_msr_hsave_pa = true;
1d268dec
LP		 1236 break;
1237 case MSR_TSC_AUX:
c9b8f6b6 1238 has_msr_tsc_aux = true;
1d268dec
LP		 1239 break;
1240 case MSR_TSC_ADJUST:
f28558d3 1241 has_msr_tsc_adjust = true;
1d268dec
LP		 1242 break;
1243 case MSR_IA32_TSCDEADLINE:
aa82ba54 1244 has_msr_tsc_deadline = true;
1d268dec
LP		 1245 break;
1246 case MSR_IA32_SMBASE:
fc12d72e 1247 has_msr_smbase = true;
1d268dec 1248 break;
e13713db
LA		 1249 case MSR_SMI_COUNT:
1250 has_msr_smi_count = true;
1251 break;
1d268dec 1252 case MSR_IA32_MISC_ENABLE:
21e87c46 1253 has_msr_misc_enable = true;
1d268dec
LP		 1254 break;
1255 case MSR_IA32_BNDCFGS:
79e9ebeb 1256 has_msr_bndcfgs = true;
1d268dec
LP		 1257 break;
1258 case MSR_IA32_XSS:
18cd2c17 1259 has_msr_xss = true;
3c254ab8 1260 break;
1d268dec 1261 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1262 has_msr_hv_crash = true;
1d268dec
LP		 1263 break;
1264 case HV_X64_MSR_RESET:
744b8a94 1265 has_msr_hv_reset = true;
1d268dec
LP		 1266 break;
1267 case HV_X64_MSR_VP_INDEX:
8c145d7c 1268 has_msr_hv_vpindex = true;
1d268dec
LP		 1269 break;
1270 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1271 has_msr_hv_runtime = true;
1d268dec
LP		 1272 break;
1273 case HV_X64_MSR_SCONTROL:
866eea9a 1274 has_msr_hv_synic = true;
1d268dec
LP		 1275 break;
1276 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1277 has_msr_hv_stimer = true;
1d268dec 1278 break;
d72bc7f6
LP		 1279 case HV_X64_MSR_TSC_FREQUENCY:
1280 has_msr_hv_frequencies = true;
1281 break;
ba6a4fd9
VK		 1282 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1283 has_msr_hv_reenlightenment = true;
1284 break;
a33a2cfe
PB		 1285 case MSR_IA32_SPEC_CTRL:
1286 has_msr_spec_ctrl = true;
1287 break;
cfeea0c0
KRW		 1288 case MSR_VIRT_SSBD:
1289 has_msr_virt_ssbd = true;
1290 break;
ff99aa64 1291 }
05330448
AL		 1292 }
1293 }
1294
7267c094 1295 g_free(kvm_msr_list);
05330448
AL		 1296 }
1297
c3a3a7d3 1298 return ret;
05330448
AL		 1299}
1300
6410848b
PB		 1301static Notifier smram_machine_done;
1302static KVMMemoryListener smram_listener;
1303static AddressSpace smram_address_space;
1304static MemoryRegion smram_as_root;
1305static MemoryRegion smram_as_mem;
1306
1307static void register_smram_listener(Notifier *n, void *unused)
1308{
1309 MemoryRegion *smram =
1310 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1311
1312 /* Outer container... */
1313 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1314 memory_region_set_enabled(&smram_as_root, true);
1315
1316 /* ... with two regions inside: normal system memory with low
1317 * priority, and...
1318 */
1319 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1320 get_system_memory(), 0, ~0ull);
1321 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1322 memory_region_set_enabled(&smram_as_mem, true);
1323
1324 if (smram) {
1325 /* ... SMRAM with higher priority */
1326 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1327 memory_region_set_enabled(smram, true);
1328 }
1329
1330 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1331 kvm_memory_listener_register(kvm_state, &smram_listener,
1332 &smram_address_space, 1);
1333}
1334
b16565b3 1335int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1336{
11076198 1337 uint64_t identity_base = 0xfffbc000;
39d6960a 1338 uint64_t shadow_mem;
20420430 1339 int ret;
25d2e361 1340 struct utsname utsname;
20420430 1341
28143b40
TH		 1342#ifdef KVM_CAP_XSAVE
1343 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1344#endif
1345
1346#ifdef KVM_CAP_XCRS
1347 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1348#endif
1349
1350#ifdef KVM_CAP_PIT_STATE2
1351 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1352#endif
1353
c3a3a7d3 1354 ret = kvm_get_supported_msrs(s);
20420430 1355 if (ret < 0) {
20420430
SY		 1356 return ret;
1357 }
25d2e361
MT		 1358
1359 uname(&utsname);
1360 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1361
4c5b10b7 1362 /*
11076198
JK		 1363 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1364 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1365 * Since these must be part of guest physical memory, we need to allocate
1366 * them, both by setting their start addresses in the kernel and by
1367 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1368 *
1369 * Older KVM versions may not support setting the identity map base. In
1370 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1371 * size.
4c5b10b7 1372 */
11076198
JK		 1373 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1374 /* Allows up to 16M BIOSes. */
1375 identity_base = 0xfeffc000;
1376
1377 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1378 if (ret < 0) {
1379 return ret;
1380 }
4c5b10b7 1381 }
e56ff191 1382
11076198
JK		 1383 /* Set TSS base one page after EPT identity map. */
1384 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1385 if (ret < 0) {
1386 return ret;
1387 }
1388
11076198
JK		 1389 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1390 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1391 if (ret < 0) {
11076198 1392 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1393 return ret;
1394 }
3c85e74f 1395 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1396
4689b77b 1397 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1398 if (shadow_mem != -1) {
1399 shadow_mem /= 4096;
1400 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1401 if (ret < 0) {
1402 return ret;
39d6960a
JK		 1403 }
1404 }
6410848b 1405
d870cfde
GA		 1406 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1407 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1408 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1409 smram_machine_done.notify = register_smram_listener;
1410 qemu_add_machine_init_done_notifier(&smram_machine_done);
1411 }
6f131f13
MT		 1412
1413 if (enable_cpu_pm) {
1414 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1415 int ret;
1416
1417/* Work around for kernel header with a typo. TODO: fix header and drop. */
1418#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1419#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1420#endif
1421 if (disable_exits) {
1422 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1423 KVM_X86_DISABLE_EXITS_HLT |
1424 KVM_X86_DISABLE_EXITS_PAUSE);
1425 }
1426
1427 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1428 disable_exits);
1429 if (ret < 0) {
1430 error_report("kvm: guest stopping CPU not supported: %s",
1431 strerror(-ret));
1432 }
1433 }
1434
11076198 1435 return 0;
05330448 1436}
b9bec74b 1437
05330448
AL		 1438static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1439{
1440 lhs->selector = rhs->selector;
1441 lhs->base = rhs->base;
1442 lhs->limit = rhs->limit;
1443 lhs->type = 3;
1444 lhs->present = 1;
1445 lhs->dpl = 3;
1446 lhs->db = 0;
1447 lhs->s = 1;
1448 lhs->l = 0;
1449 lhs->g = 0;
1450 lhs->avl = 0;
1451 lhs->unusable = 0;
1452}
1453
1454static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1455{
1456 unsigned flags = rhs->flags;
1457 lhs->selector = rhs->selector;
1458 lhs->base = rhs->base;
1459 lhs->limit = rhs->limit;
1460 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1461 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1462 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1463 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1464 lhs->s = (flags & DESC_S_MASK) != 0;
1465 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1466 lhs->g = (flags & DESC_G_MASK) != 0;
1467 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1468 lhs->unusable = !lhs->present;
7e680753 1469 lhs->padding = 0;
05330448
AL		 1470}
1471
1472static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1473{
1474 lhs->selector = rhs->selector;
1475 lhs->base = rhs->base;
1476 lhs->limit = rhs->limit;
d45fc087
RP		 1477 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1478 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1479 (rhs->dpl << DESC_DPL_SHIFT) |
1480 (rhs->db << DESC_B_SHIFT) |
1481 (rhs->s * DESC_S_MASK) |
1482 (rhs->l << DESC_L_SHIFT) |
1483 (rhs->g * DESC_G_MASK) |
1484 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1485}
1486
1487static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1488{
b9bec74b 1489 if (set) {
05330448 1490 *kvm_reg = *qemu_reg;
b9bec74b 1491 } else {
05330448 1492 *qemu_reg = *kvm_reg;
b9bec74b 1493 }
05330448
AL		 1494}
1495
1bc22652 1496static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1497{
1bc22652 1498 CPUX86State *env = &cpu->env;
05330448
AL		 1499 struct kvm_regs regs;
1500 int ret = 0;
1501
1502 if (!set) {
1bc22652 1503 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1504 if (ret < 0) {
05330448 1505 return ret;
b9bec74b 1506 }
05330448
AL		 1507 }
1508
1509 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1510 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1511 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1512 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1513 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1514 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1515 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1516 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1517#ifdef TARGET_X86_64
1518 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1519 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1520 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1521 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1522 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1523 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1524 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1525 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1526#endif
1527
1528 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1529 kvm_getput_reg(&regs.rip, &env->eip, set);
1530
b9bec74b 1531 if (set) {
1bc22652 1532 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1533 }
05330448
AL		 1534
1535 return ret;
1536}
1537
1bc22652 1538static int kvm_put_fpu(X86CPU *cpu)
05330448 1539{
1bc22652 1540 CPUX86State *env = &cpu->env;
05330448
AL		 1541 struct kvm_fpu fpu;
1542 int i;
1543
1544 memset(&fpu, 0, sizeof fpu);
1545 fpu.fsw = env->fpus & ~(7 << 11);
1546 fpu.fsw |= (env->fpstt & 7) << 11;
1547 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1548 fpu.last_opcode = env->fpop;
1549 fpu.last_ip = env->fpip;
1550 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1551 for (i = 0; i < 8; ++i) {
1552 fpu.ftwx |= (!env->fptags[i]) << i;
1553 }
05330448 1554 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1555 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1556 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1557 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1558 }
05330448
AL		 1559 fpu.mxcsr = env->mxcsr;
1560
1bc22652 1561 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1562}
1563
6b42494b
JK		 1564#define XSAVE_FCW_FSW 0
1565#define XSAVE_FTW_FOP 1
f1665b21
SY		 1566#define XSAVE_CWD_RIP 2
1567#define XSAVE_CWD_RDP 4
1568#define XSAVE_MXCSR 6
1569#define XSAVE_ST_SPACE 8
1570#define XSAVE_XMM_SPACE 40
1571#define XSAVE_XSTATE_BV 128
1572#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1573#define XSAVE_BNDREGS 240
1574#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1575#define XSAVE_OPMASK 272
1576#define XSAVE_ZMM_Hi256 288
1577#define XSAVE_Hi16_ZMM 416
f74eefe0 1578#define XSAVE_PKRU 672
f1665b21 1579
b503717d 1580#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 1581 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 1582
1583#define ASSERT_OFFSET(word_offset, field) \
1584 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1585 offsetof(X86XSaveArea, field))
1586
1587ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1588ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1589ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1590ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1591ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1592ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1593ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1594ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1595ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1596ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1597ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1598ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1599ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1600ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1601ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1602
1bc22652 1603static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1604{
1bc22652 1605 CPUX86State *env = &cpu->env;
86cd2ea0 1606 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1607
28143b40 1608 if (!has_xsave) {
1bc22652 1609 return kvm_put_fpu(cpu);
b9bec74b 1610 }
86a57621 1611 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1612
9be38598 1613 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1614}
1615
1bc22652 1616static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1617{
1bc22652 1618 CPUX86State *env = &cpu->env;
bdfc8480 1619 struct kvm_xcrs xcrs = {};
f1665b21 1620
28143b40 1621 if (!has_xcrs) {
f1665b21 1622 return 0;
b9bec74b 1623 }
f1665b21
SY		 1624
1625 xcrs.nr_xcrs = 1;
1626 xcrs.flags = 0;
1627 xcrs.xcrs[0].xcr = 0;
1628 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1629 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1630}
1631
1bc22652 1632static int kvm_put_sregs(X86CPU *cpu)
05330448 1633{
1bc22652 1634 CPUX86State *env = &cpu->env;
05330448
AL		 1635 struct kvm_sregs sregs;
1636
0e607a80
JK		 1637 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1638 if (env->interrupt_injected >= 0) {
1639 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1640 (uint64_t)1 << (env->interrupt_injected % 64);
1641 }
05330448
AL		 1642
1643 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1644 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1645 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1646 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1647 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1648 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1649 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1650 } else {
b9bec74b
JK		 1651 set_seg(&sregs.cs, &env->segs[R_CS]);
1652 set_seg(&sregs.ds, &env->segs[R_DS]);
1653 set_seg(&sregs.es, &env->segs[R_ES]);
1654 set_seg(&sregs.fs, &env->segs[R_FS]);
1655 set_seg(&sregs.gs, &env->segs[R_GS]);
1656 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1657 }
1658
1659 set_seg(&sregs.tr, &env->tr);
1660 set_seg(&sregs.ldt, &env->ldt);
1661
1662 sregs.idt.limit = env->idt.limit;
1663 sregs.idt.base = env->idt.base;
7e680753 1664 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1665 sregs.gdt.limit = env->gdt.limit;
1666 sregs.gdt.base = env->gdt.base;
7e680753 1667 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1668
1669 sregs.cr0 = env->cr[0];
1670 sregs.cr2 = env->cr[2];
1671 sregs.cr3 = env->cr[3];
1672 sregs.cr4 = env->cr[4];
1673
02e51483
CF		 1674 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1675 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1676
1677 sregs.efer = env->efer;
1678
1bc22652 1679 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1680}
1681
d71b62a1
EH		 1682static void kvm_msr_buf_reset(X86CPU *cpu)
1683{
1684 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1685}
1686
9c600a84
EH		 1687static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1688{
1689 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1690 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1691 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1692
1693 assert((void *)(entry + 1) <= limit);
1694
1abc2cae
EH		 1695 entry->index = index;
1696 entry->reserved = 0;
1697 entry->data = value;
9c600a84
EH		 1698 msrs->nmsrs++;
1699}
1700
73e1b8f2
PB		 1701static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1702{
1703 kvm_msr_buf_reset(cpu);
1704 kvm_msr_entry_add(cpu, index, value);
1705
1706 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1707}
1708
f8d9ccf8
DDAG		 1709void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1710{
1711 int ret;
1712
1713 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1714 assert(ret == 1);
1715}
1716
7477cd38
MT		 1717static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1718{
1719 CPUX86State *env = &cpu->env;
48e1a45c 1720 int ret;
7477cd38
MT		 1721
1722 if (!has_msr_tsc_deadline) {
1723 return 0;
1724 }
1725
73e1b8f2 1726 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1727 if (ret < 0) {
1728 return ret;
1729 }
1730
1731 assert(ret == 1);
1732 return 0;
7477cd38
MT		 1733}
1734
6bdf863d
JK		 1735/*
1736 * Provide a separate write service for the feature control MSR in order to
1737 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1738 * before writing any other state because forcibly leaving nested mode
1739 * invalidates the VCPU state.
1740 */
1741static int kvm_put_msr_feature_control(X86CPU *cpu)
1742{
48e1a45c
PB		 1743 int ret;
1744
1745 if (!has_msr_feature_control) {
1746 return 0;
1747 }
6bdf863d 1748
73e1b8f2
PB		 1749 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1750 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1751 if (ret < 0) {
1752 return ret;
1753 }
1754
1755 assert(ret == 1);
1756 return 0;
6bdf863d
JK		 1757}
1758
1bc22652 1759static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1760{
1bc22652 1761 CPUX86State *env = &cpu->env;
9c600a84 1762 int i;
48e1a45c 1763 int ret;
05330448 1764
d71b62a1
EH		 1765 kvm_msr_buf_reset(cpu);
1766
9c600a84
EH		 1767 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1768 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1769 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1770 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1771 if (has_msr_star) {
9c600a84 1772 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1773 }
c3a3a7d3 1774 if (has_msr_hsave_pa) {
9c600a84 1775 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1776 }
c9b8f6b6 1777 if (has_msr_tsc_aux) {
9c600a84 1778 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1779 }
f28558d3 1780 if (has_msr_tsc_adjust) {
9c600a84 1781 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1782 }
21e87c46 1783 if (has_msr_misc_enable) {
9c600a84 1784 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1785 env->msr_ia32_misc_enable);
1786 }
fc12d72e 1787 if (has_msr_smbase) {
9c600a84 1788 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1789 }
e13713db
LA		 1790 if (has_msr_smi_count) {
1791 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1792 }
439d19f2 1793 if (has_msr_bndcfgs) {
9c600a84 1794 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1795 }
18cd2c17 1796 if (has_msr_xss) {
9c600a84 1797 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1798 }
a33a2cfe
PB		 1799 if (has_msr_spec_ctrl) {
1800 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1801 }
cfeea0c0
KRW		 1802 if (has_msr_virt_ssbd) {
1803 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1804 }
1805
05330448 1806#ifdef TARGET_X86_64
25d2e361 1807 if (lm_capable_kernel) {
9c600a84
EH		 1808 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1809 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1810 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1811 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1812 }
05330448 1813#endif
a33a2cfe 1814
ff5c186b 1815 /*
0d894367
PB		 1816 * The following MSRs have side effects on the guest or are too heavy
1817 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1818 */
1819 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1820 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1821 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1822 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1823 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1824 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1825 }
55c911a5 1826 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1827 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1828 }
55c911a5 1829 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1830 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1831 }
0b368a10
JD		 1832 if (has_architectural_pmu_version > 0) {
1833 if (has_architectural_pmu_version > 1) {
1834 /* Stop the counter. */
1835 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1836 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1837 }
0d894367
PB		 1838
1839 /* Set the counter values. */
0b368a10 1840 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 1841 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1842 env->msr_fixed_counters[i]);
1843 }
0b368a10 1844 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 1845 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1846 env->msr_gp_counters[i]);
9c600a84 1847 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1848 env->msr_gp_evtsel[i]);
1849 }
0b368a10
JD		 1850 if (has_architectural_pmu_version > 1) {
1851 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1852 env->msr_global_status);
1853 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1854 env->msr_global_ovf_ctrl);
1855
1856 /* Now start the PMU. */
1857 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1858 env->msr_fixed_ctr_ctrl);
1859 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1860 env->msr_global_ctrl);
1861 }
0d894367 1862 }
da1cc323
EY		 1863 /*
1864 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1865 * only sync them to KVM on the first cpu
1866 */
1867 if (current_cpu == first_cpu) {
1868 if (has_msr_hv_hypercall) {
1869 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1870 env->msr_hv_guest_os_id);
1871 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1872 env->msr_hv_hypercall);
1873 }
1874 if (cpu->hyperv_time) {
1875 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1876 env->msr_hv_tsc);
1877 }
ba6a4fd9
VK		 1878 if (cpu->hyperv_reenlightenment) {
1879 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
1880 env->msr_hv_reenlightenment_control);
1881 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
1882 env->msr_hv_tsc_emulation_control);
1883 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
1884 env->msr_hv_tsc_emulation_status);
1885 }
eab70139 1886 }
2d5aa872 1887 if (cpu->hyperv_vapic) {
9c600a84 1888 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1889 env->msr_hv_vapic);
eab70139 1890 }
f2a53c9e
AS		 1891 if (has_msr_hv_crash) {
1892 int j;
1893
5e953812 1894 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 1895 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1896 env->msr_hv_crash_params[j]);
1897
5e953812 1898 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 1899 }
46eb8f98 1900 if (has_msr_hv_runtime) {
9c600a84 1901 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1902 }
866eea9a
AS		 1903 if (cpu->hyperv_synic) {
1904 int j;
1905
09df29b6
RK		 1906 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1907
9c600a84 1908 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1909 env->msr_hv_synic_control);
9c600a84 1910 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1911 env->msr_hv_synic_evt_page);
9c600a84 1912 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1913 env->msr_hv_synic_msg_page);
1914
1915 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1916 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1917 env->msr_hv_synic_sint[j]);
1918 }
1919 }
ff99aa64
AS		 1920 if (has_msr_hv_stimer) {
1921 int j;
1922
1923 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1924 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1925 env->msr_hv_stimer_config[j]);
1926 }
1927
1928 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1929 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1930 env->msr_hv_stimer_count[j]);
1931 }
1932 }
1eabfce6 1933 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1934 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1935
9c600a84
EH		 1936 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1937 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1938 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1939 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1940 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1941 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1942 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1943 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1944 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1945 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1946 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1947 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1948 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1949 /* The CPU GPs if we write to a bit above the physical limit of
1950 * the host CPU (and KVM emulates that)
1951 */
1952 uint64_t mask = env->mtrr_var[i].mask;
1953 mask &= phys_mask;
1954
9c600a84
EH		 1955 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1956 env->mtrr_var[i].base);
112dad69 1957 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1958 }
1959 }
b77146e9
CP		 1960 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
1961 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
1962 0x14, 1, R_EAX) & 0x7;
1963
1964 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
1965 env->msr_rtit_ctrl);
1966 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
1967 env->msr_rtit_status);
1968 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
1969 env->msr_rtit_output_base);
1970 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
1971 env->msr_rtit_output_mask);
1972 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
1973 env->msr_rtit_cr3_match);
1974 for (i = 0; i < addr_num; i++) {
1975 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
1976 env->msr_rtit_addrs[i]);
1977 }
1978 }
6bdf863d
JK		 1979
1980 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1981 * kvm_put_msr_feature_control. */
ea643051 1982 }
57780495 1983 if (env->mcg_cap) {
d8da8574 1984 int i;
b9bec74b 1985
9c600a84
EH		 1986 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1987 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1988 if (has_msr_mcg_ext_ctl) {
1989 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1990 }
c34d440a 1991 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1992 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1993 }
1994 }
1a03675d 1995
d71b62a1 1996 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1997 if (ret < 0) {
1998 return ret;
1999 }
05330448 2000
c70b11d1
EH		 2001 if (ret < cpu->kvm_msr_buf->nmsrs) {
2002 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2003 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2004 (uint32_t)e->index, (uint64_t)e->data);
2005 }
2006
9c600a84 2007 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2008 return 0;
05330448
AL		 2009}
2010
2011
1bc22652 2012static int kvm_get_fpu(X86CPU *cpu)
05330448 2013{
1bc22652 2014 CPUX86State *env = &cpu->env;
05330448
AL		 2015 struct kvm_fpu fpu;
2016 int i, ret;
2017
1bc22652 2018 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2019 if (ret < 0) {
05330448 2020 return ret;
b9bec74b 2021 }
05330448
AL		 2022
2023 env->fpstt = (fpu.fsw >> 11) & 7;
2024 env->fpus = fpu.fsw;
2025 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2026 env->fpop = fpu.last_opcode;
2027 env->fpip = fpu.last_ip;
2028 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2029 for (i = 0; i < 8; ++i) {
2030 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2031 }
05330448 2032 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2033 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2034 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2035 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2036 }
05330448
AL		 2037 env->mxcsr = fpu.mxcsr;
2038
2039 return 0;
2040}
2041
1bc22652 2042static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2043{
1bc22652 2044 CPUX86State *env = &cpu->env;
86cd2ea0 2045 X86XSaveArea *xsave = env->kvm_xsave_buf;
86a57621 2046 int ret;
f1665b21 2047
28143b40 2048 if (!has_xsave) {
1bc22652 2049 return kvm_get_fpu(cpu);
b9bec74b 2050 }
f1665b21 2051
1bc22652 2052 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2053 if (ret < 0) {
f1665b21 2054 return ret;
0f53994f 2055 }
86a57621 2056 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2057
f1665b21 2058 return 0;
f1665b21
SY		 2059}
2060
1bc22652 2061static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2062{
1bc22652 2063 CPUX86State *env = &cpu->env;
f1665b21
SY		 2064 int i, ret;
2065 struct kvm_xcrs xcrs;
2066
28143b40 2067 if (!has_xcrs) {
f1665b21 2068 return 0;
b9bec74b 2069 }
f1665b21 2070
1bc22652 2071 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2072 if (ret < 0) {
f1665b21 2073 return ret;
b9bec74b 2074 }
f1665b21 2075
b9bec74b 2076 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2077 /* Only support xcr0 now */
0fd53fec
PB		 2078 if (xcrs.xcrs[i].xcr == 0) {
2079 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2080 break;
2081 }
b9bec74b 2082 }
f1665b21 2083 return 0;
f1665b21
SY		 2084}
2085
1bc22652 2086static int kvm_get_sregs(X86CPU *cpu)
05330448 2087{
1bc22652 2088 CPUX86State *env = &cpu->env;
05330448 2089 struct kvm_sregs sregs;
0e607a80 2090 int bit, i, ret;
05330448 2091
1bc22652 2092 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2093 if (ret < 0) {
05330448 2094 return ret;
b9bec74b 2095 }
05330448 2096
0e607a80
JK		 2097 /* There can only be one pending IRQ set in the bitmap at a time, so try
2098 to find it and save its number instead (-1 for none). */
2099 env->interrupt_injected = -1;
2100 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2101 if (sregs.interrupt_bitmap[i]) {
2102 bit = ctz64(sregs.interrupt_bitmap[i]);
2103 env->interrupt_injected = i * 64 + bit;
2104 break;
2105 }
2106 }
05330448
AL		 2107
2108 get_seg(&env->segs[R_CS], &sregs.cs);
2109 get_seg(&env->segs[R_DS], &sregs.ds);
2110 get_seg(&env->segs[R_ES], &sregs.es);
2111 get_seg(&env->segs[R_FS], &sregs.fs);
2112 get_seg(&env->segs[R_GS], &sregs.gs);
2113 get_seg(&env->segs[R_SS], &sregs.ss);
2114
2115 get_seg(&env->tr, &sregs.tr);
2116 get_seg(&env->ldt, &sregs.ldt);
2117
2118 env->idt.limit = sregs.idt.limit;
2119 env->idt.base = sregs.idt.base;
2120 env->gdt.limit = sregs.gdt.limit;
2121 env->gdt.base = sregs.gdt.base;
2122
2123 env->cr[0] = sregs.cr0;
2124 env->cr[2] = sregs.cr2;
2125 env->cr[3] = sregs.cr3;
2126 env->cr[4] = sregs.cr4;
2127
05330448 2128 env->efer = sregs.efer;
cce47516
JK		 2129
2130 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2131 x86_update_hflags(env);
05330448
AL		 2132
2133 return 0;
2134}
2135
1bc22652 2136static int kvm_get_msrs(X86CPU *cpu)
05330448 2137{
1bc22652 2138 CPUX86State *env = &cpu->env;
d71b62a1 2139 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2140 int ret, i;
fcc35e7c 2141 uint64_t mtrr_top_bits;
05330448 2142
d71b62a1
EH		 2143 kvm_msr_buf_reset(cpu);
2144
9c600a84
EH		 2145 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2146 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2147 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2148 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2149 if (has_msr_star) {
9c600a84 2150 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2151 }
c3a3a7d3 2152 if (has_msr_hsave_pa) {
9c600a84 2153 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2154 }
c9b8f6b6 2155 if (has_msr_tsc_aux) {
9c600a84 2156 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2157 }
f28558d3 2158 if (has_msr_tsc_adjust) {
9c600a84 2159 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2160 }
aa82ba54 2161 if (has_msr_tsc_deadline) {
9c600a84 2162 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2163 }
21e87c46 2164 if (has_msr_misc_enable) {
9c600a84 2165 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2166 }
fc12d72e 2167 if (has_msr_smbase) {
9c600a84 2168 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2169 }
e13713db
LA		 2170 if (has_msr_smi_count) {
2171 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2172 }
df67696e 2173 if (has_msr_feature_control) {
9c600a84 2174 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2175 }
79e9ebeb 2176 if (has_msr_bndcfgs) {
9c600a84 2177 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2178 }
18cd2c17 2179 if (has_msr_xss) {
9c600a84 2180 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2181 }
a33a2cfe
PB		 2182 if (has_msr_spec_ctrl) {
2183 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2184 }
cfeea0c0
KRW		 2185 if (has_msr_virt_ssbd) {
2186 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2187 }
b8cc45d6 2188 if (!env->tsc_valid) {
9c600a84 2189 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2190 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2191 }
2192
05330448 2193#ifdef TARGET_X86_64
25d2e361 2194 if (lm_capable_kernel) {
9c600a84
EH		 2195 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2196 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2197 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2198 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2199 }
05330448 2200#endif
9c600a84
EH		 2201 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2202 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2203 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2204 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2205 }
55c911a5 2206 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2207 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2208 }
55c911a5 2209 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2210 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2211 }
0b368a10
JD		 2212 if (has_architectural_pmu_version > 0) {
2213 if (has_architectural_pmu_version > 1) {
2214 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2215 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2216 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2217 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2218 }
2219 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2220 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2221 }
0b368a10 2222 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2223 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2224 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2225 }
2226 }
1a03675d 2227
57780495 2228 if (env->mcg_cap) {
9c600a84
EH		 2229 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2230 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2231 if (has_msr_mcg_ext_ctl) {
2232 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2233 }
b9bec74b 2234 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2235 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2236 }
57780495 2237 }
57780495 2238
1c90ef26 2239 if (has_msr_hv_hypercall) {
9c600a84
EH		 2240 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2241 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2242 }
2d5aa872 2243 if (cpu->hyperv_vapic) {
9c600a84 2244 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2245 }
3ddcd2ed 2246 if (cpu->hyperv_time) {
9c600a84 2247 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2248 }
ba6a4fd9
VK		 2249 if (cpu->hyperv_reenlightenment) {
2250 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2251 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2252 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2253 }
f2a53c9e
AS		 2254 if (has_msr_hv_crash) {
2255 int j;
2256
5e953812 2257 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2258 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2259 }
2260 }
46eb8f98 2261 if (has_msr_hv_runtime) {
9c600a84 2262 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2263 }
866eea9a
AS		 2264 if (cpu->hyperv_synic) {
2265 uint32_t msr;
2266
9c600a84 2267 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2268 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2269 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2270 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2271 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2272 }
2273 }
ff99aa64
AS		 2274 if (has_msr_hv_stimer) {
2275 uint32_t msr;
2276
2277 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2278 msr++) {
9c600a84 2279 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2280 }
2281 }
1eabfce6 2282 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2283 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2284 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2285 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2286 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2287 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2288 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2289 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2290 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2291 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2292 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2293 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2294 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2295 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2296 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2297 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2298 }
2299 }
5ef68987 2300
b77146e9
CP		 2301 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2302 int addr_num =
2303 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2304
2305 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2306 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2307 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2308 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2309 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2310 for (i = 0; i < addr_num; i++) {
2311 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2312 }
2313 }
2314
d71b62a1 2315 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2316 if (ret < 0) {
05330448 2317 return ret;
b9bec74b 2318 }
05330448 2319
c70b11d1
EH		 2320 if (ret < cpu->kvm_msr_buf->nmsrs) {
2321 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2322 error_report("error: failed to get MSR 0x%" PRIx32,
2323 (uint32_t)e->index);
2324 }
2325
9c600a84 2326 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2327 /*
2328 * MTRR masks: Each mask consists of 5 parts
2329 * a 10..0: must be zero
2330 * b 11 : valid bit
2331 * c n-1.12: actual mask bits
2332 * d 51..n: reserved must be zero
2333 * e 63.52: reserved must be zero
2334 *
2335 * 'n' is the number of physical bits supported by the CPU and is
2336 * apparently always <= 52. We know our 'n' but don't know what
2337 * the destinations 'n' is; it might be smaller, in which case
2338 * it masks (c) on loading. It might be larger, in which case
2339 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2340 * we're migrating to.
2341 */
2342
2343 if (cpu->fill_mtrr_mask) {
2344 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2345 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2346 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2347 } else {
2348 mtrr_top_bits = 0;
2349 }
2350
05330448 2351 for (i = 0; i < ret; i++) {
0d894367
PB		 2352 uint32_t index = msrs[i].index;
2353 switch (index) {
05330448
AL		 2354 case MSR_IA32_SYSENTER_CS:
2355 env->sysenter_cs = msrs[i].data;
2356 break;
2357 case MSR_IA32_SYSENTER_ESP:
2358 env->sysenter_esp = msrs[i].data;
2359 break;
2360 case MSR_IA32_SYSENTER_EIP:
2361 env->sysenter_eip = msrs[i].data;
2362 break;
0c03266a
JK		 2363 case MSR_PAT:
2364 env->pat = msrs[i].data;
2365 break;
05330448
AL		 2366 case MSR_STAR:
2367 env->star = msrs[i].data;
2368 break;
2369#ifdef TARGET_X86_64
2370 case MSR_CSTAR:
2371 env->cstar = msrs[i].data;
2372 break;
2373 case MSR_KERNELGSBASE:
2374 env->kernelgsbase = msrs[i].data;
2375 break;
2376 case MSR_FMASK:
2377 env->fmask = msrs[i].data;
2378 break;
2379 case MSR_LSTAR:
2380 env->lstar = msrs[i].data;
2381 break;
2382#endif
2383 case MSR_IA32_TSC:
2384 env->tsc = msrs[i].data;
2385 break;
c9b8f6b6
AS		 2386 case MSR_TSC_AUX:
2387 env->tsc_aux = msrs[i].data;
2388 break;
f28558d3
WA		 2389 case MSR_TSC_ADJUST:
2390 env->tsc_adjust = msrs[i].data;
2391 break;
aa82ba54
LJ		 2392 case MSR_IA32_TSCDEADLINE:
2393 env->tsc_deadline = msrs[i].data;
2394 break;
aa851e36
MT		 2395 case MSR_VM_HSAVE_PA:
2396 env->vm_hsave = msrs[i].data;
2397 break;
1a03675d
GC		 2398 case MSR_KVM_SYSTEM_TIME:
2399 env->system_time_msr = msrs[i].data;
2400 break;
2401 case MSR_KVM_WALL_CLOCK:
2402 env->wall_clock_msr = msrs[i].data;
2403 break;
57780495
MT		 2404 case MSR_MCG_STATUS:
2405 env->mcg_status = msrs[i].data;
2406 break;
2407 case MSR_MCG_CTL:
2408 env->mcg_ctl = msrs[i].data;
2409 break;
87f8b626
AR		 2410 case MSR_MCG_EXT_CTL:
2411 env->mcg_ext_ctl = msrs[i].data;
2412 break;
21e87c46
AK		 2413 case MSR_IA32_MISC_ENABLE:
2414 env->msr_ia32_misc_enable = msrs[i].data;
2415 break;
fc12d72e
PB		 2416 case MSR_IA32_SMBASE:
2417 env->smbase = msrs[i].data;
2418 break;
e13713db
LA		 2419 case MSR_SMI_COUNT:
2420 env->msr_smi_count = msrs[i].data;
2421 break;
0779caeb
ACL		 2422 case MSR_IA32_FEATURE_CONTROL:
2423 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2424 break;
79e9ebeb
LJ		 2425 case MSR_IA32_BNDCFGS:
2426 env->msr_bndcfgs = msrs[i].data;
2427 break;
18cd2c17
WL		 2428 case MSR_IA32_XSS:
2429 env->xss = msrs[i].data;
2430 break;
57780495 2431 default:
57780495
MT		 2432 if (msrs[i].index >= MSR_MC0_CTL &&
2433 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2434 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2435 }
d8da8574 2436 break;
f6584ee2
GN		 2437 case MSR_KVM_ASYNC_PF_EN:
2438 env->async_pf_en_msr = msrs[i].data;
2439 break;
bc9a839d
MT		 2440 case MSR_KVM_PV_EOI_EN:
2441 env->pv_eoi_en_msr = msrs[i].data;
2442 break;
917367aa
MT		 2443 case MSR_KVM_STEAL_TIME:
2444 env->steal_time_msr = msrs[i].data;
2445 break;
0d894367
PB		 2446 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2447 env->msr_fixed_ctr_ctrl = msrs[i].data;
2448 break;
2449 case MSR_CORE_PERF_GLOBAL_CTRL:
2450 env->msr_global_ctrl = msrs[i].data;
2451 break;
2452 case MSR_CORE_PERF_GLOBAL_STATUS:
2453 env->msr_global_status = msrs[i].data;
2454 break;
2455 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2456 env->msr_global_ovf_ctrl = msrs[i].data;
2457 break;
2458 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2459 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2460 break;
2461 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2462 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2463 break;
2464 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2465 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2466 break;
1c90ef26
VR		 2467 case HV_X64_MSR_HYPERCALL:
2468 env->msr_hv_hypercall = msrs[i].data;
2469 break;
2470 case HV_X64_MSR_GUEST_OS_ID:
2471 env->msr_hv_guest_os_id = msrs[i].data;
2472 break;
5ef68987
VR		 2473 case HV_X64_MSR_APIC_ASSIST_PAGE:
2474 env->msr_hv_vapic = msrs[i].data;
2475 break;
48a5f3bc
VR		 2476 case HV_X64_MSR_REFERENCE_TSC:
2477 env->msr_hv_tsc = msrs[i].data;
2478 break;
f2a53c9e
AS		 2479 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2480 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2481 break;
46eb8f98
AS		 2482 case HV_X64_MSR_VP_RUNTIME:
2483 env->msr_hv_runtime = msrs[i].data;
2484 break;
866eea9a
AS		 2485 case HV_X64_MSR_SCONTROL:
2486 env->msr_hv_synic_control = msrs[i].data;
2487 break;
866eea9a
AS		 2488 case HV_X64_MSR_SIEFP:
2489 env->msr_hv_synic_evt_page = msrs[i].data;
2490 break;
2491 case HV_X64_MSR_SIMP:
2492 env->msr_hv_synic_msg_page = msrs[i].data;
2493 break;
2494 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2495 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2496 break;
2497 case HV_X64_MSR_STIMER0_CONFIG:
2498 case HV_X64_MSR_STIMER1_CONFIG:
2499 case HV_X64_MSR_STIMER2_CONFIG:
2500 case HV_X64_MSR_STIMER3_CONFIG:
2501 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2502 msrs[i].data;
2503 break;
2504 case HV_X64_MSR_STIMER0_COUNT:
2505 case HV_X64_MSR_STIMER1_COUNT:
2506 case HV_X64_MSR_STIMER2_COUNT:
2507 case HV_X64_MSR_STIMER3_COUNT:
2508 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2509 msrs[i].data;
866eea9a 2510 break;
ba6a4fd9
VK		 2511 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2512 env->msr_hv_reenlightenment_control = msrs[i].data;
2513 break;
2514 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2515 env->msr_hv_tsc_emulation_control = msrs[i].data;
2516 break;
2517 case HV_X64_MSR_TSC_EMULATION_STATUS:
2518 env->msr_hv_tsc_emulation_status = msrs[i].data;
2519 break;
d1ae67f6
AW		 2520 case MSR_MTRRdefType:
2521 env->mtrr_deftype = msrs[i].data;
2522 break;
2523 case MSR_MTRRfix64K_00000:
2524 env->mtrr_fixed[0] = msrs[i].data;
2525 break;
2526 case MSR_MTRRfix16K_80000:
2527 env->mtrr_fixed[1] = msrs[i].data;
2528 break;
2529 case MSR_MTRRfix16K_A0000:
2530 env->mtrr_fixed[2] = msrs[i].data;
2531 break;
2532 case MSR_MTRRfix4K_C0000:
2533 env->mtrr_fixed[3] = msrs[i].data;
2534 break;
2535 case MSR_MTRRfix4K_C8000:
2536 env->mtrr_fixed[4] = msrs[i].data;
2537 break;
2538 case MSR_MTRRfix4K_D0000:
2539 env->mtrr_fixed[5] = msrs[i].data;
2540 break;
2541 case MSR_MTRRfix4K_D8000:
2542 env->mtrr_fixed[6] = msrs[i].data;
2543 break;
2544 case MSR_MTRRfix4K_E0000:
2545 env->mtrr_fixed[7] = msrs[i].data;
2546 break;
2547 case MSR_MTRRfix4K_E8000:
2548 env->mtrr_fixed[8] = msrs[i].data;
2549 break;
2550 case MSR_MTRRfix4K_F0000:
2551 env->mtrr_fixed[9] = msrs[i].data;
2552 break;
2553 case MSR_MTRRfix4K_F8000:
2554 env->mtrr_fixed[10] = msrs[i].data;
2555 break;
2556 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2557 if (index & 1) {
fcc35e7c
DDAG		 2558 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2559 mtrr_top_bits;
d1ae67f6
AW		 2560 } else {
2561 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2562 }
2563 break;
a33a2cfe
PB		 2564 case MSR_IA32_SPEC_CTRL:
2565 env->spec_ctrl = msrs[i].data;
2566 break;
cfeea0c0
KRW		 2567 case MSR_VIRT_SSBD:
2568 env->virt_ssbd = msrs[i].data;
2569 break;
b77146e9
CP		 2570 case MSR_IA32_RTIT_CTL:
2571 env->msr_rtit_ctrl = msrs[i].data;
2572 break;
2573 case MSR_IA32_RTIT_STATUS:
2574 env->msr_rtit_status = msrs[i].data;
2575 break;
2576 case MSR_IA32_RTIT_OUTPUT_BASE:
2577 env->msr_rtit_output_base = msrs[i].data;
2578 break;
2579 case MSR_IA32_RTIT_OUTPUT_MASK:
2580 env->msr_rtit_output_mask = msrs[i].data;
2581 break;
2582 case MSR_IA32_RTIT_CR3_MATCH:
2583 env->msr_rtit_cr3_match = msrs[i].data;
2584 break;
2585 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2586 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2587 break;
05330448
AL		 2588 }
2589 }
2590
2591 return 0;
2592}
2593
1bc22652 2594static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2595{
1bc22652 2596 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2597
1bc22652 2598 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2599}
2600
23d02d9b 2601static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2602{
259186a7 2603 CPUState *cs = CPU(cpu);
23d02d9b 2604 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2605 struct kvm_mp_state mp_state;
2606 int ret;
2607
259186a7 2608 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2609 if (ret < 0) {
2610 return ret;
2611 }
2612 env->mp_state = mp_state.mp_state;
c14750e8 2613 if (kvm_irqchip_in_kernel()) {
259186a7 2614 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2615 }
9bdbe550
HB		 2616 return 0;
2617}
2618
1bc22652 2619static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2620{
02e51483 2621 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2622 struct kvm_lapic_state kapic;
2623 int ret;
2624
3d4b2649 2625 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2626 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2627 if (ret < 0) {
2628 return ret;
2629 }
2630
2631 kvm_get_apic_state(apic, &kapic);
2632 }
2633 return 0;
2634}
2635
1bc22652 2636static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2637{
fc12d72e 2638 CPUState *cs = CPU(cpu);
1bc22652 2639 CPUX86State *env = &cpu->env;
076796f8 2640 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2641
2642 if (!kvm_has_vcpu_events()) {
2643 return 0;
2644 }
2645
31827373
JK		 2646 events.exception.injected = (env->exception_injected >= 0);
2647 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2648 events.exception.has_error_code = env->has_error_code;
2649 events.exception.error_code = env->error_code;
7e680753 2650 events.exception.pad = 0;
a0fb002c
JK		 2651
2652 events.interrupt.injected = (env->interrupt_injected >= 0);
2653 events.interrupt.nr = env->interrupt_injected;
2654 events.interrupt.soft = env->soft_interrupt;
2655
2656 events.nmi.injected = env->nmi_injected;
2657 events.nmi.pending = env->nmi_pending;
2658 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2659 events.nmi.pad = 0;
a0fb002c
JK		 2660
2661 events.sipi_vector = env->sipi_vector;
68c6efe0 2662 events.flags = 0;
a0fb002c 2663
fc12d72e
PB		 2664 if (has_msr_smbase) {
2665 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2666 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2667 if (kvm_irqchip_in_kernel()) {
2668 /* As soon as these are moved to the kernel, remove them
2669 * from cs->interrupt_request.
2670 */
2671 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2672 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2673 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2674 } else {
2675 /* Keep these in cs->interrupt_request. */
2676 events.smi.pending = 0;
2677 events.smi.latched_init = 0;
2678 }
fc3a1fd7
DDAG		 2679 /* Stop SMI delivery on old machine types to avoid a reboot
2680 * on an inward migration of an old VM.
2681 */
2682 if (!cpu->kvm_no_smi_migration) {
2683 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2684 }
fc12d72e
PB		 2685 }
2686
ea643051 2687 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2688 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2689 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2690 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2691 }
ea643051 2692 }
aee028b9 2693
1bc22652 2694 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2695}
2696
1bc22652 2697static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2698{
1bc22652 2699 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2700 struct kvm_vcpu_events events;
2701 int ret;
2702
2703 if (!kvm_has_vcpu_events()) {
2704 return 0;
2705 }
2706
fc12d72e 2707 memset(&events, 0, sizeof(events));
1bc22652 2708 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2709 if (ret < 0) {
2710 return ret;
2711 }
31827373 2712 env->exception_injected =
a0fb002c
JK		 2713 events.exception.injected ? events.exception.nr : -1;
2714 env->has_error_code = events.exception.has_error_code;
2715 env->error_code = events.exception.error_code;
2716
2717 env->interrupt_injected =
2718 events.interrupt.injected ? events.interrupt.nr : -1;
2719 env->soft_interrupt = events.interrupt.soft;
2720
2721 env->nmi_injected = events.nmi.injected;
2722 env->nmi_pending = events.nmi.pending;
2723 if (events.nmi.masked) {
2724 env->hflags2 |= HF2_NMI_MASK;
2725 } else {
2726 env->hflags2 &= ~HF2_NMI_MASK;
2727 }
2728
fc12d72e
PB		 2729 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2730 if (events.smi.smm) {
2731 env->hflags |= HF_SMM_MASK;
2732 } else {
2733 env->hflags &= ~HF_SMM_MASK;
2734 }
2735 if (events.smi.pending) {
2736 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2737 } else {
2738 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2739 }
2740 if (events.smi.smm_inside_nmi) {
2741 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2742 } else {
2743 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2744 }
2745 if (events.smi.latched_init) {
2746 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2747 } else {
2748 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2749 }
2750 }
2751
a0fb002c 2752 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2753
2754 return 0;
2755}
2756
1bc22652 2757static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2758{
ed2803da 2759 CPUState *cs = CPU(cpu);
1bc22652 2760 CPUX86State *env = &cpu->env;
b0b1d690 2761 int ret = 0;
b0b1d690
JK		 2762 unsigned long reinject_trap = 0;
2763
2764 if (!kvm_has_vcpu_events()) {
2765 if (env->exception_injected == 1) {
2766 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2767 } else if (env->exception_injected == 3) {
2768 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2769 }
2770 env->exception_injected = -1;
2771 }
2772
2773 /*
2774 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2775 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2776 * by updating the debug state once again if single-stepping is on.
2777 * Another reason to call kvm_update_guest_debug here is a pending debug
2778 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2779 * reinject them via SET_GUEST_DEBUG.
2780 */
2781 if (reinject_trap ||
ed2803da 2782 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2783 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2784 }
b0b1d690
JK		 2785 return ret;
2786}
2787
1bc22652 2788static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2789{
1bc22652 2790 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2791 struct kvm_debugregs dbgregs;
2792 int i;
2793
2794 if (!kvm_has_debugregs()) {
2795 return 0;
2796 }
2797
2798 for (i = 0; i < 4; i++) {
2799 dbgregs.db[i] = env->dr[i];
2800 }
2801 dbgregs.dr6 = env->dr[6];
2802 dbgregs.dr7 = env->dr[7];
2803 dbgregs.flags = 0;
2804
1bc22652 2805 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2806}
2807
1bc22652 2808static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2809{
1bc22652 2810 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2811 struct kvm_debugregs dbgregs;
2812 int i, ret;
2813
2814 if (!kvm_has_debugregs()) {
2815 return 0;
2816 }
2817
1bc22652 2818 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2819 if (ret < 0) {
b9bec74b 2820 return ret;
ff44f1a3
JK		 2821 }
2822 for (i = 0; i < 4; i++) {
2823 env->dr[i] = dbgregs.db[i];
2824 }
2825 env->dr[4] = env->dr[6] = dbgregs.dr6;
2826 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2827
2828 return 0;
2829}
2830
20d695a9 2831int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2832{
20d695a9 2833 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2834 int ret;
2835
2fa45344 2836 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2837
48e1a45c 2838 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2839 ret = kvm_put_msr_feature_control(x86_cpu);
2840 if (ret < 0) {
2841 return ret;
2842 }
2843 }
2844
36f96c4b
HZ		 2845 if (level == KVM_PUT_FULL_STATE) {
2846 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2847 * because TSC frequency mismatch shouldn't abort migration,
2848 * unless the user explicitly asked for a more strict TSC
2849 * setting (e.g. using an explicit "tsc-freq" option).
2850 */
2851 kvm_arch_set_tsc_khz(cpu);
2852 }
2853
1bc22652 2854 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2855 if (ret < 0) {
05330448 2856 return ret;
b9bec74b 2857 }
1bc22652 2858 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2859 if (ret < 0) {
f1665b21 2860 return ret;
b9bec74b 2861 }
1bc22652 2862 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2863 if (ret < 0) {
05330448 2864 return ret;
b9bec74b 2865 }
1bc22652 2866 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2867 if (ret < 0) {
05330448 2868 return ret;
b9bec74b 2869 }
ab443475 2870 /* must be before kvm_put_msrs */
1bc22652 2871 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2872 if (ret < 0) {
2873 return ret;
2874 }
1bc22652 2875 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2876 if (ret < 0) {
05330448 2877 return ret;
b9bec74b 2878 }
4fadfa00
PH		 2879 ret = kvm_put_vcpu_events(x86_cpu, level);
2880 if (ret < 0) {
2881 return ret;
2882 }
ea643051 2883 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2884 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2885 if (ret < 0) {
680c1c6f
JK		 2886 return ret;
2887 }
ea643051 2888 }
7477cd38
MT		 2889
2890 ret = kvm_put_tscdeadline_msr(x86_cpu);
2891 if (ret < 0) {
2892 return ret;
2893 }
1bc22652 2894 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2895 if (ret < 0) {
b0b1d690 2896 return ret;
b9bec74b 2897 }
b0b1d690 2898 /* must be last */
1bc22652 2899 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2900 if (ret < 0) {
ff44f1a3 2901 return ret;
b9bec74b 2902 }
05330448
AL		 2903 return 0;
2904}
2905
20d695a9 2906int kvm_arch_get_registers(CPUState *cs)
05330448 2907{
20d695a9 2908 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2909 int ret;
2910
20d695a9 2911 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2912
4fadfa00 2913 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2914 if (ret < 0) {
f4f1110e 2915 goto out;
b9bec74b 2916 }
4fadfa00
PH		 2917 /*
2918 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2919 * KVM_GET_REGS and KVM_GET_SREGS.
2920 */
2921 ret = kvm_get_mp_state(cpu);
b9bec74b 2922 if (ret < 0) {
f4f1110e 2923 goto out;
b9bec74b 2924 }
4fadfa00 2925 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2926 if (ret < 0) {
f4f1110e 2927 goto out;
b9bec74b 2928 }
4fadfa00 2929 ret = kvm_get_xsave(cpu);
b9bec74b 2930 if (ret < 0) {
f4f1110e 2931 goto out;
b9bec74b 2932 }
4fadfa00 2933 ret = kvm_get_xcrs(cpu);
b9bec74b 2934 if (ret < 0) {
f4f1110e 2935 goto out;
b9bec74b 2936 }
4fadfa00 2937 ret = kvm_get_sregs(cpu);
b9bec74b 2938 if (ret < 0) {
f4f1110e 2939 goto out;
b9bec74b 2940 }
4fadfa00 2941 ret = kvm_get_msrs(cpu);
680c1c6f 2942 if (ret < 0) {
f4f1110e 2943 goto out;
680c1c6f 2944 }
4fadfa00 2945 ret = kvm_get_apic(cpu);
b9bec74b 2946 if (ret < 0) {
f4f1110e 2947 goto out;
b9bec74b 2948 }
1bc22652 2949 ret = kvm_get_debugregs(cpu);
b9bec74b 2950 if (ret < 0) {
f4f1110e 2951 goto out;
b9bec74b 2952 }
f4f1110e
RH		 2953 ret = 0;
2954 out:
2955 cpu_sync_bndcs_hflags(&cpu->env);
2956 return ret;
05330448
AL		 2957}
2958
20d695a9 2959void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2960{
20d695a9
AF		 2961 X86CPU *x86_cpu = X86_CPU(cpu);
2962 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2963 int ret;
2964
276ce815 2965 /* Inject NMI */
fc12d72e
PB		 2966 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2967 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2968 qemu_mutex_lock_iothread();
2969 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2970 qemu_mutex_unlock_iothread();
2971 DPRINTF("injected NMI\n");
2972 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2973 if (ret < 0) {
2974 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2975 strerror(-ret));
2976 }
2977 }
2978 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2979 qemu_mutex_lock_iothread();
2980 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2981 qemu_mutex_unlock_iothread();
2982 DPRINTF("injected SMI\n");
2983 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2984 if (ret < 0) {
2985 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2986 strerror(-ret));
2987 }
ce377af3 2988 }
276ce815
LJ		 2989 }
2990
15eafc2e 2991 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2992 qemu_mutex_lock_iothread();
2993 }
2994
e0723c45
PB		 2995 /* Force the VCPU out of its inner loop to process any INIT requests
2996 * or (for userspace APIC, but it is cheap to combine the checks here)
2997 * pending TPR access reports.
2998 */
2999 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3000 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3001 !(env->hflags & HF_SMM_MASK)) {
3002 cpu->exit_request = 1;
3003 }
3004 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3005 cpu->exit_request = 1;
3006 }
e0723c45 3007 }
05330448 3008
15eafc2e 3009 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3010 /* Try to inject an interrupt if the guest can accept it */
3011 if (run->ready_for_interrupt_injection &&
259186a7 3012 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3013 (env->eflags & IF_MASK)) {
3014 int irq;
3015
259186a7 3016 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3017 irq = cpu_get_pic_interrupt(env);
3018 if (irq >= 0) {
3019 struct kvm_interrupt intr;
3020
3021 intr.irq = irq;
db1669bc 3022 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3023 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3024 if (ret < 0) {
3025 fprintf(stderr,
3026 "KVM: injection failed, interrupt lost (%s)\n",
3027 strerror(-ret));
3028 }
db1669bc
JK		 3029 }
3030 }
05330448 3031
db1669bc
JK		 3032 /* If we have an interrupt but the guest is not ready to receive an
3033 * interrupt, request an interrupt window exit. This will
3034 * cause a return to userspace as soon as the guest is ready to
3035 * receive interrupts. */
259186a7 3036 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3037 run->request_interrupt_window = 1;
3038 } else {
3039 run->request_interrupt_window = 0;
3040 }
3041
3042 DPRINTF("setting tpr\n");
02e51483 3043 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3044
3045 qemu_mutex_unlock_iothread();
db1669bc 3046 }
05330448
AL		 3047}
3048
4c663752 3049MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3050{
20d695a9
AF		 3051 X86CPU *x86_cpu = X86_CPU(cpu);
3052 CPUX86State *env = &x86_cpu->env;
3053
fc12d72e
PB		 3054 if (run->flags & KVM_RUN_X86_SMM) {
3055 env->hflags |= HF_SMM_MASK;
3056 } else {
f5c052b9 3057 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3058 }
b9bec74b 3059 if (run->if_flag) {
05330448 3060 env->eflags |= IF_MASK;
b9bec74b 3061 } else {
05330448 3062 env->eflags &= ~IF_MASK;
b9bec74b 3063 }
4b8523ee
JK		 3064
3065 /* We need to protect the apic state against concurrent accesses from
3066 * different threads in case the userspace irqchip is used. */
3067 if (!kvm_irqchip_in_kernel()) {
3068 qemu_mutex_lock_iothread();
3069 }
02e51483
CF		 3070 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3071 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3072 if (!kvm_irqchip_in_kernel()) {
3073 qemu_mutex_unlock_iothread();
3074 }
f794aa4a 3075 return cpu_get_mem_attrs(env);
05330448
AL		 3076}
3077
20d695a9 3078int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3079{
20d695a9
AF		 3080 X86CPU *cpu = X86_CPU(cs);
3081 CPUX86State *env = &cpu->env;
232fc23b 3082
259186a7 3083 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3084 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3085 assert(env->mcg_cap);
3086
259186a7 3087 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3088
dd1750d7 3089 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3090
3091 if (env->exception_injected == EXCP08_DBLE) {
3092 /* this means triple fault */
cf83f140 3093 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3094 cs->exit_request = 1;
ab443475
JK		 3095 return 0;
3096 }
3097 env->exception_injected = EXCP12_MCHK;
3098 env->has_error_code = 0;
3099
259186a7 3100 cs->halted = 0;
ab443475
JK		 3101 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3102 env->mp_state = KVM_MP_STATE_RUNNABLE;
3103 }
3104 }
3105
fc12d72e
PB		 3106 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3107 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3108 kvm_cpu_synchronize_state(cs);
3109 do_cpu_init(cpu);
3110 }
3111
db1669bc
JK		 3112 if (kvm_irqchip_in_kernel()) {
3113 return 0;
3114 }
3115
259186a7
AF		 3116 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3117 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3118 apic_poll_irq(cpu->apic_state);
5d62c43a 3119 }
259186a7 3120 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3121 (env->eflags & IF_MASK)) ||
259186a7
AF		 3122 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3123 cs->halted = 0;
6792a57b 3124 }
259186a7 3125 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3126 kvm_cpu_synchronize_state(cs);
232fc23b 3127 do_cpu_sipi(cpu);
0af691d7 3128 }
259186a7
AF		 3129 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3130 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3131 kvm_cpu_synchronize_state(cs);
02e51483 3132 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3133 env->tpr_access_type);
3134 }
0af691d7 3135
259186a7 3136 return cs->halted;
0af691d7
MT		 3137}
3138
839b5630 3139static int kvm_handle_halt(X86CPU *cpu)
05330448 3140{
259186a7 3141 CPUState *cs = CPU(cpu);
839b5630
AF		 3142 CPUX86State *env = &cpu->env;
3143
259186a7 3144 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3145 (env->eflags & IF_MASK)) &&
259186a7
AF		 3146 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3147 cs->halted = 1;
bb4ea393 3148 return EXCP_HLT;
05330448
AL		 3149 }
3150
bb4ea393 3151 return 0;
05330448
AL		 3152}
3153
f7575c96 3154static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3155{
f7575c96
AF		 3156 CPUState *cs = CPU(cpu);
3157 struct kvm_run *run = cs->kvm_run;
d362e757 3158
02e51483 3159 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3160 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3161 : TPR_ACCESS_READ);
3162 return 1;
3163}
3164
f17ec444 3165int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3166{
38972938 3167 static const uint8_t int3 = 0xcc;
64bf3f4e 3168
f17ec444
AF		 3169 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3170 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3171 return -EINVAL;
b9bec74b 3172 }
e22a25c9
AL		 3173 return 0;
3174}
3175
f17ec444 3176int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3177{
3178 uint8_t int3;
3179
f17ec444
AF		 3180 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3181 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3182 return -EINVAL;
b9bec74b 3183 }
e22a25c9
AL		 3184 return 0;
3185}
3186
3187static struct {
3188 target_ulong addr;
3189 int len;
3190 int type;
3191} hw_breakpoint[4];
3192
3193static int nb_hw_breakpoint;
3194
3195static int find_hw_breakpoint(target_ulong addr, int len, int type)
3196{
3197 int n;
3198
b9bec74b 3199 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3200 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3201 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3202 return n;
b9bec74b
JK		 3203 }
3204 }
e22a25c9
AL		 3205 return -1;
3206}
3207
3208int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3209 target_ulong len, int type)
3210{
3211 switch (type) {
3212 case GDB_BREAKPOINT_HW:
3213 len = 1;
3214 break;
3215 case GDB_WATCHPOINT_WRITE:
3216 case GDB_WATCHPOINT_ACCESS:
3217 switch (len) {
3218 case 1:
3219 break;
3220 case 2:
3221 case 4:
3222 case 8:
b9bec74b 3223 if (addr & (len - 1)) {
e22a25c9 3224 return -EINVAL;
b9bec74b 3225 }
e22a25c9
AL		 3226 break;
3227 default:
3228 return -EINVAL;
3229 }
3230 break;
3231 default:
3232 return -ENOSYS;
3233 }
3234
b9bec74b 3235 if (nb_hw_breakpoint == 4) {
e22a25c9 3236 return -ENOBUFS;
b9bec74b
JK		 3237 }
3238 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3239 return -EEXIST;
b9bec74b 3240 }
e22a25c9
AL		 3241 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3242 hw_breakpoint[nb_hw_breakpoint].len = len;
3243 hw_breakpoint[nb_hw_breakpoint].type = type;
3244 nb_hw_breakpoint++;
3245
3246 return 0;
3247}
3248
3249int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3250 target_ulong len, int type)
3251{
3252 int n;
3253
3254 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3255 if (n < 0) {
e22a25c9 3256 return -ENOENT;
b9bec74b 3257 }
e22a25c9
AL		 3258 nb_hw_breakpoint--;
3259 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3260
3261 return 0;
3262}
3263
3264void kvm_arch_remove_all_hw_breakpoints(void)
3265{
3266 nb_hw_breakpoint = 0;
3267}
3268
3269static CPUWatchpoint hw_watchpoint;
3270
a60f24b5 3271static int kvm_handle_debug(X86CPU *cpu,
48405526 3272 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3273{
ed2803da 3274 CPUState *cs = CPU(cpu);
a60f24b5 3275 CPUX86State *env = &cpu->env;
f2574737 3276 int ret = 0;
e22a25c9
AL		 3277 int n;
3278
3279 if (arch_info->exception == 1) {
3280 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3281 if (cs->singlestep_enabled) {
f2574737 3282 ret = EXCP_DEBUG;
b9bec74b 3283 }
e22a25c9 3284 } else {
b9bec74b
JK		 3285 for (n = 0; n < 4; n++) {
3286 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3287 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3288 case 0x0:
f2574737 3289 ret = EXCP_DEBUG;
e22a25c9
AL		 3290 break;
3291 case 0x1:
f2574737 3292 ret = EXCP_DEBUG;
ff4700b0 3293 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3294 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3295 hw_watchpoint.flags = BP_MEM_WRITE;
3296 break;
3297 case 0x3:
f2574737 3298 ret = EXCP_DEBUG;
ff4700b0 3299 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3300 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3301 hw_watchpoint.flags = BP_MEM_ACCESS;
3302 break;
3303 }
b9bec74b
JK		 3304 }
3305 }
e22a25c9 3306 }
ff4700b0 3307 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3308 ret = EXCP_DEBUG;
b9bec74b 3309 }
f2574737 3310 if (ret == 0) {
ff4700b0 3311 cpu_synchronize_state(cs);
48405526 3312 assert(env->exception_injected == -1);
b0b1d690 3313
f2574737 3314 /* pass to guest */
48405526
BS		 3315 env->exception_injected = arch_info->exception;
3316 env->has_error_code = 0;
b0b1d690 3317 }
e22a25c9 3318
f2574737 3319 return ret;
e22a25c9
AL		 3320}
3321
20d695a9 3322void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3323{
3324 const uint8_t type_code[] = {
3325 [GDB_BREAKPOINT_HW] = 0x0,
3326 [GDB_WATCHPOINT_WRITE] = 0x1,
3327 [GDB_WATCHPOINT_ACCESS] = 0x3
3328 };
3329 const uint8_t len_code[] = {
3330 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3331 };
3332 int n;
3333
a60f24b5 3334 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3335 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3336 }
e22a25c9
AL		 3337 if (nb_hw_breakpoint > 0) {
3338 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3339 dbg->arch.debugreg[7] = 0x0600;
3340 for (n = 0; n < nb_hw_breakpoint; n++) {
3341 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3342 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3343 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3344 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3345 }
3346 }
3347}
4513d923 3348
2a4dac83
JK		 3349static bool host_supports_vmx(void)
3350{
3351 uint32_t ecx, unused;
3352
3353 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3354 return ecx & CPUID_EXT_VMX;
3355}
3356
3357#define VMX_INVALID_GUEST_STATE 0x80000021
3358
20d695a9 3359int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3360{
20d695a9 3361 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3362 uint64_t code;
3363 int ret;
3364
3365 switch (run->exit_reason) {
3366 case KVM_EXIT_HLT:
3367 DPRINTF("handle_hlt\n");
4b8523ee 3368 qemu_mutex_lock_iothread();
839b5630 3369 ret = kvm_handle_halt(cpu);
4b8523ee 3370 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3371 break;
3372 case KVM_EXIT_SET_TPR:
3373 ret = 0;
3374 break;
d362e757 3375 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3376 qemu_mutex_lock_iothread();
f7575c96 3377 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3378 qemu_mutex_unlock_iothread();
d362e757 3379 break;
2a4dac83
JK		 3380 case KVM_EXIT_FAIL_ENTRY:
3381 code = run->fail_entry.hardware_entry_failure_reason;
3382 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3383 code);
3384 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3385 fprintf(stderr,
12619721 3386 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3387 "unrestricted mode\n"
3388 "support, the failure can be most likely due to the guest "
3389 "entering an invalid\n"
3390 "state for Intel VT. For example, the guest maybe running "
3391 "in big real mode\n"
3392 "which is not supported on less recent Intel processors."
3393 "\n\n");
3394 }
3395 ret = -1;
3396 break;
3397 case KVM_EXIT_EXCEPTION:
3398 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3399 run->ex.exception, run->ex.error_code);
3400 ret = -1;
3401 break;
f2574737
JK		 3402 case KVM_EXIT_DEBUG:
3403 DPRINTF("kvm_exit_debug\n");
4b8523ee 3404 qemu_mutex_lock_iothread();
a60f24b5 3405 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3406 qemu_mutex_unlock_iothread();
f2574737 3407 break;
50efe82c
AS		 3408 case KVM_EXIT_HYPERV:
3409 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3410 break;
15eafc2e
PB		 3411 case KVM_EXIT_IOAPIC_EOI:
3412 ioapic_eoi_broadcast(run->eoi.vector);
3413 ret = 0;
3414 break;
2a4dac83
JK		 3415 default:
3416 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3417 ret = -1;
3418 break;
3419 }
3420
3421 return ret;
3422}
3423
20d695a9 3424bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3425{
20d695a9
AF		 3426 X86CPU *cpu = X86_CPU(cs);
3427 CPUX86State *env = &cpu->env;
3428
dd1750d7 3429 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3430 return !(env->cr[0] & CR0_PE_MASK) ||
3431 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3432}
84b058d7
JK		 3433
3434void kvm_arch_init_irq_routing(KVMState *s)
3435{
3436 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3437 /* If kernel can't do irq routing, interrupt source
3438 * override 0->2 cannot be set up as required by HPET.
3439 * So we have to disable it.
3440 */
3441 no_hpet = 1;
3442 }
cc7e0ddf 3443 /* We know at this point that we're using the in-kernel
614e41bc 3444 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3445 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3446 */
614e41bc 3447 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3448 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3449
3450 if (kvm_irqchip_is_split()) {
3451 int i;
3452
3453 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3454 MSI routes for signaling interrupts to the local apics. */
3455 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3456 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3457 error_report("Could not enable split IRQ mode.");
3458 exit(1);
3459 }
3460 }
3461 }
3462}
3463
3464int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3465{
3466 int ret;
3467 if (machine_kernel_irqchip_split(ms)) {
3468 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3469 if (ret) {
df3c286c 3470 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3471 strerror(-ret));
3472 exit(1);
3473 } else {
3474 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3475 kvm_split_irqchip = true;
3476 return 1;
3477 }
3478 } else {
3479 return 0;
3480 }
84b058d7 3481}
b139bd30
JK		 3482
3483/* Classic KVM device assignment interface. Will remain x86 only. */
3484int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3485 uint32_t flags, uint32_t *dev_id)
3486{
3487 struct kvm_assigned_pci_dev dev_data = {
3488 .segnr = dev_addr->domain,
3489 .busnr = dev_addr->bus,
3490 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3491 .flags = flags,
3492 };
3493 int ret;
3494
3495 dev_data.assigned_dev_id =
3496 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3497
3498 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3499 if (ret < 0) {
3500 return ret;
3501 }
3502
3503 *dev_id = dev_data.assigned_dev_id;
3504
3505 return 0;
3506}
3507
3508int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3509{
3510 struct kvm_assigned_pci_dev dev_data = {
3511 .assigned_dev_id = dev_id,
3512 };
3513
3514 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3515}
3516
3517static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3518 uint32_t irq_type, uint32_t guest_irq)
3519{
3520 struct kvm_assigned_irq assigned_irq = {
3521 .assigned_dev_id = dev_id,
3522 .guest_irq = guest_irq,
3523 .flags = irq_type,
3524 };
3525
3526 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3527 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3528 } else {
3529 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3530 }
3531}
3532
3533int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3534 uint32_t guest_irq)
3535{
3536 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3537 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3538
3539 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3540}
3541
3542int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3543{
3544 struct kvm_assigned_pci_dev dev_data = {
3545 .assigned_dev_id = dev_id,
3546 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3547 };
3548
3549 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3550}
3551
3552static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3553 uint32_t type)
3554{
3555 struct kvm_assigned_irq assigned_irq = {
3556 .assigned_dev_id = dev_id,
3557 .flags = type,
3558 };
3559
3560 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3561}
3562
3563int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3564{
3565 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3566 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3567}
3568
3569int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3570{
3571 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3572 KVM_DEV_IRQ_GUEST_MSI, virq);
3573}
3574
3575int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3576{
3577 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3578 KVM_DEV_IRQ_HOST_MSI);
3579}
3580
3581bool kvm_device_msix_supported(KVMState *s)
3582{
3583 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3584 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3585 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3586}
3587
3588int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3589 uint32_t nr_vectors)
3590{
3591 struct kvm_assigned_msix_nr msix_nr = {
3592 .assigned_dev_id = dev_id,
3593 .entry_nr = nr_vectors,
3594 };
3595
3596 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3597}
3598
3599int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3600 int virq)
3601{
3602 struct kvm_assigned_msix_entry msix_entry = {
3603 .assigned_dev_id = dev_id,
3604 .gsi = virq,
3605 .entry = vector,
3606 };
3607
3608 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3609}
3610
3611int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3612{
3613 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3614 KVM_DEV_IRQ_GUEST_MSIX, 0);
3615}
3616
3617int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3618{
3619 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3620 KVM_DEV_IRQ_HOST_MSIX);
3621}
9e03a040
FB		 3622
3623int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3624 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3625{
8b5ed7df
PX		 3626 X86IOMMUState *iommu = x86_iommu_get_default();
3627
3628 if (iommu) {
3629 int ret;
3630 MSIMessage src, dst;
3631 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3632
3633 src.address = route->u.msi.address_hi;
3634 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3635 src.address |= route->u.msi.address_lo;
3636 src.data = route->u.msi.data;
3637
3638 ret = class->int_remap(iommu, &src, &dst, dev ? \
3639 pci_requester_id(dev) : \
3640 X86_IOMMU_SID_INVALID);
3641 if (ret) {
3642 trace_kvm_x86_fixup_msi_error(route->gsi);
3643 return 1;
3644 }
3645
3646 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3647 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3648 route->u.msi.data = dst.data;
3649 }
3650
9e03a040
FB		 3651 return 0;
3652}
1850b6b7 3653
38d87493
PX		 3654typedef struct MSIRouteEntry MSIRouteEntry;
3655
3656struct MSIRouteEntry {
3657 PCIDevice *dev; /* Device pointer */
3658 int vector; /* MSI/MSIX vector index */
3659 int virq; /* Virtual IRQ index */
3660 QLIST_ENTRY(MSIRouteEntry) list;
3661};
3662
3663/* List of used GSI routes */
3664static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3665 QLIST_HEAD_INITIALIZER(msi_route_list);
3666
e1d4fb2d
PX		 3667static void kvm_update_msi_routes_all(void *private, bool global,
3668 uint32_t index, uint32_t mask)
3669{
3670 int cnt = 0;
3671 MSIRouteEntry *entry;
3672 MSIMessage msg;
fd563564
PX		 3673 PCIDevice *dev;
3674
e1d4fb2d
PX		 3675 /* TODO: explicit route update */
3676 QLIST_FOREACH(entry, &msi_route_list, list) {
3677 cnt++;
fd563564
PX		 3678 dev = entry->dev;
3679 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3680 continue;
3681 }
3682 msg = pci_get_msi_message(dev, entry->vector);
3683 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3684 }
3f1fea0f 3685 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3686 trace_kvm_x86_update_msi_routes(cnt);
3687}
3688
38d87493
PX		 3689int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3690 int vector, PCIDevice *dev)
3691{
e1d4fb2d 3692 static bool notify_list_inited = false;
38d87493
PX		 3693 MSIRouteEntry *entry;
3694
3695 if (!dev) {
3696 /* These are (possibly) IOAPIC routes only used for split
3697 * kernel irqchip mode, while what we are housekeeping are
3698 * PCI devices only. */
3699 return 0;
3700 }
3701
3702 entry = g_new0(MSIRouteEntry, 1);
3703 entry->dev = dev;
3704 entry->vector = vector;
3705 entry->virq = route->gsi;
3706 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3707
3708 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3709
3710 if (!notify_list_inited) {
3711 /* For the first time we do add route, add ourselves into
3712 * IOMMU's IEC notify list if needed. */
3713 X86IOMMUState *iommu = x86_iommu_get_default();
3714 if (iommu) {
3715 x86_iommu_iec_register_notifier(iommu,
3716 kvm_update_msi_routes_all,
3717 NULL);
3718 }
3719 notify_list_inited = true;
3720 }
38d87493
PX		 3721 return 0;
3722}
3723
3724int kvm_arch_release_virq_post(int virq)
3725{
3726 MSIRouteEntry *entry, *next;
3727 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3728 if (entry->virq == virq) {
3729 trace_kvm_x86_remove_msi_route(virq);
3730 QLIST_REMOVE(entry, list);
01960e6d 3731 g_free(entry);
38d87493
PX		 3732 break;
3733 }
3734 }
9e03a040
FB		 3735 return 0;
3736}
1850b6b7
EA		 3737
3738int kvm_arch_msi_data_to_gsi(uint32_t data)
3739{
3740 abort();
3741}
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