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i386/cpu: make -cpu host support monitor/mwait
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
a2cb15b0 43#include "hw/pci/pci.h"
15eafc2e 44#include "hw/pci/msi.h"
fd563564 45#include "hw/pci/msix.h"
795c40b8 46#include "migration/blocker.h"
4c663752 47#include "exec/memattrs.h"
8b5ed7df 48#include "trace.h"
05330448
AL		 49
50//#define DEBUG_KVM
51
52#ifdef DEBUG_KVM
8c0d577e 53#define DPRINTF(fmt, ...) \
05330448
AL		 54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55#else
8c0d577e 56#define DPRINTF(fmt, ...) \
05330448
AL		 57 do { } while (0)
58#endif
59
1a03675d
GC		 60#define MSR_KVM_WALL_CLOCK 0x11
61#define MSR_KVM_SYSTEM_TIME 0x12
62
d1138251
EH		 63/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65#define MSR_BUF_SIZE 4096
d71b62a1 66
94a8d39a
JK		 67const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72};
25d2e361 73
c3a3a7d3
JK		 74static bool has_msr_star;
75static bool has_msr_hsave_pa;
c9b8f6b6 76static bool has_msr_tsc_aux;
f28558d3 77static bool has_msr_tsc_adjust;
aa82ba54 78static bool has_msr_tsc_deadline;
df67696e 79static bool has_msr_feature_control;
21e87c46 80static bool has_msr_misc_enable;
fc12d72e 81static bool has_msr_smbase;
79e9ebeb 82static bool has_msr_bndcfgs;
25d2e361 83static int lm_capable_kernel;
7bc3d711 84static bool has_msr_hv_hypercall;
f2a53c9e 85static bool has_msr_hv_crash;
744b8a94 86static bool has_msr_hv_reset;
8c145d7c 87static bool has_msr_hv_vpindex;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
b827df58 97
0b368a10
JD		 98static uint32_t has_architectural_pmu_version;
99static uint32_t num_architectural_pmu_gp_counters;
100static uint32_t num_architectural_pmu_fixed_counters;
0d894367 101
28143b40
TH		 102static int has_xsave;
103static int has_xcrs;
104static int has_pit_state2;
105
87f8b626
AR		 106static bool has_msr_mcg_ext_ctl;
107
494e95e9
CP		 108static struct kvm_cpuid2 *cpuid_cache;
109
28143b40
TH		 110int kvm_has_pit_state2(void)
111{
112 return has_pit_state2;
113}
114
355023f2
PB		 115bool kvm_has_smm(void)
116{
117 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
118}
119
6053a86f
MT		 120bool kvm_has_adjust_clock_stable(void)
121{
122 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
123
124 return (ret == KVM_CLOCK_TSC_STABLE);
125}
126
1d31f66b
PM		 127bool kvm_allows_irq0_override(void)
128{
129 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
130}
131
fb506e70
RK		 132static bool kvm_x2apic_api_set_flags(uint64_t flags)
133{
134 KVMState *s = KVM_STATE(current_machine->accelerator);
135
136 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
137}
138
e391c009 139#define MEMORIZE(fn, _result) \
2a138ec3 140 ({ \
2a138ec3
RK		 141 static bool _memorized; \
142 \
143 if (_memorized) { \
144 return _result; \
145 } \
146 _memorized = true; \
147 _result = fn; \
148 })
149
e391c009
IM		 150static bool has_x2apic_api;
151
152bool kvm_has_x2apic_api(void)
153{
154 return has_x2apic_api;
155}
156
fb506e70
RK		 157bool kvm_enable_x2apic(void)
158{
2a138ec3
RK		 159 return MEMORIZE(
160 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 161 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
162 has_x2apic_api);
fb506e70
RK		 163}
164
0fd7e098
LL		 165static int kvm_get_tsc(CPUState *cs)
166{
167 X86CPU *cpu = X86_CPU(cs);
168 CPUX86State *env = &cpu->env;
169 struct {
170 struct kvm_msrs info;
171 struct kvm_msr_entry entries[1];
172 } msr_data;
173 int ret;
174
175 if (env->tsc_valid) {
176 return 0;
177 }
178
179 msr_data.info.nmsrs = 1;
180 msr_data.entries[0].index = MSR_IA32_TSC;
181 env->tsc_valid = !runstate_is_running();
182
183 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
184 if (ret < 0) {
185 return ret;
186 }
187
48e1a45c 188 assert(ret == 1);
0fd7e098
LL		 189 env->tsc = msr_data.entries[0].data;
190 return 0;
191}
192
14e6fe12 193static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 194{
0fd7e098
LL		 195 kvm_get_tsc(cpu);
196}
197
198void kvm_synchronize_all_tsc(void)
199{
200 CPUState *cpu;
201
202 if (kvm_enabled()) {
203 CPU_FOREACH(cpu) {
14e6fe12 204 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 205 }
206 }
207}
208
b827df58
AK		 209static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
210{
211 struct kvm_cpuid2 *cpuid;
212 int r, size;
213
214 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 215 cpuid = g_malloc0(size);
b827df58
AK		 216 cpuid->nent = max;
217 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 218 if (r == 0 && cpuid->nent >= max) {
219 r = -E2BIG;
220 }
b827df58
AK		 221 if (r < 0) {
222 if (r == -E2BIG) {
7267c094 223 g_free(cpuid);
b827df58
AK		 224 return NULL;
225 } else {
226 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
227 strerror(-r));
228 exit(1);
229 }
230 }
231 return cpuid;
232}
233
dd87f8a6
EH		 234/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
235 * for all entries.
236 */
237static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
238{
239 struct kvm_cpuid2 *cpuid;
240 int max = 1;
494e95e9
CP		 241
242 if (cpuid_cache != NULL) {
243 return cpuid_cache;
244 }
dd87f8a6
EH		 245 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
246 max *= 2;
247 }
494e95e9 248 cpuid_cache = cpuid;
dd87f8a6
EH		 249 return cpuid;
250}
251
a443bc34 252static const struct kvm_para_features {
0c31b744
GC		 253 int cap;
254 int feature;
255} para_features[] = {
256 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
257 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
258 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 259 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 260};
261
ba9bc59e 262static int get_para_features(KVMState *s)
0c31b744
GC		 263{
264 int i, features = 0;
265
8e03c100 266 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 267 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 268 features |= (1 << para_features[i].feature);
269 }
270 }
271
272 return features;
273}
0c31b744 274
40e80ee4
EH		 275static bool host_tsx_blacklisted(void)
276{
277 int family, model, stepping;\
278 char vendor[CPUID_VENDOR_SZ + 1];
279
280 host_vendor_fms(vendor, &family, &model, &stepping);
281
282 /* Check if we are running on a Haswell host known to have broken TSX */
283 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
284 (family == 6) &&
285 ((model == 63 && stepping < 4) ||
286 model == 60 || model == 69 || model == 70);
287}
0c31b744 288
829ae2f9
EH		 289/* Returns the value for a specific register on the cpuid entry
290 */
291static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
292{
293 uint32_t ret = 0;
294 switch (reg) {
295 case R_EAX:
296 ret = entry->eax;
297 break;
298 case R_EBX:
299 ret = entry->ebx;
300 break;
301 case R_ECX:
302 ret = entry->ecx;
303 break;
304 case R_EDX:
305 ret = entry->edx;
306 break;
307 }
308 return ret;
309}
310
4fb73f1d
EH		 311/* Find matching entry for function/index on kvm_cpuid2 struct
312 */
313static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
314 uint32_t function,
315 uint32_t index)
316{
317 int i;
318 for (i = 0; i < cpuid->nent; ++i) {
319 if (cpuid->entries[i].function == function &&
320 cpuid->entries[i].index == index) {
321 return &cpuid->entries[i];
322 }
323 }
324 /* not found: */
325 return NULL;
326}
327
ba9bc59e 328uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 329 uint32_t index, int reg)
b827df58
AK		 330{
331 struct kvm_cpuid2 *cpuid;
b827df58
AK		 332 uint32_t ret = 0;
333 uint32_t cpuid_1_edx;
8c723b79 334 bool found = false;
b827df58 335
dd87f8a6 336 cpuid = get_supported_cpuid(s);
b827df58 337
4fb73f1d
EH		 338 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
339 if (entry) {
340 found = true;
341 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 342 }
343
7b46e5ce
EH		 344 /* Fixups for the data returned by KVM, below */
345
c2acb022
EH		 346 if (function == 1 && reg == R_EDX) {
347 /* KVM before 2.6.30 misreports the following features */
348 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 349 } else if (function == 1 && reg == R_ECX) {
350 /* We can set the hypervisor flag, even if KVM does not return it on
351 * GET_SUPPORTED_CPUID
352 */
353 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 354 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
355 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
356 * and the irqchip is in the kernel.
357 */
358 if (kvm_irqchip_in_kernel() &&
359 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
360 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
361 }
41e5e76d
EH		 362
363 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
364 * without the in-kernel irqchip
365 */
366 if (!kvm_irqchip_in_kernel()) {
367 ret &= ~CPUID_EXT_X2APIC;
b827df58 368 }
2266d443
MT		 369
370 if (enable_cpu_pm) {
371 int disable_exits = kvm_check_extension(s,
372 KVM_CAP_X86_DISABLE_EXITS);
373
374 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
375 ret |= CPUID_EXT_MONITOR;
376 }
377 }
28b8e4d0
JK		 378 } else if (function == 6 && reg == R_EAX) {
379 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 380 } else if (function == 7 && index == 0 && reg == R_EBX) {
381 if (host_tsx_blacklisted()) {
382 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
383 }
f98bbd83
BM		 384 } else if (function == 0x80000001 && reg == R_ECX) {
385 /*
386 * It's safe to enable TOPOEXT even if it's not returned by
387 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
388 * us to keep CPU models including TOPOEXT runnable on older kernels.
389 */
390 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 391 } else if (function == 0x80000001 && reg == R_EDX) {
392 /* On Intel, kvm returns cpuid according to the Intel spec,
393 * so add missing bits according to the AMD spec:
394 */
395 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
396 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 397 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
398 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
399 * be enabled without the in-kernel irqchip
400 */
401 if (!kvm_irqchip_in_kernel()) {
402 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
403 }
be777326 404 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 405 ret |= 1U << KVM_HINTS_REALTIME;
be777326 406 found = 1;
b827df58
AK		 407 }
408
0c31b744 409 /* fallback for older kernels */
8c723b79 410 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 411 ret = get_para_features(s);
b9bec74b 412 }
0c31b744
GC		 413
414 return ret;
bb0300dc 415}
bb0300dc 416
3c85e74f
HY		 417typedef struct HWPoisonPage {
418 ram_addr_t ram_addr;
419 QLIST_ENTRY(HWPoisonPage) list;
420} HWPoisonPage;
421
422static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
423 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
424
425static void kvm_unpoison_all(void *param)
426{
427 HWPoisonPage *page, *next_page;
428
429 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
430 QLIST_REMOVE(page, list);
431 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 432 g_free(page);
3c85e74f
HY		 433 }
434}
435
3c85e74f
HY		 436static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
437{
438 HWPoisonPage *page;
439
440 QLIST_FOREACH(page, &hwpoison_page_list, list) {
441 if (page->ram_addr == ram_addr) {
442 return;
443 }
444 }
ab3ad07f 445 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 446 page->ram_addr = ram_addr;
447 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
448}
449
e7701825
MT		 450static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
451 int *max_banks)
452{
453 int r;
454
14a09518 455 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 456 if (r > 0) {
457 *max_banks = r;
458 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
459 }
460 return -ENOSYS;
461}
462
bee615d4 463static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 464{
87f8b626 465 CPUState *cs = CPU(cpu);
bee615d4 466 CPUX86State *env = &cpu->env;
c34d440a
JK		 467 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
468 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
469 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 470 int flags = 0;
e7701825 471
c34d440a
JK		 472 if (code == BUS_MCEERR_AR) {
473 status |= MCI_STATUS_AR | 0x134;
474 mcg_status |= MCG_STATUS_EIPV;
475 } else {
476 status |= 0xc0;
477 mcg_status |= MCG_STATUS_RIPV;
419fb20a 478 }
87f8b626
AR		 479
480 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
481 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
482 * guest kernel back into env->mcg_ext_ctl.
483 */
484 cpu_synchronize_state(cs);
485 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
486 mcg_status |= MCG_STATUS_LMCE;
487 flags = 0;
488 }
489
8c5cf3b6 490 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 491 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 492}
419fb20a
JK		 493
494static void hardware_memory_error(void)
495{
496 fprintf(stderr, "Hardware memory error!\n");
497 exit(1);
498}
499
2ae41db2 500void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 501{
20d695a9
AF		 502 X86CPU *cpu = X86_CPU(c);
503 CPUX86State *env = &cpu->env;
419fb20a 504 ram_addr_t ram_addr;
a8170e5e 505 hwaddr paddr;
419fb20a 506
4d39892c
PB		 507 /* If we get an action required MCE, it has been injected by KVM
508 * while the VM was running. An action optional MCE instead should
509 * be coming from the main thread, which qemu_init_sigbus identifies
510 * as the "early kill" thread.
511 */
a16fc07e 512 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 513
20e0ff59 514 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 515 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 516 if (ram_addr != RAM_ADDR_INVALID &&
517 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
518 kvm_hwpoison_page_add(ram_addr);
519 kvm_mce_inject(cpu, paddr, code);
2ae41db2 520 return;
419fb20a 521 }
20e0ff59
PB		 522
523 fprintf(stderr, "Hardware memory error for memory used by "
524 "QEMU itself instead of guest system!\n");
419fb20a 525 }
20e0ff59
PB		 526
527 if (code == BUS_MCEERR_AR) {
528 hardware_memory_error();
529 }
530
531 /* Hope we are lucky for AO MCE */
419fb20a
JK		 532}
533
1bc22652 534static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 535{
1bc22652
AF		 536 CPUX86State *env = &cpu->env;
537
ab443475
JK		 538 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
539 unsigned int bank, bank_num = env->mcg_cap & 0xff;
540 struct kvm_x86_mce mce;
541
542 env->exception_injected = -1;
543
544 /*
545 * There must be at least one bank in use if an MCE is pending.
546 * Find it and use its values for the event injection.
547 */
548 for (bank = 0; bank < bank_num; bank++) {
549 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
550 break;
551 }
552 }
553 assert(bank < bank_num);
554
555 mce.bank = bank;
556 mce.status = env->mce_banks[bank * 4 + 1];
557 mce.mcg_status = env->mcg_status;
558 mce.addr = env->mce_banks[bank * 4 + 2];
559 mce.misc = env->mce_banks[bank * 4 + 3];
560
1bc22652 561 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 562 }
ab443475
JK		 563 return 0;
564}
565
1dfb4dd9 566static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 567{
317ac620 568 CPUX86State *env = opaque;
b8cc45d6
GC		 569
570 if (running) {
571 env->tsc_valid = false;
572 }
573}
574
83b17af5 575unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 576{
83b17af5 577 X86CPU *cpu = X86_CPU(cs);
7e72a45c 578 return cpu->apic_id;
b164e48e
EH		 579}
580
92067bf4
IM		 581#ifndef KVM_CPUID_SIGNATURE_NEXT
582#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
583#endif
584
585static bool hyperv_hypercall_available(X86CPU *cpu)
586{
587 return cpu->hyperv_vapic ||
588 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
589}
590
591static bool hyperv_enabled(X86CPU *cpu)
592{
7bc3d711
PB		 593 CPUState *cs = CPU(cpu);
594 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
595 (hyperv_hypercall_available(cpu) ||
48a5f3bc 596 cpu->hyperv_time ||
f2a53c9e 597 cpu->hyperv_relaxed_timing ||
744b8a94 598 cpu->hyperv_crash ||
8c145d7c 599 cpu->hyperv_reset ||
46eb8f98 600 cpu->hyperv_vpindex ||
866eea9a 601 cpu->hyperv_runtime ||
ff99aa64 602 cpu->hyperv_synic ||
ba6a4fd9
VK		 603 cpu->hyperv_stimer ||
604 cpu->hyperv_reenlightenment);
92067bf4
IM		 605}
606
5031283d
HZ		 607static int kvm_arch_set_tsc_khz(CPUState *cs)
608{
609 X86CPU *cpu = X86_CPU(cs);
610 CPUX86State *env = &cpu->env;
611 int r;
612
613 if (!env->tsc_khz) {
614 return 0;
615 }
616
617 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
618 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
619 -ENOTSUP;
620 if (r < 0) {
621 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
622 * TSC frequency doesn't match the one we want.
623 */
624 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
625 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
626 -ENOTSUP;
627 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 628 warn_report("TSC frequency mismatch between "
629 "VM (%" PRId64 " kHz) and host (%d kHz), "
630 "and TSC scaling unavailable",
631 env->tsc_khz, cur_freq);
5031283d
HZ		 632 return r;
633 }
634 }
635
636 return 0;
637}
638
4bb95b82
LP		 639static bool tsc_is_stable_and_known(CPUX86State *env)
640{
641 if (!env->tsc_khz) {
642 return false;
643 }
644 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
645 || env->user_tsc_khz;
646}
647
c35bd19a
EY		 648static int hyperv_handle_properties(CPUState *cs)
649{
650 X86CPU *cpu = X86_CPU(cs);
651 CPUX86State *env = &cpu->env;
652
653 if (cpu->hyperv_relaxed_timing) {
5e953812 654 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 655 }
656 if (cpu->hyperv_vapic) {
5e953812
RK		 657 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
658 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 659 }
3ddcd2ed 660 if (cpu->hyperv_time) {
1221f150
RK		 661 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
662 fprintf(stderr, "Hyper-V clocksources "
663 "(requested by 'hv-time' cpu flag) "
664 "are not supported by kernel\n");
665 return -ENOSYS;
666 }
5e953812
RK		 667 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
668 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
669 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
9445597b
RK		 670 }
671 if (cpu->hyperv_frequencies) {
672 if (!has_msr_hv_frequencies) {
673 fprintf(stderr, "Hyper-V frequency MSRs "
674 "(requested by 'hv-frequencies' cpu flag) "
675 "are not supported by kernel\n");
676 return -ENOSYS;
d72bc7f6 677 }
9445597b
RK		 678 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
679 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 680 }
1221f150
RK		 681 if (cpu->hyperv_crash) {
682 if (!has_msr_hv_crash) {
683 fprintf(stderr, "Hyper-V crash MSRs "
684 "(requested by 'hv-crash' cpu flag) "
685 "are not supported by kernel\n");
686 return -ENOSYS;
687 }
5e953812 688 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 689 }
ba6a4fd9
VK		 690 if (cpu->hyperv_reenlightenment) {
691 if (!has_msr_hv_reenlightenment) {
692 fprintf(stderr,
693 "Hyper-V Reenlightenment MSRs "
694 "(requested by 'hv-reenlightenment' cpu flag) "
695 "are not supported by kernel\n");
696 return -ENOSYS;
697 }
698 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
699 }
5e953812 700 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1221f150
RK		 701 if (cpu->hyperv_reset) {
702 if (!has_msr_hv_reset) {
703 fprintf(stderr, "Hyper-V reset MSR "
704 "(requested by 'hv-reset' cpu flag) "
705 "is not supported by kernel\n");
706 return -ENOSYS;
707 }
5e953812 708 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a 709 }
1221f150
RK		 710 if (cpu->hyperv_vpindex) {
711 if (!has_msr_hv_vpindex) {
712 fprintf(stderr, "Hyper-V VP_INDEX MSR "
713 "(requested by 'hv-vpindex' cpu flag) "
714 "is not supported by kernel\n");
715 return -ENOSYS;
716 }
5e953812 717 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a 718 }
1221f150
RK		 719 if (cpu->hyperv_runtime) {
720 if (!has_msr_hv_runtime) {
721 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
722 "(requested by 'hv-runtime' cpu flag) "
723 "is not supported by kernel\n");
724 return -ENOSYS;
725 }
5e953812 726 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 727 }
728 if (cpu->hyperv_synic) {
c35bd19a
EY		 729 if (!has_msr_hv_synic ||
730 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
731 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
732 return -ENOSYS;
733 }
734
5e953812 735 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a
EY		 736 }
737 if (cpu->hyperv_stimer) {
738 if (!has_msr_hv_stimer) {
739 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
740 return -ENOSYS;
741 }
5e953812 742 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a
EY		 743 }
744 return 0;
745}
746
68bfd0ad
MT		 747static Error *invtsc_mig_blocker;
748
f8bb0565 749#define KVM_MAX_CPUID_ENTRIES 100
0893d460 750
20d695a9 751int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 752{
753 struct {
486bd5a2 754 struct kvm_cpuid2 cpuid;
f8bb0565 755 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 756 } QEMU_PACKED cpuid_data;
20d695a9
AF		 757 X86CPU *cpu = X86_CPU(cs);
758 CPUX86State *env = &cpu->env;
486bd5a2 759 uint32_t limit, i, j, cpuid_i;
a33609ca 760 uint32_t unused;
bb0300dc 761 struct kvm_cpuid_entry2 *c;
bb0300dc 762 uint32_t signature[3];
234cc647 763 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 764 int r;
fe44dc91 765 Error *local_err = NULL;
05330448 766
ef4cbe14
SW		 767 memset(&cpuid_data, 0, sizeof(cpuid_data));
768
05330448
AL		 769 cpuid_i = 0;
770
ddb98b5a
LP		 771 r = kvm_arch_set_tsc_khz(cs);
772 if (r < 0) {
773 goto fail;
774 }
775
776 /* vcpu's TSC frequency is either specified by user, or following
777 * the value used by KVM if the former is not present. In the
778 * latter case, we query it from KVM and record in env->tsc_khz,
779 * so that vcpu's TSC frequency can be migrated later via this field.
780 */
781 if (!env->tsc_khz) {
782 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
783 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
784 -ENOTSUP;
785 if (r > 0) {
786 env->tsc_khz = r;
787 }
788 }
789
bb0300dc 790 /* Paravirtualization CPUIDs */
234cc647
PB		 791 if (hyperv_enabled(cpu)) {
792 c = &cpuid_data.entries[cpuid_i++];
5e953812 793 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 794 if (!cpu->hyperv_vendor_id) {
795 memcpy(signature, "Microsoft Hv", 12);
796 } else {
797 size_t len = strlen(cpu->hyperv_vendor_id);
798
799 if (len > 12) {
800 error_report("hv-vendor-id truncated to 12 characters");
801 len = 12;
802 }
803 memset(signature, 0, 12);
804 memcpy(signature, cpu->hyperv_vendor_id, len);
805 }
5e953812 806 c->eax = HV_CPUID_MIN;
234cc647
PB		 807 c->ebx = signature[0];
808 c->ecx = signature[1];
809 c->edx = signature[2];
0c31b744 810
234cc647 811 c = &cpuid_data.entries[cpuid_i++];
5e953812 812 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 813 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
814 c->eax = signature[0];
234cc647
PB		 815 c->ebx = 0;
816 c->ecx = 0;
817 c->edx = 0;
eab70139
VR		 818
819 c = &cpuid_data.entries[cpuid_i++];
5e953812 820 c->function = HV_CPUID_VERSION;
eab70139
VR		 821 c->eax = 0x00001bbc;
822 c->ebx = 0x00060001;
823
824 c = &cpuid_data.entries[cpuid_i++];
5e953812 825 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 826 r = hyperv_handle_properties(cs);
827 if (r) {
828 return r;
46eb8f98 829 }
c35bd19a
EY		 830 c->eax = env->features[FEAT_HYPERV_EAX];
831 c->ebx = env->features[FEAT_HYPERV_EBX];
832 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 833
eab70139 834 c = &cpuid_data.entries[cpuid_i++];
5e953812 835 c->function = HV_CPUID_ENLIGHTMENT_INFO;
92067bf4 836 if (cpu->hyperv_relaxed_timing) {
5e953812 837 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
eab70139 838 }
2d5aa872 839 if (cpu->hyperv_vapic) {
5e953812 840 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
eab70139 841 }
92067bf4 842 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 843
844 c = &cpuid_data.entries[cpuid_i++];
5e953812 845 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 846
847 c->eax = cpu->hv_max_vps;
eab70139
VR		 848 c->ebx = 0x40;
849
234cc647 850 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 851 has_msr_hv_hypercall = true;
eab70139
VR		 852 }
853
f522d2ac
AW		 854 if (cpu->expose_kvm) {
855 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
856 c = &cpuid_data.entries[cpuid_i++];
857 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 858 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 859 c->ebx = signature[0];
860 c->ecx = signature[1];
861 c->edx = signature[2];
234cc647 862
f522d2ac
AW		 863 c = &cpuid_data.entries[cpuid_i++];
864 c->function = KVM_CPUID_FEATURES | kvm_base;
865 c->eax = env->features[FEAT_KVM];
be777326 866 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 867 }
917367aa 868
a33609ca 869 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 870
871 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 872 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
873 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
874 abort();
875 }
bb0300dc 876 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 877
878 switch (i) {
a36b1029
AL		 879 case 2: {
880 /* Keep reading function 2 till all the input is received */
881 int times;
882
a36b1029 883 c->function = i;
a33609ca
AL		 884 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
885 KVM_CPUID_FLAG_STATE_READ_NEXT;
886 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
887 times = c->eax & 0xff;
a36b1029
AL		 888
889 for (j = 1; j < times; ++j) {
f8bb0565
IM		 890 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
891 fprintf(stderr, "cpuid_data is full, no space for "
892 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
893 abort();
894 }
a33609ca 895 c = &cpuid_data.entries[cpuid_i++];
a36b1029 896 c->function = i;
a33609ca
AL		 897 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
898 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 899 }
900 break;
901 }
486bd5a2
AL		 902 case 4:
903 case 0xb:
904 case 0xd:
905 for (j = 0; ; j++) {
31e8c696
AP		 906 if (i == 0xd && j == 64) {
907 break;
908 }
486bd5a2
AL		 909 c->function = i;
910 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
911 c->index = j;
a33609ca 912 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 913
b9bec74b 914 if (i == 4 && c->eax == 0) {
486bd5a2 915 break;
b9bec74b
JK		 916 }
917 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 918 break;
b9bec74b
JK		 919 }
920 if (i == 0xd && c->eax == 0) {
31e8c696 921 continue;
b9bec74b 922 }
f8bb0565
IM		 923 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
924 fprintf(stderr, "cpuid_data is full, no space for "
925 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
926 abort();
927 }
a33609ca 928 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 929 }
930 break;
e37a5c7f
CP		 931 case 0x14: {
932 uint32_t times;
933
934 c->function = i;
935 c->index = 0;
936 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
937 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
938 times = c->eax;
939
940 for (j = 1; j <= times; ++j) {
941 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
942 fprintf(stderr, "cpuid_data is full, no space for "
943 "cpuid(eax:0x14,ecx:0x%x)\n", j);
944 abort();
945 }
946 c = &cpuid_data.entries[cpuid_i++];
947 c->function = i;
948 c->index = j;
949 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
950 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
951 }
952 break;
953 }
486bd5a2 954 default:
486bd5a2 955 c->function = i;
a33609ca
AL		 956 c->flags = 0;
957 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 958 break;
959 }
05330448 960 }
0d894367
PB		 961
962 if (limit >= 0x0a) {
0b368a10 963 uint32_t eax, edx;
0d894367 964
0b368a10
JD		 965 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
966
967 has_architectural_pmu_version = eax & 0xff;
968 if (has_architectural_pmu_version > 0) {
969 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 970
971 /* Shouldn't be more than 32, since that's the number of bits
972 * available in EBX to tell us _which_ counters are available.
973 * Play it safe.
974 */
0b368a10
JD		 975 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
976 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
977 }
978
979 if (has_architectural_pmu_version > 1) {
980 num_architectural_pmu_fixed_counters = edx & 0x1f;
981
982 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
983 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
984 }
0d894367
PB		 985 }
986 }
987 }
988
a33609ca 989 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 990
991 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 992 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
993 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
994 abort();
995 }
bb0300dc 996 c = &cpuid_data.entries[cpuid_i++];
05330448 997
8f4202fb
BM		 998 switch (i) {
999 case 0x8000001d:
1000 /* Query for all AMD cache information leaves */
1001 for (j = 0; ; j++) {
1002 c->function = i;
1003 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1004 c->index = j;
1005 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1006
1007 if (c->eax == 0) {
1008 break;
1009 }
1010 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1011 fprintf(stderr, "cpuid_data is full, no space for "
1012 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1013 abort();
1014 }
1015 c = &cpuid_data.entries[cpuid_i++];
1016 }
1017 break;
1018 default:
1019 c->function = i;
1020 c->flags = 0;
1021 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1022 break;
1023 }
05330448
AL		 1024 }
1025
b3baa152
BW		 1026 /* Call Centaur's CPUID instructions they are supported. */
1027 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1028 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1029
1030 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1031 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1032 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1033 abort();
1034 }
b3baa152
BW		 1035 c = &cpuid_data.entries[cpuid_i++];
1036
1037 c->function = i;
1038 c->flags = 0;
1039 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1040 }
1041 }
1042
05330448
AL		 1043 cpuid_data.cpuid.nent = cpuid_i;
1044
e7701825 1045 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1046 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1047 (CPUID_MCE | CPUID_MCA)
a60f24b5 1048 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1049 uint64_t mcg_cap, unsupported_caps;
e7701825 1050 int banks;
32a42024 1051 int ret;
e7701825 1052
a60f24b5 1053 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1054 if (ret < 0) {
1055 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1056 return ret;
e7701825 1057 }
75d49497 1058
2590f15b 1059 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1060 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1061 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1062 return -ENOTSUP;
75d49497 1063 }
49b69cbf 1064
5120901a
EH		 1065 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1066 if (unsupported_caps) {
87f8b626
AR		 1067 if (unsupported_caps & MCG_LMCE_P) {
1068 error_report("kvm: LMCE not supported");
1069 return -ENOTSUP;
1070 }
3dc6f869
AF		 1071 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1072 unsupported_caps);
5120901a
EH		 1073 }
1074
2590f15b
EH		 1075 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1076 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1077 if (ret < 0) {
1078 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1079 return ret;
1080 }
e7701825 1081 }
e7701825 1082
b8cc45d6
GC		 1083 qemu_add_vm_change_state_handler(cpu_update_state, env);
1084
df67696e
LJ		 1085 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1086 if (c) {
1087 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1088 !!(c->ecx & CPUID_EXT_SMX);
1089 }
1090
87f8b626
AR		 1091 if (env->mcg_cap & MCG_LMCE_P) {
1092 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1093 }
1094
d99569d9
EH		 1095 if (!env->user_tsc_khz) {
1096 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1097 invtsc_mig_blocker == NULL) {
1098 /* for migration */
1099 error_setg(&invtsc_mig_blocker,
1100 "State blocked by non-migratable CPU device"
1101 " (invtsc flag)");
fe44dc91
AA		 1102 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1103 if (local_err) {
1104 error_report_err(local_err);
1105 error_free(invtsc_mig_blocker);
1106 goto fail;
1107 }
d99569d9
EH		 1108 /* for savevm */
1109 vmstate_x86_cpu.unmigratable = 1;
1110 }
68bfd0ad
MT		 1111 }
1112
9954a158
PDJ		 1113 if (cpu->vmware_cpuid_freq
1114 /* Guests depend on 0x40000000 to detect this feature, so only expose
1115 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1116 && cpu->expose_kvm
1117 && kvm_base == KVM_CPUID_SIGNATURE
1118 /* TSC clock must be stable and known for this feature. */
4bb95b82 1119 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1120
1121 c = &cpuid_data.entries[cpuid_i++];
1122 c->function = KVM_CPUID_SIGNATURE | 0x10;
1123 c->eax = env->tsc_khz;
1124 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1125 * APIC_BUS_CYCLE_NS */
1126 c->ebx = 1000000;
1127 c->ecx = c->edx = 0;
1128
1129 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1130 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1131 }
1132
1133 cpuid_data.cpuid.nent = cpuid_i;
1134
1135 cpuid_data.cpuid.padding = 0;
1136 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1137 if (r) {
1138 goto fail;
1139 }
1140
28143b40 1141 if (has_xsave) {
fabacc0f
JK		 1142 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1143 }
d71b62a1 1144 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1145
273c515c
PB		 1146 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1147 has_msr_tsc_aux = false;
1148 }
d1ae67f6 1149
e7429073 1150 return 0;
fe44dc91
AA		 1151
1152 fail:
1153 migrate_del_blocker(invtsc_mig_blocker);
1154 return r;
05330448
AL		 1155}
1156
50a2c6e5 1157void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1158{
20d695a9 1159 CPUX86State *env = &cpu->env;
dd673288 1160
1a5e9d2f 1161 env->xcr0 = 1;
ddced198 1162 if (kvm_irqchip_in_kernel()) {
dd673288 1163 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1164 KVM_MP_STATE_UNINITIALIZED;
1165 } else {
1166 env->mp_state = KVM_MP_STATE_RUNNABLE;
1167 }
689141dd
RK		 1168
1169 if (cpu->hyperv_synic) {
1170 int i;
1171 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1172 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1173 }
1174 }
caa5af0f
JK		 1175}
1176
e0723c45
PB		 1177void kvm_arch_do_init_vcpu(X86CPU *cpu)
1178{
1179 CPUX86State *env = &cpu->env;
1180
1181 /* APs get directly into wait-for-SIPI state. */
1182 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1183 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1184 }
1185}
1186
c3a3a7d3 1187static int kvm_get_supported_msrs(KVMState *s)
05330448 1188{
75b10c43 1189 static int kvm_supported_msrs;
c3a3a7d3 1190 int ret = 0;
05330448
AL		 1191
1192 /* first time */
75b10c43 1193 if (kvm_supported_msrs == 0) {
05330448
AL		 1194 struct kvm_msr_list msr_list, *kvm_msr_list;
1195
75b10c43 1196 kvm_supported_msrs = -1;
05330448
AL		 1197
1198 /* Obtain MSR list from KVM. These are the MSRs that we must
1199 * save/restore */
4c9f7372 1200 msr_list.nmsrs = 0;
c3a3a7d3 1201 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1202 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1203 return ret;
6fb6d245 1204 }
d9db889f
JK		 1205 /* Old kernel modules had a bug and could write beyond the provided
1206 memory. Allocate at least a safe amount of 1K. */
7267c094 1207 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1208 msr_list.nmsrs *
1209 sizeof(msr_list.indices[0])));
05330448 1210
55308450 1211 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1212 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1213 if (ret >= 0) {
1214 int i;
1215
1216 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1217 switch (kvm_msr_list->indices[i]) {
1218 case MSR_STAR:
c3a3a7d3 1219 has_msr_star = true;
1d268dec
LP		 1220 break;
1221 case MSR_VM_HSAVE_PA:
c3a3a7d3 1222 has_msr_hsave_pa = true;
1d268dec
LP		 1223 break;
1224 case MSR_TSC_AUX:
c9b8f6b6 1225 has_msr_tsc_aux = true;
1d268dec
LP		 1226 break;
1227 case MSR_TSC_ADJUST:
f28558d3 1228 has_msr_tsc_adjust = true;
1d268dec
LP		 1229 break;
1230 case MSR_IA32_TSCDEADLINE:
aa82ba54 1231 has_msr_tsc_deadline = true;
1d268dec
LP		 1232 break;
1233 case MSR_IA32_SMBASE:
fc12d72e 1234 has_msr_smbase = true;
1d268dec 1235 break;
e13713db
LA		 1236 case MSR_SMI_COUNT:
1237 has_msr_smi_count = true;
1238 break;
1d268dec 1239 case MSR_IA32_MISC_ENABLE:
21e87c46 1240 has_msr_misc_enable = true;
1d268dec
LP		 1241 break;
1242 case MSR_IA32_BNDCFGS:
79e9ebeb 1243 has_msr_bndcfgs = true;
1d268dec
LP		 1244 break;
1245 case MSR_IA32_XSS:
18cd2c17 1246 has_msr_xss = true;
3c254ab8 1247 break;
1d268dec 1248 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1249 has_msr_hv_crash = true;
1d268dec
LP		 1250 break;
1251 case HV_X64_MSR_RESET:
744b8a94 1252 has_msr_hv_reset = true;
1d268dec
LP		 1253 break;
1254 case HV_X64_MSR_VP_INDEX:
8c145d7c 1255 has_msr_hv_vpindex = true;
1d268dec
LP		 1256 break;
1257 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1258 has_msr_hv_runtime = true;
1d268dec
LP		 1259 break;
1260 case HV_X64_MSR_SCONTROL:
866eea9a 1261 has_msr_hv_synic = true;
1d268dec
LP		 1262 break;
1263 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1264 has_msr_hv_stimer = true;
1d268dec 1265 break;
d72bc7f6
LP		 1266 case HV_X64_MSR_TSC_FREQUENCY:
1267 has_msr_hv_frequencies = true;
1268 break;
ba6a4fd9
VK		 1269 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1270 has_msr_hv_reenlightenment = true;
1271 break;
a33a2cfe
PB		 1272 case MSR_IA32_SPEC_CTRL:
1273 has_msr_spec_ctrl = true;
1274 break;
cfeea0c0
KRW		 1275 case MSR_VIRT_SSBD:
1276 has_msr_virt_ssbd = true;
1277 break;
ff99aa64 1278 }
05330448
AL		 1279 }
1280 }
1281
7267c094 1282 g_free(kvm_msr_list);
05330448
AL		 1283 }
1284
c3a3a7d3 1285 return ret;
05330448
AL		 1286}
1287
6410848b
PB		 1288static Notifier smram_machine_done;
1289static KVMMemoryListener smram_listener;
1290static AddressSpace smram_address_space;
1291static MemoryRegion smram_as_root;
1292static MemoryRegion smram_as_mem;
1293
1294static void register_smram_listener(Notifier *n, void *unused)
1295{
1296 MemoryRegion *smram =
1297 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1298
1299 /* Outer container... */
1300 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1301 memory_region_set_enabled(&smram_as_root, true);
1302
1303 /* ... with two regions inside: normal system memory with low
1304 * priority, and...
1305 */
1306 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1307 get_system_memory(), 0, ~0ull);
1308 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1309 memory_region_set_enabled(&smram_as_mem, true);
1310
1311 if (smram) {
1312 /* ... SMRAM with higher priority */
1313 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1314 memory_region_set_enabled(smram, true);
1315 }
1316
1317 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1318 kvm_memory_listener_register(kvm_state, &smram_listener,
1319 &smram_address_space, 1);
1320}
1321
b16565b3 1322int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1323{
11076198 1324 uint64_t identity_base = 0xfffbc000;
39d6960a 1325 uint64_t shadow_mem;
20420430 1326 int ret;
25d2e361 1327 struct utsname utsname;
20420430 1328
28143b40
TH		 1329#ifdef KVM_CAP_XSAVE
1330 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1331#endif
1332
1333#ifdef KVM_CAP_XCRS
1334 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1335#endif
1336
1337#ifdef KVM_CAP_PIT_STATE2
1338 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1339#endif
1340
c3a3a7d3 1341 ret = kvm_get_supported_msrs(s);
20420430 1342 if (ret < 0) {
20420430
SY		 1343 return ret;
1344 }
25d2e361
MT		 1345
1346 uname(&utsname);
1347 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1348
4c5b10b7 1349 /*
11076198
JK		 1350 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1351 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1352 * Since these must be part of guest physical memory, we need to allocate
1353 * them, both by setting their start addresses in the kernel and by
1354 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1355 *
1356 * Older KVM versions may not support setting the identity map base. In
1357 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1358 * size.
4c5b10b7 1359 */
11076198
JK		 1360 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1361 /* Allows up to 16M BIOSes. */
1362 identity_base = 0xfeffc000;
1363
1364 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1365 if (ret < 0) {
1366 return ret;
1367 }
4c5b10b7 1368 }
e56ff191 1369
11076198
JK		 1370 /* Set TSS base one page after EPT identity map. */
1371 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1372 if (ret < 0) {
1373 return ret;
1374 }
1375
11076198
JK		 1376 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1377 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1378 if (ret < 0) {
11076198 1379 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1380 return ret;
1381 }
3c85e74f 1382 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1383
4689b77b 1384 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1385 if (shadow_mem != -1) {
1386 shadow_mem /= 4096;
1387 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1388 if (ret < 0) {
1389 return ret;
39d6960a
JK		 1390 }
1391 }
6410848b 1392
d870cfde
GA		 1393 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1394 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1395 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1396 smram_machine_done.notify = register_smram_listener;
1397 qemu_add_machine_init_done_notifier(&smram_machine_done);
1398 }
6f131f13
MT		 1399
1400 if (enable_cpu_pm) {
1401 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1402 int ret;
1403
1404/* Work around for kernel header with a typo. TODO: fix header and drop. */
1405#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1406#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1407#endif
1408 if (disable_exits) {
1409 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1410 KVM_X86_DISABLE_EXITS_HLT |
1411 KVM_X86_DISABLE_EXITS_PAUSE);
1412 }
1413
1414 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1415 disable_exits);
1416 if (ret < 0) {
1417 error_report("kvm: guest stopping CPU not supported: %s",
1418 strerror(-ret));
1419 }
1420 }
1421
11076198 1422 return 0;
05330448 1423}
b9bec74b 1424
05330448
AL		 1425static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1426{
1427 lhs->selector = rhs->selector;
1428 lhs->base = rhs->base;
1429 lhs->limit = rhs->limit;
1430 lhs->type = 3;
1431 lhs->present = 1;
1432 lhs->dpl = 3;
1433 lhs->db = 0;
1434 lhs->s = 1;
1435 lhs->l = 0;
1436 lhs->g = 0;
1437 lhs->avl = 0;
1438 lhs->unusable = 0;
1439}
1440
1441static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1442{
1443 unsigned flags = rhs->flags;
1444 lhs->selector = rhs->selector;
1445 lhs->base = rhs->base;
1446 lhs->limit = rhs->limit;
1447 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1448 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1449 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1450 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1451 lhs->s = (flags & DESC_S_MASK) != 0;
1452 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1453 lhs->g = (flags & DESC_G_MASK) != 0;
1454 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1455 lhs->unusable = !lhs->present;
7e680753 1456 lhs->padding = 0;
05330448
AL		 1457}
1458
1459static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1460{
1461 lhs->selector = rhs->selector;
1462 lhs->base = rhs->base;
1463 lhs->limit = rhs->limit;
d45fc087
RP		 1464 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1465 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1466 (rhs->dpl << DESC_DPL_SHIFT) |
1467 (rhs->db << DESC_B_SHIFT) |
1468 (rhs->s * DESC_S_MASK) |
1469 (rhs->l << DESC_L_SHIFT) |
1470 (rhs->g * DESC_G_MASK) |
1471 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1472}
1473
1474static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1475{
b9bec74b 1476 if (set) {
05330448 1477 *kvm_reg = *qemu_reg;
b9bec74b 1478 } else {
05330448 1479 *qemu_reg = *kvm_reg;
b9bec74b 1480 }
05330448
AL		 1481}
1482
1bc22652 1483static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1484{
1bc22652 1485 CPUX86State *env = &cpu->env;
05330448
AL		 1486 struct kvm_regs regs;
1487 int ret = 0;
1488
1489 if (!set) {
1bc22652 1490 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1491 if (ret < 0) {
05330448 1492 return ret;
b9bec74b 1493 }
05330448
AL		 1494 }
1495
1496 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1497 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1498 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1499 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1500 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1501 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1502 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1503 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1504#ifdef TARGET_X86_64
1505 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1506 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1507 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1508 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1509 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1510 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1511 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1512 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1513#endif
1514
1515 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1516 kvm_getput_reg(&regs.rip, &env->eip, set);
1517
b9bec74b 1518 if (set) {
1bc22652 1519 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1520 }
05330448
AL		 1521
1522 return ret;
1523}
1524
1bc22652 1525static int kvm_put_fpu(X86CPU *cpu)
05330448 1526{
1bc22652 1527 CPUX86State *env = &cpu->env;
05330448
AL		 1528 struct kvm_fpu fpu;
1529 int i;
1530
1531 memset(&fpu, 0, sizeof fpu);
1532 fpu.fsw = env->fpus & ~(7 << 11);
1533 fpu.fsw |= (env->fpstt & 7) << 11;
1534 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1535 fpu.last_opcode = env->fpop;
1536 fpu.last_ip = env->fpip;
1537 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1538 for (i = 0; i < 8; ++i) {
1539 fpu.ftwx |= (!env->fptags[i]) << i;
1540 }
05330448 1541 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1542 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1543 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1544 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1545 }
05330448
AL		 1546 fpu.mxcsr = env->mxcsr;
1547
1bc22652 1548 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1549}
1550
6b42494b
JK		 1551#define XSAVE_FCW_FSW 0
1552#define XSAVE_FTW_FOP 1
f1665b21
SY		 1553#define XSAVE_CWD_RIP 2
1554#define XSAVE_CWD_RDP 4
1555#define XSAVE_MXCSR 6
1556#define XSAVE_ST_SPACE 8
1557#define XSAVE_XMM_SPACE 40
1558#define XSAVE_XSTATE_BV 128
1559#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1560#define XSAVE_BNDREGS 240
1561#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1562#define XSAVE_OPMASK 272
1563#define XSAVE_ZMM_Hi256 288
1564#define XSAVE_Hi16_ZMM 416
f74eefe0 1565#define XSAVE_PKRU 672
f1665b21 1566
b503717d
EH		 1567#define XSAVE_BYTE_OFFSET(word_offset) \
1568 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1569
1570#define ASSERT_OFFSET(word_offset, field) \
1571 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1572 offsetof(X86XSaveArea, field))
1573
1574ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1575ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1576ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1577ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1578ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1579ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1580ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1581ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1582ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1583ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1584ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1585ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1586ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1587ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1588ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1589
1bc22652 1590static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1591{
1bc22652 1592 CPUX86State *env = &cpu->env;
86cd2ea0 1593 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1594
28143b40 1595 if (!has_xsave) {
1bc22652 1596 return kvm_put_fpu(cpu);
b9bec74b 1597 }
86a57621 1598 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1599
9be38598 1600 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1601}
1602
1bc22652 1603static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1604{
1bc22652 1605 CPUX86State *env = &cpu->env;
bdfc8480 1606 struct kvm_xcrs xcrs = {};
f1665b21 1607
28143b40 1608 if (!has_xcrs) {
f1665b21 1609 return 0;
b9bec74b 1610 }
f1665b21
SY		 1611
1612 xcrs.nr_xcrs = 1;
1613 xcrs.flags = 0;
1614 xcrs.xcrs[0].xcr = 0;
1615 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1616 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1617}
1618
1bc22652 1619static int kvm_put_sregs(X86CPU *cpu)
05330448 1620{
1bc22652 1621 CPUX86State *env = &cpu->env;
05330448
AL		 1622 struct kvm_sregs sregs;
1623
0e607a80
JK		 1624 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1625 if (env->interrupt_injected >= 0) {
1626 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1627 (uint64_t)1 << (env->interrupt_injected % 64);
1628 }
05330448
AL		 1629
1630 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1631 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1632 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1633 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1634 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1635 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1636 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1637 } else {
b9bec74b
JK		 1638 set_seg(&sregs.cs, &env->segs[R_CS]);
1639 set_seg(&sregs.ds, &env->segs[R_DS]);
1640 set_seg(&sregs.es, &env->segs[R_ES]);
1641 set_seg(&sregs.fs, &env->segs[R_FS]);
1642 set_seg(&sregs.gs, &env->segs[R_GS]);
1643 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1644 }
1645
1646 set_seg(&sregs.tr, &env->tr);
1647 set_seg(&sregs.ldt, &env->ldt);
1648
1649 sregs.idt.limit = env->idt.limit;
1650 sregs.idt.base = env->idt.base;
7e680753 1651 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1652 sregs.gdt.limit = env->gdt.limit;
1653 sregs.gdt.base = env->gdt.base;
7e680753 1654 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1655
1656 sregs.cr0 = env->cr[0];
1657 sregs.cr2 = env->cr[2];
1658 sregs.cr3 = env->cr[3];
1659 sregs.cr4 = env->cr[4];
1660
02e51483
CF		 1661 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1662 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1663
1664 sregs.efer = env->efer;
1665
1bc22652 1666 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1667}
1668
d71b62a1
EH		 1669static void kvm_msr_buf_reset(X86CPU *cpu)
1670{
1671 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1672}
1673
9c600a84
EH		 1674static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1675{
1676 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1677 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1678 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1679
1680 assert((void *)(entry + 1) <= limit);
1681
1abc2cae
EH		 1682 entry->index = index;
1683 entry->reserved = 0;
1684 entry->data = value;
9c600a84
EH		 1685 msrs->nmsrs++;
1686}
1687
73e1b8f2
PB		 1688static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1689{
1690 kvm_msr_buf_reset(cpu);
1691 kvm_msr_entry_add(cpu, index, value);
1692
1693 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1694}
1695
f8d9ccf8
DDAG		 1696void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1697{
1698 int ret;
1699
1700 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1701 assert(ret == 1);
1702}
1703
7477cd38
MT		 1704static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1705{
1706 CPUX86State *env = &cpu->env;
48e1a45c 1707 int ret;
7477cd38
MT		 1708
1709 if (!has_msr_tsc_deadline) {
1710 return 0;
1711 }
1712
73e1b8f2 1713 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1714 if (ret < 0) {
1715 return ret;
1716 }
1717
1718 assert(ret == 1);
1719 return 0;
7477cd38
MT		 1720}
1721
6bdf863d
JK		 1722/*
1723 * Provide a separate write service for the feature control MSR in order to
1724 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1725 * before writing any other state because forcibly leaving nested mode
1726 * invalidates the VCPU state.
1727 */
1728static int kvm_put_msr_feature_control(X86CPU *cpu)
1729{
48e1a45c
PB		 1730 int ret;
1731
1732 if (!has_msr_feature_control) {
1733 return 0;
1734 }
6bdf863d 1735
73e1b8f2
PB		 1736 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1737 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1738 if (ret < 0) {
1739 return ret;
1740 }
1741
1742 assert(ret == 1);
1743 return 0;
6bdf863d
JK		 1744}
1745
1bc22652 1746static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1747{
1bc22652 1748 CPUX86State *env = &cpu->env;
9c600a84 1749 int i;
48e1a45c 1750 int ret;
05330448 1751
d71b62a1
EH		 1752 kvm_msr_buf_reset(cpu);
1753
9c600a84
EH		 1754 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1755 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1756 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1757 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1758 if (has_msr_star) {
9c600a84 1759 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1760 }
c3a3a7d3 1761 if (has_msr_hsave_pa) {
9c600a84 1762 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1763 }
c9b8f6b6 1764 if (has_msr_tsc_aux) {
9c600a84 1765 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1766 }
f28558d3 1767 if (has_msr_tsc_adjust) {
9c600a84 1768 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1769 }
21e87c46 1770 if (has_msr_misc_enable) {
9c600a84 1771 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1772 env->msr_ia32_misc_enable);
1773 }
fc12d72e 1774 if (has_msr_smbase) {
9c600a84 1775 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1776 }
e13713db
LA		 1777 if (has_msr_smi_count) {
1778 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1779 }
439d19f2 1780 if (has_msr_bndcfgs) {
9c600a84 1781 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1782 }
18cd2c17 1783 if (has_msr_xss) {
9c600a84 1784 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1785 }
a33a2cfe
PB		 1786 if (has_msr_spec_ctrl) {
1787 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1788 }
cfeea0c0
KRW		 1789 if (has_msr_virt_ssbd) {
1790 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1791 }
1792
05330448 1793#ifdef TARGET_X86_64
25d2e361 1794 if (lm_capable_kernel) {
9c600a84
EH		 1795 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1796 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1797 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1798 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1799 }
05330448 1800#endif
a33a2cfe 1801
ff5c186b 1802 /*
0d894367
PB		 1803 * The following MSRs have side effects on the guest or are too heavy
1804 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1805 */
1806 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1807 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1808 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1809 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1810 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1811 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1812 }
55c911a5 1813 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1814 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1815 }
55c911a5 1816 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1817 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1818 }
0b368a10
JD		 1819 if (has_architectural_pmu_version > 0) {
1820 if (has_architectural_pmu_version > 1) {
1821 /* Stop the counter. */
1822 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1823 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1824 }
0d894367
PB		 1825
1826 /* Set the counter values. */
0b368a10 1827 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 1828 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1829 env->msr_fixed_counters[i]);
1830 }
0b368a10 1831 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 1832 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1833 env->msr_gp_counters[i]);
9c600a84 1834 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1835 env->msr_gp_evtsel[i]);
1836 }
0b368a10
JD		 1837 if (has_architectural_pmu_version > 1) {
1838 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1839 env->msr_global_status);
1840 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1841 env->msr_global_ovf_ctrl);
1842
1843 /* Now start the PMU. */
1844 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1845 env->msr_fixed_ctr_ctrl);
1846 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1847 env->msr_global_ctrl);
1848 }
0d894367 1849 }
da1cc323
EY		 1850 /*
1851 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1852 * only sync them to KVM on the first cpu
1853 */
1854 if (current_cpu == first_cpu) {
1855 if (has_msr_hv_hypercall) {
1856 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1857 env->msr_hv_guest_os_id);
1858 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1859 env->msr_hv_hypercall);
1860 }
1861 if (cpu->hyperv_time) {
1862 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1863 env->msr_hv_tsc);
1864 }
ba6a4fd9
VK		 1865 if (cpu->hyperv_reenlightenment) {
1866 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
1867 env->msr_hv_reenlightenment_control);
1868 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
1869 env->msr_hv_tsc_emulation_control);
1870 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
1871 env->msr_hv_tsc_emulation_status);
1872 }
eab70139 1873 }
2d5aa872 1874 if (cpu->hyperv_vapic) {
9c600a84 1875 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1876 env->msr_hv_vapic);
eab70139 1877 }
f2a53c9e
AS		 1878 if (has_msr_hv_crash) {
1879 int j;
1880
5e953812 1881 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 1882 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1883 env->msr_hv_crash_params[j]);
1884
5e953812 1885 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 1886 }
46eb8f98 1887 if (has_msr_hv_runtime) {
9c600a84 1888 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1889 }
866eea9a
AS		 1890 if (cpu->hyperv_synic) {
1891 int j;
1892
09df29b6
RK		 1893 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1894
9c600a84 1895 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1896 env->msr_hv_synic_control);
9c600a84 1897 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1898 env->msr_hv_synic_evt_page);
9c600a84 1899 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1900 env->msr_hv_synic_msg_page);
1901
1902 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1903 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1904 env->msr_hv_synic_sint[j]);
1905 }
1906 }
ff99aa64
AS		 1907 if (has_msr_hv_stimer) {
1908 int j;
1909
1910 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1911 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1912 env->msr_hv_stimer_config[j]);
1913 }
1914
1915 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1916 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1917 env->msr_hv_stimer_count[j]);
1918 }
1919 }
1eabfce6 1920 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1921 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1922
9c600a84
EH		 1923 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1924 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1925 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1926 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1927 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1928 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1929 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1930 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1931 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1932 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1933 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1934 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1935 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1936 /* The CPU GPs if we write to a bit above the physical limit of
1937 * the host CPU (and KVM emulates that)
1938 */
1939 uint64_t mask = env->mtrr_var[i].mask;
1940 mask &= phys_mask;
1941
9c600a84
EH		 1942 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1943 env->mtrr_var[i].base);
112dad69 1944 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1945 }
1946 }
b77146e9
CP		 1947 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
1948 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
1949 0x14, 1, R_EAX) & 0x7;
1950
1951 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
1952 env->msr_rtit_ctrl);
1953 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
1954 env->msr_rtit_status);
1955 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
1956 env->msr_rtit_output_base);
1957 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
1958 env->msr_rtit_output_mask);
1959 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
1960 env->msr_rtit_cr3_match);
1961 for (i = 0; i < addr_num; i++) {
1962 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
1963 env->msr_rtit_addrs[i]);
1964 }
1965 }
6bdf863d
JK		 1966
1967 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1968 * kvm_put_msr_feature_control. */
ea643051 1969 }
57780495 1970 if (env->mcg_cap) {
d8da8574 1971 int i;
b9bec74b 1972
9c600a84
EH		 1973 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1974 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1975 if (has_msr_mcg_ext_ctl) {
1976 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1977 }
c34d440a 1978 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1979 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1980 }
1981 }
1a03675d 1982
d71b62a1 1983 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1984 if (ret < 0) {
1985 return ret;
1986 }
05330448 1987
c70b11d1
EH		 1988 if (ret < cpu->kvm_msr_buf->nmsrs) {
1989 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1990 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1991 (uint32_t)e->index, (uint64_t)e->data);
1992 }
1993
9c600a84 1994 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1995 return 0;
05330448
AL		 1996}
1997
1998
1bc22652 1999static int kvm_get_fpu(X86CPU *cpu)
05330448 2000{
1bc22652 2001 CPUX86State *env = &cpu->env;
05330448
AL		 2002 struct kvm_fpu fpu;
2003 int i, ret;
2004
1bc22652 2005 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2006 if (ret < 0) {
05330448 2007 return ret;
b9bec74b 2008 }
05330448
AL		 2009
2010 env->fpstt = (fpu.fsw >> 11) & 7;
2011 env->fpus = fpu.fsw;
2012 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2013 env->fpop = fpu.last_opcode;
2014 env->fpip = fpu.last_ip;
2015 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2016 for (i = 0; i < 8; ++i) {
2017 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2018 }
05330448 2019 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2020 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2021 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2022 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2023 }
05330448
AL		 2024 env->mxcsr = fpu.mxcsr;
2025
2026 return 0;
2027}
2028
1bc22652 2029static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2030{
1bc22652 2031 CPUX86State *env = &cpu->env;
86cd2ea0 2032 X86XSaveArea *xsave = env->kvm_xsave_buf;
86a57621 2033 int ret;
f1665b21 2034
28143b40 2035 if (!has_xsave) {
1bc22652 2036 return kvm_get_fpu(cpu);
b9bec74b 2037 }
f1665b21 2038
1bc22652 2039 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2040 if (ret < 0) {
f1665b21 2041 return ret;
0f53994f 2042 }
86a57621 2043 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2044
f1665b21 2045 return 0;
f1665b21
SY		 2046}
2047
1bc22652 2048static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2049{
1bc22652 2050 CPUX86State *env = &cpu->env;
f1665b21
SY		 2051 int i, ret;
2052 struct kvm_xcrs xcrs;
2053
28143b40 2054 if (!has_xcrs) {
f1665b21 2055 return 0;
b9bec74b 2056 }
f1665b21 2057
1bc22652 2058 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2059 if (ret < 0) {
f1665b21 2060 return ret;
b9bec74b 2061 }
f1665b21 2062
b9bec74b 2063 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2064 /* Only support xcr0 now */
0fd53fec
PB		 2065 if (xcrs.xcrs[i].xcr == 0) {
2066 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2067 break;
2068 }
b9bec74b 2069 }
f1665b21 2070 return 0;
f1665b21
SY		 2071}
2072
1bc22652 2073static int kvm_get_sregs(X86CPU *cpu)
05330448 2074{
1bc22652 2075 CPUX86State *env = &cpu->env;
05330448 2076 struct kvm_sregs sregs;
0e607a80 2077 int bit, i, ret;
05330448 2078
1bc22652 2079 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2080 if (ret < 0) {
05330448 2081 return ret;
b9bec74b 2082 }
05330448 2083
0e607a80
JK		 2084 /* There can only be one pending IRQ set in the bitmap at a time, so try
2085 to find it and save its number instead (-1 for none). */
2086 env->interrupt_injected = -1;
2087 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2088 if (sregs.interrupt_bitmap[i]) {
2089 bit = ctz64(sregs.interrupt_bitmap[i]);
2090 env->interrupt_injected = i * 64 + bit;
2091 break;
2092 }
2093 }
05330448
AL		 2094
2095 get_seg(&env->segs[R_CS], &sregs.cs);
2096 get_seg(&env->segs[R_DS], &sregs.ds);
2097 get_seg(&env->segs[R_ES], &sregs.es);
2098 get_seg(&env->segs[R_FS], &sregs.fs);
2099 get_seg(&env->segs[R_GS], &sregs.gs);
2100 get_seg(&env->segs[R_SS], &sregs.ss);
2101
2102 get_seg(&env->tr, &sregs.tr);
2103 get_seg(&env->ldt, &sregs.ldt);
2104
2105 env->idt.limit = sregs.idt.limit;
2106 env->idt.base = sregs.idt.base;
2107 env->gdt.limit = sregs.gdt.limit;
2108 env->gdt.base = sregs.gdt.base;
2109
2110 env->cr[0] = sregs.cr0;
2111 env->cr[2] = sregs.cr2;
2112 env->cr[3] = sregs.cr3;
2113 env->cr[4] = sregs.cr4;
2114
05330448 2115 env->efer = sregs.efer;
cce47516
JK		 2116
2117 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2118 x86_update_hflags(env);
05330448
AL		 2119
2120 return 0;
2121}
2122
1bc22652 2123static int kvm_get_msrs(X86CPU *cpu)
05330448 2124{
1bc22652 2125 CPUX86State *env = &cpu->env;
d71b62a1 2126 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2127 int ret, i;
fcc35e7c 2128 uint64_t mtrr_top_bits;
05330448 2129
d71b62a1
EH		 2130 kvm_msr_buf_reset(cpu);
2131
9c600a84
EH		 2132 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2133 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2134 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2135 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2136 if (has_msr_star) {
9c600a84 2137 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2138 }
c3a3a7d3 2139 if (has_msr_hsave_pa) {
9c600a84 2140 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2141 }
c9b8f6b6 2142 if (has_msr_tsc_aux) {
9c600a84 2143 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2144 }
f28558d3 2145 if (has_msr_tsc_adjust) {
9c600a84 2146 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2147 }
aa82ba54 2148 if (has_msr_tsc_deadline) {
9c600a84 2149 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2150 }
21e87c46 2151 if (has_msr_misc_enable) {
9c600a84 2152 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2153 }
fc12d72e 2154 if (has_msr_smbase) {
9c600a84 2155 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2156 }
e13713db
LA		 2157 if (has_msr_smi_count) {
2158 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2159 }
df67696e 2160 if (has_msr_feature_control) {
9c600a84 2161 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2162 }
79e9ebeb 2163 if (has_msr_bndcfgs) {
9c600a84 2164 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2165 }
18cd2c17 2166 if (has_msr_xss) {
9c600a84 2167 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2168 }
a33a2cfe
PB		 2169 if (has_msr_spec_ctrl) {
2170 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2171 }
cfeea0c0
KRW		 2172 if (has_msr_virt_ssbd) {
2173 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2174 }
b8cc45d6 2175 if (!env->tsc_valid) {
9c600a84 2176 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2177 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2178 }
2179
05330448 2180#ifdef TARGET_X86_64
25d2e361 2181 if (lm_capable_kernel) {
9c600a84
EH		 2182 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2183 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2184 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2185 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2186 }
05330448 2187#endif
9c600a84
EH		 2188 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2189 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2190 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2191 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2192 }
55c911a5 2193 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2194 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2195 }
55c911a5 2196 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2197 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2198 }
0b368a10
JD		 2199 if (has_architectural_pmu_version > 0) {
2200 if (has_architectural_pmu_version > 1) {
2201 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2202 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2203 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2204 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2205 }
2206 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2207 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2208 }
0b368a10 2209 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2210 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2211 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2212 }
2213 }
1a03675d 2214
57780495 2215 if (env->mcg_cap) {
9c600a84
EH		 2216 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2217 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2218 if (has_msr_mcg_ext_ctl) {
2219 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2220 }
b9bec74b 2221 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2222 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2223 }
57780495 2224 }
57780495 2225
1c90ef26 2226 if (has_msr_hv_hypercall) {
9c600a84
EH		 2227 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2228 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2229 }
2d5aa872 2230 if (cpu->hyperv_vapic) {
9c600a84 2231 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2232 }
3ddcd2ed 2233 if (cpu->hyperv_time) {
9c600a84 2234 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2235 }
ba6a4fd9
VK		 2236 if (cpu->hyperv_reenlightenment) {
2237 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2238 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2239 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2240 }
f2a53c9e
AS		 2241 if (has_msr_hv_crash) {
2242 int j;
2243
5e953812 2244 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2245 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2246 }
2247 }
46eb8f98 2248 if (has_msr_hv_runtime) {
9c600a84 2249 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2250 }
866eea9a
AS		 2251 if (cpu->hyperv_synic) {
2252 uint32_t msr;
2253
9c600a84 2254 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2255 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2256 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2257 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2258 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2259 }
2260 }
ff99aa64
AS		 2261 if (has_msr_hv_stimer) {
2262 uint32_t msr;
2263
2264 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2265 msr++) {
9c600a84 2266 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2267 }
2268 }
1eabfce6 2269 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2270 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2271 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2272 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2273 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2274 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2275 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2276 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2277 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2278 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2279 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2280 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2281 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2282 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2283 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2284 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2285 }
2286 }
5ef68987 2287
b77146e9
CP		 2288 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2289 int addr_num =
2290 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2291
2292 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2293 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2294 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2295 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2296 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2297 for (i = 0; i < addr_num; i++) {
2298 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2299 }
2300 }
2301
d71b62a1 2302 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2303 if (ret < 0) {
05330448 2304 return ret;
b9bec74b 2305 }
05330448 2306
c70b11d1
EH		 2307 if (ret < cpu->kvm_msr_buf->nmsrs) {
2308 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2309 error_report("error: failed to get MSR 0x%" PRIx32,
2310 (uint32_t)e->index);
2311 }
2312
9c600a84 2313 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2314 /*
2315 * MTRR masks: Each mask consists of 5 parts
2316 * a 10..0: must be zero
2317 * b 11 : valid bit
2318 * c n-1.12: actual mask bits
2319 * d 51..n: reserved must be zero
2320 * e 63.52: reserved must be zero
2321 *
2322 * 'n' is the number of physical bits supported by the CPU and is
2323 * apparently always <= 52. We know our 'n' but don't know what
2324 * the destinations 'n' is; it might be smaller, in which case
2325 * it masks (c) on loading. It might be larger, in which case
2326 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2327 * we're migrating to.
2328 */
2329
2330 if (cpu->fill_mtrr_mask) {
2331 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2332 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2333 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2334 } else {
2335 mtrr_top_bits = 0;
2336 }
2337
05330448 2338 for (i = 0; i < ret; i++) {
0d894367
PB		 2339 uint32_t index = msrs[i].index;
2340 switch (index) {
05330448
AL		 2341 case MSR_IA32_SYSENTER_CS:
2342 env->sysenter_cs = msrs[i].data;
2343 break;
2344 case MSR_IA32_SYSENTER_ESP:
2345 env->sysenter_esp = msrs[i].data;
2346 break;
2347 case MSR_IA32_SYSENTER_EIP:
2348 env->sysenter_eip = msrs[i].data;
2349 break;
0c03266a
JK		 2350 case MSR_PAT:
2351 env->pat = msrs[i].data;
2352 break;
05330448
AL		 2353 case MSR_STAR:
2354 env->star = msrs[i].data;
2355 break;
2356#ifdef TARGET_X86_64
2357 case MSR_CSTAR:
2358 env->cstar = msrs[i].data;
2359 break;
2360 case MSR_KERNELGSBASE:
2361 env->kernelgsbase = msrs[i].data;
2362 break;
2363 case MSR_FMASK:
2364 env->fmask = msrs[i].data;
2365 break;
2366 case MSR_LSTAR:
2367 env->lstar = msrs[i].data;
2368 break;
2369#endif
2370 case MSR_IA32_TSC:
2371 env->tsc = msrs[i].data;
2372 break;
c9b8f6b6
AS		 2373 case MSR_TSC_AUX:
2374 env->tsc_aux = msrs[i].data;
2375 break;
f28558d3
WA		 2376 case MSR_TSC_ADJUST:
2377 env->tsc_adjust = msrs[i].data;
2378 break;
aa82ba54
LJ		 2379 case MSR_IA32_TSCDEADLINE:
2380 env->tsc_deadline = msrs[i].data;
2381 break;
aa851e36
MT		 2382 case MSR_VM_HSAVE_PA:
2383 env->vm_hsave = msrs[i].data;
2384 break;
1a03675d
GC		 2385 case MSR_KVM_SYSTEM_TIME:
2386 env->system_time_msr = msrs[i].data;
2387 break;
2388 case MSR_KVM_WALL_CLOCK:
2389 env->wall_clock_msr = msrs[i].data;
2390 break;
57780495
MT		 2391 case MSR_MCG_STATUS:
2392 env->mcg_status = msrs[i].data;
2393 break;
2394 case MSR_MCG_CTL:
2395 env->mcg_ctl = msrs[i].data;
2396 break;
87f8b626
AR		 2397 case MSR_MCG_EXT_CTL:
2398 env->mcg_ext_ctl = msrs[i].data;
2399 break;
21e87c46
AK		 2400 case MSR_IA32_MISC_ENABLE:
2401 env->msr_ia32_misc_enable = msrs[i].data;
2402 break;
fc12d72e
PB		 2403 case MSR_IA32_SMBASE:
2404 env->smbase = msrs[i].data;
2405 break;
e13713db
LA		 2406 case MSR_SMI_COUNT:
2407 env->msr_smi_count = msrs[i].data;
2408 break;
0779caeb
ACL		 2409 case MSR_IA32_FEATURE_CONTROL:
2410 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2411 break;
79e9ebeb
LJ		 2412 case MSR_IA32_BNDCFGS:
2413 env->msr_bndcfgs = msrs[i].data;
2414 break;
18cd2c17
WL		 2415 case MSR_IA32_XSS:
2416 env->xss = msrs[i].data;
2417 break;
57780495 2418 default:
57780495
MT		 2419 if (msrs[i].index >= MSR_MC0_CTL &&
2420 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2421 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2422 }
d8da8574 2423 break;
f6584ee2
GN		 2424 case MSR_KVM_ASYNC_PF_EN:
2425 env->async_pf_en_msr = msrs[i].data;
2426 break;
bc9a839d
MT		 2427 case MSR_KVM_PV_EOI_EN:
2428 env->pv_eoi_en_msr = msrs[i].data;
2429 break;
917367aa
MT		 2430 case MSR_KVM_STEAL_TIME:
2431 env->steal_time_msr = msrs[i].data;
2432 break;
0d894367
PB		 2433 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2434 env->msr_fixed_ctr_ctrl = msrs[i].data;
2435 break;
2436 case MSR_CORE_PERF_GLOBAL_CTRL:
2437 env->msr_global_ctrl = msrs[i].data;
2438 break;
2439 case MSR_CORE_PERF_GLOBAL_STATUS:
2440 env->msr_global_status = msrs[i].data;
2441 break;
2442 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2443 env->msr_global_ovf_ctrl = msrs[i].data;
2444 break;
2445 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2446 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2447 break;
2448 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2449 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2450 break;
2451 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2452 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2453 break;
1c90ef26
VR		 2454 case HV_X64_MSR_HYPERCALL:
2455 env->msr_hv_hypercall = msrs[i].data;
2456 break;
2457 case HV_X64_MSR_GUEST_OS_ID:
2458 env->msr_hv_guest_os_id = msrs[i].data;
2459 break;
5ef68987
VR		 2460 case HV_X64_MSR_APIC_ASSIST_PAGE:
2461 env->msr_hv_vapic = msrs[i].data;
2462 break;
48a5f3bc
VR		 2463 case HV_X64_MSR_REFERENCE_TSC:
2464 env->msr_hv_tsc = msrs[i].data;
2465 break;
f2a53c9e
AS		 2466 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2467 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2468 break;
46eb8f98
AS		 2469 case HV_X64_MSR_VP_RUNTIME:
2470 env->msr_hv_runtime = msrs[i].data;
2471 break;
866eea9a
AS		 2472 case HV_X64_MSR_SCONTROL:
2473 env->msr_hv_synic_control = msrs[i].data;
2474 break;
866eea9a
AS		 2475 case HV_X64_MSR_SIEFP:
2476 env->msr_hv_synic_evt_page = msrs[i].data;
2477 break;
2478 case HV_X64_MSR_SIMP:
2479 env->msr_hv_synic_msg_page = msrs[i].data;
2480 break;
2481 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2482 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2483 break;
2484 case HV_X64_MSR_STIMER0_CONFIG:
2485 case HV_X64_MSR_STIMER1_CONFIG:
2486 case HV_X64_MSR_STIMER2_CONFIG:
2487 case HV_X64_MSR_STIMER3_CONFIG:
2488 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2489 msrs[i].data;
2490 break;
2491 case HV_X64_MSR_STIMER0_COUNT:
2492 case HV_X64_MSR_STIMER1_COUNT:
2493 case HV_X64_MSR_STIMER2_COUNT:
2494 case HV_X64_MSR_STIMER3_COUNT:
2495 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2496 msrs[i].data;
866eea9a 2497 break;
ba6a4fd9
VK		 2498 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2499 env->msr_hv_reenlightenment_control = msrs[i].data;
2500 break;
2501 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2502 env->msr_hv_tsc_emulation_control = msrs[i].data;
2503 break;
2504 case HV_X64_MSR_TSC_EMULATION_STATUS:
2505 env->msr_hv_tsc_emulation_status = msrs[i].data;
2506 break;
d1ae67f6
AW		 2507 case MSR_MTRRdefType:
2508 env->mtrr_deftype = msrs[i].data;
2509 break;
2510 case MSR_MTRRfix64K_00000:
2511 env->mtrr_fixed[0] = msrs[i].data;
2512 break;
2513 case MSR_MTRRfix16K_80000:
2514 env->mtrr_fixed[1] = msrs[i].data;
2515 break;
2516 case MSR_MTRRfix16K_A0000:
2517 env->mtrr_fixed[2] = msrs[i].data;
2518 break;
2519 case MSR_MTRRfix4K_C0000:
2520 env->mtrr_fixed[3] = msrs[i].data;
2521 break;
2522 case MSR_MTRRfix4K_C8000:
2523 env->mtrr_fixed[4] = msrs[i].data;
2524 break;
2525 case MSR_MTRRfix4K_D0000:
2526 env->mtrr_fixed[5] = msrs[i].data;
2527 break;
2528 case MSR_MTRRfix4K_D8000:
2529 env->mtrr_fixed[6] = msrs[i].data;
2530 break;
2531 case MSR_MTRRfix4K_E0000:
2532 env->mtrr_fixed[7] = msrs[i].data;
2533 break;
2534 case MSR_MTRRfix4K_E8000:
2535 env->mtrr_fixed[8] = msrs[i].data;
2536 break;
2537 case MSR_MTRRfix4K_F0000:
2538 env->mtrr_fixed[9] = msrs[i].data;
2539 break;
2540 case MSR_MTRRfix4K_F8000:
2541 env->mtrr_fixed[10] = msrs[i].data;
2542 break;
2543 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2544 if (index & 1) {
fcc35e7c
DDAG		 2545 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2546 mtrr_top_bits;
d1ae67f6
AW		 2547 } else {
2548 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2549 }
2550 break;
a33a2cfe
PB		 2551 case MSR_IA32_SPEC_CTRL:
2552 env->spec_ctrl = msrs[i].data;
2553 break;
cfeea0c0
KRW		 2554 case MSR_VIRT_SSBD:
2555 env->virt_ssbd = msrs[i].data;
2556 break;
b77146e9
CP		 2557 case MSR_IA32_RTIT_CTL:
2558 env->msr_rtit_ctrl = msrs[i].data;
2559 break;
2560 case MSR_IA32_RTIT_STATUS:
2561 env->msr_rtit_status = msrs[i].data;
2562 break;
2563 case MSR_IA32_RTIT_OUTPUT_BASE:
2564 env->msr_rtit_output_base = msrs[i].data;
2565 break;
2566 case MSR_IA32_RTIT_OUTPUT_MASK:
2567 env->msr_rtit_output_mask = msrs[i].data;
2568 break;
2569 case MSR_IA32_RTIT_CR3_MATCH:
2570 env->msr_rtit_cr3_match = msrs[i].data;
2571 break;
2572 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2573 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2574 break;
05330448
AL		 2575 }
2576 }
2577
2578 return 0;
2579}
2580
1bc22652 2581static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2582{
1bc22652 2583 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2584
1bc22652 2585 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2586}
2587
23d02d9b 2588static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2589{
259186a7 2590 CPUState *cs = CPU(cpu);
23d02d9b 2591 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2592 struct kvm_mp_state mp_state;
2593 int ret;
2594
259186a7 2595 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2596 if (ret < 0) {
2597 return ret;
2598 }
2599 env->mp_state = mp_state.mp_state;
c14750e8 2600 if (kvm_irqchip_in_kernel()) {
259186a7 2601 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2602 }
9bdbe550
HB		 2603 return 0;
2604}
2605
1bc22652 2606static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2607{
02e51483 2608 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2609 struct kvm_lapic_state kapic;
2610 int ret;
2611
3d4b2649 2612 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2613 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2614 if (ret < 0) {
2615 return ret;
2616 }
2617
2618 kvm_get_apic_state(apic, &kapic);
2619 }
2620 return 0;
2621}
2622
1bc22652 2623static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2624{
fc12d72e 2625 CPUState *cs = CPU(cpu);
1bc22652 2626 CPUX86State *env = &cpu->env;
076796f8 2627 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2628
2629 if (!kvm_has_vcpu_events()) {
2630 return 0;
2631 }
2632
31827373
JK		 2633 events.exception.injected = (env->exception_injected >= 0);
2634 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2635 events.exception.has_error_code = env->has_error_code;
2636 events.exception.error_code = env->error_code;
7e680753 2637 events.exception.pad = 0;
a0fb002c
JK		 2638
2639 events.interrupt.injected = (env->interrupt_injected >= 0);
2640 events.interrupt.nr = env->interrupt_injected;
2641 events.interrupt.soft = env->soft_interrupt;
2642
2643 events.nmi.injected = env->nmi_injected;
2644 events.nmi.pending = env->nmi_pending;
2645 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2646 events.nmi.pad = 0;
a0fb002c
JK		 2647
2648 events.sipi_vector = env->sipi_vector;
68c6efe0 2649 events.flags = 0;
a0fb002c 2650
fc12d72e
PB		 2651 if (has_msr_smbase) {
2652 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2653 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2654 if (kvm_irqchip_in_kernel()) {
2655 /* As soon as these are moved to the kernel, remove them
2656 * from cs->interrupt_request.
2657 */
2658 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2659 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2660 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2661 } else {
2662 /* Keep these in cs->interrupt_request. */
2663 events.smi.pending = 0;
2664 events.smi.latched_init = 0;
2665 }
fc3a1fd7
DDAG		 2666 /* Stop SMI delivery on old machine types to avoid a reboot
2667 * on an inward migration of an old VM.
2668 */
2669 if (!cpu->kvm_no_smi_migration) {
2670 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2671 }
fc12d72e
PB		 2672 }
2673
ea643051 2674 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2675 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2676 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2677 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2678 }
ea643051 2679 }
aee028b9 2680
1bc22652 2681 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2682}
2683
1bc22652 2684static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2685{
1bc22652 2686 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2687 struct kvm_vcpu_events events;
2688 int ret;
2689
2690 if (!kvm_has_vcpu_events()) {
2691 return 0;
2692 }
2693
fc12d72e 2694 memset(&events, 0, sizeof(events));
1bc22652 2695 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2696 if (ret < 0) {
2697 return ret;
2698 }
31827373 2699 env->exception_injected =
a0fb002c
JK		 2700 events.exception.injected ? events.exception.nr : -1;
2701 env->has_error_code = events.exception.has_error_code;
2702 env->error_code = events.exception.error_code;
2703
2704 env->interrupt_injected =
2705 events.interrupt.injected ? events.interrupt.nr : -1;
2706 env->soft_interrupt = events.interrupt.soft;
2707
2708 env->nmi_injected = events.nmi.injected;
2709 env->nmi_pending = events.nmi.pending;
2710 if (events.nmi.masked) {
2711 env->hflags2 |= HF2_NMI_MASK;
2712 } else {
2713 env->hflags2 &= ~HF2_NMI_MASK;
2714 }
2715
fc12d72e
PB		 2716 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2717 if (events.smi.smm) {
2718 env->hflags |= HF_SMM_MASK;
2719 } else {
2720 env->hflags &= ~HF_SMM_MASK;
2721 }
2722 if (events.smi.pending) {
2723 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2724 } else {
2725 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2726 }
2727 if (events.smi.smm_inside_nmi) {
2728 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2729 } else {
2730 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2731 }
2732 if (events.smi.latched_init) {
2733 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2734 } else {
2735 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2736 }
2737 }
2738
a0fb002c 2739 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2740
2741 return 0;
2742}
2743
1bc22652 2744static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2745{
ed2803da 2746 CPUState *cs = CPU(cpu);
1bc22652 2747 CPUX86State *env = &cpu->env;
b0b1d690 2748 int ret = 0;
b0b1d690
JK		 2749 unsigned long reinject_trap = 0;
2750
2751 if (!kvm_has_vcpu_events()) {
2752 if (env->exception_injected == 1) {
2753 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2754 } else if (env->exception_injected == 3) {
2755 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2756 }
2757 env->exception_injected = -1;
2758 }
2759
2760 /*
2761 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2762 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2763 * by updating the debug state once again if single-stepping is on.
2764 * Another reason to call kvm_update_guest_debug here is a pending debug
2765 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2766 * reinject them via SET_GUEST_DEBUG.
2767 */
2768 if (reinject_trap ||
ed2803da 2769 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2770 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2771 }
b0b1d690
JK		 2772 return ret;
2773}
2774
1bc22652 2775static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2776{
1bc22652 2777 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2778 struct kvm_debugregs dbgregs;
2779 int i;
2780
2781 if (!kvm_has_debugregs()) {
2782 return 0;
2783 }
2784
2785 for (i = 0; i < 4; i++) {
2786 dbgregs.db[i] = env->dr[i];
2787 }
2788 dbgregs.dr6 = env->dr[6];
2789 dbgregs.dr7 = env->dr[7];
2790 dbgregs.flags = 0;
2791
1bc22652 2792 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2793}
2794
1bc22652 2795static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2796{
1bc22652 2797 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2798 struct kvm_debugregs dbgregs;
2799 int i, ret;
2800
2801 if (!kvm_has_debugregs()) {
2802 return 0;
2803 }
2804
1bc22652 2805 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2806 if (ret < 0) {
b9bec74b 2807 return ret;
ff44f1a3
JK		 2808 }
2809 for (i = 0; i < 4; i++) {
2810 env->dr[i] = dbgregs.db[i];
2811 }
2812 env->dr[4] = env->dr[6] = dbgregs.dr6;
2813 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2814
2815 return 0;
2816}
2817
20d695a9 2818int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2819{
20d695a9 2820 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2821 int ret;
2822
2fa45344 2823 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2824
48e1a45c 2825 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2826 ret = kvm_put_msr_feature_control(x86_cpu);
2827 if (ret < 0) {
2828 return ret;
2829 }
2830 }
2831
36f96c4b
HZ		 2832 if (level == KVM_PUT_FULL_STATE) {
2833 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2834 * because TSC frequency mismatch shouldn't abort migration,
2835 * unless the user explicitly asked for a more strict TSC
2836 * setting (e.g. using an explicit "tsc-freq" option).
2837 */
2838 kvm_arch_set_tsc_khz(cpu);
2839 }
2840
1bc22652 2841 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2842 if (ret < 0) {
05330448 2843 return ret;
b9bec74b 2844 }
1bc22652 2845 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2846 if (ret < 0) {
f1665b21 2847 return ret;
b9bec74b 2848 }
1bc22652 2849 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2850 if (ret < 0) {
05330448 2851 return ret;
b9bec74b 2852 }
1bc22652 2853 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2854 if (ret < 0) {
05330448 2855 return ret;
b9bec74b 2856 }
ab443475 2857 /* must be before kvm_put_msrs */
1bc22652 2858 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2859 if (ret < 0) {
2860 return ret;
2861 }
1bc22652 2862 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2863 if (ret < 0) {
05330448 2864 return ret;
b9bec74b 2865 }
4fadfa00
PH		 2866 ret = kvm_put_vcpu_events(x86_cpu, level);
2867 if (ret < 0) {
2868 return ret;
2869 }
ea643051 2870 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2871 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2872 if (ret < 0) {
680c1c6f
JK		 2873 return ret;
2874 }
ea643051 2875 }
7477cd38
MT		 2876
2877 ret = kvm_put_tscdeadline_msr(x86_cpu);
2878 if (ret < 0) {
2879 return ret;
2880 }
1bc22652 2881 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2882 if (ret < 0) {
b0b1d690 2883 return ret;
b9bec74b 2884 }
b0b1d690 2885 /* must be last */
1bc22652 2886 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2887 if (ret < 0) {
ff44f1a3 2888 return ret;
b9bec74b 2889 }
05330448
AL		 2890 return 0;
2891}
2892
20d695a9 2893int kvm_arch_get_registers(CPUState *cs)
05330448 2894{
20d695a9 2895 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2896 int ret;
2897
20d695a9 2898 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2899
4fadfa00 2900 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2901 if (ret < 0) {
f4f1110e 2902 goto out;
b9bec74b 2903 }
4fadfa00
PH		 2904 /*
2905 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2906 * KVM_GET_REGS and KVM_GET_SREGS.
2907 */
2908 ret = kvm_get_mp_state(cpu);
b9bec74b 2909 if (ret < 0) {
f4f1110e 2910 goto out;
b9bec74b 2911 }
4fadfa00 2912 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2913 if (ret < 0) {
f4f1110e 2914 goto out;
b9bec74b 2915 }
4fadfa00 2916 ret = kvm_get_xsave(cpu);
b9bec74b 2917 if (ret < 0) {
f4f1110e 2918 goto out;
b9bec74b 2919 }
4fadfa00 2920 ret = kvm_get_xcrs(cpu);
b9bec74b 2921 if (ret < 0) {
f4f1110e 2922 goto out;
b9bec74b 2923 }
4fadfa00 2924 ret = kvm_get_sregs(cpu);
b9bec74b 2925 if (ret < 0) {
f4f1110e 2926 goto out;
b9bec74b 2927 }
4fadfa00 2928 ret = kvm_get_msrs(cpu);
680c1c6f 2929 if (ret < 0) {
f4f1110e 2930 goto out;
680c1c6f 2931 }
4fadfa00 2932 ret = kvm_get_apic(cpu);
b9bec74b 2933 if (ret < 0) {
f4f1110e 2934 goto out;
b9bec74b 2935 }
1bc22652 2936 ret = kvm_get_debugregs(cpu);
b9bec74b 2937 if (ret < 0) {
f4f1110e 2938 goto out;
b9bec74b 2939 }
f4f1110e
RH		 2940 ret = 0;
2941 out:
2942 cpu_sync_bndcs_hflags(&cpu->env);
2943 return ret;
05330448
AL		 2944}
2945
20d695a9 2946void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2947{
20d695a9
AF		 2948 X86CPU *x86_cpu = X86_CPU(cpu);
2949 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2950 int ret;
2951
276ce815 2952 /* Inject NMI */
fc12d72e
PB		 2953 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2954 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2955 qemu_mutex_lock_iothread();
2956 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2957 qemu_mutex_unlock_iothread();
2958 DPRINTF("injected NMI\n");
2959 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2960 if (ret < 0) {
2961 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2962 strerror(-ret));
2963 }
2964 }
2965 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2966 qemu_mutex_lock_iothread();
2967 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2968 qemu_mutex_unlock_iothread();
2969 DPRINTF("injected SMI\n");
2970 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2971 if (ret < 0) {
2972 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2973 strerror(-ret));
2974 }
ce377af3 2975 }
276ce815
LJ		 2976 }
2977
15eafc2e 2978 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2979 qemu_mutex_lock_iothread();
2980 }
2981
e0723c45
PB		 2982 /* Force the VCPU out of its inner loop to process any INIT requests
2983 * or (for userspace APIC, but it is cheap to combine the checks here)
2984 * pending TPR access reports.
2985 */
2986 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2987 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2988 !(env->hflags & HF_SMM_MASK)) {
2989 cpu->exit_request = 1;
2990 }
2991 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2992 cpu->exit_request = 1;
2993 }
e0723c45 2994 }
05330448 2995
15eafc2e 2996 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2997 /* Try to inject an interrupt if the guest can accept it */
2998 if (run->ready_for_interrupt_injection &&
259186a7 2999 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3000 (env->eflags & IF_MASK)) {
3001 int irq;
3002
259186a7 3003 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3004 irq = cpu_get_pic_interrupt(env);
3005 if (irq >= 0) {
3006 struct kvm_interrupt intr;
3007
3008 intr.irq = irq;
db1669bc 3009 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3010 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3011 if (ret < 0) {
3012 fprintf(stderr,
3013 "KVM: injection failed, interrupt lost (%s)\n",
3014 strerror(-ret));
3015 }
db1669bc
JK		 3016 }
3017 }
05330448 3018
db1669bc
JK		 3019 /* If we have an interrupt but the guest is not ready to receive an
3020 * interrupt, request an interrupt window exit. This will
3021 * cause a return to userspace as soon as the guest is ready to
3022 * receive interrupts. */
259186a7 3023 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3024 run->request_interrupt_window = 1;
3025 } else {
3026 run->request_interrupt_window = 0;
3027 }
3028
3029 DPRINTF("setting tpr\n");
02e51483 3030 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3031
3032 qemu_mutex_unlock_iothread();
db1669bc 3033 }
05330448
AL		 3034}
3035
4c663752 3036MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3037{
20d695a9
AF		 3038 X86CPU *x86_cpu = X86_CPU(cpu);
3039 CPUX86State *env = &x86_cpu->env;
3040
fc12d72e
PB		 3041 if (run->flags & KVM_RUN_X86_SMM) {
3042 env->hflags |= HF_SMM_MASK;
3043 } else {
f5c052b9 3044 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3045 }
b9bec74b 3046 if (run->if_flag) {
05330448 3047 env->eflags |= IF_MASK;
b9bec74b 3048 } else {
05330448 3049 env->eflags &= ~IF_MASK;
b9bec74b 3050 }
4b8523ee
JK		 3051
3052 /* We need to protect the apic state against concurrent accesses from
3053 * different threads in case the userspace irqchip is used. */
3054 if (!kvm_irqchip_in_kernel()) {
3055 qemu_mutex_lock_iothread();
3056 }
02e51483
CF		 3057 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3058 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3059 if (!kvm_irqchip_in_kernel()) {
3060 qemu_mutex_unlock_iothread();
3061 }
f794aa4a 3062 return cpu_get_mem_attrs(env);
05330448
AL		 3063}
3064
20d695a9 3065int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3066{
20d695a9
AF		 3067 X86CPU *cpu = X86_CPU(cs);
3068 CPUX86State *env = &cpu->env;
232fc23b 3069
259186a7 3070 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3071 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3072 assert(env->mcg_cap);
3073
259186a7 3074 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3075
dd1750d7 3076 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3077
3078 if (env->exception_injected == EXCP08_DBLE) {
3079 /* this means triple fault */
cf83f140 3080 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3081 cs->exit_request = 1;
ab443475
JK		 3082 return 0;
3083 }
3084 env->exception_injected = EXCP12_MCHK;
3085 env->has_error_code = 0;
3086
259186a7 3087 cs->halted = 0;
ab443475
JK		 3088 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3089 env->mp_state = KVM_MP_STATE_RUNNABLE;
3090 }
3091 }
3092
fc12d72e
PB		 3093 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3094 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3095 kvm_cpu_synchronize_state(cs);
3096 do_cpu_init(cpu);
3097 }
3098
db1669bc
JK		 3099 if (kvm_irqchip_in_kernel()) {
3100 return 0;
3101 }
3102
259186a7
AF		 3103 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3104 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3105 apic_poll_irq(cpu->apic_state);
5d62c43a 3106 }
259186a7 3107 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3108 (env->eflags & IF_MASK)) ||
259186a7
AF		 3109 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3110 cs->halted = 0;
6792a57b 3111 }
259186a7 3112 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3113 kvm_cpu_synchronize_state(cs);
232fc23b 3114 do_cpu_sipi(cpu);
0af691d7 3115 }
259186a7
AF		 3116 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3117 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3118 kvm_cpu_synchronize_state(cs);
02e51483 3119 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3120 env->tpr_access_type);
3121 }
0af691d7 3122
259186a7 3123 return cs->halted;
0af691d7
MT		 3124}
3125
839b5630 3126static int kvm_handle_halt(X86CPU *cpu)
05330448 3127{
259186a7 3128 CPUState *cs = CPU(cpu);
839b5630
AF		 3129 CPUX86State *env = &cpu->env;
3130
259186a7 3131 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3132 (env->eflags & IF_MASK)) &&
259186a7
AF		 3133 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3134 cs->halted = 1;
bb4ea393 3135 return EXCP_HLT;
05330448
AL		 3136 }
3137
bb4ea393 3138 return 0;
05330448
AL		 3139}
3140
f7575c96 3141static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3142{
f7575c96
AF		 3143 CPUState *cs = CPU(cpu);
3144 struct kvm_run *run = cs->kvm_run;
d362e757 3145
02e51483 3146 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3147 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3148 : TPR_ACCESS_READ);
3149 return 1;
3150}
3151
f17ec444 3152int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3153{
38972938 3154 static const uint8_t int3 = 0xcc;
64bf3f4e 3155
f17ec444
AF		 3156 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3157 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3158 return -EINVAL;
b9bec74b 3159 }
e22a25c9
AL		 3160 return 0;
3161}
3162
f17ec444 3163int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3164{
3165 uint8_t int3;
3166
f17ec444
AF		 3167 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3168 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3169 return -EINVAL;
b9bec74b 3170 }
e22a25c9
AL		 3171 return 0;
3172}
3173
3174static struct {
3175 target_ulong addr;
3176 int len;
3177 int type;
3178} hw_breakpoint[4];
3179
3180static int nb_hw_breakpoint;
3181
3182static int find_hw_breakpoint(target_ulong addr, int len, int type)
3183{
3184 int n;
3185
b9bec74b 3186 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3187 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3188 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3189 return n;
b9bec74b
JK		 3190 }
3191 }
e22a25c9
AL		 3192 return -1;
3193}
3194
3195int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3196 target_ulong len, int type)
3197{
3198 switch (type) {
3199 case GDB_BREAKPOINT_HW:
3200 len = 1;
3201 break;
3202 case GDB_WATCHPOINT_WRITE:
3203 case GDB_WATCHPOINT_ACCESS:
3204 switch (len) {
3205 case 1:
3206 break;
3207 case 2:
3208 case 4:
3209 case 8:
b9bec74b 3210 if (addr & (len - 1)) {
e22a25c9 3211 return -EINVAL;
b9bec74b 3212 }
e22a25c9
AL		 3213 break;
3214 default:
3215 return -EINVAL;
3216 }
3217 break;
3218 default:
3219 return -ENOSYS;
3220 }
3221
b9bec74b 3222 if (nb_hw_breakpoint == 4) {
e22a25c9 3223 return -ENOBUFS;
b9bec74b
JK		 3224 }
3225 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3226 return -EEXIST;
b9bec74b 3227 }
e22a25c9
AL		 3228 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3229 hw_breakpoint[nb_hw_breakpoint].len = len;
3230 hw_breakpoint[nb_hw_breakpoint].type = type;
3231 nb_hw_breakpoint++;
3232
3233 return 0;
3234}
3235
3236int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3237 target_ulong len, int type)
3238{
3239 int n;
3240
3241 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3242 if (n < 0) {
e22a25c9 3243 return -ENOENT;
b9bec74b 3244 }
e22a25c9
AL		 3245 nb_hw_breakpoint--;
3246 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3247
3248 return 0;
3249}
3250
3251void kvm_arch_remove_all_hw_breakpoints(void)
3252{
3253 nb_hw_breakpoint = 0;
3254}
3255
3256static CPUWatchpoint hw_watchpoint;
3257
a60f24b5 3258static int kvm_handle_debug(X86CPU *cpu,
48405526 3259 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3260{
ed2803da 3261 CPUState *cs = CPU(cpu);
a60f24b5 3262 CPUX86State *env = &cpu->env;
f2574737 3263 int ret = 0;
e22a25c9
AL		 3264 int n;
3265
3266 if (arch_info->exception == 1) {
3267 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3268 if (cs->singlestep_enabled) {
f2574737 3269 ret = EXCP_DEBUG;
b9bec74b 3270 }
e22a25c9 3271 } else {
b9bec74b
JK		 3272 for (n = 0; n < 4; n++) {
3273 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3274 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3275 case 0x0:
f2574737 3276 ret = EXCP_DEBUG;
e22a25c9
AL		 3277 break;
3278 case 0x1:
f2574737 3279 ret = EXCP_DEBUG;
ff4700b0 3280 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3281 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3282 hw_watchpoint.flags = BP_MEM_WRITE;
3283 break;
3284 case 0x3:
f2574737 3285 ret = EXCP_DEBUG;
ff4700b0 3286 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3287 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3288 hw_watchpoint.flags = BP_MEM_ACCESS;
3289 break;
3290 }
b9bec74b
JK		 3291 }
3292 }
e22a25c9 3293 }
ff4700b0 3294 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3295 ret = EXCP_DEBUG;
b9bec74b 3296 }
f2574737 3297 if (ret == 0) {
ff4700b0 3298 cpu_synchronize_state(cs);
48405526 3299 assert(env->exception_injected == -1);
b0b1d690 3300
f2574737 3301 /* pass to guest */
48405526
BS		 3302 env->exception_injected = arch_info->exception;
3303 env->has_error_code = 0;
b0b1d690 3304 }
e22a25c9 3305
f2574737 3306 return ret;
e22a25c9
AL		 3307}
3308
20d695a9 3309void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3310{
3311 const uint8_t type_code[] = {
3312 [GDB_BREAKPOINT_HW] = 0x0,
3313 [GDB_WATCHPOINT_WRITE] = 0x1,
3314 [GDB_WATCHPOINT_ACCESS] = 0x3
3315 };
3316 const uint8_t len_code[] = {
3317 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3318 };
3319 int n;
3320
a60f24b5 3321 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3322 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3323 }
e22a25c9
AL		 3324 if (nb_hw_breakpoint > 0) {
3325 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3326 dbg->arch.debugreg[7] = 0x0600;
3327 for (n = 0; n < nb_hw_breakpoint; n++) {
3328 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3329 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3330 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3331 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3332 }
3333 }
3334}
4513d923 3335
2a4dac83
JK		 3336static bool host_supports_vmx(void)
3337{
3338 uint32_t ecx, unused;
3339
3340 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3341 return ecx & CPUID_EXT_VMX;
3342}
3343
3344#define VMX_INVALID_GUEST_STATE 0x80000021
3345
20d695a9 3346int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3347{
20d695a9 3348 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3349 uint64_t code;
3350 int ret;
3351
3352 switch (run->exit_reason) {
3353 case KVM_EXIT_HLT:
3354 DPRINTF("handle_hlt\n");
4b8523ee 3355 qemu_mutex_lock_iothread();
839b5630 3356 ret = kvm_handle_halt(cpu);
4b8523ee 3357 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3358 break;
3359 case KVM_EXIT_SET_TPR:
3360 ret = 0;
3361 break;
d362e757 3362 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3363 qemu_mutex_lock_iothread();
f7575c96 3364 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3365 qemu_mutex_unlock_iothread();
d362e757 3366 break;
2a4dac83
JK		 3367 case KVM_EXIT_FAIL_ENTRY:
3368 code = run->fail_entry.hardware_entry_failure_reason;
3369 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3370 code);
3371 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3372 fprintf(stderr,
12619721 3373 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3374 "unrestricted mode\n"
3375 "support, the failure can be most likely due to the guest "
3376 "entering an invalid\n"
3377 "state for Intel VT. For example, the guest maybe running "
3378 "in big real mode\n"
3379 "which is not supported on less recent Intel processors."
3380 "\n\n");
3381 }
3382 ret = -1;
3383 break;
3384 case KVM_EXIT_EXCEPTION:
3385 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3386 run->ex.exception, run->ex.error_code);
3387 ret = -1;
3388 break;
f2574737
JK		 3389 case KVM_EXIT_DEBUG:
3390 DPRINTF("kvm_exit_debug\n");
4b8523ee 3391 qemu_mutex_lock_iothread();
a60f24b5 3392 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3393 qemu_mutex_unlock_iothread();
f2574737 3394 break;
50efe82c
AS		 3395 case KVM_EXIT_HYPERV:
3396 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3397 break;
15eafc2e
PB		 3398 case KVM_EXIT_IOAPIC_EOI:
3399 ioapic_eoi_broadcast(run->eoi.vector);
3400 ret = 0;
3401 break;
2a4dac83
JK		 3402 default:
3403 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3404 ret = -1;
3405 break;
3406 }
3407
3408 return ret;
3409}
3410
20d695a9 3411bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3412{
20d695a9
AF		 3413 X86CPU *cpu = X86_CPU(cs);
3414 CPUX86State *env = &cpu->env;
3415
dd1750d7 3416 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3417 return !(env->cr[0] & CR0_PE_MASK) ||
3418 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3419}
84b058d7
JK		 3420
3421void kvm_arch_init_irq_routing(KVMState *s)
3422{
3423 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3424 /* If kernel can't do irq routing, interrupt source
3425 * override 0->2 cannot be set up as required by HPET.
3426 * So we have to disable it.
3427 */
3428 no_hpet = 1;
3429 }
cc7e0ddf 3430 /* We know at this point that we're using the in-kernel
614e41bc 3431 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3432 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3433 */
614e41bc 3434 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3435 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3436
3437 if (kvm_irqchip_is_split()) {
3438 int i;
3439
3440 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3441 MSI routes for signaling interrupts to the local apics. */
3442 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3443 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3444 error_report("Could not enable split IRQ mode.");
3445 exit(1);
3446 }
3447 }
3448 }
3449}
3450
3451int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3452{
3453 int ret;
3454 if (machine_kernel_irqchip_split(ms)) {
3455 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3456 if (ret) {
df3c286c 3457 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3458 strerror(-ret));
3459 exit(1);
3460 } else {
3461 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3462 kvm_split_irqchip = true;
3463 return 1;
3464 }
3465 } else {
3466 return 0;
3467 }
84b058d7 3468}
b139bd30
JK		 3469
3470/* Classic KVM device assignment interface. Will remain x86 only. */
3471int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3472 uint32_t flags, uint32_t *dev_id)
3473{
3474 struct kvm_assigned_pci_dev dev_data = {
3475 .segnr = dev_addr->domain,
3476 .busnr = dev_addr->bus,
3477 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3478 .flags = flags,
3479 };
3480 int ret;
3481
3482 dev_data.assigned_dev_id =
3483 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3484
3485 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3486 if (ret < 0) {
3487 return ret;
3488 }
3489
3490 *dev_id = dev_data.assigned_dev_id;
3491
3492 return 0;
3493}
3494
3495int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3496{
3497 struct kvm_assigned_pci_dev dev_data = {
3498 .assigned_dev_id = dev_id,
3499 };
3500
3501 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3502}
3503
3504static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3505 uint32_t irq_type, uint32_t guest_irq)
3506{
3507 struct kvm_assigned_irq assigned_irq = {
3508 .assigned_dev_id = dev_id,
3509 .guest_irq = guest_irq,
3510 .flags = irq_type,
3511 };
3512
3513 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3514 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3515 } else {
3516 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3517 }
3518}
3519
3520int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3521 uint32_t guest_irq)
3522{
3523 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3524 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3525
3526 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3527}
3528
3529int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3530{
3531 struct kvm_assigned_pci_dev dev_data = {
3532 .assigned_dev_id = dev_id,
3533 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3534 };
3535
3536 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3537}
3538
3539static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3540 uint32_t type)
3541{
3542 struct kvm_assigned_irq assigned_irq = {
3543 .assigned_dev_id = dev_id,
3544 .flags = type,
3545 };
3546
3547 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3548}
3549
3550int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3551{
3552 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3553 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3554}
3555
3556int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3557{
3558 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3559 KVM_DEV_IRQ_GUEST_MSI, virq);
3560}
3561
3562int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3563{
3564 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3565 KVM_DEV_IRQ_HOST_MSI);
3566}
3567
3568bool kvm_device_msix_supported(KVMState *s)
3569{
3570 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3571 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3572 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3573}
3574
3575int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3576 uint32_t nr_vectors)
3577{
3578 struct kvm_assigned_msix_nr msix_nr = {
3579 .assigned_dev_id = dev_id,
3580 .entry_nr = nr_vectors,
3581 };
3582
3583 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3584}
3585
3586int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3587 int virq)
3588{
3589 struct kvm_assigned_msix_entry msix_entry = {
3590 .assigned_dev_id = dev_id,
3591 .gsi = virq,
3592 .entry = vector,
3593 };
3594
3595 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3596}
3597
3598int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3599{
3600 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3601 KVM_DEV_IRQ_GUEST_MSIX, 0);
3602}
3603
3604int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3605{
3606 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3607 KVM_DEV_IRQ_HOST_MSIX);
3608}
9e03a040
FB		 3609
3610int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3611 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3612{
8b5ed7df
PX		 3613 X86IOMMUState *iommu = x86_iommu_get_default();
3614
3615 if (iommu) {
3616 int ret;
3617 MSIMessage src, dst;
3618 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3619
3620 src.address = route->u.msi.address_hi;
3621 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3622 src.address |= route->u.msi.address_lo;
3623 src.data = route->u.msi.data;
3624
3625 ret = class->int_remap(iommu, &src, &dst, dev ? \
3626 pci_requester_id(dev) : \
3627 X86_IOMMU_SID_INVALID);
3628 if (ret) {
3629 trace_kvm_x86_fixup_msi_error(route->gsi);
3630 return 1;
3631 }
3632
3633 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3634 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3635 route->u.msi.data = dst.data;
3636 }
3637
9e03a040
FB		 3638 return 0;
3639}
1850b6b7 3640
38d87493
PX		 3641typedef struct MSIRouteEntry MSIRouteEntry;
3642
3643struct MSIRouteEntry {
3644 PCIDevice *dev; /* Device pointer */
3645 int vector; /* MSI/MSIX vector index */
3646 int virq; /* Virtual IRQ index */
3647 QLIST_ENTRY(MSIRouteEntry) list;
3648};
3649
3650/* List of used GSI routes */
3651static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3652 QLIST_HEAD_INITIALIZER(msi_route_list);
3653
e1d4fb2d
PX		 3654static void kvm_update_msi_routes_all(void *private, bool global,
3655 uint32_t index, uint32_t mask)
3656{
3657 int cnt = 0;
3658 MSIRouteEntry *entry;
3659 MSIMessage msg;
fd563564
PX		 3660 PCIDevice *dev;
3661
e1d4fb2d
PX		 3662 /* TODO: explicit route update */
3663 QLIST_FOREACH(entry, &msi_route_list, list) {
3664 cnt++;
fd563564
PX		 3665 dev = entry->dev;
3666 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3667 continue;
3668 }
3669 msg = pci_get_msi_message(dev, entry->vector);
3670 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3671 }
3f1fea0f 3672 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3673 trace_kvm_x86_update_msi_routes(cnt);
3674}
3675
38d87493
PX		 3676int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3677 int vector, PCIDevice *dev)
3678{
e1d4fb2d 3679 static bool notify_list_inited = false;
38d87493
PX		 3680 MSIRouteEntry *entry;
3681
3682 if (!dev) {
3683 /* These are (possibly) IOAPIC routes only used for split
3684 * kernel irqchip mode, while what we are housekeeping are
3685 * PCI devices only. */
3686 return 0;
3687 }
3688
3689 entry = g_new0(MSIRouteEntry, 1);
3690 entry->dev = dev;
3691 entry->vector = vector;
3692 entry->virq = route->gsi;
3693 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3694
3695 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3696
3697 if (!notify_list_inited) {
3698 /* For the first time we do add route, add ourselves into
3699 * IOMMU's IEC notify list if needed. */
3700 X86IOMMUState *iommu = x86_iommu_get_default();
3701 if (iommu) {
3702 x86_iommu_iec_register_notifier(iommu,
3703 kvm_update_msi_routes_all,
3704 NULL);
3705 }
3706 notify_list_inited = true;
3707 }
38d87493
PX		 3708 return 0;
3709}
3710
3711int kvm_arch_release_virq_post(int virq)
3712{
3713 MSIRouteEntry *entry, *next;
3714 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3715 if (entry->virq == virq) {
3716 trace_kvm_x86_remove_msi_route(virq);
3717 QLIST_REMOVE(entry, list);
01960e6d 3718 g_free(entry);
38d87493
PX		 3719 break;
3720 }
3721 }
9e03a040
FB		 3722 return 0;
3723}
1850b6b7
EA		 3724
3725int kvm_arch_msi_data_to_gsi(uint32_t data)
3726{
3727 abort();
3728}
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