]> git.proxmox.com Git - mirror_qemu.git/blame - target/i386/kvm.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
hw/i386/pc: Use e820_get_num_entries() to access e820_entries
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
71e8a915 27#include "sysemu/reset.h"
54d31236 28#include "sysemu/runstate.h"
1d31f66b 29#include "kvm_i386.h"
50efe82c 30#include "hyperv.h"
5e953812 31#include "hyperv-proto.h"
50efe82c 32
022c62cb 33#include "exec/gdbstub.h"
1de7afc9 34#include "qemu/host-utils.h"
db725815 35#include "qemu/main-loop.h"
1de7afc9 36#include "qemu/config-file.h"
1c4a55db 37#include "qemu/error-report.h"
0d09e41a
PB		 38#include "hw/i386/pc.h"
39#include "hw/i386/apic.h"
e0723c45
PB		 40#include "hw/i386/apic_internal.h"
41#include "hw/i386/apic-msidef.h"
8b5ed7df 42#include "hw/i386/intel_iommu.h"
e1d4fb2d 43#include "hw/i386/x86-iommu.h"
50efe82c 44
a2cb15b0 45#include "hw/pci/pci.h"
15eafc2e 46#include "hw/pci/msi.h"
fd563564 47#include "hw/pci/msix.h"
795c40b8 48#include "migration/blocker.h"
4c663752 49#include "exec/memattrs.h"
8b5ed7df 50#include "trace.h"
05330448
AL		 51
52//#define DEBUG_KVM
53
54#ifdef DEBUG_KVM
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
57#else
8c0d577e 58#define DPRINTF(fmt, ...) \
05330448
AL		 59 do { } while (0)
60#endif
61
1a03675d
GC		 62#define MSR_KVM_WALL_CLOCK 0x11
63#define MSR_KVM_SYSTEM_TIME 0x12
64
d1138251
EH		 65/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
66 * 255 kvm_msr_entry structs */
67#define MSR_BUF_SIZE 4096
d71b62a1 68
94a8d39a
JK		 69const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
70 KVM_CAP_INFO(SET_TSS_ADDR),
71 KVM_CAP_INFO(EXT_CPUID),
72 KVM_CAP_INFO(MP_STATE),
73 KVM_CAP_LAST_INFO
74};
25d2e361 75
c3a3a7d3
JK		 76static bool has_msr_star;
77static bool has_msr_hsave_pa;
c9b8f6b6 78static bool has_msr_tsc_aux;
f28558d3 79static bool has_msr_tsc_adjust;
aa82ba54 80static bool has_msr_tsc_deadline;
df67696e 81static bool has_msr_feature_control;
21e87c46 82static bool has_msr_misc_enable;
fc12d72e 83static bool has_msr_smbase;
79e9ebeb 84static bool has_msr_bndcfgs;
25d2e361 85static int lm_capable_kernel;
7bc3d711 86static bool has_msr_hv_hypercall;
f2a53c9e 87static bool has_msr_hv_crash;
744b8a94 88static bool has_msr_hv_reset;
8c145d7c 89static bool has_msr_hv_vpindex;
e9688fab 90static bool hv_vpindex_settable;
46eb8f98 91static bool has_msr_hv_runtime;
866eea9a 92static bool has_msr_hv_synic;
ff99aa64 93static bool has_msr_hv_stimer;
d72bc7f6 94static bool has_msr_hv_frequencies;
ba6a4fd9 95static bool has_msr_hv_reenlightenment;
18cd2c17 96static bool has_msr_xss;
a33a2cfe 97static bool has_msr_spec_ctrl;
cfeea0c0 98static bool has_msr_virt_ssbd;
e13713db 99static bool has_msr_smi_count;
aec5e9c3 100static bool has_msr_arch_capabs;
597360c0 101static bool has_msr_core_capabs;
b827df58 102
0b368a10
JD		 103static uint32_t has_architectural_pmu_version;
104static uint32_t num_architectural_pmu_gp_counters;
105static uint32_t num_architectural_pmu_fixed_counters;
0d894367 106
28143b40
TH		 107static int has_xsave;
108static int has_xcrs;
109static int has_pit_state2;
fd13f23b 110static int has_exception_payload;
28143b40 111
87f8b626
AR		 112static bool has_msr_mcg_ext_ctl;
113
494e95e9 114static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 115static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 116
28143b40
TH		 117int kvm_has_pit_state2(void)
118{
119 return has_pit_state2;
120}
121
355023f2
PB		 122bool kvm_has_smm(void)
123{
124 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
125}
126
6053a86f
MT		 127bool kvm_has_adjust_clock_stable(void)
128{
129 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
130
131 return (ret == KVM_CLOCK_TSC_STABLE);
132}
133
79a197ab
LA		 134bool kvm_has_exception_payload(void)
135{
136 return has_exception_payload;
137}
138
1d31f66b
PM		 139bool kvm_allows_irq0_override(void)
140{
141 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
142}
143
fb506e70
RK		 144static bool kvm_x2apic_api_set_flags(uint64_t flags)
145{
146 KVMState *s = KVM_STATE(current_machine->accelerator);
147
148 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
149}
150
e391c009 151#define MEMORIZE(fn, _result) \
2a138ec3 152 ({ \
2a138ec3
RK		 153 static bool _memorized; \
154 \
155 if (_memorized) { \
156 return _result; \
157 } \
158 _memorized = true; \
159 _result = fn; \
160 })
161
e391c009
IM		 162static bool has_x2apic_api;
163
164bool kvm_has_x2apic_api(void)
165{
166 return has_x2apic_api;
167}
168
fb506e70
RK		 169bool kvm_enable_x2apic(void)
170{
2a138ec3
RK		 171 return MEMORIZE(
172 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 173 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
174 has_x2apic_api);
fb506e70
RK		 175}
176
e9688fab
RK		 177bool kvm_hv_vpindex_settable(void)
178{
179 return hv_vpindex_settable;
180}
181
0fd7e098
LL		 182static int kvm_get_tsc(CPUState *cs)
183{
184 X86CPU *cpu = X86_CPU(cs);
185 CPUX86State *env = &cpu->env;
186 struct {
187 struct kvm_msrs info;
188 struct kvm_msr_entry entries[1];
189 } msr_data;
190 int ret;
191
192 if (env->tsc_valid) {
193 return 0;
194 }
195
1f670a95 196 memset(&msr_data, 0, sizeof(msr_data));
0fd7e098
LL		 197 msr_data.info.nmsrs = 1;
198 msr_data.entries[0].index = MSR_IA32_TSC;
199 env->tsc_valid = !runstate_is_running();
200
201 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
202 if (ret < 0) {
203 return ret;
204 }
205
48e1a45c 206 assert(ret == 1);
0fd7e098
LL		 207 env->tsc = msr_data.entries[0].data;
208 return 0;
209}
210
14e6fe12 211static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 212{
0fd7e098
LL		 213 kvm_get_tsc(cpu);
214}
215
216void kvm_synchronize_all_tsc(void)
217{
218 CPUState *cpu;
219
220 if (kvm_enabled()) {
221 CPU_FOREACH(cpu) {
14e6fe12 222 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 223 }
224 }
225}
226
b827df58
AK		 227static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
228{
229 struct kvm_cpuid2 *cpuid;
230 int r, size;
231
232 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 233 cpuid = g_malloc0(size);
b827df58
AK		 234 cpuid->nent = max;
235 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 236 if (r == 0 && cpuid->nent >= max) {
237 r = -E2BIG;
238 }
b827df58
AK		 239 if (r < 0) {
240 if (r == -E2BIG) {
7267c094 241 g_free(cpuid);
b827df58
AK		 242 return NULL;
243 } else {
244 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
245 strerror(-r));
246 exit(1);
247 }
248 }
249 return cpuid;
250}
251
dd87f8a6
EH		 252/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
253 * for all entries.
254 */
255static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
256{
257 struct kvm_cpuid2 *cpuid;
258 int max = 1;
494e95e9
CP		 259
260 if (cpuid_cache != NULL) {
261 return cpuid_cache;
262 }
dd87f8a6
EH		 263 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
264 max *= 2;
265 }
494e95e9 266 cpuid_cache = cpuid;
dd87f8a6
EH		 267 return cpuid;
268}
269
a443bc34 270static const struct kvm_para_features {
0c31b744
GC		 271 int cap;
272 int feature;
273} para_features[] = {
274 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
275 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
276 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 277 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 278};
279
ba9bc59e 280static int get_para_features(KVMState *s)
0c31b744
GC		 281{
282 int i, features = 0;
283
8e03c100 284 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 285 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 286 features |= (1 << para_features[i].feature);
287 }
288 }
289
290 return features;
291}
0c31b744 292
40e80ee4
EH		 293static bool host_tsx_blacklisted(void)
294{
295 int family, model, stepping;\
296 char vendor[CPUID_VENDOR_SZ + 1];
297
298 host_vendor_fms(vendor, &family, &model, &stepping);
299
300 /* Check if we are running on a Haswell host known to have broken TSX */
301 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
302 (family == 6) &&
303 ((model == 63 && stepping < 4) ||
304 model == 60 || model == 69 || model == 70);
305}
0c31b744 306
829ae2f9
EH		 307/* Returns the value for a specific register on the cpuid entry
308 */
309static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
310{
311 uint32_t ret = 0;
312 switch (reg) {
313 case R_EAX:
314 ret = entry->eax;
315 break;
316 case R_EBX:
317 ret = entry->ebx;
318 break;
319 case R_ECX:
320 ret = entry->ecx;
321 break;
322 case R_EDX:
323 ret = entry->edx;
324 break;
325 }
326 return ret;
327}
328
4fb73f1d
EH		 329/* Find matching entry for function/index on kvm_cpuid2 struct
330 */
331static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
332 uint32_t function,
333 uint32_t index)
334{
335 int i;
336 for (i = 0; i < cpuid->nent; ++i) {
337 if (cpuid->entries[i].function == function &&
338 cpuid->entries[i].index == index) {
339 return &cpuid->entries[i];
340 }
341 }
342 /* not found: */
343 return NULL;
344}
345
ba9bc59e 346uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 347 uint32_t index, int reg)
b827df58
AK		 348{
349 struct kvm_cpuid2 *cpuid;
b827df58
AK		 350 uint32_t ret = 0;
351 uint32_t cpuid_1_edx;
8c723b79 352 bool found = false;
b827df58 353
dd87f8a6 354 cpuid = get_supported_cpuid(s);
b827df58 355
4fb73f1d
EH		 356 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
357 if (entry) {
358 found = true;
359 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 360 }
361
7b46e5ce
EH		 362 /* Fixups for the data returned by KVM, below */
363
c2acb022
EH		 364 if (function == 1 && reg == R_EDX) {
365 /* KVM before 2.6.30 misreports the following features */
366 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 367 } else if (function == 1 && reg == R_ECX) {
368 /* We can set the hypervisor flag, even if KVM does not return it on
369 * GET_SUPPORTED_CPUID
370 */
371 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 372 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
373 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
374 * and the irqchip is in the kernel.
375 */
376 if (kvm_irqchip_in_kernel() &&
377 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
378 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
379 }
41e5e76d
EH		 380
381 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
382 * without the in-kernel irqchip
383 */
384 if (!kvm_irqchip_in_kernel()) {
385 ret &= ~CPUID_EXT_X2APIC;
b827df58 386 }
2266d443
MT		 387
388 if (enable_cpu_pm) {
389 int disable_exits = kvm_check_extension(s,
390 KVM_CAP_X86_DISABLE_EXITS);
391
392 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
393 ret |= CPUID_EXT_MONITOR;
394 }
395 }
28b8e4d0
JK		 396 } else if (function == 6 && reg == R_EAX) {
397 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 398 } else if (function == 7 && index == 0 && reg == R_EBX) {
399 if (host_tsx_blacklisted()) {
400 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
401 }
485b1d25
EH		 402 } else if (function == 7 && index == 0 && reg == R_EDX) {
403 /*
404 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
405 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
406 * returned by KVM_GET_MSR_INDEX_LIST.
407 */
408 if (!has_msr_arch_capabs) {
409 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
410 }
f98bbd83
BM		 411 } else if (function == 0x80000001 && reg == R_ECX) {
412 /*
413 * It's safe to enable TOPOEXT even if it's not returned by
414 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
415 * us to keep CPU models including TOPOEXT runnable on older kernels.
416 */
417 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 418 } else if (function == 0x80000001 && reg == R_EDX) {
419 /* On Intel, kvm returns cpuid according to the Intel spec,
420 * so add missing bits according to the AMD spec:
421 */
422 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
423 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 424 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
425 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
426 * be enabled without the in-kernel irqchip
427 */
428 if (!kvm_irqchip_in_kernel()) {
429 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
430 }
be777326 431 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 432 ret |= 1U << KVM_HINTS_REALTIME;
be777326 433 found = 1;
b827df58
AK		 434 }
435
0c31b744 436 /* fallback for older kernels */
8c723b79 437 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 438 ret = get_para_features(s);
b9bec74b 439 }
0c31b744
GC		 440
441 return ret;
bb0300dc 442}
bb0300dc 443
f57bceb6
RH		 444uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
445{
446 struct {
447 struct kvm_msrs info;
448 struct kvm_msr_entry entries[1];
449 } msr_data;
450 uint32_t ret;
451
452 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
453 return 0;
454 }
455
456 /* Check if requested MSR is supported feature MSR */
457 int i;
458 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
459 if (kvm_feature_msrs->indices[i] == index) {
460 break;
461 }
462 if (i == kvm_feature_msrs->nmsrs) {
463 return 0; /* if the feature MSR is not supported, simply return 0 */
464 }
465
466 msr_data.info.nmsrs = 1;
467 msr_data.entries[0].index = index;
468
469 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
470 if (ret != 1) {
471 error_report("KVM get MSR (index=0x%x) feature failed, %s",
472 index, strerror(-ret));
473 exit(1);
474 }
475
476 return msr_data.entries[0].data;
477}
478
479
3c85e74f
HY		 480typedef struct HWPoisonPage {
481 ram_addr_t ram_addr;
482 QLIST_ENTRY(HWPoisonPage) list;
483} HWPoisonPage;
484
485static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
486 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
487
488static void kvm_unpoison_all(void *param)
489{
490 HWPoisonPage *page, *next_page;
491
492 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
493 QLIST_REMOVE(page, list);
494 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 495 g_free(page);
3c85e74f
HY		 496 }
497}
498
3c85e74f
HY		 499static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
500{
501 HWPoisonPage *page;
502
503 QLIST_FOREACH(page, &hwpoison_page_list, list) {
504 if (page->ram_addr == ram_addr) {
505 return;
506 }
507 }
ab3ad07f 508 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 509 page->ram_addr = ram_addr;
510 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
511}
512
e7701825
MT		 513static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
514 int *max_banks)
515{
516 int r;
517
14a09518 518 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 519 if (r > 0) {
520 *max_banks = r;
521 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
522 }
523 return -ENOSYS;
524}
525
bee615d4 526static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 527{
87f8b626 528 CPUState *cs = CPU(cpu);
bee615d4 529 CPUX86State *env = &cpu->env;
c34d440a
JK		 530 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
531 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
532 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 533 int flags = 0;
e7701825 534
c34d440a
JK		 535 if (code == BUS_MCEERR_AR) {
536 status |= MCI_STATUS_AR | 0x134;
537 mcg_status |= MCG_STATUS_EIPV;
538 } else {
539 status |= 0xc0;
540 mcg_status |= MCG_STATUS_RIPV;
419fb20a 541 }
87f8b626
AR		 542
543 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
544 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
545 * guest kernel back into env->mcg_ext_ctl.
546 */
547 cpu_synchronize_state(cs);
548 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
549 mcg_status |= MCG_STATUS_LMCE;
550 flags = 0;
551 }
552
8c5cf3b6 553 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 554 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 555}
419fb20a
JK		 556
557static void hardware_memory_error(void)
558{
559 fprintf(stderr, "Hardware memory error!\n");
560 exit(1);
561}
562
2ae41db2 563void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 564{
20d695a9
AF		 565 X86CPU *cpu = X86_CPU(c);
566 CPUX86State *env = &cpu->env;
419fb20a 567 ram_addr_t ram_addr;
a8170e5e 568 hwaddr paddr;
419fb20a 569
4d39892c
PB		 570 /* If we get an action required MCE, it has been injected by KVM
571 * while the VM was running. An action optional MCE instead should
572 * be coming from the main thread, which qemu_init_sigbus identifies
573 * as the "early kill" thread.
574 */
a16fc07e 575 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 576
20e0ff59 577 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 578 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 579 if (ram_addr != RAM_ADDR_INVALID &&
580 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
581 kvm_hwpoison_page_add(ram_addr);
582 kvm_mce_inject(cpu, paddr, code);
2ae41db2 583 return;
419fb20a 584 }
20e0ff59
PB		 585
586 fprintf(stderr, "Hardware memory error for memory used by "
587 "QEMU itself instead of guest system!\n");
419fb20a 588 }
20e0ff59
PB		 589
590 if (code == BUS_MCEERR_AR) {
591 hardware_memory_error();
592 }
593
594 /* Hope we are lucky for AO MCE */
419fb20a
JK		 595}
596
fd13f23b
LA		 597static void kvm_reset_exception(CPUX86State *env)
598{
599 env->exception_nr = -1;
600 env->exception_pending = 0;
601 env->exception_injected = 0;
602 env->exception_has_payload = false;
603 env->exception_payload = 0;
604}
605
606static void kvm_queue_exception(CPUX86State *env,
607 int32_t exception_nr,
608 uint8_t exception_has_payload,
609 uint64_t exception_payload)
610{
611 assert(env->exception_nr == -1);
612 assert(!env->exception_pending);
613 assert(!env->exception_injected);
614 assert(!env->exception_has_payload);
615
616 env->exception_nr = exception_nr;
617
618 if (has_exception_payload) {
619 env->exception_pending = 1;
620
621 env->exception_has_payload = exception_has_payload;
622 env->exception_payload = exception_payload;
623 } else {
624 env->exception_injected = 1;
625
626 if (exception_nr == EXCP01_DB) {
627 assert(exception_has_payload);
628 env->dr[6] = exception_payload;
629 } else if (exception_nr == EXCP0E_PAGE) {
630 assert(exception_has_payload);
631 env->cr[2] = exception_payload;
632 } else {
633 assert(!exception_has_payload);
634 }
635 }
636}
637
1bc22652 638static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 639{
1bc22652
AF		 640 CPUX86State *env = &cpu->env;
641
fd13f23b 642 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 643 unsigned int bank, bank_num = env->mcg_cap & 0xff;
644 struct kvm_x86_mce mce;
645
fd13f23b 646 kvm_reset_exception(env);
ab443475
JK		 647
648 /*
649 * There must be at least one bank in use if an MCE is pending.
650 * Find it and use its values for the event injection.
651 */
652 for (bank = 0; bank < bank_num; bank++) {
653 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
654 break;
655 }
656 }
657 assert(bank < bank_num);
658
659 mce.bank = bank;
660 mce.status = env->mce_banks[bank * 4 + 1];
661 mce.mcg_status = env->mcg_status;
662 mce.addr = env->mce_banks[bank * 4 + 2];
663 mce.misc = env->mce_banks[bank * 4 + 3];
664
1bc22652 665 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 666 }
ab443475
JK		 667 return 0;
668}
669
1dfb4dd9 670static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 671{
317ac620 672 CPUX86State *env = opaque;
b8cc45d6
GC		 673
674 if (running) {
675 env->tsc_valid = false;
676 }
677}
678
83b17af5 679unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 680{
83b17af5 681 X86CPU *cpu = X86_CPU(cs);
7e72a45c 682 return cpu->apic_id;
b164e48e
EH		 683}
684
92067bf4
IM		 685#ifndef KVM_CPUID_SIGNATURE_NEXT
686#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
687#endif
688
92067bf4
IM		 689static bool hyperv_enabled(X86CPU *cpu)
690{
7bc3d711
PB		 691 CPUState *cs = CPU(cpu);
692 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c 693 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
e48ddcc6 694 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 695}
696
5031283d
HZ		 697static int kvm_arch_set_tsc_khz(CPUState *cs)
698{
699 X86CPU *cpu = X86_CPU(cs);
700 CPUX86State *env = &cpu->env;
701 int r;
702
703 if (!env->tsc_khz) {
704 return 0;
705 }
706
707 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
708 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
709 -ENOTSUP;
710 if (r < 0) {
711 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
712 * TSC frequency doesn't match the one we want.
713 */
714 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
715 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
716 -ENOTSUP;
717 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 718 warn_report("TSC frequency mismatch between "
719 "VM (%" PRId64 " kHz) and host (%d kHz), "
720 "and TSC scaling unavailable",
721 env->tsc_khz, cur_freq);
5031283d
HZ		 722 return r;
723 }
724 }
725
726 return 0;
727}
728
4bb95b82
LP		 729static bool tsc_is_stable_and_known(CPUX86State *env)
730{
731 if (!env->tsc_khz) {
732 return false;
733 }
734 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
735 || env->user_tsc_khz;
736}
737
6760bd20
VK		 738static struct {
739 const char *desc;
740 struct {
741 uint32_t fw;
742 uint32_t bits;
743 } flags[2];
c6861930 744 uint64_t dependencies;
6760bd20
VK		 745} kvm_hyperv_properties[] = {
746 [HYPERV_FEAT_RELAXED] = {
747 .desc = "relaxed timing (hv-relaxed)",
748 .flags = {
749 {.fw = FEAT_HYPERV_EAX,
750 .bits = HV_HYPERCALL_AVAILABLE},
751 {.fw = FEAT_HV_RECOMM_EAX,
752 .bits = HV_RELAXED_TIMING_RECOMMENDED}
753 }
754 },
755 [HYPERV_FEAT_VAPIC] = {
756 .desc = "virtual APIC (hv-vapic)",
757 .flags = {
758 {.fw = FEAT_HYPERV_EAX,
759 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
760 {.fw = FEAT_HV_RECOMM_EAX,
761 .bits = HV_APIC_ACCESS_RECOMMENDED}
762 }
763 },
764 [HYPERV_FEAT_TIME] = {
765 .desc = "clocksources (hv-time)",
766 .flags = {
767 {.fw = FEAT_HYPERV_EAX,
768 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
769 HV_REFERENCE_TSC_AVAILABLE}
770 }
771 },
772 [HYPERV_FEAT_CRASH] = {
773 .desc = "crash MSRs (hv-crash)",
774 .flags = {
775 {.fw = FEAT_HYPERV_EDX,
776 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
777 }
778 },
779 [HYPERV_FEAT_RESET] = {
780 .desc = "reset MSR (hv-reset)",
781 .flags = {
782 {.fw = FEAT_HYPERV_EAX,
783 .bits = HV_RESET_AVAILABLE}
784 }
785 },
786 [HYPERV_FEAT_VPINDEX] = {
787 .desc = "VP_INDEX MSR (hv-vpindex)",
788 .flags = {
789 {.fw = FEAT_HYPERV_EAX,
790 .bits = HV_VP_INDEX_AVAILABLE}
791 }
792 },
793 [HYPERV_FEAT_RUNTIME] = {
794 .desc = "VP_RUNTIME MSR (hv-runtime)",
795 .flags = {
796 {.fw = FEAT_HYPERV_EAX,
797 .bits = HV_VP_RUNTIME_AVAILABLE}
798 }
799 },
800 [HYPERV_FEAT_SYNIC] = {
801 .desc = "synthetic interrupt controller (hv-synic)",
802 .flags = {
803 {.fw = FEAT_HYPERV_EAX,
804 .bits = HV_SYNIC_AVAILABLE}
805 }
806 },
807 [HYPERV_FEAT_STIMER] = {
808 .desc = "synthetic timers (hv-stimer)",
809 .flags = {
810 {.fw = FEAT_HYPERV_EAX,
811 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 812 },
813 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 814 },
815 [HYPERV_FEAT_FREQUENCIES] = {
816 .desc = "frequency MSRs (hv-frequencies)",
817 .flags = {
818 {.fw = FEAT_HYPERV_EAX,
819 .bits = HV_ACCESS_FREQUENCY_MSRS},
820 {.fw = FEAT_HYPERV_EDX,
821 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
822 }
823 },
824 [HYPERV_FEAT_REENLIGHTENMENT] = {
825 .desc = "reenlightenment MSRs (hv-reenlightenment)",
826 .flags = {
827 {.fw = FEAT_HYPERV_EAX,
828 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
829 }
830 },
831 [HYPERV_FEAT_TLBFLUSH] = {
832 .desc = "paravirtualized TLB flush (hv-tlbflush)",
833 .flags = {
834 {.fw = FEAT_HV_RECOMM_EAX,
835 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
836 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 837 },
838 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 839 },
840 [HYPERV_FEAT_EVMCS] = {
841 .desc = "enlightened VMCS (hv-evmcs)",
842 .flags = {
843 {.fw = FEAT_HV_RECOMM_EAX,
844 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 845 },
846 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 847 },
848 [HYPERV_FEAT_IPI] = {
849 .desc = "paravirtualized IPI (hv-ipi)",
850 .flags = {
851 {.fw = FEAT_HV_RECOMM_EAX,
852 .bits = HV_CLUSTER_IPI_RECOMMENDED |
853 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 854 },
855 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 856 },
128531d9
VK		 857 [HYPERV_FEAT_STIMER_DIRECT] = {
858 .desc = "direct mode synthetic timers (hv-stimer-direct)",
859 .flags = {
860 {.fw = FEAT_HYPERV_EDX,
861 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
862 },
863 .dependencies = BIT(HYPERV_FEAT_STIMER)
864 },
6760bd20
VK		 865};
866
867static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
868{
869 struct kvm_cpuid2 *cpuid;
870 int r, size;
871
872 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
873 cpuid = g_malloc0(size);
874 cpuid->nent = max;
875
876 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
877 if (r == 0 && cpuid->nent >= max) {
878 r = -E2BIG;
879 }
880 if (r < 0) {
881 if (r == -E2BIG) {
882 g_free(cpuid);
883 return NULL;
884 } else {
885 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
886 strerror(-r));
887 exit(1);
888 }
889 }
890 return cpuid;
891}
892
893/*
894 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
895 * for all entries.
896 */
897static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
898{
899 struct kvm_cpuid2 *cpuid;
900 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
901
902 /*
903 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
904 * -E2BIG, however, it doesn't report back the right size. Keep increasing
905 * it and re-trying until we succeed.
906 */
907 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
908 max++;
909 }
910 return cpuid;
911}
912
913/*
914 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
915 * leaves from KVM_CAP_HYPERV* and present MSRs data.
916 */
917static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 918{
919 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 920 struct kvm_cpuid2 *cpuid;
921 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
922
923 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
924 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
925 cpuid->nent = 2;
926
927 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
928 entry_feat = &cpuid->entries[0];
929 entry_feat->function = HV_CPUID_FEATURES;
930
931 entry_recomm = &cpuid->entries[1];
932 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
933 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
934
935 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
936 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
937 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
938 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
939 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
940 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
941 }
c35bd19a 942
6760bd20
VK		 943 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
944 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
945 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 946 }
6760bd20
VK		 947
948 if (has_msr_hv_frequencies) {
949 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
950 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 951 }
6760bd20
VK		 952
953 if (has_msr_hv_crash) {
954 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 955 }
6760bd20
VK		 956
957 if (has_msr_hv_reenlightenment) {
958 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 959 }
6760bd20
VK		 960
961 if (has_msr_hv_reset) {
962 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 963 }
6760bd20
VK		 964
965 if (has_msr_hv_vpindex) {
966 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 967 }
6760bd20
VK		 968
969 if (has_msr_hv_runtime) {
970 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 971 }
6760bd20
VK		 972
973 if (has_msr_hv_synic) {
974 unsigned int cap = cpu->hyperv_synic_kvm_only ?
975 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
976
977 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
978 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 979 }
c35bd19a 980 }
6760bd20
VK		 981
982 if (has_msr_hv_stimer) {
983 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 984 }
9b4cf107 985
6760bd20
VK		 986 if (kvm_check_extension(cs->kvm_state,
987 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
988 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
989 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
990 }
c35bd19a 991
6760bd20
VK		 992 if (kvm_check_extension(cs->kvm_state,
993 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
994 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 995 }
6760bd20
VK		 996
997 if (kvm_check_extension(cs->kvm_state,
998 KVM_CAP_HYPERV_SEND_IPI) > 0) {
999 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1000 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 1001 }
6760bd20
VK		 1002
1003 return cpuid;
1004}
1005
1006static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
1007{
1008 struct kvm_cpuid_entry2 *entry;
1009 uint32_t func;
1010 int reg;
1011
1012 switch (fw) {
1013 case FEAT_HYPERV_EAX:
1014 reg = R_EAX;
1015 func = HV_CPUID_FEATURES;
1016 break;
1017 case FEAT_HYPERV_EDX:
1018 reg = R_EDX;
1019 func = HV_CPUID_FEATURES;
1020 break;
1021 case FEAT_HV_RECOMM_EAX:
1022 reg = R_EAX;
1023 func = HV_CPUID_ENLIGHTMENT_INFO;
1024 break;
1025 default:
1026 return -EINVAL;
a2b107db 1027 }
6760bd20
VK		 1028
1029 entry = cpuid_find_entry(cpuid, func, 0);
1030 if (!entry) {
1031 return -ENOENT;
a2b107db 1032 }
6760bd20
VK		 1033
1034 switch (reg) {
1035 case R_EAX:
1036 *r = entry->eax;
1037 break;
1038 case R_EDX:
1039 *r = entry->edx;
1040 break;
1041 default:
1042 return -EINVAL;
a2b107db 1043 }
6760bd20
VK		 1044
1045 return 0;
1046}
1047
1048static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
1049 int feature)
1050{
1051 X86CPU *cpu = X86_CPU(cs);
1052 CPUX86State *env = &cpu->env;
e48ddcc6 1053 uint32_t r, fw, bits;
c6861930 1054 uint64_t deps;
9dc83cd9 1055 int i, dep_feat;
6760bd20 1056
e48ddcc6 1057 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1058 return 0;
1059 }
1060
c6861930 1061 deps = kvm_hyperv_properties[feature].dependencies;
9dc83cd9
HR		 1062 while (deps) {
1063 dep_feat = ctz64(deps);
c6861930
VK		 1064 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1065 fprintf(stderr,
1066 "Hyper-V %s requires Hyper-V %s\n",
1067 kvm_hyperv_properties[feature].desc,
1068 kvm_hyperv_properties[dep_feat].desc);
1069 return 1;
1070 }
9dc83cd9 1071 deps &= ~(1ull << dep_feat);
c6861930
VK		 1072 }
1073
6760bd20
VK		 1074 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1075 fw = kvm_hyperv_properties[feature].flags[i].fw;
1076 bits = kvm_hyperv_properties[feature].flags[i].bits;
1077
1078 if (!fw) {
1079 continue;
a2b107db 1080 }
6760bd20
VK		 1081
1082 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
e48ddcc6
VK		 1083 if (hyperv_feat_enabled(cpu, feature)) {
1084 fprintf(stderr,
1085 "Hyper-V %s is not supported by kernel\n",
1086 kvm_hyperv_properties[feature].desc);
1087 return 1;
1088 } else {
1089 return 0;
1090 }
6760bd20
VK		 1091 }
1092
1093 env->features[fw] |= bits;
a2b107db 1094 }
6760bd20 1095
e48ddcc6
VK		 1096 if (cpu->hyperv_passthrough) {
1097 cpu->hyperv_features |= BIT(feature);
1098 }
1099
6760bd20
VK		 1100 return 0;
1101}
1102
2344d22e
VK		 1103/*
1104 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1105 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1106 * extentions are enabled.
1107 */
1108static int hyperv_handle_properties(CPUState *cs,
1109 struct kvm_cpuid_entry2 *cpuid_ent)
6760bd20
VK		 1110{
1111 X86CPU *cpu = X86_CPU(cs);
1112 CPUX86State *env = &cpu->env;
1113 struct kvm_cpuid2 *cpuid;
2344d22e
VK		 1114 struct kvm_cpuid_entry2 *c;
1115 uint32_t signature[3];
1116 uint32_t cpuid_i = 0;
e48ddcc6 1117 int r;
6760bd20 1118
2344d22e
VK		 1119 if (!hyperv_enabled(cpu))
1120 return 0;
1121
e48ddcc6
VK		 1122 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1123 cpu->hyperv_passthrough) {
a2b107db
VK		 1124 uint16_t evmcs_version;
1125
e48ddcc6
VK		 1126 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1127 (uintptr_t)&evmcs_version);
1128
1129 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1130 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1131 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1132 return -ENOSYS;
1133 }
e48ddcc6
VK		 1134
1135 if (!r) {
1136 env->features[FEAT_HV_RECOMM_EAX] |=
1137 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1138 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1139 }
a2b107db
VK		 1140 }
1141
6760bd20
VK		 1142 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1143 cpuid = get_supported_hv_cpuid(cs);
1144 } else {
1145 cpuid = get_supported_hv_cpuid_legacy(cs);
1146 }
1147
e48ddcc6
VK		 1148 if (cpu->hyperv_passthrough) {
1149 memcpy(cpuid_ent, &cpuid->entries[0],
1150 cpuid->nent * sizeof(cpuid->entries[0]));
1151
1152 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1153 if (c) {
1154 env->features[FEAT_HYPERV_EAX] = c->eax;
1155 env->features[FEAT_HYPERV_EBX] = c->ebx;
1156 env->features[FEAT_HYPERV_EDX] = c->eax;
1157 }
1158 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1159 if (c) {
1160 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1161
1162 /* hv-spinlocks may have been overriden */
1163 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1164 c->ebx = cpu->hyperv_spinlock_attempts;
1165 }
1166 }
1167 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1168 if (c) {
1169 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1170 }
1171 }
1172
6760bd20 1173 /* Features */
e48ddcc6 1174 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
6760bd20
VK		 1175 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1176 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1177 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1178 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1179 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1180 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1181 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1182 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1183 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1184 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1185 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1186 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1187 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
128531d9 1188 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
6760bd20 1189
c6861930 1190 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1191 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1192 !cpu->hyperv_synic_kvm_only &&
1193 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1194 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1195 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1196 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1197 r |= 1;
1198 }
1199
1200 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1201 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1202
2344d22e
VK		 1203 if (r) {
1204 r = -ENOSYS;
1205 goto free;
1206 }
1207
e48ddcc6
VK		 1208 if (cpu->hyperv_passthrough) {
1209 /* We already copied all feature words from KVM as is */
1210 r = cpuid->nent;
1211 goto free;
1212 }
1213
2344d22e
VK		 1214 c = &cpuid_ent[cpuid_i++];
1215 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1216 if (!cpu->hyperv_vendor_id) {
1217 memcpy(signature, "Microsoft Hv", 12);
1218 } else {
1219 size_t len = strlen(cpu->hyperv_vendor_id);
1220
1221 if (len > 12) {
1222 error_report("hv-vendor-id truncated to 12 characters");
1223 len = 12;
1224 }
1225 memset(signature, 0, 12);
1226 memcpy(signature, cpu->hyperv_vendor_id, len);
1227 }
1228 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1229 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1230 c->ebx = signature[0];
1231 c->ecx = signature[1];
1232 c->edx = signature[2];
1233
1234 c = &cpuid_ent[cpuid_i++];
1235 c->function = HV_CPUID_INTERFACE;
1236 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1237 c->eax = signature[0];
1238 c->ebx = 0;
1239 c->ecx = 0;
1240 c->edx = 0;
1241
1242 c = &cpuid_ent[cpuid_i++];
1243 c->function = HV_CPUID_VERSION;
1244 c->eax = 0x00001bbc;
1245 c->ebx = 0x00060001;
1246
1247 c = &cpuid_ent[cpuid_i++];
1248 c->function = HV_CPUID_FEATURES;
1249 c->eax = env->features[FEAT_HYPERV_EAX];
1250 c->ebx = env->features[FEAT_HYPERV_EBX];
1251 c->edx = env->features[FEAT_HYPERV_EDX];
1252
1253 c = &cpuid_ent[cpuid_i++];
1254 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1255 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1256 c->ebx = cpu->hyperv_spinlock_attempts;
1257
1258 c = &cpuid_ent[cpuid_i++];
1259 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1260 c->eax = cpu->hv_max_vps;
1261 c->ebx = 0x40;
1262
1263 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1264 __u32 function;
1265
1266 /* Create zeroed 0x40000006..0x40000009 leaves */
1267 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1268 function < HV_CPUID_NESTED_FEATURES; function++) {
1269 c = &cpuid_ent[cpuid_i++];
1270 c->function = function;
1271 }
1272
1273 c = &cpuid_ent[cpuid_i++];
1274 c->function = HV_CPUID_NESTED_FEATURES;
1275 c->eax = env->features[FEAT_HV_NESTED_EAX];
1276 }
1277 r = cpuid_i;
1278
1279free:
6760bd20
VK		 1280 g_free(cpuid);
1281
2344d22e 1282 return r;
c35bd19a
EY		 1283}
1284
e48ddcc6
VK		 1285static Error *hv_passthrough_mig_blocker;
1286
e9688fab
RK		 1287static int hyperv_init_vcpu(X86CPU *cpu)
1288{
729ce7e1 1289 CPUState *cs = CPU(cpu);
e48ddcc6 1290 Error *local_err = NULL;
729ce7e1
RK		 1291 int ret;
1292
e48ddcc6
VK		 1293 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1294 error_setg(&hv_passthrough_mig_blocker,
1295 "'hv-passthrough' CPU flag prevents migration, use explicit"
1296 " set of hv-* flags instead");
1297 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1298 if (local_err) {
1299 error_report_err(local_err);
1300 error_free(hv_passthrough_mig_blocker);
1301 return ret;
1302 }
1303 }
1304
2d384d7c 1305 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1306 /*
1307 * the kernel doesn't support setting vp_index; assert that its value
1308 * is in sync
1309 */
e9688fab
RK		 1310 struct {
1311 struct kvm_msrs info;
1312 struct kvm_msr_entry entries[1];
1313 } msr_data = {
1314 .info.nmsrs = 1,
1315 .entries[0].index = HV_X64_MSR_VP_INDEX,
1316 };
1317
729ce7e1 1318 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1319 if (ret < 0) {
1320 return ret;
1321 }
1322 assert(ret == 1);
1323
701189e3 1324 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1325 error_report("kernel's vp_index != QEMU's vp_index");
1326 return -ENXIO;
1327 }
1328 }
1329
2d384d7c 1330 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1331 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1332 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1333 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1334 if (ret < 0) {
1335 error_report("failed to turn on HyperV SynIC in KVM: %s",
1336 strerror(-ret));
1337 return ret;
1338 }
606c34bf 1339
9b4cf107
RK		 1340 if (!cpu->hyperv_synic_kvm_only) {
1341 ret = hyperv_x86_synic_add(cpu);
1342 if (ret < 0) {
1343 error_report("failed to create HyperV SynIC: %s",
1344 strerror(-ret));
1345 return ret;
1346 }
606c34bf 1347 }
729ce7e1
RK		 1348 }
1349
e9688fab
RK		 1350 return 0;
1351}
1352
68bfd0ad
MT		 1353static Error *invtsc_mig_blocker;
1354
f8bb0565 1355#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1356
20d695a9 1357int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1358{
1359 struct {
486bd5a2 1360 struct kvm_cpuid2 cpuid;
f8bb0565 1361 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1362 } cpuid_data;
1363 /*
1364 * The kernel defines these structs with padding fields so there
1365 * should be no extra padding in our cpuid_data struct.
1366 */
1367 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1368 sizeof(struct kvm_cpuid2) +
1369 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1370
20d695a9
AF		 1371 X86CPU *cpu = X86_CPU(cs);
1372 CPUX86State *env = &cpu->env;
486bd5a2 1373 uint32_t limit, i, j, cpuid_i;
a33609ca 1374 uint32_t unused;
bb0300dc 1375 struct kvm_cpuid_entry2 *c;
bb0300dc 1376 uint32_t signature[3];
234cc647 1377 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1378 int max_nested_state_len;
e7429073 1379 int r;
fe44dc91 1380 Error *local_err = NULL;
05330448 1381
ef4cbe14
SW		 1382 memset(&cpuid_data, 0, sizeof(cpuid_data));
1383
05330448
AL		 1384 cpuid_i = 0;
1385
ddb98b5a
LP		 1386 r = kvm_arch_set_tsc_khz(cs);
1387 if (r < 0) {
6b2341ee 1388 return r;
ddb98b5a
LP		 1389 }
1390
1391 /* vcpu's TSC frequency is either specified by user, or following
1392 * the value used by KVM if the former is not present. In the
1393 * latter case, we query it from KVM and record in env->tsc_khz,
1394 * so that vcpu's TSC frequency can be migrated later via this field.
1395 */
1396 if (!env->tsc_khz) {
1397 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1398 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1399 -ENOTSUP;
1400 if (r > 0) {
1401 env->tsc_khz = r;
1402 }
1403 }
1404
bb0300dc 1405 /* Paravirtualization CPUIDs */
2344d22e
VK		 1406 r = hyperv_handle_properties(cs, cpuid_data.entries);
1407 if (r < 0) {
1408 return r;
1409 } else if (r > 0) {
1410 cpuid_i = r;
234cc647 1411 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1412 has_msr_hv_hypercall = true;
eab70139
VR		 1413 }
1414
f522d2ac
AW		 1415 if (cpu->expose_kvm) {
1416 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1417 c = &cpuid_data.entries[cpuid_i++];
1418 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1419 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1420 c->ebx = signature[0];
1421 c->ecx = signature[1];
1422 c->edx = signature[2];
234cc647 1423
f522d2ac
AW		 1424 c = &cpuid_data.entries[cpuid_i++];
1425 c->function = KVM_CPUID_FEATURES | kvm_base;
1426 c->eax = env->features[FEAT_KVM];
be777326 1427 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1428 }
917367aa 1429
a33609ca 1430 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1431
1432 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1433 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1434 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1435 abort();
1436 }
bb0300dc 1437 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1438
1439 switch (i) {
a36b1029
AL		 1440 case 2: {
1441 /* Keep reading function 2 till all the input is received */
1442 int times;
1443
a36b1029 1444 c->function = i;
a33609ca
AL		 1445 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1446 KVM_CPUID_FLAG_STATE_READ_NEXT;
1447 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1448 times = c->eax & 0xff;
a36b1029
AL		 1449
1450 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1451 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1452 fprintf(stderr, "cpuid_data is full, no space for "
1453 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1454 abort();
1455 }
a33609ca 1456 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1457 c->function = i;
a33609ca
AL		 1458 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1459 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1460 }
1461 break;
1462 }
a94e1428
LX		 1463 case 0x1f:
1464 if (env->nr_dies < 2) {
1465 break;
1466 }
486bd5a2
AL		 1467 case 4:
1468 case 0xb:
1469 case 0xd:
1470 for (j = 0; ; j++) {
31e8c696
AP		 1471 if (i == 0xd && j == 64) {
1472 break;
1473 }
a94e1428
LX		 1474
1475 if (i == 0x1f && j == 64) {
1476 break;
1477 }
1478
486bd5a2
AL		 1479 c->function = i;
1480 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1481 c->index = j;
a33609ca 1482 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1483
b9bec74b 1484 if (i == 4 && c->eax == 0) {
486bd5a2 1485 break;
b9bec74b
JK		 1486 }
1487 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1488 break;
b9bec74b 1489 }
a94e1428
LX		 1490 if (i == 0x1f && !(c->ecx & 0xff00)) {
1491 break;
1492 }
b9bec74b 1493 if (i == 0xd && c->eax == 0) {
31e8c696 1494 continue;
b9bec74b 1495 }
f8bb0565
IM		 1496 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1497 fprintf(stderr, "cpuid_data is full, no space for "
1498 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1499 abort();
1500 }
a33609ca 1501 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1502 }
1503 break;
80db491d 1504 case 0x7:
e37a5c7f
CP		 1505 case 0x14: {
1506 uint32_t times;
1507
1508 c->function = i;
1509 c->index = 0;
1510 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1511 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1512 times = c->eax;
1513
1514 for (j = 1; j <= times; ++j) {
1515 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1516 fprintf(stderr, "cpuid_data is full, no space for "
80db491d 1517 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
e37a5c7f
CP		 1518 abort();
1519 }
1520 c = &cpuid_data.entries[cpuid_i++];
1521 c->function = i;
1522 c->index = j;
1523 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1524 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1525 }
1526 break;
1527 }
486bd5a2 1528 default:
486bd5a2 1529 c->function = i;
a33609ca
AL		 1530 c->flags = 0;
1531 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1532 break;
1533 }
05330448 1534 }
0d894367
PB		 1535
1536 if (limit >= 0x0a) {
0b368a10 1537 uint32_t eax, edx;
0d894367 1538
0b368a10
JD		 1539 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1540
1541 has_architectural_pmu_version = eax & 0xff;
1542 if (has_architectural_pmu_version > 0) {
1543 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1544
1545 /* Shouldn't be more than 32, since that's the number of bits
1546 * available in EBX to tell us _which_ counters are available.
1547 * Play it safe.
1548 */
0b368a10
JD		 1549 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1550 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1551 }
1552
1553 if (has_architectural_pmu_version > 1) {
1554 num_architectural_pmu_fixed_counters = edx & 0x1f;
1555
1556 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1557 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1558 }
0d894367
PB		 1559 }
1560 }
1561 }
1562
a33609ca 1563 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1564
1565 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1566 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1567 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1568 abort();
1569 }
bb0300dc 1570 c = &cpuid_data.entries[cpuid_i++];
05330448 1571
8f4202fb
BM		 1572 switch (i) {
1573 case 0x8000001d:
1574 /* Query for all AMD cache information leaves */
1575 for (j = 0; ; j++) {
1576 c->function = i;
1577 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1578 c->index = j;
1579 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1580
1581 if (c->eax == 0) {
1582 break;
1583 }
1584 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1585 fprintf(stderr, "cpuid_data is full, no space for "
1586 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1587 abort();
1588 }
1589 c = &cpuid_data.entries[cpuid_i++];
1590 }
1591 break;
1592 default:
1593 c->function = i;
1594 c->flags = 0;
1595 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1596 break;
1597 }
05330448
AL		 1598 }
1599
b3baa152
BW		 1600 /* Call Centaur's CPUID instructions they are supported. */
1601 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1602 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1603
1604 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1605 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1606 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1607 abort();
1608 }
b3baa152
BW		 1609 c = &cpuid_data.entries[cpuid_i++];
1610
1611 c->function = i;
1612 c->flags = 0;
1613 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1614 }
1615 }
1616
05330448
AL		 1617 cpuid_data.cpuid.nent = cpuid_i;
1618
e7701825 1619 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1620 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1621 (CPUID_MCE | CPUID_MCA)
a60f24b5 1622 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1623 uint64_t mcg_cap, unsupported_caps;
e7701825 1624 int banks;
32a42024 1625 int ret;
e7701825 1626
a60f24b5 1627 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1628 if (ret < 0) {
1629 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1630 return ret;
e7701825 1631 }
75d49497 1632
2590f15b 1633 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1634 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1635 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1636 return -ENOTSUP;
75d49497 1637 }
49b69cbf 1638
5120901a
EH		 1639 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1640 if (unsupported_caps) {
87f8b626
AR		 1641 if (unsupported_caps & MCG_LMCE_P) {
1642 error_report("kvm: LMCE not supported");
1643 return -ENOTSUP;
1644 }
3dc6f869
AF		 1645 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1646 unsupported_caps);
5120901a
EH		 1647 }
1648
2590f15b
EH		 1649 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1650 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1651 if (ret < 0) {
1652 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1653 return ret;
1654 }
e7701825 1655 }
e7701825 1656
b8cc45d6
GC		 1657 qemu_add_vm_change_state_handler(cpu_update_state, env);
1658
df67696e
LJ		 1659 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1660 if (c) {
1661 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1662 !!(c->ecx & CPUID_EXT_SMX);
1663 }
1664
87f8b626
AR		 1665 if (env->mcg_cap & MCG_LMCE_P) {
1666 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1667 }
1668
d99569d9
EH		 1669 if (!env->user_tsc_khz) {
1670 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1671 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1672 error_setg(&invtsc_mig_blocker,
1673 "State blocked by non-migratable CPU device"
1674 " (invtsc flag)");
fe44dc91
AA		 1675 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1676 if (local_err) {
1677 error_report_err(local_err);
1678 error_free(invtsc_mig_blocker);
79a197ab 1679 return r;
fe44dc91 1680 }
d99569d9 1681 }
68bfd0ad
MT		 1682 }
1683
9954a158
PDJ		 1684 if (cpu->vmware_cpuid_freq
1685 /* Guests depend on 0x40000000 to detect this feature, so only expose
1686 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1687 && cpu->expose_kvm
1688 && kvm_base == KVM_CPUID_SIGNATURE
1689 /* TSC clock must be stable and known for this feature. */
4bb95b82 1690 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1691
1692 c = &cpuid_data.entries[cpuid_i++];
1693 c->function = KVM_CPUID_SIGNATURE | 0x10;
1694 c->eax = env->tsc_khz;
1695 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1696 * APIC_BUS_CYCLE_NS */
1697 c->ebx = 1000000;
1698 c->ecx = c->edx = 0;
1699
1700 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1701 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1702 }
1703
1704 cpuid_data.cpuid.nent = cpuid_i;
1705
1706 cpuid_data.cpuid.padding = 0;
1707 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1708 if (r) {
1709 goto fail;
1710 }
1711
28143b40 1712 if (has_xsave) {
5b8063c4 1713 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1f670a95 1714 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
fabacc0f 1715 }
ebbfef2f
LA		 1716
1717 max_nested_state_len = kvm_max_nested_state_length();
1718 if (max_nested_state_len > 0) {
1719 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
ebbfef2f 1720
1e44f3ab
PB		 1721 if (cpu_has_vmx(env)) {
1722 struct kvm_vmx_nested_state_hdr *vmx_hdr;
ebbfef2f 1723
1e44f3ab
PB		 1724 env->nested_state = g_malloc0(max_nested_state_len);
1725 env->nested_state->size = max_nested_state_len;
ebbfef2f 1726 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1e44f3ab
PB		 1727
1728 vmx_hdr = &env->nested_state->hdr.vmx;
ebbfef2f
LA		 1729 vmx_hdr->vmxon_pa = -1ull;
1730 vmx_hdr->vmcs12_pa = -1ull;
1731 }
1732 }
1733
d71b62a1 1734 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1735
273c515c
PB		 1736 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1737 has_msr_tsc_aux = false;
1738 }
d1ae67f6 1739
e9688fab
RK		 1740 r = hyperv_init_vcpu(cpu);
1741 if (r) {
1742 goto fail;
1743 }
1744
e7429073 1745 return 0;
fe44dc91
AA		 1746
1747 fail:
1748 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 1749
fe44dc91 1750 return r;
05330448
AL		 1751}
1752
b1115c99
LA		 1753int kvm_arch_destroy_vcpu(CPUState *cs)
1754{
1755 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 1756 CPUX86State *env = &cpu->env;
b1115c99
LA		 1757
1758 if (cpu->kvm_msr_buf) {
1759 g_free(cpu->kvm_msr_buf);
1760 cpu->kvm_msr_buf = NULL;
1761 }
1762
ebbfef2f
LA		 1763 if (env->nested_state) {
1764 g_free(env->nested_state);
1765 env->nested_state = NULL;
1766 }
1767
b1115c99
LA		 1768 return 0;
1769}
1770
50a2c6e5 1771void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1772{
20d695a9 1773 CPUX86State *env = &cpu->env;
dd673288 1774
1a5e9d2f 1775 env->xcr0 = 1;
ddced198 1776 if (kvm_irqchip_in_kernel()) {
dd673288 1777 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1778 KVM_MP_STATE_UNINITIALIZED;
1779 } else {
1780 env->mp_state = KVM_MP_STATE_RUNNABLE;
1781 }
689141dd 1782
2d384d7c 1783 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1784 int i;
1785 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1786 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1787 }
606c34bf
RK		 1788
1789 hyperv_x86_synic_reset(cpu);
689141dd 1790 }
d645e132
MT		 1791 /* enabled by default */
1792 env->poll_control_msr = 1;
caa5af0f
JK		 1793}
1794
e0723c45
PB		 1795void kvm_arch_do_init_vcpu(X86CPU *cpu)
1796{
1797 CPUX86State *env = &cpu->env;
1798
1799 /* APs get directly into wait-for-SIPI state. */
1800 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1801 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1802 }
1803}
1804
f57bceb6
RH		 1805static int kvm_get_supported_feature_msrs(KVMState *s)
1806{
1807 int ret = 0;
1808
1809 if (kvm_feature_msrs != NULL) {
1810 return 0;
1811 }
1812
1813 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1814 return 0;
1815 }
1816
1817 struct kvm_msr_list msr_list;
1818
1819 msr_list.nmsrs = 0;
1820 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1821 if (ret < 0 && ret != -E2BIG) {
1822 error_report("Fetch KVM feature MSR list failed: %s",
1823 strerror(-ret));
1824 return ret;
1825 }
1826
1827 assert(msr_list.nmsrs > 0);
1828 kvm_feature_msrs = (struct kvm_msr_list *) \
1829 g_malloc0(sizeof(msr_list) +
1830 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1831
1832 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1833 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1834
1835 if (ret < 0) {
1836 error_report("Fetch KVM feature MSR list failed: %s",
1837 strerror(-ret));
1838 g_free(kvm_feature_msrs);
1839 kvm_feature_msrs = NULL;
1840 return ret;
1841 }
1842
1843 return 0;
1844}
1845
c3a3a7d3 1846static int kvm_get_supported_msrs(KVMState *s)
05330448 1847{
c3a3a7d3 1848 int ret = 0;
de428cea 1849 struct kvm_msr_list msr_list, *kvm_msr_list;
05330448 1850
de428cea
LQ		 1851 /*
1852 * Obtain MSR list from KVM. These are the MSRs that we must
1853 * save/restore.
1854 */
1855 msr_list.nmsrs = 0;
1856 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1857 if (ret < 0 && ret != -E2BIG) {
1858 return ret;
1859 }
1860 /*
1861 * Old kernel modules had a bug and could write beyond the provided
1862 * memory. Allocate at least a safe amount of 1K.
1863 */
1864 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1865 msr_list.nmsrs *
1866 sizeof(msr_list.indices[0])));
05330448 1867
de428cea
LQ		 1868 kvm_msr_list->nmsrs = msr_list.nmsrs;
1869 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1870 if (ret >= 0) {
1871 int i;
05330448 1872
de428cea
LQ		 1873 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1874 switch (kvm_msr_list->indices[i]) {
1875 case MSR_STAR:
1876 has_msr_star = true;
1877 break;
1878 case MSR_VM_HSAVE_PA:
1879 has_msr_hsave_pa = true;
1880 break;
1881 case MSR_TSC_AUX:
1882 has_msr_tsc_aux = true;
1883 break;
1884 case MSR_TSC_ADJUST:
1885 has_msr_tsc_adjust = true;
1886 break;
1887 case MSR_IA32_TSCDEADLINE:
1888 has_msr_tsc_deadline = true;
1889 break;
1890 case MSR_IA32_SMBASE:
1891 has_msr_smbase = true;
1892 break;
1893 case MSR_SMI_COUNT:
1894 has_msr_smi_count = true;
1895 break;
1896 case MSR_IA32_MISC_ENABLE:
1897 has_msr_misc_enable = true;
1898 break;
1899 case MSR_IA32_BNDCFGS:
1900 has_msr_bndcfgs = true;
1901 break;
1902 case MSR_IA32_XSS:
1903 has_msr_xss = true;
1904 break;
1905 case HV_X64_MSR_CRASH_CTL:
1906 has_msr_hv_crash = true;
1907 break;
1908 case HV_X64_MSR_RESET:
1909 has_msr_hv_reset = true;
1910 break;
1911 case HV_X64_MSR_VP_INDEX:
1912 has_msr_hv_vpindex = true;
1913 break;
1914 case HV_X64_MSR_VP_RUNTIME:
1915 has_msr_hv_runtime = true;
1916 break;
1917 case HV_X64_MSR_SCONTROL:
1918 has_msr_hv_synic = true;
1919 break;
1920 case HV_X64_MSR_STIMER0_CONFIG:
1921 has_msr_hv_stimer = true;
1922 break;
1923 case HV_X64_MSR_TSC_FREQUENCY:
1924 has_msr_hv_frequencies = true;
1925 break;
1926 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1927 has_msr_hv_reenlightenment = true;
1928 break;
1929 case MSR_IA32_SPEC_CTRL:
1930 has_msr_spec_ctrl = true;
1931 break;
1932 case MSR_VIRT_SSBD:
1933 has_msr_virt_ssbd = true;
1934 break;
1935 case MSR_IA32_ARCH_CAPABILITIES:
1936 has_msr_arch_capabs = true;
1937 break;
1938 case MSR_IA32_CORE_CAPABILITY:
1939 has_msr_core_capabs = true;
1940 break;
05330448
AL		 1941 }
1942 }
05330448
AL		 1943 }
1944
de428cea
LQ		 1945 g_free(kvm_msr_list);
1946
c3a3a7d3 1947 return ret;
05330448
AL		 1948}
1949
6410848b
PB		 1950static Notifier smram_machine_done;
1951static KVMMemoryListener smram_listener;
1952static AddressSpace smram_address_space;
1953static MemoryRegion smram_as_root;
1954static MemoryRegion smram_as_mem;
1955
1956static void register_smram_listener(Notifier *n, void *unused)
1957{
1958 MemoryRegion *smram =
1959 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1960
1961 /* Outer container... */
1962 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1963 memory_region_set_enabled(&smram_as_root, true);
1964
1965 /* ... with two regions inside: normal system memory with low
1966 * priority, and...
1967 */
1968 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1969 get_system_memory(), 0, ~0ull);
1970 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1971 memory_region_set_enabled(&smram_as_mem, true);
1972
1973 if (smram) {
1974 /* ... SMRAM with higher priority */
1975 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1976 memory_region_set_enabled(smram, true);
1977 }
1978
1979 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1980 kvm_memory_listener_register(kvm_state, &smram_listener,
1981 &smram_address_space, 1);
1982}
1983
b16565b3 1984int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1985{
11076198 1986 uint64_t identity_base = 0xfffbc000;
39d6960a 1987 uint64_t shadow_mem;
20420430 1988 int ret;
25d2e361 1989 struct utsname utsname;
20420430 1990
28143b40 1991 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1992 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1993 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1994
e9688fab
RK		 1995 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1996
fd13f23b
LA		 1997 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
1998 if (has_exception_payload) {
1999 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2000 if (ret < 0) {
2001 error_report("kvm: Failed to enable exception payload cap: %s",
2002 strerror(-ret));
2003 return ret;
2004 }
2005 }
2006
c3a3a7d3 2007 ret = kvm_get_supported_msrs(s);
20420430 2008 if (ret < 0) {
20420430
SY		 2009 return ret;
2010 }
25d2e361 2011
f57bceb6
RH		 2012 kvm_get_supported_feature_msrs(s);
2013
25d2e361
MT		 2014 uname(&utsname);
2015 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2016
4c5b10b7 2017 /*
11076198
JK		 2018 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2019 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2020 * Since these must be part of guest physical memory, we need to allocate
2021 * them, both by setting their start addresses in the kernel and by
2022 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2023 *
2024 * Older KVM versions may not support setting the identity map base. In
2025 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2026 * size.
4c5b10b7 2027 */
11076198
JK		 2028 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2029 /* Allows up to 16M BIOSes. */
2030 identity_base = 0xfeffc000;
2031
2032 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2033 if (ret < 0) {
2034 return ret;
2035 }
4c5b10b7 2036 }
e56ff191 2037
11076198
JK		 2038 /* Set TSS base one page after EPT identity map. */
2039 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2040 if (ret < 0) {
2041 return ret;
2042 }
2043
11076198
JK		 2044 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2045 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2046 if (ret < 0) {
11076198 2047 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2048 return ret;
2049 }
3c85e74f 2050 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 2051
4689b77b 2052 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 2053 if (shadow_mem != -1) {
2054 shadow_mem /= 4096;
2055 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2056 if (ret < 0) {
2057 return ret;
39d6960a
JK		 2058 }
2059 }
6410848b 2060
d870cfde
GA		 2061 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2062 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
2063 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 2064 smram_machine_done.notify = register_smram_listener;
2065 qemu_add_machine_init_done_notifier(&smram_machine_done);
2066 }
6f131f13
MT		 2067
2068 if (enable_cpu_pm) {
2069 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2070 int ret;
2071
2072/* Work around for kernel header with a typo. TODO: fix header and drop. */
2073#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2074#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2075#endif
2076 if (disable_exits) {
2077 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2078 KVM_X86_DISABLE_EXITS_HLT |
d38d201f
WL		 2079 KVM_X86_DISABLE_EXITS_PAUSE |
2080 KVM_X86_DISABLE_EXITS_CSTATE);
6f131f13
MT		 2081 }
2082
2083 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2084 disable_exits);
2085 if (ret < 0) {
2086 error_report("kvm: guest stopping CPU not supported: %s",
2087 strerror(-ret));
2088 }
2089 }
2090
11076198 2091 return 0;
05330448 2092}
b9bec74b 2093
05330448
AL		 2094static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2095{
2096 lhs->selector = rhs->selector;
2097 lhs->base = rhs->base;
2098 lhs->limit = rhs->limit;
2099 lhs->type = 3;
2100 lhs->present = 1;
2101 lhs->dpl = 3;
2102 lhs->db = 0;
2103 lhs->s = 1;
2104 lhs->l = 0;
2105 lhs->g = 0;
2106 lhs->avl = 0;
2107 lhs->unusable = 0;
2108}
2109
2110static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2111{
2112 unsigned flags = rhs->flags;
2113 lhs->selector = rhs->selector;
2114 lhs->base = rhs->base;
2115 lhs->limit = rhs->limit;
2116 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2117 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2118 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2119 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2120 lhs->s = (flags & DESC_S_MASK) != 0;
2121 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2122 lhs->g = (flags & DESC_G_MASK) != 0;
2123 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2124 lhs->unusable = !lhs->present;
7e680753 2125 lhs->padding = 0;
05330448
AL		 2126}
2127
2128static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2129{
2130 lhs->selector = rhs->selector;
2131 lhs->base = rhs->base;
2132 lhs->limit = rhs->limit;
d45fc087
RP		 2133 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2134 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2135 (rhs->dpl << DESC_DPL_SHIFT) |
2136 (rhs->db << DESC_B_SHIFT) |
2137 (rhs->s * DESC_S_MASK) |
2138 (rhs->l << DESC_L_SHIFT) |
2139 (rhs->g * DESC_G_MASK) |
2140 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2141}
2142
2143static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2144{
b9bec74b 2145 if (set) {
05330448 2146 *kvm_reg = *qemu_reg;
b9bec74b 2147 } else {
05330448 2148 *qemu_reg = *kvm_reg;
b9bec74b 2149 }
05330448
AL		 2150}
2151
1bc22652 2152static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2153{
1bc22652 2154 CPUX86State *env = &cpu->env;
05330448
AL		 2155 struct kvm_regs regs;
2156 int ret = 0;
2157
2158 if (!set) {
1bc22652 2159 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2160 if (ret < 0) {
05330448 2161 return ret;
b9bec74b 2162 }
05330448
AL		 2163 }
2164
2165 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2166 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2167 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2168 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2169 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2170 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2171 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2172 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2173#ifdef TARGET_X86_64
2174 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2175 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2176 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2177 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2178 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2179 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2180 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2181 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2182#endif
2183
2184 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2185 kvm_getput_reg(&regs.rip, &env->eip, set);
2186
b9bec74b 2187 if (set) {
1bc22652 2188 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2189 }
05330448
AL		 2190
2191 return ret;
2192}
2193
1bc22652 2194static int kvm_put_fpu(X86CPU *cpu)
05330448 2195{
1bc22652 2196 CPUX86State *env = &cpu->env;
05330448
AL		 2197 struct kvm_fpu fpu;
2198 int i;
2199
2200 memset(&fpu, 0, sizeof fpu);
2201 fpu.fsw = env->fpus & ~(7 << 11);
2202 fpu.fsw |= (env->fpstt & 7) << 11;
2203 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2204 fpu.last_opcode = env->fpop;
2205 fpu.last_ip = env->fpip;
2206 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2207 for (i = 0; i < 8; ++i) {
2208 fpu.ftwx |= (!env->fptags[i]) << i;
2209 }
05330448 2210 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2211 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2212 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2213 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2214 }
05330448
AL		 2215 fpu.mxcsr = env->mxcsr;
2216
1bc22652 2217 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2218}
2219
6b42494b
JK		 2220#define XSAVE_FCW_FSW 0
2221#define XSAVE_FTW_FOP 1
f1665b21
SY		 2222#define XSAVE_CWD_RIP 2
2223#define XSAVE_CWD_RDP 4
2224#define XSAVE_MXCSR 6
2225#define XSAVE_ST_SPACE 8
2226#define XSAVE_XMM_SPACE 40
2227#define XSAVE_XSTATE_BV 128
2228#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2229#define XSAVE_BNDREGS 240
2230#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2231#define XSAVE_OPMASK 272
2232#define XSAVE_ZMM_Hi256 288
2233#define XSAVE_Hi16_ZMM 416
f74eefe0 2234#define XSAVE_PKRU 672
f1665b21 2235
b503717d 2236#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2237 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2238
2239#define ASSERT_OFFSET(word_offset, field) \
2240 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2241 offsetof(X86XSaveArea, field))
2242
2243ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2244ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2245ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2246ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2247ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2248ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2249ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2250ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2251ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2252ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2253ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2254ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2255ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2256ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2257ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2258
1bc22652 2259static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2260{
1bc22652 2261 CPUX86State *env = &cpu->env;
5b8063c4 2262 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2263
28143b40 2264 if (!has_xsave) {
1bc22652 2265 return kvm_put_fpu(cpu);
b9bec74b 2266 }
86a57621 2267 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2268
9be38598 2269 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2270}
2271
1bc22652 2272static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2273{
1bc22652 2274 CPUX86State *env = &cpu->env;
bdfc8480 2275 struct kvm_xcrs xcrs = {};
f1665b21 2276
28143b40 2277 if (!has_xcrs) {
f1665b21 2278 return 0;
b9bec74b 2279 }
f1665b21
SY		 2280
2281 xcrs.nr_xcrs = 1;
2282 xcrs.flags = 0;
2283 xcrs.xcrs[0].xcr = 0;
2284 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2285 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2286}
2287
1bc22652 2288static int kvm_put_sregs(X86CPU *cpu)
05330448 2289{
1bc22652 2290 CPUX86State *env = &cpu->env;
05330448
AL		 2291 struct kvm_sregs sregs;
2292
0e607a80
JK		 2293 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2294 if (env->interrupt_injected >= 0) {
2295 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2296 (uint64_t)1 << (env->interrupt_injected % 64);
2297 }
05330448
AL		 2298
2299 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2300 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2301 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2302 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2303 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2304 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2305 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2306 } else {
b9bec74b
JK		 2307 set_seg(&sregs.cs, &env->segs[R_CS]);
2308 set_seg(&sregs.ds, &env->segs[R_DS]);
2309 set_seg(&sregs.es, &env->segs[R_ES]);
2310 set_seg(&sregs.fs, &env->segs[R_FS]);
2311 set_seg(&sregs.gs, &env->segs[R_GS]);
2312 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2313 }
2314
2315 set_seg(&sregs.tr, &env->tr);
2316 set_seg(&sregs.ldt, &env->ldt);
2317
2318 sregs.idt.limit = env->idt.limit;
2319 sregs.idt.base = env->idt.base;
7e680753 2320 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2321 sregs.gdt.limit = env->gdt.limit;
2322 sregs.gdt.base = env->gdt.base;
7e680753 2323 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2324
2325 sregs.cr0 = env->cr[0];
2326 sregs.cr2 = env->cr[2];
2327 sregs.cr3 = env->cr[3];
2328 sregs.cr4 = env->cr[4];
2329
02e51483
CF		 2330 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2331 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2332
2333 sregs.efer = env->efer;
2334
1bc22652 2335 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2336}
2337
d71b62a1
EH		 2338static void kvm_msr_buf_reset(X86CPU *cpu)
2339{
2340 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2341}
2342
9c600a84
EH		 2343static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2344{
2345 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2346 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2347 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2348
2349 assert((void *)(entry + 1) <= limit);
2350
1abc2cae
EH		 2351 entry->index = index;
2352 entry->reserved = 0;
2353 entry->data = value;
9c600a84
EH		 2354 msrs->nmsrs++;
2355}
2356
73e1b8f2
PB		 2357static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2358{
2359 kvm_msr_buf_reset(cpu);
2360 kvm_msr_entry_add(cpu, index, value);
2361
2362 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2363}
2364
f8d9ccf8
DDAG		 2365void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2366{
2367 int ret;
2368
2369 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2370 assert(ret == 1);
2371}
2372
7477cd38
MT		 2373static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2374{
2375 CPUX86State *env = &cpu->env;
48e1a45c 2376 int ret;
7477cd38
MT		 2377
2378 if (!has_msr_tsc_deadline) {
2379 return 0;
2380 }
2381
73e1b8f2 2382 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2383 if (ret < 0) {
2384 return ret;
2385 }
2386
2387 assert(ret == 1);
2388 return 0;
7477cd38
MT		 2389}
2390
6bdf863d
JK		 2391/*
2392 * Provide a separate write service for the feature control MSR in order to
2393 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2394 * before writing any other state because forcibly leaving nested mode
2395 * invalidates the VCPU state.
2396 */
2397static int kvm_put_msr_feature_control(X86CPU *cpu)
2398{
48e1a45c
PB		 2399 int ret;
2400
2401 if (!has_msr_feature_control) {
2402 return 0;
2403 }
6bdf863d 2404
73e1b8f2
PB		 2405 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2406 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2407 if (ret < 0) {
2408 return ret;
2409 }
2410
2411 assert(ret == 1);
2412 return 0;
6bdf863d
JK		 2413}
2414
1bc22652 2415static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2416{
1bc22652 2417 CPUX86State *env = &cpu->env;
9c600a84 2418 int i;
48e1a45c 2419 int ret;
05330448 2420
d71b62a1
EH		 2421 kvm_msr_buf_reset(cpu);
2422
9c600a84
EH		 2423 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2424 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2425 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2426 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2427 if (has_msr_star) {
9c600a84 2428 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2429 }
c3a3a7d3 2430 if (has_msr_hsave_pa) {
9c600a84 2431 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2432 }
c9b8f6b6 2433 if (has_msr_tsc_aux) {
9c600a84 2434 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2435 }
f28558d3 2436 if (has_msr_tsc_adjust) {
9c600a84 2437 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2438 }
21e87c46 2439 if (has_msr_misc_enable) {
9c600a84 2440 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2441 env->msr_ia32_misc_enable);
2442 }
fc12d72e 2443 if (has_msr_smbase) {
9c600a84 2444 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2445 }
e13713db
LA		 2446 if (has_msr_smi_count) {
2447 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2448 }
439d19f2 2449 if (has_msr_bndcfgs) {
9c600a84 2450 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2451 }
18cd2c17 2452 if (has_msr_xss) {
9c600a84 2453 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2454 }
a33a2cfe
PB		 2455 if (has_msr_spec_ctrl) {
2456 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2457 }
cfeea0c0
KRW		 2458 if (has_msr_virt_ssbd) {
2459 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2460 }
2461
05330448 2462#ifdef TARGET_X86_64
25d2e361 2463 if (lm_capable_kernel) {
9c600a84
EH		 2464 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2465 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2466 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2467 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2468 }
05330448 2469#endif
a33a2cfe 2470
d86f9636 2471 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2472 if (has_msr_arch_capabs) {
2473 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2474 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2475 }
2476
597360c0
XL		 2477 if (has_msr_core_capabs) {
2478 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2479 env->features[FEAT_CORE_CAPABILITY]);
2480 }
2481
ff5c186b 2482 /*
0d894367
PB		 2483 * The following MSRs have side effects on the guest or are too heavy
2484 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2485 */
2486 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2487 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2488 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2489 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2490 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2491 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2492 }
55c911a5 2493 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2494 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2495 }
55c911a5 2496 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2497 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2498 }
d645e132
MT		 2499
2500 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2501 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2502 }
2503
0b368a10
JD		 2504 if (has_architectural_pmu_version > 0) {
2505 if (has_architectural_pmu_version > 1) {
2506 /* Stop the counter. */
2507 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2508 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2509 }
0d894367
PB		 2510
2511 /* Set the counter values. */
0b368a10 2512 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2513 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2514 env->msr_fixed_counters[i]);
2515 }
0b368a10 2516 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2517 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2518 env->msr_gp_counters[i]);
9c600a84 2519 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2520 env->msr_gp_evtsel[i]);
2521 }
0b368a10
JD		 2522 if (has_architectural_pmu_version > 1) {
2523 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2524 env->msr_global_status);
2525 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2526 env->msr_global_ovf_ctrl);
2527
2528 /* Now start the PMU. */
2529 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2530 env->msr_fixed_ctr_ctrl);
2531 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2532 env->msr_global_ctrl);
2533 }
0d894367 2534 }
da1cc323
EY		 2535 /*
2536 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2537 * only sync them to KVM on the first cpu
2538 */
2539 if (current_cpu == first_cpu) {
2540 if (has_msr_hv_hypercall) {
2541 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2542 env->msr_hv_guest_os_id);
2543 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2544 env->msr_hv_hypercall);
2545 }
2d384d7c 2546 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2547 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2548 env->msr_hv_tsc);
2549 }
2d384d7c 2550 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2551 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2552 env->msr_hv_reenlightenment_control);
2553 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2554 env->msr_hv_tsc_emulation_control);
2555 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2556 env->msr_hv_tsc_emulation_status);
2557 }
eab70139 2558 }
2d384d7c 2559 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2560 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2561 env->msr_hv_vapic);
eab70139 2562 }
f2a53c9e
AS		 2563 if (has_msr_hv_crash) {
2564 int j;
2565
5e953812 2566 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2567 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2568 env->msr_hv_crash_params[j]);
2569
5e953812 2570 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2571 }
46eb8f98 2572 if (has_msr_hv_runtime) {
9c600a84 2573 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2574 }
2d384d7c
VK		 2575 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2576 && hv_vpindex_settable) {
701189e3
RK		 2577 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2578 hyperv_vp_index(CPU(cpu)));
e9688fab 2579 }
2d384d7c 2580 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2581 int j;
2582
09df29b6
RK		 2583 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2584
9c600a84 2585 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2586 env->msr_hv_synic_control);
9c600a84 2587 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2588 env->msr_hv_synic_evt_page);
9c600a84 2589 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2590 env->msr_hv_synic_msg_page);
2591
2592 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2593 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2594 env->msr_hv_synic_sint[j]);
2595 }
2596 }
ff99aa64
AS		 2597 if (has_msr_hv_stimer) {
2598 int j;
2599
2600 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2601 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2602 env->msr_hv_stimer_config[j]);
2603 }
2604
2605 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2606 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2607 env->msr_hv_stimer_count[j]);
2608 }
2609 }
1eabfce6 2610 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2611 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2612
9c600a84
EH		 2613 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2614 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2615 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2616 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2617 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2618 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2619 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2620 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2621 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2622 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2623 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2624 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2625 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2626 /* The CPU GPs if we write to a bit above the physical limit of
2627 * the host CPU (and KVM emulates that)
2628 */
2629 uint64_t mask = env->mtrr_var[i].mask;
2630 mask &= phys_mask;
2631
9c600a84
EH		 2632 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2633 env->mtrr_var[i].base);
112dad69 2634 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2635 }
2636 }
b77146e9
CP		 2637 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2638 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2639 0x14, 1, R_EAX) & 0x7;
2640
2641 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2642 env->msr_rtit_ctrl);
2643 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2644 env->msr_rtit_status);
2645 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2646 env->msr_rtit_output_base);
2647 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2648 env->msr_rtit_output_mask);
2649 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2650 env->msr_rtit_cr3_match);
2651 for (i = 0; i < addr_num; i++) {
2652 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2653 env->msr_rtit_addrs[i]);
2654 }
2655 }
6bdf863d
JK		 2656
2657 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2658 * kvm_put_msr_feature_control. */
ea643051 2659 }
57780495 2660 if (env->mcg_cap) {
d8da8574 2661 int i;
b9bec74b 2662
9c600a84
EH		 2663 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2664 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2665 if (has_msr_mcg_ext_ctl) {
2666 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2667 }
c34d440a 2668 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2669 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2670 }
2671 }
1a03675d 2672
d71b62a1 2673 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2674 if (ret < 0) {
2675 return ret;
2676 }
05330448 2677
c70b11d1
EH		 2678 if (ret < cpu->kvm_msr_buf->nmsrs) {
2679 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2680 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2681 (uint32_t)e->index, (uint64_t)e->data);
2682 }
2683
9c600a84 2684 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2685 return 0;
05330448
AL		 2686}
2687
2688
1bc22652 2689static int kvm_get_fpu(X86CPU *cpu)
05330448 2690{
1bc22652 2691 CPUX86State *env = &cpu->env;
05330448
AL		 2692 struct kvm_fpu fpu;
2693 int i, ret;
2694
1bc22652 2695 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2696 if (ret < 0) {
05330448 2697 return ret;
b9bec74b 2698 }
05330448
AL		 2699
2700 env->fpstt = (fpu.fsw >> 11) & 7;
2701 env->fpus = fpu.fsw;
2702 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2703 env->fpop = fpu.last_opcode;
2704 env->fpip = fpu.last_ip;
2705 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2706 for (i = 0; i < 8; ++i) {
2707 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2708 }
05330448 2709 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2710 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2711 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2712 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2713 }
05330448
AL		 2714 env->mxcsr = fpu.mxcsr;
2715
2716 return 0;
2717}
2718
1bc22652 2719static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2720{
1bc22652 2721 CPUX86State *env = &cpu->env;
5b8063c4 2722 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2723 int ret;
f1665b21 2724
28143b40 2725 if (!has_xsave) {
1bc22652 2726 return kvm_get_fpu(cpu);
b9bec74b 2727 }
f1665b21 2728
1bc22652 2729 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2730 if (ret < 0) {
f1665b21 2731 return ret;
0f53994f 2732 }
86a57621 2733 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2734
f1665b21 2735 return 0;
f1665b21
SY		 2736}
2737
1bc22652 2738static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2739{
1bc22652 2740 CPUX86State *env = &cpu->env;
f1665b21
SY		 2741 int i, ret;
2742 struct kvm_xcrs xcrs;
2743
28143b40 2744 if (!has_xcrs) {
f1665b21 2745 return 0;
b9bec74b 2746 }
f1665b21 2747
1bc22652 2748 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2749 if (ret < 0) {
f1665b21 2750 return ret;
b9bec74b 2751 }
f1665b21 2752
b9bec74b 2753 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2754 /* Only support xcr0 now */
0fd53fec
PB		 2755 if (xcrs.xcrs[i].xcr == 0) {
2756 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2757 break;
2758 }
b9bec74b 2759 }
f1665b21 2760 return 0;
f1665b21
SY		 2761}
2762
1bc22652 2763static int kvm_get_sregs(X86CPU *cpu)
05330448 2764{
1bc22652 2765 CPUX86State *env = &cpu->env;
05330448 2766 struct kvm_sregs sregs;
0e607a80 2767 int bit, i, ret;
05330448 2768
1bc22652 2769 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2770 if (ret < 0) {
05330448 2771 return ret;
b9bec74b 2772 }
05330448 2773
0e607a80
JK		 2774 /* There can only be one pending IRQ set in the bitmap at a time, so try
2775 to find it and save its number instead (-1 for none). */
2776 env->interrupt_injected = -1;
2777 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2778 if (sregs.interrupt_bitmap[i]) {
2779 bit = ctz64(sregs.interrupt_bitmap[i]);
2780 env->interrupt_injected = i * 64 + bit;
2781 break;
2782 }
2783 }
05330448
AL		 2784
2785 get_seg(&env->segs[R_CS], &sregs.cs);
2786 get_seg(&env->segs[R_DS], &sregs.ds);
2787 get_seg(&env->segs[R_ES], &sregs.es);
2788 get_seg(&env->segs[R_FS], &sregs.fs);
2789 get_seg(&env->segs[R_GS], &sregs.gs);
2790 get_seg(&env->segs[R_SS], &sregs.ss);
2791
2792 get_seg(&env->tr, &sregs.tr);
2793 get_seg(&env->ldt, &sregs.ldt);
2794
2795 env->idt.limit = sregs.idt.limit;
2796 env->idt.base = sregs.idt.base;
2797 env->gdt.limit = sregs.gdt.limit;
2798 env->gdt.base = sregs.gdt.base;
2799
2800 env->cr[0] = sregs.cr0;
2801 env->cr[2] = sregs.cr2;
2802 env->cr[3] = sregs.cr3;
2803 env->cr[4] = sregs.cr4;
2804
05330448 2805 env->efer = sregs.efer;
cce47516
JK		 2806
2807 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2808 x86_update_hflags(env);
05330448
AL		 2809
2810 return 0;
2811}
2812
1bc22652 2813static int kvm_get_msrs(X86CPU *cpu)
05330448 2814{
1bc22652 2815 CPUX86State *env = &cpu->env;
d71b62a1 2816 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2817 int ret, i;
fcc35e7c 2818 uint64_t mtrr_top_bits;
05330448 2819
d71b62a1
EH		 2820 kvm_msr_buf_reset(cpu);
2821
9c600a84
EH		 2822 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2823 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2824 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2825 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2826 if (has_msr_star) {
9c600a84 2827 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2828 }
c3a3a7d3 2829 if (has_msr_hsave_pa) {
9c600a84 2830 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2831 }
c9b8f6b6 2832 if (has_msr_tsc_aux) {
9c600a84 2833 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2834 }
f28558d3 2835 if (has_msr_tsc_adjust) {
9c600a84 2836 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2837 }
aa82ba54 2838 if (has_msr_tsc_deadline) {
9c600a84 2839 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2840 }
21e87c46 2841 if (has_msr_misc_enable) {
9c600a84 2842 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2843 }
fc12d72e 2844 if (has_msr_smbase) {
9c600a84 2845 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2846 }
e13713db
LA		 2847 if (has_msr_smi_count) {
2848 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2849 }
df67696e 2850 if (has_msr_feature_control) {
9c600a84 2851 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2852 }
79e9ebeb 2853 if (has_msr_bndcfgs) {
9c600a84 2854 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2855 }
18cd2c17 2856 if (has_msr_xss) {
9c600a84 2857 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2858 }
a33a2cfe
PB		 2859 if (has_msr_spec_ctrl) {
2860 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2861 }
cfeea0c0
KRW		 2862 if (has_msr_virt_ssbd) {
2863 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2864 }
b8cc45d6 2865 if (!env->tsc_valid) {
9c600a84 2866 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2867 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2868 }
2869
05330448 2870#ifdef TARGET_X86_64
25d2e361 2871 if (lm_capable_kernel) {
9c600a84
EH		 2872 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2873 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2874 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2875 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2876 }
05330448 2877#endif
9c600a84
EH		 2878 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2879 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2880 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2881 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2882 }
55c911a5 2883 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2884 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2885 }
55c911a5 2886 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2887 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2888 }
d645e132
MT		 2889 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2890 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
2891 }
0b368a10
JD		 2892 if (has_architectural_pmu_version > 0) {
2893 if (has_architectural_pmu_version > 1) {
2894 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2895 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2896 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2897 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2898 }
2899 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2900 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2901 }
0b368a10 2902 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2903 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2904 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2905 }
2906 }
1a03675d 2907
57780495 2908 if (env->mcg_cap) {
9c600a84
EH		 2909 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2910 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2911 if (has_msr_mcg_ext_ctl) {
2912 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2913 }
b9bec74b 2914 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2915 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2916 }
57780495 2917 }
57780495 2918
1c90ef26 2919 if (has_msr_hv_hypercall) {
9c600a84
EH		 2920 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2921 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2922 }
2d384d7c 2923 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2924 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2925 }
2d384d7c 2926 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 2927 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2928 }
2d384d7c 2929 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2930 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2931 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2932 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2933 }
f2a53c9e
AS		 2934 if (has_msr_hv_crash) {
2935 int j;
2936
5e953812 2937 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2938 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2939 }
2940 }
46eb8f98 2941 if (has_msr_hv_runtime) {
9c600a84 2942 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2943 }
2d384d7c 2944 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2945 uint32_t msr;
2946
9c600a84 2947 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2948 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2949 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2950 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2951 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2952 }
2953 }
ff99aa64
AS		 2954 if (has_msr_hv_stimer) {
2955 uint32_t msr;
2956
2957 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2958 msr++) {
9c600a84 2959 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2960 }
2961 }
1eabfce6 2962 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2963 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2964 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2965 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2966 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2967 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2968 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2969 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2970 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2971 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2972 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2973 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2974 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2975 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2976 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2977 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2978 }
2979 }
5ef68987 2980
b77146e9
CP		 2981 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2982 int addr_num =
2983 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2984
2985 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2986 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2987 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2988 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2989 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2990 for (i = 0; i < addr_num; i++) {
2991 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2992 }
2993 }
2994
d71b62a1 2995 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2996 if (ret < 0) {
05330448 2997 return ret;
b9bec74b 2998 }
05330448 2999
c70b11d1
EH		 3000 if (ret < cpu->kvm_msr_buf->nmsrs) {
3001 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3002 error_report("error: failed to get MSR 0x%" PRIx32,
3003 (uint32_t)e->index);
3004 }
3005
9c600a84 3006 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 3007 /*
3008 * MTRR masks: Each mask consists of 5 parts
3009 * a 10..0: must be zero
3010 * b 11 : valid bit
3011 * c n-1.12: actual mask bits
3012 * d 51..n: reserved must be zero
3013 * e 63.52: reserved must be zero
3014 *
3015 * 'n' is the number of physical bits supported by the CPU and is
3016 * apparently always <= 52. We know our 'n' but don't know what
3017 * the destinations 'n' is; it might be smaller, in which case
3018 * it masks (c) on loading. It might be larger, in which case
3019 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3020 * we're migrating to.
3021 */
3022
3023 if (cpu->fill_mtrr_mask) {
3024 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3025 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3026 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3027 } else {
3028 mtrr_top_bits = 0;
3029 }
3030
05330448 3031 for (i = 0; i < ret; i++) {
0d894367
PB		 3032 uint32_t index = msrs[i].index;
3033 switch (index) {
05330448
AL		 3034 case MSR_IA32_SYSENTER_CS:
3035 env->sysenter_cs = msrs[i].data;
3036 break;
3037 case MSR_IA32_SYSENTER_ESP:
3038 env->sysenter_esp = msrs[i].data;
3039 break;
3040 case MSR_IA32_SYSENTER_EIP:
3041 env->sysenter_eip = msrs[i].data;
3042 break;
0c03266a
JK		 3043 case MSR_PAT:
3044 env->pat = msrs[i].data;
3045 break;
05330448
AL		 3046 case MSR_STAR:
3047 env->star = msrs[i].data;
3048 break;
3049#ifdef TARGET_X86_64
3050 case MSR_CSTAR:
3051 env->cstar = msrs[i].data;
3052 break;
3053 case MSR_KERNELGSBASE:
3054 env->kernelgsbase = msrs[i].data;
3055 break;
3056 case MSR_FMASK:
3057 env->fmask = msrs[i].data;
3058 break;
3059 case MSR_LSTAR:
3060 env->lstar = msrs[i].data;
3061 break;
3062#endif
3063 case MSR_IA32_TSC:
3064 env->tsc = msrs[i].data;
3065 break;
c9b8f6b6
AS		 3066 case MSR_TSC_AUX:
3067 env->tsc_aux = msrs[i].data;
3068 break;
f28558d3
WA		 3069 case MSR_TSC_ADJUST:
3070 env->tsc_adjust = msrs[i].data;
3071 break;
aa82ba54
LJ		 3072 case MSR_IA32_TSCDEADLINE:
3073 env->tsc_deadline = msrs[i].data;
3074 break;
aa851e36
MT		 3075 case MSR_VM_HSAVE_PA:
3076 env->vm_hsave = msrs[i].data;
3077 break;
1a03675d
GC		 3078 case MSR_KVM_SYSTEM_TIME:
3079 env->system_time_msr = msrs[i].data;
3080 break;
3081 case MSR_KVM_WALL_CLOCK:
3082 env->wall_clock_msr = msrs[i].data;
3083 break;
57780495
MT		 3084 case MSR_MCG_STATUS:
3085 env->mcg_status = msrs[i].data;
3086 break;
3087 case MSR_MCG_CTL:
3088 env->mcg_ctl = msrs[i].data;
3089 break;
87f8b626
AR		 3090 case MSR_MCG_EXT_CTL:
3091 env->mcg_ext_ctl = msrs[i].data;
3092 break;
21e87c46
AK		 3093 case MSR_IA32_MISC_ENABLE:
3094 env->msr_ia32_misc_enable = msrs[i].data;
3095 break;
fc12d72e
PB		 3096 case MSR_IA32_SMBASE:
3097 env->smbase = msrs[i].data;
3098 break;
e13713db
LA		 3099 case MSR_SMI_COUNT:
3100 env->msr_smi_count = msrs[i].data;
3101 break;
0779caeb
ACL		 3102 case MSR_IA32_FEATURE_CONTROL:
3103 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3104 break;
79e9ebeb
LJ		 3105 case MSR_IA32_BNDCFGS:
3106 env->msr_bndcfgs = msrs[i].data;
3107 break;
18cd2c17
WL		 3108 case MSR_IA32_XSS:
3109 env->xss = msrs[i].data;
3110 break;
57780495 3111 default:
57780495
MT		 3112 if (msrs[i].index >= MSR_MC0_CTL &&
3113 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3114 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3115 }
d8da8574 3116 break;
f6584ee2
GN		 3117 case MSR_KVM_ASYNC_PF_EN:
3118 env->async_pf_en_msr = msrs[i].data;
3119 break;
bc9a839d
MT		 3120 case MSR_KVM_PV_EOI_EN:
3121 env->pv_eoi_en_msr = msrs[i].data;
3122 break;
917367aa
MT		 3123 case MSR_KVM_STEAL_TIME:
3124 env->steal_time_msr = msrs[i].data;
3125 break;
d645e132
MT		 3126 case MSR_KVM_POLL_CONTROL: {
3127 env->poll_control_msr = msrs[i].data;
3128 break;
3129 }
0d894367
PB		 3130 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3131 env->msr_fixed_ctr_ctrl = msrs[i].data;
3132 break;
3133 case MSR_CORE_PERF_GLOBAL_CTRL:
3134 env->msr_global_ctrl = msrs[i].data;
3135 break;
3136 case MSR_CORE_PERF_GLOBAL_STATUS:
3137 env->msr_global_status = msrs[i].data;
3138 break;
3139 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3140 env->msr_global_ovf_ctrl = msrs[i].data;
3141 break;
3142 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3143 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3144 break;
3145 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3146 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3147 break;
3148 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3149 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3150 break;
1c90ef26
VR		 3151 case HV_X64_MSR_HYPERCALL:
3152 env->msr_hv_hypercall = msrs[i].data;
3153 break;
3154 case HV_X64_MSR_GUEST_OS_ID:
3155 env->msr_hv_guest_os_id = msrs[i].data;
3156 break;
5ef68987
VR		 3157 case HV_X64_MSR_APIC_ASSIST_PAGE:
3158 env->msr_hv_vapic = msrs[i].data;
3159 break;
48a5f3bc
VR		 3160 case HV_X64_MSR_REFERENCE_TSC:
3161 env->msr_hv_tsc = msrs[i].data;
3162 break;
f2a53c9e
AS		 3163 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3164 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3165 break;
46eb8f98
AS		 3166 case HV_X64_MSR_VP_RUNTIME:
3167 env->msr_hv_runtime = msrs[i].data;
3168 break;
866eea9a
AS		 3169 case HV_X64_MSR_SCONTROL:
3170 env->msr_hv_synic_control = msrs[i].data;
3171 break;
866eea9a
AS		 3172 case HV_X64_MSR_SIEFP:
3173 env->msr_hv_synic_evt_page = msrs[i].data;
3174 break;
3175 case HV_X64_MSR_SIMP:
3176 env->msr_hv_synic_msg_page = msrs[i].data;
3177 break;
3178 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3179 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3180 break;
3181 case HV_X64_MSR_STIMER0_CONFIG:
3182 case HV_X64_MSR_STIMER1_CONFIG:
3183 case HV_X64_MSR_STIMER2_CONFIG:
3184 case HV_X64_MSR_STIMER3_CONFIG:
3185 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3186 msrs[i].data;
3187 break;
3188 case HV_X64_MSR_STIMER0_COUNT:
3189 case HV_X64_MSR_STIMER1_COUNT:
3190 case HV_X64_MSR_STIMER2_COUNT:
3191 case HV_X64_MSR_STIMER3_COUNT:
3192 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3193 msrs[i].data;
866eea9a 3194 break;
ba6a4fd9
VK		 3195 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3196 env->msr_hv_reenlightenment_control = msrs[i].data;
3197 break;
3198 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3199 env->msr_hv_tsc_emulation_control = msrs[i].data;
3200 break;
3201 case HV_X64_MSR_TSC_EMULATION_STATUS:
3202 env->msr_hv_tsc_emulation_status = msrs[i].data;
3203 break;
d1ae67f6
AW		 3204 case MSR_MTRRdefType:
3205 env->mtrr_deftype = msrs[i].data;
3206 break;
3207 case MSR_MTRRfix64K_00000:
3208 env->mtrr_fixed[0] = msrs[i].data;
3209 break;
3210 case MSR_MTRRfix16K_80000:
3211 env->mtrr_fixed[1] = msrs[i].data;
3212 break;
3213 case MSR_MTRRfix16K_A0000:
3214 env->mtrr_fixed[2] = msrs[i].data;
3215 break;
3216 case MSR_MTRRfix4K_C0000:
3217 env->mtrr_fixed[3] = msrs[i].data;
3218 break;
3219 case MSR_MTRRfix4K_C8000:
3220 env->mtrr_fixed[4] = msrs[i].data;
3221 break;
3222 case MSR_MTRRfix4K_D0000:
3223 env->mtrr_fixed[5] = msrs[i].data;
3224 break;
3225 case MSR_MTRRfix4K_D8000:
3226 env->mtrr_fixed[6] = msrs[i].data;
3227 break;
3228 case MSR_MTRRfix4K_E0000:
3229 env->mtrr_fixed[7] = msrs[i].data;
3230 break;
3231 case MSR_MTRRfix4K_E8000:
3232 env->mtrr_fixed[8] = msrs[i].data;
3233 break;
3234 case MSR_MTRRfix4K_F0000:
3235 env->mtrr_fixed[9] = msrs[i].data;
3236 break;
3237 case MSR_MTRRfix4K_F8000:
3238 env->mtrr_fixed[10] = msrs[i].data;
3239 break;
3240 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3241 if (index & 1) {
fcc35e7c
DDAG		 3242 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3243 mtrr_top_bits;
d1ae67f6
AW		 3244 } else {
3245 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3246 }
3247 break;
a33a2cfe
PB		 3248 case MSR_IA32_SPEC_CTRL:
3249 env->spec_ctrl = msrs[i].data;
3250 break;
cfeea0c0
KRW		 3251 case MSR_VIRT_SSBD:
3252 env->virt_ssbd = msrs[i].data;
3253 break;
b77146e9
CP		 3254 case MSR_IA32_RTIT_CTL:
3255 env->msr_rtit_ctrl = msrs[i].data;
3256 break;
3257 case MSR_IA32_RTIT_STATUS:
3258 env->msr_rtit_status = msrs[i].data;
3259 break;
3260 case MSR_IA32_RTIT_OUTPUT_BASE:
3261 env->msr_rtit_output_base = msrs[i].data;
3262 break;
3263 case MSR_IA32_RTIT_OUTPUT_MASK:
3264 env->msr_rtit_output_mask = msrs[i].data;
3265 break;
3266 case MSR_IA32_RTIT_CR3_MATCH:
3267 env->msr_rtit_cr3_match = msrs[i].data;
3268 break;
3269 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3270 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3271 break;
05330448
AL		 3272 }
3273 }
3274
3275 return 0;
3276}
3277
1bc22652 3278static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3279{
1bc22652 3280 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3281
1bc22652 3282 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3283}
3284
23d02d9b 3285static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3286{
259186a7 3287 CPUState *cs = CPU(cpu);
23d02d9b 3288 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3289 struct kvm_mp_state mp_state;
3290 int ret;
3291
259186a7 3292 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3293 if (ret < 0) {
3294 return ret;
3295 }
3296 env->mp_state = mp_state.mp_state;
c14750e8 3297 if (kvm_irqchip_in_kernel()) {
259186a7 3298 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3299 }
9bdbe550
HB		 3300 return 0;
3301}
3302
1bc22652 3303static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3304{
02e51483 3305 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3306 struct kvm_lapic_state kapic;
3307 int ret;
3308
3d4b2649 3309 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3310 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3311 if (ret < 0) {
3312 return ret;
3313 }
3314
3315 kvm_get_apic_state(apic, &kapic);
3316 }
3317 return 0;
3318}
3319
1bc22652 3320static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3321{
fc12d72e 3322 CPUState *cs = CPU(cpu);
1bc22652 3323 CPUX86State *env = &cpu->env;
076796f8 3324 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3325
3326 if (!kvm_has_vcpu_events()) {
3327 return 0;
3328 }
3329
fd13f23b
LA		 3330 events.flags = 0;
3331
3332 if (has_exception_payload) {
3333 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3334 events.exception.pending = env->exception_pending;
3335 events.exception_has_payload = env->exception_has_payload;
3336 events.exception_payload = env->exception_payload;
3337 }
3338 events.exception.nr = env->exception_nr;
3339 events.exception.injected = env->exception_injected;
a0fb002c
JK		 3340 events.exception.has_error_code = env->has_error_code;
3341 events.exception.error_code = env->error_code;
3342
3343 events.interrupt.injected = (env->interrupt_injected >= 0);
3344 events.interrupt.nr = env->interrupt_injected;
3345 events.interrupt.soft = env->soft_interrupt;
3346
3347 events.nmi.injected = env->nmi_injected;
3348 events.nmi.pending = env->nmi_pending;
3349 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3350
3351 events.sipi_vector = env->sipi_vector;
3352
fc12d72e
PB		 3353 if (has_msr_smbase) {
3354 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3355 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3356 if (kvm_irqchip_in_kernel()) {
3357 /* As soon as these are moved to the kernel, remove them
3358 * from cs->interrupt_request.
3359 */
3360 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3361 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3362 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3363 } else {
3364 /* Keep these in cs->interrupt_request. */
3365 events.smi.pending = 0;
3366 events.smi.latched_init = 0;
3367 }
fc3a1fd7
DDAG		 3368 /* Stop SMI delivery on old machine types to avoid a reboot
3369 * on an inward migration of an old VM.
3370 */
3371 if (!cpu->kvm_no_smi_migration) {
3372 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3373 }
fc12d72e
PB		 3374 }
3375
ea643051 3376 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3377 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3378 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3379 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3380 }
ea643051 3381 }
aee028b9 3382
1bc22652 3383 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3384}
3385
1bc22652 3386static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3387{
1bc22652 3388 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3389 struct kvm_vcpu_events events;
3390 int ret;
3391
3392 if (!kvm_has_vcpu_events()) {
3393 return 0;
3394 }
3395
fc12d72e 3396 memset(&events, 0, sizeof(events));
1bc22652 3397 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3398 if (ret < 0) {
3399 return ret;
3400 }
fd13f23b
LA		 3401
3402 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3403 env->exception_pending = events.exception.pending;
3404 env->exception_has_payload = events.exception_has_payload;
3405 env->exception_payload = events.exception_payload;
3406 } else {
3407 env->exception_pending = 0;
3408 env->exception_has_payload = false;
3409 }
3410 env->exception_injected = events.exception.injected;
3411 env->exception_nr =
3412 (env->exception_pending || env->exception_injected) ?
3413 events.exception.nr : -1;
a0fb002c
JK		 3414 env->has_error_code = events.exception.has_error_code;
3415 env->error_code = events.exception.error_code;
3416
3417 env->interrupt_injected =
3418 events.interrupt.injected ? events.interrupt.nr : -1;
3419 env->soft_interrupt = events.interrupt.soft;
3420
3421 env->nmi_injected = events.nmi.injected;
3422 env->nmi_pending = events.nmi.pending;
3423 if (events.nmi.masked) {
3424 env->hflags2 |= HF2_NMI_MASK;
3425 } else {
3426 env->hflags2 &= ~HF2_NMI_MASK;
3427 }
3428
fc12d72e
PB		 3429 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3430 if (events.smi.smm) {
3431 env->hflags |= HF_SMM_MASK;
3432 } else {
3433 env->hflags &= ~HF_SMM_MASK;
3434 }
3435 if (events.smi.pending) {
3436 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3437 } else {
3438 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3439 }
3440 if (events.smi.smm_inside_nmi) {
3441 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3442 } else {
3443 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3444 }
3445 if (events.smi.latched_init) {
3446 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3447 } else {
3448 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3449 }
3450 }
3451
a0fb002c 3452 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3453
3454 return 0;
3455}
3456
1bc22652 3457static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3458{
ed2803da 3459 CPUState *cs = CPU(cpu);
1bc22652 3460 CPUX86State *env = &cpu->env;
b0b1d690 3461 int ret = 0;
b0b1d690
JK		 3462 unsigned long reinject_trap = 0;
3463
3464 if (!kvm_has_vcpu_events()) {
fd13f23b 3465 if (env->exception_nr == EXCP01_DB) {
b0b1d690 3466 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 3467 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 3468 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3469 }
fd13f23b 3470 kvm_reset_exception(env);
b0b1d690
JK		 3471 }
3472
3473 /*
3474 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3475 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3476 * by updating the debug state once again if single-stepping is on.
3477 * Another reason to call kvm_update_guest_debug here is a pending debug
3478 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3479 * reinject them via SET_GUEST_DEBUG.
3480 */
3481 if (reinject_trap ||
ed2803da 3482 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3483 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3484 }
b0b1d690
JK		 3485 return ret;
3486}
3487
1bc22652 3488static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3489{
1bc22652 3490 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3491 struct kvm_debugregs dbgregs;
3492 int i;
3493
3494 if (!kvm_has_debugregs()) {
3495 return 0;
3496 }
3497
1f670a95 3498 memset(&dbgregs, 0, sizeof(dbgregs));
ff44f1a3
JK		 3499 for (i = 0; i < 4; i++) {
3500 dbgregs.db[i] = env->dr[i];
3501 }
3502 dbgregs.dr6 = env->dr[6];
3503 dbgregs.dr7 = env->dr[7];
3504 dbgregs.flags = 0;
3505
1bc22652 3506 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3507}
3508
1bc22652 3509static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3510{
1bc22652 3511 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3512 struct kvm_debugregs dbgregs;
3513 int i, ret;
3514
3515 if (!kvm_has_debugregs()) {
3516 return 0;
3517 }
3518
1bc22652 3519 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3520 if (ret < 0) {
b9bec74b 3521 return ret;
ff44f1a3
JK		 3522 }
3523 for (i = 0; i < 4; i++) {
3524 env->dr[i] = dbgregs.db[i];
3525 }
3526 env->dr[4] = env->dr[6] = dbgregs.dr6;
3527 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3528
3529 return 0;
3530}
3531
ebbfef2f
LA		 3532static int kvm_put_nested_state(X86CPU *cpu)
3533{
3534 CPUX86State *env = &cpu->env;
3535 int max_nested_state_len = kvm_max_nested_state_length();
3536
1e44f3ab 3537 if (!env->nested_state) {
ebbfef2f
LA		 3538 return 0;
3539 }
3540
3541 assert(env->nested_state->size <= max_nested_state_len);
3542 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3543}
3544
3545static int kvm_get_nested_state(X86CPU *cpu)
3546{
3547 CPUX86State *env = &cpu->env;
3548 int max_nested_state_len = kvm_max_nested_state_length();
3549 int ret;
3550
1e44f3ab 3551 if (!env->nested_state) {
ebbfef2f
LA		 3552 return 0;
3553 }
3554
3555 /*
3556 * It is possible that migration restored a smaller size into
3557 * nested_state->hdr.size than what our kernel support.
3558 * We preserve migration origin nested_state->hdr.size for
3559 * call to KVM_SET_NESTED_STATE but wish that our next call
3560 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3561 */
3562 env->nested_state->size = max_nested_state_len;
3563
3564 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3565 if (ret < 0) {
3566 return ret;
3567 }
3568
3569 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3570 env->hflags |= HF_GUEST_MASK;
3571 } else {
3572 env->hflags &= ~HF_GUEST_MASK;
3573 }
3574
3575 return ret;
3576}
3577
20d695a9 3578int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3579{
20d695a9 3580 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3581 int ret;
3582
2fa45344 3583 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3584
48e1a45c 3585 if (level >= KVM_PUT_RESET_STATE) {
bec7156a
JK		 3586 ret = kvm_put_nested_state(x86_cpu);
3587 if (ret < 0) {
3588 return ret;
3589 }
3590
6bdf863d
JK		 3591 ret = kvm_put_msr_feature_control(x86_cpu);
3592 if (ret < 0) {
3593 return ret;
3594 }
3595 }
3596
36f96c4b
HZ		 3597 if (level == KVM_PUT_FULL_STATE) {
3598 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3599 * because TSC frequency mismatch shouldn't abort migration,
3600 * unless the user explicitly asked for a more strict TSC
3601 * setting (e.g. using an explicit "tsc-freq" option).
3602 */
3603 kvm_arch_set_tsc_khz(cpu);
3604 }
3605
1bc22652 3606 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3607 if (ret < 0) {
05330448 3608 return ret;
b9bec74b 3609 }
1bc22652 3610 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3611 if (ret < 0) {
f1665b21 3612 return ret;
b9bec74b 3613 }
1bc22652 3614 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3615 if (ret < 0) {
05330448 3616 return ret;
b9bec74b 3617 }
1bc22652 3618 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3619 if (ret < 0) {
05330448 3620 return ret;
b9bec74b 3621 }
ab443475 3622 /* must be before kvm_put_msrs */
1bc22652 3623 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3624 if (ret < 0) {
3625 return ret;
3626 }
1bc22652 3627 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3628 if (ret < 0) {
05330448 3629 return ret;
b9bec74b 3630 }
4fadfa00
PH		 3631 ret = kvm_put_vcpu_events(x86_cpu, level);
3632 if (ret < 0) {
3633 return ret;
3634 }
ea643051 3635 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3636 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3637 if (ret < 0) {
680c1c6f
JK		 3638 return ret;
3639 }
ea643051 3640 }
7477cd38
MT		 3641
3642 ret = kvm_put_tscdeadline_msr(x86_cpu);
3643 if (ret < 0) {
3644 return ret;
3645 }
1bc22652 3646 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3647 if (ret < 0) {
b0b1d690 3648 return ret;
b9bec74b 3649 }
b0b1d690 3650 /* must be last */
1bc22652 3651 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3652 if (ret < 0) {
ff44f1a3 3653 return ret;
b9bec74b 3654 }
05330448
AL		 3655 return 0;
3656}
3657
20d695a9 3658int kvm_arch_get_registers(CPUState *cs)
05330448 3659{
20d695a9 3660 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3661 int ret;
3662
20d695a9 3663 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3664
4fadfa00 3665 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3666 if (ret < 0) {
f4f1110e 3667 goto out;
b9bec74b 3668 }
4fadfa00
PH		 3669 /*
3670 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3671 * KVM_GET_REGS and KVM_GET_SREGS.
3672 */
3673 ret = kvm_get_mp_state(cpu);
b9bec74b 3674 if (ret < 0) {
f4f1110e 3675 goto out;
b9bec74b 3676 }
4fadfa00 3677 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3678 if (ret < 0) {
f4f1110e 3679 goto out;
b9bec74b 3680 }
4fadfa00 3681 ret = kvm_get_xsave(cpu);
b9bec74b 3682 if (ret < 0) {
f4f1110e 3683 goto out;
b9bec74b 3684 }
4fadfa00 3685 ret = kvm_get_xcrs(cpu);
b9bec74b 3686 if (ret < 0) {
f4f1110e 3687 goto out;
b9bec74b 3688 }
4fadfa00 3689 ret = kvm_get_sregs(cpu);
b9bec74b 3690 if (ret < 0) {
f4f1110e 3691 goto out;
b9bec74b 3692 }
4fadfa00 3693 ret = kvm_get_msrs(cpu);
680c1c6f 3694 if (ret < 0) {
f4f1110e 3695 goto out;
680c1c6f 3696 }
4fadfa00 3697 ret = kvm_get_apic(cpu);
b9bec74b 3698 if (ret < 0) {
f4f1110e 3699 goto out;
b9bec74b 3700 }
1bc22652 3701 ret = kvm_get_debugregs(cpu);
b9bec74b 3702 if (ret < 0) {
f4f1110e 3703 goto out;
b9bec74b 3704 }
ebbfef2f
LA		 3705 ret = kvm_get_nested_state(cpu);
3706 if (ret < 0) {
3707 goto out;
3708 }
f4f1110e
RH		 3709 ret = 0;
3710 out:
3711 cpu_sync_bndcs_hflags(&cpu->env);
3712 return ret;
05330448
AL		 3713}
3714
20d695a9 3715void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3716{
20d695a9
AF		 3717 X86CPU *x86_cpu = X86_CPU(cpu);
3718 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3719 int ret;
3720
276ce815 3721 /* Inject NMI */
fc12d72e
PB		 3722 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3723 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3724 qemu_mutex_lock_iothread();
3725 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3726 qemu_mutex_unlock_iothread();
3727 DPRINTF("injected NMI\n");
3728 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3729 if (ret < 0) {
3730 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3731 strerror(-ret));
3732 }
3733 }
3734 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3735 qemu_mutex_lock_iothread();
3736 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3737 qemu_mutex_unlock_iothread();
3738 DPRINTF("injected SMI\n");
3739 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3740 if (ret < 0) {
3741 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3742 strerror(-ret));
3743 }
ce377af3 3744 }
276ce815
LJ		 3745 }
3746
15eafc2e 3747 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3748 qemu_mutex_lock_iothread();
3749 }
3750
e0723c45
PB		 3751 /* Force the VCPU out of its inner loop to process any INIT requests
3752 * or (for userspace APIC, but it is cheap to combine the checks here)
3753 * pending TPR access reports.
3754 */
3755 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3756 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3757 !(env->hflags & HF_SMM_MASK)) {
3758 cpu->exit_request = 1;
3759 }
3760 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3761 cpu->exit_request = 1;
3762 }
e0723c45 3763 }
05330448 3764
15eafc2e 3765 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3766 /* Try to inject an interrupt if the guest can accept it */
3767 if (run->ready_for_interrupt_injection &&
259186a7 3768 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3769 (env->eflags & IF_MASK)) {
3770 int irq;
3771
259186a7 3772 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3773 irq = cpu_get_pic_interrupt(env);
3774 if (irq >= 0) {
3775 struct kvm_interrupt intr;
3776
3777 intr.irq = irq;
db1669bc 3778 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3779 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3780 if (ret < 0) {
3781 fprintf(stderr,
3782 "KVM: injection failed, interrupt lost (%s)\n",
3783 strerror(-ret));
3784 }
db1669bc
JK		 3785 }
3786 }
05330448 3787
db1669bc
JK		 3788 /* If we have an interrupt but the guest is not ready to receive an
3789 * interrupt, request an interrupt window exit. This will
3790 * cause a return to userspace as soon as the guest is ready to
3791 * receive interrupts. */
259186a7 3792 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3793 run->request_interrupt_window = 1;
3794 } else {
3795 run->request_interrupt_window = 0;
3796 }
3797
3798 DPRINTF("setting tpr\n");
02e51483 3799 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3800
3801 qemu_mutex_unlock_iothread();
db1669bc 3802 }
05330448
AL		 3803}
3804
4c663752 3805MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3806{
20d695a9
AF		 3807 X86CPU *x86_cpu = X86_CPU(cpu);
3808 CPUX86State *env = &x86_cpu->env;
3809
fc12d72e
PB		 3810 if (run->flags & KVM_RUN_X86_SMM) {
3811 env->hflags |= HF_SMM_MASK;
3812 } else {
f5c052b9 3813 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3814 }
b9bec74b 3815 if (run->if_flag) {
05330448 3816 env->eflags |= IF_MASK;
b9bec74b 3817 } else {
05330448 3818 env->eflags &= ~IF_MASK;
b9bec74b 3819 }
4b8523ee
JK		 3820
3821 /* We need to protect the apic state against concurrent accesses from
3822 * different threads in case the userspace irqchip is used. */
3823 if (!kvm_irqchip_in_kernel()) {
3824 qemu_mutex_lock_iothread();
3825 }
02e51483
CF		 3826 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3827 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3828 if (!kvm_irqchip_in_kernel()) {
3829 qemu_mutex_unlock_iothread();
3830 }
f794aa4a 3831 return cpu_get_mem_attrs(env);
05330448
AL		 3832}
3833
20d695a9 3834int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3835{
20d695a9
AF		 3836 X86CPU *cpu = X86_CPU(cs);
3837 CPUX86State *env = &cpu->env;
232fc23b 3838
259186a7 3839 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3840 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3841 assert(env->mcg_cap);
3842
259186a7 3843 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3844
dd1750d7 3845 kvm_cpu_synchronize_state(cs);
ab443475 3846
fd13f23b 3847 if (env->exception_nr == EXCP08_DBLE) {
ab443475 3848 /* this means triple fault */
cf83f140 3849 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3850 cs->exit_request = 1;
ab443475
JK		 3851 return 0;
3852 }
fd13f23b 3853 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 3854 env->has_error_code = 0;
3855
259186a7 3856 cs->halted = 0;
ab443475
JK		 3857 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3858 env->mp_state = KVM_MP_STATE_RUNNABLE;
3859 }
3860 }
3861
fc12d72e
PB		 3862 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3863 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3864 kvm_cpu_synchronize_state(cs);
3865 do_cpu_init(cpu);
3866 }
3867
db1669bc
JK		 3868 if (kvm_irqchip_in_kernel()) {
3869 return 0;
3870 }
3871
259186a7
AF		 3872 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3873 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3874 apic_poll_irq(cpu->apic_state);
5d62c43a 3875 }
259186a7 3876 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3877 (env->eflags & IF_MASK)) ||
259186a7
AF		 3878 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3879 cs->halted = 0;
6792a57b 3880 }
259186a7 3881 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3882 kvm_cpu_synchronize_state(cs);
232fc23b 3883 do_cpu_sipi(cpu);
0af691d7 3884 }
259186a7
AF		 3885 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3886 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3887 kvm_cpu_synchronize_state(cs);
02e51483 3888 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3889 env->tpr_access_type);
3890 }
0af691d7 3891
259186a7 3892 return cs->halted;
0af691d7
MT		 3893}
3894
839b5630 3895static int kvm_handle_halt(X86CPU *cpu)
05330448 3896{
259186a7 3897 CPUState *cs = CPU(cpu);
839b5630
AF		 3898 CPUX86State *env = &cpu->env;
3899
259186a7 3900 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3901 (env->eflags & IF_MASK)) &&
259186a7
AF		 3902 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3903 cs->halted = 1;
bb4ea393 3904 return EXCP_HLT;
05330448
AL		 3905 }
3906
bb4ea393 3907 return 0;
05330448
AL		 3908}
3909
f7575c96 3910static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3911{
f7575c96
AF		 3912 CPUState *cs = CPU(cpu);
3913 struct kvm_run *run = cs->kvm_run;
d362e757 3914
02e51483 3915 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3916 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3917 : TPR_ACCESS_READ);
3918 return 1;
3919}
3920
f17ec444 3921int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3922{
38972938 3923 static const uint8_t int3 = 0xcc;
64bf3f4e 3924
f17ec444
AF		 3925 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3926 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3927 return -EINVAL;
b9bec74b 3928 }
e22a25c9
AL		 3929 return 0;
3930}
3931
f17ec444 3932int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3933{
3934 uint8_t int3;
3935
f17ec444
AF		 3936 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3937 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3938 return -EINVAL;
b9bec74b 3939 }
e22a25c9
AL		 3940 return 0;
3941}
3942
3943static struct {
3944 target_ulong addr;
3945 int len;
3946 int type;
3947} hw_breakpoint[4];
3948
3949static int nb_hw_breakpoint;
3950
3951static int find_hw_breakpoint(target_ulong addr, int len, int type)
3952{
3953 int n;
3954
b9bec74b 3955 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3956 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3957 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3958 return n;
b9bec74b
JK		 3959 }
3960 }
e22a25c9
AL		 3961 return -1;
3962}
3963
3964int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3965 target_ulong len, int type)
3966{
3967 switch (type) {
3968 case GDB_BREAKPOINT_HW:
3969 len = 1;
3970 break;
3971 case GDB_WATCHPOINT_WRITE:
3972 case GDB_WATCHPOINT_ACCESS:
3973 switch (len) {
3974 case 1:
3975 break;
3976 case 2:
3977 case 4:
3978 case 8:
b9bec74b 3979 if (addr & (len - 1)) {
e22a25c9 3980 return -EINVAL;
b9bec74b 3981 }
e22a25c9
AL		 3982 break;
3983 default:
3984 return -EINVAL;
3985 }
3986 break;
3987 default:
3988 return -ENOSYS;
3989 }
3990
b9bec74b 3991 if (nb_hw_breakpoint == 4) {
e22a25c9 3992 return -ENOBUFS;
b9bec74b
JK		 3993 }
3994 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3995 return -EEXIST;
b9bec74b 3996 }
e22a25c9
AL		 3997 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3998 hw_breakpoint[nb_hw_breakpoint].len = len;
3999 hw_breakpoint[nb_hw_breakpoint].type = type;
4000 nb_hw_breakpoint++;
4001
4002 return 0;
4003}
4004
4005int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4006 target_ulong len, int type)
4007{
4008 int n;
4009
4010 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 4011 if (n < 0) {
e22a25c9 4012 return -ENOENT;
b9bec74b 4013 }
e22a25c9
AL		 4014 nb_hw_breakpoint--;
4015 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4016
4017 return 0;
4018}
4019
4020void kvm_arch_remove_all_hw_breakpoints(void)
4021{
4022 nb_hw_breakpoint = 0;
4023}
4024
4025static CPUWatchpoint hw_watchpoint;
4026
a60f24b5 4027static int kvm_handle_debug(X86CPU *cpu,
48405526 4028 struct kvm_debug_exit_arch *arch_info)
e22a25c9 4029{
ed2803da 4030 CPUState *cs = CPU(cpu);
a60f24b5 4031 CPUX86State *env = &cpu->env;
f2574737 4032 int ret = 0;
e22a25c9
AL		 4033 int n;
4034
37936ac7
LA		 4035 if (arch_info->exception == EXCP01_DB) {
4036 if (arch_info->dr6 & DR6_BS) {
ed2803da 4037 if (cs->singlestep_enabled) {
f2574737 4038 ret = EXCP_DEBUG;
b9bec74b 4039 }
e22a25c9 4040 } else {
b9bec74b
JK		 4041 for (n = 0; n < 4; n++) {
4042 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 4043 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4044 case 0x0:
f2574737 4045 ret = EXCP_DEBUG;
e22a25c9
AL		 4046 break;
4047 case 0x1:
f2574737 4048 ret = EXCP_DEBUG;
ff4700b0 4049 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4050 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4051 hw_watchpoint.flags = BP_MEM_WRITE;
4052 break;
4053 case 0x3:
f2574737 4054 ret = EXCP_DEBUG;
ff4700b0 4055 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4056 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4057 hw_watchpoint.flags = BP_MEM_ACCESS;
4058 break;
4059 }
b9bec74b
JK		 4060 }
4061 }
e22a25c9 4062 }
ff4700b0 4063 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 4064 ret = EXCP_DEBUG;
b9bec74b 4065 }
f2574737 4066 if (ret == 0) {
ff4700b0 4067 cpu_synchronize_state(cs);
fd13f23b 4068 assert(env->exception_nr == -1);
b0b1d690 4069
f2574737 4070 /* pass to guest */
fd13f23b
LA		 4071 kvm_queue_exception(env, arch_info->exception,
4072 arch_info->exception == EXCP01_DB,
4073 arch_info->dr6);
48405526 4074 env->has_error_code = 0;
b0b1d690 4075 }
e22a25c9 4076
f2574737 4077 return ret;
e22a25c9
AL		 4078}
4079
20d695a9 4080void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 4081{
4082 const uint8_t type_code[] = {
4083 [GDB_BREAKPOINT_HW] = 0x0,
4084 [GDB_WATCHPOINT_WRITE] = 0x1,
4085 [GDB_WATCHPOINT_ACCESS] = 0x3
4086 };
4087 const uint8_t len_code[] = {
4088 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4089 };
4090 int n;
4091
a60f24b5 4092 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 4093 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 4094 }
e22a25c9
AL		 4095 if (nb_hw_breakpoint > 0) {
4096 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4097 dbg->arch.debugreg[7] = 0x0600;
4098 for (n = 0; n < nb_hw_breakpoint; n++) {
4099 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4100 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4101 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 4102 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 4103 }
4104 }
4105}
4513d923 4106
2a4dac83
JK		 4107static bool host_supports_vmx(void)
4108{
4109 uint32_t ecx, unused;
4110
4111 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4112 return ecx & CPUID_EXT_VMX;
4113}
4114
4115#define VMX_INVALID_GUEST_STATE 0x80000021
4116
20d695a9 4117int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 4118{
20d695a9 4119 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 4120 uint64_t code;
4121 int ret;
4122
4123 switch (run->exit_reason) {
4124 case KVM_EXIT_HLT:
4125 DPRINTF("handle_hlt\n");
4b8523ee 4126 qemu_mutex_lock_iothread();
839b5630 4127 ret = kvm_handle_halt(cpu);
4b8523ee 4128 qemu_mutex_unlock_iothread();
2a4dac83
JK		 4129 break;
4130 case KVM_EXIT_SET_TPR:
4131 ret = 0;
4132 break;
d362e757 4133 case KVM_EXIT_TPR_ACCESS:
4b8523ee 4134 qemu_mutex_lock_iothread();
f7575c96 4135 ret = kvm_handle_tpr_access(cpu);
4b8523ee 4136 qemu_mutex_unlock_iothread();
d362e757 4137 break;
2a4dac83
JK		 4138 case KVM_EXIT_FAIL_ENTRY:
4139 code = run->fail_entry.hardware_entry_failure_reason;
4140 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4141 code);
4142 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4143 fprintf(stderr,
12619721 4144 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 4145 "unrestricted mode\n"
4146 "support, the failure can be most likely due to the guest "
4147 "entering an invalid\n"
4148 "state for Intel VT. For example, the guest maybe running "
4149 "in big real mode\n"
4150 "which is not supported on less recent Intel processors."
4151 "\n\n");
4152 }
4153 ret = -1;
4154 break;
4155 case KVM_EXIT_EXCEPTION:
4156 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4157 run->ex.exception, run->ex.error_code);
4158 ret = -1;
4159 break;
f2574737
JK		 4160 case KVM_EXIT_DEBUG:
4161 DPRINTF("kvm_exit_debug\n");
4b8523ee 4162 qemu_mutex_lock_iothread();
a60f24b5 4163 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 4164 qemu_mutex_unlock_iothread();
f2574737 4165 break;
50efe82c
AS		 4166 case KVM_EXIT_HYPERV:
4167 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4168 break;
15eafc2e
PB		 4169 case KVM_EXIT_IOAPIC_EOI:
4170 ioapic_eoi_broadcast(run->eoi.vector);
4171 ret = 0;
4172 break;
2a4dac83
JK		 4173 default:
4174 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4175 ret = -1;
4176 break;
4177 }
4178
4179 return ret;
4180}
4181
20d695a9 4182bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4183{
20d695a9
AF		 4184 X86CPU *cpu = X86_CPU(cs);
4185 CPUX86State *env = &cpu->env;
4186
dd1750d7 4187 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4188 return !(env->cr[0] & CR0_PE_MASK) ||
4189 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4190}
84b058d7
JK		 4191
4192void kvm_arch_init_irq_routing(KVMState *s)
4193{
4194 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4195 /* If kernel can't do irq routing, interrupt source
4196 * override 0->2 cannot be set up as required by HPET.
4197 * So we have to disable it.
4198 */
4199 no_hpet = 1;
4200 }
cc7e0ddf 4201 /* We know at this point that we're using the in-kernel
614e41bc 4202 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4203 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4204 */
614e41bc 4205 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4206 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4207
4208 if (kvm_irqchip_is_split()) {
4209 int i;
4210
4211 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4212 MSI routes for signaling interrupts to the local apics. */
4213 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4214 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4215 error_report("Could not enable split IRQ mode.");
4216 exit(1);
4217 }
4218 }
4219 }
4220}
4221
4222int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4223{
4224 int ret;
4225 if (machine_kernel_irqchip_split(ms)) {
4226 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4227 if (ret) {
df3c286c 4228 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4229 strerror(-ret));
4230 exit(1);
4231 } else {
4232 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4233 kvm_split_irqchip = true;
4234 return 1;
4235 }
4236 } else {
4237 return 0;
4238 }
84b058d7 4239}
b139bd30
JK		 4240
4241/* Classic KVM device assignment interface. Will remain x86 only. */
4242int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4243 uint32_t flags, uint32_t *dev_id)
4244{
4245 struct kvm_assigned_pci_dev dev_data = {
4246 .segnr = dev_addr->domain,
4247 .busnr = dev_addr->bus,
4248 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4249 .flags = flags,
4250 };
4251 int ret;
4252
4253 dev_data.assigned_dev_id =
4254 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4255
4256 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4257 if (ret < 0) {
4258 return ret;
4259 }
4260
4261 *dev_id = dev_data.assigned_dev_id;
4262
4263 return 0;
4264}
4265
4266int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4267{
4268 struct kvm_assigned_pci_dev dev_data = {
4269 .assigned_dev_id = dev_id,
4270 };
4271
4272 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4273}
4274
4275static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4276 uint32_t irq_type, uint32_t guest_irq)
4277{
4278 struct kvm_assigned_irq assigned_irq = {
4279 .assigned_dev_id = dev_id,
4280 .guest_irq = guest_irq,
4281 .flags = irq_type,
4282 };
4283
4284 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4285 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4286 } else {
4287 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4288 }
4289}
4290
4291int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4292 uint32_t guest_irq)
4293{
4294 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4295 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4296
4297 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4298}
4299
4300int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4301{
4302 struct kvm_assigned_pci_dev dev_data = {
4303 .assigned_dev_id = dev_id,
4304 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4305 };
4306
4307 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4308}
4309
4310static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4311 uint32_t type)
4312{
4313 struct kvm_assigned_irq assigned_irq = {
4314 .assigned_dev_id = dev_id,
4315 .flags = type,
4316 };
4317
4318 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4319}
4320
4321int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4322{
4323 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4324 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4325}
4326
4327int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4328{
4329 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4330 KVM_DEV_IRQ_GUEST_MSI, virq);
4331}
4332
4333int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4334{
4335 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4336 KVM_DEV_IRQ_HOST_MSI);
4337}
4338
4339bool kvm_device_msix_supported(KVMState *s)
4340{
4341 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4342 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4343 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4344}
4345
4346int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4347 uint32_t nr_vectors)
4348{
4349 struct kvm_assigned_msix_nr msix_nr = {
4350 .assigned_dev_id = dev_id,
4351 .entry_nr = nr_vectors,
4352 };
4353
4354 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4355}
4356
4357int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4358 int virq)
4359{
4360 struct kvm_assigned_msix_entry msix_entry = {
4361 .assigned_dev_id = dev_id,
4362 .gsi = virq,
4363 .entry = vector,
4364 };
4365
4366 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4367}
4368
4369int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4370{
4371 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4372 KVM_DEV_IRQ_GUEST_MSIX, 0);
4373}
4374
4375int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4376{
4377 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4378 KVM_DEV_IRQ_HOST_MSIX);
4379}
9e03a040
FB		 4380
4381int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4382 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4383{
8b5ed7df
PX		 4384 X86IOMMUState *iommu = x86_iommu_get_default();
4385
4386 if (iommu) {
4387 int ret;
4388 MSIMessage src, dst;
4389 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4390
0ea1472d
JK		 4391 if (!class->int_remap) {
4392 return 0;
4393 }
4394
8b5ed7df
PX		 4395 src.address = route->u.msi.address_hi;
4396 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4397 src.address |= route->u.msi.address_lo;
4398 src.data = route->u.msi.data;
4399
4400 ret = class->int_remap(iommu, &src, &dst, dev ? \
4401 pci_requester_id(dev) : \
4402 X86_IOMMU_SID_INVALID);
4403 if (ret) {
4404 trace_kvm_x86_fixup_msi_error(route->gsi);
4405 return 1;
4406 }
4407
4408 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4409 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4410 route->u.msi.data = dst.data;
4411 }
4412
9e03a040
FB		 4413 return 0;
4414}
1850b6b7 4415
38d87493
PX		 4416typedef struct MSIRouteEntry MSIRouteEntry;
4417
4418struct MSIRouteEntry {
4419 PCIDevice *dev; /* Device pointer */
4420 int vector; /* MSI/MSIX vector index */
4421 int virq; /* Virtual IRQ index */
4422 QLIST_ENTRY(MSIRouteEntry) list;
4423};
4424
4425/* List of used GSI routes */
4426static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4427 QLIST_HEAD_INITIALIZER(msi_route_list);
4428
e1d4fb2d
PX		 4429static void kvm_update_msi_routes_all(void *private, bool global,
4430 uint32_t index, uint32_t mask)
4431{
a56de056 4432 int cnt = 0, vector;
e1d4fb2d
PX		 4433 MSIRouteEntry *entry;
4434 MSIMessage msg;
fd563564
PX		 4435 PCIDevice *dev;
4436
e1d4fb2d
PX		 4437 /* TODO: explicit route update */
4438 QLIST_FOREACH(entry, &msi_route_list, list) {
4439 cnt++;
a56de056 4440 vector = entry->vector;
fd563564 4441 dev = entry->dev;
a56de056
PX		 4442 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4443 msg = msix_get_message(dev, vector);
4444 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4445 msg = msi_get_message(dev, vector);
4446 } else {
4447 /*
4448 * Either MSI/MSIX is disabled for the device, or the
4449 * specific message was masked out. Skip this one.
4450 */
fd563564
PX		 4451 continue;
4452 }
fd563564 4453 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4454 }
3f1fea0f 4455 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4456 trace_kvm_x86_update_msi_routes(cnt);
4457}
4458
38d87493
PX		 4459int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4460 int vector, PCIDevice *dev)
4461{
e1d4fb2d 4462 static bool notify_list_inited = false;
38d87493
PX		 4463 MSIRouteEntry *entry;
4464
4465 if (!dev) {
4466 /* These are (possibly) IOAPIC routes only used for split
4467 * kernel irqchip mode, while what we are housekeeping are
4468 * PCI devices only. */
4469 return 0;
4470 }
4471
4472 entry = g_new0(MSIRouteEntry, 1);
4473 entry->dev = dev;
4474 entry->vector = vector;
4475 entry->virq = route->gsi;
4476 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4477
4478 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4479
4480 if (!notify_list_inited) {
4481 /* For the first time we do add route, add ourselves into
4482 * IOMMU's IEC notify list if needed. */
4483 X86IOMMUState *iommu = x86_iommu_get_default();
4484 if (iommu) {
4485 x86_iommu_iec_register_notifier(iommu,
4486 kvm_update_msi_routes_all,
4487 NULL);
4488 }
4489 notify_list_inited = true;
4490 }
38d87493
PX		 4491 return 0;
4492}
4493
4494int kvm_arch_release_virq_post(int virq)
4495{
4496 MSIRouteEntry *entry, *next;
4497 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4498 if (entry->virq == virq) {
4499 trace_kvm_x86_remove_msi_route(virq);
4500 QLIST_REMOVE(entry, list);
01960e6d 4501 g_free(entry);
38d87493
PX		 4502 break;
4503 }
4504 }
9e03a040
FB		 4505 return 0;
4506}
1850b6b7
EA		 4507
4508int kvm_arch_msi_data_to_gsi(uint32_t data)
4509{
4510 abort();
4511}
QEMU mirror