]> git.proxmox.com Git - mirror_qemu.git/blame - target/i386/kvm.c
projects / mirror_qemu.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
hw/i386/pc: Convert DPRINTF() to trace events
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
71e8a915 27#include "sysemu/reset.h"
54d31236 28#include "sysemu/runstate.h"
1d31f66b 29#include "kvm_i386.h"
50efe82c 30#include "hyperv.h"
5e953812 31#include "hyperv-proto.h"
50efe82c 32
022c62cb 33#include "exec/gdbstub.h"
1de7afc9 34#include "qemu/host-utils.h"
db725815 35#include "qemu/main-loop.h"
1de7afc9 36#include "qemu/config-file.h"
1c4a55db 37#include "qemu/error-report.h"
0d09e41a
PB		 38#include "hw/i386/pc.h"
39#include "hw/i386/apic.h"
e0723c45
PB		 40#include "hw/i386/apic_internal.h"
41#include "hw/i386/apic-msidef.h"
8b5ed7df 42#include "hw/i386/intel_iommu.h"
e1d4fb2d 43#include "hw/i386/x86-iommu.h"
d6d059ca 44#include "hw/i386/e820_memory_layout.h"
50efe82c 45
a2cb15b0 46#include "hw/pci/pci.h"
15eafc2e 47#include "hw/pci/msi.h"
fd563564 48#include "hw/pci/msix.h"
795c40b8 49#include "migration/blocker.h"
4c663752 50#include "exec/memattrs.h"
8b5ed7df 51#include "trace.h"
05330448
AL		 52
53//#define DEBUG_KVM
54
55#ifdef DEBUG_KVM
8c0d577e 56#define DPRINTF(fmt, ...) \
05330448
AL		 57 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
58#else
8c0d577e 59#define DPRINTF(fmt, ...) \
05330448
AL		 60 do { } while (0)
61#endif
62
1a03675d
GC		 63#define MSR_KVM_WALL_CLOCK 0x11
64#define MSR_KVM_SYSTEM_TIME 0x12
65
d1138251
EH		 66/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
67 * 255 kvm_msr_entry structs */
68#define MSR_BUF_SIZE 4096
d71b62a1 69
94a8d39a
JK		 70const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
71 KVM_CAP_INFO(SET_TSS_ADDR),
72 KVM_CAP_INFO(EXT_CPUID),
73 KVM_CAP_INFO(MP_STATE),
74 KVM_CAP_LAST_INFO
75};
25d2e361 76
c3a3a7d3
JK		 77static bool has_msr_star;
78static bool has_msr_hsave_pa;
c9b8f6b6 79static bool has_msr_tsc_aux;
f28558d3 80static bool has_msr_tsc_adjust;
aa82ba54 81static bool has_msr_tsc_deadline;
df67696e 82static bool has_msr_feature_control;
21e87c46 83static bool has_msr_misc_enable;
fc12d72e 84static bool has_msr_smbase;
79e9ebeb 85static bool has_msr_bndcfgs;
25d2e361 86static int lm_capable_kernel;
7bc3d711 87static bool has_msr_hv_hypercall;
f2a53c9e 88static bool has_msr_hv_crash;
744b8a94 89static bool has_msr_hv_reset;
8c145d7c 90static bool has_msr_hv_vpindex;
e9688fab 91static bool hv_vpindex_settable;
46eb8f98 92static bool has_msr_hv_runtime;
866eea9a 93static bool has_msr_hv_synic;
ff99aa64 94static bool has_msr_hv_stimer;
d72bc7f6 95static bool has_msr_hv_frequencies;
ba6a4fd9 96static bool has_msr_hv_reenlightenment;
18cd2c17 97static bool has_msr_xss;
65087997 98static bool has_msr_umwait;
a33a2cfe 99static bool has_msr_spec_ctrl;
2a9758c5 100static bool has_msr_tsx_ctrl;
cfeea0c0 101static bool has_msr_virt_ssbd;
e13713db 102static bool has_msr_smi_count;
aec5e9c3 103static bool has_msr_arch_capabs;
597360c0 104static bool has_msr_core_capabs;
20a78b02 105static bool has_msr_vmx_vmfunc;
b827df58 106
0b368a10
JD		 107static uint32_t has_architectural_pmu_version;
108static uint32_t num_architectural_pmu_gp_counters;
109static uint32_t num_architectural_pmu_fixed_counters;
0d894367 110
28143b40
TH		 111static int has_xsave;
112static int has_xcrs;
113static int has_pit_state2;
fd13f23b 114static int has_exception_payload;
28143b40 115
87f8b626
AR		 116static bool has_msr_mcg_ext_ctl;
117
494e95e9 118static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 119static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 120
28143b40
TH		 121int kvm_has_pit_state2(void)
122{
123 return has_pit_state2;
124}
125
355023f2
PB		 126bool kvm_has_smm(void)
127{
128 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
129}
130
6053a86f
MT		 131bool kvm_has_adjust_clock_stable(void)
132{
133 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
134
135 return (ret == KVM_CLOCK_TSC_STABLE);
136}
137
79a197ab
LA		 138bool kvm_has_exception_payload(void)
139{
140 return has_exception_payload;
141}
142
1d31f66b
PM		 143bool kvm_allows_irq0_override(void)
144{
145 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
146}
147
fb506e70
RK		 148static bool kvm_x2apic_api_set_flags(uint64_t flags)
149{
150 KVMState *s = KVM_STATE(current_machine->accelerator);
151
152 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
153}
154
e391c009 155#define MEMORIZE(fn, _result) \
2a138ec3 156 ({ \
2a138ec3
RK		 157 static bool _memorized; \
158 \
159 if (_memorized) { \
160 return _result; \
161 } \
162 _memorized = true; \
163 _result = fn; \
164 })
165
e391c009
IM		 166static bool has_x2apic_api;
167
168bool kvm_has_x2apic_api(void)
169{
170 return has_x2apic_api;
171}
172
fb506e70
RK		 173bool kvm_enable_x2apic(void)
174{
2a138ec3
RK		 175 return MEMORIZE(
176 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 177 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
178 has_x2apic_api);
fb506e70
RK		 179}
180
e9688fab
RK		 181bool kvm_hv_vpindex_settable(void)
182{
183 return hv_vpindex_settable;
184}
185
0fd7e098
LL		 186static int kvm_get_tsc(CPUState *cs)
187{
188 X86CPU *cpu = X86_CPU(cs);
189 CPUX86State *env = &cpu->env;
190 struct {
191 struct kvm_msrs info;
192 struct kvm_msr_entry entries[1];
a1834d97 193 } msr_data = {};
0fd7e098
LL		 194 int ret;
195
196 if (env->tsc_valid) {
197 return 0;
198 }
199
1f670a95 200 memset(&msr_data, 0, sizeof(msr_data));
0fd7e098
LL		 201 msr_data.info.nmsrs = 1;
202 msr_data.entries[0].index = MSR_IA32_TSC;
203 env->tsc_valid = !runstate_is_running();
204
205 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
206 if (ret < 0) {
207 return ret;
208 }
209
48e1a45c 210 assert(ret == 1);
0fd7e098
LL		 211 env->tsc = msr_data.entries[0].data;
212 return 0;
213}
214
14e6fe12 215static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 216{
0fd7e098
LL		 217 kvm_get_tsc(cpu);
218}
219
220void kvm_synchronize_all_tsc(void)
221{
222 CPUState *cpu;
223
224 if (kvm_enabled()) {
225 CPU_FOREACH(cpu) {
14e6fe12 226 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 227 }
228 }
229}
230
b827df58
AK		 231static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
232{
233 struct kvm_cpuid2 *cpuid;
234 int r, size;
235
236 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 237 cpuid = g_malloc0(size);
b827df58
AK		 238 cpuid->nent = max;
239 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 240 if (r == 0 && cpuid->nent >= max) {
241 r = -E2BIG;
242 }
b827df58
AK		 243 if (r < 0) {
244 if (r == -E2BIG) {
7267c094 245 g_free(cpuid);
b827df58
AK		 246 return NULL;
247 } else {
248 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
249 strerror(-r));
250 exit(1);
251 }
252 }
253 return cpuid;
254}
255
dd87f8a6
EH		 256/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
257 * for all entries.
258 */
259static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
260{
261 struct kvm_cpuid2 *cpuid;
262 int max = 1;
494e95e9
CP		 263
264 if (cpuid_cache != NULL) {
265 return cpuid_cache;
266 }
dd87f8a6
EH		 267 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
268 max *= 2;
269 }
494e95e9 270 cpuid_cache = cpuid;
dd87f8a6
EH		 271 return cpuid;
272}
273
a443bc34 274static const struct kvm_para_features {
0c31b744
GC		 275 int cap;
276 int feature;
277} para_features[] = {
278 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
279 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
280 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 281 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 282};
283
ba9bc59e 284static int get_para_features(KVMState *s)
0c31b744
GC		 285{
286 int i, features = 0;
287
8e03c100 288 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 289 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 290 features |= (1 << para_features[i].feature);
291 }
292 }
293
294 return features;
295}
0c31b744 296
40e80ee4
EH		 297static bool host_tsx_blacklisted(void)
298{
299 int family, model, stepping;\
300 char vendor[CPUID_VENDOR_SZ + 1];
301
302 host_vendor_fms(vendor, &family, &model, &stepping);
303
304 /* Check if we are running on a Haswell host known to have broken TSX */
305 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
306 (family == 6) &&
307 ((model == 63 && stepping < 4) ||
308 model == 60 || model == 69 || model == 70);
309}
0c31b744 310
829ae2f9
EH		 311/* Returns the value for a specific register on the cpuid entry
312 */
313static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
314{
315 uint32_t ret = 0;
316 switch (reg) {
317 case R_EAX:
318 ret = entry->eax;
319 break;
320 case R_EBX:
321 ret = entry->ebx;
322 break;
323 case R_ECX:
324 ret = entry->ecx;
325 break;
326 case R_EDX:
327 ret = entry->edx;
328 break;
329 }
330 return ret;
331}
332
4fb73f1d
EH		 333/* Find matching entry for function/index on kvm_cpuid2 struct
334 */
335static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
336 uint32_t function,
337 uint32_t index)
338{
339 int i;
340 for (i = 0; i < cpuid->nent; ++i) {
341 if (cpuid->entries[i].function == function &&
342 cpuid->entries[i].index == index) {
343 return &cpuid->entries[i];
344 }
345 }
346 /* not found: */
347 return NULL;
348}
349
ba9bc59e 350uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 351 uint32_t index, int reg)
b827df58
AK		 352{
353 struct kvm_cpuid2 *cpuid;
b827df58
AK		 354 uint32_t ret = 0;
355 uint32_t cpuid_1_edx;
8c723b79 356 bool found = false;
b827df58 357
dd87f8a6 358 cpuid = get_supported_cpuid(s);
b827df58 359
4fb73f1d
EH		 360 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
361 if (entry) {
362 found = true;
363 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 364 }
365
7b46e5ce
EH		 366 /* Fixups for the data returned by KVM, below */
367
c2acb022
EH		 368 if (function == 1 && reg == R_EDX) {
369 /* KVM before 2.6.30 misreports the following features */
370 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 371 } else if (function == 1 && reg == R_ECX) {
372 /* We can set the hypervisor flag, even if KVM does not return it on
373 * GET_SUPPORTED_CPUID
374 */
375 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 376 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
377 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
378 * and the irqchip is in the kernel.
379 */
380 if (kvm_irqchip_in_kernel() &&
381 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
382 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
383 }
41e5e76d
EH		 384
385 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
386 * without the in-kernel irqchip
387 */
388 if (!kvm_irqchip_in_kernel()) {
389 ret &= ~CPUID_EXT_X2APIC;
b827df58 390 }
2266d443
MT		 391
392 if (enable_cpu_pm) {
393 int disable_exits = kvm_check_extension(s,
394 KVM_CAP_X86_DISABLE_EXITS);
395
396 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
397 ret |= CPUID_EXT_MONITOR;
398 }
399 }
28b8e4d0
JK		 400 } else if (function == 6 && reg == R_EAX) {
401 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 402 } else if (function == 7 && index == 0 && reg == R_EBX) {
403 if (host_tsx_blacklisted()) {
404 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
405 }
67192a29
TX		 406 } else if (function == 7 && index == 0 && reg == R_ECX) {
407 if (enable_cpu_pm) {
408 ret |= CPUID_7_0_ECX_WAITPKG;
409 } else {
410 ret &= ~CPUID_7_0_ECX_WAITPKG;
411 }
485b1d25
EH		 412 } else if (function == 7 && index == 0 && reg == R_EDX) {
413 /*
414 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
415 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
416 * returned by KVM_GET_MSR_INDEX_LIST.
417 */
418 if (!has_msr_arch_capabs) {
419 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
420 }
f98bbd83
BM		 421 } else if (function == 0x80000001 && reg == R_ECX) {
422 /*
423 * It's safe to enable TOPOEXT even if it's not returned by
424 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
425 * us to keep CPU models including TOPOEXT runnable on older kernels.
426 */
427 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 428 } else if (function == 0x80000001 && reg == R_EDX) {
429 /* On Intel, kvm returns cpuid according to the Intel spec,
430 * so add missing bits according to the AMD spec:
431 */
432 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
433 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 434 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
435 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
436 * be enabled without the in-kernel irqchip
437 */
438 if (!kvm_irqchip_in_kernel()) {
439 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
440 }
be777326 441 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 442 ret |= 1U << KVM_HINTS_REALTIME;
be777326 443 found = 1;
b827df58
AK		 444 }
445
0c31b744 446 /* fallback for older kernels */
8c723b79 447 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 448 ret = get_para_features(s);
b9bec74b 449 }
0c31b744
GC		 450
451 return ret;
bb0300dc 452}
bb0300dc 453
ede146c2 454uint64_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
f57bceb6
RH		 455{
456 struct {
457 struct kvm_msrs info;
458 struct kvm_msr_entry entries[1];
a1834d97 459 } msr_data = {};
20a78b02
PB		 460 uint64_t value;
461 uint32_t ret, can_be_one, must_be_one;
f57bceb6
RH		 462
463 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
464 return 0;
465 }
466
467 /* Check if requested MSR is supported feature MSR */
468 int i;
469 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
470 if (kvm_feature_msrs->indices[i] == index) {
471 break;
472 }
473 if (i == kvm_feature_msrs->nmsrs) {
474 return 0; /* if the feature MSR is not supported, simply return 0 */
475 }
476
477 msr_data.info.nmsrs = 1;
478 msr_data.entries[0].index = index;
479
480 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
481 if (ret != 1) {
482 error_report("KVM get MSR (index=0x%x) feature failed, %s",
483 index, strerror(-ret));
484 exit(1);
485 }
486
20a78b02
PB		 487 value = msr_data.entries[0].data;
488 switch (index) {
489 case MSR_IA32_VMX_PROCBASED_CTLS2:
048c9516
PB		 490 /* KVM forgot to add these bits for some time, do this ourselves. */
491 if (kvm_arch_get_supported_cpuid(s, 0xD, 1, R_ECX) & CPUID_XSAVE_XSAVES) {
492 value |= (uint64_t)VMX_SECONDARY_EXEC_XSAVES << 32;
493 }
494 if (kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX) & CPUID_EXT_RDRAND) {
495 value |= (uint64_t)VMX_SECONDARY_EXEC_RDRAND_EXITING << 32;
496 }
497 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & CPUID_7_0_EBX_INVPCID) {
498 value |= (uint64_t)VMX_SECONDARY_EXEC_ENABLE_INVPCID << 32;
499 }
500 if (kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX) & CPUID_7_0_EBX_RDSEED) {
501 value |= (uint64_t)VMX_SECONDARY_EXEC_RDSEED_EXITING << 32;
502 }
503 if (kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX) & CPUID_EXT2_RDTSCP) {
504 value |= (uint64_t)VMX_SECONDARY_EXEC_RDTSCP << 32;
505 }
506 /* fall through */
20a78b02
PB		 507 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
508 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
509 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
510 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
511 /*
512 * Return true for bits that can be one, but do not have to be one.
513 * The SDM tells us which bits could have a "must be one" setting,
514 * so we can do the opposite transformation in make_vmx_msr_value.
515 */
516 must_be_one = (uint32_t)value;
517 can_be_one = (uint32_t)(value >> 32);
518 return can_be_one & ~must_be_one;
519
520 default:
521 return value;
522 }
f57bceb6
RH		 523}
524
525
3c85e74f
HY		 526typedef struct HWPoisonPage {
527 ram_addr_t ram_addr;
528 QLIST_ENTRY(HWPoisonPage) list;
529} HWPoisonPage;
530
531static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
532 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
533
534static void kvm_unpoison_all(void *param)
535{
536 HWPoisonPage *page, *next_page;
537
538 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
539 QLIST_REMOVE(page, list);
540 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 541 g_free(page);
3c85e74f
HY		 542 }
543}
544
3c85e74f
HY		 545static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
546{
547 HWPoisonPage *page;
548
549 QLIST_FOREACH(page, &hwpoison_page_list, list) {
550 if (page->ram_addr == ram_addr) {
551 return;
552 }
553 }
ab3ad07f 554 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 555 page->ram_addr = ram_addr;
556 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
557}
558
e7701825
MT		 559static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
560 int *max_banks)
561{
562 int r;
563
14a09518 564 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 565 if (r > 0) {
566 *max_banks = r;
567 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
568 }
569 return -ENOSYS;
570}
571
bee615d4 572static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 573{
87f8b626 574 CPUState *cs = CPU(cpu);
bee615d4 575 CPUX86State *env = &cpu->env;
c34d440a
JK		 576 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
577 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
578 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 579 int flags = 0;
e7701825 580
c34d440a
JK		 581 if (code == BUS_MCEERR_AR) {
582 status |= MCI_STATUS_AR | 0x134;
583 mcg_status |= MCG_STATUS_EIPV;
584 } else {
585 status |= 0xc0;
586 mcg_status |= MCG_STATUS_RIPV;
419fb20a 587 }
87f8b626
AR		 588
589 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
590 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
591 * guest kernel back into env->mcg_ext_ctl.
592 */
593 cpu_synchronize_state(cs);
594 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
595 mcg_status |= MCG_STATUS_LMCE;
596 flags = 0;
597 }
598
8c5cf3b6 599 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 600 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 601}
419fb20a 602
73284563 603static void hardware_memory_error(void *host_addr)
419fb20a 604{
73284563 605 error_report("QEMU got Hardware memory error at addr %p", host_addr);
419fb20a
JK		 606 exit(1);
607}
608
2ae41db2 609void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 610{
20d695a9
AF		 611 X86CPU *cpu = X86_CPU(c);
612 CPUX86State *env = &cpu->env;
419fb20a 613 ram_addr_t ram_addr;
a8170e5e 614 hwaddr paddr;
419fb20a 615
4d39892c
PB		 616 /* If we get an action required MCE, it has been injected by KVM
617 * while the VM was running. An action optional MCE instead should
618 * be coming from the main thread, which qemu_init_sigbus identifies
619 * as the "early kill" thread.
620 */
a16fc07e 621 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 622
20e0ff59 623 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 624 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 625 if (ram_addr != RAM_ADDR_INVALID &&
626 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
627 kvm_hwpoison_page_add(ram_addr);
628 kvm_mce_inject(cpu, paddr, code);
73284563
MS		 629
630 /*
631 * Use different logging severity based on error type.
632 * If there is additional MCE reporting on the hypervisor, QEMU VA
633 * could be another source to identify the PA and MCE details.
634 */
635 if (code == BUS_MCEERR_AR) {
636 error_report("Guest MCE Memory Error at QEMU addr %p and "
637 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
638 addr, paddr, "BUS_MCEERR_AR");
639 } else {
640 warn_report("Guest MCE Memory Error at QEMU addr %p and "
641 "GUEST addr 0x%" HWADDR_PRIx " of type %s injected",
642 addr, paddr, "BUS_MCEERR_AO");
643 }
644
2ae41db2 645 return;
419fb20a 646 }
20e0ff59 647
73284563
MS		 648 if (code == BUS_MCEERR_AO) {
649 warn_report("Hardware memory error at addr %p of type %s "
650 "for memory used by QEMU itself instead of guest system!",
651 addr, "BUS_MCEERR_AO");
652 }
419fb20a 653 }
20e0ff59
PB		 654
655 if (code == BUS_MCEERR_AR) {
73284563 656 hardware_memory_error(addr);
20e0ff59
PB		 657 }
658
659 /* Hope we are lucky for AO MCE */
419fb20a
JK		 660}
661
fd13f23b
LA		 662static void kvm_reset_exception(CPUX86State *env)
663{
664 env->exception_nr = -1;
665 env->exception_pending = 0;
666 env->exception_injected = 0;
667 env->exception_has_payload = false;
668 env->exception_payload = 0;
669}
670
671static void kvm_queue_exception(CPUX86State *env,
672 int32_t exception_nr,
673 uint8_t exception_has_payload,
674 uint64_t exception_payload)
675{
676 assert(env->exception_nr == -1);
677 assert(!env->exception_pending);
678 assert(!env->exception_injected);
679 assert(!env->exception_has_payload);
680
681 env->exception_nr = exception_nr;
682
683 if (has_exception_payload) {
684 env->exception_pending = 1;
685
686 env->exception_has_payload = exception_has_payload;
687 env->exception_payload = exception_payload;
688 } else {
689 env->exception_injected = 1;
690
691 if (exception_nr == EXCP01_DB) {
692 assert(exception_has_payload);
693 env->dr[6] = exception_payload;
694 } else if (exception_nr == EXCP0E_PAGE) {
695 assert(exception_has_payload);
696 env->cr[2] = exception_payload;
697 } else {
698 assert(!exception_has_payload);
699 }
700 }
701}
702
1bc22652 703static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 704{
1bc22652
AF		 705 CPUX86State *env = &cpu->env;
706
fd13f23b 707 if (!kvm_has_vcpu_events() && env->exception_nr == EXCP12_MCHK) {
ab443475
JK		 708 unsigned int bank, bank_num = env->mcg_cap & 0xff;
709 struct kvm_x86_mce mce;
710
fd13f23b 711 kvm_reset_exception(env);
ab443475
JK		 712
713 /*
714 * There must be at least one bank in use if an MCE is pending.
715 * Find it and use its values for the event injection.
716 */
717 for (bank = 0; bank < bank_num; bank++) {
718 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
719 break;
720 }
721 }
722 assert(bank < bank_num);
723
724 mce.bank = bank;
725 mce.status = env->mce_banks[bank * 4 + 1];
726 mce.mcg_status = env->mcg_status;
727 mce.addr = env->mce_banks[bank * 4 + 2];
728 mce.misc = env->mce_banks[bank * 4 + 3];
729
1bc22652 730 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 731 }
ab443475
JK		 732 return 0;
733}
734
1dfb4dd9 735static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 736{
317ac620 737 CPUX86State *env = opaque;
b8cc45d6
GC		 738
739 if (running) {
740 env->tsc_valid = false;
741 }
742}
743
83b17af5 744unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 745{
83b17af5 746 X86CPU *cpu = X86_CPU(cs);
7e72a45c 747 return cpu->apic_id;
b164e48e
EH		 748}
749
92067bf4
IM		 750#ifndef KVM_CPUID_SIGNATURE_NEXT
751#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
752#endif
753
92067bf4
IM		 754static bool hyperv_enabled(X86CPU *cpu)
755{
7bc3d711
PB		 756 CPUState *cs = CPU(cpu);
757 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c 758 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
e48ddcc6 759 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 760}
761
5031283d
HZ		 762static int kvm_arch_set_tsc_khz(CPUState *cs)
763{
764 X86CPU *cpu = X86_CPU(cs);
765 CPUX86State *env = &cpu->env;
766 int r;
767
768 if (!env->tsc_khz) {
769 return 0;
770 }
771
772 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
773 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
774 -ENOTSUP;
775 if (r < 0) {
776 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
777 * TSC frequency doesn't match the one we want.
778 */
779 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
780 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
781 -ENOTSUP;
782 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 783 warn_report("TSC frequency mismatch between "
784 "VM (%" PRId64 " kHz) and host (%d kHz), "
785 "and TSC scaling unavailable",
786 env->tsc_khz, cur_freq);
5031283d
HZ		 787 return r;
788 }
789 }
790
791 return 0;
792}
793
4bb95b82
LP		 794static bool tsc_is_stable_and_known(CPUX86State *env)
795{
796 if (!env->tsc_khz) {
797 return false;
798 }
799 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
800 || env->user_tsc_khz;
801}
802
6760bd20
VK		 803static struct {
804 const char *desc;
805 struct {
806 uint32_t fw;
807 uint32_t bits;
808 } flags[2];
c6861930 809 uint64_t dependencies;
6760bd20
VK		 810} kvm_hyperv_properties[] = {
811 [HYPERV_FEAT_RELAXED] = {
812 .desc = "relaxed timing (hv-relaxed)",
813 .flags = {
814 {.fw = FEAT_HYPERV_EAX,
815 .bits = HV_HYPERCALL_AVAILABLE},
816 {.fw = FEAT_HV_RECOMM_EAX,
817 .bits = HV_RELAXED_TIMING_RECOMMENDED}
818 }
819 },
820 [HYPERV_FEAT_VAPIC] = {
821 .desc = "virtual APIC (hv-vapic)",
822 .flags = {
823 {.fw = FEAT_HYPERV_EAX,
824 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
825 {.fw = FEAT_HV_RECOMM_EAX,
826 .bits = HV_APIC_ACCESS_RECOMMENDED}
827 }
828 },
829 [HYPERV_FEAT_TIME] = {
830 .desc = "clocksources (hv-time)",
831 .flags = {
832 {.fw = FEAT_HYPERV_EAX,
833 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
834 HV_REFERENCE_TSC_AVAILABLE}
835 }
836 },
837 [HYPERV_FEAT_CRASH] = {
838 .desc = "crash MSRs (hv-crash)",
839 .flags = {
840 {.fw = FEAT_HYPERV_EDX,
841 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
842 }
843 },
844 [HYPERV_FEAT_RESET] = {
845 .desc = "reset MSR (hv-reset)",
846 .flags = {
847 {.fw = FEAT_HYPERV_EAX,
848 .bits = HV_RESET_AVAILABLE}
849 }
850 },
851 [HYPERV_FEAT_VPINDEX] = {
852 .desc = "VP_INDEX MSR (hv-vpindex)",
853 .flags = {
854 {.fw = FEAT_HYPERV_EAX,
855 .bits = HV_VP_INDEX_AVAILABLE}
856 }
857 },
858 [HYPERV_FEAT_RUNTIME] = {
859 .desc = "VP_RUNTIME MSR (hv-runtime)",
860 .flags = {
861 {.fw = FEAT_HYPERV_EAX,
862 .bits = HV_VP_RUNTIME_AVAILABLE}
863 }
864 },
865 [HYPERV_FEAT_SYNIC] = {
866 .desc = "synthetic interrupt controller (hv-synic)",
867 .flags = {
868 {.fw = FEAT_HYPERV_EAX,
869 .bits = HV_SYNIC_AVAILABLE}
870 }
871 },
872 [HYPERV_FEAT_STIMER] = {
873 .desc = "synthetic timers (hv-stimer)",
874 .flags = {
875 {.fw = FEAT_HYPERV_EAX,
876 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 877 },
878 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 879 },
880 [HYPERV_FEAT_FREQUENCIES] = {
881 .desc = "frequency MSRs (hv-frequencies)",
882 .flags = {
883 {.fw = FEAT_HYPERV_EAX,
884 .bits = HV_ACCESS_FREQUENCY_MSRS},
885 {.fw = FEAT_HYPERV_EDX,
886 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
887 }
888 },
889 [HYPERV_FEAT_REENLIGHTENMENT] = {
890 .desc = "reenlightenment MSRs (hv-reenlightenment)",
891 .flags = {
892 {.fw = FEAT_HYPERV_EAX,
893 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
894 }
895 },
896 [HYPERV_FEAT_TLBFLUSH] = {
897 .desc = "paravirtualized TLB flush (hv-tlbflush)",
898 .flags = {
899 {.fw = FEAT_HV_RECOMM_EAX,
900 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
901 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 902 },
903 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 904 },
905 [HYPERV_FEAT_EVMCS] = {
906 .desc = "enlightened VMCS (hv-evmcs)",
907 .flags = {
908 {.fw = FEAT_HV_RECOMM_EAX,
909 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 910 },
911 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 912 },
913 [HYPERV_FEAT_IPI] = {
914 .desc = "paravirtualized IPI (hv-ipi)",
915 .flags = {
916 {.fw = FEAT_HV_RECOMM_EAX,
917 .bits = HV_CLUSTER_IPI_RECOMMENDED |
918 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 919 },
920 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 921 },
128531d9
VK		 922 [HYPERV_FEAT_STIMER_DIRECT] = {
923 .desc = "direct mode synthetic timers (hv-stimer-direct)",
924 .flags = {
925 {.fw = FEAT_HYPERV_EDX,
926 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
927 },
928 .dependencies = BIT(HYPERV_FEAT_STIMER)
929 },
6760bd20
VK		 930};
931
932static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
933{
934 struct kvm_cpuid2 *cpuid;
935 int r, size;
936
937 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
938 cpuid = g_malloc0(size);
939 cpuid->nent = max;
940
941 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
942 if (r == 0 && cpuid->nent >= max) {
943 r = -E2BIG;
944 }
945 if (r < 0) {
946 if (r == -E2BIG) {
947 g_free(cpuid);
948 return NULL;
949 } else {
950 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
951 strerror(-r));
952 exit(1);
953 }
954 }
955 return cpuid;
956}
957
958/*
959 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
960 * for all entries.
961 */
962static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
963{
964 struct kvm_cpuid2 *cpuid;
965 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
966
967 /*
968 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
969 * -E2BIG, however, it doesn't report back the right size. Keep increasing
970 * it and re-trying until we succeed.
971 */
972 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
973 max++;
974 }
975 return cpuid;
976}
977
978/*
979 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
980 * leaves from KVM_CAP_HYPERV* and present MSRs data.
981 */
982static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 983{
984 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 985 struct kvm_cpuid2 *cpuid;
986 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
987
988 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
989 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
990 cpuid->nent = 2;
991
992 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
993 entry_feat = &cpuid->entries[0];
994 entry_feat->function = HV_CPUID_FEATURES;
995
996 entry_recomm = &cpuid->entries[1];
997 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
998 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
999
1000 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
1001 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
1002 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
1003 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1004 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
1005 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
1006 }
c35bd19a 1007
6760bd20
VK		 1008 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
1009 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
1010 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 1011 }
6760bd20
VK		 1012
1013 if (has_msr_hv_frequencies) {
1014 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
1015 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 1016 }
6760bd20
VK		 1017
1018 if (has_msr_hv_crash) {
1019 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 1020 }
6760bd20
VK		 1021
1022 if (has_msr_hv_reenlightenment) {
1023 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 1024 }
6760bd20
VK		 1025
1026 if (has_msr_hv_reset) {
1027 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 1028 }
6760bd20
VK		 1029
1030 if (has_msr_hv_vpindex) {
1031 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 1032 }
6760bd20
VK		 1033
1034 if (has_msr_hv_runtime) {
1035 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 1036 }
6760bd20
VK		 1037
1038 if (has_msr_hv_synic) {
1039 unsigned int cap = cpu->hyperv_synic_kvm_only ?
1040 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1041
1042 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
1043 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 1044 }
c35bd19a 1045 }
6760bd20
VK		 1046
1047 if (has_msr_hv_stimer) {
1048 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 1049 }
9b4cf107 1050
6760bd20
VK		 1051 if (kvm_check_extension(cs->kvm_state,
1052 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
1053 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
1054 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
1055 }
c35bd19a 1056
6760bd20
VK		 1057 if (kvm_check_extension(cs->kvm_state,
1058 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
1059 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 1060 }
6760bd20
VK		 1061
1062 if (kvm_check_extension(cs->kvm_state,
1063 KVM_CAP_HYPERV_SEND_IPI) > 0) {
1064 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
1065 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 1066 }
6760bd20
VK		 1067
1068 return cpuid;
1069}
1070
1071static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
1072{
1073 struct kvm_cpuid_entry2 *entry;
1074 uint32_t func;
1075 int reg;
1076
1077 switch (fw) {
1078 case FEAT_HYPERV_EAX:
1079 reg = R_EAX;
1080 func = HV_CPUID_FEATURES;
1081 break;
1082 case FEAT_HYPERV_EDX:
1083 reg = R_EDX;
1084 func = HV_CPUID_FEATURES;
1085 break;
1086 case FEAT_HV_RECOMM_EAX:
1087 reg = R_EAX;
1088 func = HV_CPUID_ENLIGHTMENT_INFO;
1089 break;
1090 default:
1091 return -EINVAL;
a2b107db 1092 }
6760bd20
VK		 1093
1094 entry = cpuid_find_entry(cpuid, func, 0);
1095 if (!entry) {
1096 return -ENOENT;
a2b107db 1097 }
6760bd20
VK		 1098
1099 switch (reg) {
1100 case R_EAX:
1101 *r = entry->eax;
1102 break;
1103 case R_EDX:
1104 *r = entry->edx;
1105 break;
1106 default:
1107 return -EINVAL;
a2b107db 1108 }
6760bd20
VK		 1109
1110 return 0;
1111}
1112
1113static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
1114 int feature)
1115{
1116 X86CPU *cpu = X86_CPU(cs);
1117 CPUX86State *env = &cpu->env;
e48ddcc6 1118 uint32_t r, fw, bits;
c6861930 1119 uint64_t deps;
9dc83cd9 1120 int i, dep_feat;
6760bd20 1121
e48ddcc6 1122 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1123 return 0;
1124 }
1125
c6861930 1126 deps = kvm_hyperv_properties[feature].dependencies;
9dc83cd9
HR		 1127 while (deps) {
1128 dep_feat = ctz64(deps);
c6861930
VK		 1129 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1130 fprintf(stderr,
1131 "Hyper-V %s requires Hyper-V %s\n",
1132 kvm_hyperv_properties[feature].desc,
1133 kvm_hyperv_properties[dep_feat].desc);
1134 return 1;
1135 }
9dc83cd9 1136 deps &= ~(1ull << dep_feat);
c6861930
VK		 1137 }
1138
6760bd20
VK		 1139 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1140 fw = kvm_hyperv_properties[feature].flags[i].fw;
1141 bits = kvm_hyperv_properties[feature].flags[i].bits;
1142
1143 if (!fw) {
1144 continue;
a2b107db 1145 }
6760bd20
VK		 1146
1147 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
e48ddcc6
VK		 1148 if (hyperv_feat_enabled(cpu, feature)) {
1149 fprintf(stderr,
1150 "Hyper-V %s is not supported by kernel\n",
1151 kvm_hyperv_properties[feature].desc);
1152 return 1;
1153 } else {
1154 return 0;
1155 }
6760bd20
VK		 1156 }
1157
1158 env->features[fw] |= bits;
a2b107db 1159 }
6760bd20 1160
e48ddcc6
VK		 1161 if (cpu->hyperv_passthrough) {
1162 cpu->hyperv_features |= BIT(feature);
1163 }
1164
6760bd20
VK		 1165 return 0;
1166}
1167
2344d22e
VK		 1168/*
1169 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1170 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1171 * extentions are enabled.
1172 */
1173static int hyperv_handle_properties(CPUState *cs,
1174 struct kvm_cpuid_entry2 *cpuid_ent)
6760bd20
VK		 1175{
1176 X86CPU *cpu = X86_CPU(cs);
1177 CPUX86State *env = &cpu->env;
1178 struct kvm_cpuid2 *cpuid;
2344d22e
VK		 1179 struct kvm_cpuid_entry2 *c;
1180 uint32_t signature[3];
1181 uint32_t cpuid_i = 0;
e48ddcc6 1182 int r;
6760bd20 1183
2344d22e
VK		 1184 if (!hyperv_enabled(cpu))
1185 return 0;
1186
e48ddcc6
VK		 1187 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1188 cpu->hyperv_passthrough) {
a2b107db
VK		 1189 uint16_t evmcs_version;
1190
e48ddcc6
VK		 1191 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1192 (uintptr_t)&evmcs_version);
1193
1194 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1195 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1196 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1197 return -ENOSYS;
1198 }
e48ddcc6
VK		 1199
1200 if (!r) {
1201 env->features[FEAT_HV_RECOMM_EAX] |=
1202 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1203 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1204 }
a2b107db
VK		 1205 }
1206
6760bd20
VK		 1207 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1208 cpuid = get_supported_hv_cpuid(cs);
1209 } else {
1210 cpuid = get_supported_hv_cpuid_legacy(cs);
1211 }
1212
e48ddcc6
VK		 1213 if (cpu->hyperv_passthrough) {
1214 memcpy(cpuid_ent, &cpuid->entries[0],
1215 cpuid->nent * sizeof(cpuid->entries[0]));
1216
1217 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1218 if (c) {
1219 env->features[FEAT_HYPERV_EAX] = c->eax;
1220 env->features[FEAT_HYPERV_EBX] = c->ebx;
1221 env->features[FEAT_HYPERV_EDX] = c->eax;
1222 }
1223 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1224 if (c) {
1225 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1226
1227 /* hv-spinlocks may have been overriden */
1228 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1229 c->ebx = cpu->hyperv_spinlock_attempts;
1230 }
1231 }
1232 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1233 if (c) {
1234 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1235 }
1236 }
1237
30d6ff66
VK		 1238 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_ON) {
1239 env->features[FEAT_HV_RECOMM_EAX] |= HV_NO_NONARCH_CORESHARING;
1240 } else if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO) {
1241 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1242 if (c) {
1243 env->features[FEAT_HV_RECOMM_EAX] |=
1244 c->eax & HV_NO_NONARCH_CORESHARING;
1245 }
1246 }
1247
6760bd20 1248 /* Features */
e48ddcc6 1249 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
6760bd20
VK		 1250 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1251 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1252 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1253 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1254 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1255 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1256 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1257 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1258 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1259 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1260 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1261 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1262 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
128531d9 1263 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
6760bd20 1264
c6861930 1265 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1266 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1267 !cpu->hyperv_synic_kvm_only &&
1268 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1269 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1270 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1271 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1272 r |= 1;
1273 }
1274
1275 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1276 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1277
2344d22e
VK		 1278 if (r) {
1279 r = -ENOSYS;
1280 goto free;
1281 }
1282
e48ddcc6
VK		 1283 if (cpu->hyperv_passthrough) {
1284 /* We already copied all feature words from KVM as is */
1285 r = cpuid->nent;
1286 goto free;
1287 }
1288
2344d22e
VK		 1289 c = &cpuid_ent[cpuid_i++];
1290 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1291 if (!cpu->hyperv_vendor_id) {
1292 memcpy(signature, "Microsoft Hv", 12);
1293 } else {
1294 size_t len = strlen(cpu->hyperv_vendor_id);
1295
1296 if (len > 12) {
1297 error_report("hv-vendor-id truncated to 12 characters");
1298 len = 12;
1299 }
1300 memset(signature, 0, 12);
1301 memcpy(signature, cpu->hyperv_vendor_id, len);
1302 }
1303 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1304 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1305 c->ebx = signature[0];
1306 c->ecx = signature[1];
1307 c->edx = signature[2];
1308
1309 c = &cpuid_ent[cpuid_i++];
1310 c->function = HV_CPUID_INTERFACE;
1311 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1312 c->eax = signature[0];
1313 c->ebx = 0;
1314 c->ecx = 0;
1315 c->edx = 0;
1316
1317 c = &cpuid_ent[cpuid_i++];
1318 c->function = HV_CPUID_VERSION;
1319 c->eax = 0x00001bbc;
1320 c->ebx = 0x00060001;
1321
1322 c = &cpuid_ent[cpuid_i++];
1323 c->function = HV_CPUID_FEATURES;
1324 c->eax = env->features[FEAT_HYPERV_EAX];
1325 c->ebx = env->features[FEAT_HYPERV_EBX];
1326 c->edx = env->features[FEAT_HYPERV_EDX];
1327
1328 c = &cpuid_ent[cpuid_i++];
1329 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1330 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1331 c->ebx = cpu->hyperv_spinlock_attempts;
1332
1333 c = &cpuid_ent[cpuid_i++];
1334 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1335 c->eax = cpu->hv_max_vps;
1336 c->ebx = 0x40;
1337
1338 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1339 __u32 function;
1340
1341 /* Create zeroed 0x40000006..0x40000009 leaves */
1342 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1343 function < HV_CPUID_NESTED_FEATURES; function++) {
1344 c = &cpuid_ent[cpuid_i++];
1345 c->function = function;
1346 }
1347
1348 c = &cpuid_ent[cpuid_i++];
1349 c->function = HV_CPUID_NESTED_FEATURES;
1350 c->eax = env->features[FEAT_HV_NESTED_EAX];
1351 }
1352 r = cpuid_i;
1353
1354free:
6760bd20
VK		 1355 g_free(cpuid);
1356
2344d22e 1357 return r;
c35bd19a
EY		 1358}
1359
e48ddcc6 1360static Error *hv_passthrough_mig_blocker;
30d6ff66 1361static Error *hv_no_nonarch_cs_mig_blocker;
e48ddcc6 1362
e9688fab
RK		 1363static int hyperv_init_vcpu(X86CPU *cpu)
1364{
729ce7e1 1365 CPUState *cs = CPU(cpu);
e48ddcc6 1366 Error *local_err = NULL;
729ce7e1
RK		 1367 int ret;
1368
e48ddcc6
VK		 1369 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1370 error_setg(&hv_passthrough_mig_blocker,
1371 "'hv-passthrough' CPU flag prevents migration, use explicit"
1372 " set of hv-* flags instead");
1373 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1374 if (local_err) {
1375 error_report_err(local_err);
1376 error_free(hv_passthrough_mig_blocker);
1377 return ret;
1378 }
1379 }
1380
30d6ff66
VK		 1381 if (cpu->hyperv_no_nonarch_cs == ON_OFF_AUTO_AUTO &&
1382 hv_no_nonarch_cs_mig_blocker == NULL) {
1383 error_setg(&hv_no_nonarch_cs_mig_blocker,
1384 "'hv-no-nonarch-coresharing=auto' CPU flag prevents migration"
1385 " use explicit 'hv-no-nonarch-coresharing=on' instead (but"
1386 " make sure SMT is disabled and/or that vCPUs are properly"
1387 " pinned)");
1388 ret = migrate_add_blocker(hv_no_nonarch_cs_mig_blocker, &local_err);
1389 if (local_err) {
1390 error_report_err(local_err);
1391 error_free(hv_no_nonarch_cs_mig_blocker);
1392 return ret;
1393 }
1394 }
1395
2d384d7c 1396 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1397 /*
1398 * the kernel doesn't support setting vp_index; assert that its value
1399 * is in sync
1400 */
e9688fab
RK		 1401 struct {
1402 struct kvm_msrs info;
1403 struct kvm_msr_entry entries[1];
1404 } msr_data = {
1405 .info.nmsrs = 1,
1406 .entries[0].index = HV_X64_MSR_VP_INDEX,
1407 };
1408
729ce7e1 1409 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1410 if (ret < 0) {
1411 return ret;
1412 }
1413 assert(ret == 1);
1414
701189e3 1415 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1416 error_report("kernel's vp_index != QEMU's vp_index");
1417 return -ENXIO;
1418 }
1419 }
1420
2d384d7c 1421 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1422 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1423 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1424 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1425 if (ret < 0) {
1426 error_report("failed to turn on HyperV SynIC in KVM: %s",
1427 strerror(-ret));
1428 return ret;
1429 }
606c34bf 1430
9b4cf107
RK		 1431 if (!cpu->hyperv_synic_kvm_only) {
1432 ret = hyperv_x86_synic_add(cpu);
1433 if (ret < 0) {
1434 error_report("failed to create HyperV SynIC: %s",
1435 strerror(-ret));
1436 return ret;
1437 }
606c34bf 1438 }
729ce7e1
RK		 1439 }
1440
e9688fab
RK		 1441 return 0;
1442}
1443
68bfd0ad
MT		 1444static Error *invtsc_mig_blocker;
1445
f8bb0565 1446#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1447
20d695a9 1448int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1449{
1450 struct {
486bd5a2 1451 struct kvm_cpuid2 cpuid;
f8bb0565 1452 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1453 } cpuid_data;
1454 /*
1455 * The kernel defines these structs with padding fields so there
1456 * should be no extra padding in our cpuid_data struct.
1457 */
1458 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1459 sizeof(struct kvm_cpuid2) +
1460 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1461
20d695a9
AF		 1462 X86CPU *cpu = X86_CPU(cs);
1463 CPUX86State *env = &cpu->env;
486bd5a2 1464 uint32_t limit, i, j, cpuid_i;
a33609ca 1465 uint32_t unused;
bb0300dc 1466 struct kvm_cpuid_entry2 *c;
bb0300dc 1467 uint32_t signature[3];
234cc647 1468 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1469 int max_nested_state_len;
e7429073 1470 int r;
fe44dc91 1471 Error *local_err = NULL;
05330448 1472
ef4cbe14
SW		 1473 memset(&cpuid_data, 0, sizeof(cpuid_data));
1474
05330448
AL		 1475 cpuid_i = 0;
1476
ddb98b5a
LP		 1477 r = kvm_arch_set_tsc_khz(cs);
1478 if (r < 0) {
6b2341ee 1479 return r;
ddb98b5a
LP		 1480 }
1481
1482 /* vcpu's TSC frequency is either specified by user, or following
1483 * the value used by KVM if the former is not present. In the
1484 * latter case, we query it from KVM and record in env->tsc_khz,
1485 * so that vcpu's TSC frequency can be migrated later via this field.
1486 */
1487 if (!env->tsc_khz) {
1488 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1489 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1490 -ENOTSUP;
1491 if (r > 0) {
1492 env->tsc_khz = r;
1493 }
1494 }
1495
bb0300dc 1496 /* Paravirtualization CPUIDs */
2344d22e
VK		 1497 r = hyperv_handle_properties(cs, cpuid_data.entries);
1498 if (r < 0) {
1499 return r;
1500 } else if (r > 0) {
1501 cpuid_i = r;
234cc647 1502 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1503 has_msr_hv_hypercall = true;
eab70139
VR		 1504 }
1505
f522d2ac
AW		 1506 if (cpu->expose_kvm) {
1507 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1508 c = &cpuid_data.entries[cpuid_i++];
1509 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1510 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1511 c->ebx = signature[0];
1512 c->ecx = signature[1];
1513 c->edx = signature[2];
234cc647 1514
f522d2ac
AW		 1515 c = &cpuid_data.entries[cpuid_i++];
1516 c->function = KVM_CPUID_FEATURES | kvm_base;
1517 c->eax = env->features[FEAT_KVM];
be777326 1518 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1519 }
917367aa 1520
a33609ca 1521 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1522
1523 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1524 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1525 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1526 abort();
1527 }
bb0300dc 1528 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1529
1530 switch (i) {
a36b1029
AL		 1531 case 2: {
1532 /* Keep reading function 2 till all the input is received */
1533 int times;
1534
a36b1029 1535 c->function = i;
a33609ca
AL		 1536 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1537 KVM_CPUID_FLAG_STATE_READ_NEXT;
1538 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1539 times = c->eax & 0xff;
a36b1029
AL		 1540
1541 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1542 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1543 fprintf(stderr, "cpuid_data is full, no space for "
1544 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1545 abort();
1546 }
a33609ca 1547 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1548 c->function = i;
a33609ca
AL		 1549 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1550 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1551 }
1552 break;
1553 }
a94e1428
LX		 1554 case 0x1f:
1555 if (env->nr_dies < 2) {
1556 break;
1557 }
486bd5a2
AL		 1558 case 4:
1559 case 0xb:
1560 case 0xd:
1561 for (j = 0; ; j++) {
31e8c696
AP		 1562 if (i == 0xd && j == 64) {
1563 break;
1564 }
a94e1428
LX		 1565
1566 if (i == 0x1f && j == 64) {
1567 break;
1568 }
1569
486bd5a2
AL		 1570 c->function = i;
1571 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1572 c->index = j;
a33609ca 1573 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1574
b9bec74b 1575 if (i == 4 && c->eax == 0) {
486bd5a2 1576 break;
b9bec74b
JK		 1577 }
1578 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1579 break;
b9bec74b 1580 }
a94e1428
LX		 1581 if (i == 0x1f && !(c->ecx & 0xff00)) {
1582 break;
1583 }
b9bec74b 1584 if (i == 0xd && c->eax == 0) {
31e8c696 1585 continue;
b9bec74b 1586 }
f8bb0565
IM		 1587 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1588 fprintf(stderr, "cpuid_data is full, no space for "
1589 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1590 abort();
1591 }
a33609ca 1592 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1593 }
1594 break;
80db491d 1595 case 0x7:
e37a5c7f
CP		 1596 case 0x14: {
1597 uint32_t times;
1598
1599 c->function = i;
1600 c->index = 0;
1601 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1602 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1603 times = c->eax;
1604
1605 for (j = 1; j <= times; ++j) {
1606 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1607 fprintf(stderr, "cpuid_data is full, no space for "
80db491d 1608 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
e37a5c7f
CP		 1609 abort();
1610 }
1611 c = &cpuid_data.entries[cpuid_i++];
1612 c->function = i;
1613 c->index = j;
1614 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1615 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1616 }
1617 break;
1618 }
486bd5a2 1619 default:
486bd5a2 1620 c->function = i;
a33609ca
AL		 1621 c->flags = 0;
1622 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1623 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1624 /*
1625 * KVM already returns all zeroes if a CPUID entry is missing,
1626 * so we can omit it and avoid hitting KVM's 80-entry limit.
1627 */
1628 cpuid_i--;
1629 }
486bd5a2
AL		 1630 break;
1631 }
05330448 1632 }
0d894367
PB		 1633
1634 if (limit >= 0x0a) {
0b368a10 1635 uint32_t eax, edx;
0d894367 1636
0b368a10
JD		 1637 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1638
1639 has_architectural_pmu_version = eax & 0xff;
1640 if (has_architectural_pmu_version > 0) {
1641 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1642
1643 /* Shouldn't be more than 32, since that's the number of bits
1644 * available in EBX to tell us _which_ counters are available.
1645 * Play it safe.
1646 */
0b368a10
JD		 1647 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1648 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1649 }
1650
1651 if (has_architectural_pmu_version > 1) {
1652 num_architectural_pmu_fixed_counters = edx & 0x1f;
1653
1654 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1655 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1656 }
0d894367
PB		 1657 }
1658 }
1659 }
1660
a33609ca 1661 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1662
1663 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1664 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1665 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1666 abort();
1667 }
bb0300dc 1668 c = &cpuid_data.entries[cpuid_i++];
05330448 1669
8f4202fb
BM		 1670 switch (i) {
1671 case 0x8000001d:
1672 /* Query for all AMD cache information leaves */
1673 for (j = 0; ; j++) {
1674 c->function = i;
1675 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1676 c->index = j;
1677 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1678
1679 if (c->eax == 0) {
1680 break;
1681 }
1682 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1683 fprintf(stderr, "cpuid_data is full, no space for "
1684 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1685 abort();
1686 }
1687 c = &cpuid_data.entries[cpuid_i++];
1688 }
1689 break;
1690 default:
1691 c->function = i;
1692 c->flags = 0;
1693 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
af95cafb
EH		 1694 if (!c->eax && !c->ebx && !c->ecx && !c->edx) {
1695 /*
1696 * KVM already returns all zeroes if a CPUID entry is missing,
1697 * so we can omit it and avoid hitting KVM's 80-entry limit.
1698 */
1699 cpuid_i--;
1700 }
8f4202fb
BM		 1701 break;
1702 }
05330448
AL		 1703 }
1704
b3baa152
BW		 1705 /* Call Centaur's CPUID instructions they are supported. */
1706 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1707 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1708
1709 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1710 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1711 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1712 abort();
1713 }
b3baa152
BW		 1714 c = &cpuid_data.entries[cpuid_i++];
1715
1716 c->function = i;
1717 c->flags = 0;
1718 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1719 }
1720 }
1721
05330448
AL		 1722 cpuid_data.cpuid.nent = cpuid_i;
1723
e7701825 1724 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1725 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1726 (CPUID_MCE | CPUID_MCA)
a60f24b5 1727 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1728 uint64_t mcg_cap, unsupported_caps;
e7701825 1729 int banks;
32a42024 1730 int ret;
e7701825 1731
a60f24b5 1732 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1733 if (ret < 0) {
1734 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1735 return ret;
e7701825 1736 }
75d49497 1737
2590f15b 1738 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1739 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1740 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1741 return -ENOTSUP;
75d49497 1742 }
49b69cbf 1743
5120901a
EH		 1744 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1745 if (unsupported_caps) {
87f8b626
AR		 1746 if (unsupported_caps & MCG_LMCE_P) {
1747 error_report("kvm: LMCE not supported");
1748 return -ENOTSUP;
1749 }
3dc6f869
AF		 1750 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1751 unsupported_caps);
5120901a
EH		 1752 }
1753
2590f15b
EH		 1754 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1755 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1756 if (ret < 0) {
1757 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1758 return ret;
1759 }
e7701825 1760 }
e7701825 1761
b8cc45d6
GC		 1762 qemu_add_vm_change_state_handler(cpu_update_state, env);
1763
df67696e
LJ		 1764 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1765 if (c) {
1766 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1767 !!(c->ecx & CPUID_EXT_SMX);
1768 }
1769
87f8b626
AR		 1770 if (env->mcg_cap & MCG_LMCE_P) {
1771 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1772 }
1773
d99569d9
EH		 1774 if (!env->user_tsc_khz) {
1775 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1776 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1777 error_setg(&invtsc_mig_blocker,
1778 "State blocked by non-migratable CPU device"
1779 " (invtsc flag)");
fe44dc91
AA		 1780 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1781 if (local_err) {
1782 error_report_err(local_err);
1783 error_free(invtsc_mig_blocker);
79a197ab 1784 return r;
fe44dc91 1785 }
d99569d9 1786 }
68bfd0ad
MT		 1787 }
1788
9954a158
PDJ		 1789 if (cpu->vmware_cpuid_freq
1790 /* Guests depend on 0x40000000 to detect this feature, so only expose
1791 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1792 && cpu->expose_kvm
1793 && kvm_base == KVM_CPUID_SIGNATURE
1794 /* TSC clock must be stable and known for this feature. */
4bb95b82 1795 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1796
1797 c = &cpuid_data.entries[cpuid_i++];
1798 c->function = KVM_CPUID_SIGNATURE | 0x10;
1799 c->eax = env->tsc_khz;
1800 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1801 * APIC_BUS_CYCLE_NS */
1802 c->ebx = 1000000;
1803 c->ecx = c->edx = 0;
1804
1805 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1806 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1807 }
1808
1809 cpuid_data.cpuid.nent = cpuid_i;
1810
1811 cpuid_data.cpuid.padding = 0;
1812 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1813 if (r) {
1814 goto fail;
1815 }
1816
28143b40 1817 if (has_xsave) {
5b8063c4 1818 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1f670a95 1819 memset(env->xsave_buf, 0, sizeof(struct kvm_xsave));
fabacc0f 1820 }
ebbfef2f
LA		 1821
1822 max_nested_state_len = kvm_max_nested_state_length();
1823 if (max_nested_state_len > 0) {
1824 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
ebbfef2f 1825
1e44f3ab
PB		 1826 if (cpu_has_vmx(env)) {
1827 struct kvm_vmx_nested_state_hdr *vmx_hdr;
ebbfef2f 1828
1e44f3ab
PB		 1829 env->nested_state = g_malloc0(max_nested_state_len);
1830 env->nested_state->size = max_nested_state_len;
ebbfef2f 1831 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1e44f3ab
PB		 1832
1833 vmx_hdr = &env->nested_state->hdr.vmx;
ebbfef2f
LA		 1834 vmx_hdr->vmxon_pa = -1ull;
1835 vmx_hdr->vmcs12_pa = -1ull;
1836 }
1837 }
1838
d71b62a1 1839 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1840
273c515c
PB		 1841 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1842 has_msr_tsc_aux = false;
1843 }
d1ae67f6 1844
e9688fab
RK		 1845 r = hyperv_init_vcpu(cpu);
1846 if (r) {
1847 goto fail;
1848 }
1849
e7429073 1850 return 0;
fe44dc91
AA		 1851
1852 fail:
1853 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 1854
fe44dc91 1855 return r;
05330448
AL		 1856}
1857
b1115c99
LA		 1858int kvm_arch_destroy_vcpu(CPUState *cs)
1859{
1860 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 1861 CPUX86State *env = &cpu->env;
b1115c99
LA		 1862
1863 if (cpu->kvm_msr_buf) {
1864 g_free(cpu->kvm_msr_buf);
1865 cpu->kvm_msr_buf = NULL;
1866 }
1867
ebbfef2f
LA		 1868 if (env->nested_state) {
1869 g_free(env->nested_state);
1870 env->nested_state = NULL;
1871 }
1872
b1115c99
LA		 1873 return 0;
1874}
1875
50a2c6e5 1876void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1877{
20d695a9 1878 CPUX86State *env = &cpu->env;
dd673288 1879
1a5e9d2f 1880 env->xcr0 = 1;
ddced198 1881 if (kvm_irqchip_in_kernel()) {
dd673288 1882 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1883 KVM_MP_STATE_UNINITIALIZED;
1884 } else {
1885 env->mp_state = KVM_MP_STATE_RUNNABLE;
1886 }
689141dd 1887
2d384d7c 1888 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1889 int i;
1890 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1891 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1892 }
606c34bf
RK		 1893
1894 hyperv_x86_synic_reset(cpu);
689141dd 1895 }
d645e132
MT		 1896 /* enabled by default */
1897 env->poll_control_msr = 1;
caa5af0f
JK		 1898}
1899
e0723c45
PB		 1900void kvm_arch_do_init_vcpu(X86CPU *cpu)
1901{
1902 CPUX86State *env = &cpu->env;
1903
1904 /* APs get directly into wait-for-SIPI state. */
1905 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1906 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1907 }
1908}
1909
f57bceb6
RH		 1910static int kvm_get_supported_feature_msrs(KVMState *s)
1911{
1912 int ret = 0;
1913
1914 if (kvm_feature_msrs != NULL) {
1915 return 0;
1916 }
1917
1918 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1919 return 0;
1920 }
1921
1922 struct kvm_msr_list msr_list;
1923
1924 msr_list.nmsrs = 0;
1925 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1926 if (ret < 0 && ret != -E2BIG) {
1927 error_report("Fetch KVM feature MSR list failed: %s",
1928 strerror(-ret));
1929 return ret;
1930 }
1931
1932 assert(msr_list.nmsrs > 0);
1933 kvm_feature_msrs = (struct kvm_msr_list *) \
1934 g_malloc0(sizeof(msr_list) +
1935 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1936
1937 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1938 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1939
1940 if (ret < 0) {
1941 error_report("Fetch KVM feature MSR list failed: %s",
1942 strerror(-ret));
1943 g_free(kvm_feature_msrs);
1944 kvm_feature_msrs = NULL;
1945 return ret;
1946 }
1947
1948 return 0;
1949}
1950
c3a3a7d3 1951static int kvm_get_supported_msrs(KVMState *s)
05330448 1952{
c3a3a7d3 1953 int ret = 0;
de428cea 1954 struct kvm_msr_list msr_list, *kvm_msr_list;
05330448 1955
de428cea
LQ		 1956 /*
1957 * Obtain MSR list from KVM. These are the MSRs that we must
1958 * save/restore.
1959 */
1960 msr_list.nmsrs = 0;
1961 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1962 if (ret < 0 && ret != -E2BIG) {
1963 return ret;
1964 }
1965 /*
1966 * Old kernel modules had a bug and could write beyond the provided
1967 * memory. Allocate at least a safe amount of 1K.
1968 */
1969 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1970 msr_list.nmsrs *
1971 sizeof(msr_list.indices[0])));
05330448 1972
de428cea
LQ		 1973 kvm_msr_list->nmsrs = msr_list.nmsrs;
1974 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1975 if (ret >= 0) {
1976 int i;
05330448 1977
de428cea
LQ		 1978 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1979 switch (kvm_msr_list->indices[i]) {
1980 case MSR_STAR:
1981 has_msr_star = true;
1982 break;
1983 case MSR_VM_HSAVE_PA:
1984 has_msr_hsave_pa = true;
1985 break;
1986 case MSR_TSC_AUX:
1987 has_msr_tsc_aux = true;
1988 break;
1989 case MSR_TSC_ADJUST:
1990 has_msr_tsc_adjust = true;
1991 break;
1992 case MSR_IA32_TSCDEADLINE:
1993 has_msr_tsc_deadline = true;
1994 break;
1995 case MSR_IA32_SMBASE:
1996 has_msr_smbase = true;
1997 break;
1998 case MSR_SMI_COUNT:
1999 has_msr_smi_count = true;
2000 break;
2001 case MSR_IA32_MISC_ENABLE:
2002 has_msr_misc_enable = true;
2003 break;
2004 case MSR_IA32_BNDCFGS:
2005 has_msr_bndcfgs = true;
2006 break;
2007 case MSR_IA32_XSS:
2008 has_msr_xss = true;
2009 break;
65087997
TX		 2010 case MSR_IA32_UMWAIT_CONTROL:
2011 has_msr_umwait = true;
2012 break;
de428cea
LQ		 2013 case HV_X64_MSR_CRASH_CTL:
2014 has_msr_hv_crash = true;
2015 break;
2016 case HV_X64_MSR_RESET:
2017 has_msr_hv_reset = true;
2018 break;
2019 case HV_X64_MSR_VP_INDEX:
2020 has_msr_hv_vpindex = true;
2021 break;
2022 case HV_X64_MSR_VP_RUNTIME:
2023 has_msr_hv_runtime = true;
2024 break;
2025 case HV_X64_MSR_SCONTROL:
2026 has_msr_hv_synic = true;
2027 break;
2028 case HV_X64_MSR_STIMER0_CONFIG:
2029 has_msr_hv_stimer = true;
2030 break;
2031 case HV_X64_MSR_TSC_FREQUENCY:
2032 has_msr_hv_frequencies = true;
2033 break;
2034 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2035 has_msr_hv_reenlightenment = true;
2036 break;
2037 case MSR_IA32_SPEC_CTRL:
2038 has_msr_spec_ctrl = true;
2039 break;
2a9758c5
PB		 2040 case MSR_IA32_TSX_CTRL:
2041 has_msr_tsx_ctrl = true;
2042 break;
de428cea
LQ		 2043 case MSR_VIRT_SSBD:
2044 has_msr_virt_ssbd = true;
2045 break;
2046 case MSR_IA32_ARCH_CAPABILITIES:
2047 has_msr_arch_capabs = true;
2048 break;
2049 case MSR_IA32_CORE_CAPABILITY:
2050 has_msr_core_capabs = true;
2051 break;
20a78b02
PB		 2052 case MSR_IA32_VMX_VMFUNC:
2053 has_msr_vmx_vmfunc = true;
2054 break;
05330448
AL		 2055 }
2056 }
05330448
AL		 2057 }
2058
de428cea
LQ		 2059 g_free(kvm_msr_list);
2060
c3a3a7d3 2061 return ret;
05330448
AL		 2062}
2063
6410848b
PB		 2064static Notifier smram_machine_done;
2065static KVMMemoryListener smram_listener;
2066static AddressSpace smram_address_space;
2067static MemoryRegion smram_as_root;
2068static MemoryRegion smram_as_mem;
2069
2070static void register_smram_listener(Notifier *n, void *unused)
2071{
2072 MemoryRegion *smram =
2073 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2074
2075 /* Outer container... */
2076 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
2077 memory_region_set_enabled(&smram_as_root, true);
2078
2079 /* ... with two regions inside: normal system memory with low
2080 * priority, and...
2081 */
2082 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
2083 get_system_memory(), 0, ~0ull);
2084 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
2085 memory_region_set_enabled(&smram_as_mem, true);
2086
2087 if (smram) {
2088 /* ... SMRAM with higher priority */
2089 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
2090 memory_region_set_enabled(smram, true);
2091 }
2092
2093 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
2094 kvm_memory_listener_register(kvm_state, &smram_listener,
2095 &smram_address_space, 1);
2096}
2097
b16565b3 2098int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 2099{
11076198 2100 uint64_t identity_base = 0xfffbc000;
39d6960a 2101 uint64_t shadow_mem;
20420430 2102 int ret;
25d2e361 2103 struct utsname utsname;
20420430 2104
28143b40 2105 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 2106 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 2107 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 2108
e9688fab
RK		 2109 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
2110
fd13f23b
LA		 2111 has_exception_payload = kvm_check_extension(s, KVM_CAP_EXCEPTION_PAYLOAD);
2112 if (has_exception_payload) {
2113 ret = kvm_vm_enable_cap(s, KVM_CAP_EXCEPTION_PAYLOAD, 0, true);
2114 if (ret < 0) {
2115 error_report("kvm: Failed to enable exception payload cap: %s",
2116 strerror(-ret));
2117 return ret;
2118 }
2119 }
2120
c3a3a7d3 2121 ret = kvm_get_supported_msrs(s);
20420430 2122 if (ret < 0) {
20420430
SY		 2123 return ret;
2124 }
25d2e361 2125
f57bceb6
RH		 2126 kvm_get_supported_feature_msrs(s);
2127
25d2e361
MT		 2128 uname(&utsname);
2129 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
2130
4c5b10b7 2131 /*
11076198
JK		 2132 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
2133 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
2134 * Since these must be part of guest physical memory, we need to allocate
2135 * them, both by setting their start addresses in the kernel and by
2136 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
2137 *
2138 * Older KVM versions may not support setting the identity map base. In
2139 * that case we need to stick with the default, i.e. a 256K maximum BIOS
2140 * size.
4c5b10b7 2141 */
11076198
JK		 2142 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
2143 /* Allows up to 16M BIOSes. */
2144 identity_base = 0xfeffc000;
2145
2146 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
2147 if (ret < 0) {
2148 return ret;
2149 }
4c5b10b7 2150 }
e56ff191 2151
11076198
JK		 2152 /* Set TSS base one page after EPT identity map. */
2153 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 2154 if (ret < 0) {
2155 return ret;
2156 }
2157
11076198
JK		 2158 /* Tell fw_cfg to notify the BIOS to reserve the range. */
2159 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 2160 if (ret < 0) {
11076198 2161 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 2162 return ret;
2163 }
3c85e74f 2164 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 2165
23b0898e 2166 shadow_mem = object_property_get_int(OBJECT(s), "kvm-shadow-mem", &error_abort);
36ad0e94
MA		 2167 if (shadow_mem != -1) {
2168 shadow_mem /= 4096;
2169 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
2170 if (ret < 0) {
2171 return ret;
39d6960a
JK		 2172 }
2173 }
6410848b 2174
d870cfde 2175 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
ed9e923c 2176 x86_machine_is_smm_enabled(X86_MACHINE(ms))) {
6410848b
PB		 2177 smram_machine_done.notify = register_smram_listener;
2178 qemu_add_machine_init_done_notifier(&smram_machine_done);
2179 }
6f131f13
MT		 2180
2181 if (enable_cpu_pm) {
2182 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2183 int ret;
2184
2185/* Work around for kernel header with a typo. TODO: fix header and drop. */
2186#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2187#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2188#endif
2189 if (disable_exits) {
2190 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2191 KVM_X86_DISABLE_EXITS_HLT |
d38d201f
WL		 2192 KVM_X86_DISABLE_EXITS_PAUSE |
2193 KVM_X86_DISABLE_EXITS_CSTATE);
6f131f13
MT		 2194 }
2195
2196 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2197 disable_exits);
2198 if (ret < 0) {
2199 error_report("kvm: guest stopping CPU not supported: %s",
2200 strerror(-ret));
2201 }
2202 }
2203
11076198 2204 return 0;
05330448 2205}
b9bec74b 2206
05330448
AL		 2207static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2208{
2209 lhs->selector = rhs->selector;
2210 lhs->base = rhs->base;
2211 lhs->limit = rhs->limit;
2212 lhs->type = 3;
2213 lhs->present = 1;
2214 lhs->dpl = 3;
2215 lhs->db = 0;
2216 lhs->s = 1;
2217 lhs->l = 0;
2218 lhs->g = 0;
2219 lhs->avl = 0;
2220 lhs->unusable = 0;
2221}
2222
2223static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2224{
2225 unsigned flags = rhs->flags;
2226 lhs->selector = rhs->selector;
2227 lhs->base = rhs->base;
2228 lhs->limit = rhs->limit;
2229 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2230 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2231 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2232 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2233 lhs->s = (flags & DESC_S_MASK) != 0;
2234 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2235 lhs->g = (flags & DESC_G_MASK) != 0;
2236 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2237 lhs->unusable = !lhs->present;
7e680753 2238 lhs->padding = 0;
05330448
AL		 2239}
2240
2241static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2242{
2243 lhs->selector = rhs->selector;
2244 lhs->base = rhs->base;
2245 lhs->limit = rhs->limit;
d45fc087
RP		 2246 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2247 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2248 (rhs->dpl << DESC_DPL_SHIFT) |
2249 (rhs->db << DESC_B_SHIFT) |
2250 (rhs->s * DESC_S_MASK) |
2251 (rhs->l << DESC_L_SHIFT) |
2252 (rhs->g * DESC_G_MASK) |
2253 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2254}
2255
2256static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2257{
b9bec74b 2258 if (set) {
05330448 2259 *kvm_reg = *qemu_reg;
b9bec74b 2260 } else {
05330448 2261 *qemu_reg = *kvm_reg;
b9bec74b 2262 }
05330448
AL		 2263}
2264
1bc22652 2265static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2266{
1bc22652 2267 CPUX86State *env = &cpu->env;
05330448
AL		 2268 struct kvm_regs regs;
2269 int ret = 0;
2270
2271 if (!set) {
1bc22652 2272 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2273 if (ret < 0) {
05330448 2274 return ret;
b9bec74b 2275 }
05330448
AL		 2276 }
2277
2278 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2279 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2280 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2281 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2282 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2283 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2284 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2285 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2286#ifdef TARGET_X86_64
2287 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2288 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2289 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2290 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2291 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2292 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2293 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2294 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2295#endif
2296
2297 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2298 kvm_getput_reg(&regs.rip, &env->eip, set);
2299
b9bec74b 2300 if (set) {
1bc22652 2301 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2302 }
05330448
AL		 2303
2304 return ret;
2305}
2306
1bc22652 2307static int kvm_put_fpu(X86CPU *cpu)
05330448 2308{
1bc22652 2309 CPUX86State *env = &cpu->env;
05330448
AL		 2310 struct kvm_fpu fpu;
2311 int i;
2312
2313 memset(&fpu, 0, sizeof fpu);
2314 fpu.fsw = env->fpus & ~(7 << 11);
2315 fpu.fsw |= (env->fpstt & 7) << 11;
2316 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2317 fpu.last_opcode = env->fpop;
2318 fpu.last_ip = env->fpip;
2319 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2320 for (i = 0; i < 8; ++i) {
2321 fpu.ftwx |= (!env->fptags[i]) << i;
2322 }
05330448 2323 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2324 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2325 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2326 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2327 }
05330448
AL		 2328 fpu.mxcsr = env->mxcsr;
2329
1bc22652 2330 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2331}
2332
6b42494b
JK		 2333#define XSAVE_FCW_FSW 0
2334#define XSAVE_FTW_FOP 1
f1665b21
SY		 2335#define XSAVE_CWD_RIP 2
2336#define XSAVE_CWD_RDP 4
2337#define XSAVE_MXCSR 6
2338#define XSAVE_ST_SPACE 8
2339#define XSAVE_XMM_SPACE 40
2340#define XSAVE_XSTATE_BV 128
2341#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2342#define XSAVE_BNDREGS 240
2343#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2344#define XSAVE_OPMASK 272
2345#define XSAVE_ZMM_Hi256 288
2346#define XSAVE_Hi16_ZMM 416
f74eefe0 2347#define XSAVE_PKRU 672
f1665b21 2348
b503717d 2349#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2350 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2351
2352#define ASSERT_OFFSET(word_offset, field) \
2353 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2354 offsetof(X86XSaveArea, field))
2355
2356ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2357ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2358ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2359ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2360ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2361ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2362ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2363ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2364ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2365ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2366ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2367ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2368ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2369ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2370ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2371
1bc22652 2372static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2373{
1bc22652 2374 CPUX86State *env = &cpu->env;
5b8063c4 2375 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2376
28143b40 2377 if (!has_xsave) {
1bc22652 2378 return kvm_put_fpu(cpu);
b9bec74b 2379 }
86a57621 2380 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2381
9be38598 2382 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2383}
2384
1bc22652 2385static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2386{
1bc22652 2387 CPUX86State *env = &cpu->env;
bdfc8480 2388 struct kvm_xcrs xcrs = {};
f1665b21 2389
28143b40 2390 if (!has_xcrs) {
f1665b21 2391 return 0;
b9bec74b 2392 }
f1665b21
SY		 2393
2394 xcrs.nr_xcrs = 1;
2395 xcrs.flags = 0;
2396 xcrs.xcrs[0].xcr = 0;
2397 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2398 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2399}
2400
1bc22652 2401static int kvm_put_sregs(X86CPU *cpu)
05330448 2402{
1bc22652 2403 CPUX86State *env = &cpu->env;
05330448
AL		 2404 struct kvm_sregs sregs;
2405
0e607a80
JK		 2406 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2407 if (env->interrupt_injected >= 0) {
2408 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2409 (uint64_t)1 << (env->interrupt_injected % 64);
2410 }
05330448
AL		 2411
2412 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2413 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2414 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2415 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2416 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2417 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2418 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2419 } else {
b9bec74b
JK		 2420 set_seg(&sregs.cs, &env->segs[R_CS]);
2421 set_seg(&sregs.ds, &env->segs[R_DS]);
2422 set_seg(&sregs.es, &env->segs[R_ES]);
2423 set_seg(&sregs.fs, &env->segs[R_FS]);
2424 set_seg(&sregs.gs, &env->segs[R_GS]);
2425 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2426 }
2427
2428 set_seg(&sregs.tr, &env->tr);
2429 set_seg(&sregs.ldt, &env->ldt);
2430
2431 sregs.idt.limit = env->idt.limit;
2432 sregs.idt.base = env->idt.base;
7e680753 2433 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2434 sregs.gdt.limit = env->gdt.limit;
2435 sregs.gdt.base = env->gdt.base;
7e680753 2436 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2437
2438 sregs.cr0 = env->cr[0];
2439 sregs.cr2 = env->cr[2];
2440 sregs.cr3 = env->cr[3];
2441 sregs.cr4 = env->cr[4];
2442
02e51483
CF		 2443 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2444 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2445
2446 sregs.efer = env->efer;
2447
1bc22652 2448 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2449}
2450
d71b62a1
EH		 2451static void kvm_msr_buf_reset(X86CPU *cpu)
2452{
2453 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2454}
2455
9c600a84
EH		 2456static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2457{
2458 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2459 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2460 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2461
2462 assert((void *)(entry + 1) <= limit);
2463
1abc2cae
EH		 2464 entry->index = index;
2465 entry->reserved = 0;
2466 entry->data = value;
9c600a84
EH		 2467 msrs->nmsrs++;
2468}
2469
73e1b8f2
PB		 2470static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2471{
2472 kvm_msr_buf_reset(cpu);
2473 kvm_msr_entry_add(cpu, index, value);
2474
2475 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2476}
2477
f8d9ccf8
DDAG		 2478void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2479{
2480 int ret;
2481
2482 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2483 assert(ret == 1);
2484}
2485
7477cd38
MT		 2486static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2487{
2488 CPUX86State *env = &cpu->env;
48e1a45c 2489 int ret;
7477cd38
MT		 2490
2491 if (!has_msr_tsc_deadline) {
2492 return 0;
2493 }
2494
73e1b8f2 2495 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2496 if (ret < 0) {
2497 return ret;
2498 }
2499
2500 assert(ret == 1);
2501 return 0;
7477cd38
MT		 2502}
2503
6bdf863d
JK		 2504/*
2505 * Provide a separate write service for the feature control MSR in order to
2506 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2507 * before writing any other state because forcibly leaving nested mode
2508 * invalidates the VCPU state.
2509 */
2510static int kvm_put_msr_feature_control(X86CPU *cpu)
2511{
48e1a45c
PB		 2512 int ret;
2513
2514 if (!has_msr_feature_control) {
2515 return 0;
2516 }
6bdf863d 2517
73e1b8f2
PB		 2518 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2519 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2520 if (ret < 0) {
2521 return ret;
2522 }
2523
2524 assert(ret == 1);
2525 return 0;
6bdf863d
JK		 2526}
2527
20a78b02
PB		 2528static uint64_t make_vmx_msr_value(uint32_t index, uint32_t features)
2529{
2530 uint32_t default1, can_be_one, can_be_zero;
2531 uint32_t must_be_one;
2532
2533 switch (index) {
2534 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2535 default1 = 0x00000016;
2536 break;
2537 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2538 default1 = 0x0401e172;
2539 break;
2540 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2541 default1 = 0x000011ff;
2542 break;
2543 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2544 default1 = 0x00036dff;
2545 break;
2546 case MSR_IA32_VMX_PROCBASED_CTLS2:
2547 default1 = 0;
2548 break;
2549 default:
2550 abort();
2551 }
2552
2553 /* If a feature bit is set, the control can be either set or clear.
2554 * Otherwise the value is limited to either 0 or 1 by default1.
2555 */
2556 can_be_one = features | default1;
2557 can_be_zero = features | ~default1;
2558 must_be_one = ~can_be_zero;
2559
2560 /*
2561 * Bit 0:31 -> 0 if the control bit can be zero (i.e. 1 if it must be one).
2562 * Bit 32:63 -> 1 if the control bit can be one.
2563 */
2564 return must_be_one | (((uint64_t)can_be_one) << 32);
2565}
2566
2567#define VMCS12_MAX_FIELD_INDEX (0x17)
2568
2569static void kvm_msr_entry_add_vmx(X86CPU *cpu, FeatureWordArray f)
2570{
2571 uint64_t kvm_vmx_basic =
2572 kvm_arch_get_supported_msr_feature(kvm_state,
2573 MSR_IA32_VMX_BASIC);
26051882
YZ		 2574
2575 if (!kvm_vmx_basic) {
2576 /* If the kernel doesn't support VMX feature (kvm_intel.nested=0),
2577 * then kvm_vmx_basic will be 0 and KVM_SET_MSR will fail.
2578 */
2579 return;
2580 }
2581
20a78b02
PB		 2582 uint64_t kvm_vmx_misc =
2583 kvm_arch_get_supported_msr_feature(kvm_state,
2584 MSR_IA32_VMX_MISC);
2585 uint64_t kvm_vmx_ept_vpid =
2586 kvm_arch_get_supported_msr_feature(kvm_state,
2587 MSR_IA32_VMX_EPT_VPID_CAP);
2588
2589 /*
2590 * If the guest is 64-bit, a value of 1 is allowed for the host address
2591 * space size vmexit control.
2592 */
2593 uint64_t fixed_vmx_exit = f[FEAT_8000_0001_EDX] & CPUID_EXT2_LM
2594 ? (uint64_t)VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE << 32 : 0;
2595
2596 /*
2597 * Bits 0-30, 32-44 and 50-53 come from the host. KVM should
2598 * not change them for backwards compatibility.
2599 */
2600 uint64_t fixed_vmx_basic = kvm_vmx_basic &
2601 (MSR_VMX_BASIC_VMCS_REVISION_MASK |
2602 MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK |
2603 MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK);
2604
2605 /*
2606 * Same for bits 0-4 and 25-27. Bits 16-24 (CR3 target count) can
2607 * change in the future but are always zero for now, clear them to be
2608 * future proof. Bits 32-63 in theory could change, though KVM does
2609 * not support dual-monitor treatment and probably never will; mask
2610 * them out as well.
2611 */
2612 uint64_t fixed_vmx_misc = kvm_vmx_misc &
2613 (MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK |
2614 MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK);
2615
2616 /*
2617 * EPT memory types should not change either, so we do not bother
2618 * adding features for them.
2619 */
2620 uint64_t fixed_vmx_ept_mask =
2621 (f[FEAT_VMX_SECONDARY_CTLS] & VMX_SECONDARY_EXEC_ENABLE_EPT ?
2622 MSR_VMX_EPT_UC | MSR_VMX_EPT_WB : 0);
2623 uint64_t fixed_vmx_ept_vpid = kvm_vmx_ept_vpid & fixed_vmx_ept_mask;
2624
2625 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2626 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PROCBASED_CTLS,
2627 f[FEAT_VMX_PROCBASED_CTLS]));
2628 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2629 make_vmx_msr_value(MSR_IA32_VMX_TRUE_PINBASED_CTLS,
2630 f[FEAT_VMX_PINBASED_CTLS]));
2631 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_EXIT_CTLS,
2632 make_vmx_msr_value(MSR_IA32_VMX_TRUE_EXIT_CTLS,
2633 f[FEAT_VMX_EXIT_CTLS]) | fixed_vmx_exit);
2634 kvm_msr_entry_add(cpu, MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2635 make_vmx_msr_value(MSR_IA32_VMX_TRUE_ENTRY_CTLS,
2636 f[FEAT_VMX_ENTRY_CTLS]));
2637 kvm_msr_entry_add(cpu, MSR_IA32_VMX_PROCBASED_CTLS2,
2638 make_vmx_msr_value(MSR_IA32_VMX_PROCBASED_CTLS2,
2639 f[FEAT_VMX_SECONDARY_CTLS]));
2640 kvm_msr_entry_add(cpu, MSR_IA32_VMX_EPT_VPID_CAP,
2641 f[FEAT_VMX_EPT_VPID_CAPS] | fixed_vmx_ept_vpid);
2642 kvm_msr_entry_add(cpu, MSR_IA32_VMX_BASIC,
2643 f[FEAT_VMX_BASIC] | fixed_vmx_basic);
2644 kvm_msr_entry_add(cpu, MSR_IA32_VMX_MISC,
2645 f[FEAT_VMX_MISC] | fixed_vmx_misc);
2646 if (has_msr_vmx_vmfunc) {
2647 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMFUNC, f[FEAT_VMX_VMFUNC]);
2648 }
2649
2650 /*
2651 * Just to be safe, write these with constant values. The CRn_FIXED1
2652 * MSRs are generated by KVM based on the vCPU's CPUID.
2653 */
2654 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR0_FIXED0,
2655 CR0_PE_MASK | CR0_PG_MASK | CR0_NE_MASK);
2656 kvm_msr_entry_add(cpu, MSR_IA32_VMX_CR4_FIXED0,
2657 CR4_VMXE_MASK);
2658 kvm_msr_entry_add(cpu, MSR_IA32_VMX_VMCS_ENUM,
2659 VMCS12_MAX_FIELD_INDEX << 1);
2660}
2661
1bc22652 2662static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2663{
1bc22652 2664 CPUX86State *env = &cpu->env;
9c600a84 2665 int i;
48e1a45c 2666 int ret;
05330448 2667
d71b62a1
EH		 2668 kvm_msr_buf_reset(cpu);
2669
9c600a84
EH		 2670 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2671 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2672 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2673 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2674 if (has_msr_star) {
9c600a84 2675 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2676 }
c3a3a7d3 2677 if (has_msr_hsave_pa) {
9c600a84 2678 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2679 }
c9b8f6b6 2680 if (has_msr_tsc_aux) {
9c600a84 2681 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2682 }
f28558d3 2683 if (has_msr_tsc_adjust) {
9c600a84 2684 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2685 }
21e87c46 2686 if (has_msr_misc_enable) {
9c600a84 2687 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2688 env->msr_ia32_misc_enable);
2689 }
fc12d72e 2690 if (has_msr_smbase) {
9c600a84 2691 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2692 }
e13713db
LA		 2693 if (has_msr_smi_count) {
2694 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2695 }
439d19f2 2696 if (has_msr_bndcfgs) {
9c600a84 2697 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2698 }
18cd2c17 2699 if (has_msr_xss) {
9c600a84 2700 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2701 }
65087997
TX		 2702 if (has_msr_umwait) {
2703 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
2704 }
a33a2cfe
PB		 2705 if (has_msr_spec_ctrl) {
2706 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2707 }
2a9758c5
PB		 2708 if (has_msr_tsx_ctrl) {
2709 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
2710 }
cfeea0c0
KRW		 2711 if (has_msr_virt_ssbd) {
2712 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2713 }
2714
05330448 2715#ifdef TARGET_X86_64
25d2e361 2716 if (lm_capable_kernel) {
9c600a84
EH		 2717 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2718 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2719 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2720 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2721 }
05330448 2722#endif
a33a2cfe 2723
d86f9636 2724 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2725 if (has_msr_arch_capabs) {
2726 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2727 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2728 }
2729
597360c0
XL		 2730 if (has_msr_core_capabs) {
2731 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2732 env->features[FEAT_CORE_CAPABILITY]);
2733 }
2734
ff5c186b 2735 /*
0d894367
PB		 2736 * The following MSRs have side effects on the guest or are too heavy
2737 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2738 */
2739 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2740 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2741 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2742 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2743 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2744 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2745 }
55c911a5 2746 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2747 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2748 }
55c911a5 2749 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2750 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2751 }
d645e132
MT		 2752
2753 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
2754 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, env->poll_control_msr);
2755 }
2756
0b368a10
JD		 2757 if (has_architectural_pmu_version > 0) {
2758 if (has_architectural_pmu_version > 1) {
2759 /* Stop the counter. */
2760 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2761 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2762 }
0d894367
PB		 2763
2764 /* Set the counter values. */
0b368a10 2765 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2766 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2767 env->msr_fixed_counters[i]);
2768 }
0b368a10 2769 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2770 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2771 env->msr_gp_counters[i]);
9c600a84 2772 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2773 env->msr_gp_evtsel[i]);
2774 }
0b368a10
JD		 2775 if (has_architectural_pmu_version > 1) {
2776 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2777 env->msr_global_status);
2778 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2779 env->msr_global_ovf_ctrl);
2780
2781 /* Now start the PMU. */
2782 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2783 env->msr_fixed_ctr_ctrl);
2784 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2785 env->msr_global_ctrl);
2786 }
0d894367 2787 }
da1cc323
EY		 2788 /*
2789 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2790 * only sync them to KVM on the first cpu
2791 */
2792 if (current_cpu == first_cpu) {
2793 if (has_msr_hv_hypercall) {
2794 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2795 env->msr_hv_guest_os_id);
2796 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2797 env->msr_hv_hypercall);
2798 }
2d384d7c 2799 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2800 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2801 env->msr_hv_tsc);
2802 }
2d384d7c 2803 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2804 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2805 env->msr_hv_reenlightenment_control);
2806 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2807 env->msr_hv_tsc_emulation_control);
2808 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2809 env->msr_hv_tsc_emulation_status);
2810 }
eab70139 2811 }
2d384d7c 2812 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2813 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2814 env->msr_hv_vapic);
eab70139 2815 }
f2a53c9e
AS		 2816 if (has_msr_hv_crash) {
2817 int j;
2818
5e953812 2819 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2820 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2821 env->msr_hv_crash_params[j]);
2822
5e953812 2823 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2824 }
46eb8f98 2825 if (has_msr_hv_runtime) {
9c600a84 2826 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2827 }
2d384d7c
VK		 2828 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2829 && hv_vpindex_settable) {
701189e3
RK		 2830 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2831 hyperv_vp_index(CPU(cpu)));
e9688fab 2832 }
2d384d7c 2833 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2834 int j;
2835
09df29b6
RK		 2836 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2837
9c600a84 2838 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2839 env->msr_hv_synic_control);
9c600a84 2840 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2841 env->msr_hv_synic_evt_page);
9c600a84 2842 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2843 env->msr_hv_synic_msg_page);
2844
2845 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2846 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2847 env->msr_hv_synic_sint[j]);
2848 }
2849 }
ff99aa64
AS		 2850 if (has_msr_hv_stimer) {
2851 int j;
2852
2853 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2854 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2855 env->msr_hv_stimer_config[j]);
2856 }
2857
2858 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2859 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2860 env->msr_hv_stimer_count[j]);
2861 }
2862 }
1eabfce6 2863 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2864 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2865
9c600a84
EH		 2866 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2867 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2868 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2869 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2870 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2871 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2872 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2873 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2874 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2875 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2876 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2877 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2878 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2879 /* The CPU GPs if we write to a bit above the physical limit of
2880 * the host CPU (and KVM emulates that)
2881 */
2882 uint64_t mask = env->mtrr_var[i].mask;
2883 mask &= phys_mask;
2884
9c600a84
EH		 2885 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2886 env->mtrr_var[i].base);
112dad69 2887 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2888 }
2889 }
b77146e9
CP		 2890 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2891 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2892 0x14, 1, R_EAX) & 0x7;
2893
2894 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2895 env->msr_rtit_ctrl);
2896 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2897 env->msr_rtit_status);
2898 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2899 env->msr_rtit_output_base);
2900 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2901 env->msr_rtit_output_mask);
2902 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2903 env->msr_rtit_cr3_match);
2904 for (i = 0; i < addr_num; i++) {
2905 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2906 env->msr_rtit_addrs[i]);
2907 }
2908 }
6bdf863d
JK		 2909
2910 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2911 * kvm_put_msr_feature_control. */
20a78b02
PB		 2912
2913 /*
2914 * Older kernels do not include VMX MSRs in KVM_GET_MSR_INDEX_LIST, but
2915 * all kernels with MSR features should have them.
2916 */
2917 if (kvm_feature_msrs && cpu_has_vmx(env)) {
2918 kvm_msr_entry_add_vmx(cpu, env->features);
2919 }
ea643051 2920 }
20a78b02 2921
57780495 2922 if (env->mcg_cap) {
d8da8574 2923 int i;
b9bec74b 2924
9c600a84
EH		 2925 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2926 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2927 if (has_msr_mcg_ext_ctl) {
2928 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2929 }
c34d440a 2930 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2931 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2932 }
2933 }
1a03675d 2934
d71b62a1 2935 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2936 if (ret < 0) {
2937 return ret;
2938 }
05330448 2939
c70b11d1
EH		 2940 if (ret < cpu->kvm_msr_buf->nmsrs) {
2941 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2942 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2943 (uint32_t)e->index, (uint64_t)e->data);
2944 }
2945
9c600a84 2946 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2947 return 0;
05330448
AL		 2948}
2949
2950
1bc22652 2951static int kvm_get_fpu(X86CPU *cpu)
05330448 2952{
1bc22652 2953 CPUX86State *env = &cpu->env;
05330448
AL		 2954 struct kvm_fpu fpu;
2955 int i, ret;
2956
1bc22652 2957 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2958 if (ret < 0) {
05330448 2959 return ret;
b9bec74b 2960 }
05330448
AL		 2961
2962 env->fpstt = (fpu.fsw >> 11) & 7;
2963 env->fpus = fpu.fsw;
2964 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2965 env->fpop = fpu.last_opcode;
2966 env->fpip = fpu.last_ip;
2967 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2968 for (i = 0; i < 8; ++i) {
2969 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2970 }
05330448 2971 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2972 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2973 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2974 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2975 }
05330448
AL		 2976 env->mxcsr = fpu.mxcsr;
2977
2978 return 0;
2979}
2980
1bc22652 2981static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2982{
1bc22652 2983 CPUX86State *env = &cpu->env;
5b8063c4 2984 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2985 int ret;
f1665b21 2986
28143b40 2987 if (!has_xsave) {
1bc22652 2988 return kvm_get_fpu(cpu);
b9bec74b 2989 }
f1665b21 2990
1bc22652 2991 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2992 if (ret < 0) {
f1665b21 2993 return ret;
0f53994f 2994 }
86a57621 2995 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2996
f1665b21 2997 return 0;
f1665b21
SY		 2998}
2999
1bc22652 3000static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 3001{
1bc22652 3002 CPUX86State *env = &cpu->env;
f1665b21
SY		 3003 int i, ret;
3004 struct kvm_xcrs xcrs;
3005
28143b40 3006 if (!has_xcrs) {
f1665b21 3007 return 0;
b9bec74b 3008 }
f1665b21 3009
1bc22652 3010 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 3011 if (ret < 0) {
f1665b21 3012 return ret;
b9bec74b 3013 }
f1665b21 3014
b9bec74b 3015 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 3016 /* Only support xcr0 now */
0fd53fec
PB		 3017 if (xcrs.xcrs[i].xcr == 0) {
3018 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 3019 break;
3020 }
b9bec74b 3021 }
f1665b21 3022 return 0;
f1665b21
SY		 3023}
3024
1bc22652 3025static int kvm_get_sregs(X86CPU *cpu)
05330448 3026{
1bc22652 3027 CPUX86State *env = &cpu->env;
05330448 3028 struct kvm_sregs sregs;
0e607a80 3029 int bit, i, ret;
05330448 3030
1bc22652 3031 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 3032 if (ret < 0) {
05330448 3033 return ret;
b9bec74b 3034 }
05330448 3035
0e607a80
JK		 3036 /* There can only be one pending IRQ set in the bitmap at a time, so try
3037 to find it and save its number instead (-1 for none). */
3038 env->interrupt_injected = -1;
3039 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
3040 if (sregs.interrupt_bitmap[i]) {
3041 bit = ctz64(sregs.interrupt_bitmap[i]);
3042 env->interrupt_injected = i * 64 + bit;
3043 break;
3044 }
3045 }
05330448
AL		 3046
3047 get_seg(&env->segs[R_CS], &sregs.cs);
3048 get_seg(&env->segs[R_DS], &sregs.ds);
3049 get_seg(&env->segs[R_ES], &sregs.es);
3050 get_seg(&env->segs[R_FS], &sregs.fs);
3051 get_seg(&env->segs[R_GS], &sregs.gs);
3052 get_seg(&env->segs[R_SS], &sregs.ss);
3053
3054 get_seg(&env->tr, &sregs.tr);
3055 get_seg(&env->ldt, &sregs.ldt);
3056
3057 env->idt.limit = sregs.idt.limit;
3058 env->idt.base = sregs.idt.base;
3059 env->gdt.limit = sregs.gdt.limit;
3060 env->gdt.base = sregs.gdt.base;
3061
3062 env->cr[0] = sregs.cr0;
3063 env->cr[2] = sregs.cr2;
3064 env->cr[3] = sregs.cr3;
3065 env->cr[4] = sregs.cr4;
3066
05330448 3067 env->efer = sregs.efer;
cce47516
JK		 3068
3069 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 3070 x86_update_hflags(env);
05330448
AL		 3071
3072 return 0;
3073}
3074
1bc22652 3075static int kvm_get_msrs(X86CPU *cpu)
05330448 3076{
1bc22652 3077 CPUX86State *env = &cpu->env;
d71b62a1 3078 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 3079 int ret, i;
fcc35e7c 3080 uint64_t mtrr_top_bits;
05330448 3081
d71b62a1
EH		 3082 kvm_msr_buf_reset(cpu);
3083
9c600a84
EH		 3084 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
3085 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
3086 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
3087 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 3088 if (has_msr_star) {
9c600a84 3089 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 3090 }
c3a3a7d3 3091 if (has_msr_hsave_pa) {
9c600a84 3092 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 3093 }
c9b8f6b6 3094 if (has_msr_tsc_aux) {
9c600a84 3095 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 3096 }
f28558d3 3097 if (has_msr_tsc_adjust) {
9c600a84 3098 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 3099 }
aa82ba54 3100 if (has_msr_tsc_deadline) {
9c600a84 3101 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 3102 }
21e87c46 3103 if (has_msr_misc_enable) {
9c600a84 3104 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 3105 }
fc12d72e 3106 if (has_msr_smbase) {
9c600a84 3107 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 3108 }
e13713db
LA		 3109 if (has_msr_smi_count) {
3110 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
3111 }
df67696e 3112 if (has_msr_feature_control) {
9c600a84 3113 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 3114 }
79e9ebeb 3115 if (has_msr_bndcfgs) {
9c600a84 3116 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 3117 }
18cd2c17 3118 if (has_msr_xss) {
9c600a84 3119 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 3120 }
65087997
TX		 3121 if (has_msr_umwait) {
3122 kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
3123 }
a33a2cfe
PB		 3124 if (has_msr_spec_ctrl) {
3125 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
3126 }
2a9758c5
PB		 3127 if (has_msr_tsx_ctrl) {
3128 kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
3129 }
cfeea0c0
KRW		 3130 if (has_msr_virt_ssbd) {
3131 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
3132 }
b8cc45d6 3133 if (!env->tsc_valid) {
9c600a84 3134 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 3135 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 3136 }
3137
05330448 3138#ifdef TARGET_X86_64
25d2e361 3139 if (lm_capable_kernel) {
9c600a84
EH		 3140 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
3141 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
3142 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
3143 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 3144 }
05330448 3145#endif
9c600a84
EH		 3146 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
3147 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 3148 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 3149 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 3150 }
55c911a5 3151 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 3152 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 3153 }
55c911a5 3154 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 3155 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 3156 }
d645e132
MT		 3157 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_POLL_CONTROL)) {
3158 kvm_msr_entry_add(cpu, MSR_KVM_POLL_CONTROL, 1);
3159 }
0b368a10
JD		 3160 if (has_architectural_pmu_version > 0) {
3161 if (has_architectural_pmu_version > 1) {
3162 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
3163 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
3164 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
3165 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
3166 }
3167 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 3168 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 3169 }
0b368a10 3170 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 3171 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
3172 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 3173 }
3174 }
1a03675d 3175
57780495 3176 if (env->mcg_cap) {
9c600a84
EH		 3177 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
3178 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 3179 if (has_msr_mcg_ext_ctl) {
3180 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
3181 }
b9bec74b 3182 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 3183 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 3184 }
57780495 3185 }
57780495 3186
1c90ef26 3187 if (has_msr_hv_hypercall) {
9c600a84
EH		 3188 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
3189 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 3190 }
2d384d7c 3191 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 3192 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 3193 }
2d384d7c 3194 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 3195 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 3196 }
2d384d7c 3197 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 3198 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
3199 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
3200 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
3201 }
f2a53c9e
AS		 3202 if (has_msr_hv_crash) {
3203 int j;
3204
5e953812 3205 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 3206 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 3207 }
3208 }
46eb8f98 3209 if (has_msr_hv_runtime) {
9c600a84 3210 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 3211 }
2d384d7c 3212 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 3213 uint32_t msr;
3214
9c600a84 3215 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 3216 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
3217 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 3218 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 3219 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 3220 }
3221 }
ff99aa64
AS		 3222 if (has_msr_hv_stimer) {
3223 uint32_t msr;
3224
3225 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
3226 msr++) {
9c600a84 3227 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 3228 }
3229 }
1eabfce6 3230 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 3231 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
3232 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
3233 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
3234 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
3235 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
3236 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
3237 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
3238 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
3239 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
3240 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
3241 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
3242 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 3243 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 3244 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
3245 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 3246 }
3247 }
5ef68987 3248
b77146e9
CP		 3249 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
3250 int addr_num =
3251 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
3252
3253 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
3254 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
3255 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
3256 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
3257 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
3258 for (i = 0; i < addr_num; i++) {
3259 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
3260 }
3261 }
3262
d71b62a1 3263 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 3264 if (ret < 0) {
05330448 3265 return ret;
b9bec74b 3266 }
05330448 3267
c70b11d1
EH		 3268 if (ret < cpu->kvm_msr_buf->nmsrs) {
3269 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
3270 error_report("error: failed to get MSR 0x%" PRIx32,
3271 (uint32_t)e->index);
3272 }
3273
9c600a84 3274 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 3275 /*
3276 * MTRR masks: Each mask consists of 5 parts
3277 * a 10..0: must be zero
3278 * b 11 : valid bit
3279 * c n-1.12: actual mask bits
3280 * d 51..n: reserved must be zero
3281 * e 63.52: reserved must be zero
3282 *
3283 * 'n' is the number of physical bits supported by the CPU and is
3284 * apparently always <= 52. We know our 'n' but don't know what
3285 * the destinations 'n' is; it might be smaller, in which case
3286 * it masks (c) on loading. It might be larger, in which case
3287 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
3288 * we're migrating to.
3289 */
3290
3291 if (cpu->fill_mtrr_mask) {
3292 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
3293 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
3294 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
3295 } else {
3296 mtrr_top_bits = 0;
3297 }
3298
05330448 3299 for (i = 0; i < ret; i++) {
0d894367
PB		 3300 uint32_t index = msrs[i].index;
3301 switch (index) {
05330448
AL		 3302 case MSR_IA32_SYSENTER_CS:
3303 env->sysenter_cs = msrs[i].data;
3304 break;
3305 case MSR_IA32_SYSENTER_ESP:
3306 env->sysenter_esp = msrs[i].data;
3307 break;
3308 case MSR_IA32_SYSENTER_EIP:
3309 env->sysenter_eip = msrs[i].data;
3310 break;
0c03266a
JK		 3311 case MSR_PAT:
3312 env->pat = msrs[i].data;
3313 break;
05330448
AL		 3314 case MSR_STAR:
3315 env->star = msrs[i].data;
3316 break;
3317#ifdef TARGET_X86_64
3318 case MSR_CSTAR:
3319 env->cstar = msrs[i].data;
3320 break;
3321 case MSR_KERNELGSBASE:
3322 env->kernelgsbase = msrs[i].data;
3323 break;
3324 case MSR_FMASK:
3325 env->fmask = msrs[i].data;
3326 break;
3327 case MSR_LSTAR:
3328 env->lstar = msrs[i].data;
3329 break;
3330#endif
3331 case MSR_IA32_TSC:
3332 env->tsc = msrs[i].data;
3333 break;
c9b8f6b6
AS		 3334 case MSR_TSC_AUX:
3335 env->tsc_aux = msrs[i].data;
3336 break;
f28558d3
WA		 3337 case MSR_TSC_ADJUST:
3338 env->tsc_adjust = msrs[i].data;
3339 break;
aa82ba54
LJ		 3340 case MSR_IA32_TSCDEADLINE:
3341 env->tsc_deadline = msrs[i].data;
3342 break;
aa851e36
MT		 3343 case MSR_VM_HSAVE_PA:
3344 env->vm_hsave = msrs[i].data;
3345 break;
1a03675d
GC		 3346 case MSR_KVM_SYSTEM_TIME:
3347 env->system_time_msr = msrs[i].data;
3348 break;
3349 case MSR_KVM_WALL_CLOCK:
3350 env->wall_clock_msr = msrs[i].data;
3351 break;
57780495
MT		 3352 case MSR_MCG_STATUS:
3353 env->mcg_status = msrs[i].data;
3354 break;
3355 case MSR_MCG_CTL:
3356 env->mcg_ctl = msrs[i].data;
3357 break;
87f8b626
AR		 3358 case MSR_MCG_EXT_CTL:
3359 env->mcg_ext_ctl = msrs[i].data;
3360 break;
21e87c46
AK		 3361 case MSR_IA32_MISC_ENABLE:
3362 env->msr_ia32_misc_enable = msrs[i].data;
3363 break;
fc12d72e
PB		 3364 case MSR_IA32_SMBASE:
3365 env->smbase = msrs[i].data;
3366 break;
e13713db
LA		 3367 case MSR_SMI_COUNT:
3368 env->msr_smi_count = msrs[i].data;
3369 break;
0779caeb
ACL		 3370 case MSR_IA32_FEATURE_CONTROL:
3371 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3372 break;
79e9ebeb
LJ		 3373 case MSR_IA32_BNDCFGS:
3374 env->msr_bndcfgs = msrs[i].data;
3375 break;
18cd2c17
WL		 3376 case MSR_IA32_XSS:
3377 env->xss = msrs[i].data;
3378 break;
65087997
TX		 3379 case MSR_IA32_UMWAIT_CONTROL:
3380 env->umwait = msrs[i].data;
3381 break;
57780495 3382 default:
57780495
MT		 3383 if (msrs[i].index >= MSR_MC0_CTL &&
3384 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3385 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3386 }
d8da8574 3387 break;
f6584ee2
GN		 3388 case MSR_KVM_ASYNC_PF_EN:
3389 env->async_pf_en_msr = msrs[i].data;
3390 break;
bc9a839d
MT		 3391 case MSR_KVM_PV_EOI_EN:
3392 env->pv_eoi_en_msr = msrs[i].data;
3393 break;
917367aa
MT		 3394 case MSR_KVM_STEAL_TIME:
3395 env->steal_time_msr = msrs[i].data;
3396 break;
d645e132
MT		 3397 case MSR_KVM_POLL_CONTROL: {
3398 env->poll_control_msr = msrs[i].data;
3399 break;
3400 }
0d894367
PB		 3401 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3402 env->msr_fixed_ctr_ctrl = msrs[i].data;
3403 break;
3404 case MSR_CORE_PERF_GLOBAL_CTRL:
3405 env->msr_global_ctrl = msrs[i].data;
3406 break;
3407 case MSR_CORE_PERF_GLOBAL_STATUS:
3408 env->msr_global_status = msrs[i].data;
3409 break;
3410 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3411 env->msr_global_ovf_ctrl = msrs[i].data;
3412 break;
3413 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3414 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3415 break;
3416 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3417 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3418 break;
3419 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3420 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3421 break;
1c90ef26
VR		 3422 case HV_X64_MSR_HYPERCALL:
3423 env->msr_hv_hypercall = msrs[i].data;
3424 break;
3425 case HV_X64_MSR_GUEST_OS_ID:
3426 env->msr_hv_guest_os_id = msrs[i].data;
3427 break;
5ef68987
VR		 3428 case HV_X64_MSR_APIC_ASSIST_PAGE:
3429 env->msr_hv_vapic = msrs[i].data;
3430 break;
48a5f3bc
VR		 3431 case HV_X64_MSR_REFERENCE_TSC:
3432 env->msr_hv_tsc = msrs[i].data;
3433 break;
f2a53c9e
AS		 3434 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3435 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3436 break;
46eb8f98
AS		 3437 case HV_X64_MSR_VP_RUNTIME:
3438 env->msr_hv_runtime = msrs[i].data;
3439 break;
866eea9a
AS		 3440 case HV_X64_MSR_SCONTROL:
3441 env->msr_hv_synic_control = msrs[i].data;
3442 break;
866eea9a
AS		 3443 case HV_X64_MSR_SIEFP:
3444 env->msr_hv_synic_evt_page = msrs[i].data;
3445 break;
3446 case HV_X64_MSR_SIMP:
3447 env->msr_hv_synic_msg_page = msrs[i].data;
3448 break;
3449 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3450 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3451 break;
3452 case HV_X64_MSR_STIMER0_CONFIG:
3453 case HV_X64_MSR_STIMER1_CONFIG:
3454 case HV_X64_MSR_STIMER2_CONFIG:
3455 case HV_X64_MSR_STIMER3_CONFIG:
3456 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3457 msrs[i].data;
3458 break;
3459 case HV_X64_MSR_STIMER0_COUNT:
3460 case HV_X64_MSR_STIMER1_COUNT:
3461 case HV_X64_MSR_STIMER2_COUNT:
3462 case HV_X64_MSR_STIMER3_COUNT:
3463 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3464 msrs[i].data;
866eea9a 3465 break;
ba6a4fd9
VK		 3466 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3467 env->msr_hv_reenlightenment_control = msrs[i].data;
3468 break;
3469 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3470 env->msr_hv_tsc_emulation_control = msrs[i].data;
3471 break;
3472 case HV_X64_MSR_TSC_EMULATION_STATUS:
3473 env->msr_hv_tsc_emulation_status = msrs[i].data;
3474 break;
d1ae67f6
AW		 3475 case MSR_MTRRdefType:
3476 env->mtrr_deftype = msrs[i].data;
3477 break;
3478 case MSR_MTRRfix64K_00000:
3479 env->mtrr_fixed[0] = msrs[i].data;
3480 break;
3481 case MSR_MTRRfix16K_80000:
3482 env->mtrr_fixed[1] = msrs[i].data;
3483 break;
3484 case MSR_MTRRfix16K_A0000:
3485 env->mtrr_fixed[2] = msrs[i].data;
3486 break;
3487 case MSR_MTRRfix4K_C0000:
3488 env->mtrr_fixed[3] = msrs[i].data;
3489 break;
3490 case MSR_MTRRfix4K_C8000:
3491 env->mtrr_fixed[4] = msrs[i].data;
3492 break;
3493 case MSR_MTRRfix4K_D0000:
3494 env->mtrr_fixed[5] = msrs[i].data;
3495 break;
3496 case MSR_MTRRfix4K_D8000:
3497 env->mtrr_fixed[6] = msrs[i].data;
3498 break;
3499 case MSR_MTRRfix4K_E0000:
3500 env->mtrr_fixed[7] = msrs[i].data;
3501 break;
3502 case MSR_MTRRfix4K_E8000:
3503 env->mtrr_fixed[8] = msrs[i].data;
3504 break;
3505 case MSR_MTRRfix4K_F0000:
3506 env->mtrr_fixed[9] = msrs[i].data;
3507 break;
3508 case MSR_MTRRfix4K_F8000:
3509 env->mtrr_fixed[10] = msrs[i].data;
3510 break;
3511 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3512 if (index & 1) {
fcc35e7c
DDAG		 3513 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3514 mtrr_top_bits;
d1ae67f6
AW		 3515 } else {
3516 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3517 }
3518 break;
a33a2cfe
PB		 3519 case MSR_IA32_SPEC_CTRL:
3520 env->spec_ctrl = msrs[i].data;
3521 break;
2a9758c5
PB		 3522 case MSR_IA32_TSX_CTRL:
3523 env->tsx_ctrl = msrs[i].data;
3524 break;
cfeea0c0
KRW		 3525 case MSR_VIRT_SSBD:
3526 env->virt_ssbd = msrs[i].data;
3527 break;
b77146e9
CP		 3528 case MSR_IA32_RTIT_CTL:
3529 env->msr_rtit_ctrl = msrs[i].data;
3530 break;
3531 case MSR_IA32_RTIT_STATUS:
3532 env->msr_rtit_status = msrs[i].data;
3533 break;
3534 case MSR_IA32_RTIT_OUTPUT_BASE:
3535 env->msr_rtit_output_base = msrs[i].data;
3536 break;
3537 case MSR_IA32_RTIT_OUTPUT_MASK:
3538 env->msr_rtit_output_mask = msrs[i].data;
3539 break;
3540 case MSR_IA32_RTIT_CR3_MATCH:
3541 env->msr_rtit_cr3_match = msrs[i].data;
3542 break;
3543 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3544 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3545 break;
05330448
AL		 3546 }
3547 }
3548
3549 return 0;
3550}
3551
1bc22652 3552static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3553{
1bc22652 3554 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3555
1bc22652 3556 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3557}
3558
23d02d9b 3559static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3560{
259186a7 3561 CPUState *cs = CPU(cpu);
23d02d9b 3562 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3563 struct kvm_mp_state mp_state;
3564 int ret;
3565
259186a7 3566 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3567 if (ret < 0) {
3568 return ret;
3569 }
3570 env->mp_state = mp_state.mp_state;
c14750e8 3571 if (kvm_irqchip_in_kernel()) {
259186a7 3572 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3573 }
9bdbe550
HB		 3574 return 0;
3575}
3576
1bc22652 3577static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3578{
02e51483 3579 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3580 struct kvm_lapic_state kapic;
3581 int ret;
3582
3d4b2649 3583 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3584 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3585 if (ret < 0) {
3586 return ret;
3587 }
3588
3589 kvm_get_apic_state(apic, &kapic);
3590 }
3591 return 0;
3592}
3593
1bc22652 3594static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3595{
fc12d72e 3596 CPUState *cs = CPU(cpu);
1bc22652 3597 CPUX86State *env = &cpu->env;
076796f8 3598 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3599
3600 if (!kvm_has_vcpu_events()) {
3601 return 0;
3602 }
3603
fd13f23b
LA		 3604 events.flags = 0;
3605
3606 if (has_exception_payload) {
3607 events.flags |= KVM_VCPUEVENT_VALID_PAYLOAD;
3608 events.exception.pending = env->exception_pending;
3609 events.exception_has_payload = env->exception_has_payload;
3610 events.exception_payload = env->exception_payload;
3611 }
3612 events.exception.nr = env->exception_nr;
3613 events.exception.injected = env->exception_injected;
a0fb002c
JK		 3614 events.exception.has_error_code = env->has_error_code;
3615 events.exception.error_code = env->error_code;
3616
3617 events.interrupt.injected = (env->interrupt_injected >= 0);
3618 events.interrupt.nr = env->interrupt_injected;
3619 events.interrupt.soft = env->soft_interrupt;
3620
3621 events.nmi.injected = env->nmi_injected;
3622 events.nmi.pending = env->nmi_pending;
3623 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3624
3625 events.sipi_vector = env->sipi_vector;
3626
fc12d72e
PB		 3627 if (has_msr_smbase) {
3628 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3629 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3630 if (kvm_irqchip_in_kernel()) {
3631 /* As soon as these are moved to the kernel, remove them
3632 * from cs->interrupt_request.
3633 */
3634 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3635 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3636 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3637 } else {
3638 /* Keep these in cs->interrupt_request. */
3639 events.smi.pending = 0;
3640 events.smi.latched_init = 0;
3641 }
fc3a1fd7
DDAG		 3642 /* Stop SMI delivery on old machine types to avoid a reboot
3643 * on an inward migration of an old VM.
3644 */
3645 if (!cpu->kvm_no_smi_migration) {
3646 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3647 }
fc12d72e
PB		 3648 }
3649
ea643051 3650 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3651 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3652 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3653 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3654 }
ea643051 3655 }
aee028b9 3656
1bc22652 3657 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3658}
3659
1bc22652 3660static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3661{
1bc22652 3662 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3663 struct kvm_vcpu_events events;
3664 int ret;
3665
3666 if (!kvm_has_vcpu_events()) {
3667 return 0;
3668 }
3669
fc12d72e 3670 memset(&events, 0, sizeof(events));
1bc22652 3671 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3672 if (ret < 0) {
3673 return ret;
3674 }
fd13f23b
LA		 3675
3676 if (events.flags & KVM_VCPUEVENT_VALID_PAYLOAD) {
3677 env->exception_pending = events.exception.pending;
3678 env->exception_has_payload = events.exception_has_payload;
3679 env->exception_payload = events.exception_payload;
3680 } else {
3681 env->exception_pending = 0;
3682 env->exception_has_payload = false;
3683 }
3684 env->exception_injected = events.exception.injected;
3685 env->exception_nr =
3686 (env->exception_pending || env->exception_injected) ?
3687 events.exception.nr : -1;
a0fb002c
JK		 3688 env->has_error_code = events.exception.has_error_code;
3689 env->error_code = events.exception.error_code;
3690
3691 env->interrupt_injected =
3692 events.interrupt.injected ? events.interrupt.nr : -1;
3693 env->soft_interrupt = events.interrupt.soft;
3694
3695 env->nmi_injected = events.nmi.injected;
3696 env->nmi_pending = events.nmi.pending;
3697 if (events.nmi.masked) {
3698 env->hflags2 |= HF2_NMI_MASK;
3699 } else {
3700 env->hflags2 &= ~HF2_NMI_MASK;
3701 }
3702
fc12d72e
PB		 3703 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3704 if (events.smi.smm) {
3705 env->hflags |= HF_SMM_MASK;
3706 } else {
3707 env->hflags &= ~HF_SMM_MASK;
3708 }
3709 if (events.smi.pending) {
3710 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3711 } else {
3712 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3713 }
3714 if (events.smi.smm_inside_nmi) {
3715 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3716 } else {
3717 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3718 }
3719 if (events.smi.latched_init) {
3720 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3721 } else {
3722 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3723 }
3724 }
3725
a0fb002c 3726 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3727
3728 return 0;
3729}
3730
1bc22652 3731static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3732{
ed2803da 3733 CPUState *cs = CPU(cpu);
1bc22652 3734 CPUX86State *env = &cpu->env;
b0b1d690 3735 int ret = 0;
b0b1d690
JK		 3736 unsigned long reinject_trap = 0;
3737
3738 if (!kvm_has_vcpu_events()) {
fd13f23b 3739 if (env->exception_nr == EXCP01_DB) {
b0b1d690 3740 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 3741 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 3742 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3743 }
fd13f23b 3744 kvm_reset_exception(env);
b0b1d690
JK		 3745 }
3746
3747 /*
3748 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3749 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3750 * by updating the debug state once again if single-stepping is on.
3751 * Another reason to call kvm_update_guest_debug here is a pending debug
3752 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3753 * reinject them via SET_GUEST_DEBUG.
3754 */
3755 if (reinject_trap ||
ed2803da 3756 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3757 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3758 }
b0b1d690
JK		 3759 return ret;
3760}
3761
1bc22652 3762static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3763{
1bc22652 3764 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3765 struct kvm_debugregs dbgregs;
3766 int i;
3767
3768 if (!kvm_has_debugregs()) {
3769 return 0;
3770 }
3771
1f670a95 3772 memset(&dbgregs, 0, sizeof(dbgregs));
ff44f1a3
JK		 3773 for (i = 0; i < 4; i++) {
3774 dbgregs.db[i] = env->dr[i];
3775 }
3776 dbgregs.dr6 = env->dr[6];
3777 dbgregs.dr7 = env->dr[7];
3778 dbgregs.flags = 0;
3779
1bc22652 3780 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3781}
3782
1bc22652 3783static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3784{
1bc22652 3785 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3786 struct kvm_debugregs dbgregs;
3787 int i, ret;
3788
3789 if (!kvm_has_debugregs()) {
3790 return 0;
3791 }
3792
1bc22652 3793 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3794 if (ret < 0) {
b9bec74b 3795 return ret;
ff44f1a3
JK		 3796 }
3797 for (i = 0; i < 4; i++) {
3798 env->dr[i] = dbgregs.db[i];
3799 }
3800 env->dr[4] = env->dr[6] = dbgregs.dr6;
3801 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3802
3803 return 0;
3804}
3805
ebbfef2f
LA		 3806static int kvm_put_nested_state(X86CPU *cpu)
3807{
3808 CPUX86State *env = &cpu->env;
3809 int max_nested_state_len = kvm_max_nested_state_length();
3810
1e44f3ab 3811 if (!env->nested_state) {
ebbfef2f
LA		 3812 return 0;
3813 }
3814
3815 assert(env->nested_state->size <= max_nested_state_len);
3816 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3817}
3818
3819static int kvm_get_nested_state(X86CPU *cpu)
3820{
3821 CPUX86State *env = &cpu->env;
3822 int max_nested_state_len = kvm_max_nested_state_length();
3823 int ret;
3824
1e44f3ab 3825 if (!env->nested_state) {
ebbfef2f
LA		 3826 return 0;
3827 }
3828
3829 /*
3830 * It is possible that migration restored a smaller size into
3831 * nested_state->hdr.size than what our kernel support.
3832 * We preserve migration origin nested_state->hdr.size for
3833 * call to KVM_SET_NESTED_STATE but wish that our next call
3834 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3835 */
3836 env->nested_state->size = max_nested_state_len;
3837
3838 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3839 if (ret < 0) {
3840 return ret;
3841 }
3842
3843 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3844 env->hflags |= HF_GUEST_MASK;
3845 } else {
3846 env->hflags &= ~HF_GUEST_MASK;
3847 }
3848
3849 return ret;
3850}
3851
20d695a9 3852int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3853{
20d695a9 3854 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3855 int ret;
3856
2fa45344 3857 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3858
48e1a45c 3859 if (level >= KVM_PUT_RESET_STATE) {
bec7156a
JK		 3860 ret = kvm_put_nested_state(x86_cpu);
3861 if (ret < 0) {
3862 return ret;
3863 }
3864
6bdf863d
JK		 3865 ret = kvm_put_msr_feature_control(x86_cpu);
3866 if (ret < 0) {
3867 return ret;
3868 }
3869 }
3870
36f96c4b
HZ		 3871 if (level == KVM_PUT_FULL_STATE) {
3872 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3873 * because TSC frequency mismatch shouldn't abort migration,
3874 * unless the user explicitly asked for a more strict TSC
3875 * setting (e.g. using an explicit "tsc-freq" option).
3876 */
3877 kvm_arch_set_tsc_khz(cpu);
3878 }
3879
1bc22652 3880 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3881 if (ret < 0) {
05330448 3882 return ret;
b9bec74b 3883 }
1bc22652 3884 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3885 if (ret < 0) {
f1665b21 3886 return ret;
b9bec74b 3887 }
1bc22652 3888 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3889 if (ret < 0) {
05330448 3890 return ret;
b9bec74b 3891 }
1bc22652 3892 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3893 if (ret < 0) {
05330448 3894 return ret;
b9bec74b 3895 }
ab443475 3896 /* must be before kvm_put_msrs */
1bc22652 3897 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3898 if (ret < 0) {
3899 return ret;
3900 }
1bc22652 3901 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3902 if (ret < 0) {
05330448 3903 return ret;
b9bec74b 3904 }
4fadfa00
PH		 3905 ret = kvm_put_vcpu_events(x86_cpu, level);
3906 if (ret < 0) {
3907 return ret;
3908 }
ea643051 3909 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3910 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3911 if (ret < 0) {
680c1c6f
JK		 3912 return ret;
3913 }
ea643051 3914 }
7477cd38
MT		 3915
3916 ret = kvm_put_tscdeadline_msr(x86_cpu);
3917 if (ret < 0) {
3918 return ret;
3919 }
1bc22652 3920 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3921 if (ret < 0) {
b0b1d690 3922 return ret;
b9bec74b 3923 }
b0b1d690 3924 /* must be last */
1bc22652 3925 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3926 if (ret < 0) {
ff44f1a3 3927 return ret;
b9bec74b 3928 }
05330448
AL		 3929 return 0;
3930}
3931
20d695a9 3932int kvm_arch_get_registers(CPUState *cs)
05330448 3933{
20d695a9 3934 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3935 int ret;
3936
20d695a9 3937 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3938
4fadfa00 3939 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3940 if (ret < 0) {
f4f1110e 3941 goto out;
b9bec74b 3942 }
4fadfa00
PH		 3943 /*
3944 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3945 * KVM_GET_REGS and KVM_GET_SREGS.
3946 */
3947 ret = kvm_get_mp_state(cpu);
b9bec74b 3948 if (ret < 0) {
f4f1110e 3949 goto out;
b9bec74b 3950 }
4fadfa00 3951 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3952 if (ret < 0) {
f4f1110e 3953 goto out;
b9bec74b 3954 }
4fadfa00 3955 ret = kvm_get_xsave(cpu);
b9bec74b 3956 if (ret < 0) {
f4f1110e 3957 goto out;
b9bec74b 3958 }
4fadfa00 3959 ret = kvm_get_xcrs(cpu);
b9bec74b 3960 if (ret < 0) {
f4f1110e 3961 goto out;
b9bec74b 3962 }
4fadfa00 3963 ret = kvm_get_sregs(cpu);
b9bec74b 3964 if (ret < 0) {
f4f1110e 3965 goto out;
b9bec74b 3966 }
4fadfa00 3967 ret = kvm_get_msrs(cpu);
680c1c6f 3968 if (ret < 0) {
f4f1110e 3969 goto out;
680c1c6f 3970 }
4fadfa00 3971 ret = kvm_get_apic(cpu);
b9bec74b 3972 if (ret < 0) {
f4f1110e 3973 goto out;
b9bec74b 3974 }
1bc22652 3975 ret = kvm_get_debugregs(cpu);
b9bec74b 3976 if (ret < 0) {
f4f1110e 3977 goto out;
b9bec74b 3978 }
ebbfef2f
LA		 3979 ret = kvm_get_nested_state(cpu);
3980 if (ret < 0) {
3981 goto out;
3982 }
f4f1110e
RH		 3983 ret = 0;
3984 out:
3985 cpu_sync_bndcs_hflags(&cpu->env);
3986 return ret;
05330448
AL		 3987}
3988
20d695a9 3989void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3990{
20d695a9
AF		 3991 X86CPU *x86_cpu = X86_CPU(cpu);
3992 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3993 int ret;
3994
276ce815 3995 /* Inject NMI */
fc12d72e
PB		 3996 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3997 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3998 qemu_mutex_lock_iothread();
3999 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
4000 qemu_mutex_unlock_iothread();
4001 DPRINTF("injected NMI\n");
4002 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
4003 if (ret < 0) {
4004 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
4005 strerror(-ret));
4006 }
4007 }
4008 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
4009 qemu_mutex_lock_iothread();
4010 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
4011 qemu_mutex_unlock_iothread();
4012 DPRINTF("injected SMI\n");
4013 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
4014 if (ret < 0) {
4015 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
4016 strerror(-ret));
4017 }
ce377af3 4018 }
276ce815
LJ		 4019 }
4020
15eafc2e 4021 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 4022 qemu_mutex_lock_iothread();
4023 }
4024
e0723c45
PB		 4025 /* Force the VCPU out of its inner loop to process any INIT requests
4026 * or (for userspace APIC, but it is cheap to combine the checks here)
4027 * pending TPR access reports.
4028 */
4029 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 4030 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
4031 !(env->hflags & HF_SMM_MASK)) {
4032 cpu->exit_request = 1;
4033 }
4034 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
4035 cpu->exit_request = 1;
4036 }
e0723c45 4037 }
05330448 4038
15eafc2e 4039 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 4040 /* Try to inject an interrupt if the guest can accept it */
4041 if (run->ready_for_interrupt_injection &&
259186a7 4042 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 4043 (env->eflags & IF_MASK)) {
4044 int irq;
4045
259186a7 4046 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 4047 irq = cpu_get_pic_interrupt(env);
4048 if (irq >= 0) {
4049 struct kvm_interrupt intr;
4050
4051 intr.irq = irq;
db1669bc 4052 DPRINTF("injected interrupt %d\n", irq);
1bc22652 4053 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 4054 if (ret < 0) {
4055 fprintf(stderr,
4056 "KVM: injection failed, interrupt lost (%s)\n",
4057 strerror(-ret));
4058 }
db1669bc
JK		 4059 }
4060 }
05330448 4061
db1669bc
JK		 4062 /* If we have an interrupt but the guest is not ready to receive an
4063 * interrupt, request an interrupt window exit. This will
4064 * cause a return to userspace as soon as the guest is ready to
4065 * receive interrupts. */
259186a7 4066 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 4067 run->request_interrupt_window = 1;
4068 } else {
4069 run->request_interrupt_window = 0;
4070 }
4071
4072 DPRINTF("setting tpr\n");
02e51483 4073 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 4074
4075 qemu_mutex_unlock_iothread();
db1669bc 4076 }
05330448
AL		 4077}
4078
4c663752 4079MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 4080{
20d695a9
AF		 4081 X86CPU *x86_cpu = X86_CPU(cpu);
4082 CPUX86State *env = &x86_cpu->env;
4083
fc12d72e
PB		 4084 if (run->flags & KVM_RUN_X86_SMM) {
4085 env->hflags |= HF_SMM_MASK;
4086 } else {
f5c052b9 4087 env->hflags &= ~HF_SMM_MASK;
fc12d72e 4088 }
b9bec74b 4089 if (run->if_flag) {
05330448 4090 env->eflags |= IF_MASK;
b9bec74b 4091 } else {
05330448 4092 env->eflags &= ~IF_MASK;
b9bec74b 4093 }
4b8523ee
JK		 4094
4095 /* We need to protect the apic state against concurrent accesses from
4096 * different threads in case the userspace irqchip is used. */
4097 if (!kvm_irqchip_in_kernel()) {
4098 qemu_mutex_lock_iothread();
4099 }
02e51483
CF		 4100 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
4101 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 4102 if (!kvm_irqchip_in_kernel()) {
4103 qemu_mutex_unlock_iothread();
4104 }
f794aa4a 4105 return cpu_get_mem_attrs(env);
05330448
AL		 4106}
4107
20d695a9 4108int kvm_arch_process_async_events(CPUState *cs)
0af691d7 4109{
20d695a9
AF		 4110 X86CPU *cpu = X86_CPU(cs);
4111 CPUX86State *env = &cpu->env;
232fc23b 4112
259186a7 4113 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 4114 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
4115 assert(env->mcg_cap);
4116
259186a7 4117 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 4118
dd1750d7 4119 kvm_cpu_synchronize_state(cs);
ab443475 4120
fd13f23b 4121 if (env->exception_nr == EXCP08_DBLE) {
ab443475 4122 /* this means triple fault */
cf83f140 4123 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 4124 cs->exit_request = 1;
ab443475
JK		 4125 return 0;
4126 }
fd13f23b 4127 kvm_queue_exception(env, EXCP12_MCHK, 0, 0);
ab443475
JK		 4128 env->has_error_code = 0;
4129
259186a7 4130 cs->halted = 0;
ab443475
JK		 4131 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
4132 env->mp_state = KVM_MP_STATE_RUNNABLE;
4133 }
4134 }
4135
fc12d72e
PB		 4136 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
4137 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 4138 kvm_cpu_synchronize_state(cs);
4139 do_cpu_init(cpu);
4140 }
4141
db1669bc
JK		 4142 if (kvm_irqchip_in_kernel()) {
4143 return 0;
4144 }
4145
259186a7
AF		 4146 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
4147 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 4148 apic_poll_irq(cpu->apic_state);
5d62c43a 4149 }
259186a7 4150 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 4151 (env->eflags & IF_MASK)) ||
259186a7
AF		 4152 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4153 cs->halted = 0;
6792a57b 4154 }
259186a7 4155 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 4156 kvm_cpu_synchronize_state(cs);
232fc23b 4157 do_cpu_sipi(cpu);
0af691d7 4158 }
259186a7
AF		 4159 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
4160 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 4161 kvm_cpu_synchronize_state(cs);
02e51483 4162 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 4163 env->tpr_access_type);
4164 }
0af691d7 4165
259186a7 4166 return cs->halted;
0af691d7
MT		 4167}
4168
839b5630 4169static int kvm_handle_halt(X86CPU *cpu)
05330448 4170{
259186a7 4171 CPUState *cs = CPU(cpu);
839b5630
AF		 4172 CPUX86State *env = &cpu->env;
4173
259186a7 4174 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 4175 (env->eflags & IF_MASK)) &&
259186a7
AF		 4176 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
4177 cs->halted = 1;
bb4ea393 4178 return EXCP_HLT;
05330448
AL		 4179 }
4180
bb4ea393 4181 return 0;
05330448
AL		 4182}
4183
f7575c96 4184static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 4185{
f7575c96
AF		 4186 CPUState *cs = CPU(cpu);
4187 struct kvm_run *run = cs->kvm_run;
d362e757 4188
02e51483 4189 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 4190 run->tpr_access.is_write ? TPR_ACCESS_WRITE
4191 : TPR_ACCESS_READ);
4192 return 1;
4193}
4194
f17ec444 4195int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 4196{
38972938 4197 static const uint8_t int3 = 0xcc;
64bf3f4e 4198
f17ec444
AF		 4199 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
4200 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 4201 return -EINVAL;
b9bec74b 4202 }
e22a25c9
AL		 4203 return 0;
4204}
4205
f17ec444 4206int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 4207{
4208 uint8_t int3;
4209
f17ec444
AF		 4210 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
4211 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 4212 return -EINVAL;
b9bec74b 4213 }
e22a25c9
AL		 4214 return 0;
4215}
4216
4217static struct {
4218 target_ulong addr;
4219 int len;
4220 int type;
4221} hw_breakpoint[4];
4222
4223static int nb_hw_breakpoint;
4224
4225static int find_hw_breakpoint(target_ulong addr, int len, int type)
4226{
4227 int n;
4228
b9bec74b 4229 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 4230 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 4231 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 4232 return n;
b9bec74b
JK		 4233 }
4234 }
e22a25c9
AL		 4235 return -1;
4236}
4237
4238int kvm_arch_insert_hw_breakpoint(target_ulong addr,
4239 target_ulong len, int type)
4240{
4241 switch (type) {
4242 case GDB_BREAKPOINT_HW:
4243 len = 1;
4244 break;
4245 case GDB_WATCHPOINT_WRITE:
4246 case GDB_WATCHPOINT_ACCESS:
4247 switch (len) {
4248 case 1:
4249 break;
4250 case 2:
4251 case 4:
4252 case 8:
b9bec74b 4253 if (addr & (len - 1)) {
e22a25c9 4254 return -EINVAL;
b9bec74b 4255 }
e22a25c9
AL		 4256 break;
4257 default:
4258 return -EINVAL;
4259 }
4260 break;
4261 default:
4262 return -ENOSYS;
4263 }
4264
b9bec74b 4265 if (nb_hw_breakpoint == 4) {
e22a25c9 4266 return -ENOBUFS;
b9bec74b
JK		 4267 }
4268 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 4269 return -EEXIST;
b9bec74b 4270 }
e22a25c9
AL		 4271 hw_breakpoint[nb_hw_breakpoint].addr = addr;
4272 hw_breakpoint[nb_hw_breakpoint].len = len;
4273 hw_breakpoint[nb_hw_breakpoint].type = type;
4274 nb_hw_breakpoint++;
4275
4276 return 0;
4277}
4278
4279int kvm_arch_remove_hw_breakpoint(target_ulong addr,
4280 target_ulong len, int type)
4281{
4282 int n;
4283
4284 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 4285 if (n < 0) {
e22a25c9 4286 return -ENOENT;
b9bec74b 4287 }
e22a25c9
AL		 4288 nb_hw_breakpoint--;
4289 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
4290
4291 return 0;
4292}
4293
4294void kvm_arch_remove_all_hw_breakpoints(void)
4295{
4296 nb_hw_breakpoint = 0;
4297}
4298
4299static CPUWatchpoint hw_watchpoint;
4300
a60f24b5 4301static int kvm_handle_debug(X86CPU *cpu,
48405526 4302 struct kvm_debug_exit_arch *arch_info)
e22a25c9 4303{
ed2803da 4304 CPUState *cs = CPU(cpu);
a60f24b5 4305 CPUX86State *env = &cpu->env;
f2574737 4306 int ret = 0;
e22a25c9
AL		 4307 int n;
4308
37936ac7
LA		 4309 if (arch_info->exception == EXCP01_DB) {
4310 if (arch_info->dr6 & DR6_BS) {
ed2803da 4311 if (cs->singlestep_enabled) {
f2574737 4312 ret = EXCP_DEBUG;
b9bec74b 4313 }
e22a25c9 4314 } else {
b9bec74b
JK		 4315 for (n = 0; n < 4; n++) {
4316 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 4317 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
4318 case 0x0:
f2574737 4319 ret = EXCP_DEBUG;
e22a25c9
AL		 4320 break;
4321 case 0x1:
f2574737 4322 ret = EXCP_DEBUG;
ff4700b0 4323 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4324 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4325 hw_watchpoint.flags = BP_MEM_WRITE;
4326 break;
4327 case 0x3:
f2574737 4328 ret = EXCP_DEBUG;
ff4700b0 4329 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 4330 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
4331 hw_watchpoint.flags = BP_MEM_ACCESS;
4332 break;
4333 }
b9bec74b
JK		 4334 }
4335 }
e22a25c9 4336 }
ff4700b0 4337 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 4338 ret = EXCP_DEBUG;
b9bec74b 4339 }
f2574737 4340 if (ret == 0) {
ff4700b0 4341 cpu_synchronize_state(cs);
fd13f23b 4342 assert(env->exception_nr == -1);
b0b1d690 4343
f2574737 4344 /* pass to guest */
fd13f23b
LA		 4345 kvm_queue_exception(env, arch_info->exception,
4346 arch_info->exception == EXCP01_DB,
4347 arch_info->dr6);
48405526 4348 env->has_error_code = 0;
b0b1d690 4349 }
e22a25c9 4350
f2574737 4351 return ret;
e22a25c9
AL		 4352}
4353
20d695a9 4354void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 4355{
4356 const uint8_t type_code[] = {
4357 [GDB_BREAKPOINT_HW] = 0x0,
4358 [GDB_WATCHPOINT_WRITE] = 0x1,
4359 [GDB_WATCHPOINT_ACCESS] = 0x3
4360 };
4361 const uint8_t len_code[] = {
4362 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
4363 };
4364 int n;
4365
a60f24b5 4366 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 4367 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 4368 }
e22a25c9
AL		 4369 if (nb_hw_breakpoint > 0) {
4370 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4371 dbg->arch.debugreg[7] = 0x0600;
4372 for (n = 0; n < nb_hw_breakpoint; n++) {
4373 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4374 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4375 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 4376 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 4377 }
4378 }
4379}
4513d923 4380
2a4dac83
JK		 4381static bool host_supports_vmx(void)
4382{
4383 uint32_t ecx, unused;
4384
4385 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4386 return ecx & CPUID_EXT_VMX;
4387}
4388
4389#define VMX_INVALID_GUEST_STATE 0x80000021
4390
20d695a9 4391int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 4392{
20d695a9 4393 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 4394 uint64_t code;
4395 int ret;
4396
4397 switch (run->exit_reason) {
4398 case KVM_EXIT_HLT:
4399 DPRINTF("handle_hlt\n");
4b8523ee 4400 qemu_mutex_lock_iothread();
839b5630 4401 ret = kvm_handle_halt(cpu);
4b8523ee 4402 qemu_mutex_unlock_iothread();
2a4dac83
JK		 4403 break;
4404 case KVM_EXIT_SET_TPR:
4405 ret = 0;
4406 break;
d362e757 4407 case KVM_EXIT_TPR_ACCESS:
4b8523ee 4408 qemu_mutex_lock_iothread();
f7575c96 4409 ret = kvm_handle_tpr_access(cpu);
4b8523ee 4410 qemu_mutex_unlock_iothread();
d362e757 4411 break;
2a4dac83
JK		 4412 case KVM_EXIT_FAIL_ENTRY:
4413 code = run->fail_entry.hardware_entry_failure_reason;
4414 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4415 code);
4416 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4417 fprintf(stderr,
12619721 4418 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 4419 "unrestricted mode\n"
4420 "support, the failure can be most likely due to the guest "
4421 "entering an invalid\n"
4422 "state for Intel VT. For example, the guest maybe running "
4423 "in big real mode\n"
4424 "which is not supported on less recent Intel processors."
4425 "\n\n");
4426 }
4427 ret = -1;
4428 break;
4429 case KVM_EXIT_EXCEPTION:
4430 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4431 run->ex.exception, run->ex.error_code);
4432 ret = -1;
4433 break;
f2574737
JK		 4434 case KVM_EXIT_DEBUG:
4435 DPRINTF("kvm_exit_debug\n");
4b8523ee 4436 qemu_mutex_lock_iothread();
a60f24b5 4437 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 4438 qemu_mutex_unlock_iothread();
f2574737 4439 break;
50efe82c
AS		 4440 case KVM_EXIT_HYPERV:
4441 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4442 break;
15eafc2e
PB		 4443 case KVM_EXIT_IOAPIC_EOI:
4444 ioapic_eoi_broadcast(run->eoi.vector);
4445 ret = 0;
4446 break;
2a4dac83
JK		 4447 default:
4448 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4449 ret = -1;
4450 break;
4451 }
4452
4453 return ret;
4454}
4455
20d695a9 4456bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4457{
20d695a9
AF		 4458 X86CPU *cpu = X86_CPU(cs);
4459 CPUX86State *env = &cpu->env;
4460
dd1750d7 4461 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4462 return !(env->cr[0] & CR0_PE_MASK) ||
4463 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4464}
84b058d7
JK		 4465
4466void kvm_arch_init_irq_routing(KVMState *s)
4467{
4468 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4469 /* If kernel can't do irq routing, interrupt source
4470 * override 0->2 cannot be set up as required by HPET.
4471 * So we have to disable it.
4472 */
4473 no_hpet = 1;
4474 }
cc7e0ddf 4475 /* We know at this point that we're using the in-kernel
614e41bc 4476 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4477 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4478 */
614e41bc 4479 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4480 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4481
4482 if (kvm_irqchip_is_split()) {
4483 int i;
4484
4485 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4486 MSI routes for signaling interrupts to the local apics. */
4487 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4488 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4489 error_report("Could not enable split IRQ mode.");
4490 exit(1);
4491 }
4492 }
4493 }
4494}
4495
4376c40d 4496int kvm_arch_irqchip_create(KVMState *s)
15eafc2e
PB		 4497{
4498 int ret;
4376c40d 4499 if (kvm_kernel_irqchip_split()) {
15eafc2e
PB		 4500 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4501 if (ret) {
df3c286c 4502 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4503 strerror(-ret));
4504 exit(1);
4505 } else {
4506 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4507 kvm_split_irqchip = true;
4508 return 1;
4509 }
4510 } else {
4511 return 0;
4512 }
84b058d7 4513}
b139bd30
JK		 4514
4515/* Classic KVM device assignment interface. Will remain x86 only. */
4516int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4517 uint32_t flags, uint32_t *dev_id)
4518{
4519 struct kvm_assigned_pci_dev dev_data = {
4520 .segnr = dev_addr->domain,
4521 .busnr = dev_addr->bus,
4522 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4523 .flags = flags,
4524 };
4525 int ret;
4526
4527 dev_data.assigned_dev_id =
4528 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4529
4530 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4531 if (ret < 0) {
4532 return ret;
4533 }
4534
4535 *dev_id = dev_data.assigned_dev_id;
4536
4537 return 0;
4538}
4539
4540int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4541{
4542 struct kvm_assigned_pci_dev dev_data = {
4543 .assigned_dev_id = dev_id,
4544 };
4545
4546 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4547}
4548
4549static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4550 uint32_t irq_type, uint32_t guest_irq)
4551{
4552 struct kvm_assigned_irq assigned_irq = {
4553 .assigned_dev_id = dev_id,
4554 .guest_irq = guest_irq,
4555 .flags = irq_type,
4556 };
4557
4558 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4559 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4560 } else {
4561 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4562 }
4563}
4564
4565int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4566 uint32_t guest_irq)
4567{
4568 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4569 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4570
4571 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4572}
4573
4574int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4575{
4576 struct kvm_assigned_pci_dev dev_data = {
4577 .assigned_dev_id = dev_id,
4578 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4579 };
4580
4581 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4582}
4583
4584static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4585 uint32_t type)
4586{
4587 struct kvm_assigned_irq assigned_irq = {
4588 .assigned_dev_id = dev_id,
4589 .flags = type,
4590 };
4591
4592 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4593}
4594
4595int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4596{
4597 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4598 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4599}
4600
4601int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4602{
4603 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4604 KVM_DEV_IRQ_GUEST_MSI, virq);
4605}
4606
4607int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4608{
4609 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4610 KVM_DEV_IRQ_HOST_MSI);
4611}
4612
4613bool kvm_device_msix_supported(KVMState *s)
4614{
4615 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4616 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4617 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4618}
4619
4620int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4621 uint32_t nr_vectors)
4622{
4623 struct kvm_assigned_msix_nr msix_nr = {
4624 .assigned_dev_id = dev_id,
4625 .entry_nr = nr_vectors,
4626 };
4627
4628 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4629}
4630
4631int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4632 int virq)
4633{
4634 struct kvm_assigned_msix_entry msix_entry = {
4635 .assigned_dev_id = dev_id,
4636 .gsi = virq,
4637 .entry = vector,
4638 };
4639
4640 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4641}
4642
4643int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4644{
4645 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4646 KVM_DEV_IRQ_GUEST_MSIX, 0);
4647}
4648
4649int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4650{
4651 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4652 KVM_DEV_IRQ_HOST_MSIX);
4653}
9e03a040
FB		 4654
4655int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4656 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4657{
8b5ed7df
PX		 4658 X86IOMMUState *iommu = x86_iommu_get_default();
4659
4660 if (iommu) {
4661 int ret;
4662 MSIMessage src, dst;
4663 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4664
0ea1472d
JK		 4665 if (!class->int_remap) {
4666 return 0;
4667 }
4668
8b5ed7df
PX		 4669 src.address = route->u.msi.address_hi;
4670 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4671 src.address |= route->u.msi.address_lo;
4672 src.data = route->u.msi.data;
4673
4674 ret = class->int_remap(iommu, &src, &dst, dev ? \
4675 pci_requester_id(dev) : \
4676 X86_IOMMU_SID_INVALID);
4677 if (ret) {
4678 trace_kvm_x86_fixup_msi_error(route->gsi);
4679 return 1;
4680 }
4681
4682 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4683 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4684 route->u.msi.data = dst.data;
4685 }
4686
9e03a040
FB		 4687 return 0;
4688}
1850b6b7 4689
38d87493
PX		 4690typedef struct MSIRouteEntry MSIRouteEntry;
4691
4692struct MSIRouteEntry {
4693 PCIDevice *dev; /* Device pointer */
4694 int vector; /* MSI/MSIX vector index */
4695 int virq; /* Virtual IRQ index */
4696 QLIST_ENTRY(MSIRouteEntry) list;
4697};
4698
4699/* List of used GSI routes */
4700static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4701 QLIST_HEAD_INITIALIZER(msi_route_list);
4702
e1d4fb2d
PX		 4703static void kvm_update_msi_routes_all(void *private, bool global,
4704 uint32_t index, uint32_t mask)
4705{
a56de056 4706 int cnt = 0, vector;
e1d4fb2d
PX		 4707 MSIRouteEntry *entry;
4708 MSIMessage msg;
fd563564
PX		 4709 PCIDevice *dev;
4710
e1d4fb2d
PX		 4711 /* TODO: explicit route update */
4712 QLIST_FOREACH(entry, &msi_route_list, list) {
4713 cnt++;
a56de056 4714 vector = entry->vector;
fd563564 4715 dev = entry->dev;
a56de056
PX		 4716 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4717 msg = msix_get_message(dev, vector);
4718 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4719 msg = msi_get_message(dev, vector);
4720 } else {
4721 /*
4722 * Either MSI/MSIX is disabled for the device, or the
4723 * specific message was masked out. Skip this one.
4724 */
fd563564
PX		 4725 continue;
4726 }
fd563564 4727 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4728 }
3f1fea0f 4729 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4730 trace_kvm_x86_update_msi_routes(cnt);
4731}
4732
38d87493
PX		 4733int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4734 int vector, PCIDevice *dev)
4735{
e1d4fb2d 4736 static bool notify_list_inited = false;
38d87493
PX		 4737 MSIRouteEntry *entry;
4738
4739 if (!dev) {
4740 /* These are (possibly) IOAPIC routes only used for split
4741 * kernel irqchip mode, while what we are housekeeping are
4742 * PCI devices only. */
4743 return 0;
4744 }
4745
4746 entry = g_new0(MSIRouteEntry, 1);
4747 entry->dev = dev;
4748 entry->vector = vector;
4749 entry->virq = route->gsi;
4750 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4751
4752 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4753
4754 if (!notify_list_inited) {
4755 /* For the first time we do add route, add ourselves into
4756 * IOMMU's IEC notify list if needed. */
4757 X86IOMMUState *iommu = x86_iommu_get_default();
4758 if (iommu) {
4759 x86_iommu_iec_register_notifier(iommu,
4760 kvm_update_msi_routes_all,
4761 NULL);
4762 }
4763 notify_list_inited = true;
4764 }
38d87493
PX		 4765 return 0;
4766}
4767
4768int kvm_arch_release_virq_post(int virq)
4769{
4770 MSIRouteEntry *entry, *next;
4771 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4772 if (entry->virq == virq) {
4773 trace_kvm_x86_remove_msi_route(virq);
4774 QLIST_REMOVE(entry, list);
01960e6d 4775 g_free(entry);
38d87493
PX		 4776 break;
4777 }
4778 }
9e03a040
FB		 4779 return 0;
4780}
1850b6b7
EA		 4781
4782int kvm_arch_msi_data_to_gsi(uint32_t data)
4783{
4784 abort();
4785}
QEMU mirror