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target/i386: WHPX: set CPUID_EXT_HYPERVISOR bit
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
5802e066 21#include <linux/kvm_para.h>
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
022c62cb 43#include "exec/ioport.h"
a2cb15b0 44#include "hw/pci/pci.h"
15eafc2e 45#include "hw/pci/msi.h"
fd563564 46#include "hw/pci/msix.h"
795c40b8 47#include "migration/blocker.h"
4c663752 48#include "exec/memattrs.h"
8b5ed7df 49#include "trace.h"
05330448
AL		 50
51//#define DEBUG_KVM
52
53#ifdef DEBUG_KVM
8c0d577e 54#define DPRINTF(fmt, ...) \
05330448
AL		 55 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
56#else
8c0d577e 57#define DPRINTF(fmt, ...) \
05330448
AL		 58 do { } while (0)
59#endif
60
1a03675d
GC		 61#define MSR_KVM_WALL_CLOCK 0x11
62#define MSR_KVM_SYSTEM_TIME 0x12
63
d1138251
EH		 64/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
65 * 255 kvm_msr_entry structs */
66#define MSR_BUF_SIZE 4096
d71b62a1 67
94a8d39a
JK		 68const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
69 KVM_CAP_INFO(SET_TSS_ADDR),
70 KVM_CAP_INFO(EXT_CPUID),
71 KVM_CAP_INFO(MP_STATE),
72 KVM_CAP_LAST_INFO
73};
25d2e361 74
c3a3a7d3
JK		 75static bool has_msr_star;
76static bool has_msr_hsave_pa;
c9b8f6b6 77static bool has_msr_tsc_aux;
f28558d3 78static bool has_msr_tsc_adjust;
aa82ba54 79static bool has_msr_tsc_deadline;
df67696e 80static bool has_msr_feature_control;
21e87c46 81static bool has_msr_misc_enable;
fc12d72e 82static bool has_msr_smbase;
79e9ebeb 83static bool has_msr_bndcfgs;
25d2e361 84static int lm_capable_kernel;
7bc3d711 85static bool has_msr_hv_hypercall;
f2a53c9e 86static bool has_msr_hv_crash;
744b8a94 87static bool has_msr_hv_reset;
8c145d7c 88static bool has_msr_hv_vpindex;
46eb8f98 89static bool has_msr_hv_runtime;
866eea9a 90static bool has_msr_hv_synic;
ff99aa64 91static bool has_msr_hv_stimer;
d72bc7f6 92static bool has_msr_hv_frequencies;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
e13713db 95static bool has_msr_smi_count;
b827df58 96
0b368a10
JD		 97static uint32_t has_architectural_pmu_version;
98static uint32_t num_architectural_pmu_gp_counters;
99static uint32_t num_architectural_pmu_fixed_counters;
0d894367 100
28143b40
TH		 101static int has_xsave;
102static int has_xcrs;
103static int has_pit_state2;
104
87f8b626
AR		 105static bool has_msr_mcg_ext_ctl;
106
494e95e9
CP		 107static struct kvm_cpuid2 *cpuid_cache;
108
28143b40
TH		 109int kvm_has_pit_state2(void)
110{
111 return has_pit_state2;
112}
113
355023f2
PB		 114bool kvm_has_smm(void)
115{
116 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
117}
118
6053a86f
MT		 119bool kvm_has_adjust_clock_stable(void)
120{
121 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
122
123 return (ret == KVM_CLOCK_TSC_STABLE);
124}
125
1d31f66b
PM		 126bool kvm_allows_irq0_override(void)
127{
128 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
129}
130
fb506e70
RK		 131static bool kvm_x2apic_api_set_flags(uint64_t flags)
132{
133 KVMState *s = KVM_STATE(current_machine->accelerator);
134
135 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
136}
137
e391c009 138#define MEMORIZE(fn, _result) \
2a138ec3 139 ({ \
2a138ec3
RK		 140 static bool _memorized; \
141 \
142 if (_memorized) { \
143 return _result; \
144 } \
145 _memorized = true; \
146 _result = fn; \
147 })
148
e391c009
IM		 149static bool has_x2apic_api;
150
151bool kvm_has_x2apic_api(void)
152{
153 return has_x2apic_api;
154}
155
fb506e70
RK		 156bool kvm_enable_x2apic(void)
157{
2a138ec3
RK		 158 return MEMORIZE(
159 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 160 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
161 has_x2apic_api);
fb506e70
RK		 162}
163
0fd7e098
LL		 164static int kvm_get_tsc(CPUState *cs)
165{
166 X86CPU *cpu = X86_CPU(cs);
167 CPUX86State *env = &cpu->env;
168 struct {
169 struct kvm_msrs info;
170 struct kvm_msr_entry entries[1];
171 } msr_data;
172 int ret;
173
174 if (env->tsc_valid) {
175 return 0;
176 }
177
178 msr_data.info.nmsrs = 1;
179 msr_data.entries[0].index = MSR_IA32_TSC;
180 env->tsc_valid = !runstate_is_running();
181
182 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
183 if (ret < 0) {
184 return ret;
185 }
186
48e1a45c 187 assert(ret == 1);
0fd7e098
LL		 188 env->tsc = msr_data.entries[0].data;
189 return 0;
190}
191
14e6fe12 192static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 193{
0fd7e098
LL		 194 kvm_get_tsc(cpu);
195}
196
197void kvm_synchronize_all_tsc(void)
198{
199 CPUState *cpu;
200
201 if (kvm_enabled()) {
202 CPU_FOREACH(cpu) {
14e6fe12 203 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 204 }
205 }
206}
207
b827df58
AK		 208static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
209{
210 struct kvm_cpuid2 *cpuid;
211 int r, size;
212
213 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 214 cpuid = g_malloc0(size);
b827df58
AK		 215 cpuid->nent = max;
216 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 217 if (r == 0 && cpuid->nent >= max) {
218 r = -E2BIG;
219 }
b827df58
AK		 220 if (r < 0) {
221 if (r == -E2BIG) {
7267c094 222 g_free(cpuid);
b827df58
AK		 223 return NULL;
224 } else {
225 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
226 strerror(-r));
227 exit(1);
228 }
229 }
230 return cpuid;
231}
232
dd87f8a6
EH		 233/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
234 * for all entries.
235 */
236static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
237{
238 struct kvm_cpuid2 *cpuid;
239 int max = 1;
494e95e9
CP		 240
241 if (cpuid_cache != NULL) {
242 return cpuid_cache;
243 }
dd87f8a6
EH		 244 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
245 max *= 2;
246 }
494e95e9 247 cpuid_cache = cpuid;
dd87f8a6
EH		 248 return cpuid;
249}
250
a443bc34 251static const struct kvm_para_features {
0c31b744
GC		 252 int cap;
253 int feature;
254} para_features[] = {
255 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
256 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
257 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 258 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 259};
260
ba9bc59e 261static int get_para_features(KVMState *s)
0c31b744
GC		 262{
263 int i, features = 0;
264
8e03c100 265 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 266 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 267 features |= (1 << para_features[i].feature);
268 }
269 }
270
271 return features;
272}
0c31b744 273
40e80ee4
EH		 274static bool host_tsx_blacklisted(void)
275{
276 int family, model, stepping;\
277 char vendor[CPUID_VENDOR_SZ + 1];
278
279 host_vendor_fms(vendor, &family, &model, &stepping);
280
281 /* Check if we are running on a Haswell host known to have broken TSX */
282 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
283 (family == 6) &&
284 ((model == 63 && stepping < 4) ||
285 model == 60 || model == 69 || model == 70);
286}
0c31b744 287
829ae2f9
EH		 288/* Returns the value for a specific register on the cpuid entry
289 */
290static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
291{
292 uint32_t ret = 0;
293 switch (reg) {
294 case R_EAX:
295 ret = entry->eax;
296 break;
297 case R_EBX:
298 ret = entry->ebx;
299 break;
300 case R_ECX:
301 ret = entry->ecx;
302 break;
303 case R_EDX:
304 ret = entry->edx;
305 break;
306 }
307 return ret;
308}
309
4fb73f1d
EH		 310/* Find matching entry for function/index on kvm_cpuid2 struct
311 */
312static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
313 uint32_t function,
314 uint32_t index)
315{
316 int i;
317 for (i = 0; i < cpuid->nent; ++i) {
318 if (cpuid->entries[i].function == function &&
319 cpuid->entries[i].index == index) {
320 return &cpuid->entries[i];
321 }
322 }
323 /* not found: */
324 return NULL;
325}
326
ba9bc59e 327uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 328 uint32_t index, int reg)
b827df58
AK		 329{
330 struct kvm_cpuid2 *cpuid;
b827df58
AK		 331 uint32_t ret = 0;
332 uint32_t cpuid_1_edx;
8c723b79 333 bool found = false;
b827df58 334
dd87f8a6 335 cpuid = get_supported_cpuid(s);
b827df58 336
4fb73f1d
EH		 337 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
338 if (entry) {
339 found = true;
340 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 341 }
342
7b46e5ce
EH		 343 /* Fixups for the data returned by KVM, below */
344
c2acb022
EH		 345 if (function == 1 && reg == R_EDX) {
346 /* KVM before 2.6.30 misreports the following features */
347 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 348 } else if (function == 1 && reg == R_ECX) {
349 /* We can set the hypervisor flag, even if KVM does not return it on
350 * GET_SUPPORTED_CPUID
351 */
352 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 353 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
354 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
355 * and the irqchip is in the kernel.
356 */
357 if (kvm_irqchip_in_kernel() &&
358 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
359 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
360 }
41e5e76d
EH		 361
362 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
363 * without the in-kernel irqchip
364 */
365 if (!kvm_irqchip_in_kernel()) {
366 ret &= ~CPUID_EXT_X2APIC;
b827df58 367 }
28b8e4d0
JK		 368 } else if (function == 6 && reg == R_EAX) {
369 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 370 } else if (function == 7 && index == 0 && reg == R_EBX) {
371 if (host_tsx_blacklisted()) {
372 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
373 }
c2acb022
EH		 374 } else if (function == 0x80000001 && reg == R_EDX) {
375 /* On Intel, kvm returns cpuid according to the Intel spec,
376 * so add missing bits according to the AMD spec:
377 */
378 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
379 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 380 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
381 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
382 * be enabled without the in-kernel irqchip
383 */
384 if (!kvm_irqchip_in_kernel()) {
385 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
386 }
be777326
WL		 387 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
388 ret |= KVM_HINTS_DEDICATED;
389 found = 1;
b827df58
AK		 390 }
391
0c31b744 392 /* fallback for older kernels */
8c723b79 393 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 394 ret = get_para_features(s);
b9bec74b 395 }
0c31b744
GC		 396
397 return ret;
bb0300dc 398}
bb0300dc 399
3c85e74f
HY		 400typedef struct HWPoisonPage {
401 ram_addr_t ram_addr;
402 QLIST_ENTRY(HWPoisonPage) list;
403} HWPoisonPage;
404
405static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
406 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
407
408static void kvm_unpoison_all(void *param)
409{
410 HWPoisonPage *page, *next_page;
411
412 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
413 QLIST_REMOVE(page, list);
414 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 415 g_free(page);
3c85e74f
HY		 416 }
417}
418
3c85e74f
HY		 419static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
420{
421 HWPoisonPage *page;
422
423 QLIST_FOREACH(page, &hwpoison_page_list, list) {
424 if (page->ram_addr == ram_addr) {
425 return;
426 }
427 }
ab3ad07f 428 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 429 page->ram_addr = ram_addr;
430 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
431}
432
e7701825
MT		 433static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
434 int *max_banks)
435{
436 int r;
437
14a09518 438 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 439 if (r > 0) {
440 *max_banks = r;
441 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
442 }
443 return -ENOSYS;
444}
445
bee615d4 446static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 447{
87f8b626 448 CPUState *cs = CPU(cpu);
bee615d4 449 CPUX86State *env = &cpu->env;
c34d440a
JK		 450 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
451 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
452 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 453 int flags = 0;
e7701825 454
c34d440a
JK		 455 if (code == BUS_MCEERR_AR) {
456 status |= MCI_STATUS_AR | 0x134;
457 mcg_status |= MCG_STATUS_EIPV;
458 } else {
459 status |= 0xc0;
460 mcg_status |= MCG_STATUS_RIPV;
419fb20a 461 }
87f8b626
AR		 462
463 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
464 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
465 * guest kernel back into env->mcg_ext_ctl.
466 */
467 cpu_synchronize_state(cs);
468 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
469 mcg_status |= MCG_STATUS_LMCE;
470 flags = 0;
471 }
472
8c5cf3b6 473 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 474 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 475}
419fb20a
JK		 476
477static void hardware_memory_error(void)
478{
479 fprintf(stderr, "Hardware memory error!\n");
480 exit(1);
481}
482
2ae41db2 483void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 484{
20d695a9
AF		 485 X86CPU *cpu = X86_CPU(c);
486 CPUX86State *env = &cpu->env;
419fb20a 487 ram_addr_t ram_addr;
a8170e5e 488 hwaddr paddr;
419fb20a 489
4d39892c
PB		 490 /* If we get an action required MCE, it has been injected by KVM
491 * while the VM was running. An action optional MCE instead should
492 * be coming from the main thread, which qemu_init_sigbus identifies
493 * as the "early kill" thread.
494 */
a16fc07e 495 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 496
20e0ff59 497 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 498 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 499 if (ram_addr != RAM_ADDR_INVALID &&
500 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
501 kvm_hwpoison_page_add(ram_addr);
502 kvm_mce_inject(cpu, paddr, code);
2ae41db2 503 return;
419fb20a 504 }
20e0ff59
PB		 505
506 fprintf(stderr, "Hardware memory error for memory used by "
507 "QEMU itself instead of guest system!\n");
419fb20a 508 }
20e0ff59
PB		 509
510 if (code == BUS_MCEERR_AR) {
511 hardware_memory_error();
512 }
513
514 /* Hope we are lucky for AO MCE */
419fb20a
JK		 515}
516
1bc22652 517static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 518{
1bc22652
AF		 519 CPUX86State *env = &cpu->env;
520
ab443475
JK		 521 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
522 unsigned int bank, bank_num = env->mcg_cap & 0xff;
523 struct kvm_x86_mce mce;
524
525 env->exception_injected = -1;
526
527 /*
528 * There must be at least one bank in use if an MCE is pending.
529 * Find it and use its values for the event injection.
530 */
531 for (bank = 0; bank < bank_num; bank++) {
532 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
533 break;
534 }
535 }
536 assert(bank < bank_num);
537
538 mce.bank = bank;
539 mce.status = env->mce_banks[bank * 4 + 1];
540 mce.mcg_status = env->mcg_status;
541 mce.addr = env->mce_banks[bank * 4 + 2];
542 mce.misc = env->mce_banks[bank * 4 + 3];
543
1bc22652 544 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 545 }
ab443475
JK		 546 return 0;
547}
548
1dfb4dd9 549static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 550{
317ac620 551 CPUX86State *env = opaque;
b8cc45d6
GC		 552
553 if (running) {
554 env->tsc_valid = false;
555 }
556}
557
83b17af5 558unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 559{
83b17af5 560 X86CPU *cpu = X86_CPU(cs);
7e72a45c 561 return cpu->apic_id;
b164e48e
EH		 562}
563
92067bf4
IM		 564#ifndef KVM_CPUID_SIGNATURE_NEXT
565#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
566#endif
567
568static bool hyperv_hypercall_available(X86CPU *cpu)
569{
570 return cpu->hyperv_vapic ||
571 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
572}
573
574static bool hyperv_enabled(X86CPU *cpu)
575{
7bc3d711
PB		 576 CPUState *cs = CPU(cpu);
577 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
578 (hyperv_hypercall_available(cpu) ||
48a5f3bc 579 cpu->hyperv_time ||
f2a53c9e 580 cpu->hyperv_relaxed_timing ||
744b8a94 581 cpu->hyperv_crash ||
8c145d7c 582 cpu->hyperv_reset ||
46eb8f98 583 cpu->hyperv_vpindex ||
866eea9a 584 cpu->hyperv_runtime ||
ff99aa64
AS		 585 cpu->hyperv_synic ||
586 cpu->hyperv_stimer);
92067bf4
IM		 587}
588
5031283d
HZ		 589static int kvm_arch_set_tsc_khz(CPUState *cs)
590{
591 X86CPU *cpu = X86_CPU(cs);
592 CPUX86State *env = &cpu->env;
593 int r;
594
595 if (!env->tsc_khz) {
596 return 0;
597 }
598
599 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
600 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
601 -ENOTSUP;
602 if (r < 0) {
603 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
604 * TSC frequency doesn't match the one we want.
605 */
606 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
607 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
608 -ENOTSUP;
609 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 610 warn_report("TSC frequency mismatch between "
611 "VM (%" PRId64 " kHz) and host (%d kHz), "
612 "and TSC scaling unavailable",
613 env->tsc_khz, cur_freq);
5031283d
HZ		 614 return r;
615 }
616 }
617
618 return 0;
619}
620
4bb95b82
LP		 621static bool tsc_is_stable_and_known(CPUX86State *env)
622{
623 if (!env->tsc_khz) {
624 return false;
625 }
626 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
627 || env->user_tsc_khz;
628}
629
c35bd19a
EY		 630static int hyperv_handle_properties(CPUState *cs)
631{
632 X86CPU *cpu = X86_CPU(cs);
633 CPUX86State *env = &cpu->env;
634
3ddcd2ed
EH		 635 if (cpu->hyperv_time &&
636 kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
637 cpu->hyperv_time = false;
638 }
639
c35bd19a 640 if (cpu->hyperv_relaxed_timing) {
5e953812 641 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 642 }
643 if (cpu->hyperv_vapic) {
5e953812
RK		 644 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
645 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 646 }
3ddcd2ed 647 if (cpu->hyperv_time) {
5e953812
RK		 648 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
649 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
650 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
d72bc7f6
LP		 651
652 if (has_msr_hv_frequencies && tsc_is_stable_and_known(env)) {
5e953812
RK		 653 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
654 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
d72bc7f6 655 }
c35bd19a
EY		 656 }
657 if (cpu->hyperv_crash && has_msr_hv_crash) {
5e953812 658 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 659 }
5e953812 660 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
c35bd19a 661 if (cpu->hyperv_reset && has_msr_hv_reset) {
5e953812 662 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a
EY		 663 }
664 if (cpu->hyperv_vpindex && has_msr_hv_vpindex) {
5e953812 665 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a
EY		 666 }
667 if (cpu->hyperv_runtime && has_msr_hv_runtime) {
5e953812 668 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 669 }
670 if (cpu->hyperv_synic) {
c35bd19a
EY		 671 if (!has_msr_hv_synic ||
672 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
673 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
674 return -ENOSYS;
675 }
676
5e953812 677 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a
EY		 678 }
679 if (cpu->hyperv_stimer) {
680 if (!has_msr_hv_stimer) {
681 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
682 return -ENOSYS;
683 }
5e953812 684 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a
EY		 685 }
686 return 0;
687}
688
68bfd0ad
MT		 689static Error *invtsc_mig_blocker;
690
f8bb0565 691#define KVM_MAX_CPUID_ENTRIES 100
0893d460 692
20d695a9 693int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 694{
695 struct {
486bd5a2 696 struct kvm_cpuid2 cpuid;
f8bb0565 697 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 698 } QEMU_PACKED cpuid_data;
20d695a9
AF		 699 X86CPU *cpu = X86_CPU(cs);
700 CPUX86State *env = &cpu->env;
486bd5a2 701 uint32_t limit, i, j, cpuid_i;
a33609ca 702 uint32_t unused;
bb0300dc 703 struct kvm_cpuid_entry2 *c;
bb0300dc 704 uint32_t signature[3];
234cc647 705 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 706 int r;
fe44dc91 707 Error *local_err = NULL;
05330448 708
ef4cbe14
SW		 709 memset(&cpuid_data, 0, sizeof(cpuid_data));
710
05330448
AL		 711 cpuid_i = 0;
712
ddb98b5a
LP		 713 r = kvm_arch_set_tsc_khz(cs);
714 if (r < 0) {
715 goto fail;
716 }
717
718 /* vcpu's TSC frequency is either specified by user, or following
719 * the value used by KVM if the former is not present. In the
720 * latter case, we query it from KVM and record in env->tsc_khz,
721 * so that vcpu's TSC frequency can be migrated later via this field.
722 */
723 if (!env->tsc_khz) {
724 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
725 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
726 -ENOTSUP;
727 if (r > 0) {
728 env->tsc_khz = r;
729 }
730 }
731
bb0300dc 732 /* Paravirtualization CPUIDs */
234cc647
PB		 733 if (hyperv_enabled(cpu)) {
734 c = &cpuid_data.entries[cpuid_i++];
5e953812 735 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 736 if (!cpu->hyperv_vendor_id) {
737 memcpy(signature, "Microsoft Hv", 12);
738 } else {
739 size_t len = strlen(cpu->hyperv_vendor_id);
740
741 if (len > 12) {
742 error_report("hv-vendor-id truncated to 12 characters");
743 len = 12;
744 }
745 memset(signature, 0, 12);
746 memcpy(signature, cpu->hyperv_vendor_id, len);
747 }
5e953812 748 c->eax = HV_CPUID_MIN;
234cc647
PB		 749 c->ebx = signature[0];
750 c->ecx = signature[1];
751 c->edx = signature[2];
0c31b744 752
234cc647 753 c = &cpuid_data.entries[cpuid_i++];
5e953812 754 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 755 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
756 c->eax = signature[0];
234cc647
PB		 757 c->ebx = 0;
758 c->ecx = 0;
759 c->edx = 0;
eab70139
VR		 760
761 c = &cpuid_data.entries[cpuid_i++];
5e953812 762 c->function = HV_CPUID_VERSION;
eab70139
VR		 763 c->eax = 0x00001bbc;
764 c->ebx = 0x00060001;
765
766 c = &cpuid_data.entries[cpuid_i++];
5e953812 767 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 768 r = hyperv_handle_properties(cs);
769 if (r) {
770 return r;
46eb8f98 771 }
c35bd19a
EY		 772 c->eax = env->features[FEAT_HYPERV_EAX];
773 c->ebx = env->features[FEAT_HYPERV_EBX];
774 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 775
eab70139 776 c = &cpuid_data.entries[cpuid_i++];
5e953812 777 c->function = HV_CPUID_ENLIGHTMENT_INFO;
92067bf4 778 if (cpu->hyperv_relaxed_timing) {
5e953812 779 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
eab70139 780 }
2d5aa872 781 if (cpu->hyperv_vapic) {
5e953812 782 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
eab70139 783 }
92067bf4 784 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 785
786 c = &cpuid_data.entries[cpuid_i++];
5e953812 787 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 788
789 c->eax = cpu->hv_max_vps;
eab70139
VR		 790 c->ebx = 0x40;
791
234cc647 792 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 793 has_msr_hv_hypercall = true;
eab70139
VR		 794 }
795
f522d2ac
AW		 796 if (cpu->expose_kvm) {
797 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
798 c = &cpuid_data.entries[cpuid_i++];
799 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 800 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 801 c->ebx = signature[0];
802 c->ecx = signature[1];
803 c->edx = signature[2];
234cc647 804
f522d2ac
AW		 805 c = &cpuid_data.entries[cpuid_i++];
806 c->function = KVM_CPUID_FEATURES | kvm_base;
807 c->eax = env->features[FEAT_KVM];
be777326 808 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 809 }
917367aa 810
a33609ca 811 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 812
813 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 814 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
815 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
816 abort();
817 }
bb0300dc 818 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 819
820 switch (i) {
a36b1029
AL		 821 case 2: {
822 /* Keep reading function 2 till all the input is received */
823 int times;
824
a36b1029 825 c->function = i;
a33609ca
AL		 826 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
827 KVM_CPUID_FLAG_STATE_READ_NEXT;
828 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
829 times = c->eax & 0xff;
a36b1029
AL		 830
831 for (j = 1; j < times; ++j) {
f8bb0565
IM		 832 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
833 fprintf(stderr, "cpuid_data is full, no space for "
834 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
835 abort();
836 }
a33609ca 837 c = &cpuid_data.entries[cpuid_i++];
a36b1029 838 c->function = i;
a33609ca
AL		 839 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
840 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 841 }
842 break;
843 }
486bd5a2
AL		 844 case 4:
845 case 0xb:
846 case 0xd:
847 for (j = 0; ; j++) {
31e8c696
AP		 848 if (i == 0xd && j == 64) {
849 break;
850 }
486bd5a2
AL		 851 c->function = i;
852 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
853 c->index = j;
a33609ca 854 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 855
b9bec74b 856 if (i == 4 && c->eax == 0) {
486bd5a2 857 break;
b9bec74b
JK		 858 }
859 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 860 break;
b9bec74b
JK		 861 }
862 if (i == 0xd && c->eax == 0) {
31e8c696 863 continue;
b9bec74b 864 }
f8bb0565
IM		 865 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
866 fprintf(stderr, "cpuid_data is full, no space for "
867 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
868 abort();
869 }
a33609ca 870 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 871 }
872 break;
e37a5c7f
CP		 873 case 0x14: {
874 uint32_t times;
875
876 c->function = i;
877 c->index = 0;
878 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
879 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
880 times = c->eax;
881
882 for (j = 1; j <= times; ++j) {
883 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
884 fprintf(stderr, "cpuid_data is full, no space for "
885 "cpuid(eax:0x14,ecx:0x%x)\n", j);
886 abort();
887 }
888 c = &cpuid_data.entries[cpuid_i++];
889 c->function = i;
890 c->index = j;
891 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
892 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
893 }
894 break;
895 }
486bd5a2 896 default:
486bd5a2 897 c->function = i;
a33609ca
AL		 898 c->flags = 0;
899 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 900 break;
901 }
05330448 902 }
0d894367
PB		 903
904 if (limit >= 0x0a) {
0b368a10 905 uint32_t eax, edx;
0d894367 906
0b368a10
JD		 907 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
908
909 has_architectural_pmu_version = eax & 0xff;
910 if (has_architectural_pmu_version > 0) {
911 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 912
913 /* Shouldn't be more than 32, since that's the number of bits
914 * available in EBX to tell us _which_ counters are available.
915 * Play it safe.
916 */
0b368a10
JD		 917 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
918 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
919 }
920
921 if (has_architectural_pmu_version > 1) {
922 num_architectural_pmu_fixed_counters = edx & 0x1f;
923
924 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
925 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
926 }
0d894367
PB		 927 }
928 }
929 }
930
a33609ca 931 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 932
933 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 934 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
935 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
936 abort();
937 }
bb0300dc 938 c = &cpuid_data.entries[cpuid_i++];
05330448 939
05330448 940 c->function = i;
a33609ca
AL		 941 c->flags = 0;
942 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
05330448
AL		 943 }
944
b3baa152
BW		 945 /* Call Centaur's CPUID instructions they are supported. */
946 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 947 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
948
949 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 950 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
951 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
952 abort();
953 }
b3baa152
BW		 954 c = &cpuid_data.entries[cpuid_i++];
955
956 c->function = i;
957 c->flags = 0;
958 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
959 }
960 }
961
05330448
AL		 962 cpuid_data.cpuid.nent = cpuid_i;
963
e7701825 964 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 965 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 966 (CPUID_MCE | CPUID_MCA)
a60f24b5 967 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 968 uint64_t mcg_cap, unsupported_caps;
e7701825 969 int banks;
32a42024 970 int ret;
e7701825 971
a60f24b5 972 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 973 if (ret < 0) {
974 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
975 return ret;
e7701825 976 }
75d49497 977
2590f15b 978 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 979 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 980 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 981 return -ENOTSUP;
75d49497 982 }
49b69cbf 983
5120901a
EH		 984 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
985 if (unsupported_caps) {
87f8b626
AR		 986 if (unsupported_caps & MCG_LMCE_P) {
987 error_report("kvm: LMCE not supported");
988 return -ENOTSUP;
989 }
3dc6f869
AF		 990 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
991 unsupported_caps);
5120901a
EH		 992 }
993
2590f15b
EH		 994 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
995 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 996 if (ret < 0) {
997 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
998 return ret;
999 }
e7701825 1000 }
e7701825 1001
b8cc45d6
GC		 1002 qemu_add_vm_change_state_handler(cpu_update_state, env);
1003
df67696e
LJ		 1004 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1005 if (c) {
1006 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1007 !!(c->ecx & CPUID_EXT_SMX);
1008 }
1009
87f8b626
AR		 1010 if (env->mcg_cap & MCG_LMCE_P) {
1011 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1012 }
1013
d99569d9
EH		 1014 if (!env->user_tsc_khz) {
1015 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1016 invtsc_mig_blocker == NULL) {
1017 /* for migration */
1018 error_setg(&invtsc_mig_blocker,
1019 "State blocked by non-migratable CPU device"
1020 " (invtsc flag)");
fe44dc91
AA		 1021 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1022 if (local_err) {
1023 error_report_err(local_err);
1024 error_free(invtsc_mig_blocker);
1025 goto fail;
1026 }
d99569d9
EH		 1027 /* for savevm */
1028 vmstate_x86_cpu.unmigratable = 1;
1029 }
68bfd0ad
MT		 1030 }
1031
9954a158
PDJ		 1032 if (cpu->vmware_cpuid_freq
1033 /* Guests depend on 0x40000000 to detect this feature, so only expose
1034 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1035 && cpu->expose_kvm
1036 && kvm_base == KVM_CPUID_SIGNATURE
1037 /* TSC clock must be stable and known for this feature. */
4bb95b82 1038 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1039
1040 c = &cpuid_data.entries[cpuid_i++];
1041 c->function = KVM_CPUID_SIGNATURE | 0x10;
1042 c->eax = env->tsc_khz;
1043 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1044 * APIC_BUS_CYCLE_NS */
1045 c->ebx = 1000000;
1046 c->ecx = c->edx = 0;
1047
1048 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1049 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1050 }
1051
1052 cpuid_data.cpuid.nent = cpuid_i;
1053
1054 cpuid_data.cpuid.padding = 0;
1055 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1056 if (r) {
1057 goto fail;
1058 }
1059
28143b40 1060 if (has_xsave) {
fabacc0f
JK		 1061 env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1062 }
d71b62a1 1063 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1064
273c515c
PB		 1065 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1066 has_msr_tsc_aux = false;
1067 }
d1ae67f6 1068
e7429073 1069 return 0;
fe44dc91
AA		 1070
1071 fail:
1072 migrate_del_blocker(invtsc_mig_blocker);
1073 return r;
05330448
AL		 1074}
1075
50a2c6e5 1076void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1077{
20d695a9 1078 CPUX86State *env = &cpu->env;
dd673288 1079
1a5e9d2f 1080 env->xcr0 = 1;
ddced198 1081 if (kvm_irqchip_in_kernel()) {
dd673288 1082 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1083 KVM_MP_STATE_UNINITIALIZED;
1084 } else {
1085 env->mp_state = KVM_MP_STATE_RUNNABLE;
1086 }
689141dd
RK		 1087
1088 if (cpu->hyperv_synic) {
1089 int i;
1090 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1091 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1092 }
1093 }
caa5af0f
JK		 1094}
1095
e0723c45
PB		 1096void kvm_arch_do_init_vcpu(X86CPU *cpu)
1097{
1098 CPUX86State *env = &cpu->env;
1099
1100 /* APs get directly into wait-for-SIPI state. */
1101 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1102 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1103 }
1104}
1105
c3a3a7d3 1106static int kvm_get_supported_msrs(KVMState *s)
05330448 1107{
75b10c43 1108 static int kvm_supported_msrs;
c3a3a7d3 1109 int ret = 0;
05330448
AL		 1110
1111 /* first time */
75b10c43 1112 if (kvm_supported_msrs == 0) {
05330448
AL		 1113 struct kvm_msr_list msr_list, *kvm_msr_list;
1114
75b10c43 1115 kvm_supported_msrs = -1;
05330448
AL		 1116
1117 /* Obtain MSR list from KVM. These are the MSRs that we must
1118 * save/restore */
4c9f7372 1119 msr_list.nmsrs = 0;
c3a3a7d3 1120 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1121 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1122 return ret;
6fb6d245 1123 }
d9db889f
JK		 1124 /* Old kernel modules had a bug and could write beyond the provided
1125 memory. Allocate at least a safe amount of 1K. */
7267c094 1126 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1127 msr_list.nmsrs *
1128 sizeof(msr_list.indices[0])));
05330448 1129
55308450 1130 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1131 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1132 if (ret >= 0) {
1133 int i;
1134
1135 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1136 switch (kvm_msr_list->indices[i]) {
1137 case MSR_STAR:
c3a3a7d3 1138 has_msr_star = true;
1d268dec
LP		 1139 break;
1140 case MSR_VM_HSAVE_PA:
c3a3a7d3 1141 has_msr_hsave_pa = true;
1d268dec
LP		 1142 break;
1143 case MSR_TSC_AUX:
c9b8f6b6 1144 has_msr_tsc_aux = true;
1d268dec
LP		 1145 break;
1146 case MSR_TSC_ADJUST:
f28558d3 1147 has_msr_tsc_adjust = true;
1d268dec
LP		 1148 break;
1149 case MSR_IA32_TSCDEADLINE:
aa82ba54 1150 has_msr_tsc_deadline = true;
1d268dec
LP		 1151 break;
1152 case MSR_IA32_SMBASE:
fc12d72e 1153 has_msr_smbase = true;
1d268dec 1154 break;
e13713db
LA		 1155 case MSR_SMI_COUNT:
1156 has_msr_smi_count = true;
1157 break;
1d268dec 1158 case MSR_IA32_MISC_ENABLE:
21e87c46 1159 has_msr_misc_enable = true;
1d268dec
LP		 1160 break;
1161 case MSR_IA32_BNDCFGS:
79e9ebeb 1162 has_msr_bndcfgs = true;
1d268dec
LP		 1163 break;
1164 case MSR_IA32_XSS:
18cd2c17 1165 has_msr_xss = true;
3c254ab8 1166 break;
1d268dec 1167 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1168 has_msr_hv_crash = true;
1d268dec
LP		 1169 break;
1170 case HV_X64_MSR_RESET:
744b8a94 1171 has_msr_hv_reset = true;
1d268dec
LP		 1172 break;
1173 case HV_X64_MSR_VP_INDEX:
8c145d7c 1174 has_msr_hv_vpindex = true;
1d268dec
LP		 1175 break;
1176 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1177 has_msr_hv_runtime = true;
1d268dec
LP		 1178 break;
1179 case HV_X64_MSR_SCONTROL:
866eea9a 1180 has_msr_hv_synic = true;
1d268dec
LP		 1181 break;
1182 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1183 has_msr_hv_stimer = true;
1d268dec 1184 break;
d72bc7f6
LP		 1185 case HV_X64_MSR_TSC_FREQUENCY:
1186 has_msr_hv_frequencies = true;
1187 break;
a33a2cfe
PB		 1188 case MSR_IA32_SPEC_CTRL:
1189 has_msr_spec_ctrl = true;
1190 break;
ff99aa64 1191 }
05330448
AL		 1192 }
1193 }
1194
7267c094 1195 g_free(kvm_msr_list);
05330448
AL		 1196 }
1197
c3a3a7d3 1198 return ret;
05330448
AL		 1199}
1200
6410848b
PB		 1201static Notifier smram_machine_done;
1202static KVMMemoryListener smram_listener;
1203static AddressSpace smram_address_space;
1204static MemoryRegion smram_as_root;
1205static MemoryRegion smram_as_mem;
1206
1207static void register_smram_listener(Notifier *n, void *unused)
1208{
1209 MemoryRegion *smram =
1210 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1211
1212 /* Outer container... */
1213 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1214 memory_region_set_enabled(&smram_as_root, true);
1215
1216 /* ... with two regions inside: normal system memory with low
1217 * priority, and...
1218 */
1219 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1220 get_system_memory(), 0, ~0ull);
1221 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1222 memory_region_set_enabled(&smram_as_mem, true);
1223
1224 if (smram) {
1225 /* ... SMRAM with higher priority */
1226 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1227 memory_region_set_enabled(smram, true);
1228 }
1229
1230 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1231 kvm_memory_listener_register(kvm_state, &smram_listener,
1232 &smram_address_space, 1);
1233}
1234
b16565b3 1235int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1236{
11076198 1237 uint64_t identity_base = 0xfffbc000;
39d6960a 1238 uint64_t shadow_mem;
20420430 1239 int ret;
25d2e361 1240 struct utsname utsname;
20420430 1241
28143b40
TH		 1242#ifdef KVM_CAP_XSAVE
1243 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1244#endif
1245
1246#ifdef KVM_CAP_XCRS
1247 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1248#endif
1249
1250#ifdef KVM_CAP_PIT_STATE2
1251 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1252#endif
1253
c3a3a7d3 1254 ret = kvm_get_supported_msrs(s);
20420430 1255 if (ret < 0) {
20420430
SY		 1256 return ret;
1257 }
25d2e361
MT		 1258
1259 uname(&utsname);
1260 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1261
4c5b10b7 1262 /*
11076198
JK		 1263 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1264 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1265 * Since these must be part of guest physical memory, we need to allocate
1266 * them, both by setting their start addresses in the kernel and by
1267 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1268 *
1269 * Older KVM versions may not support setting the identity map base. In
1270 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1271 * size.
4c5b10b7 1272 */
11076198
JK		 1273 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1274 /* Allows up to 16M BIOSes. */
1275 identity_base = 0xfeffc000;
1276
1277 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1278 if (ret < 0) {
1279 return ret;
1280 }
4c5b10b7 1281 }
e56ff191 1282
11076198
JK		 1283 /* Set TSS base one page after EPT identity map. */
1284 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1285 if (ret < 0) {
1286 return ret;
1287 }
1288
11076198
JK		 1289 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1290 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1291 if (ret < 0) {
11076198 1292 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1293 return ret;
1294 }
3c85e74f 1295 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1296
4689b77b 1297 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1298 if (shadow_mem != -1) {
1299 shadow_mem /= 4096;
1300 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1301 if (ret < 0) {
1302 return ret;
39d6960a
JK		 1303 }
1304 }
6410848b 1305
d870cfde
GA		 1306 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1307 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1308 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1309 smram_machine_done.notify = register_smram_listener;
1310 qemu_add_machine_init_done_notifier(&smram_machine_done);
1311 }
11076198 1312 return 0;
05330448 1313}
b9bec74b 1314
05330448
AL		 1315static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1316{
1317 lhs->selector = rhs->selector;
1318 lhs->base = rhs->base;
1319 lhs->limit = rhs->limit;
1320 lhs->type = 3;
1321 lhs->present = 1;
1322 lhs->dpl = 3;
1323 lhs->db = 0;
1324 lhs->s = 1;
1325 lhs->l = 0;
1326 lhs->g = 0;
1327 lhs->avl = 0;
1328 lhs->unusable = 0;
1329}
1330
1331static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1332{
1333 unsigned flags = rhs->flags;
1334 lhs->selector = rhs->selector;
1335 lhs->base = rhs->base;
1336 lhs->limit = rhs->limit;
1337 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1338 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1339 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1340 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1341 lhs->s = (flags & DESC_S_MASK) != 0;
1342 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1343 lhs->g = (flags & DESC_G_MASK) != 0;
1344 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1345 lhs->unusable = !lhs->present;
7e680753 1346 lhs->padding = 0;
05330448
AL		 1347}
1348
1349static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1350{
1351 lhs->selector = rhs->selector;
1352 lhs->base = rhs->base;
1353 lhs->limit = rhs->limit;
d45fc087
RP		 1354 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1355 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1356 (rhs->dpl << DESC_DPL_SHIFT) |
1357 (rhs->db << DESC_B_SHIFT) |
1358 (rhs->s * DESC_S_MASK) |
1359 (rhs->l << DESC_L_SHIFT) |
1360 (rhs->g * DESC_G_MASK) |
1361 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1362}
1363
1364static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1365{
b9bec74b 1366 if (set) {
05330448 1367 *kvm_reg = *qemu_reg;
b9bec74b 1368 } else {
05330448 1369 *qemu_reg = *kvm_reg;
b9bec74b 1370 }
05330448
AL		 1371}
1372
1bc22652 1373static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1374{
1bc22652 1375 CPUX86State *env = &cpu->env;
05330448
AL		 1376 struct kvm_regs regs;
1377 int ret = 0;
1378
1379 if (!set) {
1bc22652 1380 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1381 if (ret < 0) {
05330448 1382 return ret;
b9bec74b 1383 }
05330448
AL		 1384 }
1385
1386 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1387 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1388 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1389 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1390 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1391 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1392 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1393 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1394#ifdef TARGET_X86_64
1395 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1396 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1397 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1398 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1399 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1400 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1401 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1402 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1403#endif
1404
1405 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1406 kvm_getput_reg(&regs.rip, &env->eip, set);
1407
b9bec74b 1408 if (set) {
1bc22652 1409 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1410 }
05330448
AL		 1411
1412 return ret;
1413}
1414
1bc22652 1415static int kvm_put_fpu(X86CPU *cpu)
05330448 1416{
1bc22652 1417 CPUX86State *env = &cpu->env;
05330448
AL		 1418 struct kvm_fpu fpu;
1419 int i;
1420
1421 memset(&fpu, 0, sizeof fpu);
1422 fpu.fsw = env->fpus & ~(7 << 11);
1423 fpu.fsw |= (env->fpstt & 7) << 11;
1424 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1425 fpu.last_opcode = env->fpop;
1426 fpu.last_ip = env->fpip;
1427 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1428 for (i = 0; i < 8; ++i) {
1429 fpu.ftwx |= (!env->fptags[i]) << i;
1430 }
05330448 1431 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1432 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1433 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1434 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1435 }
05330448
AL		 1436 fpu.mxcsr = env->mxcsr;
1437
1bc22652 1438 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1439}
1440
6b42494b
JK		 1441#define XSAVE_FCW_FSW 0
1442#define XSAVE_FTW_FOP 1
f1665b21
SY		 1443#define XSAVE_CWD_RIP 2
1444#define XSAVE_CWD_RDP 4
1445#define XSAVE_MXCSR 6
1446#define XSAVE_ST_SPACE 8
1447#define XSAVE_XMM_SPACE 40
1448#define XSAVE_XSTATE_BV 128
1449#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1450#define XSAVE_BNDREGS 240
1451#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1452#define XSAVE_OPMASK 272
1453#define XSAVE_ZMM_Hi256 288
1454#define XSAVE_Hi16_ZMM 416
f74eefe0 1455#define XSAVE_PKRU 672
f1665b21 1456
b503717d
EH		 1457#define XSAVE_BYTE_OFFSET(word_offset) \
1458 ((word_offset) * sizeof(((struct kvm_xsave *)0)->region[0]))
1459
1460#define ASSERT_OFFSET(word_offset, field) \
1461 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1462 offsetof(X86XSaveArea, field))
1463
1464ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1465ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1466ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1467ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1468ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1469ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1470ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1471ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1472ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1473ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1474ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1475ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1476ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1477ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1478ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1479
1bc22652 1480static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1481{
1bc22652 1482 CPUX86State *env = &cpu->env;
86cd2ea0 1483 X86XSaveArea *xsave = env->kvm_xsave_buf;
f1665b21 1484
28143b40 1485 if (!has_xsave) {
1bc22652 1486 return kvm_put_fpu(cpu);
b9bec74b 1487 }
86a57621 1488 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1489
9be38598 1490 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1491}
1492
1bc22652 1493static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1494{
1bc22652 1495 CPUX86State *env = &cpu->env;
bdfc8480 1496 struct kvm_xcrs xcrs = {};
f1665b21 1497
28143b40 1498 if (!has_xcrs) {
f1665b21 1499 return 0;
b9bec74b 1500 }
f1665b21
SY		 1501
1502 xcrs.nr_xcrs = 1;
1503 xcrs.flags = 0;
1504 xcrs.xcrs[0].xcr = 0;
1505 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1506 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1507}
1508
1bc22652 1509static int kvm_put_sregs(X86CPU *cpu)
05330448 1510{
1bc22652 1511 CPUX86State *env = &cpu->env;
05330448
AL		 1512 struct kvm_sregs sregs;
1513
0e607a80
JK		 1514 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1515 if (env->interrupt_injected >= 0) {
1516 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1517 (uint64_t)1 << (env->interrupt_injected % 64);
1518 }
05330448
AL		 1519
1520 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1521 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1522 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1523 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1524 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1525 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1526 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1527 } else {
b9bec74b
JK		 1528 set_seg(&sregs.cs, &env->segs[R_CS]);
1529 set_seg(&sregs.ds, &env->segs[R_DS]);
1530 set_seg(&sregs.es, &env->segs[R_ES]);
1531 set_seg(&sregs.fs, &env->segs[R_FS]);
1532 set_seg(&sregs.gs, &env->segs[R_GS]);
1533 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1534 }
1535
1536 set_seg(&sregs.tr, &env->tr);
1537 set_seg(&sregs.ldt, &env->ldt);
1538
1539 sregs.idt.limit = env->idt.limit;
1540 sregs.idt.base = env->idt.base;
7e680753 1541 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1542 sregs.gdt.limit = env->gdt.limit;
1543 sregs.gdt.base = env->gdt.base;
7e680753 1544 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1545
1546 sregs.cr0 = env->cr[0];
1547 sregs.cr2 = env->cr[2];
1548 sregs.cr3 = env->cr[3];
1549 sregs.cr4 = env->cr[4];
1550
02e51483
CF		 1551 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1552 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1553
1554 sregs.efer = env->efer;
1555
1bc22652 1556 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1557}
1558
d71b62a1
EH		 1559static void kvm_msr_buf_reset(X86CPU *cpu)
1560{
1561 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1562}
1563
9c600a84
EH		 1564static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1565{
1566 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1567 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1568 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1569
1570 assert((void *)(entry + 1) <= limit);
1571
1abc2cae
EH		 1572 entry->index = index;
1573 entry->reserved = 0;
1574 entry->data = value;
9c600a84
EH		 1575 msrs->nmsrs++;
1576}
1577
73e1b8f2
PB		 1578static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1579{
1580 kvm_msr_buf_reset(cpu);
1581 kvm_msr_entry_add(cpu, index, value);
1582
1583 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1584}
1585
f8d9ccf8
DDAG		 1586void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1587{
1588 int ret;
1589
1590 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1591 assert(ret == 1);
1592}
1593
7477cd38
MT		 1594static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1595{
1596 CPUX86State *env = &cpu->env;
48e1a45c 1597 int ret;
7477cd38
MT		 1598
1599 if (!has_msr_tsc_deadline) {
1600 return 0;
1601 }
1602
73e1b8f2 1603 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1604 if (ret < 0) {
1605 return ret;
1606 }
1607
1608 assert(ret == 1);
1609 return 0;
7477cd38
MT		 1610}
1611
6bdf863d
JK		 1612/*
1613 * Provide a separate write service for the feature control MSR in order to
1614 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1615 * before writing any other state because forcibly leaving nested mode
1616 * invalidates the VCPU state.
1617 */
1618static int kvm_put_msr_feature_control(X86CPU *cpu)
1619{
48e1a45c
PB		 1620 int ret;
1621
1622 if (!has_msr_feature_control) {
1623 return 0;
1624 }
6bdf863d 1625
73e1b8f2
PB		 1626 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1627 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1628 if (ret < 0) {
1629 return ret;
1630 }
1631
1632 assert(ret == 1);
1633 return 0;
6bdf863d
JK		 1634}
1635
1bc22652 1636static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1637{
1bc22652 1638 CPUX86State *env = &cpu->env;
9c600a84 1639 int i;
48e1a45c 1640 int ret;
05330448 1641
d71b62a1
EH		 1642 kvm_msr_buf_reset(cpu);
1643
9c600a84
EH		 1644 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1645 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1646 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1647 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1648 if (has_msr_star) {
9c600a84 1649 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1650 }
c3a3a7d3 1651 if (has_msr_hsave_pa) {
9c600a84 1652 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1653 }
c9b8f6b6 1654 if (has_msr_tsc_aux) {
9c600a84 1655 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1656 }
f28558d3 1657 if (has_msr_tsc_adjust) {
9c600a84 1658 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1659 }
21e87c46 1660 if (has_msr_misc_enable) {
9c600a84 1661 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1662 env->msr_ia32_misc_enable);
1663 }
fc12d72e 1664 if (has_msr_smbase) {
9c600a84 1665 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1666 }
e13713db
LA		 1667 if (has_msr_smi_count) {
1668 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1669 }
439d19f2 1670 if (has_msr_bndcfgs) {
9c600a84 1671 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1672 }
18cd2c17 1673 if (has_msr_xss) {
9c600a84 1674 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1675 }
a33a2cfe
PB		 1676 if (has_msr_spec_ctrl) {
1677 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1678 }
05330448 1679#ifdef TARGET_X86_64
25d2e361 1680 if (lm_capable_kernel) {
9c600a84
EH		 1681 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1682 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1683 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1684 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1685 }
05330448 1686#endif
a33a2cfe 1687
ff5c186b 1688 /*
0d894367
PB		 1689 * The following MSRs have side effects on the guest or are too heavy
1690 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1691 */
1692 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1693 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1694 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1695 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1696 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1697 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1698 }
55c911a5 1699 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1700 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1701 }
55c911a5 1702 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1703 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1704 }
0b368a10
JD		 1705 if (has_architectural_pmu_version > 0) {
1706 if (has_architectural_pmu_version > 1) {
1707 /* Stop the counter. */
1708 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1709 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1710 }
0d894367
PB		 1711
1712 /* Set the counter values. */
0b368a10 1713 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 1714 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1715 env->msr_fixed_counters[i]);
1716 }
0b368a10 1717 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 1718 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1719 env->msr_gp_counters[i]);
9c600a84 1720 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1721 env->msr_gp_evtsel[i]);
1722 }
0b368a10
JD		 1723 if (has_architectural_pmu_version > 1) {
1724 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1725 env->msr_global_status);
1726 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1727 env->msr_global_ovf_ctrl);
1728
1729 /* Now start the PMU. */
1730 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1731 env->msr_fixed_ctr_ctrl);
1732 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1733 env->msr_global_ctrl);
1734 }
0d894367 1735 }
da1cc323
EY		 1736 /*
1737 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1738 * only sync them to KVM on the first cpu
1739 */
1740 if (current_cpu == first_cpu) {
1741 if (has_msr_hv_hypercall) {
1742 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1743 env->msr_hv_guest_os_id);
1744 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1745 env->msr_hv_hypercall);
1746 }
1747 if (cpu->hyperv_time) {
1748 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1749 env->msr_hv_tsc);
1750 }
eab70139 1751 }
2d5aa872 1752 if (cpu->hyperv_vapic) {
9c600a84 1753 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1754 env->msr_hv_vapic);
eab70139 1755 }
f2a53c9e
AS		 1756 if (has_msr_hv_crash) {
1757 int j;
1758
5e953812 1759 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 1760 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1761 env->msr_hv_crash_params[j]);
1762
5e953812 1763 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 1764 }
46eb8f98 1765 if (has_msr_hv_runtime) {
9c600a84 1766 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1767 }
866eea9a
AS		 1768 if (cpu->hyperv_synic) {
1769 int j;
1770
09df29b6
RK		 1771 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1772
9c600a84 1773 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1774 env->msr_hv_synic_control);
9c600a84 1775 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1776 env->msr_hv_synic_evt_page);
9c600a84 1777 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1778 env->msr_hv_synic_msg_page);
1779
1780 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1781 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1782 env->msr_hv_synic_sint[j]);
1783 }
1784 }
ff99aa64
AS		 1785 if (has_msr_hv_stimer) {
1786 int j;
1787
1788 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1789 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1790 env->msr_hv_stimer_config[j]);
1791 }
1792
1793 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1794 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1795 env->msr_hv_stimer_count[j]);
1796 }
1797 }
1eabfce6 1798 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1799 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1800
9c600a84
EH		 1801 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1802 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1803 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1804 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1805 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1806 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1807 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1808 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1809 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1810 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1811 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1812 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1813 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1814 /* The CPU GPs if we write to a bit above the physical limit of
1815 * the host CPU (and KVM emulates that)
1816 */
1817 uint64_t mask = env->mtrr_var[i].mask;
1818 mask &= phys_mask;
1819
9c600a84
EH		 1820 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1821 env->mtrr_var[i].base);
112dad69 1822 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1823 }
1824 }
b77146e9
CP		 1825 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
1826 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
1827 0x14, 1, R_EAX) & 0x7;
1828
1829 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
1830 env->msr_rtit_ctrl);
1831 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
1832 env->msr_rtit_status);
1833 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
1834 env->msr_rtit_output_base);
1835 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
1836 env->msr_rtit_output_mask);
1837 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
1838 env->msr_rtit_cr3_match);
1839 for (i = 0; i < addr_num; i++) {
1840 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
1841 env->msr_rtit_addrs[i]);
1842 }
1843 }
6bdf863d
JK		 1844
1845 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1846 * kvm_put_msr_feature_control. */
ea643051 1847 }
57780495 1848 if (env->mcg_cap) {
d8da8574 1849 int i;
b9bec74b 1850
9c600a84
EH		 1851 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
1852 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 1853 if (has_msr_mcg_ext_ctl) {
1854 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
1855 }
c34d440a 1856 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 1857 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 1858 }
1859 }
1a03675d 1860
d71b62a1 1861 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 1862 if (ret < 0) {
1863 return ret;
1864 }
05330448 1865
c70b11d1
EH		 1866 if (ret < cpu->kvm_msr_buf->nmsrs) {
1867 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
1868 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
1869 (uint32_t)e->index, (uint64_t)e->data);
1870 }
1871
9c600a84 1872 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 1873 return 0;
05330448
AL		 1874}
1875
1876
1bc22652 1877static int kvm_get_fpu(X86CPU *cpu)
05330448 1878{
1bc22652 1879 CPUX86State *env = &cpu->env;
05330448
AL		 1880 struct kvm_fpu fpu;
1881 int i, ret;
1882
1bc22652 1883 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 1884 if (ret < 0) {
05330448 1885 return ret;
b9bec74b 1886 }
05330448
AL		 1887
1888 env->fpstt = (fpu.fsw >> 11) & 7;
1889 env->fpus = fpu.fsw;
1890 env->fpuc = fpu.fcw;
42cc8fa6
JK		 1891 env->fpop = fpu.last_opcode;
1892 env->fpip = fpu.last_ip;
1893 env->fpdp = fpu.last_dp;
b9bec74b
JK		 1894 for (i = 0; i < 8; ++i) {
1895 env->fptags[i] = !((fpu.ftwx >> i) & 1);
1896 }
05330448 1897 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 1898 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1899 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
1900 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 1901 }
05330448
AL		 1902 env->mxcsr = fpu.mxcsr;
1903
1904 return 0;
1905}
1906
1bc22652 1907static int kvm_get_xsave(X86CPU *cpu)
f1665b21 1908{
1bc22652 1909 CPUX86State *env = &cpu->env;
86cd2ea0 1910 X86XSaveArea *xsave = env->kvm_xsave_buf;
86a57621 1911 int ret;
f1665b21 1912
28143b40 1913 if (!has_xsave) {
1bc22652 1914 return kvm_get_fpu(cpu);
b9bec74b 1915 }
f1665b21 1916
1bc22652 1917 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 1918 if (ret < 0) {
f1665b21 1919 return ret;
0f53994f 1920 }
86a57621 1921 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 1922
f1665b21 1923 return 0;
f1665b21
SY		 1924}
1925
1bc22652 1926static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 1927{
1bc22652 1928 CPUX86State *env = &cpu->env;
f1665b21
SY		 1929 int i, ret;
1930 struct kvm_xcrs xcrs;
1931
28143b40 1932 if (!has_xcrs) {
f1665b21 1933 return 0;
b9bec74b 1934 }
f1665b21 1935
1bc22652 1936 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 1937 if (ret < 0) {
f1665b21 1938 return ret;
b9bec74b 1939 }
f1665b21 1940
b9bec74b 1941 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 1942 /* Only support xcr0 now */
0fd53fec
PB		 1943 if (xcrs.xcrs[i].xcr == 0) {
1944 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 1945 break;
1946 }
b9bec74b 1947 }
f1665b21 1948 return 0;
f1665b21
SY		 1949}
1950
1bc22652 1951static int kvm_get_sregs(X86CPU *cpu)
05330448 1952{
1bc22652 1953 CPUX86State *env = &cpu->env;
05330448 1954 struct kvm_sregs sregs;
0e607a80 1955 int bit, i, ret;
05330448 1956
1bc22652 1957 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 1958 if (ret < 0) {
05330448 1959 return ret;
b9bec74b 1960 }
05330448 1961
0e607a80
JK		 1962 /* There can only be one pending IRQ set in the bitmap at a time, so try
1963 to find it and save its number instead (-1 for none). */
1964 env->interrupt_injected = -1;
1965 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
1966 if (sregs.interrupt_bitmap[i]) {
1967 bit = ctz64(sregs.interrupt_bitmap[i]);
1968 env->interrupt_injected = i * 64 + bit;
1969 break;
1970 }
1971 }
05330448
AL		 1972
1973 get_seg(&env->segs[R_CS], &sregs.cs);
1974 get_seg(&env->segs[R_DS], &sregs.ds);
1975 get_seg(&env->segs[R_ES], &sregs.es);
1976 get_seg(&env->segs[R_FS], &sregs.fs);
1977 get_seg(&env->segs[R_GS], &sregs.gs);
1978 get_seg(&env->segs[R_SS], &sregs.ss);
1979
1980 get_seg(&env->tr, &sregs.tr);
1981 get_seg(&env->ldt, &sregs.ldt);
1982
1983 env->idt.limit = sregs.idt.limit;
1984 env->idt.base = sregs.idt.base;
1985 env->gdt.limit = sregs.gdt.limit;
1986 env->gdt.base = sregs.gdt.base;
1987
1988 env->cr[0] = sregs.cr0;
1989 env->cr[2] = sregs.cr2;
1990 env->cr[3] = sregs.cr3;
1991 env->cr[4] = sregs.cr4;
1992
05330448 1993 env->efer = sregs.efer;
cce47516
JK		 1994
1995 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 1996 x86_update_hflags(env);
05330448
AL		 1997
1998 return 0;
1999}
2000
1bc22652 2001static int kvm_get_msrs(X86CPU *cpu)
05330448 2002{
1bc22652 2003 CPUX86State *env = &cpu->env;
d71b62a1 2004 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2005 int ret, i;
fcc35e7c 2006 uint64_t mtrr_top_bits;
05330448 2007
d71b62a1
EH		 2008 kvm_msr_buf_reset(cpu);
2009
9c600a84
EH		 2010 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2011 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2012 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2013 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2014 if (has_msr_star) {
9c600a84 2015 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2016 }
c3a3a7d3 2017 if (has_msr_hsave_pa) {
9c600a84 2018 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2019 }
c9b8f6b6 2020 if (has_msr_tsc_aux) {
9c600a84 2021 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2022 }
f28558d3 2023 if (has_msr_tsc_adjust) {
9c600a84 2024 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2025 }
aa82ba54 2026 if (has_msr_tsc_deadline) {
9c600a84 2027 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2028 }
21e87c46 2029 if (has_msr_misc_enable) {
9c600a84 2030 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2031 }
fc12d72e 2032 if (has_msr_smbase) {
9c600a84 2033 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2034 }
e13713db
LA		 2035 if (has_msr_smi_count) {
2036 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2037 }
df67696e 2038 if (has_msr_feature_control) {
9c600a84 2039 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2040 }
79e9ebeb 2041 if (has_msr_bndcfgs) {
9c600a84 2042 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2043 }
18cd2c17 2044 if (has_msr_xss) {
9c600a84 2045 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2046 }
a33a2cfe
PB		 2047 if (has_msr_spec_ctrl) {
2048 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2049 }
18cd2c17 2050
b8cc45d6
GC		 2051
2052 if (!env->tsc_valid) {
9c600a84 2053 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2054 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2055 }
2056
05330448 2057#ifdef TARGET_X86_64
25d2e361 2058 if (lm_capable_kernel) {
9c600a84
EH		 2059 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2060 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2061 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2062 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2063 }
05330448 2064#endif
9c600a84
EH		 2065 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2066 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2067 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2068 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2069 }
55c911a5 2070 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2071 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2072 }
55c911a5 2073 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2074 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2075 }
0b368a10
JD		 2076 if (has_architectural_pmu_version > 0) {
2077 if (has_architectural_pmu_version > 1) {
2078 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2079 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2080 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2081 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2082 }
2083 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2084 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2085 }
0b368a10 2086 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2087 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2088 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2089 }
2090 }
1a03675d 2091
57780495 2092 if (env->mcg_cap) {
9c600a84
EH		 2093 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2094 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2095 if (has_msr_mcg_ext_ctl) {
2096 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2097 }
b9bec74b 2098 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2099 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2100 }
57780495 2101 }
57780495 2102
1c90ef26 2103 if (has_msr_hv_hypercall) {
9c600a84
EH		 2104 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2105 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2106 }
2d5aa872 2107 if (cpu->hyperv_vapic) {
9c600a84 2108 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2109 }
3ddcd2ed 2110 if (cpu->hyperv_time) {
9c600a84 2111 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2112 }
f2a53c9e
AS		 2113 if (has_msr_hv_crash) {
2114 int j;
2115
5e953812 2116 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2117 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2118 }
2119 }
46eb8f98 2120 if (has_msr_hv_runtime) {
9c600a84 2121 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2122 }
866eea9a
AS		 2123 if (cpu->hyperv_synic) {
2124 uint32_t msr;
2125
9c600a84 2126 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2127 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2128 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2129 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2130 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2131 }
2132 }
ff99aa64
AS		 2133 if (has_msr_hv_stimer) {
2134 uint32_t msr;
2135
2136 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2137 msr++) {
9c600a84 2138 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2139 }
2140 }
1eabfce6 2141 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2142 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2143 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2144 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2145 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2146 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2147 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2148 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2149 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2150 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2151 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2152 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2153 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2154 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2155 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2156 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2157 }
2158 }
5ef68987 2159
b77146e9
CP		 2160 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2161 int addr_num =
2162 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2163
2164 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2165 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2166 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2167 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2168 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2169 for (i = 0; i < addr_num; i++) {
2170 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2171 }
2172 }
2173
d71b62a1 2174 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2175 if (ret < 0) {
05330448 2176 return ret;
b9bec74b 2177 }
05330448 2178
c70b11d1
EH		 2179 if (ret < cpu->kvm_msr_buf->nmsrs) {
2180 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2181 error_report("error: failed to get MSR 0x%" PRIx32,
2182 (uint32_t)e->index);
2183 }
2184
9c600a84 2185 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2186 /*
2187 * MTRR masks: Each mask consists of 5 parts
2188 * a 10..0: must be zero
2189 * b 11 : valid bit
2190 * c n-1.12: actual mask bits
2191 * d 51..n: reserved must be zero
2192 * e 63.52: reserved must be zero
2193 *
2194 * 'n' is the number of physical bits supported by the CPU and is
2195 * apparently always <= 52. We know our 'n' but don't know what
2196 * the destinations 'n' is; it might be smaller, in which case
2197 * it masks (c) on loading. It might be larger, in which case
2198 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2199 * we're migrating to.
2200 */
2201
2202 if (cpu->fill_mtrr_mask) {
2203 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2204 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2205 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2206 } else {
2207 mtrr_top_bits = 0;
2208 }
2209
05330448 2210 for (i = 0; i < ret; i++) {
0d894367
PB		 2211 uint32_t index = msrs[i].index;
2212 switch (index) {
05330448
AL		 2213 case MSR_IA32_SYSENTER_CS:
2214 env->sysenter_cs = msrs[i].data;
2215 break;
2216 case MSR_IA32_SYSENTER_ESP:
2217 env->sysenter_esp = msrs[i].data;
2218 break;
2219 case MSR_IA32_SYSENTER_EIP:
2220 env->sysenter_eip = msrs[i].data;
2221 break;
0c03266a
JK		 2222 case MSR_PAT:
2223 env->pat = msrs[i].data;
2224 break;
05330448
AL		 2225 case MSR_STAR:
2226 env->star = msrs[i].data;
2227 break;
2228#ifdef TARGET_X86_64
2229 case MSR_CSTAR:
2230 env->cstar = msrs[i].data;
2231 break;
2232 case MSR_KERNELGSBASE:
2233 env->kernelgsbase = msrs[i].data;
2234 break;
2235 case MSR_FMASK:
2236 env->fmask = msrs[i].data;
2237 break;
2238 case MSR_LSTAR:
2239 env->lstar = msrs[i].data;
2240 break;
2241#endif
2242 case MSR_IA32_TSC:
2243 env->tsc = msrs[i].data;
2244 break;
c9b8f6b6
AS		 2245 case MSR_TSC_AUX:
2246 env->tsc_aux = msrs[i].data;
2247 break;
f28558d3
WA		 2248 case MSR_TSC_ADJUST:
2249 env->tsc_adjust = msrs[i].data;
2250 break;
aa82ba54
LJ		 2251 case MSR_IA32_TSCDEADLINE:
2252 env->tsc_deadline = msrs[i].data;
2253 break;
aa851e36
MT		 2254 case MSR_VM_HSAVE_PA:
2255 env->vm_hsave = msrs[i].data;
2256 break;
1a03675d
GC		 2257 case MSR_KVM_SYSTEM_TIME:
2258 env->system_time_msr = msrs[i].data;
2259 break;
2260 case MSR_KVM_WALL_CLOCK:
2261 env->wall_clock_msr = msrs[i].data;
2262 break;
57780495
MT		 2263 case MSR_MCG_STATUS:
2264 env->mcg_status = msrs[i].data;
2265 break;
2266 case MSR_MCG_CTL:
2267 env->mcg_ctl = msrs[i].data;
2268 break;
87f8b626
AR		 2269 case MSR_MCG_EXT_CTL:
2270 env->mcg_ext_ctl = msrs[i].data;
2271 break;
21e87c46
AK		 2272 case MSR_IA32_MISC_ENABLE:
2273 env->msr_ia32_misc_enable = msrs[i].data;
2274 break;
fc12d72e
PB		 2275 case MSR_IA32_SMBASE:
2276 env->smbase = msrs[i].data;
2277 break;
e13713db
LA		 2278 case MSR_SMI_COUNT:
2279 env->msr_smi_count = msrs[i].data;
2280 break;
0779caeb
ACL		 2281 case MSR_IA32_FEATURE_CONTROL:
2282 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2283 break;
79e9ebeb
LJ		 2284 case MSR_IA32_BNDCFGS:
2285 env->msr_bndcfgs = msrs[i].data;
2286 break;
18cd2c17
WL		 2287 case MSR_IA32_XSS:
2288 env->xss = msrs[i].data;
2289 break;
57780495 2290 default:
57780495
MT		 2291 if (msrs[i].index >= MSR_MC0_CTL &&
2292 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2293 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2294 }
d8da8574 2295 break;
f6584ee2
GN		 2296 case MSR_KVM_ASYNC_PF_EN:
2297 env->async_pf_en_msr = msrs[i].data;
2298 break;
bc9a839d
MT		 2299 case MSR_KVM_PV_EOI_EN:
2300 env->pv_eoi_en_msr = msrs[i].data;
2301 break;
917367aa
MT		 2302 case MSR_KVM_STEAL_TIME:
2303 env->steal_time_msr = msrs[i].data;
2304 break;
0d894367
PB		 2305 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2306 env->msr_fixed_ctr_ctrl = msrs[i].data;
2307 break;
2308 case MSR_CORE_PERF_GLOBAL_CTRL:
2309 env->msr_global_ctrl = msrs[i].data;
2310 break;
2311 case MSR_CORE_PERF_GLOBAL_STATUS:
2312 env->msr_global_status = msrs[i].data;
2313 break;
2314 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2315 env->msr_global_ovf_ctrl = msrs[i].data;
2316 break;
2317 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2318 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2319 break;
2320 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2321 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2322 break;
2323 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2324 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2325 break;
1c90ef26
VR		 2326 case HV_X64_MSR_HYPERCALL:
2327 env->msr_hv_hypercall = msrs[i].data;
2328 break;
2329 case HV_X64_MSR_GUEST_OS_ID:
2330 env->msr_hv_guest_os_id = msrs[i].data;
2331 break;
5ef68987
VR		 2332 case HV_X64_MSR_APIC_ASSIST_PAGE:
2333 env->msr_hv_vapic = msrs[i].data;
2334 break;
48a5f3bc
VR		 2335 case HV_X64_MSR_REFERENCE_TSC:
2336 env->msr_hv_tsc = msrs[i].data;
2337 break;
f2a53c9e
AS		 2338 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2339 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2340 break;
46eb8f98
AS		 2341 case HV_X64_MSR_VP_RUNTIME:
2342 env->msr_hv_runtime = msrs[i].data;
2343 break;
866eea9a
AS		 2344 case HV_X64_MSR_SCONTROL:
2345 env->msr_hv_synic_control = msrs[i].data;
2346 break;
866eea9a
AS		 2347 case HV_X64_MSR_SIEFP:
2348 env->msr_hv_synic_evt_page = msrs[i].data;
2349 break;
2350 case HV_X64_MSR_SIMP:
2351 env->msr_hv_synic_msg_page = msrs[i].data;
2352 break;
2353 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2354 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2355 break;
2356 case HV_X64_MSR_STIMER0_CONFIG:
2357 case HV_X64_MSR_STIMER1_CONFIG:
2358 case HV_X64_MSR_STIMER2_CONFIG:
2359 case HV_X64_MSR_STIMER3_CONFIG:
2360 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2361 msrs[i].data;
2362 break;
2363 case HV_X64_MSR_STIMER0_COUNT:
2364 case HV_X64_MSR_STIMER1_COUNT:
2365 case HV_X64_MSR_STIMER2_COUNT:
2366 case HV_X64_MSR_STIMER3_COUNT:
2367 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2368 msrs[i].data;
866eea9a 2369 break;
d1ae67f6
AW		 2370 case MSR_MTRRdefType:
2371 env->mtrr_deftype = msrs[i].data;
2372 break;
2373 case MSR_MTRRfix64K_00000:
2374 env->mtrr_fixed[0] = msrs[i].data;
2375 break;
2376 case MSR_MTRRfix16K_80000:
2377 env->mtrr_fixed[1] = msrs[i].data;
2378 break;
2379 case MSR_MTRRfix16K_A0000:
2380 env->mtrr_fixed[2] = msrs[i].data;
2381 break;
2382 case MSR_MTRRfix4K_C0000:
2383 env->mtrr_fixed[3] = msrs[i].data;
2384 break;
2385 case MSR_MTRRfix4K_C8000:
2386 env->mtrr_fixed[4] = msrs[i].data;
2387 break;
2388 case MSR_MTRRfix4K_D0000:
2389 env->mtrr_fixed[5] = msrs[i].data;
2390 break;
2391 case MSR_MTRRfix4K_D8000:
2392 env->mtrr_fixed[6] = msrs[i].data;
2393 break;
2394 case MSR_MTRRfix4K_E0000:
2395 env->mtrr_fixed[7] = msrs[i].data;
2396 break;
2397 case MSR_MTRRfix4K_E8000:
2398 env->mtrr_fixed[8] = msrs[i].data;
2399 break;
2400 case MSR_MTRRfix4K_F0000:
2401 env->mtrr_fixed[9] = msrs[i].data;
2402 break;
2403 case MSR_MTRRfix4K_F8000:
2404 env->mtrr_fixed[10] = msrs[i].data;
2405 break;
2406 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2407 if (index & 1) {
fcc35e7c
DDAG		 2408 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2409 mtrr_top_bits;
d1ae67f6
AW		 2410 } else {
2411 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2412 }
2413 break;
a33a2cfe
PB		 2414 case MSR_IA32_SPEC_CTRL:
2415 env->spec_ctrl = msrs[i].data;
2416 break;
b77146e9
CP		 2417 case MSR_IA32_RTIT_CTL:
2418 env->msr_rtit_ctrl = msrs[i].data;
2419 break;
2420 case MSR_IA32_RTIT_STATUS:
2421 env->msr_rtit_status = msrs[i].data;
2422 break;
2423 case MSR_IA32_RTIT_OUTPUT_BASE:
2424 env->msr_rtit_output_base = msrs[i].data;
2425 break;
2426 case MSR_IA32_RTIT_OUTPUT_MASK:
2427 env->msr_rtit_output_mask = msrs[i].data;
2428 break;
2429 case MSR_IA32_RTIT_CR3_MATCH:
2430 env->msr_rtit_cr3_match = msrs[i].data;
2431 break;
2432 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2433 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2434 break;
05330448
AL		 2435 }
2436 }
2437
2438 return 0;
2439}
2440
1bc22652 2441static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2442{
1bc22652 2443 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2444
1bc22652 2445 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2446}
2447
23d02d9b 2448static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2449{
259186a7 2450 CPUState *cs = CPU(cpu);
23d02d9b 2451 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2452 struct kvm_mp_state mp_state;
2453 int ret;
2454
259186a7 2455 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2456 if (ret < 0) {
2457 return ret;
2458 }
2459 env->mp_state = mp_state.mp_state;
c14750e8 2460 if (kvm_irqchip_in_kernel()) {
259186a7 2461 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2462 }
9bdbe550
HB		 2463 return 0;
2464}
2465
1bc22652 2466static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2467{
02e51483 2468 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2469 struct kvm_lapic_state kapic;
2470 int ret;
2471
3d4b2649 2472 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2473 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2474 if (ret < 0) {
2475 return ret;
2476 }
2477
2478 kvm_get_apic_state(apic, &kapic);
2479 }
2480 return 0;
2481}
2482
1bc22652 2483static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2484{
fc12d72e 2485 CPUState *cs = CPU(cpu);
1bc22652 2486 CPUX86State *env = &cpu->env;
076796f8 2487 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2488
2489 if (!kvm_has_vcpu_events()) {
2490 return 0;
2491 }
2492
31827373
JK		 2493 events.exception.injected = (env->exception_injected >= 0);
2494 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2495 events.exception.has_error_code = env->has_error_code;
2496 events.exception.error_code = env->error_code;
7e680753 2497 events.exception.pad = 0;
a0fb002c
JK		 2498
2499 events.interrupt.injected = (env->interrupt_injected >= 0);
2500 events.interrupt.nr = env->interrupt_injected;
2501 events.interrupt.soft = env->soft_interrupt;
2502
2503 events.nmi.injected = env->nmi_injected;
2504 events.nmi.pending = env->nmi_pending;
2505 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
7e680753 2506 events.nmi.pad = 0;
a0fb002c
JK		 2507
2508 events.sipi_vector = env->sipi_vector;
68c6efe0 2509 events.flags = 0;
a0fb002c 2510
fc12d72e
PB		 2511 if (has_msr_smbase) {
2512 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2513 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2514 if (kvm_irqchip_in_kernel()) {
2515 /* As soon as these are moved to the kernel, remove them
2516 * from cs->interrupt_request.
2517 */
2518 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2519 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2520 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2521 } else {
2522 /* Keep these in cs->interrupt_request. */
2523 events.smi.pending = 0;
2524 events.smi.latched_init = 0;
2525 }
fc3a1fd7
DDAG		 2526 /* Stop SMI delivery on old machine types to avoid a reboot
2527 * on an inward migration of an old VM.
2528 */
2529 if (!cpu->kvm_no_smi_migration) {
2530 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2531 }
fc12d72e
PB		 2532 }
2533
ea643051 2534 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2535 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2536 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2537 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2538 }
ea643051 2539 }
aee028b9 2540
1bc22652 2541 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2542}
2543
1bc22652 2544static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2545{
1bc22652 2546 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2547 struct kvm_vcpu_events events;
2548 int ret;
2549
2550 if (!kvm_has_vcpu_events()) {
2551 return 0;
2552 }
2553
fc12d72e 2554 memset(&events, 0, sizeof(events));
1bc22652 2555 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2556 if (ret < 0) {
2557 return ret;
2558 }
31827373 2559 env->exception_injected =
a0fb002c
JK		 2560 events.exception.injected ? events.exception.nr : -1;
2561 env->has_error_code = events.exception.has_error_code;
2562 env->error_code = events.exception.error_code;
2563
2564 env->interrupt_injected =
2565 events.interrupt.injected ? events.interrupt.nr : -1;
2566 env->soft_interrupt = events.interrupt.soft;
2567
2568 env->nmi_injected = events.nmi.injected;
2569 env->nmi_pending = events.nmi.pending;
2570 if (events.nmi.masked) {
2571 env->hflags2 |= HF2_NMI_MASK;
2572 } else {
2573 env->hflags2 &= ~HF2_NMI_MASK;
2574 }
2575
fc12d72e
PB		 2576 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2577 if (events.smi.smm) {
2578 env->hflags |= HF_SMM_MASK;
2579 } else {
2580 env->hflags &= ~HF_SMM_MASK;
2581 }
2582 if (events.smi.pending) {
2583 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2584 } else {
2585 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2586 }
2587 if (events.smi.smm_inside_nmi) {
2588 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2589 } else {
2590 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2591 }
2592 if (events.smi.latched_init) {
2593 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2594 } else {
2595 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2596 }
2597 }
2598
a0fb002c 2599 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2600
2601 return 0;
2602}
2603
1bc22652 2604static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2605{
ed2803da 2606 CPUState *cs = CPU(cpu);
1bc22652 2607 CPUX86State *env = &cpu->env;
b0b1d690 2608 int ret = 0;
b0b1d690
JK		 2609 unsigned long reinject_trap = 0;
2610
2611 if (!kvm_has_vcpu_events()) {
2612 if (env->exception_injected == 1) {
2613 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2614 } else if (env->exception_injected == 3) {
2615 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2616 }
2617 env->exception_injected = -1;
2618 }
2619
2620 /*
2621 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2622 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2623 * by updating the debug state once again if single-stepping is on.
2624 * Another reason to call kvm_update_guest_debug here is a pending debug
2625 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2626 * reinject them via SET_GUEST_DEBUG.
2627 */
2628 if (reinject_trap ||
ed2803da 2629 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2630 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2631 }
b0b1d690
JK		 2632 return ret;
2633}
2634
1bc22652 2635static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2636{
1bc22652 2637 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2638 struct kvm_debugregs dbgregs;
2639 int i;
2640
2641 if (!kvm_has_debugregs()) {
2642 return 0;
2643 }
2644
2645 for (i = 0; i < 4; i++) {
2646 dbgregs.db[i] = env->dr[i];
2647 }
2648 dbgregs.dr6 = env->dr[6];
2649 dbgregs.dr7 = env->dr[7];
2650 dbgregs.flags = 0;
2651
1bc22652 2652 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2653}
2654
1bc22652 2655static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2656{
1bc22652 2657 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2658 struct kvm_debugregs dbgregs;
2659 int i, ret;
2660
2661 if (!kvm_has_debugregs()) {
2662 return 0;
2663 }
2664
1bc22652 2665 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2666 if (ret < 0) {
b9bec74b 2667 return ret;
ff44f1a3
JK		 2668 }
2669 for (i = 0; i < 4; i++) {
2670 env->dr[i] = dbgregs.db[i];
2671 }
2672 env->dr[4] = env->dr[6] = dbgregs.dr6;
2673 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2674
2675 return 0;
2676}
2677
20d695a9 2678int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2679{
20d695a9 2680 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2681 int ret;
2682
2fa45344 2683 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2684
48e1a45c 2685 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2686 ret = kvm_put_msr_feature_control(x86_cpu);
2687 if (ret < 0) {
2688 return ret;
2689 }
2690 }
2691
36f96c4b
HZ		 2692 if (level == KVM_PUT_FULL_STATE) {
2693 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2694 * because TSC frequency mismatch shouldn't abort migration,
2695 * unless the user explicitly asked for a more strict TSC
2696 * setting (e.g. using an explicit "tsc-freq" option).
2697 */
2698 kvm_arch_set_tsc_khz(cpu);
2699 }
2700
1bc22652 2701 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2702 if (ret < 0) {
05330448 2703 return ret;
b9bec74b 2704 }
1bc22652 2705 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2706 if (ret < 0) {
f1665b21 2707 return ret;
b9bec74b 2708 }
1bc22652 2709 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2710 if (ret < 0) {
05330448 2711 return ret;
b9bec74b 2712 }
1bc22652 2713 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2714 if (ret < 0) {
05330448 2715 return ret;
b9bec74b 2716 }
ab443475 2717 /* must be before kvm_put_msrs */
1bc22652 2718 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2719 if (ret < 0) {
2720 return ret;
2721 }
1bc22652 2722 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2723 if (ret < 0) {
05330448 2724 return ret;
b9bec74b 2725 }
4fadfa00
PH		 2726 ret = kvm_put_vcpu_events(x86_cpu, level);
2727 if (ret < 0) {
2728 return ret;
2729 }
ea643051 2730 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2731 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2732 if (ret < 0) {
680c1c6f
JK		 2733 return ret;
2734 }
ea643051 2735 }
7477cd38
MT		 2736
2737 ret = kvm_put_tscdeadline_msr(x86_cpu);
2738 if (ret < 0) {
2739 return ret;
2740 }
1bc22652 2741 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2742 if (ret < 0) {
b0b1d690 2743 return ret;
b9bec74b 2744 }
b0b1d690 2745 /* must be last */
1bc22652 2746 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2747 if (ret < 0) {
ff44f1a3 2748 return ret;
b9bec74b 2749 }
05330448
AL		 2750 return 0;
2751}
2752
20d695a9 2753int kvm_arch_get_registers(CPUState *cs)
05330448 2754{
20d695a9 2755 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2756 int ret;
2757
20d695a9 2758 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2759
4fadfa00 2760 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2761 if (ret < 0) {
f4f1110e 2762 goto out;
b9bec74b 2763 }
4fadfa00
PH		 2764 /*
2765 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2766 * KVM_GET_REGS and KVM_GET_SREGS.
2767 */
2768 ret = kvm_get_mp_state(cpu);
b9bec74b 2769 if (ret < 0) {
f4f1110e 2770 goto out;
b9bec74b 2771 }
4fadfa00 2772 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2773 if (ret < 0) {
f4f1110e 2774 goto out;
b9bec74b 2775 }
4fadfa00 2776 ret = kvm_get_xsave(cpu);
b9bec74b 2777 if (ret < 0) {
f4f1110e 2778 goto out;
b9bec74b 2779 }
4fadfa00 2780 ret = kvm_get_xcrs(cpu);
b9bec74b 2781 if (ret < 0) {
f4f1110e 2782 goto out;
b9bec74b 2783 }
4fadfa00 2784 ret = kvm_get_sregs(cpu);
b9bec74b 2785 if (ret < 0) {
f4f1110e 2786 goto out;
b9bec74b 2787 }
4fadfa00 2788 ret = kvm_get_msrs(cpu);
680c1c6f 2789 if (ret < 0) {
f4f1110e 2790 goto out;
680c1c6f 2791 }
4fadfa00 2792 ret = kvm_get_apic(cpu);
b9bec74b 2793 if (ret < 0) {
f4f1110e 2794 goto out;
b9bec74b 2795 }
1bc22652 2796 ret = kvm_get_debugregs(cpu);
b9bec74b 2797 if (ret < 0) {
f4f1110e 2798 goto out;
b9bec74b 2799 }
f4f1110e
RH		 2800 ret = 0;
2801 out:
2802 cpu_sync_bndcs_hflags(&cpu->env);
2803 return ret;
05330448
AL		 2804}
2805
20d695a9 2806void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2807{
20d695a9
AF		 2808 X86CPU *x86_cpu = X86_CPU(cpu);
2809 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 2810 int ret;
2811
276ce815 2812 /* Inject NMI */
fc12d72e
PB		 2813 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
2814 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
2815 qemu_mutex_lock_iothread();
2816 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
2817 qemu_mutex_unlock_iothread();
2818 DPRINTF("injected NMI\n");
2819 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
2820 if (ret < 0) {
2821 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
2822 strerror(-ret));
2823 }
2824 }
2825 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
2826 qemu_mutex_lock_iothread();
2827 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
2828 qemu_mutex_unlock_iothread();
2829 DPRINTF("injected SMI\n");
2830 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
2831 if (ret < 0) {
2832 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
2833 strerror(-ret));
2834 }
ce377af3 2835 }
276ce815
LJ		 2836 }
2837
15eafc2e 2838 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 2839 qemu_mutex_lock_iothread();
2840 }
2841
e0723c45
PB		 2842 /* Force the VCPU out of its inner loop to process any INIT requests
2843 * or (for userspace APIC, but it is cheap to combine the checks here)
2844 * pending TPR access reports.
2845 */
2846 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 2847 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
2848 !(env->hflags & HF_SMM_MASK)) {
2849 cpu->exit_request = 1;
2850 }
2851 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
2852 cpu->exit_request = 1;
2853 }
e0723c45 2854 }
05330448 2855
15eafc2e 2856 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 2857 /* Try to inject an interrupt if the guest can accept it */
2858 if (run->ready_for_interrupt_injection &&
259186a7 2859 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 2860 (env->eflags & IF_MASK)) {
2861 int irq;
2862
259186a7 2863 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 2864 irq = cpu_get_pic_interrupt(env);
2865 if (irq >= 0) {
2866 struct kvm_interrupt intr;
2867
2868 intr.irq = irq;
db1669bc 2869 DPRINTF("injected interrupt %d\n", irq);
1bc22652 2870 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 2871 if (ret < 0) {
2872 fprintf(stderr,
2873 "KVM: injection failed, interrupt lost (%s)\n",
2874 strerror(-ret));
2875 }
db1669bc
JK		 2876 }
2877 }
05330448 2878
db1669bc
JK		 2879 /* If we have an interrupt but the guest is not ready to receive an
2880 * interrupt, request an interrupt window exit. This will
2881 * cause a return to userspace as soon as the guest is ready to
2882 * receive interrupts. */
259186a7 2883 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 2884 run->request_interrupt_window = 1;
2885 } else {
2886 run->request_interrupt_window = 0;
2887 }
2888
2889 DPRINTF("setting tpr\n");
02e51483 2890 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 2891
2892 qemu_mutex_unlock_iothread();
db1669bc 2893 }
05330448
AL		 2894}
2895
4c663752 2896MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 2897{
20d695a9
AF		 2898 X86CPU *x86_cpu = X86_CPU(cpu);
2899 CPUX86State *env = &x86_cpu->env;
2900
fc12d72e
PB		 2901 if (run->flags & KVM_RUN_X86_SMM) {
2902 env->hflags |= HF_SMM_MASK;
2903 } else {
f5c052b9 2904 env->hflags &= ~HF_SMM_MASK;
fc12d72e 2905 }
b9bec74b 2906 if (run->if_flag) {
05330448 2907 env->eflags |= IF_MASK;
b9bec74b 2908 } else {
05330448 2909 env->eflags &= ~IF_MASK;
b9bec74b 2910 }
4b8523ee
JK		 2911
2912 /* We need to protect the apic state against concurrent accesses from
2913 * different threads in case the userspace irqchip is used. */
2914 if (!kvm_irqchip_in_kernel()) {
2915 qemu_mutex_lock_iothread();
2916 }
02e51483
CF		 2917 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
2918 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 2919 if (!kvm_irqchip_in_kernel()) {
2920 qemu_mutex_unlock_iothread();
2921 }
f794aa4a 2922 return cpu_get_mem_attrs(env);
05330448
AL		 2923}
2924
20d695a9 2925int kvm_arch_process_async_events(CPUState *cs)
0af691d7 2926{
20d695a9
AF		 2927 X86CPU *cpu = X86_CPU(cs);
2928 CPUX86State *env = &cpu->env;
232fc23b 2929
259186a7 2930 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 2931 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2932 assert(env->mcg_cap);
2933
259186a7 2934 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 2935
dd1750d7 2936 kvm_cpu_synchronize_state(cs);
ab443475
JK		 2937
2938 if (env->exception_injected == EXCP08_DBLE) {
2939 /* this means triple fault */
cf83f140 2940 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 2941 cs->exit_request = 1;
ab443475
JK		 2942 return 0;
2943 }
2944 env->exception_injected = EXCP12_MCHK;
2945 env->has_error_code = 0;
2946
259186a7 2947 cs->halted = 0;
ab443475
JK		 2948 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
2949 env->mp_state = KVM_MP_STATE_RUNNABLE;
2950 }
2951 }
2952
fc12d72e
PB		 2953 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
2954 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 2955 kvm_cpu_synchronize_state(cs);
2956 do_cpu_init(cpu);
2957 }
2958
db1669bc
JK		 2959 if (kvm_irqchip_in_kernel()) {
2960 return 0;
2961 }
2962
259186a7
AF		 2963 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
2964 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 2965 apic_poll_irq(cpu->apic_state);
5d62c43a 2966 }
259186a7 2967 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 2968 (env->eflags & IF_MASK)) ||
259186a7
AF		 2969 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2970 cs->halted = 0;
6792a57b 2971 }
259186a7 2972 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 2973 kvm_cpu_synchronize_state(cs);
232fc23b 2974 do_cpu_sipi(cpu);
0af691d7 2975 }
259186a7
AF		 2976 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
2977 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 2978 kvm_cpu_synchronize_state(cs);
02e51483 2979 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 2980 env->tpr_access_type);
2981 }
0af691d7 2982
259186a7 2983 return cs->halted;
0af691d7
MT		 2984}
2985
839b5630 2986static int kvm_handle_halt(X86CPU *cpu)
05330448 2987{
259186a7 2988 CPUState *cs = CPU(cpu);
839b5630
AF		 2989 CPUX86State *env = &cpu->env;
2990
259186a7 2991 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 2992 (env->eflags & IF_MASK)) &&
259186a7
AF		 2993 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
2994 cs->halted = 1;
bb4ea393 2995 return EXCP_HLT;
05330448
AL		 2996 }
2997
bb4ea393 2998 return 0;
05330448
AL		 2999}
3000
f7575c96 3001static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3002{
f7575c96
AF		 3003 CPUState *cs = CPU(cpu);
3004 struct kvm_run *run = cs->kvm_run;
d362e757 3005
02e51483 3006 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3007 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3008 : TPR_ACCESS_READ);
3009 return 1;
3010}
3011
f17ec444 3012int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3013{
38972938 3014 static const uint8_t int3 = 0xcc;
64bf3f4e 3015
f17ec444
AF		 3016 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3017 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3018 return -EINVAL;
b9bec74b 3019 }
e22a25c9
AL		 3020 return 0;
3021}
3022
f17ec444 3023int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3024{
3025 uint8_t int3;
3026
f17ec444
AF		 3027 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3028 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3029 return -EINVAL;
b9bec74b 3030 }
e22a25c9
AL		 3031 return 0;
3032}
3033
3034static struct {
3035 target_ulong addr;
3036 int len;
3037 int type;
3038} hw_breakpoint[4];
3039
3040static int nb_hw_breakpoint;
3041
3042static int find_hw_breakpoint(target_ulong addr, int len, int type)
3043{
3044 int n;
3045
b9bec74b 3046 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3047 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3048 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3049 return n;
b9bec74b
JK		 3050 }
3051 }
e22a25c9
AL		 3052 return -1;
3053}
3054
3055int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3056 target_ulong len, int type)
3057{
3058 switch (type) {
3059 case GDB_BREAKPOINT_HW:
3060 len = 1;
3061 break;
3062 case GDB_WATCHPOINT_WRITE:
3063 case GDB_WATCHPOINT_ACCESS:
3064 switch (len) {
3065 case 1:
3066 break;
3067 case 2:
3068 case 4:
3069 case 8:
b9bec74b 3070 if (addr & (len - 1)) {
e22a25c9 3071 return -EINVAL;
b9bec74b 3072 }
e22a25c9
AL		 3073 break;
3074 default:
3075 return -EINVAL;
3076 }
3077 break;
3078 default:
3079 return -ENOSYS;
3080 }
3081
b9bec74b 3082 if (nb_hw_breakpoint == 4) {
e22a25c9 3083 return -ENOBUFS;
b9bec74b
JK		 3084 }
3085 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3086 return -EEXIST;
b9bec74b 3087 }
e22a25c9
AL		 3088 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3089 hw_breakpoint[nb_hw_breakpoint].len = len;
3090 hw_breakpoint[nb_hw_breakpoint].type = type;
3091 nb_hw_breakpoint++;
3092
3093 return 0;
3094}
3095
3096int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3097 target_ulong len, int type)
3098{
3099 int n;
3100
3101 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3102 if (n < 0) {
e22a25c9 3103 return -ENOENT;
b9bec74b 3104 }
e22a25c9
AL		 3105 nb_hw_breakpoint--;
3106 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3107
3108 return 0;
3109}
3110
3111void kvm_arch_remove_all_hw_breakpoints(void)
3112{
3113 nb_hw_breakpoint = 0;
3114}
3115
3116static CPUWatchpoint hw_watchpoint;
3117
a60f24b5 3118static int kvm_handle_debug(X86CPU *cpu,
48405526 3119 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3120{
ed2803da 3121 CPUState *cs = CPU(cpu);
a60f24b5 3122 CPUX86State *env = &cpu->env;
f2574737 3123 int ret = 0;
e22a25c9
AL		 3124 int n;
3125
3126 if (arch_info->exception == 1) {
3127 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3128 if (cs->singlestep_enabled) {
f2574737 3129 ret = EXCP_DEBUG;
b9bec74b 3130 }
e22a25c9 3131 } else {
b9bec74b
JK		 3132 for (n = 0; n < 4; n++) {
3133 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3134 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3135 case 0x0:
f2574737 3136 ret = EXCP_DEBUG;
e22a25c9
AL		 3137 break;
3138 case 0x1:
f2574737 3139 ret = EXCP_DEBUG;
ff4700b0 3140 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3141 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3142 hw_watchpoint.flags = BP_MEM_WRITE;
3143 break;
3144 case 0x3:
f2574737 3145 ret = EXCP_DEBUG;
ff4700b0 3146 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3147 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3148 hw_watchpoint.flags = BP_MEM_ACCESS;
3149 break;
3150 }
b9bec74b
JK		 3151 }
3152 }
e22a25c9 3153 }
ff4700b0 3154 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3155 ret = EXCP_DEBUG;
b9bec74b 3156 }
f2574737 3157 if (ret == 0) {
ff4700b0 3158 cpu_synchronize_state(cs);
48405526 3159 assert(env->exception_injected == -1);
b0b1d690 3160
f2574737 3161 /* pass to guest */
48405526
BS		 3162 env->exception_injected = arch_info->exception;
3163 env->has_error_code = 0;
b0b1d690 3164 }
e22a25c9 3165
f2574737 3166 return ret;
e22a25c9
AL		 3167}
3168
20d695a9 3169void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3170{
3171 const uint8_t type_code[] = {
3172 [GDB_BREAKPOINT_HW] = 0x0,
3173 [GDB_WATCHPOINT_WRITE] = 0x1,
3174 [GDB_WATCHPOINT_ACCESS] = 0x3
3175 };
3176 const uint8_t len_code[] = {
3177 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3178 };
3179 int n;
3180
a60f24b5 3181 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3182 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3183 }
e22a25c9
AL		 3184 if (nb_hw_breakpoint > 0) {
3185 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3186 dbg->arch.debugreg[7] = 0x0600;
3187 for (n = 0; n < nb_hw_breakpoint; n++) {
3188 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3189 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3190 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3191 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3192 }
3193 }
3194}
4513d923 3195
2a4dac83
JK		 3196static bool host_supports_vmx(void)
3197{
3198 uint32_t ecx, unused;
3199
3200 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3201 return ecx & CPUID_EXT_VMX;
3202}
3203
3204#define VMX_INVALID_GUEST_STATE 0x80000021
3205
20d695a9 3206int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3207{
20d695a9 3208 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3209 uint64_t code;
3210 int ret;
3211
3212 switch (run->exit_reason) {
3213 case KVM_EXIT_HLT:
3214 DPRINTF("handle_hlt\n");
4b8523ee 3215 qemu_mutex_lock_iothread();
839b5630 3216 ret = kvm_handle_halt(cpu);
4b8523ee 3217 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3218 break;
3219 case KVM_EXIT_SET_TPR:
3220 ret = 0;
3221 break;
d362e757 3222 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3223 qemu_mutex_lock_iothread();
f7575c96 3224 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3225 qemu_mutex_unlock_iothread();
d362e757 3226 break;
2a4dac83
JK		 3227 case KVM_EXIT_FAIL_ENTRY:
3228 code = run->fail_entry.hardware_entry_failure_reason;
3229 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3230 code);
3231 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3232 fprintf(stderr,
12619721 3233 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3234 "unrestricted mode\n"
3235 "support, the failure can be most likely due to the guest "
3236 "entering an invalid\n"
3237 "state for Intel VT. For example, the guest maybe running "
3238 "in big real mode\n"
3239 "which is not supported on less recent Intel processors."
3240 "\n\n");
3241 }
3242 ret = -1;
3243 break;
3244 case KVM_EXIT_EXCEPTION:
3245 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3246 run->ex.exception, run->ex.error_code);
3247 ret = -1;
3248 break;
f2574737
JK		 3249 case KVM_EXIT_DEBUG:
3250 DPRINTF("kvm_exit_debug\n");
4b8523ee 3251 qemu_mutex_lock_iothread();
a60f24b5 3252 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3253 qemu_mutex_unlock_iothread();
f2574737 3254 break;
50efe82c
AS		 3255 case KVM_EXIT_HYPERV:
3256 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3257 break;
15eafc2e
PB		 3258 case KVM_EXIT_IOAPIC_EOI:
3259 ioapic_eoi_broadcast(run->eoi.vector);
3260 ret = 0;
3261 break;
2a4dac83
JK		 3262 default:
3263 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3264 ret = -1;
3265 break;
3266 }
3267
3268 return ret;
3269}
3270
20d695a9 3271bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3272{
20d695a9
AF		 3273 X86CPU *cpu = X86_CPU(cs);
3274 CPUX86State *env = &cpu->env;
3275
dd1750d7 3276 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3277 return !(env->cr[0] & CR0_PE_MASK) ||
3278 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3279}
84b058d7
JK		 3280
3281void kvm_arch_init_irq_routing(KVMState *s)
3282{
3283 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3284 /* If kernel can't do irq routing, interrupt source
3285 * override 0->2 cannot be set up as required by HPET.
3286 * So we have to disable it.
3287 */
3288 no_hpet = 1;
3289 }
cc7e0ddf 3290 /* We know at this point that we're using the in-kernel
614e41bc 3291 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3292 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3293 */
614e41bc 3294 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3295 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3296
3297 if (kvm_irqchip_is_split()) {
3298 int i;
3299
3300 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3301 MSI routes for signaling interrupts to the local apics. */
3302 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3303 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3304 error_report("Could not enable split IRQ mode.");
3305 exit(1);
3306 }
3307 }
3308 }
3309}
3310
3311int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3312{
3313 int ret;
3314 if (machine_kernel_irqchip_split(ms)) {
3315 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3316 if (ret) {
df3c286c 3317 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3318 strerror(-ret));
3319 exit(1);
3320 } else {
3321 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3322 kvm_split_irqchip = true;
3323 return 1;
3324 }
3325 } else {
3326 return 0;
3327 }
84b058d7 3328}
b139bd30
JK		 3329
3330/* Classic KVM device assignment interface. Will remain x86 only. */
3331int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3332 uint32_t flags, uint32_t *dev_id)
3333{
3334 struct kvm_assigned_pci_dev dev_data = {
3335 .segnr = dev_addr->domain,
3336 .busnr = dev_addr->bus,
3337 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3338 .flags = flags,
3339 };
3340 int ret;
3341
3342 dev_data.assigned_dev_id =
3343 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3344
3345 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3346 if (ret < 0) {
3347 return ret;
3348 }
3349
3350 *dev_id = dev_data.assigned_dev_id;
3351
3352 return 0;
3353}
3354
3355int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3356{
3357 struct kvm_assigned_pci_dev dev_data = {
3358 .assigned_dev_id = dev_id,
3359 };
3360
3361 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3362}
3363
3364static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3365 uint32_t irq_type, uint32_t guest_irq)
3366{
3367 struct kvm_assigned_irq assigned_irq = {
3368 .assigned_dev_id = dev_id,
3369 .guest_irq = guest_irq,
3370 .flags = irq_type,
3371 };
3372
3373 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3374 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3375 } else {
3376 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3377 }
3378}
3379
3380int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3381 uint32_t guest_irq)
3382{
3383 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3384 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3385
3386 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3387}
3388
3389int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3390{
3391 struct kvm_assigned_pci_dev dev_data = {
3392 .assigned_dev_id = dev_id,
3393 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3394 };
3395
3396 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3397}
3398
3399static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3400 uint32_t type)
3401{
3402 struct kvm_assigned_irq assigned_irq = {
3403 .assigned_dev_id = dev_id,
3404 .flags = type,
3405 };
3406
3407 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3408}
3409
3410int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3411{
3412 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3413 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3414}
3415
3416int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3417{
3418 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3419 KVM_DEV_IRQ_GUEST_MSI, virq);
3420}
3421
3422int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3423{
3424 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3425 KVM_DEV_IRQ_HOST_MSI);
3426}
3427
3428bool kvm_device_msix_supported(KVMState *s)
3429{
3430 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3431 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3432 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3433}
3434
3435int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3436 uint32_t nr_vectors)
3437{
3438 struct kvm_assigned_msix_nr msix_nr = {
3439 .assigned_dev_id = dev_id,
3440 .entry_nr = nr_vectors,
3441 };
3442
3443 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3444}
3445
3446int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3447 int virq)
3448{
3449 struct kvm_assigned_msix_entry msix_entry = {
3450 .assigned_dev_id = dev_id,
3451 .gsi = virq,
3452 .entry = vector,
3453 };
3454
3455 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3456}
3457
3458int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3459{
3460 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3461 KVM_DEV_IRQ_GUEST_MSIX, 0);
3462}
3463
3464int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3465{
3466 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3467 KVM_DEV_IRQ_HOST_MSIX);
3468}
9e03a040
FB		 3469
3470int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3471 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3472{
8b5ed7df
PX		 3473 X86IOMMUState *iommu = x86_iommu_get_default();
3474
3475 if (iommu) {
3476 int ret;
3477 MSIMessage src, dst;
3478 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3479
3480 src.address = route->u.msi.address_hi;
3481 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3482 src.address |= route->u.msi.address_lo;
3483 src.data = route->u.msi.data;
3484
3485 ret = class->int_remap(iommu, &src, &dst, dev ? \
3486 pci_requester_id(dev) : \
3487 X86_IOMMU_SID_INVALID);
3488 if (ret) {
3489 trace_kvm_x86_fixup_msi_error(route->gsi);
3490 return 1;
3491 }
3492
3493 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3494 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3495 route->u.msi.data = dst.data;
3496 }
3497
9e03a040
FB		 3498 return 0;
3499}
1850b6b7 3500
38d87493
PX		 3501typedef struct MSIRouteEntry MSIRouteEntry;
3502
3503struct MSIRouteEntry {
3504 PCIDevice *dev; /* Device pointer */
3505 int vector; /* MSI/MSIX vector index */
3506 int virq; /* Virtual IRQ index */
3507 QLIST_ENTRY(MSIRouteEntry) list;
3508};
3509
3510/* List of used GSI routes */
3511static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3512 QLIST_HEAD_INITIALIZER(msi_route_list);
3513
e1d4fb2d
PX		 3514static void kvm_update_msi_routes_all(void *private, bool global,
3515 uint32_t index, uint32_t mask)
3516{
3517 int cnt = 0;
3518 MSIRouteEntry *entry;
3519 MSIMessage msg;
fd563564
PX		 3520 PCIDevice *dev;
3521
e1d4fb2d
PX		 3522 /* TODO: explicit route update */
3523 QLIST_FOREACH(entry, &msi_route_list, list) {
3524 cnt++;
fd563564
PX		 3525 dev = entry->dev;
3526 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3527 continue;
3528 }
3529 msg = pci_get_msi_message(dev, entry->vector);
3530 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3531 }
3f1fea0f 3532 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3533 trace_kvm_x86_update_msi_routes(cnt);
3534}
3535
38d87493
PX		 3536int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3537 int vector, PCIDevice *dev)
3538{
e1d4fb2d 3539 static bool notify_list_inited = false;
38d87493
PX		 3540 MSIRouteEntry *entry;
3541
3542 if (!dev) {
3543 /* These are (possibly) IOAPIC routes only used for split
3544 * kernel irqchip mode, while what we are housekeeping are
3545 * PCI devices only. */
3546 return 0;
3547 }
3548
3549 entry = g_new0(MSIRouteEntry, 1);
3550 entry->dev = dev;
3551 entry->vector = vector;
3552 entry->virq = route->gsi;
3553 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3554
3555 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3556
3557 if (!notify_list_inited) {
3558 /* For the first time we do add route, add ourselves into
3559 * IOMMU's IEC notify list if needed. */
3560 X86IOMMUState *iommu = x86_iommu_get_default();
3561 if (iommu) {
3562 x86_iommu_iec_register_notifier(iommu,
3563 kvm_update_msi_routes_all,
3564 NULL);
3565 }
3566 notify_list_inited = true;
3567 }
38d87493
PX		 3568 return 0;
3569}
3570
3571int kvm_arch_release_virq_post(int virq)
3572{
3573 MSIRouteEntry *entry, *next;
3574 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3575 if (entry->virq == virq) {
3576 trace_kvm_x86_remove_msi_route(virq);
3577 QLIST_REMOVE(entry, list);
01960e6d 3578 g_free(entry);
38d87493
PX		 3579 break;
3580 }
3581 }
9e03a040
FB		 3582 return 0;
3583}
1850b6b7
EA		 3584
3585int kvm_arch_msi_data_to_gsi(uint32_t data)
3586{
3587 abort();
3588}
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