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[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
a2cb15b0 43#include "hw/pci/pci.h"
15eafc2e 44#include "hw/pci/msi.h"
fd563564 45#include "hw/pci/msix.h"
795c40b8 46#include "migration/blocker.h"
4c663752 47#include "exec/memattrs.h"
8b5ed7df 48#include "trace.h"
05330448
AL		 49
50//#define DEBUG_KVM
51
52#ifdef DEBUG_KVM
8c0d577e 53#define DPRINTF(fmt, ...) \
05330448
AL		 54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55#else
8c0d577e 56#define DPRINTF(fmt, ...) \
05330448
AL		 57 do { } while (0)
58#endif
59
1a03675d
GC		 60#define MSR_KVM_WALL_CLOCK 0x11
61#define MSR_KVM_SYSTEM_TIME 0x12
62
d1138251
EH		 63/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65#define MSR_BUF_SIZE 4096
d71b62a1 66
94a8d39a
JK		 67const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72};
25d2e361 73
c3a3a7d3
JK		 74static bool has_msr_star;
75static bool has_msr_hsave_pa;
c9b8f6b6 76static bool has_msr_tsc_aux;
f28558d3 77static bool has_msr_tsc_adjust;
aa82ba54 78static bool has_msr_tsc_deadline;
df67696e 79static bool has_msr_feature_control;
21e87c46 80static bool has_msr_misc_enable;
fc12d72e 81static bool has_msr_smbase;
79e9ebeb 82static bool has_msr_bndcfgs;
25d2e361 83static int lm_capable_kernel;
7bc3d711 84static bool has_msr_hv_hypercall;
f2a53c9e 85static bool has_msr_hv_crash;
744b8a94 86static bool has_msr_hv_reset;
8c145d7c 87static bool has_msr_hv_vpindex;
e9688fab 88static bool hv_vpindex_settable;
46eb8f98 89static bool has_msr_hv_runtime;
866eea9a 90static bool has_msr_hv_synic;
ff99aa64 91static bool has_msr_hv_stimer;
d72bc7f6 92static bool has_msr_hv_frequencies;
ba6a4fd9 93static bool has_msr_hv_reenlightenment;
18cd2c17 94static bool has_msr_xss;
a33a2cfe 95static bool has_msr_spec_ctrl;
cfeea0c0 96static bool has_msr_virt_ssbd;
e13713db 97static bool has_msr_smi_count;
aec5e9c3 98static bool has_msr_arch_capabs;
b827df58 99
0b368a10
JD		 100static uint32_t has_architectural_pmu_version;
101static uint32_t num_architectural_pmu_gp_counters;
102static uint32_t num_architectural_pmu_fixed_counters;
0d894367 103
28143b40
TH		 104static int has_xsave;
105static int has_xcrs;
106static int has_pit_state2;
107
87f8b626
AR		 108static bool has_msr_mcg_ext_ctl;
109
494e95e9 110static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 111static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 112
28143b40
TH		 113int kvm_has_pit_state2(void)
114{
115 return has_pit_state2;
116}
117
355023f2
PB		 118bool kvm_has_smm(void)
119{
120 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
121}
122
6053a86f
MT		 123bool kvm_has_adjust_clock_stable(void)
124{
125 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
126
127 return (ret == KVM_CLOCK_TSC_STABLE);
128}
129
1d31f66b
PM		 130bool kvm_allows_irq0_override(void)
131{
132 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
133}
134
fb506e70
RK		 135static bool kvm_x2apic_api_set_flags(uint64_t flags)
136{
137 KVMState *s = KVM_STATE(current_machine->accelerator);
138
139 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
140}
141
e391c009 142#define MEMORIZE(fn, _result) \
2a138ec3 143 ({ \
2a138ec3
RK		 144 static bool _memorized; \
145 \
146 if (_memorized) { \
147 return _result; \
148 } \
149 _memorized = true; \
150 _result = fn; \
151 })
152
e391c009
IM		 153static bool has_x2apic_api;
154
155bool kvm_has_x2apic_api(void)
156{
157 return has_x2apic_api;
158}
159
fb506e70
RK		 160bool kvm_enable_x2apic(void)
161{
2a138ec3
RK		 162 return MEMORIZE(
163 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 164 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
165 has_x2apic_api);
fb506e70
RK		 166}
167
e9688fab
RK		 168bool kvm_hv_vpindex_settable(void)
169{
170 return hv_vpindex_settable;
171}
172
0fd7e098
LL		 173static int kvm_get_tsc(CPUState *cs)
174{
175 X86CPU *cpu = X86_CPU(cs);
176 CPUX86State *env = &cpu->env;
177 struct {
178 struct kvm_msrs info;
179 struct kvm_msr_entry entries[1];
180 } msr_data;
181 int ret;
182
183 if (env->tsc_valid) {
184 return 0;
185 }
186
187 msr_data.info.nmsrs = 1;
188 msr_data.entries[0].index = MSR_IA32_TSC;
189 env->tsc_valid = !runstate_is_running();
190
191 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
192 if (ret < 0) {
193 return ret;
194 }
195
48e1a45c 196 assert(ret == 1);
0fd7e098
LL		 197 env->tsc = msr_data.entries[0].data;
198 return 0;
199}
200
14e6fe12 201static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 202{
0fd7e098
LL		 203 kvm_get_tsc(cpu);
204}
205
206void kvm_synchronize_all_tsc(void)
207{
208 CPUState *cpu;
209
210 if (kvm_enabled()) {
211 CPU_FOREACH(cpu) {
14e6fe12 212 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 213 }
214 }
215}
216
b827df58
AK		 217static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
218{
219 struct kvm_cpuid2 *cpuid;
220 int r, size;
221
222 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 223 cpuid = g_malloc0(size);
b827df58
AK		 224 cpuid->nent = max;
225 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 226 if (r == 0 && cpuid->nent >= max) {
227 r = -E2BIG;
228 }
b827df58
AK		 229 if (r < 0) {
230 if (r == -E2BIG) {
7267c094 231 g_free(cpuid);
b827df58
AK		 232 return NULL;
233 } else {
234 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
235 strerror(-r));
236 exit(1);
237 }
238 }
239 return cpuid;
240}
241
dd87f8a6
EH		 242/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
243 * for all entries.
244 */
245static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
246{
247 struct kvm_cpuid2 *cpuid;
248 int max = 1;
494e95e9
CP		 249
250 if (cpuid_cache != NULL) {
251 return cpuid_cache;
252 }
dd87f8a6
EH		 253 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
254 max *= 2;
255 }
494e95e9 256 cpuid_cache = cpuid;
dd87f8a6
EH		 257 return cpuid;
258}
259
a443bc34 260static const struct kvm_para_features {
0c31b744
GC		 261 int cap;
262 int feature;
263} para_features[] = {
264 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
265 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
266 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 267 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 268};
269
ba9bc59e 270static int get_para_features(KVMState *s)
0c31b744
GC		 271{
272 int i, features = 0;
273
8e03c100 274 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 275 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 276 features |= (1 << para_features[i].feature);
277 }
278 }
279
280 return features;
281}
0c31b744 282
40e80ee4
EH		 283static bool host_tsx_blacklisted(void)
284{
285 int family, model, stepping;\
286 char vendor[CPUID_VENDOR_SZ + 1];
287
288 host_vendor_fms(vendor, &family, &model, &stepping);
289
290 /* Check if we are running on a Haswell host known to have broken TSX */
291 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
292 (family == 6) &&
293 ((model == 63 && stepping < 4) ||
294 model == 60 || model == 69 || model == 70);
295}
0c31b744 296
829ae2f9
EH		 297/* Returns the value for a specific register on the cpuid entry
298 */
299static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
300{
301 uint32_t ret = 0;
302 switch (reg) {
303 case R_EAX:
304 ret = entry->eax;
305 break;
306 case R_EBX:
307 ret = entry->ebx;
308 break;
309 case R_ECX:
310 ret = entry->ecx;
311 break;
312 case R_EDX:
313 ret = entry->edx;
314 break;
315 }
316 return ret;
317}
318
4fb73f1d
EH		 319/* Find matching entry for function/index on kvm_cpuid2 struct
320 */
321static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
322 uint32_t function,
323 uint32_t index)
324{
325 int i;
326 for (i = 0; i < cpuid->nent; ++i) {
327 if (cpuid->entries[i].function == function &&
328 cpuid->entries[i].index == index) {
329 return &cpuid->entries[i];
330 }
331 }
332 /* not found: */
333 return NULL;
334}
335
ba9bc59e 336uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 337 uint32_t index, int reg)
b827df58
AK		 338{
339 struct kvm_cpuid2 *cpuid;
b827df58
AK		 340 uint32_t ret = 0;
341 uint32_t cpuid_1_edx;
8c723b79 342 bool found = false;
b827df58 343
dd87f8a6 344 cpuid = get_supported_cpuid(s);
b827df58 345
4fb73f1d
EH		 346 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
347 if (entry) {
348 found = true;
349 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 350 }
351
7b46e5ce
EH		 352 /* Fixups for the data returned by KVM, below */
353
c2acb022
EH		 354 if (function == 1 && reg == R_EDX) {
355 /* KVM before 2.6.30 misreports the following features */
356 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 357 } else if (function == 1 && reg == R_ECX) {
358 /* We can set the hypervisor flag, even if KVM does not return it on
359 * GET_SUPPORTED_CPUID
360 */
361 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 362 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
363 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
364 * and the irqchip is in the kernel.
365 */
366 if (kvm_irqchip_in_kernel() &&
367 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
368 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
369 }
41e5e76d
EH		 370
371 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
372 * without the in-kernel irqchip
373 */
374 if (!kvm_irqchip_in_kernel()) {
375 ret &= ~CPUID_EXT_X2APIC;
b827df58 376 }
2266d443
MT		 377
378 if (enable_cpu_pm) {
379 int disable_exits = kvm_check_extension(s,
380 KVM_CAP_X86_DISABLE_EXITS);
381
382 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
383 ret |= CPUID_EXT_MONITOR;
384 }
385 }
28b8e4d0
JK		 386 } else if (function == 6 && reg == R_EAX) {
387 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 388 } else if (function == 7 && index == 0 && reg == R_EBX) {
389 if (host_tsx_blacklisted()) {
390 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
391 }
f98bbd83
BM		 392 } else if (function == 0x80000001 && reg == R_ECX) {
393 /*
394 * It's safe to enable TOPOEXT even if it's not returned by
395 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
396 * us to keep CPU models including TOPOEXT runnable on older kernels.
397 */
398 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 399 } else if (function == 0x80000001 && reg == R_EDX) {
400 /* On Intel, kvm returns cpuid according to the Intel spec,
401 * so add missing bits according to the AMD spec:
402 */
403 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
404 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 405 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
406 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
407 * be enabled without the in-kernel irqchip
408 */
409 if (!kvm_irqchip_in_kernel()) {
410 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
411 }
be777326 412 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 413 ret |= 1U << KVM_HINTS_REALTIME;
be777326 414 found = 1;
b827df58
AK		 415 }
416
0c31b744 417 /* fallback for older kernels */
8c723b79 418 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 419 ret = get_para_features(s);
b9bec74b 420 }
0c31b744
GC		 421
422 return ret;
bb0300dc 423}
bb0300dc 424
f57bceb6
RH		 425uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
426{
427 struct {
428 struct kvm_msrs info;
429 struct kvm_msr_entry entries[1];
430 } msr_data;
431 uint32_t ret;
432
433 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
434 return 0;
435 }
436
437 /* Check if requested MSR is supported feature MSR */
438 int i;
439 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
440 if (kvm_feature_msrs->indices[i] == index) {
441 break;
442 }
443 if (i == kvm_feature_msrs->nmsrs) {
444 return 0; /* if the feature MSR is not supported, simply return 0 */
445 }
446
447 msr_data.info.nmsrs = 1;
448 msr_data.entries[0].index = index;
449
450 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
451 if (ret != 1) {
452 error_report("KVM get MSR (index=0x%x) feature failed, %s",
453 index, strerror(-ret));
454 exit(1);
455 }
456
457 return msr_data.entries[0].data;
458}
459
460
3c85e74f
HY		 461typedef struct HWPoisonPage {
462 ram_addr_t ram_addr;
463 QLIST_ENTRY(HWPoisonPage) list;
464} HWPoisonPage;
465
466static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
467 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
468
469static void kvm_unpoison_all(void *param)
470{
471 HWPoisonPage *page, *next_page;
472
473 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
474 QLIST_REMOVE(page, list);
475 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 476 g_free(page);
3c85e74f
HY		 477 }
478}
479
3c85e74f
HY		 480static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
481{
482 HWPoisonPage *page;
483
484 QLIST_FOREACH(page, &hwpoison_page_list, list) {
485 if (page->ram_addr == ram_addr) {
486 return;
487 }
488 }
ab3ad07f 489 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 490 page->ram_addr = ram_addr;
491 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
492}
493
e7701825
MT		 494static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
495 int *max_banks)
496{
497 int r;
498
14a09518 499 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 500 if (r > 0) {
501 *max_banks = r;
502 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
503 }
504 return -ENOSYS;
505}
506
bee615d4 507static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 508{
87f8b626 509 CPUState *cs = CPU(cpu);
bee615d4 510 CPUX86State *env = &cpu->env;
c34d440a
JK		 511 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
512 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
513 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 514 int flags = 0;
e7701825 515
c34d440a
JK		 516 if (code == BUS_MCEERR_AR) {
517 status |= MCI_STATUS_AR | 0x134;
518 mcg_status |= MCG_STATUS_EIPV;
519 } else {
520 status |= 0xc0;
521 mcg_status |= MCG_STATUS_RIPV;
419fb20a 522 }
87f8b626
AR		 523
524 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
525 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
526 * guest kernel back into env->mcg_ext_ctl.
527 */
528 cpu_synchronize_state(cs);
529 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
530 mcg_status |= MCG_STATUS_LMCE;
531 flags = 0;
532 }
533
8c5cf3b6 534 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 535 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 536}
419fb20a
JK		 537
538static void hardware_memory_error(void)
539{
540 fprintf(stderr, "Hardware memory error!\n");
541 exit(1);
542}
543
2ae41db2 544void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 545{
20d695a9
AF		 546 X86CPU *cpu = X86_CPU(c);
547 CPUX86State *env = &cpu->env;
419fb20a 548 ram_addr_t ram_addr;
a8170e5e 549 hwaddr paddr;
419fb20a 550
4d39892c
PB		 551 /* If we get an action required MCE, it has been injected by KVM
552 * while the VM was running. An action optional MCE instead should
553 * be coming from the main thread, which qemu_init_sigbus identifies
554 * as the "early kill" thread.
555 */
a16fc07e 556 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 557
20e0ff59 558 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 559 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 560 if (ram_addr != RAM_ADDR_INVALID &&
561 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
562 kvm_hwpoison_page_add(ram_addr);
563 kvm_mce_inject(cpu, paddr, code);
2ae41db2 564 return;
419fb20a 565 }
20e0ff59
PB		 566
567 fprintf(stderr, "Hardware memory error for memory used by "
568 "QEMU itself instead of guest system!\n");
419fb20a 569 }
20e0ff59
PB		 570
571 if (code == BUS_MCEERR_AR) {
572 hardware_memory_error();
573 }
574
575 /* Hope we are lucky for AO MCE */
419fb20a
JK		 576}
577
1bc22652 578static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 579{
1bc22652
AF		 580 CPUX86State *env = &cpu->env;
581
ab443475
JK		 582 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
583 unsigned int bank, bank_num = env->mcg_cap & 0xff;
584 struct kvm_x86_mce mce;
585
586 env->exception_injected = -1;
587
588 /*
589 * There must be at least one bank in use if an MCE is pending.
590 * Find it and use its values for the event injection.
591 */
592 for (bank = 0; bank < bank_num; bank++) {
593 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
594 break;
595 }
596 }
597 assert(bank < bank_num);
598
599 mce.bank = bank;
600 mce.status = env->mce_banks[bank * 4 + 1];
601 mce.mcg_status = env->mcg_status;
602 mce.addr = env->mce_banks[bank * 4 + 2];
603 mce.misc = env->mce_banks[bank * 4 + 3];
604
1bc22652 605 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 606 }
ab443475
JK		 607 return 0;
608}
609
1dfb4dd9 610static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 611{
317ac620 612 CPUX86State *env = opaque;
b8cc45d6
GC		 613
614 if (running) {
615 env->tsc_valid = false;
616 }
617}
618
83b17af5 619unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 620{
83b17af5 621 X86CPU *cpu = X86_CPU(cs);
7e72a45c 622 return cpu->apic_id;
b164e48e
EH		 623}
624
92067bf4
IM		 625#ifndef KVM_CPUID_SIGNATURE_NEXT
626#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
627#endif
628
629static bool hyperv_hypercall_available(X86CPU *cpu)
630{
631 return cpu->hyperv_vapic ||
632 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
633}
634
635static bool hyperv_enabled(X86CPU *cpu)
636{
7bc3d711
PB		 637 CPUState *cs = CPU(cpu);
638 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
639 (hyperv_hypercall_available(cpu) ||
48a5f3bc 640 cpu->hyperv_time ||
f2a53c9e 641 cpu->hyperv_relaxed_timing ||
744b8a94 642 cpu->hyperv_crash ||
8c145d7c 643 cpu->hyperv_reset ||
46eb8f98 644 cpu->hyperv_vpindex ||
866eea9a 645 cpu->hyperv_runtime ||
ff99aa64 646 cpu->hyperv_synic ||
ba6a4fd9 647 cpu->hyperv_stimer ||
47512009 648 cpu->hyperv_reenlightenment ||
6b7a9830
VK		 649 cpu->hyperv_tlbflush ||
650 cpu->hyperv_ipi);
92067bf4
IM		 651}
652
5031283d
HZ		 653static int kvm_arch_set_tsc_khz(CPUState *cs)
654{
655 X86CPU *cpu = X86_CPU(cs);
656 CPUX86State *env = &cpu->env;
657 int r;
658
659 if (!env->tsc_khz) {
660 return 0;
661 }
662
663 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
664 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
665 -ENOTSUP;
666 if (r < 0) {
667 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
668 * TSC frequency doesn't match the one we want.
669 */
670 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
671 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
672 -ENOTSUP;
673 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 674 warn_report("TSC frequency mismatch between "
675 "VM (%" PRId64 " kHz) and host (%d kHz), "
676 "and TSC scaling unavailable",
677 env->tsc_khz, cur_freq);
5031283d
HZ		 678 return r;
679 }
680 }
681
682 return 0;
683}
684
4bb95b82
LP		 685static bool tsc_is_stable_and_known(CPUX86State *env)
686{
687 if (!env->tsc_khz) {
688 return false;
689 }
690 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
691 || env->user_tsc_khz;
692}
693
c35bd19a
EY		 694static int hyperv_handle_properties(CPUState *cs)
695{
696 X86CPU *cpu = X86_CPU(cs);
697 CPUX86State *env = &cpu->env;
698
699 if (cpu->hyperv_relaxed_timing) {
5e953812 700 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 701 }
702 if (cpu->hyperv_vapic) {
5e953812
RK		 703 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
704 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 705 }
3ddcd2ed 706 if (cpu->hyperv_time) {
1221f150
RK		 707 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
708 fprintf(stderr, "Hyper-V clocksources "
709 "(requested by 'hv-time' cpu flag) "
710 "are not supported by kernel\n");
711 return -ENOSYS;
712 }
5e953812
RK		 713 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
714 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
715 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
9445597b
RK		 716 }
717 if (cpu->hyperv_frequencies) {
718 if (!has_msr_hv_frequencies) {
719 fprintf(stderr, "Hyper-V frequency MSRs "
720 "(requested by 'hv-frequencies' cpu flag) "
721 "are not supported by kernel\n");
722 return -ENOSYS;
d72bc7f6 723 }
9445597b
RK		 724 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
725 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 726 }
1221f150
RK		 727 if (cpu->hyperv_crash) {
728 if (!has_msr_hv_crash) {
729 fprintf(stderr, "Hyper-V crash MSRs "
730 "(requested by 'hv-crash' cpu flag) "
731 "are not supported by kernel\n");
732 return -ENOSYS;
733 }
5e953812 734 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 735 }
ba6a4fd9
VK		 736 if (cpu->hyperv_reenlightenment) {
737 if (!has_msr_hv_reenlightenment) {
738 fprintf(stderr,
739 "Hyper-V Reenlightenment MSRs "
740 "(requested by 'hv-reenlightenment' cpu flag) "
741 "are not supported by kernel\n");
742 return -ENOSYS;
743 }
744 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
745 }
5e953812 746 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1221f150
RK		 747 if (cpu->hyperv_reset) {
748 if (!has_msr_hv_reset) {
749 fprintf(stderr, "Hyper-V reset MSR "
750 "(requested by 'hv-reset' cpu flag) "
751 "is not supported by kernel\n");
752 return -ENOSYS;
753 }
5e953812 754 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a 755 }
1221f150
RK		 756 if (cpu->hyperv_vpindex) {
757 if (!has_msr_hv_vpindex) {
758 fprintf(stderr, "Hyper-V VP_INDEX MSR "
759 "(requested by 'hv-vpindex' cpu flag) "
760 "is not supported by kernel\n");
761 return -ENOSYS;
762 }
5e953812 763 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a 764 }
1221f150
RK		 765 if (cpu->hyperv_runtime) {
766 if (!has_msr_hv_runtime) {
767 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
768 "(requested by 'hv-runtime' cpu flag) "
769 "is not supported by kernel\n");
770 return -ENOSYS;
771 }
5e953812 772 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 773 }
774 if (cpu->hyperv_synic) {
9b4cf107
RK		 775 unsigned int cap = KVM_CAP_HYPERV_SYNIC;
776 if (!cpu->hyperv_synic_kvm_only) {
777 if (!cpu->hyperv_vpindex) {
778 fprintf(stderr, "Hyper-V SynIC "
779 "(requested by 'hv-synic' cpu flag) "
780 "requires Hyper-V VP_INDEX ('hv-vpindex')\n");
781 return -ENOSYS;
782 }
783 cap = KVM_CAP_HYPERV_SYNIC2;
784 }
785
786 if (!has_msr_hv_synic || !kvm_check_extension(cs->kvm_state, cap)) {
729ce7e1
RK		 787 fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
788 "is not supported by kernel\n");
c35bd19a
EY		 789 return -ENOSYS;
790 }
791
5e953812 792 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a
EY		 793 }
794 if (cpu->hyperv_stimer) {
795 if (!has_msr_hv_stimer) {
796 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
797 return -ENOSYS;
798 }
5e953812 799 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 800 }
a2b107db
VK		 801 if (cpu->hyperv_relaxed_timing) {
802 env->features[FEAT_HV_RECOMM_EAX] |= HV_RELAXED_TIMING_RECOMMENDED;
803 }
804 if (cpu->hyperv_vapic) {
805 env->features[FEAT_HV_RECOMM_EAX] |= HV_APIC_ACCESS_RECOMMENDED;
806 }
807 if (cpu->hyperv_tlbflush) {
808 if (kvm_check_extension(cs->kvm_state,
809 KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
810 fprintf(stderr, "Hyper-V TLB flush support "
811 "(requested by 'hv-tlbflush' cpu flag) "
812 " is not supported by kernel\n");
813 return -ENOSYS;
814 }
815 env->features[FEAT_HV_RECOMM_EAX] |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
816 env->features[FEAT_HV_RECOMM_EAX] |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
817 }
818 if (cpu->hyperv_ipi) {
819 if (kvm_check_extension(cs->kvm_state,
820 KVM_CAP_HYPERV_SEND_IPI) <= 0) {
821 fprintf(stderr, "Hyper-V IPI send support "
822 "(requested by 'hv-ipi' cpu flag) "
823 " is not supported by kernel\n");
824 return -ENOSYS;
825 }
826 env->features[FEAT_HV_RECOMM_EAX] |= HV_CLUSTER_IPI_RECOMMENDED;
827 env->features[FEAT_HV_RECOMM_EAX] |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
828 }
829 if (cpu->hyperv_evmcs) {
830 uint16_t evmcs_version;
831
832 if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
833 (uintptr_t)&evmcs_version)) {
834 fprintf(stderr, "Hyper-V Enlightened VMCS "
835 "(requested by 'hv-evmcs' cpu flag) "
836 "is not supported by kernel\n");
837 return -ENOSYS;
838 }
839 env->features[FEAT_HV_RECOMM_EAX] |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
840 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
841 }
842
c35bd19a
EY		 843 return 0;
844}
845
e9688fab
RK		 846static int hyperv_init_vcpu(X86CPU *cpu)
847{
729ce7e1
RK		 848 CPUState *cs = CPU(cpu);
849 int ret;
850
e9688fab
RK		 851 if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
852 /*
853 * the kernel doesn't support setting vp_index; assert that its value
854 * is in sync
855 */
e9688fab
RK		 856 struct {
857 struct kvm_msrs info;
858 struct kvm_msr_entry entries[1];
859 } msr_data = {
860 .info.nmsrs = 1,
861 .entries[0].index = HV_X64_MSR_VP_INDEX,
862 };
863
729ce7e1 864 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 865 if (ret < 0) {
866 return ret;
867 }
868 assert(ret == 1);
869
701189e3 870 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 871 error_report("kernel's vp_index != QEMU's vp_index");
872 return -ENXIO;
873 }
874 }
875
729ce7e1 876 if (cpu->hyperv_synic) {
9b4cf107
RK		 877 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
878 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
879 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 880 if (ret < 0) {
881 error_report("failed to turn on HyperV SynIC in KVM: %s",
882 strerror(-ret));
883 return ret;
884 }
606c34bf 885
9b4cf107
RK		 886 if (!cpu->hyperv_synic_kvm_only) {
887 ret = hyperv_x86_synic_add(cpu);
888 if (ret < 0) {
889 error_report("failed to create HyperV SynIC: %s",
890 strerror(-ret));
891 return ret;
892 }
606c34bf 893 }
729ce7e1
RK		 894 }
895
e9688fab
RK		 896 return 0;
897}
898
68bfd0ad 899static Error *invtsc_mig_blocker;
d98f2607 900static Error *vmx_mig_blocker;
68bfd0ad 901
f8bb0565 902#define KVM_MAX_CPUID_ENTRIES 100
0893d460 903
20d695a9 904int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 905{
906 struct {
486bd5a2 907 struct kvm_cpuid2 cpuid;
f8bb0565 908 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 909 } cpuid_data;
910 /*
911 * The kernel defines these structs with padding fields so there
912 * should be no extra padding in our cpuid_data struct.
913 */
914 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
915 sizeof(struct kvm_cpuid2) +
916 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
917
20d695a9
AF		 918 X86CPU *cpu = X86_CPU(cs);
919 CPUX86State *env = &cpu->env;
486bd5a2 920 uint32_t limit, i, j, cpuid_i;
a33609ca 921 uint32_t unused;
bb0300dc 922 struct kvm_cpuid_entry2 *c;
bb0300dc 923 uint32_t signature[3];
234cc647 924 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 925 int r;
fe44dc91 926 Error *local_err = NULL;
05330448 927
ef4cbe14
SW		 928 memset(&cpuid_data, 0, sizeof(cpuid_data));
929
05330448
AL		 930 cpuid_i = 0;
931
ddb98b5a
LP		 932 r = kvm_arch_set_tsc_khz(cs);
933 if (r < 0) {
934 goto fail;
935 }
936
937 /* vcpu's TSC frequency is either specified by user, or following
938 * the value used by KVM if the former is not present. In the
939 * latter case, we query it from KVM and record in env->tsc_khz,
940 * so that vcpu's TSC frequency can be migrated later via this field.
941 */
942 if (!env->tsc_khz) {
943 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
944 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
945 -ENOTSUP;
946 if (r > 0) {
947 env->tsc_khz = r;
948 }
949 }
950
bb0300dc 951 /* Paravirtualization CPUIDs */
234cc647
PB		 952 if (hyperv_enabled(cpu)) {
953 c = &cpuid_data.entries[cpuid_i++];
5e953812 954 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 955 if (!cpu->hyperv_vendor_id) {
956 memcpy(signature, "Microsoft Hv", 12);
957 } else {
958 size_t len = strlen(cpu->hyperv_vendor_id);
959
960 if (len > 12) {
961 error_report("hv-vendor-id truncated to 12 characters");
962 len = 12;
963 }
964 memset(signature, 0, 12);
965 memcpy(signature, cpu->hyperv_vendor_id, len);
966 }
e204ac61
VK		 967 c->eax = cpu->hyperv_evmcs ?
968 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
234cc647
PB		 969 c->ebx = signature[0];
970 c->ecx = signature[1];
971 c->edx = signature[2];
0c31b744 972
234cc647 973 c = &cpuid_data.entries[cpuid_i++];
5e953812 974 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 975 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
976 c->eax = signature[0];
234cc647
PB		 977 c->ebx = 0;
978 c->ecx = 0;
979 c->edx = 0;
eab70139
VR		 980
981 c = &cpuid_data.entries[cpuid_i++];
5e953812 982 c->function = HV_CPUID_VERSION;
eab70139
VR		 983 c->eax = 0x00001bbc;
984 c->ebx = 0x00060001;
985
986 c = &cpuid_data.entries[cpuid_i++];
5e953812 987 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 988 r = hyperv_handle_properties(cs);
989 if (r) {
990 return r;
46eb8f98 991 }
c35bd19a
EY		 992 c->eax = env->features[FEAT_HYPERV_EAX];
993 c->ebx = env->features[FEAT_HYPERV_EBX];
994 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 995
eab70139 996 c = &cpuid_data.entries[cpuid_i++];
5e953812 997 c->function = HV_CPUID_ENLIGHTMENT_INFO;
a2b107db
VK		 998
999 c->eax = env->features[FEAT_HV_RECOMM_EAX];
92067bf4 1000 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 1001
1002 c = &cpuid_data.entries[cpuid_i++];
5e953812 1003 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 1004
1005 c->eax = cpu->hv_max_vps;
eab70139
VR		 1006 c->ebx = 0x40;
1007
234cc647 1008 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1009 has_msr_hv_hypercall = true;
e204ac61
VK		 1010
1011 if (cpu->hyperv_evmcs) {
1012 __u32 function;
1013
1014 /* Create zeroed 0x40000006..0x40000009 leaves */
1015 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1016 function < HV_CPUID_NESTED_FEATURES; function++) {
1017 c = &cpuid_data.entries[cpuid_i++];
1018 c->function = function;
1019 }
1020
1021 c = &cpuid_data.entries[cpuid_i++];
1022 c->function = HV_CPUID_NESTED_FEATURES;
a2b107db 1023 c->eax = env->features[FEAT_HV_NESTED_EAX];
e204ac61 1024 }
eab70139
VR		 1025 }
1026
f522d2ac
AW		 1027 if (cpu->expose_kvm) {
1028 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1029 c = &cpuid_data.entries[cpuid_i++];
1030 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1031 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1032 c->ebx = signature[0];
1033 c->ecx = signature[1];
1034 c->edx = signature[2];
234cc647 1035
f522d2ac
AW		 1036 c = &cpuid_data.entries[cpuid_i++];
1037 c->function = KVM_CPUID_FEATURES | kvm_base;
1038 c->eax = env->features[FEAT_KVM];
be777326 1039 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1040 }
917367aa 1041
a33609ca 1042 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1043
1044 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1045 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1046 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1047 abort();
1048 }
bb0300dc 1049 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1050
1051 switch (i) {
a36b1029
AL		 1052 case 2: {
1053 /* Keep reading function 2 till all the input is received */
1054 int times;
1055
a36b1029 1056 c->function = i;
a33609ca
AL		 1057 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1058 KVM_CPUID_FLAG_STATE_READ_NEXT;
1059 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1060 times = c->eax & 0xff;
a36b1029
AL		 1061
1062 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1063 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1064 fprintf(stderr, "cpuid_data is full, no space for "
1065 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1066 abort();
1067 }
a33609ca 1068 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1069 c->function = i;
a33609ca
AL		 1070 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1071 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1072 }
1073 break;
1074 }
486bd5a2
AL		 1075 case 4:
1076 case 0xb:
1077 case 0xd:
1078 for (j = 0; ; j++) {
31e8c696
AP		 1079 if (i == 0xd && j == 64) {
1080 break;
1081 }
486bd5a2
AL		 1082 c->function = i;
1083 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1084 c->index = j;
a33609ca 1085 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1086
b9bec74b 1087 if (i == 4 && c->eax == 0) {
486bd5a2 1088 break;
b9bec74b
JK		 1089 }
1090 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1091 break;
b9bec74b
JK		 1092 }
1093 if (i == 0xd && c->eax == 0) {
31e8c696 1094 continue;
b9bec74b 1095 }
f8bb0565
IM		 1096 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1097 fprintf(stderr, "cpuid_data is full, no space for "
1098 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1099 abort();
1100 }
a33609ca 1101 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1102 }
1103 break;
e37a5c7f
CP		 1104 case 0x14: {
1105 uint32_t times;
1106
1107 c->function = i;
1108 c->index = 0;
1109 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1110 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1111 times = c->eax;
1112
1113 for (j = 1; j <= times; ++j) {
1114 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1115 fprintf(stderr, "cpuid_data is full, no space for "
1116 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1117 abort();
1118 }
1119 c = &cpuid_data.entries[cpuid_i++];
1120 c->function = i;
1121 c->index = j;
1122 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1123 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1124 }
1125 break;
1126 }
486bd5a2 1127 default:
486bd5a2 1128 c->function = i;
a33609ca
AL		 1129 c->flags = 0;
1130 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1131 break;
1132 }
05330448 1133 }
0d894367
PB		 1134
1135 if (limit >= 0x0a) {
0b368a10 1136 uint32_t eax, edx;
0d894367 1137
0b368a10
JD		 1138 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1139
1140 has_architectural_pmu_version = eax & 0xff;
1141 if (has_architectural_pmu_version > 0) {
1142 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1143
1144 /* Shouldn't be more than 32, since that's the number of bits
1145 * available in EBX to tell us _which_ counters are available.
1146 * Play it safe.
1147 */
0b368a10
JD		 1148 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1149 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1150 }
1151
1152 if (has_architectural_pmu_version > 1) {
1153 num_architectural_pmu_fixed_counters = edx & 0x1f;
1154
1155 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1156 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1157 }
0d894367
PB		 1158 }
1159 }
1160 }
1161
a33609ca 1162 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1163
1164 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1165 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1166 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1167 abort();
1168 }
bb0300dc 1169 c = &cpuid_data.entries[cpuid_i++];
05330448 1170
8f4202fb
BM		 1171 switch (i) {
1172 case 0x8000001d:
1173 /* Query for all AMD cache information leaves */
1174 for (j = 0; ; j++) {
1175 c->function = i;
1176 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1177 c->index = j;
1178 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1179
1180 if (c->eax == 0) {
1181 break;
1182 }
1183 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1184 fprintf(stderr, "cpuid_data is full, no space for "
1185 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1186 abort();
1187 }
1188 c = &cpuid_data.entries[cpuid_i++];
1189 }
1190 break;
1191 default:
1192 c->function = i;
1193 c->flags = 0;
1194 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1195 break;
1196 }
05330448
AL		 1197 }
1198
b3baa152
BW		 1199 /* Call Centaur's CPUID instructions they are supported. */
1200 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1201 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1202
1203 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1204 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1205 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1206 abort();
1207 }
b3baa152
BW		 1208 c = &cpuid_data.entries[cpuid_i++];
1209
1210 c->function = i;
1211 c->flags = 0;
1212 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1213 }
1214 }
1215
05330448
AL		 1216 cpuid_data.cpuid.nent = cpuid_i;
1217
e7701825 1218 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1219 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1220 (CPUID_MCE | CPUID_MCA)
a60f24b5 1221 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1222 uint64_t mcg_cap, unsupported_caps;
e7701825 1223 int banks;
32a42024 1224 int ret;
e7701825 1225
a60f24b5 1226 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1227 if (ret < 0) {
1228 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1229 return ret;
e7701825 1230 }
75d49497 1231
2590f15b 1232 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1233 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1234 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1235 return -ENOTSUP;
75d49497 1236 }
49b69cbf 1237
5120901a
EH		 1238 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1239 if (unsupported_caps) {
87f8b626
AR		 1240 if (unsupported_caps & MCG_LMCE_P) {
1241 error_report("kvm: LMCE not supported");
1242 return -ENOTSUP;
1243 }
3dc6f869
AF		 1244 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1245 unsupported_caps);
5120901a
EH		 1246 }
1247
2590f15b
EH		 1248 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1249 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1250 if (ret < 0) {
1251 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1252 return ret;
1253 }
e7701825 1254 }
e7701825 1255
b8cc45d6
GC		 1256 qemu_add_vm_change_state_handler(cpu_update_state, env);
1257
df67696e
LJ		 1258 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1259 if (c) {
1260 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1261 !!(c->ecx & CPUID_EXT_SMX);
1262 }
1263
d98f2607
PB		 1264 if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1265 error_setg(&vmx_mig_blocker,
1266 "Nested VMX virtualization does not support live migration yet");
1267 r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1268 if (local_err) {
1269 error_report_err(local_err);
1270 error_free(vmx_mig_blocker);
1271 return r;
1272 }
1273 }
1274
87f8b626
AR		 1275 if (env->mcg_cap & MCG_LMCE_P) {
1276 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1277 }
1278
d99569d9
EH		 1279 if (!env->user_tsc_khz) {
1280 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1281 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1282 error_setg(&invtsc_mig_blocker,
1283 "State blocked by non-migratable CPU device"
1284 " (invtsc flag)");
fe44dc91
AA		 1285 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1286 if (local_err) {
1287 error_report_err(local_err);
1288 error_free(invtsc_mig_blocker);
0c2ed83f 1289 return r;
fe44dc91 1290 }
d99569d9 1291 }
68bfd0ad
MT		 1292 }
1293
9954a158
PDJ		 1294 if (cpu->vmware_cpuid_freq
1295 /* Guests depend on 0x40000000 to detect this feature, so only expose
1296 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1297 && cpu->expose_kvm
1298 && kvm_base == KVM_CPUID_SIGNATURE
1299 /* TSC clock must be stable and known for this feature. */
4bb95b82 1300 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1301
1302 c = &cpuid_data.entries[cpuid_i++];
1303 c->function = KVM_CPUID_SIGNATURE | 0x10;
1304 c->eax = env->tsc_khz;
1305 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1306 * APIC_BUS_CYCLE_NS */
1307 c->ebx = 1000000;
1308 c->ecx = c->edx = 0;
1309
1310 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1311 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1312 }
1313
1314 cpuid_data.cpuid.nent = cpuid_i;
1315
1316 cpuid_data.cpuid.padding = 0;
1317 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1318 if (r) {
1319 goto fail;
1320 }
1321
28143b40 1322 if (has_xsave) {
5b8063c4 1323 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1324 }
d71b62a1 1325 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1326
273c515c
PB		 1327 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1328 has_msr_tsc_aux = false;
1329 }
d1ae67f6 1330
e9688fab
RK		 1331 r = hyperv_init_vcpu(cpu);
1332 if (r) {
1333 goto fail;
1334 }
1335
e7429073 1336 return 0;
fe44dc91
AA		 1337
1338 fail:
1339 migrate_del_blocker(invtsc_mig_blocker);
1340 return r;
05330448
AL		 1341}
1342
50a2c6e5 1343void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1344{
20d695a9 1345 CPUX86State *env = &cpu->env;
dd673288 1346
1a5e9d2f 1347 env->xcr0 = 1;
ddced198 1348 if (kvm_irqchip_in_kernel()) {
dd673288 1349 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1350 KVM_MP_STATE_UNINITIALIZED;
1351 } else {
1352 env->mp_state = KVM_MP_STATE_RUNNABLE;
1353 }
689141dd
RK		 1354
1355 if (cpu->hyperv_synic) {
1356 int i;
1357 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1358 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1359 }
606c34bf
RK		 1360
1361 hyperv_x86_synic_reset(cpu);
689141dd 1362 }
caa5af0f
JK		 1363}
1364
e0723c45
PB		 1365void kvm_arch_do_init_vcpu(X86CPU *cpu)
1366{
1367 CPUX86State *env = &cpu->env;
1368
1369 /* APs get directly into wait-for-SIPI state. */
1370 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1371 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1372 }
1373}
1374
f57bceb6
RH		 1375static int kvm_get_supported_feature_msrs(KVMState *s)
1376{
1377 int ret = 0;
1378
1379 if (kvm_feature_msrs != NULL) {
1380 return 0;
1381 }
1382
1383 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1384 return 0;
1385 }
1386
1387 struct kvm_msr_list msr_list;
1388
1389 msr_list.nmsrs = 0;
1390 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1391 if (ret < 0 && ret != -E2BIG) {
1392 error_report("Fetch KVM feature MSR list failed: %s",
1393 strerror(-ret));
1394 return ret;
1395 }
1396
1397 assert(msr_list.nmsrs > 0);
1398 kvm_feature_msrs = (struct kvm_msr_list *) \
1399 g_malloc0(sizeof(msr_list) +
1400 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1401
1402 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1403 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1404
1405 if (ret < 0) {
1406 error_report("Fetch KVM feature MSR list failed: %s",
1407 strerror(-ret));
1408 g_free(kvm_feature_msrs);
1409 kvm_feature_msrs = NULL;
1410 return ret;
1411 }
1412
1413 return 0;
1414}
1415
c3a3a7d3 1416static int kvm_get_supported_msrs(KVMState *s)
05330448 1417{
75b10c43 1418 static int kvm_supported_msrs;
c3a3a7d3 1419 int ret = 0;
05330448
AL		 1420
1421 /* first time */
75b10c43 1422 if (kvm_supported_msrs == 0) {
05330448
AL		 1423 struct kvm_msr_list msr_list, *kvm_msr_list;
1424
75b10c43 1425 kvm_supported_msrs = -1;
05330448
AL		 1426
1427 /* Obtain MSR list from KVM. These are the MSRs that we must
1428 * save/restore */
4c9f7372 1429 msr_list.nmsrs = 0;
c3a3a7d3 1430 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1431 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1432 return ret;
6fb6d245 1433 }
d9db889f
JK		 1434 /* Old kernel modules had a bug and could write beyond the provided
1435 memory. Allocate at least a safe amount of 1K. */
7267c094 1436 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1437 msr_list.nmsrs *
1438 sizeof(msr_list.indices[0])));
05330448 1439
55308450 1440 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1441 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1442 if (ret >= 0) {
1443 int i;
1444
1445 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1446 switch (kvm_msr_list->indices[i]) {
1447 case MSR_STAR:
c3a3a7d3 1448 has_msr_star = true;
1d268dec
LP		 1449 break;
1450 case MSR_VM_HSAVE_PA:
c3a3a7d3 1451 has_msr_hsave_pa = true;
1d268dec
LP		 1452 break;
1453 case MSR_TSC_AUX:
c9b8f6b6 1454 has_msr_tsc_aux = true;
1d268dec
LP		 1455 break;
1456 case MSR_TSC_ADJUST:
f28558d3 1457 has_msr_tsc_adjust = true;
1d268dec
LP		 1458 break;
1459 case MSR_IA32_TSCDEADLINE:
aa82ba54 1460 has_msr_tsc_deadline = true;
1d268dec
LP		 1461 break;
1462 case MSR_IA32_SMBASE:
fc12d72e 1463 has_msr_smbase = true;
1d268dec 1464 break;
e13713db
LA		 1465 case MSR_SMI_COUNT:
1466 has_msr_smi_count = true;
1467 break;
1d268dec 1468 case MSR_IA32_MISC_ENABLE:
21e87c46 1469 has_msr_misc_enable = true;
1d268dec
LP		 1470 break;
1471 case MSR_IA32_BNDCFGS:
79e9ebeb 1472 has_msr_bndcfgs = true;
1d268dec
LP		 1473 break;
1474 case MSR_IA32_XSS:
18cd2c17 1475 has_msr_xss = true;
3c254ab8 1476 break;
1d268dec 1477 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1478 has_msr_hv_crash = true;
1d268dec
LP		 1479 break;
1480 case HV_X64_MSR_RESET:
744b8a94 1481 has_msr_hv_reset = true;
1d268dec
LP		 1482 break;
1483 case HV_X64_MSR_VP_INDEX:
8c145d7c 1484 has_msr_hv_vpindex = true;
1d268dec
LP		 1485 break;
1486 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1487 has_msr_hv_runtime = true;
1d268dec
LP		 1488 break;
1489 case HV_X64_MSR_SCONTROL:
866eea9a 1490 has_msr_hv_synic = true;
1d268dec
LP		 1491 break;
1492 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1493 has_msr_hv_stimer = true;
1d268dec 1494 break;
d72bc7f6
LP		 1495 case HV_X64_MSR_TSC_FREQUENCY:
1496 has_msr_hv_frequencies = true;
1497 break;
ba6a4fd9
VK		 1498 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1499 has_msr_hv_reenlightenment = true;
1500 break;
a33a2cfe
PB		 1501 case MSR_IA32_SPEC_CTRL:
1502 has_msr_spec_ctrl = true;
1503 break;
cfeea0c0
KRW		 1504 case MSR_VIRT_SSBD:
1505 has_msr_virt_ssbd = true;
1506 break;
aec5e9c3
BD		 1507 case MSR_IA32_ARCH_CAPABILITIES:
1508 has_msr_arch_capabs = true;
1509 break;
ff99aa64 1510 }
05330448
AL		 1511 }
1512 }
1513
7267c094 1514 g_free(kvm_msr_list);
05330448
AL		 1515 }
1516
c3a3a7d3 1517 return ret;
05330448
AL		 1518}
1519
6410848b
PB		 1520static Notifier smram_machine_done;
1521static KVMMemoryListener smram_listener;
1522static AddressSpace smram_address_space;
1523static MemoryRegion smram_as_root;
1524static MemoryRegion smram_as_mem;
1525
1526static void register_smram_listener(Notifier *n, void *unused)
1527{
1528 MemoryRegion *smram =
1529 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1530
1531 /* Outer container... */
1532 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1533 memory_region_set_enabled(&smram_as_root, true);
1534
1535 /* ... with two regions inside: normal system memory with low
1536 * priority, and...
1537 */
1538 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1539 get_system_memory(), 0, ~0ull);
1540 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1541 memory_region_set_enabled(&smram_as_mem, true);
1542
1543 if (smram) {
1544 /* ... SMRAM with higher priority */
1545 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1546 memory_region_set_enabled(smram, true);
1547 }
1548
1549 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1550 kvm_memory_listener_register(kvm_state, &smram_listener,
1551 &smram_address_space, 1);
1552}
1553
b16565b3 1554int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1555{
11076198 1556 uint64_t identity_base = 0xfffbc000;
39d6960a 1557 uint64_t shadow_mem;
20420430 1558 int ret;
25d2e361 1559 struct utsname utsname;
20420430 1560
28143b40 1561 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1562 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1563 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1564
e9688fab
RK		 1565 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1566
c3a3a7d3 1567 ret = kvm_get_supported_msrs(s);
20420430 1568 if (ret < 0) {
20420430
SY		 1569 return ret;
1570 }
25d2e361 1571
f57bceb6
RH		 1572 kvm_get_supported_feature_msrs(s);
1573
25d2e361
MT		 1574 uname(&utsname);
1575 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1576
4c5b10b7 1577 /*
11076198
JK		 1578 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1579 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1580 * Since these must be part of guest physical memory, we need to allocate
1581 * them, both by setting their start addresses in the kernel and by
1582 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1583 *
1584 * Older KVM versions may not support setting the identity map base. In
1585 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1586 * size.
4c5b10b7 1587 */
11076198
JK		 1588 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1589 /* Allows up to 16M BIOSes. */
1590 identity_base = 0xfeffc000;
1591
1592 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1593 if (ret < 0) {
1594 return ret;
1595 }
4c5b10b7 1596 }
e56ff191 1597
11076198
JK		 1598 /* Set TSS base one page after EPT identity map. */
1599 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1600 if (ret < 0) {
1601 return ret;
1602 }
1603
11076198
JK		 1604 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1605 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1606 if (ret < 0) {
11076198 1607 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1608 return ret;
1609 }
3c85e74f 1610 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1611
4689b77b 1612 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1613 if (shadow_mem != -1) {
1614 shadow_mem /= 4096;
1615 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1616 if (ret < 0) {
1617 return ret;
39d6960a
JK		 1618 }
1619 }
6410848b 1620
d870cfde
GA		 1621 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1622 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1623 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1624 smram_machine_done.notify = register_smram_listener;
1625 qemu_add_machine_init_done_notifier(&smram_machine_done);
1626 }
6f131f13
MT		 1627
1628 if (enable_cpu_pm) {
1629 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1630 int ret;
1631
1632/* Work around for kernel header with a typo. TODO: fix header and drop. */
1633#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1634#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1635#endif
1636 if (disable_exits) {
1637 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1638 KVM_X86_DISABLE_EXITS_HLT |
1639 KVM_X86_DISABLE_EXITS_PAUSE);
1640 }
1641
1642 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1643 disable_exits);
1644 if (ret < 0) {
1645 error_report("kvm: guest stopping CPU not supported: %s",
1646 strerror(-ret));
1647 }
1648 }
1649
11076198 1650 return 0;
05330448 1651}
b9bec74b 1652
05330448
AL		 1653static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1654{
1655 lhs->selector = rhs->selector;
1656 lhs->base = rhs->base;
1657 lhs->limit = rhs->limit;
1658 lhs->type = 3;
1659 lhs->present = 1;
1660 lhs->dpl = 3;
1661 lhs->db = 0;
1662 lhs->s = 1;
1663 lhs->l = 0;
1664 lhs->g = 0;
1665 lhs->avl = 0;
1666 lhs->unusable = 0;
1667}
1668
1669static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1670{
1671 unsigned flags = rhs->flags;
1672 lhs->selector = rhs->selector;
1673 lhs->base = rhs->base;
1674 lhs->limit = rhs->limit;
1675 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1676 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1677 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1678 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1679 lhs->s = (flags & DESC_S_MASK) != 0;
1680 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1681 lhs->g = (flags & DESC_G_MASK) != 0;
1682 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1683 lhs->unusable = !lhs->present;
7e680753 1684 lhs->padding = 0;
05330448
AL		 1685}
1686
1687static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1688{
1689 lhs->selector = rhs->selector;
1690 lhs->base = rhs->base;
1691 lhs->limit = rhs->limit;
d45fc087
RP		 1692 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1693 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1694 (rhs->dpl << DESC_DPL_SHIFT) |
1695 (rhs->db << DESC_B_SHIFT) |
1696 (rhs->s * DESC_S_MASK) |
1697 (rhs->l << DESC_L_SHIFT) |
1698 (rhs->g * DESC_G_MASK) |
1699 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1700}
1701
1702static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1703{
b9bec74b 1704 if (set) {
05330448 1705 *kvm_reg = *qemu_reg;
b9bec74b 1706 } else {
05330448 1707 *qemu_reg = *kvm_reg;
b9bec74b 1708 }
05330448
AL		 1709}
1710
1bc22652 1711static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1712{
1bc22652 1713 CPUX86State *env = &cpu->env;
05330448
AL		 1714 struct kvm_regs regs;
1715 int ret = 0;
1716
1717 if (!set) {
1bc22652 1718 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1719 if (ret < 0) {
05330448 1720 return ret;
b9bec74b 1721 }
05330448
AL		 1722 }
1723
1724 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1725 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1726 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1727 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1728 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1729 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1730 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1731 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1732#ifdef TARGET_X86_64
1733 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1734 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1735 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1736 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1737 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1738 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1739 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1740 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1741#endif
1742
1743 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1744 kvm_getput_reg(&regs.rip, &env->eip, set);
1745
b9bec74b 1746 if (set) {
1bc22652 1747 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1748 }
05330448
AL		 1749
1750 return ret;
1751}
1752
1bc22652 1753static int kvm_put_fpu(X86CPU *cpu)
05330448 1754{
1bc22652 1755 CPUX86State *env = &cpu->env;
05330448
AL		 1756 struct kvm_fpu fpu;
1757 int i;
1758
1759 memset(&fpu, 0, sizeof fpu);
1760 fpu.fsw = env->fpus & ~(7 << 11);
1761 fpu.fsw |= (env->fpstt & 7) << 11;
1762 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1763 fpu.last_opcode = env->fpop;
1764 fpu.last_ip = env->fpip;
1765 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1766 for (i = 0; i < 8; ++i) {
1767 fpu.ftwx |= (!env->fptags[i]) << i;
1768 }
05330448 1769 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1770 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1771 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1772 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1773 }
05330448
AL		 1774 fpu.mxcsr = env->mxcsr;
1775
1bc22652 1776 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1777}
1778
6b42494b
JK		 1779#define XSAVE_FCW_FSW 0
1780#define XSAVE_FTW_FOP 1
f1665b21
SY		 1781#define XSAVE_CWD_RIP 2
1782#define XSAVE_CWD_RDP 4
1783#define XSAVE_MXCSR 6
1784#define XSAVE_ST_SPACE 8
1785#define XSAVE_XMM_SPACE 40
1786#define XSAVE_XSTATE_BV 128
1787#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1788#define XSAVE_BNDREGS 240
1789#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1790#define XSAVE_OPMASK 272
1791#define XSAVE_ZMM_Hi256 288
1792#define XSAVE_Hi16_ZMM 416
f74eefe0 1793#define XSAVE_PKRU 672
f1665b21 1794
b503717d 1795#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 1796 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 1797
1798#define ASSERT_OFFSET(word_offset, field) \
1799 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1800 offsetof(X86XSaveArea, field))
1801
1802ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1803ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1804ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1805ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1806ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1807ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1808ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1809ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1810ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1811ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1812ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1813ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1814ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1815ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1816ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1817
1bc22652 1818static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1819{
1bc22652 1820 CPUX86State *env = &cpu->env;
5b8063c4 1821 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 1822
28143b40 1823 if (!has_xsave) {
1bc22652 1824 return kvm_put_fpu(cpu);
b9bec74b 1825 }
86a57621 1826 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1827
9be38598 1828 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1829}
1830
1bc22652 1831static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1832{
1bc22652 1833 CPUX86State *env = &cpu->env;
bdfc8480 1834 struct kvm_xcrs xcrs = {};
f1665b21 1835
28143b40 1836 if (!has_xcrs) {
f1665b21 1837 return 0;
b9bec74b 1838 }
f1665b21
SY		 1839
1840 xcrs.nr_xcrs = 1;
1841 xcrs.flags = 0;
1842 xcrs.xcrs[0].xcr = 0;
1843 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1844 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1845}
1846
1bc22652 1847static int kvm_put_sregs(X86CPU *cpu)
05330448 1848{
1bc22652 1849 CPUX86State *env = &cpu->env;
05330448
AL		 1850 struct kvm_sregs sregs;
1851
0e607a80
JK		 1852 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1853 if (env->interrupt_injected >= 0) {
1854 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1855 (uint64_t)1 << (env->interrupt_injected % 64);
1856 }
05330448
AL		 1857
1858 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1859 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1860 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1861 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1862 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1863 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1864 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1865 } else {
b9bec74b
JK		 1866 set_seg(&sregs.cs, &env->segs[R_CS]);
1867 set_seg(&sregs.ds, &env->segs[R_DS]);
1868 set_seg(&sregs.es, &env->segs[R_ES]);
1869 set_seg(&sregs.fs, &env->segs[R_FS]);
1870 set_seg(&sregs.gs, &env->segs[R_GS]);
1871 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1872 }
1873
1874 set_seg(&sregs.tr, &env->tr);
1875 set_seg(&sregs.ldt, &env->ldt);
1876
1877 sregs.idt.limit = env->idt.limit;
1878 sregs.idt.base = env->idt.base;
7e680753 1879 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1880 sregs.gdt.limit = env->gdt.limit;
1881 sregs.gdt.base = env->gdt.base;
7e680753 1882 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1883
1884 sregs.cr0 = env->cr[0];
1885 sregs.cr2 = env->cr[2];
1886 sregs.cr3 = env->cr[3];
1887 sregs.cr4 = env->cr[4];
1888
02e51483
CF		 1889 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1890 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1891
1892 sregs.efer = env->efer;
1893
1bc22652 1894 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1895}
1896
d71b62a1
EH		 1897static void kvm_msr_buf_reset(X86CPU *cpu)
1898{
1899 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1900}
1901
9c600a84
EH		 1902static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1903{
1904 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1905 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1906 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1907
1908 assert((void *)(entry + 1) <= limit);
1909
1abc2cae
EH		 1910 entry->index = index;
1911 entry->reserved = 0;
1912 entry->data = value;
9c600a84
EH		 1913 msrs->nmsrs++;
1914}
1915
73e1b8f2
PB		 1916static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1917{
1918 kvm_msr_buf_reset(cpu);
1919 kvm_msr_entry_add(cpu, index, value);
1920
1921 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1922}
1923
f8d9ccf8
DDAG		 1924void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1925{
1926 int ret;
1927
1928 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1929 assert(ret == 1);
1930}
1931
7477cd38
MT		 1932static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1933{
1934 CPUX86State *env = &cpu->env;
48e1a45c 1935 int ret;
7477cd38
MT		 1936
1937 if (!has_msr_tsc_deadline) {
1938 return 0;
1939 }
1940
73e1b8f2 1941 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1942 if (ret < 0) {
1943 return ret;
1944 }
1945
1946 assert(ret == 1);
1947 return 0;
7477cd38
MT		 1948}
1949
6bdf863d
JK		 1950/*
1951 * Provide a separate write service for the feature control MSR in order to
1952 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1953 * before writing any other state because forcibly leaving nested mode
1954 * invalidates the VCPU state.
1955 */
1956static int kvm_put_msr_feature_control(X86CPU *cpu)
1957{
48e1a45c
PB		 1958 int ret;
1959
1960 if (!has_msr_feature_control) {
1961 return 0;
1962 }
6bdf863d 1963
73e1b8f2
PB		 1964 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1965 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1966 if (ret < 0) {
1967 return ret;
1968 }
1969
1970 assert(ret == 1);
1971 return 0;
6bdf863d
JK		 1972}
1973
1bc22652 1974static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1975{
1bc22652 1976 CPUX86State *env = &cpu->env;
9c600a84 1977 int i;
48e1a45c 1978 int ret;
05330448 1979
d71b62a1
EH		 1980 kvm_msr_buf_reset(cpu);
1981
9c600a84
EH		 1982 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1983 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1984 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1985 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1986 if (has_msr_star) {
9c600a84 1987 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1988 }
c3a3a7d3 1989 if (has_msr_hsave_pa) {
9c600a84 1990 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1991 }
c9b8f6b6 1992 if (has_msr_tsc_aux) {
9c600a84 1993 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1994 }
f28558d3 1995 if (has_msr_tsc_adjust) {
9c600a84 1996 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1997 }
21e87c46 1998 if (has_msr_misc_enable) {
9c600a84 1999 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2000 env->msr_ia32_misc_enable);
2001 }
fc12d72e 2002 if (has_msr_smbase) {
9c600a84 2003 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2004 }
e13713db
LA		 2005 if (has_msr_smi_count) {
2006 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2007 }
439d19f2 2008 if (has_msr_bndcfgs) {
9c600a84 2009 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2010 }
18cd2c17 2011 if (has_msr_xss) {
9c600a84 2012 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2013 }
a33a2cfe
PB		 2014 if (has_msr_spec_ctrl) {
2015 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2016 }
cfeea0c0
KRW		 2017 if (has_msr_virt_ssbd) {
2018 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2019 }
2020
05330448 2021#ifdef TARGET_X86_64
25d2e361 2022 if (lm_capable_kernel) {
9c600a84
EH		 2023 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2024 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2025 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2026 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2027 }
05330448 2028#endif
a33a2cfe 2029
d86f9636 2030 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2031 if (has_msr_arch_capabs) {
2032 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2033 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2034 }
2035
ff5c186b 2036 /*
0d894367
PB		 2037 * The following MSRs have side effects on the guest or are too heavy
2038 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2039 */
2040 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2041 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2042 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2043 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2044 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2045 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2046 }
55c911a5 2047 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2048 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2049 }
55c911a5 2050 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2051 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2052 }
0b368a10
JD		 2053 if (has_architectural_pmu_version > 0) {
2054 if (has_architectural_pmu_version > 1) {
2055 /* Stop the counter. */
2056 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2057 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2058 }
0d894367
PB		 2059
2060 /* Set the counter values. */
0b368a10 2061 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2062 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2063 env->msr_fixed_counters[i]);
2064 }
0b368a10 2065 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2066 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2067 env->msr_gp_counters[i]);
9c600a84 2068 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2069 env->msr_gp_evtsel[i]);
2070 }
0b368a10
JD		 2071 if (has_architectural_pmu_version > 1) {
2072 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2073 env->msr_global_status);
2074 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2075 env->msr_global_ovf_ctrl);
2076
2077 /* Now start the PMU. */
2078 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2079 env->msr_fixed_ctr_ctrl);
2080 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2081 env->msr_global_ctrl);
2082 }
0d894367 2083 }
da1cc323
EY		 2084 /*
2085 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2086 * only sync them to KVM on the first cpu
2087 */
2088 if (current_cpu == first_cpu) {
2089 if (has_msr_hv_hypercall) {
2090 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2091 env->msr_hv_guest_os_id);
2092 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2093 env->msr_hv_hypercall);
2094 }
2095 if (cpu->hyperv_time) {
2096 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2097 env->msr_hv_tsc);
2098 }
ba6a4fd9
VK		 2099 if (cpu->hyperv_reenlightenment) {
2100 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2101 env->msr_hv_reenlightenment_control);
2102 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2103 env->msr_hv_tsc_emulation_control);
2104 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2105 env->msr_hv_tsc_emulation_status);
2106 }
eab70139 2107 }
2d5aa872 2108 if (cpu->hyperv_vapic) {
9c600a84 2109 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2110 env->msr_hv_vapic);
eab70139 2111 }
f2a53c9e
AS		 2112 if (has_msr_hv_crash) {
2113 int j;
2114
5e953812 2115 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2116 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2117 env->msr_hv_crash_params[j]);
2118
5e953812 2119 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2120 }
46eb8f98 2121 if (has_msr_hv_runtime) {
9c600a84 2122 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2123 }
e9688fab 2124 if (cpu->hyperv_vpindex && hv_vpindex_settable) {
701189e3
RK		 2125 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2126 hyperv_vp_index(CPU(cpu)));
e9688fab 2127 }
866eea9a
AS		 2128 if (cpu->hyperv_synic) {
2129 int j;
2130
09df29b6
RK		 2131 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2132
9c600a84 2133 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2134 env->msr_hv_synic_control);
9c600a84 2135 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2136 env->msr_hv_synic_evt_page);
9c600a84 2137 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2138 env->msr_hv_synic_msg_page);
2139
2140 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2141 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2142 env->msr_hv_synic_sint[j]);
2143 }
2144 }
ff99aa64
AS		 2145 if (has_msr_hv_stimer) {
2146 int j;
2147
2148 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2149 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2150 env->msr_hv_stimer_config[j]);
2151 }
2152
2153 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2154 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2155 env->msr_hv_stimer_count[j]);
2156 }
2157 }
1eabfce6 2158 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2159 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2160
9c600a84
EH		 2161 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2162 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2163 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2164 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2165 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2166 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2167 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2168 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2169 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2170 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2171 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2172 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2173 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2174 /* The CPU GPs if we write to a bit above the physical limit of
2175 * the host CPU (and KVM emulates that)
2176 */
2177 uint64_t mask = env->mtrr_var[i].mask;
2178 mask &= phys_mask;
2179
9c600a84
EH		 2180 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2181 env->mtrr_var[i].base);
112dad69 2182 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2183 }
2184 }
b77146e9
CP		 2185 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2186 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2187 0x14, 1, R_EAX) & 0x7;
2188
2189 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2190 env->msr_rtit_ctrl);
2191 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2192 env->msr_rtit_status);
2193 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2194 env->msr_rtit_output_base);
2195 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2196 env->msr_rtit_output_mask);
2197 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2198 env->msr_rtit_cr3_match);
2199 for (i = 0; i < addr_num; i++) {
2200 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2201 env->msr_rtit_addrs[i]);
2202 }
2203 }
6bdf863d
JK		 2204
2205 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2206 * kvm_put_msr_feature_control. */
ea643051 2207 }
57780495 2208 if (env->mcg_cap) {
d8da8574 2209 int i;
b9bec74b 2210
9c600a84
EH		 2211 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2212 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2213 if (has_msr_mcg_ext_ctl) {
2214 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2215 }
c34d440a 2216 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2217 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2218 }
2219 }
1a03675d 2220
d71b62a1 2221 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2222 if (ret < 0) {
2223 return ret;
2224 }
05330448 2225
c70b11d1
EH		 2226 if (ret < cpu->kvm_msr_buf->nmsrs) {
2227 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2228 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2229 (uint32_t)e->index, (uint64_t)e->data);
2230 }
2231
9c600a84 2232 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2233 return 0;
05330448
AL		 2234}
2235
2236
1bc22652 2237static int kvm_get_fpu(X86CPU *cpu)
05330448 2238{
1bc22652 2239 CPUX86State *env = &cpu->env;
05330448
AL		 2240 struct kvm_fpu fpu;
2241 int i, ret;
2242
1bc22652 2243 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2244 if (ret < 0) {
05330448 2245 return ret;
b9bec74b 2246 }
05330448
AL		 2247
2248 env->fpstt = (fpu.fsw >> 11) & 7;
2249 env->fpus = fpu.fsw;
2250 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2251 env->fpop = fpu.last_opcode;
2252 env->fpip = fpu.last_ip;
2253 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2254 for (i = 0; i < 8; ++i) {
2255 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2256 }
05330448 2257 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2258 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2259 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2260 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2261 }
05330448
AL		 2262 env->mxcsr = fpu.mxcsr;
2263
2264 return 0;
2265}
2266
1bc22652 2267static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2268{
1bc22652 2269 CPUX86State *env = &cpu->env;
5b8063c4 2270 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2271 int ret;
f1665b21 2272
28143b40 2273 if (!has_xsave) {
1bc22652 2274 return kvm_get_fpu(cpu);
b9bec74b 2275 }
f1665b21 2276
1bc22652 2277 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2278 if (ret < 0) {
f1665b21 2279 return ret;
0f53994f 2280 }
86a57621 2281 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2282
f1665b21 2283 return 0;
f1665b21
SY		 2284}
2285
1bc22652 2286static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2287{
1bc22652 2288 CPUX86State *env = &cpu->env;
f1665b21
SY		 2289 int i, ret;
2290 struct kvm_xcrs xcrs;
2291
28143b40 2292 if (!has_xcrs) {
f1665b21 2293 return 0;
b9bec74b 2294 }
f1665b21 2295
1bc22652 2296 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2297 if (ret < 0) {
f1665b21 2298 return ret;
b9bec74b 2299 }
f1665b21 2300
b9bec74b 2301 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2302 /* Only support xcr0 now */
0fd53fec
PB		 2303 if (xcrs.xcrs[i].xcr == 0) {
2304 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2305 break;
2306 }
b9bec74b 2307 }
f1665b21 2308 return 0;
f1665b21
SY		 2309}
2310
1bc22652 2311static int kvm_get_sregs(X86CPU *cpu)
05330448 2312{
1bc22652 2313 CPUX86State *env = &cpu->env;
05330448 2314 struct kvm_sregs sregs;
0e607a80 2315 int bit, i, ret;
05330448 2316
1bc22652 2317 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2318 if (ret < 0) {
05330448 2319 return ret;
b9bec74b 2320 }
05330448 2321
0e607a80
JK		 2322 /* There can only be one pending IRQ set in the bitmap at a time, so try
2323 to find it and save its number instead (-1 for none). */
2324 env->interrupt_injected = -1;
2325 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2326 if (sregs.interrupt_bitmap[i]) {
2327 bit = ctz64(sregs.interrupt_bitmap[i]);
2328 env->interrupt_injected = i * 64 + bit;
2329 break;
2330 }
2331 }
05330448
AL		 2332
2333 get_seg(&env->segs[R_CS], &sregs.cs);
2334 get_seg(&env->segs[R_DS], &sregs.ds);
2335 get_seg(&env->segs[R_ES], &sregs.es);
2336 get_seg(&env->segs[R_FS], &sregs.fs);
2337 get_seg(&env->segs[R_GS], &sregs.gs);
2338 get_seg(&env->segs[R_SS], &sregs.ss);
2339
2340 get_seg(&env->tr, &sregs.tr);
2341 get_seg(&env->ldt, &sregs.ldt);
2342
2343 env->idt.limit = sregs.idt.limit;
2344 env->idt.base = sregs.idt.base;
2345 env->gdt.limit = sregs.gdt.limit;
2346 env->gdt.base = sregs.gdt.base;
2347
2348 env->cr[0] = sregs.cr0;
2349 env->cr[2] = sregs.cr2;
2350 env->cr[3] = sregs.cr3;
2351 env->cr[4] = sregs.cr4;
2352
05330448 2353 env->efer = sregs.efer;
cce47516
JK		 2354
2355 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2356 x86_update_hflags(env);
05330448
AL		 2357
2358 return 0;
2359}
2360
1bc22652 2361static int kvm_get_msrs(X86CPU *cpu)
05330448 2362{
1bc22652 2363 CPUX86State *env = &cpu->env;
d71b62a1 2364 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2365 int ret, i;
fcc35e7c 2366 uint64_t mtrr_top_bits;
05330448 2367
d71b62a1
EH		 2368 kvm_msr_buf_reset(cpu);
2369
9c600a84
EH		 2370 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2371 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2372 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2373 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2374 if (has_msr_star) {
9c600a84 2375 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2376 }
c3a3a7d3 2377 if (has_msr_hsave_pa) {
9c600a84 2378 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2379 }
c9b8f6b6 2380 if (has_msr_tsc_aux) {
9c600a84 2381 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2382 }
f28558d3 2383 if (has_msr_tsc_adjust) {
9c600a84 2384 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2385 }
aa82ba54 2386 if (has_msr_tsc_deadline) {
9c600a84 2387 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2388 }
21e87c46 2389 if (has_msr_misc_enable) {
9c600a84 2390 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2391 }
fc12d72e 2392 if (has_msr_smbase) {
9c600a84 2393 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2394 }
e13713db
LA		 2395 if (has_msr_smi_count) {
2396 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2397 }
df67696e 2398 if (has_msr_feature_control) {
9c600a84 2399 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2400 }
79e9ebeb 2401 if (has_msr_bndcfgs) {
9c600a84 2402 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2403 }
18cd2c17 2404 if (has_msr_xss) {
9c600a84 2405 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2406 }
a33a2cfe
PB		 2407 if (has_msr_spec_ctrl) {
2408 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2409 }
cfeea0c0
KRW		 2410 if (has_msr_virt_ssbd) {
2411 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2412 }
b8cc45d6 2413 if (!env->tsc_valid) {
9c600a84 2414 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2415 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2416 }
2417
05330448 2418#ifdef TARGET_X86_64
25d2e361 2419 if (lm_capable_kernel) {
9c600a84
EH		 2420 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2421 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2422 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2423 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2424 }
05330448 2425#endif
9c600a84
EH		 2426 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2427 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2428 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2429 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2430 }
55c911a5 2431 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2432 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2433 }
55c911a5 2434 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2435 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2436 }
0b368a10
JD		 2437 if (has_architectural_pmu_version > 0) {
2438 if (has_architectural_pmu_version > 1) {
2439 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2440 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2441 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2442 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2443 }
2444 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2445 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2446 }
0b368a10 2447 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2448 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2449 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2450 }
2451 }
1a03675d 2452
57780495 2453 if (env->mcg_cap) {
9c600a84
EH		 2454 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2455 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2456 if (has_msr_mcg_ext_ctl) {
2457 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2458 }
b9bec74b 2459 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2460 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2461 }
57780495 2462 }
57780495 2463
1c90ef26 2464 if (has_msr_hv_hypercall) {
9c600a84
EH		 2465 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2466 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2467 }
2d5aa872 2468 if (cpu->hyperv_vapic) {
9c600a84 2469 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2470 }
3ddcd2ed 2471 if (cpu->hyperv_time) {
9c600a84 2472 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2473 }
ba6a4fd9
VK		 2474 if (cpu->hyperv_reenlightenment) {
2475 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2476 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2477 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2478 }
f2a53c9e
AS		 2479 if (has_msr_hv_crash) {
2480 int j;
2481
5e953812 2482 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2483 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2484 }
2485 }
46eb8f98 2486 if (has_msr_hv_runtime) {
9c600a84 2487 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2488 }
866eea9a
AS		 2489 if (cpu->hyperv_synic) {
2490 uint32_t msr;
2491
9c600a84 2492 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2493 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2494 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2495 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2496 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2497 }
2498 }
ff99aa64
AS		 2499 if (has_msr_hv_stimer) {
2500 uint32_t msr;
2501
2502 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2503 msr++) {
9c600a84 2504 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2505 }
2506 }
1eabfce6 2507 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2508 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2509 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2510 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2511 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2512 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2513 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2514 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2515 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2516 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2517 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2518 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2519 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2520 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2521 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2522 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2523 }
2524 }
5ef68987 2525
b77146e9
CP		 2526 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2527 int addr_num =
2528 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2529
2530 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2531 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2532 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2533 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2534 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2535 for (i = 0; i < addr_num; i++) {
2536 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2537 }
2538 }
2539
d71b62a1 2540 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2541 if (ret < 0) {
05330448 2542 return ret;
b9bec74b 2543 }
05330448 2544
c70b11d1
EH		 2545 if (ret < cpu->kvm_msr_buf->nmsrs) {
2546 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2547 error_report("error: failed to get MSR 0x%" PRIx32,
2548 (uint32_t)e->index);
2549 }
2550
9c600a84 2551 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2552 /*
2553 * MTRR masks: Each mask consists of 5 parts
2554 * a 10..0: must be zero
2555 * b 11 : valid bit
2556 * c n-1.12: actual mask bits
2557 * d 51..n: reserved must be zero
2558 * e 63.52: reserved must be zero
2559 *
2560 * 'n' is the number of physical bits supported by the CPU and is
2561 * apparently always <= 52. We know our 'n' but don't know what
2562 * the destinations 'n' is; it might be smaller, in which case
2563 * it masks (c) on loading. It might be larger, in which case
2564 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2565 * we're migrating to.
2566 */
2567
2568 if (cpu->fill_mtrr_mask) {
2569 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2570 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2571 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2572 } else {
2573 mtrr_top_bits = 0;
2574 }
2575
05330448 2576 for (i = 0; i < ret; i++) {
0d894367
PB		 2577 uint32_t index = msrs[i].index;
2578 switch (index) {
05330448
AL		 2579 case MSR_IA32_SYSENTER_CS:
2580 env->sysenter_cs = msrs[i].data;
2581 break;
2582 case MSR_IA32_SYSENTER_ESP:
2583 env->sysenter_esp = msrs[i].data;
2584 break;
2585 case MSR_IA32_SYSENTER_EIP:
2586 env->sysenter_eip = msrs[i].data;
2587 break;
0c03266a
JK		 2588 case MSR_PAT:
2589 env->pat = msrs[i].data;
2590 break;
05330448
AL		 2591 case MSR_STAR:
2592 env->star = msrs[i].data;
2593 break;
2594#ifdef TARGET_X86_64
2595 case MSR_CSTAR:
2596 env->cstar = msrs[i].data;
2597 break;
2598 case MSR_KERNELGSBASE:
2599 env->kernelgsbase = msrs[i].data;
2600 break;
2601 case MSR_FMASK:
2602 env->fmask = msrs[i].data;
2603 break;
2604 case MSR_LSTAR:
2605 env->lstar = msrs[i].data;
2606 break;
2607#endif
2608 case MSR_IA32_TSC:
2609 env->tsc = msrs[i].data;
2610 break;
c9b8f6b6
AS		 2611 case MSR_TSC_AUX:
2612 env->tsc_aux = msrs[i].data;
2613 break;
f28558d3
WA		 2614 case MSR_TSC_ADJUST:
2615 env->tsc_adjust = msrs[i].data;
2616 break;
aa82ba54
LJ		 2617 case MSR_IA32_TSCDEADLINE:
2618 env->tsc_deadline = msrs[i].data;
2619 break;
aa851e36
MT		 2620 case MSR_VM_HSAVE_PA:
2621 env->vm_hsave = msrs[i].data;
2622 break;
1a03675d
GC		 2623 case MSR_KVM_SYSTEM_TIME:
2624 env->system_time_msr = msrs[i].data;
2625 break;
2626 case MSR_KVM_WALL_CLOCK:
2627 env->wall_clock_msr = msrs[i].data;
2628 break;
57780495
MT		 2629 case MSR_MCG_STATUS:
2630 env->mcg_status = msrs[i].data;
2631 break;
2632 case MSR_MCG_CTL:
2633 env->mcg_ctl = msrs[i].data;
2634 break;
87f8b626
AR		 2635 case MSR_MCG_EXT_CTL:
2636 env->mcg_ext_ctl = msrs[i].data;
2637 break;
21e87c46
AK		 2638 case MSR_IA32_MISC_ENABLE:
2639 env->msr_ia32_misc_enable = msrs[i].data;
2640 break;
fc12d72e
PB		 2641 case MSR_IA32_SMBASE:
2642 env->smbase = msrs[i].data;
2643 break;
e13713db
LA		 2644 case MSR_SMI_COUNT:
2645 env->msr_smi_count = msrs[i].data;
2646 break;
0779caeb
ACL		 2647 case MSR_IA32_FEATURE_CONTROL:
2648 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2649 break;
79e9ebeb
LJ		 2650 case MSR_IA32_BNDCFGS:
2651 env->msr_bndcfgs = msrs[i].data;
2652 break;
18cd2c17
WL		 2653 case MSR_IA32_XSS:
2654 env->xss = msrs[i].data;
2655 break;
57780495 2656 default:
57780495
MT		 2657 if (msrs[i].index >= MSR_MC0_CTL &&
2658 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2659 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2660 }
d8da8574 2661 break;
f6584ee2
GN		 2662 case MSR_KVM_ASYNC_PF_EN:
2663 env->async_pf_en_msr = msrs[i].data;
2664 break;
bc9a839d
MT		 2665 case MSR_KVM_PV_EOI_EN:
2666 env->pv_eoi_en_msr = msrs[i].data;
2667 break;
917367aa
MT		 2668 case MSR_KVM_STEAL_TIME:
2669 env->steal_time_msr = msrs[i].data;
2670 break;
0d894367
PB		 2671 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2672 env->msr_fixed_ctr_ctrl = msrs[i].data;
2673 break;
2674 case MSR_CORE_PERF_GLOBAL_CTRL:
2675 env->msr_global_ctrl = msrs[i].data;
2676 break;
2677 case MSR_CORE_PERF_GLOBAL_STATUS:
2678 env->msr_global_status = msrs[i].data;
2679 break;
2680 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2681 env->msr_global_ovf_ctrl = msrs[i].data;
2682 break;
2683 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2684 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2685 break;
2686 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2687 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2688 break;
2689 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2690 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2691 break;
1c90ef26
VR		 2692 case HV_X64_MSR_HYPERCALL:
2693 env->msr_hv_hypercall = msrs[i].data;
2694 break;
2695 case HV_X64_MSR_GUEST_OS_ID:
2696 env->msr_hv_guest_os_id = msrs[i].data;
2697 break;
5ef68987
VR		 2698 case HV_X64_MSR_APIC_ASSIST_PAGE:
2699 env->msr_hv_vapic = msrs[i].data;
2700 break;
48a5f3bc
VR		 2701 case HV_X64_MSR_REFERENCE_TSC:
2702 env->msr_hv_tsc = msrs[i].data;
2703 break;
f2a53c9e
AS		 2704 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2705 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2706 break;
46eb8f98
AS		 2707 case HV_X64_MSR_VP_RUNTIME:
2708 env->msr_hv_runtime = msrs[i].data;
2709 break;
866eea9a
AS		 2710 case HV_X64_MSR_SCONTROL:
2711 env->msr_hv_synic_control = msrs[i].data;
2712 break;
866eea9a
AS		 2713 case HV_X64_MSR_SIEFP:
2714 env->msr_hv_synic_evt_page = msrs[i].data;
2715 break;
2716 case HV_X64_MSR_SIMP:
2717 env->msr_hv_synic_msg_page = msrs[i].data;
2718 break;
2719 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2720 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2721 break;
2722 case HV_X64_MSR_STIMER0_CONFIG:
2723 case HV_X64_MSR_STIMER1_CONFIG:
2724 case HV_X64_MSR_STIMER2_CONFIG:
2725 case HV_X64_MSR_STIMER3_CONFIG:
2726 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2727 msrs[i].data;
2728 break;
2729 case HV_X64_MSR_STIMER0_COUNT:
2730 case HV_X64_MSR_STIMER1_COUNT:
2731 case HV_X64_MSR_STIMER2_COUNT:
2732 case HV_X64_MSR_STIMER3_COUNT:
2733 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2734 msrs[i].data;
866eea9a 2735 break;
ba6a4fd9
VK		 2736 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2737 env->msr_hv_reenlightenment_control = msrs[i].data;
2738 break;
2739 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2740 env->msr_hv_tsc_emulation_control = msrs[i].data;
2741 break;
2742 case HV_X64_MSR_TSC_EMULATION_STATUS:
2743 env->msr_hv_tsc_emulation_status = msrs[i].data;
2744 break;
d1ae67f6
AW		 2745 case MSR_MTRRdefType:
2746 env->mtrr_deftype = msrs[i].data;
2747 break;
2748 case MSR_MTRRfix64K_00000:
2749 env->mtrr_fixed[0] = msrs[i].data;
2750 break;
2751 case MSR_MTRRfix16K_80000:
2752 env->mtrr_fixed[1] = msrs[i].data;
2753 break;
2754 case MSR_MTRRfix16K_A0000:
2755 env->mtrr_fixed[2] = msrs[i].data;
2756 break;
2757 case MSR_MTRRfix4K_C0000:
2758 env->mtrr_fixed[3] = msrs[i].data;
2759 break;
2760 case MSR_MTRRfix4K_C8000:
2761 env->mtrr_fixed[4] = msrs[i].data;
2762 break;
2763 case MSR_MTRRfix4K_D0000:
2764 env->mtrr_fixed[5] = msrs[i].data;
2765 break;
2766 case MSR_MTRRfix4K_D8000:
2767 env->mtrr_fixed[6] = msrs[i].data;
2768 break;
2769 case MSR_MTRRfix4K_E0000:
2770 env->mtrr_fixed[7] = msrs[i].data;
2771 break;
2772 case MSR_MTRRfix4K_E8000:
2773 env->mtrr_fixed[8] = msrs[i].data;
2774 break;
2775 case MSR_MTRRfix4K_F0000:
2776 env->mtrr_fixed[9] = msrs[i].data;
2777 break;
2778 case MSR_MTRRfix4K_F8000:
2779 env->mtrr_fixed[10] = msrs[i].data;
2780 break;
2781 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2782 if (index & 1) {
fcc35e7c
DDAG		 2783 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2784 mtrr_top_bits;
d1ae67f6
AW		 2785 } else {
2786 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2787 }
2788 break;
a33a2cfe
PB		 2789 case MSR_IA32_SPEC_CTRL:
2790 env->spec_ctrl = msrs[i].data;
2791 break;
cfeea0c0
KRW		 2792 case MSR_VIRT_SSBD:
2793 env->virt_ssbd = msrs[i].data;
2794 break;
b77146e9
CP		 2795 case MSR_IA32_RTIT_CTL:
2796 env->msr_rtit_ctrl = msrs[i].data;
2797 break;
2798 case MSR_IA32_RTIT_STATUS:
2799 env->msr_rtit_status = msrs[i].data;
2800 break;
2801 case MSR_IA32_RTIT_OUTPUT_BASE:
2802 env->msr_rtit_output_base = msrs[i].data;
2803 break;
2804 case MSR_IA32_RTIT_OUTPUT_MASK:
2805 env->msr_rtit_output_mask = msrs[i].data;
2806 break;
2807 case MSR_IA32_RTIT_CR3_MATCH:
2808 env->msr_rtit_cr3_match = msrs[i].data;
2809 break;
2810 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2811 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2812 break;
05330448
AL		 2813 }
2814 }
2815
2816 return 0;
2817}
2818
1bc22652 2819static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2820{
1bc22652 2821 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2822
1bc22652 2823 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2824}
2825
23d02d9b 2826static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2827{
259186a7 2828 CPUState *cs = CPU(cpu);
23d02d9b 2829 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2830 struct kvm_mp_state mp_state;
2831 int ret;
2832
259186a7 2833 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2834 if (ret < 0) {
2835 return ret;
2836 }
2837 env->mp_state = mp_state.mp_state;
c14750e8 2838 if (kvm_irqchip_in_kernel()) {
259186a7 2839 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2840 }
9bdbe550
HB		 2841 return 0;
2842}
2843
1bc22652 2844static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2845{
02e51483 2846 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2847 struct kvm_lapic_state kapic;
2848 int ret;
2849
3d4b2649 2850 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2851 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2852 if (ret < 0) {
2853 return ret;
2854 }
2855
2856 kvm_get_apic_state(apic, &kapic);
2857 }
2858 return 0;
2859}
2860
1bc22652 2861static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2862{
fc12d72e 2863 CPUState *cs = CPU(cpu);
1bc22652 2864 CPUX86State *env = &cpu->env;
076796f8 2865 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2866
2867 if (!kvm_has_vcpu_events()) {
2868 return 0;
2869 }
2870
31827373
JK		 2871 events.exception.injected = (env->exception_injected >= 0);
2872 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2873 events.exception.has_error_code = env->has_error_code;
2874 events.exception.error_code = env->error_code;
2875
2876 events.interrupt.injected = (env->interrupt_injected >= 0);
2877 events.interrupt.nr = env->interrupt_injected;
2878 events.interrupt.soft = env->soft_interrupt;
2879
2880 events.nmi.injected = env->nmi_injected;
2881 events.nmi.pending = env->nmi_pending;
2882 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2883
2884 events.sipi_vector = env->sipi_vector;
68c6efe0 2885 events.flags = 0;
a0fb002c 2886
fc12d72e
PB		 2887 if (has_msr_smbase) {
2888 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2889 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2890 if (kvm_irqchip_in_kernel()) {
2891 /* As soon as these are moved to the kernel, remove them
2892 * from cs->interrupt_request.
2893 */
2894 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2895 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2896 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2897 } else {
2898 /* Keep these in cs->interrupt_request. */
2899 events.smi.pending = 0;
2900 events.smi.latched_init = 0;
2901 }
fc3a1fd7
DDAG		 2902 /* Stop SMI delivery on old machine types to avoid a reboot
2903 * on an inward migration of an old VM.
2904 */
2905 if (!cpu->kvm_no_smi_migration) {
2906 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2907 }
fc12d72e
PB		 2908 }
2909
ea643051 2910 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2911 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2912 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2913 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2914 }
ea643051 2915 }
aee028b9 2916
1bc22652 2917 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2918}
2919
1bc22652 2920static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2921{
1bc22652 2922 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2923 struct kvm_vcpu_events events;
2924 int ret;
2925
2926 if (!kvm_has_vcpu_events()) {
2927 return 0;
2928 }
2929
fc12d72e 2930 memset(&events, 0, sizeof(events));
1bc22652 2931 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2932 if (ret < 0) {
2933 return ret;
2934 }
31827373 2935 env->exception_injected =
a0fb002c
JK		 2936 events.exception.injected ? events.exception.nr : -1;
2937 env->has_error_code = events.exception.has_error_code;
2938 env->error_code = events.exception.error_code;
2939
2940 env->interrupt_injected =
2941 events.interrupt.injected ? events.interrupt.nr : -1;
2942 env->soft_interrupt = events.interrupt.soft;
2943
2944 env->nmi_injected = events.nmi.injected;
2945 env->nmi_pending = events.nmi.pending;
2946 if (events.nmi.masked) {
2947 env->hflags2 |= HF2_NMI_MASK;
2948 } else {
2949 env->hflags2 &= ~HF2_NMI_MASK;
2950 }
2951
fc12d72e
PB		 2952 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2953 if (events.smi.smm) {
2954 env->hflags |= HF_SMM_MASK;
2955 } else {
2956 env->hflags &= ~HF_SMM_MASK;
2957 }
2958 if (events.smi.pending) {
2959 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2960 } else {
2961 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2962 }
2963 if (events.smi.smm_inside_nmi) {
2964 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2965 } else {
2966 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2967 }
2968 if (events.smi.latched_init) {
2969 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2970 } else {
2971 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2972 }
2973 }
2974
a0fb002c 2975 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2976
2977 return 0;
2978}
2979
1bc22652 2980static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2981{
ed2803da 2982 CPUState *cs = CPU(cpu);
1bc22652 2983 CPUX86State *env = &cpu->env;
b0b1d690 2984 int ret = 0;
b0b1d690
JK		 2985 unsigned long reinject_trap = 0;
2986
2987 if (!kvm_has_vcpu_events()) {
2988 if (env->exception_injected == 1) {
2989 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2990 } else if (env->exception_injected == 3) {
2991 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2992 }
2993 env->exception_injected = -1;
2994 }
2995
2996 /*
2997 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2998 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2999 * by updating the debug state once again if single-stepping is on.
3000 * Another reason to call kvm_update_guest_debug here is a pending debug
3001 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3002 * reinject them via SET_GUEST_DEBUG.
3003 */
3004 if (reinject_trap ||
ed2803da 3005 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3006 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3007 }
b0b1d690
JK		 3008 return ret;
3009}
3010
1bc22652 3011static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3012{
1bc22652 3013 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3014 struct kvm_debugregs dbgregs;
3015 int i;
3016
3017 if (!kvm_has_debugregs()) {
3018 return 0;
3019 }
3020
3021 for (i = 0; i < 4; i++) {
3022 dbgregs.db[i] = env->dr[i];
3023 }
3024 dbgregs.dr6 = env->dr[6];
3025 dbgregs.dr7 = env->dr[7];
3026 dbgregs.flags = 0;
3027
1bc22652 3028 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3029}
3030
1bc22652 3031static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3032{
1bc22652 3033 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3034 struct kvm_debugregs dbgregs;
3035 int i, ret;
3036
3037 if (!kvm_has_debugregs()) {
3038 return 0;
3039 }
3040
1bc22652 3041 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3042 if (ret < 0) {
b9bec74b 3043 return ret;
ff44f1a3
JK		 3044 }
3045 for (i = 0; i < 4; i++) {
3046 env->dr[i] = dbgregs.db[i];
3047 }
3048 env->dr[4] = env->dr[6] = dbgregs.dr6;
3049 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3050
3051 return 0;
3052}
3053
20d695a9 3054int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3055{
20d695a9 3056 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3057 int ret;
3058
2fa45344 3059 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3060
48e1a45c 3061 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 3062 ret = kvm_put_msr_feature_control(x86_cpu);
3063 if (ret < 0) {
3064 return ret;
3065 }
3066 }
3067
36f96c4b
HZ		 3068 if (level == KVM_PUT_FULL_STATE) {
3069 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3070 * because TSC frequency mismatch shouldn't abort migration,
3071 * unless the user explicitly asked for a more strict TSC
3072 * setting (e.g. using an explicit "tsc-freq" option).
3073 */
3074 kvm_arch_set_tsc_khz(cpu);
3075 }
3076
1bc22652 3077 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3078 if (ret < 0) {
05330448 3079 return ret;
b9bec74b 3080 }
1bc22652 3081 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3082 if (ret < 0) {
f1665b21 3083 return ret;
b9bec74b 3084 }
1bc22652 3085 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3086 if (ret < 0) {
05330448 3087 return ret;
b9bec74b 3088 }
1bc22652 3089 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3090 if (ret < 0) {
05330448 3091 return ret;
b9bec74b 3092 }
ab443475 3093 /* must be before kvm_put_msrs */
1bc22652 3094 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3095 if (ret < 0) {
3096 return ret;
3097 }
1bc22652 3098 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3099 if (ret < 0) {
05330448 3100 return ret;
b9bec74b 3101 }
4fadfa00
PH		 3102 ret = kvm_put_vcpu_events(x86_cpu, level);
3103 if (ret < 0) {
3104 return ret;
3105 }
ea643051 3106 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3107 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3108 if (ret < 0) {
680c1c6f
JK		 3109 return ret;
3110 }
ea643051 3111 }
7477cd38
MT		 3112
3113 ret = kvm_put_tscdeadline_msr(x86_cpu);
3114 if (ret < 0) {
3115 return ret;
3116 }
1bc22652 3117 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3118 if (ret < 0) {
b0b1d690 3119 return ret;
b9bec74b 3120 }
b0b1d690 3121 /* must be last */
1bc22652 3122 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3123 if (ret < 0) {
ff44f1a3 3124 return ret;
b9bec74b 3125 }
05330448
AL		 3126 return 0;
3127}
3128
20d695a9 3129int kvm_arch_get_registers(CPUState *cs)
05330448 3130{
20d695a9 3131 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3132 int ret;
3133
20d695a9 3134 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3135
4fadfa00 3136 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3137 if (ret < 0) {
f4f1110e 3138 goto out;
b9bec74b 3139 }
4fadfa00
PH		 3140 /*
3141 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3142 * KVM_GET_REGS and KVM_GET_SREGS.
3143 */
3144 ret = kvm_get_mp_state(cpu);
b9bec74b 3145 if (ret < 0) {
f4f1110e 3146 goto out;
b9bec74b 3147 }
4fadfa00 3148 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3149 if (ret < 0) {
f4f1110e 3150 goto out;
b9bec74b 3151 }
4fadfa00 3152 ret = kvm_get_xsave(cpu);
b9bec74b 3153 if (ret < 0) {
f4f1110e 3154 goto out;
b9bec74b 3155 }
4fadfa00 3156 ret = kvm_get_xcrs(cpu);
b9bec74b 3157 if (ret < 0) {
f4f1110e 3158 goto out;
b9bec74b 3159 }
4fadfa00 3160 ret = kvm_get_sregs(cpu);
b9bec74b 3161 if (ret < 0) {
f4f1110e 3162 goto out;
b9bec74b 3163 }
4fadfa00 3164 ret = kvm_get_msrs(cpu);
680c1c6f 3165 if (ret < 0) {
f4f1110e 3166 goto out;
680c1c6f 3167 }
4fadfa00 3168 ret = kvm_get_apic(cpu);
b9bec74b 3169 if (ret < 0) {
f4f1110e 3170 goto out;
b9bec74b 3171 }
1bc22652 3172 ret = kvm_get_debugregs(cpu);
b9bec74b 3173 if (ret < 0) {
f4f1110e 3174 goto out;
b9bec74b 3175 }
f4f1110e
RH		 3176 ret = 0;
3177 out:
3178 cpu_sync_bndcs_hflags(&cpu->env);
3179 return ret;
05330448
AL		 3180}
3181
20d695a9 3182void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3183{
20d695a9
AF		 3184 X86CPU *x86_cpu = X86_CPU(cpu);
3185 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3186 int ret;
3187
276ce815 3188 /* Inject NMI */
fc12d72e
PB		 3189 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3190 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3191 qemu_mutex_lock_iothread();
3192 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3193 qemu_mutex_unlock_iothread();
3194 DPRINTF("injected NMI\n");
3195 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3196 if (ret < 0) {
3197 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3198 strerror(-ret));
3199 }
3200 }
3201 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3202 qemu_mutex_lock_iothread();
3203 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3204 qemu_mutex_unlock_iothread();
3205 DPRINTF("injected SMI\n");
3206 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3207 if (ret < 0) {
3208 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3209 strerror(-ret));
3210 }
ce377af3 3211 }
276ce815
LJ		 3212 }
3213
15eafc2e 3214 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3215 qemu_mutex_lock_iothread();
3216 }
3217
e0723c45
PB		 3218 /* Force the VCPU out of its inner loop to process any INIT requests
3219 * or (for userspace APIC, but it is cheap to combine the checks here)
3220 * pending TPR access reports.
3221 */
3222 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3223 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3224 !(env->hflags & HF_SMM_MASK)) {
3225 cpu->exit_request = 1;
3226 }
3227 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3228 cpu->exit_request = 1;
3229 }
e0723c45 3230 }
05330448 3231
15eafc2e 3232 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3233 /* Try to inject an interrupt if the guest can accept it */
3234 if (run->ready_for_interrupt_injection &&
259186a7 3235 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3236 (env->eflags & IF_MASK)) {
3237 int irq;
3238
259186a7 3239 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3240 irq = cpu_get_pic_interrupt(env);
3241 if (irq >= 0) {
3242 struct kvm_interrupt intr;
3243
3244 intr.irq = irq;
db1669bc 3245 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3246 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3247 if (ret < 0) {
3248 fprintf(stderr,
3249 "KVM: injection failed, interrupt lost (%s)\n",
3250 strerror(-ret));
3251 }
db1669bc
JK		 3252 }
3253 }
05330448 3254
db1669bc
JK		 3255 /* If we have an interrupt but the guest is not ready to receive an
3256 * interrupt, request an interrupt window exit. This will
3257 * cause a return to userspace as soon as the guest is ready to
3258 * receive interrupts. */
259186a7 3259 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3260 run->request_interrupt_window = 1;
3261 } else {
3262 run->request_interrupt_window = 0;
3263 }
3264
3265 DPRINTF("setting tpr\n");
02e51483 3266 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3267
3268 qemu_mutex_unlock_iothread();
db1669bc 3269 }
05330448
AL		 3270}
3271
4c663752 3272MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3273{
20d695a9
AF		 3274 X86CPU *x86_cpu = X86_CPU(cpu);
3275 CPUX86State *env = &x86_cpu->env;
3276
fc12d72e
PB		 3277 if (run->flags & KVM_RUN_X86_SMM) {
3278 env->hflags |= HF_SMM_MASK;
3279 } else {
f5c052b9 3280 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3281 }
b9bec74b 3282 if (run->if_flag) {
05330448 3283 env->eflags |= IF_MASK;
b9bec74b 3284 } else {
05330448 3285 env->eflags &= ~IF_MASK;
b9bec74b 3286 }
4b8523ee
JK		 3287
3288 /* We need to protect the apic state against concurrent accesses from
3289 * different threads in case the userspace irqchip is used. */
3290 if (!kvm_irqchip_in_kernel()) {
3291 qemu_mutex_lock_iothread();
3292 }
02e51483
CF		 3293 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3294 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3295 if (!kvm_irqchip_in_kernel()) {
3296 qemu_mutex_unlock_iothread();
3297 }
f794aa4a 3298 return cpu_get_mem_attrs(env);
05330448
AL		 3299}
3300
20d695a9 3301int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3302{
20d695a9
AF		 3303 X86CPU *cpu = X86_CPU(cs);
3304 CPUX86State *env = &cpu->env;
232fc23b 3305
259186a7 3306 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3307 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3308 assert(env->mcg_cap);
3309
259186a7 3310 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3311
dd1750d7 3312 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3313
3314 if (env->exception_injected == EXCP08_DBLE) {
3315 /* this means triple fault */
cf83f140 3316 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3317 cs->exit_request = 1;
ab443475
JK		 3318 return 0;
3319 }
3320 env->exception_injected = EXCP12_MCHK;
3321 env->has_error_code = 0;
3322
259186a7 3323 cs->halted = 0;
ab443475
JK		 3324 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3325 env->mp_state = KVM_MP_STATE_RUNNABLE;
3326 }
3327 }
3328
fc12d72e
PB		 3329 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3330 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3331 kvm_cpu_synchronize_state(cs);
3332 do_cpu_init(cpu);
3333 }
3334
db1669bc
JK		 3335 if (kvm_irqchip_in_kernel()) {
3336 return 0;
3337 }
3338
259186a7
AF		 3339 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3340 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3341 apic_poll_irq(cpu->apic_state);
5d62c43a 3342 }
259186a7 3343 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3344 (env->eflags & IF_MASK)) ||
259186a7
AF		 3345 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3346 cs->halted = 0;
6792a57b 3347 }
259186a7 3348 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3349 kvm_cpu_synchronize_state(cs);
232fc23b 3350 do_cpu_sipi(cpu);
0af691d7 3351 }
259186a7
AF		 3352 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3353 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3354 kvm_cpu_synchronize_state(cs);
02e51483 3355 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3356 env->tpr_access_type);
3357 }
0af691d7 3358
259186a7 3359 return cs->halted;
0af691d7
MT		 3360}
3361
839b5630 3362static int kvm_handle_halt(X86CPU *cpu)
05330448 3363{
259186a7 3364 CPUState *cs = CPU(cpu);
839b5630
AF		 3365 CPUX86State *env = &cpu->env;
3366
259186a7 3367 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3368 (env->eflags & IF_MASK)) &&
259186a7
AF		 3369 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3370 cs->halted = 1;
bb4ea393 3371 return EXCP_HLT;
05330448
AL		 3372 }
3373
bb4ea393 3374 return 0;
05330448
AL		 3375}
3376
f7575c96 3377static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3378{
f7575c96
AF		 3379 CPUState *cs = CPU(cpu);
3380 struct kvm_run *run = cs->kvm_run;
d362e757 3381
02e51483 3382 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3383 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3384 : TPR_ACCESS_READ);
3385 return 1;
3386}
3387
f17ec444 3388int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3389{
38972938 3390 static const uint8_t int3 = 0xcc;
64bf3f4e 3391
f17ec444
AF		 3392 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3393 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3394 return -EINVAL;
b9bec74b 3395 }
e22a25c9
AL		 3396 return 0;
3397}
3398
f17ec444 3399int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3400{
3401 uint8_t int3;
3402
f17ec444
AF		 3403 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3404 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3405 return -EINVAL;
b9bec74b 3406 }
e22a25c9
AL		 3407 return 0;
3408}
3409
3410static struct {
3411 target_ulong addr;
3412 int len;
3413 int type;
3414} hw_breakpoint[4];
3415
3416static int nb_hw_breakpoint;
3417
3418static int find_hw_breakpoint(target_ulong addr, int len, int type)
3419{
3420 int n;
3421
b9bec74b 3422 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3423 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3424 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3425 return n;
b9bec74b
JK		 3426 }
3427 }
e22a25c9
AL		 3428 return -1;
3429}
3430
3431int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3432 target_ulong len, int type)
3433{
3434 switch (type) {
3435 case GDB_BREAKPOINT_HW:
3436 len = 1;
3437 break;
3438 case GDB_WATCHPOINT_WRITE:
3439 case GDB_WATCHPOINT_ACCESS:
3440 switch (len) {
3441 case 1:
3442 break;
3443 case 2:
3444 case 4:
3445 case 8:
b9bec74b 3446 if (addr & (len - 1)) {
e22a25c9 3447 return -EINVAL;
b9bec74b 3448 }
e22a25c9
AL		 3449 break;
3450 default:
3451 return -EINVAL;
3452 }
3453 break;
3454 default:
3455 return -ENOSYS;
3456 }
3457
b9bec74b 3458 if (nb_hw_breakpoint == 4) {
e22a25c9 3459 return -ENOBUFS;
b9bec74b
JK		 3460 }
3461 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3462 return -EEXIST;
b9bec74b 3463 }
e22a25c9
AL		 3464 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3465 hw_breakpoint[nb_hw_breakpoint].len = len;
3466 hw_breakpoint[nb_hw_breakpoint].type = type;
3467 nb_hw_breakpoint++;
3468
3469 return 0;
3470}
3471
3472int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3473 target_ulong len, int type)
3474{
3475 int n;
3476
3477 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3478 if (n < 0) {
e22a25c9 3479 return -ENOENT;
b9bec74b 3480 }
e22a25c9
AL		 3481 nb_hw_breakpoint--;
3482 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3483
3484 return 0;
3485}
3486
3487void kvm_arch_remove_all_hw_breakpoints(void)
3488{
3489 nb_hw_breakpoint = 0;
3490}
3491
3492static CPUWatchpoint hw_watchpoint;
3493
a60f24b5 3494static int kvm_handle_debug(X86CPU *cpu,
48405526 3495 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3496{
ed2803da 3497 CPUState *cs = CPU(cpu);
a60f24b5 3498 CPUX86State *env = &cpu->env;
f2574737 3499 int ret = 0;
e22a25c9
AL		 3500 int n;
3501
3502 if (arch_info->exception == 1) {
3503 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3504 if (cs->singlestep_enabled) {
f2574737 3505 ret = EXCP_DEBUG;
b9bec74b 3506 }
e22a25c9 3507 } else {
b9bec74b
JK		 3508 for (n = 0; n < 4; n++) {
3509 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3510 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3511 case 0x0:
f2574737 3512 ret = EXCP_DEBUG;
e22a25c9
AL		 3513 break;
3514 case 0x1:
f2574737 3515 ret = EXCP_DEBUG;
ff4700b0 3516 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3517 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3518 hw_watchpoint.flags = BP_MEM_WRITE;
3519 break;
3520 case 0x3:
f2574737 3521 ret = EXCP_DEBUG;
ff4700b0 3522 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3523 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3524 hw_watchpoint.flags = BP_MEM_ACCESS;
3525 break;
3526 }
b9bec74b
JK		 3527 }
3528 }
e22a25c9 3529 }
ff4700b0 3530 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3531 ret = EXCP_DEBUG;
b9bec74b 3532 }
f2574737 3533 if (ret == 0) {
ff4700b0 3534 cpu_synchronize_state(cs);
48405526 3535 assert(env->exception_injected == -1);
b0b1d690 3536
f2574737 3537 /* pass to guest */
48405526
BS		 3538 env->exception_injected = arch_info->exception;
3539 env->has_error_code = 0;
b0b1d690 3540 }
e22a25c9 3541
f2574737 3542 return ret;
e22a25c9
AL		 3543}
3544
20d695a9 3545void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3546{
3547 const uint8_t type_code[] = {
3548 [GDB_BREAKPOINT_HW] = 0x0,
3549 [GDB_WATCHPOINT_WRITE] = 0x1,
3550 [GDB_WATCHPOINT_ACCESS] = 0x3
3551 };
3552 const uint8_t len_code[] = {
3553 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3554 };
3555 int n;
3556
a60f24b5 3557 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3558 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3559 }
e22a25c9
AL		 3560 if (nb_hw_breakpoint > 0) {
3561 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3562 dbg->arch.debugreg[7] = 0x0600;
3563 for (n = 0; n < nb_hw_breakpoint; n++) {
3564 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3565 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3566 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3567 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3568 }
3569 }
3570}
4513d923 3571
2a4dac83
JK		 3572static bool host_supports_vmx(void)
3573{
3574 uint32_t ecx, unused;
3575
3576 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3577 return ecx & CPUID_EXT_VMX;
3578}
3579
3580#define VMX_INVALID_GUEST_STATE 0x80000021
3581
20d695a9 3582int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3583{
20d695a9 3584 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3585 uint64_t code;
3586 int ret;
3587
3588 switch (run->exit_reason) {
3589 case KVM_EXIT_HLT:
3590 DPRINTF("handle_hlt\n");
4b8523ee 3591 qemu_mutex_lock_iothread();
839b5630 3592 ret = kvm_handle_halt(cpu);
4b8523ee 3593 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3594 break;
3595 case KVM_EXIT_SET_TPR:
3596 ret = 0;
3597 break;
d362e757 3598 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3599 qemu_mutex_lock_iothread();
f7575c96 3600 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3601 qemu_mutex_unlock_iothread();
d362e757 3602 break;
2a4dac83
JK		 3603 case KVM_EXIT_FAIL_ENTRY:
3604 code = run->fail_entry.hardware_entry_failure_reason;
3605 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3606 code);
3607 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3608 fprintf(stderr,
12619721 3609 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3610 "unrestricted mode\n"
3611 "support, the failure can be most likely due to the guest "
3612 "entering an invalid\n"
3613 "state for Intel VT. For example, the guest maybe running "
3614 "in big real mode\n"
3615 "which is not supported on less recent Intel processors."
3616 "\n\n");
3617 }
3618 ret = -1;
3619 break;
3620 case KVM_EXIT_EXCEPTION:
3621 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3622 run->ex.exception, run->ex.error_code);
3623 ret = -1;
3624 break;
f2574737
JK		 3625 case KVM_EXIT_DEBUG:
3626 DPRINTF("kvm_exit_debug\n");
4b8523ee 3627 qemu_mutex_lock_iothread();
a60f24b5 3628 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3629 qemu_mutex_unlock_iothread();
f2574737 3630 break;
50efe82c
AS		 3631 case KVM_EXIT_HYPERV:
3632 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3633 break;
15eafc2e
PB		 3634 case KVM_EXIT_IOAPIC_EOI:
3635 ioapic_eoi_broadcast(run->eoi.vector);
3636 ret = 0;
3637 break;
2a4dac83
JK		 3638 default:
3639 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3640 ret = -1;
3641 break;
3642 }
3643
3644 return ret;
3645}
3646
20d695a9 3647bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3648{
20d695a9
AF		 3649 X86CPU *cpu = X86_CPU(cs);
3650 CPUX86State *env = &cpu->env;
3651
dd1750d7 3652 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3653 return !(env->cr[0] & CR0_PE_MASK) ||
3654 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3655}
84b058d7
JK		 3656
3657void kvm_arch_init_irq_routing(KVMState *s)
3658{
3659 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3660 /* If kernel can't do irq routing, interrupt source
3661 * override 0->2 cannot be set up as required by HPET.
3662 * So we have to disable it.
3663 */
3664 no_hpet = 1;
3665 }
cc7e0ddf 3666 /* We know at this point that we're using the in-kernel
614e41bc 3667 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3668 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3669 */
614e41bc 3670 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3671 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3672
3673 if (kvm_irqchip_is_split()) {
3674 int i;
3675
3676 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3677 MSI routes for signaling interrupts to the local apics. */
3678 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3679 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3680 error_report("Could not enable split IRQ mode.");
3681 exit(1);
3682 }
3683 }
3684 }
3685}
3686
3687int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3688{
3689 int ret;
3690 if (machine_kernel_irqchip_split(ms)) {
3691 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3692 if (ret) {
df3c286c 3693 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3694 strerror(-ret));
3695 exit(1);
3696 } else {
3697 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3698 kvm_split_irqchip = true;
3699 return 1;
3700 }
3701 } else {
3702 return 0;
3703 }
84b058d7 3704}
b139bd30
JK		 3705
3706/* Classic KVM device assignment interface. Will remain x86 only. */
3707int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3708 uint32_t flags, uint32_t *dev_id)
3709{
3710 struct kvm_assigned_pci_dev dev_data = {
3711 .segnr = dev_addr->domain,
3712 .busnr = dev_addr->bus,
3713 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3714 .flags = flags,
3715 };
3716 int ret;
3717
3718 dev_data.assigned_dev_id =
3719 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3720
3721 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3722 if (ret < 0) {
3723 return ret;
3724 }
3725
3726 *dev_id = dev_data.assigned_dev_id;
3727
3728 return 0;
3729}
3730
3731int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3732{
3733 struct kvm_assigned_pci_dev dev_data = {
3734 .assigned_dev_id = dev_id,
3735 };
3736
3737 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3738}
3739
3740static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3741 uint32_t irq_type, uint32_t guest_irq)
3742{
3743 struct kvm_assigned_irq assigned_irq = {
3744 .assigned_dev_id = dev_id,
3745 .guest_irq = guest_irq,
3746 .flags = irq_type,
3747 };
3748
3749 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3750 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3751 } else {
3752 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3753 }
3754}
3755
3756int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3757 uint32_t guest_irq)
3758{
3759 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3760 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3761
3762 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3763}
3764
3765int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3766{
3767 struct kvm_assigned_pci_dev dev_data = {
3768 .assigned_dev_id = dev_id,
3769 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3770 };
3771
3772 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3773}
3774
3775static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3776 uint32_t type)
3777{
3778 struct kvm_assigned_irq assigned_irq = {
3779 .assigned_dev_id = dev_id,
3780 .flags = type,
3781 };
3782
3783 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3784}
3785
3786int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3787{
3788 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3789 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3790}
3791
3792int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3793{
3794 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3795 KVM_DEV_IRQ_GUEST_MSI, virq);
3796}
3797
3798int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3799{
3800 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3801 KVM_DEV_IRQ_HOST_MSI);
3802}
3803
3804bool kvm_device_msix_supported(KVMState *s)
3805{
3806 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3807 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3808 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3809}
3810
3811int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3812 uint32_t nr_vectors)
3813{
3814 struct kvm_assigned_msix_nr msix_nr = {
3815 .assigned_dev_id = dev_id,
3816 .entry_nr = nr_vectors,
3817 };
3818
3819 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3820}
3821
3822int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3823 int virq)
3824{
3825 struct kvm_assigned_msix_entry msix_entry = {
3826 .assigned_dev_id = dev_id,
3827 .gsi = virq,
3828 .entry = vector,
3829 };
3830
3831 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3832}
3833
3834int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3835{
3836 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3837 KVM_DEV_IRQ_GUEST_MSIX, 0);
3838}
3839
3840int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3841{
3842 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3843 KVM_DEV_IRQ_HOST_MSIX);
3844}
9e03a040
FB		 3845
3846int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3847 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3848{
8b5ed7df
PX		 3849 X86IOMMUState *iommu = x86_iommu_get_default();
3850
3851 if (iommu) {
3852 int ret;
3853 MSIMessage src, dst;
3854 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3855
0ea1472d
JK		 3856 if (!class->int_remap) {
3857 return 0;
3858 }
3859
8b5ed7df
PX		 3860 src.address = route->u.msi.address_hi;
3861 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3862 src.address |= route->u.msi.address_lo;
3863 src.data = route->u.msi.data;
3864
3865 ret = class->int_remap(iommu, &src, &dst, dev ? \
3866 pci_requester_id(dev) : \
3867 X86_IOMMU_SID_INVALID);
3868 if (ret) {
3869 trace_kvm_x86_fixup_msi_error(route->gsi);
3870 return 1;
3871 }
3872
3873 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3874 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3875 route->u.msi.data = dst.data;
3876 }
3877
9e03a040
FB		 3878 return 0;
3879}
1850b6b7 3880
38d87493
PX		 3881typedef struct MSIRouteEntry MSIRouteEntry;
3882
3883struct MSIRouteEntry {
3884 PCIDevice *dev; /* Device pointer */
3885 int vector; /* MSI/MSIX vector index */
3886 int virq; /* Virtual IRQ index */
3887 QLIST_ENTRY(MSIRouteEntry) list;
3888};
3889
3890/* List of used GSI routes */
3891static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3892 QLIST_HEAD_INITIALIZER(msi_route_list);
3893
e1d4fb2d
PX		 3894static void kvm_update_msi_routes_all(void *private, bool global,
3895 uint32_t index, uint32_t mask)
3896{
3897 int cnt = 0;
3898 MSIRouteEntry *entry;
3899 MSIMessage msg;
fd563564
PX		 3900 PCIDevice *dev;
3901
e1d4fb2d
PX		 3902 /* TODO: explicit route update */
3903 QLIST_FOREACH(entry, &msi_route_list, list) {
3904 cnt++;
fd563564
PX		 3905 dev = entry->dev;
3906 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3907 continue;
3908 }
3909 msg = pci_get_msi_message(dev, entry->vector);
3910 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3911 }
3f1fea0f 3912 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3913 trace_kvm_x86_update_msi_routes(cnt);
3914}
3915
38d87493
PX		 3916int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3917 int vector, PCIDevice *dev)
3918{
e1d4fb2d 3919 static bool notify_list_inited = false;
38d87493
PX		 3920 MSIRouteEntry *entry;
3921
3922 if (!dev) {
3923 /* These are (possibly) IOAPIC routes only used for split
3924 * kernel irqchip mode, while what we are housekeeping are
3925 * PCI devices only. */
3926 return 0;
3927 }
3928
3929 entry = g_new0(MSIRouteEntry, 1);
3930 entry->dev = dev;
3931 entry->vector = vector;
3932 entry->virq = route->gsi;
3933 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3934
3935 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3936
3937 if (!notify_list_inited) {
3938 /* For the first time we do add route, add ourselves into
3939 * IOMMU's IEC notify list if needed. */
3940 X86IOMMUState *iommu = x86_iommu_get_default();
3941 if (iommu) {
3942 x86_iommu_iec_register_notifier(iommu,
3943 kvm_update_msi_routes_all,
3944 NULL);
3945 }
3946 notify_list_inited = true;
3947 }
38d87493
PX		 3948 return 0;
3949}
3950
3951int kvm_arch_release_virq_post(int virq)
3952{
3953 MSIRouteEntry *entry, *next;
3954 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3955 if (entry->virq == virq) {
3956 trace_kvm_x86_remove_msi_route(virq);
3957 QLIST_REMOVE(entry, list);
01960e6d 3958 g_free(entry);
38d87493
PX		 3959 break;
3960 }
3961 }
9e03a040
FB		 3962 return 0;
3963}
1850b6b7
EA		 3964
3965int kvm_arch_msi_data_to_gsi(uint32_t data)
3966{
3967 abort();
3968}
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