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KVM: Introduce kvm_arch_destroy_vcpu()
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c 28#include "hyperv.h"
5e953812 29#include "hyperv-proto.h"
50efe82c 30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
a2cb15b0 42#include "hw/pci/pci.h"
15eafc2e 43#include "hw/pci/msi.h"
fd563564 44#include "hw/pci/msix.h"
795c40b8 45#include "migration/blocker.h"
4c663752 46#include "exec/memattrs.h"
8b5ed7df 47#include "trace.h"
05330448
AL		 48
49//#define DEBUG_KVM
50
51#ifdef DEBUG_KVM
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54#else
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { } while (0)
57#endif
58
1a03675d
GC		 59#define MSR_KVM_WALL_CLOCK 0x11
60#define MSR_KVM_SYSTEM_TIME 0x12
61
d1138251
EH		 62/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64#define MSR_BUF_SIZE 4096
d71b62a1 65
94a8d39a
JK		 66const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71};
25d2e361 72
c3a3a7d3
JK		 73static bool has_msr_star;
74static bool has_msr_hsave_pa;
c9b8f6b6 75static bool has_msr_tsc_aux;
f28558d3 76static bool has_msr_tsc_adjust;
aa82ba54 77static bool has_msr_tsc_deadline;
df67696e 78static bool has_msr_feature_control;
21e87c46 79static bool has_msr_misc_enable;
fc12d72e 80static bool has_msr_smbase;
79e9ebeb 81static bool has_msr_bndcfgs;
25d2e361 82static int lm_capable_kernel;
7bc3d711 83static bool has_msr_hv_hypercall;
f2a53c9e 84static bool has_msr_hv_crash;
744b8a94 85static bool has_msr_hv_reset;
8c145d7c 86static bool has_msr_hv_vpindex;
e9688fab 87static bool hv_vpindex_settable;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
aec5e9c3 97static bool has_msr_arch_capabs;
597360c0 98static bool has_msr_core_capabs;
b827df58 99
0b368a10
JD		 100static uint32_t has_architectural_pmu_version;
101static uint32_t num_architectural_pmu_gp_counters;
102static uint32_t num_architectural_pmu_fixed_counters;
0d894367 103
28143b40
TH		 104static int has_xsave;
105static int has_xcrs;
106static int has_pit_state2;
107
87f8b626
AR		 108static bool has_msr_mcg_ext_ctl;
109
494e95e9 110static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 111static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 112
28143b40
TH		 113int kvm_has_pit_state2(void)
114{
115 return has_pit_state2;
116}
117
355023f2
PB		 118bool kvm_has_smm(void)
119{
120 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
121}
122
6053a86f
MT		 123bool kvm_has_adjust_clock_stable(void)
124{
125 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
126
127 return (ret == KVM_CLOCK_TSC_STABLE);
128}
129
1d31f66b
PM		 130bool kvm_allows_irq0_override(void)
131{
132 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
133}
134
fb506e70
RK		 135static bool kvm_x2apic_api_set_flags(uint64_t flags)
136{
137 KVMState *s = KVM_STATE(current_machine->accelerator);
138
139 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
140}
141
e391c009 142#define MEMORIZE(fn, _result) \
2a138ec3 143 ({ \
2a138ec3
RK		 144 static bool _memorized; \
145 \
146 if (_memorized) { \
147 return _result; \
148 } \
149 _memorized = true; \
150 _result = fn; \
151 })
152
e391c009
IM		 153static bool has_x2apic_api;
154
155bool kvm_has_x2apic_api(void)
156{
157 return has_x2apic_api;
158}
159
fb506e70
RK		 160bool kvm_enable_x2apic(void)
161{
2a138ec3
RK		 162 return MEMORIZE(
163 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 164 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
165 has_x2apic_api);
fb506e70
RK		 166}
167
e9688fab
RK		 168bool kvm_hv_vpindex_settable(void)
169{
170 return hv_vpindex_settable;
171}
172
0fd7e098
LL		 173static int kvm_get_tsc(CPUState *cs)
174{
175 X86CPU *cpu = X86_CPU(cs);
176 CPUX86State *env = &cpu->env;
177 struct {
178 struct kvm_msrs info;
179 struct kvm_msr_entry entries[1];
180 } msr_data;
181 int ret;
182
183 if (env->tsc_valid) {
184 return 0;
185 }
186
187 msr_data.info.nmsrs = 1;
188 msr_data.entries[0].index = MSR_IA32_TSC;
189 env->tsc_valid = !runstate_is_running();
190
191 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
192 if (ret < 0) {
193 return ret;
194 }
195
48e1a45c 196 assert(ret == 1);
0fd7e098
LL		 197 env->tsc = msr_data.entries[0].data;
198 return 0;
199}
200
14e6fe12 201static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 202{
0fd7e098
LL		 203 kvm_get_tsc(cpu);
204}
205
206void kvm_synchronize_all_tsc(void)
207{
208 CPUState *cpu;
209
210 if (kvm_enabled()) {
211 CPU_FOREACH(cpu) {
14e6fe12 212 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 213 }
214 }
215}
216
b827df58
AK		 217static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
218{
219 struct kvm_cpuid2 *cpuid;
220 int r, size;
221
222 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 223 cpuid = g_malloc0(size);
b827df58
AK		 224 cpuid->nent = max;
225 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 226 if (r == 0 && cpuid->nent >= max) {
227 r = -E2BIG;
228 }
b827df58
AK		 229 if (r < 0) {
230 if (r == -E2BIG) {
7267c094 231 g_free(cpuid);
b827df58
AK		 232 return NULL;
233 } else {
234 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
235 strerror(-r));
236 exit(1);
237 }
238 }
239 return cpuid;
240}
241
dd87f8a6
EH		 242/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
243 * for all entries.
244 */
245static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
246{
247 struct kvm_cpuid2 *cpuid;
248 int max = 1;
494e95e9
CP		 249
250 if (cpuid_cache != NULL) {
251 return cpuid_cache;
252 }
dd87f8a6
EH		 253 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
254 max *= 2;
255 }
494e95e9 256 cpuid_cache = cpuid;
dd87f8a6
EH		 257 return cpuid;
258}
259
a443bc34 260static const struct kvm_para_features {
0c31b744
GC		 261 int cap;
262 int feature;
263} para_features[] = {
264 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
265 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
266 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 267 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 268};
269
ba9bc59e 270static int get_para_features(KVMState *s)
0c31b744
GC		 271{
272 int i, features = 0;
273
8e03c100 274 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 275 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 276 features |= (1 << para_features[i].feature);
277 }
278 }
279
280 return features;
281}
0c31b744 282
40e80ee4
EH		 283static bool host_tsx_blacklisted(void)
284{
285 int family, model, stepping;\
286 char vendor[CPUID_VENDOR_SZ + 1];
287
288 host_vendor_fms(vendor, &family, &model, &stepping);
289
290 /* Check if we are running on a Haswell host known to have broken TSX */
291 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
292 (family == 6) &&
293 ((model == 63 && stepping < 4) ||
294 model == 60 || model == 69 || model == 70);
295}
0c31b744 296
829ae2f9
EH		 297/* Returns the value for a specific register on the cpuid entry
298 */
299static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
300{
301 uint32_t ret = 0;
302 switch (reg) {
303 case R_EAX:
304 ret = entry->eax;
305 break;
306 case R_EBX:
307 ret = entry->ebx;
308 break;
309 case R_ECX:
310 ret = entry->ecx;
311 break;
312 case R_EDX:
313 ret = entry->edx;
314 break;
315 }
316 return ret;
317}
318
4fb73f1d
EH		 319/* Find matching entry for function/index on kvm_cpuid2 struct
320 */
321static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
322 uint32_t function,
323 uint32_t index)
324{
325 int i;
326 for (i = 0; i < cpuid->nent; ++i) {
327 if (cpuid->entries[i].function == function &&
328 cpuid->entries[i].index == index) {
329 return &cpuid->entries[i];
330 }
331 }
332 /* not found: */
333 return NULL;
334}
335
ba9bc59e 336uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 337 uint32_t index, int reg)
b827df58
AK		 338{
339 struct kvm_cpuid2 *cpuid;
b827df58
AK		 340 uint32_t ret = 0;
341 uint32_t cpuid_1_edx;
8c723b79 342 bool found = false;
b827df58 343
dd87f8a6 344 cpuid = get_supported_cpuid(s);
b827df58 345
4fb73f1d
EH		 346 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
347 if (entry) {
348 found = true;
349 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 350 }
351
7b46e5ce
EH		 352 /* Fixups for the data returned by KVM, below */
353
c2acb022
EH		 354 if (function == 1 && reg == R_EDX) {
355 /* KVM before 2.6.30 misreports the following features */
356 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 357 } else if (function == 1 && reg == R_ECX) {
358 /* We can set the hypervisor flag, even if KVM does not return it on
359 * GET_SUPPORTED_CPUID
360 */
361 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 362 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
363 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
364 * and the irqchip is in the kernel.
365 */
366 if (kvm_irqchip_in_kernel() &&
367 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
368 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
369 }
41e5e76d
EH		 370
371 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
372 * without the in-kernel irqchip
373 */
374 if (!kvm_irqchip_in_kernel()) {
375 ret &= ~CPUID_EXT_X2APIC;
b827df58 376 }
2266d443
MT		 377
378 if (enable_cpu_pm) {
379 int disable_exits = kvm_check_extension(s,
380 KVM_CAP_X86_DISABLE_EXITS);
381
382 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
383 ret |= CPUID_EXT_MONITOR;
384 }
385 }
28b8e4d0
JK		 386 } else if (function == 6 && reg == R_EAX) {
387 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 388 } else if (function == 7 && index == 0 && reg == R_EBX) {
389 if (host_tsx_blacklisted()) {
390 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
391 }
485b1d25
EH		 392 } else if (function == 7 && index == 0 && reg == R_EDX) {
393 /*
394 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
395 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
396 * returned by KVM_GET_MSR_INDEX_LIST.
397 */
398 if (!has_msr_arch_capabs) {
399 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
400 }
f98bbd83
BM		 401 } else if (function == 0x80000001 && reg == R_ECX) {
402 /*
403 * It's safe to enable TOPOEXT even if it's not returned by
404 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
405 * us to keep CPU models including TOPOEXT runnable on older kernels.
406 */
407 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 408 } else if (function == 0x80000001 && reg == R_EDX) {
409 /* On Intel, kvm returns cpuid according to the Intel spec,
410 * so add missing bits according to the AMD spec:
411 */
412 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
413 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 414 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
415 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
416 * be enabled without the in-kernel irqchip
417 */
418 if (!kvm_irqchip_in_kernel()) {
419 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
420 }
be777326 421 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 422 ret |= 1U << KVM_HINTS_REALTIME;
be777326 423 found = 1;
b827df58
AK		 424 }
425
0c31b744 426 /* fallback for older kernels */
8c723b79 427 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 428 ret = get_para_features(s);
b9bec74b 429 }
0c31b744
GC		 430
431 return ret;
bb0300dc 432}
bb0300dc 433
f57bceb6
RH		 434uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
435{
436 struct {
437 struct kvm_msrs info;
438 struct kvm_msr_entry entries[1];
439 } msr_data;
440 uint32_t ret;
441
442 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
443 return 0;
444 }
445
446 /* Check if requested MSR is supported feature MSR */
447 int i;
448 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
449 if (kvm_feature_msrs->indices[i] == index) {
450 break;
451 }
452 if (i == kvm_feature_msrs->nmsrs) {
453 return 0; /* if the feature MSR is not supported, simply return 0 */
454 }
455
456 msr_data.info.nmsrs = 1;
457 msr_data.entries[0].index = index;
458
459 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
460 if (ret != 1) {
461 error_report("KVM get MSR (index=0x%x) feature failed, %s",
462 index, strerror(-ret));
463 exit(1);
464 }
465
466 return msr_data.entries[0].data;
467}
468
469
3c85e74f
HY		 470typedef struct HWPoisonPage {
471 ram_addr_t ram_addr;
472 QLIST_ENTRY(HWPoisonPage) list;
473} HWPoisonPage;
474
475static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
476 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
477
478static void kvm_unpoison_all(void *param)
479{
480 HWPoisonPage *page, *next_page;
481
482 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
483 QLIST_REMOVE(page, list);
484 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 485 g_free(page);
3c85e74f
HY		 486 }
487}
488
3c85e74f
HY		 489static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
490{
491 HWPoisonPage *page;
492
493 QLIST_FOREACH(page, &hwpoison_page_list, list) {
494 if (page->ram_addr == ram_addr) {
495 return;
496 }
497 }
ab3ad07f 498 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 499 page->ram_addr = ram_addr;
500 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
501}
502
e7701825
MT		 503static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
504 int *max_banks)
505{
506 int r;
507
14a09518 508 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 509 if (r > 0) {
510 *max_banks = r;
511 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
512 }
513 return -ENOSYS;
514}
515
bee615d4 516static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 517{
87f8b626 518 CPUState *cs = CPU(cpu);
bee615d4 519 CPUX86State *env = &cpu->env;
c34d440a
JK		 520 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
521 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
522 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 523 int flags = 0;
e7701825 524
c34d440a
JK		 525 if (code == BUS_MCEERR_AR) {
526 status |= MCI_STATUS_AR | 0x134;
527 mcg_status |= MCG_STATUS_EIPV;
528 } else {
529 status |= 0xc0;
530 mcg_status |= MCG_STATUS_RIPV;
419fb20a 531 }
87f8b626
AR		 532
533 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
534 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
535 * guest kernel back into env->mcg_ext_ctl.
536 */
537 cpu_synchronize_state(cs);
538 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
539 mcg_status |= MCG_STATUS_LMCE;
540 flags = 0;
541 }
542
8c5cf3b6 543 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 544 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 545}
419fb20a
JK		 546
547static void hardware_memory_error(void)
548{
549 fprintf(stderr, "Hardware memory error!\n");
550 exit(1);
551}
552
2ae41db2 553void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 554{
20d695a9
AF		 555 X86CPU *cpu = X86_CPU(c);
556 CPUX86State *env = &cpu->env;
419fb20a 557 ram_addr_t ram_addr;
a8170e5e 558 hwaddr paddr;
419fb20a 559
4d39892c
PB		 560 /* If we get an action required MCE, it has been injected by KVM
561 * while the VM was running. An action optional MCE instead should
562 * be coming from the main thread, which qemu_init_sigbus identifies
563 * as the "early kill" thread.
564 */
a16fc07e 565 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 566
20e0ff59 567 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 568 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 569 if (ram_addr != RAM_ADDR_INVALID &&
570 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
571 kvm_hwpoison_page_add(ram_addr);
572 kvm_mce_inject(cpu, paddr, code);
2ae41db2 573 return;
419fb20a 574 }
20e0ff59
PB		 575
576 fprintf(stderr, "Hardware memory error for memory used by "
577 "QEMU itself instead of guest system!\n");
419fb20a 578 }
20e0ff59
PB		 579
580 if (code == BUS_MCEERR_AR) {
581 hardware_memory_error();
582 }
583
584 /* Hope we are lucky for AO MCE */
419fb20a
JK		 585}
586
1bc22652 587static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 588{
1bc22652
AF		 589 CPUX86State *env = &cpu->env;
590
ab443475
JK		 591 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
592 unsigned int bank, bank_num = env->mcg_cap & 0xff;
593 struct kvm_x86_mce mce;
594
595 env->exception_injected = -1;
596
597 /*
598 * There must be at least one bank in use if an MCE is pending.
599 * Find it and use its values for the event injection.
600 */
601 for (bank = 0; bank < bank_num; bank++) {
602 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
603 break;
604 }
605 }
606 assert(bank < bank_num);
607
608 mce.bank = bank;
609 mce.status = env->mce_banks[bank * 4 + 1];
610 mce.mcg_status = env->mcg_status;
611 mce.addr = env->mce_banks[bank * 4 + 2];
612 mce.misc = env->mce_banks[bank * 4 + 3];
613
1bc22652 614 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 615 }
ab443475
JK		 616 return 0;
617}
618
1dfb4dd9 619static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 620{
317ac620 621 CPUX86State *env = opaque;
b8cc45d6
GC		 622
623 if (running) {
624 env->tsc_valid = false;
625 }
626}
627
83b17af5 628unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 629{
83b17af5 630 X86CPU *cpu = X86_CPU(cs);
7e72a45c 631 return cpu->apic_id;
b164e48e
EH		 632}
633
92067bf4
IM		 634#ifndef KVM_CPUID_SIGNATURE_NEXT
635#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
636#endif
637
92067bf4
IM		 638static bool hyperv_enabled(X86CPU *cpu)
639{
7bc3d711
PB		 640 CPUState *cs = CPU(cpu);
641 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c 642 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
e48ddcc6 643 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 644}
645
5031283d
HZ		 646static int kvm_arch_set_tsc_khz(CPUState *cs)
647{
648 X86CPU *cpu = X86_CPU(cs);
649 CPUX86State *env = &cpu->env;
650 int r;
651
652 if (!env->tsc_khz) {
653 return 0;
654 }
655
656 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
657 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
658 -ENOTSUP;
659 if (r < 0) {
660 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
661 * TSC frequency doesn't match the one we want.
662 */
663 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
664 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
665 -ENOTSUP;
666 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 667 warn_report("TSC frequency mismatch between "
668 "VM (%" PRId64 " kHz) and host (%d kHz), "
669 "and TSC scaling unavailable",
670 env->tsc_khz, cur_freq);
5031283d
HZ		 671 return r;
672 }
673 }
674
675 return 0;
676}
677
4bb95b82
LP		 678static bool tsc_is_stable_and_known(CPUX86State *env)
679{
680 if (!env->tsc_khz) {
681 return false;
682 }
683 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
684 || env->user_tsc_khz;
685}
686
6760bd20
VK		 687static struct {
688 const char *desc;
689 struct {
690 uint32_t fw;
691 uint32_t bits;
692 } flags[2];
c6861930 693 uint64_t dependencies;
6760bd20
VK		 694} kvm_hyperv_properties[] = {
695 [HYPERV_FEAT_RELAXED] = {
696 .desc = "relaxed timing (hv-relaxed)",
697 .flags = {
698 {.fw = FEAT_HYPERV_EAX,
699 .bits = HV_HYPERCALL_AVAILABLE},
700 {.fw = FEAT_HV_RECOMM_EAX,
701 .bits = HV_RELAXED_TIMING_RECOMMENDED}
702 }
703 },
704 [HYPERV_FEAT_VAPIC] = {
705 .desc = "virtual APIC (hv-vapic)",
706 .flags = {
707 {.fw = FEAT_HYPERV_EAX,
708 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
709 {.fw = FEAT_HV_RECOMM_EAX,
710 .bits = HV_APIC_ACCESS_RECOMMENDED}
711 }
712 },
713 [HYPERV_FEAT_TIME] = {
714 .desc = "clocksources (hv-time)",
715 .flags = {
716 {.fw = FEAT_HYPERV_EAX,
717 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
718 HV_REFERENCE_TSC_AVAILABLE}
719 }
720 },
721 [HYPERV_FEAT_CRASH] = {
722 .desc = "crash MSRs (hv-crash)",
723 .flags = {
724 {.fw = FEAT_HYPERV_EDX,
725 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
726 }
727 },
728 [HYPERV_FEAT_RESET] = {
729 .desc = "reset MSR (hv-reset)",
730 .flags = {
731 {.fw = FEAT_HYPERV_EAX,
732 .bits = HV_RESET_AVAILABLE}
733 }
734 },
735 [HYPERV_FEAT_VPINDEX] = {
736 .desc = "VP_INDEX MSR (hv-vpindex)",
737 .flags = {
738 {.fw = FEAT_HYPERV_EAX,
739 .bits = HV_VP_INDEX_AVAILABLE}
740 }
741 },
742 [HYPERV_FEAT_RUNTIME] = {
743 .desc = "VP_RUNTIME MSR (hv-runtime)",
744 .flags = {
745 {.fw = FEAT_HYPERV_EAX,
746 .bits = HV_VP_RUNTIME_AVAILABLE}
747 }
748 },
749 [HYPERV_FEAT_SYNIC] = {
750 .desc = "synthetic interrupt controller (hv-synic)",
751 .flags = {
752 {.fw = FEAT_HYPERV_EAX,
753 .bits = HV_SYNIC_AVAILABLE}
754 }
755 },
756 [HYPERV_FEAT_STIMER] = {
757 .desc = "synthetic timers (hv-stimer)",
758 .flags = {
759 {.fw = FEAT_HYPERV_EAX,
760 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 761 },
762 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 763 },
764 [HYPERV_FEAT_FREQUENCIES] = {
765 .desc = "frequency MSRs (hv-frequencies)",
766 .flags = {
767 {.fw = FEAT_HYPERV_EAX,
768 .bits = HV_ACCESS_FREQUENCY_MSRS},
769 {.fw = FEAT_HYPERV_EDX,
770 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
771 }
772 },
773 [HYPERV_FEAT_REENLIGHTENMENT] = {
774 .desc = "reenlightenment MSRs (hv-reenlightenment)",
775 .flags = {
776 {.fw = FEAT_HYPERV_EAX,
777 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
778 }
779 },
780 [HYPERV_FEAT_TLBFLUSH] = {
781 .desc = "paravirtualized TLB flush (hv-tlbflush)",
782 .flags = {
783 {.fw = FEAT_HV_RECOMM_EAX,
784 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
785 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 786 },
787 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 788 },
789 [HYPERV_FEAT_EVMCS] = {
790 .desc = "enlightened VMCS (hv-evmcs)",
791 .flags = {
792 {.fw = FEAT_HV_RECOMM_EAX,
793 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 794 },
795 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 796 },
797 [HYPERV_FEAT_IPI] = {
798 .desc = "paravirtualized IPI (hv-ipi)",
799 .flags = {
800 {.fw = FEAT_HV_RECOMM_EAX,
801 .bits = HV_CLUSTER_IPI_RECOMMENDED |
802 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 803 },
804 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 805 },
128531d9
VK		 806 [HYPERV_FEAT_STIMER_DIRECT] = {
807 .desc = "direct mode synthetic timers (hv-stimer-direct)",
808 .flags = {
809 {.fw = FEAT_HYPERV_EDX,
810 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
811 },
812 .dependencies = BIT(HYPERV_FEAT_STIMER)
813 },
6760bd20
VK		 814};
815
816static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
817{
818 struct kvm_cpuid2 *cpuid;
819 int r, size;
820
821 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
822 cpuid = g_malloc0(size);
823 cpuid->nent = max;
824
825 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
826 if (r == 0 && cpuid->nent >= max) {
827 r = -E2BIG;
828 }
829 if (r < 0) {
830 if (r == -E2BIG) {
831 g_free(cpuid);
832 return NULL;
833 } else {
834 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
835 strerror(-r));
836 exit(1);
837 }
838 }
839 return cpuid;
840}
841
842/*
843 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
844 * for all entries.
845 */
846static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
847{
848 struct kvm_cpuid2 *cpuid;
849 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
850
851 /*
852 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
853 * -E2BIG, however, it doesn't report back the right size. Keep increasing
854 * it and re-trying until we succeed.
855 */
856 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
857 max++;
858 }
859 return cpuid;
860}
861
862/*
863 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
864 * leaves from KVM_CAP_HYPERV* and present MSRs data.
865 */
866static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 867{
868 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 869 struct kvm_cpuid2 *cpuid;
870 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
871
872 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
873 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
874 cpuid->nent = 2;
875
876 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
877 entry_feat = &cpuid->entries[0];
878 entry_feat->function = HV_CPUID_FEATURES;
879
880 entry_recomm = &cpuid->entries[1];
881 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
882 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
883
884 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
885 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
886 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
887 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
888 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
889 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
890 }
c35bd19a 891
6760bd20
VK		 892 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
893 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
894 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 895 }
6760bd20
VK		 896
897 if (has_msr_hv_frequencies) {
898 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
899 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 900 }
6760bd20
VK		 901
902 if (has_msr_hv_crash) {
903 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 904 }
6760bd20
VK		 905
906 if (has_msr_hv_reenlightenment) {
907 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 908 }
6760bd20
VK		 909
910 if (has_msr_hv_reset) {
911 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 912 }
6760bd20
VK		 913
914 if (has_msr_hv_vpindex) {
915 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 916 }
6760bd20
VK		 917
918 if (has_msr_hv_runtime) {
919 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 920 }
6760bd20
VK		 921
922 if (has_msr_hv_synic) {
923 unsigned int cap = cpu->hyperv_synic_kvm_only ?
924 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
925
926 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
927 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 928 }
c35bd19a 929 }
6760bd20
VK		 930
931 if (has_msr_hv_stimer) {
932 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 933 }
9b4cf107 934
6760bd20
VK		 935 if (kvm_check_extension(cs->kvm_state,
936 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
937 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
938 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
939 }
c35bd19a 940
6760bd20
VK		 941 if (kvm_check_extension(cs->kvm_state,
942 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
943 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 944 }
6760bd20
VK		 945
946 if (kvm_check_extension(cs->kvm_state,
947 KVM_CAP_HYPERV_SEND_IPI) > 0) {
948 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
949 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 950 }
6760bd20
VK		 951
952 return cpuid;
953}
954
955static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
956{
957 struct kvm_cpuid_entry2 *entry;
958 uint32_t func;
959 int reg;
960
961 switch (fw) {
962 case FEAT_HYPERV_EAX:
963 reg = R_EAX;
964 func = HV_CPUID_FEATURES;
965 break;
966 case FEAT_HYPERV_EDX:
967 reg = R_EDX;
968 func = HV_CPUID_FEATURES;
969 break;
970 case FEAT_HV_RECOMM_EAX:
971 reg = R_EAX;
972 func = HV_CPUID_ENLIGHTMENT_INFO;
973 break;
974 default:
975 return -EINVAL;
a2b107db 976 }
6760bd20
VK		 977
978 entry = cpuid_find_entry(cpuid, func, 0);
979 if (!entry) {
980 return -ENOENT;
a2b107db 981 }
6760bd20
VK		 982
983 switch (reg) {
984 case R_EAX:
985 *r = entry->eax;
986 break;
987 case R_EDX:
988 *r = entry->edx;
989 break;
990 default:
991 return -EINVAL;
a2b107db 992 }
6760bd20
VK		 993
994 return 0;
995}
996
997static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
998 int feature)
999{
1000 X86CPU *cpu = X86_CPU(cs);
1001 CPUX86State *env = &cpu->env;
e48ddcc6 1002 uint32_t r, fw, bits;
c6861930
VK		 1003 uint64_t deps;
1004 int i, dep_feat = 0;
6760bd20 1005
e48ddcc6 1006 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1007 return 0;
1008 }
1009
c6861930
VK		 1010 deps = kvm_hyperv_properties[feature].dependencies;
1011 while ((dep_feat = find_next_bit(&deps, 64, dep_feat)) < 64) {
1012 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1013 fprintf(stderr,
1014 "Hyper-V %s requires Hyper-V %s\n",
1015 kvm_hyperv_properties[feature].desc,
1016 kvm_hyperv_properties[dep_feat].desc);
1017 return 1;
1018 }
1019 dep_feat++;
1020 }
1021
6760bd20
VK		 1022 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1023 fw = kvm_hyperv_properties[feature].flags[i].fw;
1024 bits = kvm_hyperv_properties[feature].flags[i].bits;
1025
1026 if (!fw) {
1027 continue;
a2b107db 1028 }
6760bd20
VK		 1029
1030 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
e48ddcc6
VK		 1031 if (hyperv_feat_enabled(cpu, feature)) {
1032 fprintf(stderr,
1033 "Hyper-V %s is not supported by kernel\n",
1034 kvm_hyperv_properties[feature].desc);
1035 return 1;
1036 } else {
1037 return 0;
1038 }
6760bd20
VK		 1039 }
1040
1041 env->features[fw] |= bits;
a2b107db 1042 }
6760bd20 1043
e48ddcc6
VK		 1044 if (cpu->hyperv_passthrough) {
1045 cpu->hyperv_features |= BIT(feature);
1046 }
1047
6760bd20
VK		 1048 return 0;
1049}
1050
2344d22e
VK		 1051/*
1052 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1053 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1054 * extentions are enabled.
1055 */
1056static int hyperv_handle_properties(CPUState *cs,
1057 struct kvm_cpuid_entry2 *cpuid_ent)
6760bd20
VK		 1058{
1059 X86CPU *cpu = X86_CPU(cs);
1060 CPUX86State *env = &cpu->env;
1061 struct kvm_cpuid2 *cpuid;
2344d22e
VK		 1062 struct kvm_cpuid_entry2 *c;
1063 uint32_t signature[3];
1064 uint32_t cpuid_i = 0;
e48ddcc6 1065 int r;
6760bd20 1066
2344d22e
VK		 1067 if (!hyperv_enabled(cpu))
1068 return 0;
1069
e48ddcc6
VK		 1070 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1071 cpu->hyperv_passthrough) {
a2b107db
VK		 1072 uint16_t evmcs_version;
1073
e48ddcc6
VK		 1074 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1075 (uintptr_t)&evmcs_version);
1076
1077 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1078 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1079 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1080 return -ENOSYS;
1081 }
e48ddcc6
VK		 1082
1083 if (!r) {
1084 env->features[FEAT_HV_RECOMM_EAX] |=
1085 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1086 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1087 }
a2b107db
VK		 1088 }
1089
6760bd20
VK		 1090 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1091 cpuid = get_supported_hv_cpuid(cs);
1092 } else {
1093 cpuid = get_supported_hv_cpuid_legacy(cs);
1094 }
1095
e48ddcc6
VK		 1096 if (cpu->hyperv_passthrough) {
1097 memcpy(cpuid_ent, &cpuid->entries[0],
1098 cpuid->nent * sizeof(cpuid->entries[0]));
1099
1100 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1101 if (c) {
1102 env->features[FEAT_HYPERV_EAX] = c->eax;
1103 env->features[FEAT_HYPERV_EBX] = c->ebx;
1104 env->features[FEAT_HYPERV_EDX] = c->eax;
1105 }
1106 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1107 if (c) {
1108 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1109
1110 /* hv-spinlocks may have been overriden */
1111 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1112 c->ebx = cpu->hyperv_spinlock_attempts;
1113 }
1114 }
1115 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1116 if (c) {
1117 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1118 }
1119 }
1120
6760bd20 1121 /* Features */
e48ddcc6 1122 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
6760bd20
VK		 1123 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1124 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1125 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1126 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1127 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1128 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1129 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1130 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1131 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1132 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1133 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1134 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1135 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
128531d9 1136 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
6760bd20 1137
c6861930 1138 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1139 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1140 !cpu->hyperv_synic_kvm_only &&
1141 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1142 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1143 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1144 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1145 r |= 1;
1146 }
1147
1148 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1149 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1150
2344d22e
VK		 1151 if (r) {
1152 r = -ENOSYS;
1153 goto free;
1154 }
1155
e48ddcc6
VK		 1156 if (cpu->hyperv_passthrough) {
1157 /* We already copied all feature words from KVM as is */
1158 r = cpuid->nent;
1159 goto free;
1160 }
1161
2344d22e
VK		 1162 c = &cpuid_ent[cpuid_i++];
1163 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1164 if (!cpu->hyperv_vendor_id) {
1165 memcpy(signature, "Microsoft Hv", 12);
1166 } else {
1167 size_t len = strlen(cpu->hyperv_vendor_id);
1168
1169 if (len > 12) {
1170 error_report("hv-vendor-id truncated to 12 characters");
1171 len = 12;
1172 }
1173 memset(signature, 0, 12);
1174 memcpy(signature, cpu->hyperv_vendor_id, len);
1175 }
1176 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1177 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1178 c->ebx = signature[0];
1179 c->ecx = signature[1];
1180 c->edx = signature[2];
1181
1182 c = &cpuid_ent[cpuid_i++];
1183 c->function = HV_CPUID_INTERFACE;
1184 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1185 c->eax = signature[0];
1186 c->ebx = 0;
1187 c->ecx = 0;
1188 c->edx = 0;
1189
1190 c = &cpuid_ent[cpuid_i++];
1191 c->function = HV_CPUID_VERSION;
1192 c->eax = 0x00001bbc;
1193 c->ebx = 0x00060001;
1194
1195 c = &cpuid_ent[cpuid_i++];
1196 c->function = HV_CPUID_FEATURES;
1197 c->eax = env->features[FEAT_HYPERV_EAX];
1198 c->ebx = env->features[FEAT_HYPERV_EBX];
1199 c->edx = env->features[FEAT_HYPERV_EDX];
1200
1201 c = &cpuid_ent[cpuid_i++];
1202 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1203 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1204 c->ebx = cpu->hyperv_spinlock_attempts;
1205
1206 c = &cpuid_ent[cpuid_i++];
1207 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1208 c->eax = cpu->hv_max_vps;
1209 c->ebx = 0x40;
1210
1211 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1212 __u32 function;
1213
1214 /* Create zeroed 0x40000006..0x40000009 leaves */
1215 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1216 function < HV_CPUID_NESTED_FEATURES; function++) {
1217 c = &cpuid_ent[cpuid_i++];
1218 c->function = function;
1219 }
1220
1221 c = &cpuid_ent[cpuid_i++];
1222 c->function = HV_CPUID_NESTED_FEATURES;
1223 c->eax = env->features[FEAT_HV_NESTED_EAX];
1224 }
1225 r = cpuid_i;
1226
1227free:
6760bd20
VK		 1228 g_free(cpuid);
1229
2344d22e 1230 return r;
c35bd19a
EY		 1231}
1232
e48ddcc6
VK		 1233static Error *hv_passthrough_mig_blocker;
1234
e9688fab
RK		 1235static int hyperv_init_vcpu(X86CPU *cpu)
1236{
729ce7e1 1237 CPUState *cs = CPU(cpu);
e48ddcc6 1238 Error *local_err = NULL;
729ce7e1
RK		 1239 int ret;
1240
e48ddcc6
VK		 1241 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1242 error_setg(&hv_passthrough_mig_blocker,
1243 "'hv-passthrough' CPU flag prevents migration, use explicit"
1244 " set of hv-* flags instead");
1245 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1246 if (local_err) {
1247 error_report_err(local_err);
1248 error_free(hv_passthrough_mig_blocker);
1249 return ret;
1250 }
1251 }
1252
2d384d7c 1253 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1254 /*
1255 * the kernel doesn't support setting vp_index; assert that its value
1256 * is in sync
1257 */
e9688fab
RK		 1258 struct {
1259 struct kvm_msrs info;
1260 struct kvm_msr_entry entries[1];
1261 } msr_data = {
1262 .info.nmsrs = 1,
1263 .entries[0].index = HV_X64_MSR_VP_INDEX,
1264 };
1265
729ce7e1 1266 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1267 if (ret < 0) {
1268 return ret;
1269 }
1270 assert(ret == 1);
1271
701189e3 1272 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1273 error_report("kernel's vp_index != QEMU's vp_index");
1274 return -ENXIO;
1275 }
1276 }
1277
2d384d7c 1278 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1279 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1280 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1281 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1282 if (ret < 0) {
1283 error_report("failed to turn on HyperV SynIC in KVM: %s",
1284 strerror(-ret));
1285 return ret;
1286 }
606c34bf 1287
9b4cf107
RK		 1288 if (!cpu->hyperv_synic_kvm_only) {
1289 ret = hyperv_x86_synic_add(cpu);
1290 if (ret < 0) {
1291 error_report("failed to create HyperV SynIC: %s",
1292 strerror(-ret));
1293 return ret;
1294 }
606c34bf 1295 }
729ce7e1
RK		 1296 }
1297
e9688fab
RK		 1298 return 0;
1299}
1300
68bfd0ad 1301static Error *invtsc_mig_blocker;
d98f2607 1302static Error *vmx_mig_blocker;
68bfd0ad 1303
f8bb0565 1304#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1305
20d695a9 1306int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1307{
1308 struct {
486bd5a2 1309 struct kvm_cpuid2 cpuid;
f8bb0565 1310 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1311 } cpuid_data;
1312 /*
1313 * The kernel defines these structs with padding fields so there
1314 * should be no extra padding in our cpuid_data struct.
1315 */
1316 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1317 sizeof(struct kvm_cpuid2) +
1318 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1319
20d695a9
AF		 1320 X86CPU *cpu = X86_CPU(cs);
1321 CPUX86State *env = &cpu->env;
486bd5a2 1322 uint32_t limit, i, j, cpuid_i;
a33609ca 1323 uint32_t unused;
bb0300dc 1324 struct kvm_cpuid_entry2 *c;
bb0300dc 1325 uint32_t signature[3];
234cc647 1326 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 1327 int r;
fe44dc91 1328 Error *local_err = NULL;
05330448 1329
ef4cbe14
SW		 1330 memset(&cpuid_data, 0, sizeof(cpuid_data));
1331
05330448
AL		 1332 cpuid_i = 0;
1333
ddb98b5a
LP		 1334 r = kvm_arch_set_tsc_khz(cs);
1335 if (r < 0) {
6b2341ee 1336 return r;
ddb98b5a
LP		 1337 }
1338
1339 /* vcpu's TSC frequency is either specified by user, or following
1340 * the value used by KVM if the former is not present. In the
1341 * latter case, we query it from KVM and record in env->tsc_khz,
1342 * so that vcpu's TSC frequency can be migrated later via this field.
1343 */
1344 if (!env->tsc_khz) {
1345 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1346 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1347 -ENOTSUP;
1348 if (r > 0) {
1349 env->tsc_khz = r;
1350 }
1351 }
1352
bb0300dc 1353 /* Paravirtualization CPUIDs */
2344d22e
VK		 1354 r = hyperv_handle_properties(cs, cpuid_data.entries);
1355 if (r < 0) {
1356 return r;
1357 } else if (r > 0) {
1358 cpuid_i = r;
234cc647 1359 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1360 has_msr_hv_hypercall = true;
eab70139
VR		 1361 }
1362
f522d2ac
AW		 1363 if (cpu->expose_kvm) {
1364 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1365 c = &cpuid_data.entries[cpuid_i++];
1366 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1367 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1368 c->ebx = signature[0];
1369 c->ecx = signature[1];
1370 c->edx = signature[2];
234cc647 1371
f522d2ac
AW		 1372 c = &cpuid_data.entries[cpuid_i++];
1373 c->function = KVM_CPUID_FEATURES | kvm_base;
1374 c->eax = env->features[FEAT_KVM];
be777326 1375 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1376 }
917367aa 1377
a33609ca 1378 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1379
1380 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1381 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1382 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1383 abort();
1384 }
bb0300dc 1385 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1386
1387 switch (i) {
a36b1029
AL		 1388 case 2: {
1389 /* Keep reading function 2 till all the input is received */
1390 int times;
1391
a36b1029 1392 c->function = i;
a33609ca
AL		 1393 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1394 KVM_CPUID_FLAG_STATE_READ_NEXT;
1395 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1396 times = c->eax & 0xff;
a36b1029
AL		 1397
1398 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1399 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1400 fprintf(stderr, "cpuid_data is full, no space for "
1401 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1402 abort();
1403 }
a33609ca 1404 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1405 c->function = i;
a33609ca
AL		 1406 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1407 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1408 }
1409 break;
1410 }
486bd5a2
AL		 1411 case 4:
1412 case 0xb:
1413 case 0xd:
1414 for (j = 0; ; j++) {
31e8c696
AP		 1415 if (i == 0xd && j == 64) {
1416 break;
1417 }
486bd5a2
AL		 1418 c->function = i;
1419 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1420 c->index = j;
a33609ca 1421 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1422
b9bec74b 1423 if (i == 4 && c->eax == 0) {
486bd5a2 1424 break;
b9bec74b
JK		 1425 }
1426 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1427 break;
b9bec74b
JK		 1428 }
1429 if (i == 0xd && c->eax == 0) {
31e8c696 1430 continue;
b9bec74b 1431 }
f8bb0565
IM		 1432 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1433 fprintf(stderr, "cpuid_data is full, no space for "
1434 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1435 abort();
1436 }
a33609ca 1437 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1438 }
1439 break;
e37a5c7f
CP		 1440 case 0x14: {
1441 uint32_t times;
1442
1443 c->function = i;
1444 c->index = 0;
1445 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1446 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1447 times = c->eax;
1448
1449 for (j = 1; j <= times; ++j) {
1450 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1451 fprintf(stderr, "cpuid_data is full, no space for "
1452 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1453 abort();
1454 }
1455 c = &cpuid_data.entries[cpuid_i++];
1456 c->function = i;
1457 c->index = j;
1458 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1459 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1460 }
1461 break;
1462 }
486bd5a2 1463 default:
486bd5a2 1464 c->function = i;
a33609ca
AL		 1465 c->flags = 0;
1466 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1467 break;
1468 }
05330448 1469 }
0d894367
PB		 1470
1471 if (limit >= 0x0a) {
0b368a10 1472 uint32_t eax, edx;
0d894367 1473
0b368a10
JD		 1474 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1475
1476 has_architectural_pmu_version = eax & 0xff;
1477 if (has_architectural_pmu_version > 0) {
1478 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1479
1480 /* Shouldn't be more than 32, since that's the number of bits
1481 * available in EBX to tell us _which_ counters are available.
1482 * Play it safe.
1483 */
0b368a10
JD		 1484 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1485 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1486 }
1487
1488 if (has_architectural_pmu_version > 1) {
1489 num_architectural_pmu_fixed_counters = edx & 0x1f;
1490
1491 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1492 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1493 }
0d894367
PB		 1494 }
1495 }
1496 }
1497
a33609ca 1498 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1499
1500 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1501 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1502 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1503 abort();
1504 }
bb0300dc 1505 c = &cpuid_data.entries[cpuid_i++];
05330448 1506
8f4202fb
BM		 1507 switch (i) {
1508 case 0x8000001d:
1509 /* Query for all AMD cache information leaves */
1510 for (j = 0; ; j++) {
1511 c->function = i;
1512 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1513 c->index = j;
1514 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1515
1516 if (c->eax == 0) {
1517 break;
1518 }
1519 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1520 fprintf(stderr, "cpuid_data is full, no space for "
1521 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1522 abort();
1523 }
1524 c = &cpuid_data.entries[cpuid_i++];
1525 }
1526 break;
1527 default:
1528 c->function = i;
1529 c->flags = 0;
1530 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1531 break;
1532 }
05330448
AL		 1533 }
1534
b3baa152
BW		 1535 /* Call Centaur's CPUID instructions they are supported. */
1536 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1537 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1538
1539 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1540 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1541 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1542 abort();
1543 }
b3baa152
BW		 1544 c = &cpuid_data.entries[cpuid_i++];
1545
1546 c->function = i;
1547 c->flags = 0;
1548 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1549 }
1550 }
1551
05330448
AL		 1552 cpuid_data.cpuid.nent = cpuid_i;
1553
e7701825 1554 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1555 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1556 (CPUID_MCE | CPUID_MCA)
a60f24b5 1557 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1558 uint64_t mcg_cap, unsupported_caps;
e7701825 1559 int banks;
32a42024 1560 int ret;
e7701825 1561
a60f24b5 1562 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1563 if (ret < 0) {
1564 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1565 return ret;
e7701825 1566 }
75d49497 1567
2590f15b 1568 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1569 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1570 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1571 return -ENOTSUP;
75d49497 1572 }
49b69cbf 1573
5120901a
EH		 1574 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1575 if (unsupported_caps) {
87f8b626
AR		 1576 if (unsupported_caps & MCG_LMCE_P) {
1577 error_report("kvm: LMCE not supported");
1578 return -ENOTSUP;
1579 }
3dc6f869
AF		 1580 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1581 unsupported_caps);
5120901a
EH		 1582 }
1583
2590f15b
EH		 1584 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1585 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1586 if (ret < 0) {
1587 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1588 return ret;
1589 }
e7701825 1590 }
e7701825 1591
b8cc45d6
GC		 1592 qemu_add_vm_change_state_handler(cpu_update_state, env);
1593
df67696e
LJ		 1594 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1595 if (c) {
1596 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1597 !!(c->ecx & CPUID_EXT_SMX);
1598 }
1599
d98f2607
PB		 1600 if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1601 error_setg(&vmx_mig_blocker,
1602 "Nested VMX virtualization does not support live migration yet");
1603 r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1604 if (local_err) {
1605 error_report_err(local_err);
1606 error_free(vmx_mig_blocker);
1607 return r;
1608 }
1609 }
1610
87f8b626
AR		 1611 if (env->mcg_cap & MCG_LMCE_P) {
1612 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1613 }
1614
d99569d9
EH		 1615 if (!env->user_tsc_khz) {
1616 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1617 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1618 error_setg(&invtsc_mig_blocker,
1619 "State blocked by non-migratable CPU device"
1620 " (invtsc flag)");
fe44dc91
AA		 1621 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1622 if (local_err) {
1623 error_report_err(local_err);
1624 error_free(invtsc_mig_blocker);
6b2341ee 1625 goto fail2;
fe44dc91 1626 }
d99569d9 1627 }
68bfd0ad
MT		 1628 }
1629
9954a158
PDJ		 1630 if (cpu->vmware_cpuid_freq
1631 /* Guests depend on 0x40000000 to detect this feature, so only expose
1632 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1633 && cpu->expose_kvm
1634 && kvm_base == KVM_CPUID_SIGNATURE
1635 /* TSC clock must be stable and known for this feature. */
4bb95b82 1636 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1637
1638 c = &cpuid_data.entries[cpuid_i++];
1639 c->function = KVM_CPUID_SIGNATURE | 0x10;
1640 c->eax = env->tsc_khz;
1641 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1642 * APIC_BUS_CYCLE_NS */
1643 c->ebx = 1000000;
1644 c->ecx = c->edx = 0;
1645
1646 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1647 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1648 }
1649
1650 cpuid_data.cpuid.nent = cpuid_i;
1651
1652 cpuid_data.cpuid.padding = 0;
1653 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1654 if (r) {
1655 goto fail;
1656 }
1657
28143b40 1658 if (has_xsave) {
5b8063c4 1659 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1660 }
d71b62a1 1661 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1662
273c515c
PB		 1663 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1664 has_msr_tsc_aux = false;
1665 }
d1ae67f6 1666
e9688fab
RK		 1667 r = hyperv_init_vcpu(cpu);
1668 if (r) {
1669 goto fail;
1670 }
1671
e7429073 1672 return 0;
fe44dc91
AA		 1673
1674 fail:
1675 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee
LA		 1676 fail2:
1677 migrate_del_blocker(vmx_mig_blocker);
1678
fe44dc91 1679 return r;
05330448
AL		 1680}
1681
b1115c99
LA		 1682int kvm_arch_destroy_vcpu(CPUState *cs)
1683{
1684 X86CPU *cpu = X86_CPU(cs);
1685
1686 if (cpu->kvm_msr_buf) {
1687 g_free(cpu->kvm_msr_buf);
1688 cpu->kvm_msr_buf = NULL;
1689 }
1690
1691 return 0;
1692}
1693
50a2c6e5 1694void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1695{
20d695a9 1696 CPUX86State *env = &cpu->env;
dd673288 1697
1a5e9d2f 1698 env->xcr0 = 1;
ddced198 1699 if (kvm_irqchip_in_kernel()) {
dd673288 1700 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1701 KVM_MP_STATE_UNINITIALIZED;
1702 } else {
1703 env->mp_state = KVM_MP_STATE_RUNNABLE;
1704 }
689141dd 1705
2d384d7c 1706 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1707 int i;
1708 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1709 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1710 }
606c34bf
RK		 1711
1712 hyperv_x86_synic_reset(cpu);
689141dd 1713 }
caa5af0f
JK		 1714}
1715
e0723c45
PB		 1716void kvm_arch_do_init_vcpu(X86CPU *cpu)
1717{
1718 CPUX86State *env = &cpu->env;
1719
1720 /* APs get directly into wait-for-SIPI state. */
1721 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1722 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1723 }
1724}
1725
f57bceb6
RH		 1726static int kvm_get_supported_feature_msrs(KVMState *s)
1727{
1728 int ret = 0;
1729
1730 if (kvm_feature_msrs != NULL) {
1731 return 0;
1732 }
1733
1734 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1735 return 0;
1736 }
1737
1738 struct kvm_msr_list msr_list;
1739
1740 msr_list.nmsrs = 0;
1741 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1742 if (ret < 0 && ret != -E2BIG) {
1743 error_report("Fetch KVM feature MSR list failed: %s",
1744 strerror(-ret));
1745 return ret;
1746 }
1747
1748 assert(msr_list.nmsrs > 0);
1749 kvm_feature_msrs = (struct kvm_msr_list *) \
1750 g_malloc0(sizeof(msr_list) +
1751 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1752
1753 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1754 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1755
1756 if (ret < 0) {
1757 error_report("Fetch KVM feature MSR list failed: %s",
1758 strerror(-ret));
1759 g_free(kvm_feature_msrs);
1760 kvm_feature_msrs = NULL;
1761 return ret;
1762 }
1763
1764 return 0;
1765}
1766
c3a3a7d3 1767static int kvm_get_supported_msrs(KVMState *s)
05330448 1768{
75b10c43 1769 static int kvm_supported_msrs;
c3a3a7d3 1770 int ret = 0;
05330448
AL		 1771
1772 /* first time */
75b10c43 1773 if (kvm_supported_msrs == 0) {
05330448
AL		 1774 struct kvm_msr_list msr_list, *kvm_msr_list;
1775
75b10c43 1776 kvm_supported_msrs = -1;
05330448
AL		 1777
1778 /* Obtain MSR list from KVM. These are the MSRs that we must
1779 * save/restore */
4c9f7372 1780 msr_list.nmsrs = 0;
c3a3a7d3 1781 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1782 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1783 return ret;
6fb6d245 1784 }
d9db889f
JK		 1785 /* Old kernel modules had a bug and could write beyond the provided
1786 memory. Allocate at least a safe amount of 1K. */
7267c094 1787 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1788 msr_list.nmsrs *
1789 sizeof(msr_list.indices[0])));
05330448 1790
55308450 1791 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1792 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1793 if (ret >= 0) {
1794 int i;
1795
1796 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1797 switch (kvm_msr_list->indices[i]) {
1798 case MSR_STAR:
c3a3a7d3 1799 has_msr_star = true;
1d268dec
LP		 1800 break;
1801 case MSR_VM_HSAVE_PA:
c3a3a7d3 1802 has_msr_hsave_pa = true;
1d268dec
LP		 1803 break;
1804 case MSR_TSC_AUX:
c9b8f6b6 1805 has_msr_tsc_aux = true;
1d268dec
LP		 1806 break;
1807 case MSR_TSC_ADJUST:
f28558d3 1808 has_msr_tsc_adjust = true;
1d268dec
LP		 1809 break;
1810 case MSR_IA32_TSCDEADLINE:
aa82ba54 1811 has_msr_tsc_deadline = true;
1d268dec
LP		 1812 break;
1813 case MSR_IA32_SMBASE:
fc12d72e 1814 has_msr_smbase = true;
1d268dec 1815 break;
e13713db
LA		 1816 case MSR_SMI_COUNT:
1817 has_msr_smi_count = true;
1818 break;
1d268dec 1819 case MSR_IA32_MISC_ENABLE:
21e87c46 1820 has_msr_misc_enable = true;
1d268dec
LP		 1821 break;
1822 case MSR_IA32_BNDCFGS:
79e9ebeb 1823 has_msr_bndcfgs = true;
1d268dec
LP		 1824 break;
1825 case MSR_IA32_XSS:
18cd2c17 1826 has_msr_xss = true;
3c254ab8 1827 break;
1d268dec 1828 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1829 has_msr_hv_crash = true;
1d268dec
LP		 1830 break;
1831 case HV_X64_MSR_RESET:
744b8a94 1832 has_msr_hv_reset = true;
1d268dec
LP		 1833 break;
1834 case HV_X64_MSR_VP_INDEX:
8c145d7c 1835 has_msr_hv_vpindex = true;
1d268dec
LP		 1836 break;
1837 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1838 has_msr_hv_runtime = true;
1d268dec
LP		 1839 break;
1840 case HV_X64_MSR_SCONTROL:
866eea9a 1841 has_msr_hv_synic = true;
1d268dec
LP		 1842 break;
1843 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1844 has_msr_hv_stimer = true;
1d268dec 1845 break;
d72bc7f6
LP		 1846 case HV_X64_MSR_TSC_FREQUENCY:
1847 has_msr_hv_frequencies = true;
1848 break;
ba6a4fd9
VK		 1849 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1850 has_msr_hv_reenlightenment = true;
1851 break;
a33a2cfe
PB		 1852 case MSR_IA32_SPEC_CTRL:
1853 has_msr_spec_ctrl = true;
1854 break;
cfeea0c0
KRW		 1855 case MSR_VIRT_SSBD:
1856 has_msr_virt_ssbd = true;
1857 break;
aec5e9c3
BD		 1858 case MSR_IA32_ARCH_CAPABILITIES:
1859 has_msr_arch_capabs = true;
1860 break;
597360c0
XL		 1861 case MSR_IA32_CORE_CAPABILITY:
1862 has_msr_core_capabs = true;
1863 break;
ff99aa64 1864 }
05330448
AL		 1865 }
1866 }
1867
7267c094 1868 g_free(kvm_msr_list);
05330448
AL		 1869 }
1870
c3a3a7d3 1871 return ret;
05330448
AL		 1872}
1873
6410848b
PB		 1874static Notifier smram_machine_done;
1875static KVMMemoryListener smram_listener;
1876static AddressSpace smram_address_space;
1877static MemoryRegion smram_as_root;
1878static MemoryRegion smram_as_mem;
1879
1880static void register_smram_listener(Notifier *n, void *unused)
1881{
1882 MemoryRegion *smram =
1883 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1884
1885 /* Outer container... */
1886 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1887 memory_region_set_enabled(&smram_as_root, true);
1888
1889 /* ... with two regions inside: normal system memory with low
1890 * priority, and...
1891 */
1892 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1893 get_system_memory(), 0, ~0ull);
1894 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1895 memory_region_set_enabled(&smram_as_mem, true);
1896
1897 if (smram) {
1898 /* ... SMRAM with higher priority */
1899 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1900 memory_region_set_enabled(smram, true);
1901 }
1902
1903 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1904 kvm_memory_listener_register(kvm_state, &smram_listener,
1905 &smram_address_space, 1);
1906}
1907
b16565b3 1908int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1909{
11076198 1910 uint64_t identity_base = 0xfffbc000;
39d6960a 1911 uint64_t shadow_mem;
20420430 1912 int ret;
25d2e361 1913 struct utsname utsname;
20420430 1914
28143b40 1915 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1916 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1917 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1918
e9688fab
RK		 1919 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1920
c3a3a7d3 1921 ret = kvm_get_supported_msrs(s);
20420430 1922 if (ret < 0) {
20420430
SY		 1923 return ret;
1924 }
25d2e361 1925
f57bceb6
RH		 1926 kvm_get_supported_feature_msrs(s);
1927
25d2e361
MT		 1928 uname(&utsname);
1929 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1930
4c5b10b7 1931 /*
11076198
JK		 1932 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1933 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1934 * Since these must be part of guest physical memory, we need to allocate
1935 * them, both by setting their start addresses in the kernel and by
1936 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1937 *
1938 * Older KVM versions may not support setting the identity map base. In
1939 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1940 * size.
4c5b10b7 1941 */
11076198
JK		 1942 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1943 /* Allows up to 16M BIOSes. */
1944 identity_base = 0xfeffc000;
1945
1946 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1947 if (ret < 0) {
1948 return ret;
1949 }
4c5b10b7 1950 }
e56ff191 1951
11076198
JK		 1952 /* Set TSS base one page after EPT identity map. */
1953 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1954 if (ret < 0) {
1955 return ret;
1956 }
1957
11076198
JK		 1958 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1959 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1960 if (ret < 0) {
11076198 1961 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1962 return ret;
1963 }
3c85e74f 1964 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1965
4689b77b 1966 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1967 if (shadow_mem != -1) {
1968 shadow_mem /= 4096;
1969 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1970 if (ret < 0) {
1971 return ret;
39d6960a
JK		 1972 }
1973 }
6410848b 1974
d870cfde
GA		 1975 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1976 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1977 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1978 smram_machine_done.notify = register_smram_listener;
1979 qemu_add_machine_init_done_notifier(&smram_machine_done);
1980 }
6f131f13
MT		 1981
1982 if (enable_cpu_pm) {
1983 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1984 int ret;
1985
1986/* Work around for kernel header with a typo. TODO: fix header and drop. */
1987#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1988#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1989#endif
1990 if (disable_exits) {
1991 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1992 KVM_X86_DISABLE_EXITS_HLT |
1993 KVM_X86_DISABLE_EXITS_PAUSE);
1994 }
1995
1996 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1997 disable_exits);
1998 if (ret < 0) {
1999 error_report("kvm: guest stopping CPU not supported: %s",
2000 strerror(-ret));
2001 }
2002 }
2003
11076198 2004 return 0;
05330448 2005}
b9bec74b 2006
05330448
AL		 2007static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2008{
2009 lhs->selector = rhs->selector;
2010 lhs->base = rhs->base;
2011 lhs->limit = rhs->limit;
2012 lhs->type = 3;
2013 lhs->present = 1;
2014 lhs->dpl = 3;
2015 lhs->db = 0;
2016 lhs->s = 1;
2017 lhs->l = 0;
2018 lhs->g = 0;
2019 lhs->avl = 0;
2020 lhs->unusable = 0;
2021}
2022
2023static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2024{
2025 unsigned flags = rhs->flags;
2026 lhs->selector = rhs->selector;
2027 lhs->base = rhs->base;
2028 lhs->limit = rhs->limit;
2029 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2030 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2031 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2032 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2033 lhs->s = (flags & DESC_S_MASK) != 0;
2034 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2035 lhs->g = (flags & DESC_G_MASK) != 0;
2036 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2037 lhs->unusable = !lhs->present;
7e680753 2038 lhs->padding = 0;
05330448
AL		 2039}
2040
2041static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2042{
2043 lhs->selector = rhs->selector;
2044 lhs->base = rhs->base;
2045 lhs->limit = rhs->limit;
d45fc087
RP		 2046 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2047 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2048 (rhs->dpl << DESC_DPL_SHIFT) |
2049 (rhs->db << DESC_B_SHIFT) |
2050 (rhs->s * DESC_S_MASK) |
2051 (rhs->l << DESC_L_SHIFT) |
2052 (rhs->g * DESC_G_MASK) |
2053 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2054}
2055
2056static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2057{
b9bec74b 2058 if (set) {
05330448 2059 *kvm_reg = *qemu_reg;
b9bec74b 2060 } else {
05330448 2061 *qemu_reg = *kvm_reg;
b9bec74b 2062 }
05330448
AL		 2063}
2064
1bc22652 2065static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2066{
1bc22652 2067 CPUX86State *env = &cpu->env;
05330448
AL		 2068 struct kvm_regs regs;
2069 int ret = 0;
2070
2071 if (!set) {
1bc22652 2072 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2073 if (ret < 0) {
05330448 2074 return ret;
b9bec74b 2075 }
05330448
AL		 2076 }
2077
2078 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2079 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2080 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2081 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2082 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2083 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2084 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2085 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2086#ifdef TARGET_X86_64
2087 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2088 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2089 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2090 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2091 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2092 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2093 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2094 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2095#endif
2096
2097 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2098 kvm_getput_reg(&regs.rip, &env->eip, set);
2099
b9bec74b 2100 if (set) {
1bc22652 2101 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2102 }
05330448
AL		 2103
2104 return ret;
2105}
2106
1bc22652 2107static int kvm_put_fpu(X86CPU *cpu)
05330448 2108{
1bc22652 2109 CPUX86State *env = &cpu->env;
05330448
AL		 2110 struct kvm_fpu fpu;
2111 int i;
2112
2113 memset(&fpu, 0, sizeof fpu);
2114 fpu.fsw = env->fpus & ~(7 << 11);
2115 fpu.fsw |= (env->fpstt & 7) << 11;
2116 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2117 fpu.last_opcode = env->fpop;
2118 fpu.last_ip = env->fpip;
2119 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2120 for (i = 0; i < 8; ++i) {
2121 fpu.ftwx |= (!env->fptags[i]) << i;
2122 }
05330448 2123 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2124 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2125 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2126 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2127 }
05330448
AL		 2128 fpu.mxcsr = env->mxcsr;
2129
1bc22652 2130 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2131}
2132
6b42494b
JK		 2133#define XSAVE_FCW_FSW 0
2134#define XSAVE_FTW_FOP 1
f1665b21
SY		 2135#define XSAVE_CWD_RIP 2
2136#define XSAVE_CWD_RDP 4
2137#define XSAVE_MXCSR 6
2138#define XSAVE_ST_SPACE 8
2139#define XSAVE_XMM_SPACE 40
2140#define XSAVE_XSTATE_BV 128
2141#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2142#define XSAVE_BNDREGS 240
2143#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2144#define XSAVE_OPMASK 272
2145#define XSAVE_ZMM_Hi256 288
2146#define XSAVE_Hi16_ZMM 416
f74eefe0 2147#define XSAVE_PKRU 672
f1665b21 2148
b503717d 2149#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2150 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2151
2152#define ASSERT_OFFSET(word_offset, field) \
2153 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2154 offsetof(X86XSaveArea, field))
2155
2156ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2157ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2158ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2159ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2160ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2161ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2162ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2163ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2164ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2165ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2166ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2167ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2168ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2169ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2170ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2171
1bc22652 2172static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2173{
1bc22652 2174 CPUX86State *env = &cpu->env;
5b8063c4 2175 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2176
28143b40 2177 if (!has_xsave) {
1bc22652 2178 return kvm_put_fpu(cpu);
b9bec74b 2179 }
86a57621 2180 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2181
9be38598 2182 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2183}
2184
1bc22652 2185static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2186{
1bc22652 2187 CPUX86State *env = &cpu->env;
bdfc8480 2188 struct kvm_xcrs xcrs = {};
f1665b21 2189
28143b40 2190 if (!has_xcrs) {
f1665b21 2191 return 0;
b9bec74b 2192 }
f1665b21
SY		 2193
2194 xcrs.nr_xcrs = 1;
2195 xcrs.flags = 0;
2196 xcrs.xcrs[0].xcr = 0;
2197 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2198 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2199}
2200
1bc22652 2201static int kvm_put_sregs(X86CPU *cpu)
05330448 2202{
1bc22652 2203 CPUX86State *env = &cpu->env;
05330448
AL		 2204 struct kvm_sregs sregs;
2205
0e607a80
JK		 2206 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2207 if (env->interrupt_injected >= 0) {
2208 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2209 (uint64_t)1 << (env->interrupt_injected % 64);
2210 }
05330448
AL		 2211
2212 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2213 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2214 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2215 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2216 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2217 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2218 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2219 } else {
b9bec74b
JK		 2220 set_seg(&sregs.cs, &env->segs[R_CS]);
2221 set_seg(&sregs.ds, &env->segs[R_DS]);
2222 set_seg(&sregs.es, &env->segs[R_ES]);
2223 set_seg(&sregs.fs, &env->segs[R_FS]);
2224 set_seg(&sregs.gs, &env->segs[R_GS]);
2225 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2226 }
2227
2228 set_seg(&sregs.tr, &env->tr);
2229 set_seg(&sregs.ldt, &env->ldt);
2230
2231 sregs.idt.limit = env->idt.limit;
2232 sregs.idt.base = env->idt.base;
7e680753 2233 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2234 sregs.gdt.limit = env->gdt.limit;
2235 sregs.gdt.base = env->gdt.base;
7e680753 2236 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2237
2238 sregs.cr0 = env->cr[0];
2239 sregs.cr2 = env->cr[2];
2240 sregs.cr3 = env->cr[3];
2241 sregs.cr4 = env->cr[4];
2242
02e51483
CF		 2243 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2244 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2245
2246 sregs.efer = env->efer;
2247
1bc22652 2248 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2249}
2250
d71b62a1
EH		 2251static void kvm_msr_buf_reset(X86CPU *cpu)
2252{
2253 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2254}
2255
9c600a84
EH		 2256static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2257{
2258 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2259 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2260 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2261
2262 assert((void *)(entry + 1) <= limit);
2263
1abc2cae
EH		 2264 entry->index = index;
2265 entry->reserved = 0;
2266 entry->data = value;
9c600a84
EH		 2267 msrs->nmsrs++;
2268}
2269
73e1b8f2
PB		 2270static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2271{
2272 kvm_msr_buf_reset(cpu);
2273 kvm_msr_entry_add(cpu, index, value);
2274
2275 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2276}
2277
f8d9ccf8
DDAG		 2278void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2279{
2280 int ret;
2281
2282 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2283 assert(ret == 1);
2284}
2285
7477cd38
MT		 2286static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2287{
2288 CPUX86State *env = &cpu->env;
48e1a45c 2289 int ret;
7477cd38
MT		 2290
2291 if (!has_msr_tsc_deadline) {
2292 return 0;
2293 }
2294
73e1b8f2 2295 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2296 if (ret < 0) {
2297 return ret;
2298 }
2299
2300 assert(ret == 1);
2301 return 0;
7477cd38
MT		 2302}
2303
6bdf863d
JK		 2304/*
2305 * Provide a separate write service for the feature control MSR in order to
2306 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2307 * before writing any other state because forcibly leaving nested mode
2308 * invalidates the VCPU state.
2309 */
2310static int kvm_put_msr_feature_control(X86CPU *cpu)
2311{
48e1a45c
PB		 2312 int ret;
2313
2314 if (!has_msr_feature_control) {
2315 return 0;
2316 }
6bdf863d 2317
73e1b8f2
PB		 2318 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2319 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2320 if (ret < 0) {
2321 return ret;
2322 }
2323
2324 assert(ret == 1);
2325 return 0;
6bdf863d
JK		 2326}
2327
1bc22652 2328static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2329{
1bc22652 2330 CPUX86State *env = &cpu->env;
9c600a84 2331 int i;
48e1a45c 2332 int ret;
05330448 2333
d71b62a1
EH		 2334 kvm_msr_buf_reset(cpu);
2335
9c600a84
EH		 2336 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2337 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2338 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2339 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2340 if (has_msr_star) {
9c600a84 2341 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2342 }
c3a3a7d3 2343 if (has_msr_hsave_pa) {
9c600a84 2344 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2345 }
c9b8f6b6 2346 if (has_msr_tsc_aux) {
9c600a84 2347 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2348 }
f28558d3 2349 if (has_msr_tsc_adjust) {
9c600a84 2350 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2351 }
21e87c46 2352 if (has_msr_misc_enable) {
9c600a84 2353 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2354 env->msr_ia32_misc_enable);
2355 }
fc12d72e 2356 if (has_msr_smbase) {
9c600a84 2357 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2358 }
e13713db
LA		 2359 if (has_msr_smi_count) {
2360 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2361 }
439d19f2 2362 if (has_msr_bndcfgs) {
9c600a84 2363 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2364 }
18cd2c17 2365 if (has_msr_xss) {
9c600a84 2366 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2367 }
a33a2cfe
PB		 2368 if (has_msr_spec_ctrl) {
2369 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2370 }
cfeea0c0
KRW		 2371 if (has_msr_virt_ssbd) {
2372 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2373 }
2374
05330448 2375#ifdef TARGET_X86_64
25d2e361 2376 if (lm_capable_kernel) {
9c600a84
EH		 2377 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2378 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2379 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2380 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2381 }
05330448 2382#endif
a33a2cfe 2383
d86f9636 2384 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2385 if (has_msr_arch_capabs) {
2386 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2387 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2388 }
2389
597360c0
XL		 2390 if (has_msr_core_capabs) {
2391 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2392 env->features[FEAT_CORE_CAPABILITY]);
2393 }
2394
ff5c186b 2395 /*
0d894367
PB		 2396 * The following MSRs have side effects on the guest or are too heavy
2397 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2398 */
2399 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2400 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2401 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2402 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2403 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2404 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2405 }
55c911a5 2406 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2407 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2408 }
55c911a5 2409 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2410 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2411 }
0b368a10
JD		 2412 if (has_architectural_pmu_version > 0) {
2413 if (has_architectural_pmu_version > 1) {
2414 /* Stop the counter. */
2415 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2416 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2417 }
0d894367
PB		 2418
2419 /* Set the counter values. */
0b368a10 2420 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2421 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2422 env->msr_fixed_counters[i]);
2423 }
0b368a10 2424 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2425 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2426 env->msr_gp_counters[i]);
9c600a84 2427 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2428 env->msr_gp_evtsel[i]);
2429 }
0b368a10
JD		 2430 if (has_architectural_pmu_version > 1) {
2431 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2432 env->msr_global_status);
2433 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2434 env->msr_global_ovf_ctrl);
2435
2436 /* Now start the PMU. */
2437 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2438 env->msr_fixed_ctr_ctrl);
2439 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2440 env->msr_global_ctrl);
2441 }
0d894367 2442 }
da1cc323
EY		 2443 /*
2444 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2445 * only sync them to KVM on the first cpu
2446 */
2447 if (current_cpu == first_cpu) {
2448 if (has_msr_hv_hypercall) {
2449 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2450 env->msr_hv_guest_os_id);
2451 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2452 env->msr_hv_hypercall);
2453 }
2d384d7c 2454 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2455 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2456 env->msr_hv_tsc);
2457 }
2d384d7c 2458 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2459 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2460 env->msr_hv_reenlightenment_control);
2461 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2462 env->msr_hv_tsc_emulation_control);
2463 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2464 env->msr_hv_tsc_emulation_status);
2465 }
eab70139 2466 }
2d384d7c 2467 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2468 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2469 env->msr_hv_vapic);
eab70139 2470 }
f2a53c9e
AS		 2471 if (has_msr_hv_crash) {
2472 int j;
2473
5e953812 2474 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2475 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2476 env->msr_hv_crash_params[j]);
2477
5e953812 2478 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2479 }
46eb8f98 2480 if (has_msr_hv_runtime) {
9c600a84 2481 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2482 }
2d384d7c
VK		 2483 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2484 && hv_vpindex_settable) {
701189e3
RK		 2485 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2486 hyperv_vp_index(CPU(cpu)));
e9688fab 2487 }
2d384d7c 2488 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2489 int j;
2490
09df29b6
RK		 2491 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2492
9c600a84 2493 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2494 env->msr_hv_synic_control);
9c600a84 2495 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2496 env->msr_hv_synic_evt_page);
9c600a84 2497 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2498 env->msr_hv_synic_msg_page);
2499
2500 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2501 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2502 env->msr_hv_synic_sint[j]);
2503 }
2504 }
ff99aa64
AS		 2505 if (has_msr_hv_stimer) {
2506 int j;
2507
2508 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2509 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2510 env->msr_hv_stimer_config[j]);
2511 }
2512
2513 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2514 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2515 env->msr_hv_stimer_count[j]);
2516 }
2517 }
1eabfce6 2518 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2519 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2520
9c600a84
EH		 2521 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2522 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2523 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2524 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2525 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2526 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2527 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2528 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2529 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2530 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2531 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2532 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2533 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2534 /* The CPU GPs if we write to a bit above the physical limit of
2535 * the host CPU (and KVM emulates that)
2536 */
2537 uint64_t mask = env->mtrr_var[i].mask;
2538 mask &= phys_mask;
2539
9c600a84
EH		 2540 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2541 env->mtrr_var[i].base);
112dad69 2542 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2543 }
2544 }
b77146e9
CP		 2545 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2546 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2547 0x14, 1, R_EAX) & 0x7;
2548
2549 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2550 env->msr_rtit_ctrl);
2551 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2552 env->msr_rtit_status);
2553 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2554 env->msr_rtit_output_base);
2555 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2556 env->msr_rtit_output_mask);
2557 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2558 env->msr_rtit_cr3_match);
2559 for (i = 0; i < addr_num; i++) {
2560 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2561 env->msr_rtit_addrs[i]);
2562 }
2563 }
6bdf863d
JK		 2564
2565 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2566 * kvm_put_msr_feature_control. */
ea643051 2567 }
57780495 2568 if (env->mcg_cap) {
d8da8574 2569 int i;
b9bec74b 2570
9c600a84
EH		 2571 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2572 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2573 if (has_msr_mcg_ext_ctl) {
2574 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2575 }
c34d440a 2576 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2577 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2578 }
2579 }
1a03675d 2580
d71b62a1 2581 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2582 if (ret < 0) {
2583 return ret;
2584 }
05330448 2585
c70b11d1
EH		 2586 if (ret < cpu->kvm_msr_buf->nmsrs) {
2587 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2588 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2589 (uint32_t)e->index, (uint64_t)e->data);
2590 }
2591
9c600a84 2592 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2593 return 0;
05330448
AL		 2594}
2595
2596
1bc22652 2597static int kvm_get_fpu(X86CPU *cpu)
05330448 2598{
1bc22652 2599 CPUX86State *env = &cpu->env;
05330448
AL		 2600 struct kvm_fpu fpu;
2601 int i, ret;
2602
1bc22652 2603 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2604 if (ret < 0) {
05330448 2605 return ret;
b9bec74b 2606 }
05330448
AL		 2607
2608 env->fpstt = (fpu.fsw >> 11) & 7;
2609 env->fpus = fpu.fsw;
2610 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2611 env->fpop = fpu.last_opcode;
2612 env->fpip = fpu.last_ip;
2613 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2614 for (i = 0; i < 8; ++i) {
2615 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2616 }
05330448 2617 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2618 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2619 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2620 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2621 }
05330448
AL		 2622 env->mxcsr = fpu.mxcsr;
2623
2624 return 0;
2625}
2626
1bc22652 2627static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2628{
1bc22652 2629 CPUX86State *env = &cpu->env;
5b8063c4 2630 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2631 int ret;
f1665b21 2632
28143b40 2633 if (!has_xsave) {
1bc22652 2634 return kvm_get_fpu(cpu);
b9bec74b 2635 }
f1665b21 2636
1bc22652 2637 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2638 if (ret < 0) {
f1665b21 2639 return ret;
0f53994f 2640 }
86a57621 2641 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2642
f1665b21 2643 return 0;
f1665b21
SY		 2644}
2645
1bc22652 2646static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2647{
1bc22652 2648 CPUX86State *env = &cpu->env;
f1665b21
SY		 2649 int i, ret;
2650 struct kvm_xcrs xcrs;
2651
28143b40 2652 if (!has_xcrs) {
f1665b21 2653 return 0;
b9bec74b 2654 }
f1665b21 2655
1bc22652 2656 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2657 if (ret < 0) {
f1665b21 2658 return ret;
b9bec74b 2659 }
f1665b21 2660
b9bec74b 2661 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2662 /* Only support xcr0 now */
0fd53fec
PB		 2663 if (xcrs.xcrs[i].xcr == 0) {
2664 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2665 break;
2666 }
b9bec74b 2667 }
f1665b21 2668 return 0;
f1665b21
SY		 2669}
2670
1bc22652 2671static int kvm_get_sregs(X86CPU *cpu)
05330448 2672{
1bc22652 2673 CPUX86State *env = &cpu->env;
05330448 2674 struct kvm_sregs sregs;
0e607a80 2675 int bit, i, ret;
05330448 2676
1bc22652 2677 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2678 if (ret < 0) {
05330448 2679 return ret;
b9bec74b 2680 }
05330448 2681
0e607a80
JK		 2682 /* There can only be one pending IRQ set in the bitmap at a time, so try
2683 to find it and save its number instead (-1 for none). */
2684 env->interrupt_injected = -1;
2685 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2686 if (sregs.interrupt_bitmap[i]) {
2687 bit = ctz64(sregs.interrupt_bitmap[i]);
2688 env->interrupt_injected = i * 64 + bit;
2689 break;
2690 }
2691 }
05330448
AL		 2692
2693 get_seg(&env->segs[R_CS], &sregs.cs);
2694 get_seg(&env->segs[R_DS], &sregs.ds);
2695 get_seg(&env->segs[R_ES], &sregs.es);
2696 get_seg(&env->segs[R_FS], &sregs.fs);
2697 get_seg(&env->segs[R_GS], &sregs.gs);
2698 get_seg(&env->segs[R_SS], &sregs.ss);
2699
2700 get_seg(&env->tr, &sregs.tr);
2701 get_seg(&env->ldt, &sregs.ldt);
2702
2703 env->idt.limit = sregs.idt.limit;
2704 env->idt.base = sregs.idt.base;
2705 env->gdt.limit = sregs.gdt.limit;
2706 env->gdt.base = sregs.gdt.base;
2707
2708 env->cr[0] = sregs.cr0;
2709 env->cr[2] = sregs.cr2;
2710 env->cr[3] = sregs.cr3;
2711 env->cr[4] = sregs.cr4;
2712
05330448 2713 env->efer = sregs.efer;
cce47516
JK		 2714
2715 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2716 x86_update_hflags(env);
05330448
AL		 2717
2718 return 0;
2719}
2720
1bc22652 2721static int kvm_get_msrs(X86CPU *cpu)
05330448 2722{
1bc22652 2723 CPUX86State *env = &cpu->env;
d71b62a1 2724 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2725 int ret, i;
fcc35e7c 2726 uint64_t mtrr_top_bits;
05330448 2727
d71b62a1
EH		 2728 kvm_msr_buf_reset(cpu);
2729
9c600a84
EH		 2730 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2731 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2732 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2733 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2734 if (has_msr_star) {
9c600a84 2735 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2736 }
c3a3a7d3 2737 if (has_msr_hsave_pa) {
9c600a84 2738 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2739 }
c9b8f6b6 2740 if (has_msr_tsc_aux) {
9c600a84 2741 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2742 }
f28558d3 2743 if (has_msr_tsc_adjust) {
9c600a84 2744 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2745 }
aa82ba54 2746 if (has_msr_tsc_deadline) {
9c600a84 2747 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2748 }
21e87c46 2749 if (has_msr_misc_enable) {
9c600a84 2750 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2751 }
fc12d72e 2752 if (has_msr_smbase) {
9c600a84 2753 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2754 }
e13713db
LA		 2755 if (has_msr_smi_count) {
2756 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2757 }
df67696e 2758 if (has_msr_feature_control) {
9c600a84 2759 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2760 }
79e9ebeb 2761 if (has_msr_bndcfgs) {
9c600a84 2762 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2763 }
18cd2c17 2764 if (has_msr_xss) {
9c600a84 2765 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2766 }
a33a2cfe
PB		 2767 if (has_msr_spec_ctrl) {
2768 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2769 }
cfeea0c0
KRW		 2770 if (has_msr_virt_ssbd) {
2771 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2772 }
b8cc45d6 2773 if (!env->tsc_valid) {
9c600a84 2774 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2775 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2776 }
2777
05330448 2778#ifdef TARGET_X86_64
25d2e361 2779 if (lm_capable_kernel) {
9c600a84
EH		 2780 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2781 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2782 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2783 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2784 }
05330448 2785#endif
9c600a84
EH		 2786 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2787 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2788 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2789 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2790 }
55c911a5 2791 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2792 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2793 }
55c911a5 2794 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2795 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2796 }
0b368a10
JD		 2797 if (has_architectural_pmu_version > 0) {
2798 if (has_architectural_pmu_version > 1) {
2799 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2800 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2801 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2802 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2803 }
2804 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2805 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2806 }
0b368a10 2807 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2808 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2809 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2810 }
2811 }
1a03675d 2812
57780495 2813 if (env->mcg_cap) {
9c600a84
EH		 2814 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2815 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2816 if (has_msr_mcg_ext_ctl) {
2817 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2818 }
b9bec74b 2819 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2820 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2821 }
57780495 2822 }
57780495 2823
1c90ef26 2824 if (has_msr_hv_hypercall) {
9c600a84
EH		 2825 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2826 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2827 }
2d384d7c 2828 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2829 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2830 }
2d384d7c 2831 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 2832 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2833 }
2d384d7c 2834 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2835 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2836 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2837 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2838 }
f2a53c9e
AS		 2839 if (has_msr_hv_crash) {
2840 int j;
2841
5e953812 2842 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2843 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2844 }
2845 }
46eb8f98 2846 if (has_msr_hv_runtime) {
9c600a84 2847 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2848 }
2d384d7c 2849 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2850 uint32_t msr;
2851
9c600a84 2852 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2853 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2854 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2855 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2856 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2857 }
2858 }
ff99aa64
AS		 2859 if (has_msr_hv_stimer) {
2860 uint32_t msr;
2861
2862 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2863 msr++) {
9c600a84 2864 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2865 }
2866 }
1eabfce6 2867 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2868 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2869 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2870 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2871 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2872 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2873 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2874 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2875 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2876 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2877 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2878 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2879 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2880 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2881 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2882 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2883 }
2884 }
5ef68987 2885
b77146e9
CP		 2886 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2887 int addr_num =
2888 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2889
2890 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2891 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2892 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2893 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2894 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2895 for (i = 0; i < addr_num; i++) {
2896 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2897 }
2898 }
2899
d71b62a1 2900 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2901 if (ret < 0) {
05330448 2902 return ret;
b9bec74b 2903 }
05330448 2904
c70b11d1
EH		 2905 if (ret < cpu->kvm_msr_buf->nmsrs) {
2906 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2907 error_report("error: failed to get MSR 0x%" PRIx32,
2908 (uint32_t)e->index);
2909 }
2910
9c600a84 2911 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2912 /*
2913 * MTRR masks: Each mask consists of 5 parts
2914 * a 10..0: must be zero
2915 * b 11 : valid bit
2916 * c n-1.12: actual mask bits
2917 * d 51..n: reserved must be zero
2918 * e 63.52: reserved must be zero
2919 *
2920 * 'n' is the number of physical bits supported by the CPU and is
2921 * apparently always <= 52. We know our 'n' but don't know what
2922 * the destinations 'n' is; it might be smaller, in which case
2923 * it masks (c) on loading. It might be larger, in which case
2924 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2925 * we're migrating to.
2926 */
2927
2928 if (cpu->fill_mtrr_mask) {
2929 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2930 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2931 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2932 } else {
2933 mtrr_top_bits = 0;
2934 }
2935
05330448 2936 for (i = 0; i < ret; i++) {
0d894367
PB		 2937 uint32_t index = msrs[i].index;
2938 switch (index) {
05330448
AL		 2939 case MSR_IA32_SYSENTER_CS:
2940 env->sysenter_cs = msrs[i].data;
2941 break;
2942 case MSR_IA32_SYSENTER_ESP:
2943 env->sysenter_esp = msrs[i].data;
2944 break;
2945 case MSR_IA32_SYSENTER_EIP:
2946 env->sysenter_eip = msrs[i].data;
2947 break;
0c03266a
JK		 2948 case MSR_PAT:
2949 env->pat = msrs[i].data;
2950 break;
05330448
AL		 2951 case MSR_STAR:
2952 env->star = msrs[i].data;
2953 break;
2954#ifdef TARGET_X86_64
2955 case MSR_CSTAR:
2956 env->cstar = msrs[i].data;
2957 break;
2958 case MSR_KERNELGSBASE:
2959 env->kernelgsbase = msrs[i].data;
2960 break;
2961 case MSR_FMASK:
2962 env->fmask = msrs[i].data;
2963 break;
2964 case MSR_LSTAR:
2965 env->lstar = msrs[i].data;
2966 break;
2967#endif
2968 case MSR_IA32_TSC:
2969 env->tsc = msrs[i].data;
2970 break;
c9b8f6b6
AS		 2971 case MSR_TSC_AUX:
2972 env->tsc_aux = msrs[i].data;
2973 break;
f28558d3
WA		 2974 case MSR_TSC_ADJUST:
2975 env->tsc_adjust = msrs[i].data;
2976 break;
aa82ba54
LJ		 2977 case MSR_IA32_TSCDEADLINE:
2978 env->tsc_deadline = msrs[i].data;
2979 break;
aa851e36
MT		 2980 case MSR_VM_HSAVE_PA:
2981 env->vm_hsave = msrs[i].data;
2982 break;
1a03675d
GC		 2983 case MSR_KVM_SYSTEM_TIME:
2984 env->system_time_msr = msrs[i].data;
2985 break;
2986 case MSR_KVM_WALL_CLOCK:
2987 env->wall_clock_msr = msrs[i].data;
2988 break;
57780495
MT		 2989 case MSR_MCG_STATUS:
2990 env->mcg_status = msrs[i].data;
2991 break;
2992 case MSR_MCG_CTL:
2993 env->mcg_ctl = msrs[i].data;
2994 break;
87f8b626
AR		 2995 case MSR_MCG_EXT_CTL:
2996 env->mcg_ext_ctl = msrs[i].data;
2997 break;
21e87c46
AK		 2998 case MSR_IA32_MISC_ENABLE:
2999 env->msr_ia32_misc_enable = msrs[i].data;
3000 break;
fc12d72e
PB		 3001 case MSR_IA32_SMBASE:
3002 env->smbase = msrs[i].data;
3003 break;
e13713db
LA		 3004 case MSR_SMI_COUNT:
3005 env->msr_smi_count = msrs[i].data;
3006 break;
0779caeb
ACL		 3007 case MSR_IA32_FEATURE_CONTROL:
3008 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3009 break;
79e9ebeb
LJ		 3010 case MSR_IA32_BNDCFGS:
3011 env->msr_bndcfgs = msrs[i].data;
3012 break;
18cd2c17
WL		 3013 case MSR_IA32_XSS:
3014 env->xss = msrs[i].data;
3015 break;
57780495 3016 default:
57780495
MT		 3017 if (msrs[i].index >= MSR_MC0_CTL &&
3018 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3019 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3020 }
d8da8574 3021 break;
f6584ee2
GN		 3022 case MSR_KVM_ASYNC_PF_EN:
3023 env->async_pf_en_msr = msrs[i].data;
3024 break;
bc9a839d
MT		 3025 case MSR_KVM_PV_EOI_EN:
3026 env->pv_eoi_en_msr = msrs[i].data;
3027 break;
917367aa
MT		 3028 case MSR_KVM_STEAL_TIME:
3029 env->steal_time_msr = msrs[i].data;
3030 break;
0d894367
PB		 3031 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3032 env->msr_fixed_ctr_ctrl = msrs[i].data;
3033 break;
3034 case MSR_CORE_PERF_GLOBAL_CTRL:
3035 env->msr_global_ctrl = msrs[i].data;
3036 break;
3037 case MSR_CORE_PERF_GLOBAL_STATUS:
3038 env->msr_global_status = msrs[i].data;
3039 break;
3040 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3041 env->msr_global_ovf_ctrl = msrs[i].data;
3042 break;
3043 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3044 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3045 break;
3046 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3047 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3048 break;
3049 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3050 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3051 break;
1c90ef26
VR		 3052 case HV_X64_MSR_HYPERCALL:
3053 env->msr_hv_hypercall = msrs[i].data;
3054 break;
3055 case HV_X64_MSR_GUEST_OS_ID:
3056 env->msr_hv_guest_os_id = msrs[i].data;
3057 break;
5ef68987
VR		 3058 case HV_X64_MSR_APIC_ASSIST_PAGE:
3059 env->msr_hv_vapic = msrs[i].data;
3060 break;
48a5f3bc
VR		 3061 case HV_X64_MSR_REFERENCE_TSC:
3062 env->msr_hv_tsc = msrs[i].data;
3063 break;
f2a53c9e
AS		 3064 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3065 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3066 break;
46eb8f98
AS		 3067 case HV_X64_MSR_VP_RUNTIME:
3068 env->msr_hv_runtime = msrs[i].data;
3069 break;
866eea9a
AS		 3070 case HV_X64_MSR_SCONTROL:
3071 env->msr_hv_synic_control = msrs[i].data;
3072 break;
866eea9a
AS		 3073 case HV_X64_MSR_SIEFP:
3074 env->msr_hv_synic_evt_page = msrs[i].data;
3075 break;
3076 case HV_X64_MSR_SIMP:
3077 env->msr_hv_synic_msg_page = msrs[i].data;
3078 break;
3079 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3080 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3081 break;
3082 case HV_X64_MSR_STIMER0_CONFIG:
3083 case HV_X64_MSR_STIMER1_CONFIG:
3084 case HV_X64_MSR_STIMER2_CONFIG:
3085 case HV_X64_MSR_STIMER3_CONFIG:
3086 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3087 msrs[i].data;
3088 break;
3089 case HV_X64_MSR_STIMER0_COUNT:
3090 case HV_X64_MSR_STIMER1_COUNT:
3091 case HV_X64_MSR_STIMER2_COUNT:
3092 case HV_X64_MSR_STIMER3_COUNT:
3093 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3094 msrs[i].data;
866eea9a 3095 break;
ba6a4fd9
VK		 3096 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3097 env->msr_hv_reenlightenment_control = msrs[i].data;
3098 break;
3099 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3100 env->msr_hv_tsc_emulation_control = msrs[i].data;
3101 break;
3102 case HV_X64_MSR_TSC_EMULATION_STATUS:
3103 env->msr_hv_tsc_emulation_status = msrs[i].data;
3104 break;
d1ae67f6
AW		 3105 case MSR_MTRRdefType:
3106 env->mtrr_deftype = msrs[i].data;
3107 break;
3108 case MSR_MTRRfix64K_00000:
3109 env->mtrr_fixed[0] = msrs[i].data;
3110 break;
3111 case MSR_MTRRfix16K_80000:
3112 env->mtrr_fixed[1] = msrs[i].data;
3113 break;
3114 case MSR_MTRRfix16K_A0000:
3115 env->mtrr_fixed[2] = msrs[i].data;
3116 break;
3117 case MSR_MTRRfix4K_C0000:
3118 env->mtrr_fixed[3] = msrs[i].data;
3119 break;
3120 case MSR_MTRRfix4K_C8000:
3121 env->mtrr_fixed[4] = msrs[i].data;
3122 break;
3123 case MSR_MTRRfix4K_D0000:
3124 env->mtrr_fixed[5] = msrs[i].data;
3125 break;
3126 case MSR_MTRRfix4K_D8000:
3127 env->mtrr_fixed[6] = msrs[i].data;
3128 break;
3129 case MSR_MTRRfix4K_E0000:
3130 env->mtrr_fixed[7] = msrs[i].data;
3131 break;
3132 case MSR_MTRRfix4K_E8000:
3133 env->mtrr_fixed[8] = msrs[i].data;
3134 break;
3135 case MSR_MTRRfix4K_F0000:
3136 env->mtrr_fixed[9] = msrs[i].data;
3137 break;
3138 case MSR_MTRRfix4K_F8000:
3139 env->mtrr_fixed[10] = msrs[i].data;
3140 break;
3141 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3142 if (index & 1) {
fcc35e7c
DDAG		 3143 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3144 mtrr_top_bits;
d1ae67f6
AW		 3145 } else {
3146 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3147 }
3148 break;
a33a2cfe
PB		 3149 case MSR_IA32_SPEC_CTRL:
3150 env->spec_ctrl = msrs[i].data;
3151 break;
cfeea0c0
KRW		 3152 case MSR_VIRT_SSBD:
3153 env->virt_ssbd = msrs[i].data;
3154 break;
b77146e9
CP		 3155 case MSR_IA32_RTIT_CTL:
3156 env->msr_rtit_ctrl = msrs[i].data;
3157 break;
3158 case MSR_IA32_RTIT_STATUS:
3159 env->msr_rtit_status = msrs[i].data;
3160 break;
3161 case MSR_IA32_RTIT_OUTPUT_BASE:
3162 env->msr_rtit_output_base = msrs[i].data;
3163 break;
3164 case MSR_IA32_RTIT_OUTPUT_MASK:
3165 env->msr_rtit_output_mask = msrs[i].data;
3166 break;
3167 case MSR_IA32_RTIT_CR3_MATCH:
3168 env->msr_rtit_cr3_match = msrs[i].data;
3169 break;
3170 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3171 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3172 break;
05330448
AL		 3173 }
3174 }
3175
3176 return 0;
3177}
3178
1bc22652 3179static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3180{
1bc22652 3181 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3182
1bc22652 3183 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3184}
3185
23d02d9b 3186static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3187{
259186a7 3188 CPUState *cs = CPU(cpu);
23d02d9b 3189 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3190 struct kvm_mp_state mp_state;
3191 int ret;
3192
259186a7 3193 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3194 if (ret < 0) {
3195 return ret;
3196 }
3197 env->mp_state = mp_state.mp_state;
c14750e8 3198 if (kvm_irqchip_in_kernel()) {
259186a7 3199 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3200 }
9bdbe550
HB		 3201 return 0;
3202}
3203
1bc22652 3204static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3205{
02e51483 3206 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3207 struct kvm_lapic_state kapic;
3208 int ret;
3209
3d4b2649 3210 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3211 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3212 if (ret < 0) {
3213 return ret;
3214 }
3215
3216 kvm_get_apic_state(apic, &kapic);
3217 }
3218 return 0;
3219}
3220
1bc22652 3221static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3222{
fc12d72e 3223 CPUState *cs = CPU(cpu);
1bc22652 3224 CPUX86State *env = &cpu->env;
076796f8 3225 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3226
3227 if (!kvm_has_vcpu_events()) {
3228 return 0;
3229 }
3230
31827373
JK		 3231 events.exception.injected = (env->exception_injected >= 0);
3232 events.exception.nr = env->exception_injected;
a0fb002c
JK		 3233 events.exception.has_error_code = env->has_error_code;
3234 events.exception.error_code = env->error_code;
3235
3236 events.interrupt.injected = (env->interrupt_injected >= 0);
3237 events.interrupt.nr = env->interrupt_injected;
3238 events.interrupt.soft = env->soft_interrupt;
3239
3240 events.nmi.injected = env->nmi_injected;
3241 events.nmi.pending = env->nmi_pending;
3242 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3243
3244 events.sipi_vector = env->sipi_vector;
68c6efe0 3245 events.flags = 0;
a0fb002c 3246
fc12d72e
PB		 3247 if (has_msr_smbase) {
3248 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3249 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3250 if (kvm_irqchip_in_kernel()) {
3251 /* As soon as these are moved to the kernel, remove them
3252 * from cs->interrupt_request.
3253 */
3254 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3255 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3256 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3257 } else {
3258 /* Keep these in cs->interrupt_request. */
3259 events.smi.pending = 0;
3260 events.smi.latched_init = 0;
3261 }
fc3a1fd7
DDAG		 3262 /* Stop SMI delivery on old machine types to avoid a reboot
3263 * on an inward migration of an old VM.
3264 */
3265 if (!cpu->kvm_no_smi_migration) {
3266 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3267 }
fc12d72e
PB		 3268 }
3269
ea643051 3270 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3271 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3272 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3273 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3274 }
ea643051 3275 }
aee028b9 3276
1bc22652 3277 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3278}
3279
1bc22652 3280static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3281{
1bc22652 3282 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3283 struct kvm_vcpu_events events;
3284 int ret;
3285
3286 if (!kvm_has_vcpu_events()) {
3287 return 0;
3288 }
3289
fc12d72e 3290 memset(&events, 0, sizeof(events));
1bc22652 3291 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3292 if (ret < 0) {
3293 return ret;
3294 }
31827373 3295 env->exception_injected =
a0fb002c
JK		 3296 events.exception.injected ? events.exception.nr : -1;
3297 env->has_error_code = events.exception.has_error_code;
3298 env->error_code = events.exception.error_code;
3299
3300 env->interrupt_injected =
3301 events.interrupt.injected ? events.interrupt.nr : -1;
3302 env->soft_interrupt = events.interrupt.soft;
3303
3304 env->nmi_injected = events.nmi.injected;
3305 env->nmi_pending = events.nmi.pending;
3306 if (events.nmi.masked) {
3307 env->hflags2 |= HF2_NMI_MASK;
3308 } else {
3309 env->hflags2 &= ~HF2_NMI_MASK;
3310 }
3311
fc12d72e
PB		 3312 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3313 if (events.smi.smm) {
3314 env->hflags |= HF_SMM_MASK;
3315 } else {
3316 env->hflags &= ~HF_SMM_MASK;
3317 }
3318 if (events.smi.pending) {
3319 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3320 } else {
3321 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3322 }
3323 if (events.smi.smm_inside_nmi) {
3324 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3325 } else {
3326 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3327 }
3328 if (events.smi.latched_init) {
3329 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3330 } else {
3331 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3332 }
3333 }
3334
a0fb002c 3335 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3336
3337 return 0;
3338}
3339
1bc22652 3340static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3341{
ed2803da 3342 CPUState *cs = CPU(cpu);
1bc22652 3343 CPUX86State *env = &cpu->env;
b0b1d690 3344 int ret = 0;
b0b1d690
JK		 3345 unsigned long reinject_trap = 0;
3346
3347 if (!kvm_has_vcpu_events()) {
3348 if (env->exception_injected == 1) {
3349 reinject_trap = KVM_GUESTDBG_INJECT_DB;
3350 } else if (env->exception_injected == 3) {
3351 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3352 }
3353 env->exception_injected = -1;
3354 }
3355
3356 /*
3357 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3358 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3359 * by updating the debug state once again if single-stepping is on.
3360 * Another reason to call kvm_update_guest_debug here is a pending debug
3361 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3362 * reinject them via SET_GUEST_DEBUG.
3363 */
3364 if (reinject_trap ||
ed2803da 3365 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3366 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3367 }
b0b1d690
JK		 3368 return ret;
3369}
3370
1bc22652 3371static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3372{
1bc22652 3373 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3374 struct kvm_debugregs dbgregs;
3375 int i;
3376
3377 if (!kvm_has_debugregs()) {
3378 return 0;
3379 }
3380
3381 for (i = 0; i < 4; i++) {
3382 dbgregs.db[i] = env->dr[i];
3383 }
3384 dbgregs.dr6 = env->dr[6];
3385 dbgregs.dr7 = env->dr[7];
3386 dbgregs.flags = 0;
3387
1bc22652 3388 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3389}
3390
1bc22652 3391static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3392{
1bc22652 3393 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3394 struct kvm_debugregs dbgregs;
3395 int i, ret;
3396
3397 if (!kvm_has_debugregs()) {
3398 return 0;
3399 }
3400
1bc22652 3401 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3402 if (ret < 0) {
b9bec74b 3403 return ret;
ff44f1a3
JK		 3404 }
3405 for (i = 0; i < 4; i++) {
3406 env->dr[i] = dbgregs.db[i];
3407 }
3408 env->dr[4] = env->dr[6] = dbgregs.dr6;
3409 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3410
3411 return 0;
3412}
3413
20d695a9 3414int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3415{
20d695a9 3416 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3417 int ret;
3418
2fa45344 3419 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3420
48e1a45c 3421 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 3422 ret = kvm_put_msr_feature_control(x86_cpu);
3423 if (ret < 0) {
3424 return ret;
3425 }
3426 }
3427
36f96c4b
HZ		 3428 if (level == KVM_PUT_FULL_STATE) {
3429 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3430 * because TSC frequency mismatch shouldn't abort migration,
3431 * unless the user explicitly asked for a more strict TSC
3432 * setting (e.g. using an explicit "tsc-freq" option).
3433 */
3434 kvm_arch_set_tsc_khz(cpu);
3435 }
3436
1bc22652 3437 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3438 if (ret < 0) {
05330448 3439 return ret;
b9bec74b 3440 }
1bc22652 3441 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3442 if (ret < 0) {
f1665b21 3443 return ret;
b9bec74b 3444 }
1bc22652 3445 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3446 if (ret < 0) {
05330448 3447 return ret;
b9bec74b 3448 }
1bc22652 3449 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3450 if (ret < 0) {
05330448 3451 return ret;
b9bec74b 3452 }
ab443475 3453 /* must be before kvm_put_msrs */
1bc22652 3454 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3455 if (ret < 0) {
3456 return ret;
3457 }
1bc22652 3458 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3459 if (ret < 0) {
05330448 3460 return ret;
b9bec74b 3461 }
4fadfa00
PH		 3462 ret = kvm_put_vcpu_events(x86_cpu, level);
3463 if (ret < 0) {
3464 return ret;
3465 }
ea643051 3466 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3467 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3468 if (ret < 0) {
680c1c6f
JK		 3469 return ret;
3470 }
ea643051 3471 }
7477cd38
MT		 3472
3473 ret = kvm_put_tscdeadline_msr(x86_cpu);
3474 if (ret < 0) {
3475 return ret;
3476 }
1bc22652 3477 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3478 if (ret < 0) {
b0b1d690 3479 return ret;
b9bec74b 3480 }
b0b1d690 3481 /* must be last */
1bc22652 3482 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3483 if (ret < 0) {
ff44f1a3 3484 return ret;
b9bec74b 3485 }
05330448
AL		 3486 return 0;
3487}
3488
20d695a9 3489int kvm_arch_get_registers(CPUState *cs)
05330448 3490{
20d695a9 3491 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3492 int ret;
3493
20d695a9 3494 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3495
4fadfa00 3496 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3497 if (ret < 0) {
f4f1110e 3498 goto out;
b9bec74b 3499 }
4fadfa00
PH		 3500 /*
3501 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3502 * KVM_GET_REGS and KVM_GET_SREGS.
3503 */
3504 ret = kvm_get_mp_state(cpu);
b9bec74b 3505 if (ret < 0) {
f4f1110e 3506 goto out;
b9bec74b 3507 }
4fadfa00 3508 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3509 if (ret < 0) {
f4f1110e 3510 goto out;
b9bec74b 3511 }
4fadfa00 3512 ret = kvm_get_xsave(cpu);
b9bec74b 3513 if (ret < 0) {
f4f1110e 3514 goto out;
b9bec74b 3515 }
4fadfa00 3516 ret = kvm_get_xcrs(cpu);
b9bec74b 3517 if (ret < 0) {
f4f1110e 3518 goto out;
b9bec74b 3519 }
4fadfa00 3520 ret = kvm_get_sregs(cpu);
b9bec74b 3521 if (ret < 0) {
f4f1110e 3522 goto out;
b9bec74b 3523 }
4fadfa00 3524 ret = kvm_get_msrs(cpu);
680c1c6f 3525 if (ret < 0) {
f4f1110e 3526 goto out;
680c1c6f 3527 }
4fadfa00 3528 ret = kvm_get_apic(cpu);
b9bec74b 3529 if (ret < 0) {
f4f1110e 3530 goto out;
b9bec74b 3531 }
1bc22652 3532 ret = kvm_get_debugregs(cpu);
b9bec74b 3533 if (ret < 0) {
f4f1110e 3534 goto out;
b9bec74b 3535 }
f4f1110e
RH		 3536 ret = 0;
3537 out:
3538 cpu_sync_bndcs_hflags(&cpu->env);
3539 return ret;
05330448
AL		 3540}
3541
20d695a9 3542void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3543{
20d695a9
AF		 3544 X86CPU *x86_cpu = X86_CPU(cpu);
3545 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3546 int ret;
3547
276ce815 3548 /* Inject NMI */
fc12d72e
PB		 3549 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3550 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3551 qemu_mutex_lock_iothread();
3552 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3553 qemu_mutex_unlock_iothread();
3554 DPRINTF("injected NMI\n");
3555 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3556 if (ret < 0) {
3557 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3558 strerror(-ret));
3559 }
3560 }
3561 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3562 qemu_mutex_lock_iothread();
3563 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3564 qemu_mutex_unlock_iothread();
3565 DPRINTF("injected SMI\n");
3566 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3567 if (ret < 0) {
3568 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3569 strerror(-ret));
3570 }
ce377af3 3571 }
276ce815
LJ		 3572 }
3573
15eafc2e 3574 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3575 qemu_mutex_lock_iothread();
3576 }
3577
e0723c45
PB		 3578 /* Force the VCPU out of its inner loop to process any INIT requests
3579 * or (for userspace APIC, but it is cheap to combine the checks here)
3580 * pending TPR access reports.
3581 */
3582 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3583 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3584 !(env->hflags & HF_SMM_MASK)) {
3585 cpu->exit_request = 1;
3586 }
3587 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3588 cpu->exit_request = 1;
3589 }
e0723c45 3590 }
05330448 3591
15eafc2e 3592 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3593 /* Try to inject an interrupt if the guest can accept it */
3594 if (run->ready_for_interrupt_injection &&
259186a7 3595 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3596 (env->eflags & IF_MASK)) {
3597 int irq;
3598
259186a7 3599 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3600 irq = cpu_get_pic_interrupt(env);
3601 if (irq >= 0) {
3602 struct kvm_interrupt intr;
3603
3604 intr.irq = irq;
db1669bc 3605 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3606 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3607 if (ret < 0) {
3608 fprintf(stderr,
3609 "KVM: injection failed, interrupt lost (%s)\n",
3610 strerror(-ret));
3611 }
db1669bc
JK		 3612 }
3613 }
05330448 3614
db1669bc
JK		 3615 /* If we have an interrupt but the guest is not ready to receive an
3616 * interrupt, request an interrupt window exit. This will
3617 * cause a return to userspace as soon as the guest is ready to
3618 * receive interrupts. */
259186a7 3619 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3620 run->request_interrupt_window = 1;
3621 } else {
3622 run->request_interrupt_window = 0;
3623 }
3624
3625 DPRINTF("setting tpr\n");
02e51483 3626 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3627
3628 qemu_mutex_unlock_iothread();
db1669bc 3629 }
05330448
AL		 3630}
3631
4c663752 3632MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3633{
20d695a9
AF		 3634 X86CPU *x86_cpu = X86_CPU(cpu);
3635 CPUX86State *env = &x86_cpu->env;
3636
fc12d72e
PB		 3637 if (run->flags & KVM_RUN_X86_SMM) {
3638 env->hflags |= HF_SMM_MASK;
3639 } else {
f5c052b9 3640 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3641 }
b9bec74b 3642 if (run->if_flag) {
05330448 3643 env->eflags |= IF_MASK;
b9bec74b 3644 } else {
05330448 3645 env->eflags &= ~IF_MASK;
b9bec74b 3646 }
4b8523ee
JK		 3647
3648 /* We need to protect the apic state against concurrent accesses from
3649 * different threads in case the userspace irqchip is used. */
3650 if (!kvm_irqchip_in_kernel()) {
3651 qemu_mutex_lock_iothread();
3652 }
02e51483
CF		 3653 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3654 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3655 if (!kvm_irqchip_in_kernel()) {
3656 qemu_mutex_unlock_iothread();
3657 }
f794aa4a 3658 return cpu_get_mem_attrs(env);
05330448
AL		 3659}
3660
20d695a9 3661int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3662{
20d695a9
AF		 3663 X86CPU *cpu = X86_CPU(cs);
3664 CPUX86State *env = &cpu->env;
232fc23b 3665
259186a7 3666 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3667 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3668 assert(env->mcg_cap);
3669
259186a7 3670 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3671
dd1750d7 3672 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3673
3674 if (env->exception_injected == EXCP08_DBLE) {
3675 /* this means triple fault */
cf83f140 3676 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3677 cs->exit_request = 1;
ab443475
JK		 3678 return 0;
3679 }
3680 env->exception_injected = EXCP12_MCHK;
3681 env->has_error_code = 0;
3682
259186a7 3683 cs->halted = 0;
ab443475
JK		 3684 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3685 env->mp_state = KVM_MP_STATE_RUNNABLE;
3686 }
3687 }
3688
fc12d72e
PB		 3689 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3690 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3691 kvm_cpu_synchronize_state(cs);
3692 do_cpu_init(cpu);
3693 }
3694
db1669bc
JK		 3695 if (kvm_irqchip_in_kernel()) {
3696 return 0;
3697 }
3698
259186a7
AF		 3699 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3700 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3701 apic_poll_irq(cpu->apic_state);
5d62c43a 3702 }
259186a7 3703 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3704 (env->eflags & IF_MASK)) ||
259186a7
AF		 3705 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3706 cs->halted = 0;
6792a57b 3707 }
259186a7 3708 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3709 kvm_cpu_synchronize_state(cs);
232fc23b 3710 do_cpu_sipi(cpu);
0af691d7 3711 }
259186a7
AF		 3712 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3713 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3714 kvm_cpu_synchronize_state(cs);
02e51483 3715 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3716 env->tpr_access_type);
3717 }
0af691d7 3718
259186a7 3719 return cs->halted;
0af691d7
MT		 3720}
3721
839b5630 3722static int kvm_handle_halt(X86CPU *cpu)
05330448 3723{
259186a7 3724 CPUState *cs = CPU(cpu);
839b5630
AF		 3725 CPUX86State *env = &cpu->env;
3726
259186a7 3727 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3728 (env->eflags & IF_MASK)) &&
259186a7
AF		 3729 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3730 cs->halted = 1;
bb4ea393 3731 return EXCP_HLT;
05330448
AL		 3732 }
3733
bb4ea393 3734 return 0;
05330448
AL		 3735}
3736
f7575c96 3737static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3738{
f7575c96
AF		 3739 CPUState *cs = CPU(cpu);
3740 struct kvm_run *run = cs->kvm_run;
d362e757 3741
02e51483 3742 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3743 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3744 : TPR_ACCESS_READ);
3745 return 1;
3746}
3747
f17ec444 3748int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3749{
38972938 3750 static const uint8_t int3 = 0xcc;
64bf3f4e 3751
f17ec444
AF		 3752 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3753 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3754 return -EINVAL;
b9bec74b 3755 }
e22a25c9
AL		 3756 return 0;
3757}
3758
f17ec444 3759int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3760{
3761 uint8_t int3;
3762
f17ec444
AF		 3763 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3764 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3765 return -EINVAL;
b9bec74b 3766 }
e22a25c9
AL		 3767 return 0;
3768}
3769
3770static struct {
3771 target_ulong addr;
3772 int len;
3773 int type;
3774} hw_breakpoint[4];
3775
3776static int nb_hw_breakpoint;
3777
3778static int find_hw_breakpoint(target_ulong addr, int len, int type)
3779{
3780 int n;
3781
b9bec74b 3782 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3783 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3784 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3785 return n;
b9bec74b
JK		 3786 }
3787 }
e22a25c9
AL		 3788 return -1;
3789}
3790
3791int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3792 target_ulong len, int type)
3793{
3794 switch (type) {
3795 case GDB_BREAKPOINT_HW:
3796 len = 1;
3797 break;
3798 case GDB_WATCHPOINT_WRITE:
3799 case GDB_WATCHPOINT_ACCESS:
3800 switch (len) {
3801 case 1:
3802 break;
3803 case 2:
3804 case 4:
3805 case 8:
b9bec74b 3806 if (addr & (len - 1)) {
e22a25c9 3807 return -EINVAL;
b9bec74b 3808 }
e22a25c9
AL		 3809 break;
3810 default:
3811 return -EINVAL;
3812 }
3813 break;
3814 default:
3815 return -ENOSYS;
3816 }
3817
b9bec74b 3818 if (nb_hw_breakpoint == 4) {
e22a25c9 3819 return -ENOBUFS;
b9bec74b
JK		 3820 }
3821 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3822 return -EEXIST;
b9bec74b 3823 }
e22a25c9
AL		 3824 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3825 hw_breakpoint[nb_hw_breakpoint].len = len;
3826 hw_breakpoint[nb_hw_breakpoint].type = type;
3827 nb_hw_breakpoint++;
3828
3829 return 0;
3830}
3831
3832int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3833 target_ulong len, int type)
3834{
3835 int n;
3836
3837 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3838 if (n < 0) {
e22a25c9 3839 return -ENOENT;
b9bec74b 3840 }
e22a25c9
AL		 3841 nb_hw_breakpoint--;
3842 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3843
3844 return 0;
3845}
3846
3847void kvm_arch_remove_all_hw_breakpoints(void)
3848{
3849 nb_hw_breakpoint = 0;
3850}
3851
3852static CPUWatchpoint hw_watchpoint;
3853
a60f24b5 3854static int kvm_handle_debug(X86CPU *cpu,
48405526 3855 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3856{
ed2803da 3857 CPUState *cs = CPU(cpu);
a60f24b5 3858 CPUX86State *env = &cpu->env;
f2574737 3859 int ret = 0;
e22a25c9
AL		 3860 int n;
3861
3862 if (arch_info->exception == 1) {
3863 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3864 if (cs->singlestep_enabled) {
f2574737 3865 ret = EXCP_DEBUG;
b9bec74b 3866 }
e22a25c9 3867 } else {
b9bec74b
JK		 3868 for (n = 0; n < 4; n++) {
3869 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3870 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3871 case 0x0:
f2574737 3872 ret = EXCP_DEBUG;
e22a25c9
AL		 3873 break;
3874 case 0x1:
f2574737 3875 ret = EXCP_DEBUG;
ff4700b0 3876 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3877 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3878 hw_watchpoint.flags = BP_MEM_WRITE;
3879 break;
3880 case 0x3:
f2574737 3881 ret = EXCP_DEBUG;
ff4700b0 3882 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3883 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3884 hw_watchpoint.flags = BP_MEM_ACCESS;
3885 break;
3886 }
b9bec74b
JK		 3887 }
3888 }
e22a25c9 3889 }
ff4700b0 3890 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3891 ret = EXCP_DEBUG;
b9bec74b 3892 }
f2574737 3893 if (ret == 0) {
ff4700b0 3894 cpu_synchronize_state(cs);
48405526 3895 assert(env->exception_injected == -1);
b0b1d690 3896
f2574737 3897 /* pass to guest */
48405526
BS		 3898 env->exception_injected = arch_info->exception;
3899 env->has_error_code = 0;
b0b1d690 3900 }
e22a25c9 3901
f2574737 3902 return ret;
e22a25c9
AL		 3903}
3904
20d695a9 3905void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3906{
3907 const uint8_t type_code[] = {
3908 [GDB_BREAKPOINT_HW] = 0x0,
3909 [GDB_WATCHPOINT_WRITE] = 0x1,
3910 [GDB_WATCHPOINT_ACCESS] = 0x3
3911 };
3912 const uint8_t len_code[] = {
3913 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3914 };
3915 int n;
3916
a60f24b5 3917 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3918 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3919 }
e22a25c9
AL		 3920 if (nb_hw_breakpoint > 0) {
3921 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3922 dbg->arch.debugreg[7] = 0x0600;
3923 for (n = 0; n < nb_hw_breakpoint; n++) {
3924 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3925 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3926 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3927 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3928 }
3929 }
3930}
4513d923 3931
2a4dac83
JK		 3932static bool host_supports_vmx(void)
3933{
3934 uint32_t ecx, unused;
3935
3936 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3937 return ecx & CPUID_EXT_VMX;
3938}
3939
3940#define VMX_INVALID_GUEST_STATE 0x80000021
3941
20d695a9 3942int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3943{
20d695a9 3944 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3945 uint64_t code;
3946 int ret;
3947
3948 switch (run->exit_reason) {
3949 case KVM_EXIT_HLT:
3950 DPRINTF("handle_hlt\n");
4b8523ee 3951 qemu_mutex_lock_iothread();
839b5630 3952 ret = kvm_handle_halt(cpu);
4b8523ee 3953 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3954 break;
3955 case KVM_EXIT_SET_TPR:
3956 ret = 0;
3957 break;
d362e757 3958 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3959 qemu_mutex_lock_iothread();
f7575c96 3960 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3961 qemu_mutex_unlock_iothread();
d362e757 3962 break;
2a4dac83
JK		 3963 case KVM_EXIT_FAIL_ENTRY:
3964 code = run->fail_entry.hardware_entry_failure_reason;
3965 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3966 code);
3967 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3968 fprintf(stderr,
12619721 3969 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3970 "unrestricted mode\n"
3971 "support, the failure can be most likely due to the guest "
3972 "entering an invalid\n"
3973 "state for Intel VT. For example, the guest maybe running "
3974 "in big real mode\n"
3975 "which is not supported on less recent Intel processors."
3976 "\n\n");
3977 }
3978 ret = -1;
3979 break;
3980 case KVM_EXIT_EXCEPTION:
3981 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3982 run->ex.exception, run->ex.error_code);
3983 ret = -1;
3984 break;
f2574737
JK		 3985 case KVM_EXIT_DEBUG:
3986 DPRINTF("kvm_exit_debug\n");
4b8523ee 3987 qemu_mutex_lock_iothread();
a60f24b5 3988 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3989 qemu_mutex_unlock_iothread();
f2574737 3990 break;
50efe82c
AS		 3991 case KVM_EXIT_HYPERV:
3992 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3993 break;
15eafc2e
PB		 3994 case KVM_EXIT_IOAPIC_EOI:
3995 ioapic_eoi_broadcast(run->eoi.vector);
3996 ret = 0;
3997 break;
2a4dac83
JK		 3998 default:
3999 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4000 ret = -1;
4001 break;
4002 }
4003
4004 return ret;
4005}
4006
20d695a9 4007bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4008{
20d695a9
AF		 4009 X86CPU *cpu = X86_CPU(cs);
4010 CPUX86State *env = &cpu->env;
4011
dd1750d7 4012 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4013 return !(env->cr[0] & CR0_PE_MASK) ||
4014 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4015}
84b058d7
JK		 4016
4017void kvm_arch_init_irq_routing(KVMState *s)
4018{
4019 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4020 /* If kernel can't do irq routing, interrupt source
4021 * override 0->2 cannot be set up as required by HPET.
4022 * So we have to disable it.
4023 */
4024 no_hpet = 1;
4025 }
cc7e0ddf 4026 /* We know at this point that we're using the in-kernel
614e41bc 4027 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4028 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4029 */
614e41bc 4030 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4031 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4032
4033 if (kvm_irqchip_is_split()) {
4034 int i;
4035
4036 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4037 MSI routes for signaling interrupts to the local apics. */
4038 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4039 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4040 error_report("Could not enable split IRQ mode.");
4041 exit(1);
4042 }
4043 }
4044 }
4045}
4046
4047int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4048{
4049 int ret;
4050 if (machine_kernel_irqchip_split(ms)) {
4051 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4052 if (ret) {
df3c286c 4053 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4054 strerror(-ret));
4055 exit(1);
4056 } else {
4057 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4058 kvm_split_irqchip = true;
4059 return 1;
4060 }
4061 } else {
4062 return 0;
4063 }
84b058d7 4064}
b139bd30
JK		 4065
4066/* Classic KVM device assignment interface. Will remain x86 only. */
4067int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4068 uint32_t flags, uint32_t *dev_id)
4069{
4070 struct kvm_assigned_pci_dev dev_data = {
4071 .segnr = dev_addr->domain,
4072 .busnr = dev_addr->bus,
4073 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4074 .flags = flags,
4075 };
4076 int ret;
4077
4078 dev_data.assigned_dev_id =
4079 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4080
4081 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4082 if (ret < 0) {
4083 return ret;
4084 }
4085
4086 *dev_id = dev_data.assigned_dev_id;
4087
4088 return 0;
4089}
4090
4091int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4092{
4093 struct kvm_assigned_pci_dev dev_data = {
4094 .assigned_dev_id = dev_id,
4095 };
4096
4097 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4098}
4099
4100static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4101 uint32_t irq_type, uint32_t guest_irq)
4102{
4103 struct kvm_assigned_irq assigned_irq = {
4104 .assigned_dev_id = dev_id,
4105 .guest_irq = guest_irq,
4106 .flags = irq_type,
4107 };
4108
4109 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4110 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4111 } else {
4112 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4113 }
4114}
4115
4116int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4117 uint32_t guest_irq)
4118{
4119 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4120 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4121
4122 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4123}
4124
4125int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4126{
4127 struct kvm_assigned_pci_dev dev_data = {
4128 .assigned_dev_id = dev_id,
4129 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4130 };
4131
4132 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4133}
4134
4135static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4136 uint32_t type)
4137{
4138 struct kvm_assigned_irq assigned_irq = {
4139 .assigned_dev_id = dev_id,
4140 .flags = type,
4141 };
4142
4143 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4144}
4145
4146int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4147{
4148 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4149 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4150}
4151
4152int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4153{
4154 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4155 KVM_DEV_IRQ_GUEST_MSI, virq);
4156}
4157
4158int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4159{
4160 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4161 KVM_DEV_IRQ_HOST_MSI);
4162}
4163
4164bool kvm_device_msix_supported(KVMState *s)
4165{
4166 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4167 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4168 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4169}
4170
4171int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4172 uint32_t nr_vectors)
4173{
4174 struct kvm_assigned_msix_nr msix_nr = {
4175 .assigned_dev_id = dev_id,
4176 .entry_nr = nr_vectors,
4177 };
4178
4179 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4180}
4181
4182int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4183 int virq)
4184{
4185 struct kvm_assigned_msix_entry msix_entry = {
4186 .assigned_dev_id = dev_id,
4187 .gsi = virq,
4188 .entry = vector,
4189 };
4190
4191 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4192}
4193
4194int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4195{
4196 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4197 KVM_DEV_IRQ_GUEST_MSIX, 0);
4198}
4199
4200int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4201{
4202 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4203 KVM_DEV_IRQ_HOST_MSIX);
4204}
9e03a040
FB		 4205
4206int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4207 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4208{
8b5ed7df
PX		 4209 X86IOMMUState *iommu = x86_iommu_get_default();
4210
4211 if (iommu) {
4212 int ret;
4213 MSIMessage src, dst;
4214 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4215
0ea1472d
JK		 4216 if (!class->int_remap) {
4217 return 0;
4218 }
4219
8b5ed7df
PX		 4220 src.address = route->u.msi.address_hi;
4221 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4222 src.address |= route->u.msi.address_lo;
4223 src.data = route->u.msi.data;
4224
4225 ret = class->int_remap(iommu, &src, &dst, dev ? \
4226 pci_requester_id(dev) : \
4227 X86_IOMMU_SID_INVALID);
4228 if (ret) {
4229 trace_kvm_x86_fixup_msi_error(route->gsi);
4230 return 1;
4231 }
4232
4233 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4234 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4235 route->u.msi.data = dst.data;
4236 }
4237
9e03a040
FB		 4238 return 0;
4239}
1850b6b7 4240
38d87493
PX		 4241typedef struct MSIRouteEntry MSIRouteEntry;
4242
4243struct MSIRouteEntry {
4244 PCIDevice *dev; /* Device pointer */
4245 int vector; /* MSI/MSIX vector index */
4246 int virq; /* Virtual IRQ index */
4247 QLIST_ENTRY(MSIRouteEntry) list;
4248};
4249
4250/* List of used GSI routes */
4251static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4252 QLIST_HEAD_INITIALIZER(msi_route_list);
4253
e1d4fb2d
PX		 4254static void kvm_update_msi_routes_all(void *private, bool global,
4255 uint32_t index, uint32_t mask)
4256{
a56de056 4257 int cnt = 0, vector;
e1d4fb2d
PX		 4258 MSIRouteEntry *entry;
4259 MSIMessage msg;
fd563564
PX		 4260 PCIDevice *dev;
4261
e1d4fb2d
PX		 4262 /* TODO: explicit route update */
4263 QLIST_FOREACH(entry, &msi_route_list, list) {
4264 cnt++;
a56de056 4265 vector = entry->vector;
fd563564 4266 dev = entry->dev;
a56de056
PX		 4267 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4268 msg = msix_get_message(dev, vector);
4269 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4270 msg = msi_get_message(dev, vector);
4271 } else {
4272 /*
4273 * Either MSI/MSIX is disabled for the device, or the
4274 * specific message was masked out. Skip this one.
4275 */
fd563564
PX		 4276 continue;
4277 }
fd563564 4278 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4279 }
3f1fea0f 4280 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4281 trace_kvm_x86_update_msi_routes(cnt);
4282}
4283
38d87493
PX		 4284int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4285 int vector, PCIDevice *dev)
4286{
e1d4fb2d 4287 static bool notify_list_inited = false;
38d87493
PX		 4288 MSIRouteEntry *entry;
4289
4290 if (!dev) {
4291 /* These are (possibly) IOAPIC routes only used for split
4292 * kernel irqchip mode, while what we are housekeeping are
4293 * PCI devices only. */
4294 return 0;
4295 }
4296
4297 entry = g_new0(MSIRouteEntry, 1);
4298 entry->dev = dev;
4299 entry->vector = vector;
4300 entry->virq = route->gsi;
4301 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4302
4303 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4304
4305 if (!notify_list_inited) {
4306 /* For the first time we do add route, add ourselves into
4307 * IOMMU's IEC notify list if needed. */
4308 X86IOMMUState *iommu = x86_iommu_get_default();
4309 if (iommu) {
4310 x86_iommu_iec_register_notifier(iommu,
4311 kvm_update_msi_routes_all,
4312 NULL);
4313 }
4314 notify_list_inited = true;
4315 }
38d87493
PX		 4316 return 0;
4317}
4318
4319int kvm_arch_release_virq_post(int virq)
4320{
4321 MSIRouteEntry *entry, *next;
4322 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4323 if (entry->virq == virq) {
4324 trace_kvm_x86_remove_msi_route(virq);
4325 QLIST_REMOVE(entry, list);
01960e6d 4326 g_free(entry);
38d87493
PX		 4327 break;
4328 }
4329 }
9e03a040
FB		 4330 return 0;
4331}
1850b6b7
EA		 4332
4333int kvm_arch_msi_data_to_gsi(uint32_t data)
4334{
4335 abort();
4336}
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