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[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448
AL		 22
23#include "qemu-common.h"
33c11879 24#include "cpu.h"
9c17d615 25#include "sysemu/sysemu.h"
b3946626 26#include "sysemu/hw_accel.h"
6410848b 27#include "sysemu/kvm_int.h"
1d31f66b 28#include "kvm_i386.h"
50efe82c 29#include "hyperv.h"
5e953812 30#include "hyperv-proto.h"
50efe82c 31
022c62cb 32#include "exec/gdbstub.h"
1de7afc9
PB		 33#include "qemu/host-utils.h"
34#include "qemu/config-file.h"
1c4a55db 35#include "qemu/error-report.h"
0d09e41a
PB		 36#include "hw/i386/pc.h"
37#include "hw/i386/apic.h"
e0723c45
PB		 38#include "hw/i386/apic_internal.h"
39#include "hw/i386/apic-msidef.h"
8b5ed7df 40#include "hw/i386/intel_iommu.h"
e1d4fb2d 41#include "hw/i386/x86-iommu.h"
50efe82c 42
a2cb15b0 43#include "hw/pci/pci.h"
15eafc2e 44#include "hw/pci/msi.h"
fd563564 45#include "hw/pci/msix.h"
795c40b8 46#include "migration/blocker.h"
4c663752 47#include "exec/memattrs.h"
8b5ed7df 48#include "trace.h"
05330448
AL		 49
50//#define DEBUG_KVM
51
52#ifdef DEBUG_KVM
8c0d577e 53#define DPRINTF(fmt, ...) \
05330448
AL		 54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55#else
8c0d577e 56#define DPRINTF(fmt, ...) \
05330448
AL		 57 do { } while (0)
58#endif
59
1a03675d
GC		 60#define MSR_KVM_WALL_CLOCK 0x11
61#define MSR_KVM_SYSTEM_TIME 0x12
62
d1138251
EH		 63/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65#define MSR_BUF_SIZE 4096
d71b62a1 66
94a8d39a
JK		 67const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72};
25d2e361 73
c3a3a7d3
JK		 74static bool has_msr_star;
75static bool has_msr_hsave_pa;
c9b8f6b6 76static bool has_msr_tsc_aux;
f28558d3 77static bool has_msr_tsc_adjust;
aa82ba54 78static bool has_msr_tsc_deadline;
df67696e 79static bool has_msr_feature_control;
21e87c46 80static bool has_msr_misc_enable;
fc12d72e 81static bool has_msr_smbase;
79e9ebeb 82static bool has_msr_bndcfgs;
25d2e361 83static int lm_capable_kernel;
7bc3d711 84static bool has_msr_hv_hypercall;
f2a53c9e 85static bool has_msr_hv_crash;
744b8a94 86static bool has_msr_hv_reset;
8c145d7c 87static bool has_msr_hv_vpindex;
e9688fab 88static bool hv_vpindex_settable;
46eb8f98 89static bool has_msr_hv_runtime;
866eea9a 90static bool has_msr_hv_synic;
ff99aa64 91static bool has_msr_hv_stimer;
d72bc7f6 92static bool has_msr_hv_frequencies;
ba6a4fd9 93static bool has_msr_hv_reenlightenment;
18cd2c17 94static bool has_msr_xss;
a33a2cfe 95static bool has_msr_spec_ctrl;
cfeea0c0 96static bool has_msr_virt_ssbd;
e13713db 97static bool has_msr_smi_count;
b827df58 98
0b368a10
JD		 99static uint32_t has_architectural_pmu_version;
100static uint32_t num_architectural_pmu_gp_counters;
101static uint32_t num_architectural_pmu_fixed_counters;
0d894367 102
28143b40
TH		 103static int has_xsave;
104static int has_xcrs;
105static int has_pit_state2;
106
87f8b626
AR		 107static bool has_msr_mcg_ext_ctl;
108
494e95e9
CP		 109static struct kvm_cpuid2 *cpuid_cache;
110
28143b40
TH		 111int kvm_has_pit_state2(void)
112{
113 return has_pit_state2;
114}
115
355023f2
PB		 116bool kvm_has_smm(void)
117{
118 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
119}
120
6053a86f
MT		 121bool kvm_has_adjust_clock_stable(void)
122{
123 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
124
125 return (ret == KVM_CLOCK_TSC_STABLE);
126}
127
1d31f66b
PM		 128bool kvm_allows_irq0_override(void)
129{
130 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
131}
132
fb506e70
RK		 133static bool kvm_x2apic_api_set_flags(uint64_t flags)
134{
135 KVMState *s = KVM_STATE(current_machine->accelerator);
136
137 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
138}
139
e391c009 140#define MEMORIZE(fn, _result) \
2a138ec3 141 ({ \
2a138ec3
RK		 142 static bool _memorized; \
143 \
144 if (_memorized) { \
145 return _result; \
146 } \
147 _memorized = true; \
148 _result = fn; \
149 })
150
e391c009
IM		 151static bool has_x2apic_api;
152
153bool kvm_has_x2apic_api(void)
154{
155 return has_x2apic_api;
156}
157
fb506e70
RK		 158bool kvm_enable_x2apic(void)
159{
2a138ec3
RK		 160 return MEMORIZE(
161 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 162 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
163 has_x2apic_api);
fb506e70
RK		 164}
165
e9688fab
RK		 166bool kvm_hv_vpindex_settable(void)
167{
168 return hv_vpindex_settable;
169}
170
0fd7e098
LL		 171static int kvm_get_tsc(CPUState *cs)
172{
173 X86CPU *cpu = X86_CPU(cs);
174 CPUX86State *env = &cpu->env;
175 struct {
176 struct kvm_msrs info;
177 struct kvm_msr_entry entries[1];
178 } msr_data;
179 int ret;
180
181 if (env->tsc_valid) {
182 return 0;
183 }
184
185 msr_data.info.nmsrs = 1;
186 msr_data.entries[0].index = MSR_IA32_TSC;
187 env->tsc_valid = !runstate_is_running();
188
189 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
190 if (ret < 0) {
191 return ret;
192 }
193
48e1a45c 194 assert(ret == 1);
0fd7e098
LL		 195 env->tsc = msr_data.entries[0].data;
196 return 0;
197}
198
14e6fe12 199static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 200{
0fd7e098
LL		 201 kvm_get_tsc(cpu);
202}
203
204void kvm_synchronize_all_tsc(void)
205{
206 CPUState *cpu;
207
208 if (kvm_enabled()) {
209 CPU_FOREACH(cpu) {
14e6fe12 210 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 211 }
212 }
213}
214
b827df58
AK		 215static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
216{
217 struct kvm_cpuid2 *cpuid;
218 int r, size;
219
220 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 221 cpuid = g_malloc0(size);
b827df58
AK		 222 cpuid->nent = max;
223 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 224 if (r == 0 && cpuid->nent >= max) {
225 r = -E2BIG;
226 }
b827df58
AK		 227 if (r < 0) {
228 if (r == -E2BIG) {
7267c094 229 g_free(cpuid);
b827df58
AK		 230 return NULL;
231 } else {
232 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
233 strerror(-r));
234 exit(1);
235 }
236 }
237 return cpuid;
238}
239
dd87f8a6
EH		 240/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
241 * for all entries.
242 */
243static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
244{
245 struct kvm_cpuid2 *cpuid;
246 int max = 1;
494e95e9
CP		 247
248 if (cpuid_cache != NULL) {
249 return cpuid_cache;
250 }
dd87f8a6
EH		 251 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
252 max *= 2;
253 }
494e95e9 254 cpuid_cache = cpuid;
dd87f8a6
EH		 255 return cpuid;
256}
257
a443bc34 258static const struct kvm_para_features {
0c31b744
GC		 259 int cap;
260 int feature;
261} para_features[] = {
262 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
263 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
264 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 265 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 266};
267
ba9bc59e 268static int get_para_features(KVMState *s)
0c31b744
GC		 269{
270 int i, features = 0;
271
8e03c100 272 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 273 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 274 features |= (1 << para_features[i].feature);
275 }
276 }
277
278 return features;
279}
0c31b744 280
40e80ee4
EH		 281static bool host_tsx_blacklisted(void)
282{
283 int family, model, stepping;\
284 char vendor[CPUID_VENDOR_SZ + 1];
285
286 host_vendor_fms(vendor, &family, &model, &stepping);
287
288 /* Check if we are running on a Haswell host known to have broken TSX */
289 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
290 (family == 6) &&
291 ((model == 63 && stepping < 4) ||
292 model == 60 || model == 69 || model == 70);
293}
0c31b744 294
829ae2f9
EH		 295/* Returns the value for a specific register on the cpuid entry
296 */
297static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
298{
299 uint32_t ret = 0;
300 switch (reg) {
301 case R_EAX:
302 ret = entry->eax;
303 break;
304 case R_EBX:
305 ret = entry->ebx;
306 break;
307 case R_ECX:
308 ret = entry->ecx;
309 break;
310 case R_EDX:
311 ret = entry->edx;
312 break;
313 }
314 return ret;
315}
316
4fb73f1d
EH		 317/* Find matching entry for function/index on kvm_cpuid2 struct
318 */
319static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
320 uint32_t function,
321 uint32_t index)
322{
323 int i;
324 for (i = 0; i < cpuid->nent; ++i) {
325 if (cpuid->entries[i].function == function &&
326 cpuid->entries[i].index == index) {
327 return &cpuid->entries[i];
328 }
329 }
330 /* not found: */
331 return NULL;
332}
333
ba9bc59e 334uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 335 uint32_t index, int reg)
b827df58
AK		 336{
337 struct kvm_cpuid2 *cpuid;
b827df58
AK		 338 uint32_t ret = 0;
339 uint32_t cpuid_1_edx;
8c723b79 340 bool found = false;
b827df58 341
dd87f8a6 342 cpuid = get_supported_cpuid(s);
b827df58 343
4fb73f1d
EH		 344 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
345 if (entry) {
346 found = true;
347 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 348 }
349
7b46e5ce
EH		 350 /* Fixups for the data returned by KVM, below */
351
c2acb022
EH		 352 if (function == 1 && reg == R_EDX) {
353 /* KVM before 2.6.30 misreports the following features */
354 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 355 } else if (function == 1 && reg == R_ECX) {
356 /* We can set the hypervisor flag, even if KVM does not return it on
357 * GET_SUPPORTED_CPUID
358 */
359 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 360 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
361 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
362 * and the irqchip is in the kernel.
363 */
364 if (kvm_irqchip_in_kernel() &&
365 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
366 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
367 }
41e5e76d
EH		 368
369 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
370 * without the in-kernel irqchip
371 */
372 if (!kvm_irqchip_in_kernel()) {
373 ret &= ~CPUID_EXT_X2APIC;
b827df58 374 }
2266d443
MT		 375
376 if (enable_cpu_pm) {
377 int disable_exits = kvm_check_extension(s,
378 KVM_CAP_X86_DISABLE_EXITS);
379
380 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
381 ret |= CPUID_EXT_MONITOR;
382 }
383 }
28b8e4d0
JK		 384 } else if (function == 6 && reg == R_EAX) {
385 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 386 } else if (function == 7 && index == 0 && reg == R_EBX) {
387 if (host_tsx_blacklisted()) {
388 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
389 }
f98bbd83
BM		 390 } else if (function == 0x80000001 && reg == R_ECX) {
391 /*
392 * It's safe to enable TOPOEXT even if it's not returned by
393 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
394 * us to keep CPU models including TOPOEXT runnable on older kernels.
395 */
396 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 397 } else if (function == 0x80000001 && reg == R_EDX) {
398 /* On Intel, kvm returns cpuid according to the Intel spec,
399 * so add missing bits according to the AMD spec:
400 */
401 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
402 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 403 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
404 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
405 * be enabled without the in-kernel irqchip
406 */
407 if (!kvm_irqchip_in_kernel()) {
408 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
409 }
be777326 410 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 411 ret |= 1U << KVM_HINTS_REALTIME;
be777326 412 found = 1;
b827df58
AK		 413 }
414
0c31b744 415 /* fallback for older kernels */
8c723b79 416 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 417 ret = get_para_features(s);
b9bec74b 418 }
0c31b744
GC		 419
420 return ret;
bb0300dc 421}
bb0300dc 422
3c85e74f
HY		 423typedef struct HWPoisonPage {
424 ram_addr_t ram_addr;
425 QLIST_ENTRY(HWPoisonPage) list;
426} HWPoisonPage;
427
428static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
429 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
430
431static void kvm_unpoison_all(void *param)
432{
433 HWPoisonPage *page, *next_page;
434
435 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
436 QLIST_REMOVE(page, list);
437 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 438 g_free(page);
3c85e74f
HY		 439 }
440}
441
3c85e74f
HY		 442static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
443{
444 HWPoisonPage *page;
445
446 QLIST_FOREACH(page, &hwpoison_page_list, list) {
447 if (page->ram_addr == ram_addr) {
448 return;
449 }
450 }
ab3ad07f 451 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 452 page->ram_addr = ram_addr;
453 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
454}
455
e7701825
MT		 456static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
457 int *max_banks)
458{
459 int r;
460
14a09518 461 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 462 if (r > 0) {
463 *max_banks = r;
464 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
465 }
466 return -ENOSYS;
467}
468
bee615d4 469static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 470{
87f8b626 471 CPUState *cs = CPU(cpu);
bee615d4 472 CPUX86State *env = &cpu->env;
c34d440a
JK		 473 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
474 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
475 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 476 int flags = 0;
e7701825 477
c34d440a
JK		 478 if (code == BUS_MCEERR_AR) {
479 status |= MCI_STATUS_AR | 0x134;
480 mcg_status |= MCG_STATUS_EIPV;
481 } else {
482 status |= 0xc0;
483 mcg_status |= MCG_STATUS_RIPV;
419fb20a 484 }
87f8b626
AR		 485
486 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
487 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
488 * guest kernel back into env->mcg_ext_ctl.
489 */
490 cpu_synchronize_state(cs);
491 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
492 mcg_status |= MCG_STATUS_LMCE;
493 flags = 0;
494 }
495
8c5cf3b6 496 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 497 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 498}
419fb20a
JK		 499
500static void hardware_memory_error(void)
501{
502 fprintf(stderr, "Hardware memory error!\n");
503 exit(1);
504}
505
2ae41db2 506void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 507{
20d695a9
AF		 508 X86CPU *cpu = X86_CPU(c);
509 CPUX86State *env = &cpu->env;
419fb20a 510 ram_addr_t ram_addr;
a8170e5e 511 hwaddr paddr;
419fb20a 512
4d39892c
PB		 513 /* If we get an action required MCE, it has been injected by KVM
514 * while the VM was running. An action optional MCE instead should
515 * be coming from the main thread, which qemu_init_sigbus identifies
516 * as the "early kill" thread.
517 */
a16fc07e 518 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 519
20e0ff59 520 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 521 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 522 if (ram_addr != RAM_ADDR_INVALID &&
523 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
524 kvm_hwpoison_page_add(ram_addr);
525 kvm_mce_inject(cpu, paddr, code);
2ae41db2 526 return;
419fb20a 527 }
20e0ff59
PB		 528
529 fprintf(stderr, "Hardware memory error for memory used by "
530 "QEMU itself instead of guest system!\n");
419fb20a 531 }
20e0ff59
PB		 532
533 if (code == BUS_MCEERR_AR) {
534 hardware_memory_error();
535 }
536
537 /* Hope we are lucky for AO MCE */
419fb20a
JK		 538}
539
1bc22652 540static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 541{
1bc22652
AF		 542 CPUX86State *env = &cpu->env;
543
ab443475
JK		 544 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
545 unsigned int bank, bank_num = env->mcg_cap & 0xff;
546 struct kvm_x86_mce mce;
547
548 env->exception_injected = -1;
549
550 /*
551 * There must be at least one bank in use if an MCE is pending.
552 * Find it and use its values for the event injection.
553 */
554 for (bank = 0; bank < bank_num; bank++) {
555 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
556 break;
557 }
558 }
559 assert(bank < bank_num);
560
561 mce.bank = bank;
562 mce.status = env->mce_banks[bank * 4 + 1];
563 mce.mcg_status = env->mcg_status;
564 mce.addr = env->mce_banks[bank * 4 + 2];
565 mce.misc = env->mce_banks[bank * 4 + 3];
566
1bc22652 567 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 568 }
ab443475
JK		 569 return 0;
570}
571
1dfb4dd9 572static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 573{
317ac620 574 CPUX86State *env = opaque;
b8cc45d6
GC		 575
576 if (running) {
577 env->tsc_valid = false;
578 }
579}
580
83b17af5 581unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 582{
83b17af5 583 X86CPU *cpu = X86_CPU(cs);
7e72a45c 584 return cpu->apic_id;
b164e48e
EH		 585}
586
92067bf4
IM		 587#ifndef KVM_CPUID_SIGNATURE_NEXT
588#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
589#endif
590
591static bool hyperv_hypercall_available(X86CPU *cpu)
592{
593 return cpu->hyperv_vapic ||
594 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
595}
596
597static bool hyperv_enabled(X86CPU *cpu)
598{
7bc3d711
PB		 599 CPUState *cs = CPU(cpu);
600 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
601 (hyperv_hypercall_available(cpu) ||
48a5f3bc 602 cpu->hyperv_time ||
f2a53c9e 603 cpu->hyperv_relaxed_timing ||
744b8a94 604 cpu->hyperv_crash ||
8c145d7c 605 cpu->hyperv_reset ||
46eb8f98 606 cpu->hyperv_vpindex ||
866eea9a 607 cpu->hyperv_runtime ||
ff99aa64 608 cpu->hyperv_synic ||
ba6a4fd9 609 cpu->hyperv_stimer ||
47512009
VK		 610 cpu->hyperv_reenlightenment ||
611 cpu->hyperv_tlbflush);
92067bf4
IM		 612}
613
5031283d
HZ		 614static int kvm_arch_set_tsc_khz(CPUState *cs)
615{
616 X86CPU *cpu = X86_CPU(cs);
617 CPUX86State *env = &cpu->env;
618 int r;
619
620 if (!env->tsc_khz) {
621 return 0;
622 }
623
624 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
625 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
626 -ENOTSUP;
627 if (r < 0) {
628 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
629 * TSC frequency doesn't match the one we want.
630 */
631 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
632 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
633 -ENOTSUP;
634 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 635 warn_report("TSC frequency mismatch between "
636 "VM (%" PRId64 " kHz) and host (%d kHz), "
637 "and TSC scaling unavailable",
638 env->tsc_khz, cur_freq);
5031283d
HZ		 639 return r;
640 }
641 }
642
643 return 0;
644}
645
4bb95b82
LP		 646static bool tsc_is_stable_and_known(CPUX86State *env)
647{
648 if (!env->tsc_khz) {
649 return false;
650 }
651 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
652 || env->user_tsc_khz;
653}
654
c35bd19a
EY		 655static int hyperv_handle_properties(CPUState *cs)
656{
657 X86CPU *cpu = X86_CPU(cs);
658 CPUX86State *env = &cpu->env;
659
660 if (cpu->hyperv_relaxed_timing) {
5e953812 661 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a
EY		 662 }
663 if (cpu->hyperv_vapic) {
5e953812
RK		 664 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
665 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 666 }
3ddcd2ed 667 if (cpu->hyperv_time) {
1221f150
RK		 668 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
669 fprintf(stderr, "Hyper-V clocksources "
670 "(requested by 'hv-time' cpu flag) "
671 "are not supported by kernel\n");
672 return -ENOSYS;
673 }
5e953812
RK		 674 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
675 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
676 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
9445597b
RK		 677 }
678 if (cpu->hyperv_frequencies) {
679 if (!has_msr_hv_frequencies) {
680 fprintf(stderr, "Hyper-V frequency MSRs "
681 "(requested by 'hv-frequencies' cpu flag) "
682 "are not supported by kernel\n");
683 return -ENOSYS;
d72bc7f6 684 }
9445597b
RK		 685 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
686 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 687 }
1221f150
RK		 688 if (cpu->hyperv_crash) {
689 if (!has_msr_hv_crash) {
690 fprintf(stderr, "Hyper-V crash MSRs "
691 "(requested by 'hv-crash' cpu flag) "
692 "are not supported by kernel\n");
693 return -ENOSYS;
694 }
5e953812 695 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 696 }
ba6a4fd9
VK		 697 if (cpu->hyperv_reenlightenment) {
698 if (!has_msr_hv_reenlightenment) {
699 fprintf(stderr,
700 "Hyper-V Reenlightenment MSRs "
701 "(requested by 'hv-reenlightenment' cpu flag) "
702 "are not supported by kernel\n");
703 return -ENOSYS;
704 }
705 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
706 }
5e953812 707 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1221f150
RK		 708 if (cpu->hyperv_reset) {
709 if (!has_msr_hv_reset) {
710 fprintf(stderr, "Hyper-V reset MSR "
711 "(requested by 'hv-reset' cpu flag) "
712 "is not supported by kernel\n");
713 return -ENOSYS;
714 }
5e953812 715 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a 716 }
1221f150
RK		 717 if (cpu->hyperv_vpindex) {
718 if (!has_msr_hv_vpindex) {
719 fprintf(stderr, "Hyper-V VP_INDEX MSR "
720 "(requested by 'hv-vpindex' cpu flag) "
721 "is not supported by kernel\n");
722 return -ENOSYS;
723 }
5e953812 724 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a 725 }
1221f150
RK		 726 if (cpu->hyperv_runtime) {
727 if (!has_msr_hv_runtime) {
728 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
729 "(requested by 'hv-runtime' cpu flag) "
730 "is not supported by kernel\n");
731 return -ENOSYS;
732 }
5e953812 733 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a
EY		 734 }
735 if (cpu->hyperv_synic) {
c35bd19a
EY		 736 if (!has_msr_hv_synic ||
737 kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_SYNIC, 0)) {
738 fprintf(stderr, "Hyper-V SynIC is not supported by kernel\n");
739 return -ENOSYS;
740 }
741
5e953812 742 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a
EY		 743 }
744 if (cpu->hyperv_stimer) {
745 if (!has_msr_hv_stimer) {
746 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
747 return -ENOSYS;
748 }
5e953812 749 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a
EY		 750 }
751 return 0;
752}
753
e9688fab
RK		 754static int hyperv_init_vcpu(X86CPU *cpu)
755{
756 if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
757 /*
758 * the kernel doesn't support setting vp_index; assert that its value
759 * is in sync
760 */
761 int ret;
762 struct {
763 struct kvm_msrs info;
764 struct kvm_msr_entry entries[1];
765 } msr_data = {
766 .info.nmsrs = 1,
767 .entries[0].index = HV_X64_MSR_VP_INDEX,
768 };
769
770 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
771 if (ret < 0) {
772 return ret;
773 }
774 assert(ret == 1);
775
776 if (msr_data.entries[0].data != hyperv_vp_index(cpu)) {
777 error_report("kernel's vp_index != QEMU's vp_index");
778 return -ENXIO;
779 }
780 }
781
782 return 0;
783}
784
68bfd0ad
MT		 785static Error *invtsc_mig_blocker;
786
f8bb0565 787#define KVM_MAX_CPUID_ENTRIES 100
0893d460 788
20d695a9 789int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 790{
791 struct {
486bd5a2 792 struct kvm_cpuid2 cpuid;
f8bb0565 793 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
541dc0d4 794 } QEMU_PACKED cpuid_data;
20d695a9
AF		 795 X86CPU *cpu = X86_CPU(cs);
796 CPUX86State *env = &cpu->env;
486bd5a2 797 uint32_t limit, i, j, cpuid_i;
a33609ca 798 uint32_t unused;
bb0300dc 799 struct kvm_cpuid_entry2 *c;
bb0300dc 800 uint32_t signature[3];
234cc647 801 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 802 int r;
fe44dc91 803 Error *local_err = NULL;
05330448 804
ef4cbe14
SW		 805 memset(&cpuid_data, 0, sizeof(cpuid_data));
806
05330448
AL		 807 cpuid_i = 0;
808
ddb98b5a
LP		 809 r = kvm_arch_set_tsc_khz(cs);
810 if (r < 0) {
811 goto fail;
812 }
813
814 /* vcpu's TSC frequency is either specified by user, or following
815 * the value used by KVM if the former is not present. In the
816 * latter case, we query it from KVM and record in env->tsc_khz,
817 * so that vcpu's TSC frequency can be migrated later via this field.
818 */
819 if (!env->tsc_khz) {
820 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
821 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
822 -ENOTSUP;
823 if (r > 0) {
824 env->tsc_khz = r;
825 }
826 }
827
bb0300dc 828 /* Paravirtualization CPUIDs */
234cc647
PB		 829 if (hyperv_enabled(cpu)) {
830 c = &cpuid_data.entries[cpuid_i++];
5e953812 831 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 832 if (!cpu->hyperv_vendor_id) {
833 memcpy(signature, "Microsoft Hv", 12);
834 } else {
835 size_t len = strlen(cpu->hyperv_vendor_id);
836
837 if (len > 12) {
838 error_report("hv-vendor-id truncated to 12 characters");
839 len = 12;
840 }
841 memset(signature, 0, 12);
842 memcpy(signature, cpu->hyperv_vendor_id, len);
843 }
5e953812 844 c->eax = HV_CPUID_MIN;
234cc647
PB		 845 c->ebx = signature[0];
846 c->ecx = signature[1];
847 c->edx = signature[2];
0c31b744 848
234cc647 849 c = &cpuid_data.entries[cpuid_i++];
5e953812 850 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 851 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
852 c->eax = signature[0];
234cc647
PB		 853 c->ebx = 0;
854 c->ecx = 0;
855 c->edx = 0;
eab70139
VR		 856
857 c = &cpuid_data.entries[cpuid_i++];
5e953812 858 c->function = HV_CPUID_VERSION;
eab70139
VR		 859 c->eax = 0x00001bbc;
860 c->ebx = 0x00060001;
861
862 c = &cpuid_data.entries[cpuid_i++];
5e953812 863 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 864 r = hyperv_handle_properties(cs);
865 if (r) {
866 return r;
46eb8f98 867 }
c35bd19a
EY		 868 c->eax = env->features[FEAT_HYPERV_EAX];
869 c->ebx = env->features[FEAT_HYPERV_EBX];
870 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 871
eab70139 872 c = &cpuid_data.entries[cpuid_i++];
5e953812 873 c->function = HV_CPUID_ENLIGHTMENT_INFO;
92067bf4 874 if (cpu->hyperv_relaxed_timing) {
5e953812 875 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
eab70139 876 }
2d5aa872 877 if (cpu->hyperv_vapic) {
5e953812 878 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
eab70139 879 }
47512009
VK		 880 if (cpu->hyperv_tlbflush) {
881 if (kvm_check_extension(cs->kvm_state,
882 KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
883 fprintf(stderr, "Hyper-V TLB flush support "
884 "(requested by 'hv-tlbflush' cpu flag) "
885 " is not supported by kernel\n");
886 return -ENOSYS;
887 }
888 c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
889 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
890 }
891
92067bf4 892 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 893
894 c = &cpuid_data.entries[cpuid_i++];
5e953812 895 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 896
897 c->eax = cpu->hv_max_vps;
eab70139
VR		 898 c->ebx = 0x40;
899
234cc647 900 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 901 has_msr_hv_hypercall = true;
eab70139
VR		 902 }
903
f522d2ac
AW		 904 if (cpu->expose_kvm) {
905 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
906 c = &cpuid_data.entries[cpuid_i++];
907 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 908 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 909 c->ebx = signature[0];
910 c->ecx = signature[1];
911 c->edx = signature[2];
234cc647 912
f522d2ac
AW		 913 c = &cpuid_data.entries[cpuid_i++];
914 c->function = KVM_CPUID_FEATURES | kvm_base;
915 c->eax = env->features[FEAT_KVM];
be777326 916 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 917 }
917367aa 918
a33609ca 919 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 920
921 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 922 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
923 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
924 abort();
925 }
bb0300dc 926 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 927
928 switch (i) {
a36b1029
AL		 929 case 2: {
930 /* Keep reading function 2 till all the input is received */
931 int times;
932
a36b1029 933 c->function = i;
a33609ca
AL		 934 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
935 KVM_CPUID_FLAG_STATE_READ_NEXT;
936 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
937 times = c->eax & 0xff;
a36b1029
AL		 938
939 for (j = 1; j < times; ++j) {
f8bb0565
IM		 940 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
941 fprintf(stderr, "cpuid_data is full, no space for "
942 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
943 abort();
944 }
a33609ca 945 c = &cpuid_data.entries[cpuid_i++];
a36b1029 946 c->function = i;
a33609ca
AL		 947 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
948 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 949 }
950 break;
951 }
486bd5a2
AL		 952 case 4:
953 case 0xb:
954 case 0xd:
955 for (j = 0; ; j++) {
31e8c696
AP		 956 if (i == 0xd && j == 64) {
957 break;
958 }
486bd5a2
AL		 959 c->function = i;
960 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
961 c->index = j;
a33609ca 962 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 963
b9bec74b 964 if (i == 4 && c->eax == 0) {
486bd5a2 965 break;
b9bec74b
JK		 966 }
967 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 968 break;
b9bec74b
JK		 969 }
970 if (i == 0xd && c->eax == 0) {
31e8c696 971 continue;
b9bec74b 972 }
f8bb0565
IM		 973 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
974 fprintf(stderr, "cpuid_data is full, no space for "
975 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
976 abort();
977 }
a33609ca 978 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 979 }
980 break;
e37a5c7f
CP		 981 case 0x14: {
982 uint32_t times;
983
984 c->function = i;
985 c->index = 0;
986 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
987 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
988 times = c->eax;
989
990 for (j = 1; j <= times; ++j) {
991 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
992 fprintf(stderr, "cpuid_data is full, no space for "
993 "cpuid(eax:0x14,ecx:0x%x)\n", j);
994 abort();
995 }
996 c = &cpuid_data.entries[cpuid_i++];
997 c->function = i;
998 c->index = j;
999 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1000 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1001 }
1002 break;
1003 }
486bd5a2 1004 default:
486bd5a2 1005 c->function = i;
a33609ca
AL		 1006 c->flags = 0;
1007 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1008 break;
1009 }
05330448 1010 }
0d894367
PB		 1011
1012 if (limit >= 0x0a) {
0b368a10 1013 uint32_t eax, edx;
0d894367 1014
0b368a10
JD		 1015 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1016
1017 has_architectural_pmu_version = eax & 0xff;
1018 if (has_architectural_pmu_version > 0) {
1019 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1020
1021 /* Shouldn't be more than 32, since that's the number of bits
1022 * available in EBX to tell us _which_ counters are available.
1023 * Play it safe.
1024 */
0b368a10
JD		 1025 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1026 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1027 }
1028
1029 if (has_architectural_pmu_version > 1) {
1030 num_architectural_pmu_fixed_counters = edx & 0x1f;
1031
1032 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1033 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1034 }
0d894367
PB		 1035 }
1036 }
1037 }
1038
a33609ca 1039 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1040
1041 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1042 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1043 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1044 abort();
1045 }
bb0300dc 1046 c = &cpuid_data.entries[cpuid_i++];
05330448 1047
8f4202fb
BM		 1048 switch (i) {
1049 case 0x8000001d:
1050 /* Query for all AMD cache information leaves */
1051 for (j = 0; ; j++) {
1052 c->function = i;
1053 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1054 c->index = j;
1055 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1056
1057 if (c->eax == 0) {
1058 break;
1059 }
1060 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1061 fprintf(stderr, "cpuid_data is full, no space for "
1062 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1063 abort();
1064 }
1065 c = &cpuid_data.entries[cpuid_i++];
1066 }
1067 break;
1068 default:
1069 c->function = i;
1070 c->flags = 0;
1071 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1072 break;
1073 }
05330448
AL		 1074 }
1075
b3baa152
BW		 1076 /* Call Centaur's CPUID instructions they are supported. */
1077 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1078 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1079
1080 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1081 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1082 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1083 abort();
1084 }
b3baa152
BW		 1085 c = &cpuid_data.entries[cpuid_i++];
1086
1087 c->function = i;
1088 c->flags = 0;
1089 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1090 }
1091 }
1092
05330448
AL		 1093 cpuid_data.cpuid.nent = cpuid_i;
1094
e7701825 1095 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1096 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1097 (CPUID_MCE | CPUID_MCA)
a60f24b5 1098 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1099 uint64_t mcg_cap, unsupported_caps;
e7701825 1100 int banks;
32a42024 1101 int ret;
e7701825 1102
a60f24b5 1103 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1104 if (ret < 0) {
1105 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1106 return ret;
e7701825 1107 }
75d49497 1108
2590f15b 1109 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1110 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1111 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1112 return -ENOTSUP;
75d49497 1113 }
49b69cbf 1114
5120901a
EH		 1115 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1116 if (unsupported_caps) {
87f8b626
AR		 1117 if (unsupported_caps & MCG_LMCE_P) {
1118 error_report("kvm: LMCE not supported");
1119 return -ENOTSUP;
1120 }
3dc6f869
AF		 1121 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1122 unsupported_caps);
5120901a
EH		 1123 }
1124
2590f15b
EH		 1125 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1126 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1127 if (ret < 0) {
1128 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1129 return ret;
1130 }
e7701825 1131 }
e7701825 1132
b8cc45d6
GC		 1133 qemu_add_vm_change_state_handler(cpu_update_state, env);
1134
df67696e
LJ		 1135 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1136 if (c) {
1137 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1138 !!(c->ecx & CPUID_EXT_SMX);
1139 }
1140
87f8b626
AR		 1141 if (env->mcg_cap & MCG_LMCE_P) {
1142 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1143 }
1144
d99569d9
EH		 1145 if (!env->user_tsc_khz) {
1146 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1147 invtsc_mig_blocker == NULL) {
1148 /* for migration */
1149 error_setg(&invtsc_mig_blocker,
1150 "State blocked by non-migratable CPU device"
1151 " (invtsc flag)");
fe44dc91
AA		 1152 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1153 if (local_err) {
1154 error_report_err(local_err);
1155 error_free(invtsc_mig_blocker);
1156 goto fail;
1157 }
d99569d9
EH		 1158 /* for savevm */
1159 vmstate_x86_cpu.unmigratable = 1;
1160 }
68bfd0ad
MT		 1161 }
1162
9954a158
PDJ		 1163 if (cpu->vmware_cpuid_freq
1164 /* Guests depend on 0x40000000 to detect this feature, so only expose
1165 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1166 && cpu->expose_kvm
1167 && kvm_base == KVM_CPUID_SIGNATURE
1168 /* TSC clock must be stable and known for this feature. */
4bb95b82 1169 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1170
1171 c = &cpuid_data.entries[cpuid_i++];
1172 c->function = KVM_CPUID_SIGNATURE | 0x10;
1173 c->eax = env->tsc_khz;
1174 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1175 * APIC_BUS_CYCLE_NS */
1176 c->ebx = 1000000;
1177 c->ecx = c->edx = 0;
1178
1179 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1180 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1181 }
1182
1183 cpuid_data.cpuid.nent = cpuid_i;
1184
1185 cpuid_data.cpuid.padding = 0;
1186 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1187 if (r) {
1188 goto fail;
1189 }
1190
28143b40 1191 if (has_xsave) {
5b8063c4 1192 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1193 }
d71b62a1 1194 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1195
273c515c
PB		 1196 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1197 has_msr_tsc_aux = false;
1198 }
d1ae67f6 1199
e9688fab
RK		 1200 r = hyperv_init_vcpu(cpu);
1201 if (r) {
1202 goto fail;
1203 }
1204
e7429073 1205 return 0;
fe44dc91
AA		 1206
1207 fail:
1208 migrate_del_blocker(invtsc_mig_blocker);
1209 return r;
05330448
AL		 1210}
1211
50a2c6e5 1212void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1213{
20d695a9 1214 CPUX86State *env = &cpu->env;
dd673288 1215
1a5e9d2f 1216 env->xcr0 = 1;
ddced198 1217 if (kvm_irqchip_in_kernel()) {
dd673288 1218 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1219 KVM_MP_STATE_UNINITIALIZED;
1220 } else {
1221 env->mp_state = KVM_MP_STATE_RUNNABLE;
1222 }
689141dd
RK		 1223
1224 if (cpu->hyperv_synic) {
1225 int i;
1226 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1227 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1228 }
1229 }
caa5af0f
JK		 1230}
1231
e0723c45
PB		 1232void kvm_arch_do_init_vcpu(X86CPU *cpu)
1233{
1234 CPUX86State *env = &cpu->env;
1235
1236 /* APs get directly into wait-for-SIPI state. */
1237 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1238 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1239 }
1240}
1241
c3a3a7d3 1242static int kvm_get_supported_msrs(KVMState *s)
05330448 1243{
75b10c43 1244 static int kvm_supported_msrs;
c3a3a7d3 1245 int ret = 0;
05330448
AL		 1246
1247 /* first time */
75b10c43 1248 if (kvm_supported_msrs == 0) {
05330448
AL		 1249 struct kvm_msr_list msr_list, *kvm_msr_list;
1250
75b10c43 1251 kvm_supported_msrs = -1;
05330448
AL		 1252
1253 /* Obtain MSR list from KVM. These are the MSRs that we must
1254 * save/restore */
4c9f7372 1255 msr_list.nmsrs = 0;
c3a3a7d3 1256 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1257 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1258 return ret;
6fb6d245 1259 }
d9db889f
JK		 1260 /* Old kernel modules had a bug and could write beyond the provided
1261 memory. Allocate at least a safe amount of 1K. */
7267c094 1262 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1263 msr_list.nmsrs *
1264 sizeof(msr_list.indices[0])));
05330448 1265
55308450 1266 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1267 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1268 if (ret >= 0) {
1269 int i;
1270
1271 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1272 switch (kvm_msr_list->indices[i]) {
1273 case MSR_STAR:
c3a3a7d3 1274 has_msr_star = true;
1d268dec
LP		 1275 break;
1276 case MSR_VM_HSAVE_PA:
c3a3a7d3 1277 has_msr_hsave_pa = true;
1d268dec
LP		 1278 break;
1279 case MSR_TSC_AUX:
c9b8f6b6 1280 has_msr_tsc_aux = true;
1d268dec
LP		 1281 break;
1282 case MSR_TSC_ADJUST:
f28558d3 1283 has_msr_tsc_adjust = true;
1d268dec
LP		 1284 break;
1285 case MSR_IA32_TSCDEADLINE:
aa82ba54 1286 has_msr_tsc_deadline = true;
1d268dec
LP		 1287 break;
1288 case MSR_IA32_SMBASE:
fc12d72e 1289 has_msr_smbase = true;
1d268dec 1290 break;
e13713db
LA		 1291 case MSR_SMI_COUNT:
1292 has_msr_smi_count = true;
1293 break;
1d268dec 1294 case MSR_IA32_MISC_ENABLE:
21e87c46 1295 has_msr_misc_enable = true;
1d268dec
LP		 1296 break;
1297 case MSR_IA32_BNDCFGS:
79e9ebeb 1298 has_msr_bndcfgs = true;
1d268dec
LP		 1299 break;
1300 case MSR_IA32_XSS:
18cd2c17 1301 has_msr_xss = true;
3c254ab8 1302 break;
1d268dec 1303 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1304 has_msr_hv_crash = true;
1d268dec
LP		 1305 break;
1306 case HV_X64_MSR_RESET:
744b8a94 1307 has_msr_hv_reset = true;
1d268dec
LP		 1308 break;
1309 case HV_X64_MSR_VP_INDEX:
8c145d7c 1310 has_msr_hv_vpindex = true;
1d268dec
LP		 1311 break;
1312 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1313 has_msr_hv_runtime = true;
1d268dec
LP		 1314 break;
1315 case HV_X64_MSR_SCONTROL:
866eea9a 1316 has_msr_hv_synic = true;
1d268dec
LP		 1317 break;
1318 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1319 has_msr_hv_stimer = true;
1d268dec 1320 break;
d72bc7f6
LP		 1321 case HV_X64_MSR_TSC_FREQUENCY:
1322 has_msr_hv_frequencies = true;
1323 break;
ba6a4fd9
VK		 1324 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1325 has_msr_hv_reenlightenment = true;
1326 break;
a33a2cfe
PB		 1327 case MSR_IA32_SPEC_CTRL:
1328 has_msr_spec_ctrl = true;
1329 break;
cfeea0c0
KRW		 1330 case MSR_VIRT_SSBD:
1331 has_msr_virt_ssbd = true;
1332 break;
ff99aa64 1333 }
05330448
AL		 1334 }
1335 }
1336
7267c094 1337 g_free(kvm_msr_list);
05330448
AL		 1338 }
1339
c3a3a7d3 1340 return ret;
05330448
AL		 1341}
1342
6410848b
PB		 1343static Notifier smram_machine_done;
1344static KVMMemoryListener smram_listener;
1345static AddressSpace smram_address_space;
1346static MemoryRegion smram_as_root;
1347static MemoryRegion smram_as_mem;
1348
1349static void register_smram_listener(Notifier *n, void *unused)
1350{
1351 MemoryRegion *smram =
1352 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1353
1354 /* Outer container... */
1355 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1356 memory_region_set_enabled(&smram_as_root, true);
1357
1358 /* ... with two regions inside: normal system memory with low
1359 * priority, and...
1360 */
1361 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1362 get_system_memory(), 0, ~0ull);
1363 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1364 memory_region_set_enabled(&smram_as_mem, true);
1365
1366 if (smram) {
1367 /* ... SMRAM with higher priority */
1368 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1369 memory_region_set_enabled(smram, true);
1370 }
1371
1372 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1373 kvm_memory_listener_register(kvm_state, &smram_listener,
1374 &smram_address_space, 1);
1375}
1376
b16565b3 1377int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1378{
11076198 1379 uint64_t identity_base = 0xfffbc000;
39d6960a 1380 uint64_t shadow_mem;
20420430 1381 int ret;
25d2e361 1382 struct utsname utsname;
20420430 1383
28143b40 1384 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1385 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1386 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1387
e9688fab
RK		 1388 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1389
c3a3a7d3 1390 ret = kvm_get_supported_msrs(s);
20420430 1391 if (ret < 0) {
20420430
SY		 1392 return ret;
1393 }
25d2e361
MT		 1394
1395 uname(&utsname);
1396 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1397
4c5b10b7 1398 /*
11076198
JK		 1399 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1400 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1401 * Since these must be part of guest physical memory, we need to allocate
1402 * them, both by setting their start addresses in the kernel and by
1403 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1404 *
1405 * Older KVM versions may not support setting the identity map base. In
1406 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1407 * size.
4c5b10b7 1408 */
11076198
JK		 1409 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1410 /* Allows up to 16M BIOSes. */
1411 identity_base = 0xfeffc000;
1412
1413 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1414 if (ret < 0) {
1415 return ret;
1416 }
4c5b10b7 1417 }
e56ff191 1418
11076198
JK		 1419 /* Set TSS base one page after EPT identity map. */
1420 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1421 if (ret < 0) {
1422 return ret;
1423 }
1424
11076198
JK		 1425 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1426 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1427 if (ret < 0) {
11076198 1428 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1429 return ret;
1430 }
3c85e74f 1431 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1432
4689b77b 1433 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1434 if (shadow_mem != -1) {
1435 shadow_mem /= 4096;
1436 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1437 if (ret < 0) {
1438 return ret;
39d6960a
JK		 1439 }
1440 }
6410848b 1441
d870cfde
GA		 1442 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1443 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1444 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1445 smram_machine_done.notify = register_smram_listener;
1446 qemu_add_machine_init_done_notifier(&smram_machine_done);
1447 }
6f131f13
MT		 1448
1449 if (enable_cpu_pm) {
1450 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1451 int ret;
1452
1453/* Work around for kernel header with a typo. TODO: fix header and drop. */
1454#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1455#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1456#endif
1457 if (disable_exits) {
1458 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1459 KVM_X86_DISABLE_EXITS_HLT |
1460 KVM_X86_DISABLE_EXITS_PAUSE);
1461 }
1462
1463 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1464 disable_exits);
1465 if (ret < 0) {
1466 error_report("kvm: guest stopping CPU not supported: %s",
1467 strerror(-ret));
1468 }
1469 }
1470
11076198 1471 return 0;
05330448 1472}
b9bec74b 1473
05330448
AL		 1474static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1475{
1476 lhs->selector = rhs->selector;
1477 lhs->base = rhs->base;
1478 lhs->limit = rhs->limit;
1479 lhs->type = 3;
1480 lhs->present = 1;
1481 lhs->dpl = 3;
1482 lhs->db = 0;
1483 lhs->s = 1;
1484 lhs->l = 0;
1485 lhs->g = 0;
1486 lhs->avl = 0;
1487 lhs->unusable = 0;
1488}
1489
1490static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1491{
1492 unsigned flags = rhs->flags;
1493 lhs->selector = rhs->selector;
1494 lhs->base = rhs->base;
1495 lhs->limit = rhs->limit;
1496 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1497 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1498 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1499 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1500 lhs->s = (flags & DESC_S_MASK) != 0;
1501 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1502 lhs->g = (flags & DESC_G_MASK) != 0;
1503 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1504 lhs->unusable = !lhs->present;
7e680753 1505 lhs->padding = 0;
05330448
AL		 1506}
1507
1508static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1509{
1510 lhs->selector = rhs->selector;
1511 lhs->base = rhs->base;
1512 lhs->limit = rhs->limit;
d45fc087
RP		 1513 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1514 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1515 (rhs->dpl << DESC_DPL_SHIFT) |
1516 (rhs->db << DESC_B_SHIFT) |
1517 (rhs->s * DESC_S_MASK) |
1518 (rhs->l << DESC_L_SHIFT) |
1519 (rhs->g * DESC_G_MASK) |
1520 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1521}
1522
1523static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1524{
b9bec74b 1525 if (set) {
05330448 1526 *kvm_reg = *qemu_reg;
b9bec74b 1527 } else {
05330448 1528 *qemu_reg = *kvm_reg;
b9bec74b 1529 }
05330448
AL		 1530}
1531
1bc22652 1532static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1533{
1bc22652 1534 CPUX86State *env = &cpu->env;
05330448
AL		 1535 struct kvm_regs regs;
1536 int ret = 0;
1537
1538 if (!set) {
1bc22652 1539 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1540 if (ret < 0) {
05330448 1541 return ret;
b9bec74b 1542 }
05330448
AL		 1543 }
1544
1545 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1546 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1547 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1548 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1549 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1550 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1551 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1552 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1553#ifdef TARGET_X86_64
1554 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1555 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1556 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1557 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1558 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1559 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1560 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1561 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1562#endif
1563
1564 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1565 kvm_getput_reg(&regs.rip, &env->eip, set);
1566
b9bec74b 1567 if (set) {
1bc22652 1568 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1569 }
05330448
AL		 1570
1571 return ret;
1572}
1573
1bc22652 1574static int kvm_put_fpu(X86CPU *cpu)
05330448 1575{
1bc22652 1576 CPUX86State *env = &cpu->env;
05330448
AL		 1577 struct kvm_fpu fpu;
1578 int i;
1579
1580 memset(&fpu, 0, sizeof fpu);
1581 fpu.fsw = env->fpus & ~(7 << 11);
1582 fpu.fsw |= (env->fpstt & 7) << 11;
1583 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1584 fpu.last_opcode = env->fpop;
1585 fpu.last_ip = env->fpip;
1586 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1587 for (i = 0; i < 8; ++i) {
1588 fpu.ftwx |= (!env->fptags[i]) << i;
1589 }
05330448 1590 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1591 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1592 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1593 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1594 }
05330448
AL		 1595 fpu.mxcsr = env->mxcsr;
1596
1bc22652 1597 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1598}
1599
6b42494b
JK		 1600#define XSAVE_FCW_FSW 0
1601#define XSAVE_FTW_FOP 1
f1665b21
SY		 1602#define XSAVE_CWD_RIP 2
1603#define XSAVE_CWD_RDP 4
1604#define XSAVE_MXCSR 6
1605#define XSAVE_ST_SPACE 8
1606#define XSAVE_XMM_SPACE 40
1607#define XSAVE_XSTATE_BV 128
1608#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1609#define XSAVE_BNDREGS 240
1610#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1611#define XSAVE_OPMASK 272
1612#define XSAVE_ZMM_Hi256 288
1613#define XSAVE_Hi16_ZMM 416
f74eefe0 1614#define XSAVE_PKRU 672
f1665b21 1615
b503717d 1616#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 1617 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 1618
1619#define ASSERT_OFFSET(word_offset, field) \
1620 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1621 offsetof(X86XSaveArea, field))
1622
1623ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1624ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1625ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1626ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1627ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1628ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1629ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1630ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1631ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1632ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1633ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1634ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1635ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1636ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1637ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1638
1bc22652 1639static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1640{
1bc22652 1641 CPUX86State *env = &cpu->env;
5b8063c4 1642 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 1643
28143b40 1644 if (!has_xsave) {
1bc22652 1645 return kvm_put_fpu(cpu);
b9bec74b 1646 }
86a57621 1647 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1648
9be38598 1649 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1650}
1651
1bc22652 1652static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1653{
1bc22652 1654 CPUX86State *env = &cpu->env;
bdfc8480 1655 struct kvm_xcrs xcrs = {};
f1665b21 1656
28143b40 1657 if (!has_xcrs) {
f1665b21 1658 return 0;
b9bec74b 1659 }
f1665b21
SY		 1660
1661 xcrs.nr_xcrs = 1;
1662 xcrs.flags = 0;
1663 xcrs.xcrs[0].xcr = 0;
1664 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1665 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1666}
1667
1bc22652 1668static int kvm_put_sregs(X86CPU *cpu)
05330448 1669{
1bc22652 1670 CPUX86State *env = &cpu->env;
05330448
AL		 1671 struct kvm_sregs sregs;
1672
0e607a80
JK		 1673 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1674 if (env->interrupt_injected >= 0) {
1675 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1676 (uint64_t)1 << (env->interrupt_injected % 64);
1677 }
05330448
AL		 1678
1679 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1680 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1681 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1682 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1683 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1684 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1685 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1686 } else {
b9bec74b
JK		 1687 set_seg(&sregs.cs, &env->segs[R_CS]);
1688 set_seg(&sregs.ds, &env->segs[R_DS]);
1689 set_seg(&sregs.es, &env->segs[R_ES]);
1690 set_seg(&sregs.fs, &env->segs[R_FS]);
1691 set_seg(&sregs.gs, &env->segs[R_GS]);
1692 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1693 }
1694
1695 set_seg(&sregs.tr, &env->tr);
1696 set_seg(&sregs.ldt, &env->ldt);
1697
1698 sregs.idt.limit = env->idt.limit;
1699 sregs.idt.base = env->idt.base;
7e680753 1700 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1701 sregs.gdt.limit = env->gdt.limit;
1702 sregs.gdt.base = env->gdt.base;
7e680753 1703 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1704
1705 sregs.cr0 = env->cr[0];
1706 sregs.cr2 = env->cr[2];
1707 sregs.cr3 = env->cr[3];
1708 sregs.cr4 = env->cr[4];
1709
02e51483
CF		 1710 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1711 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1712
1713 sregs.efer = env->efer;
1714
1bc22652 1715 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1716}
1717
d71b62a1
EH		 1718static void kvm_msr_buf_reset(X86CPU *cpu)
1719{
1720 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1721}
1722
9c600a84
EH		 1723static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1724{
1725 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1726 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1727 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1728
1729 assert((void *)(entry + 1) <= limit);
1730
1abc2cae
EH		 1731 entry->index = index;
1732 entry->reserved = 0;
1733 entry->data = value;
9c600a84
EH		 1734 msrs->nmsrs++;
1735}
1736
73e1b8f2
PB		 1737static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1738{
1739 kvm_msr_buf_reset(cpu);
1740 kvm_msr_entry_add(cpu, index, value);
1741
1742 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1743}
1744
f8d9ccf8
DDAG		 1745void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1746{
1747 int ret;
1748
1749 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1750 assert(ret == 1);
1751}
1752
7477cd38
MT		 1753static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1754{
1755 CPUX86State *env = &cpu->env;
48e1a45c 1756 int ret;
7477cd38
MT		 1757
1758 if (!has_msr_tsc_deadline) {
1759 return 0;
1760 }
1761
73e1b8f2 1762 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1763 if (ret < 0) {
1764 return ret;
1765 }
1766
1767 assert(ret == 1);
1768 return 0;
7477cd38
MT		 1769}
1770
6bdf863d
JK		 1771/*
1772 * Provide a separate write service for the feature control MSR in order to
1773 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1774 * before writing any other state because forcibly leaving nested mode
1775 * invalidates the VCPU state.
1776 */
1777static int kvm_put_msr_feature_control(X86CPU *cpu)
1778{
48e1a45c
PB		 1779 int ret;
1780
1781 if (!has_msr_feature_control) {
1782 return 0;
1783 }
6bdf863d 1784
73e1b8f2
PB		 1785 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1786 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1787 if (ret < 0) {
1788 return ret;
1789 }
1790
1791 assert(ret == 1);
1792 return 0;
6bdf863d
JK		 1793}
1794
1bc22652 1795static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1796{
1bc22652 1797 CPUX86State *env = &cpu->env;
9c600a84 1798 int i;
48e1a45c 1799 int ret;
05330448 1800
d71b62a1
EH		 1801 kvm_msr_buf_reset(cpu);
1802
9c600a84
EH		 1803 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1804 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1805 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1806 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1807 if (has_msr_star) {
9c600a84 1808 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1809 }
c3a3a7d3 1810 if (has_msr_hsave_pa) {
9c600a84 1811 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1812 }
c9b8f6b6 1813 if (has_msr_tsc_aux) {
9c600a84 1814 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1815 }
f28558d3 1816 if (has_msr_tsc_adjust) {
9c600a84 1817 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1818 }
21e87c46 1819 if (has_msr_misc_enable) {
9c600a84 1820 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1821 env->msr_ia32_misc_enable);
1822 }
fc12d72e 1823 if (has_msr_smbase) {
9c600a84 1824 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1825 }
e13713db
LA		 1826 if (has_msr_smi_count) {
1827 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1828 }
439d19f2 1829 if (has_msr_bndcfgs) {
9c600a84 1830 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 1831 }
18cd2c17 1832 if (has_msr_xss) {
9c600a84 1833 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 1834 }
a33a2cfe
PB		 1835 if (has_msr_spec_ctrl) {
1836 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1837 }
cfeea0c0
KRW		 1838 if (has_msr_virt_ssbd) {
1839 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1840 }
1841
05330448 1842#ifdef TARGET_X86_64
25d2e361 1843 if (lm_capable_kernel) {
9c600a84
EH		 1844 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1845 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1846 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1847 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 1848 }
05330448 1849#endif
a33a2cfe 1850
ff5c186b 1851 /*
0d894367
PB		 1852 * The following MSRs have side effects on the guest or are too heavy
1853 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 1854 */
1855 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 1856 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1857 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1858 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 1859 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 1860 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 1861 }
55c911a5 1862 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 1863 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 1864 }
55c911a5 1865 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 1866 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 1867 }
0b368a10
JD		 1868 if (has_architectural_pmu_version > 0) {
1869 if (has_architectural_pmu_version > 1) {
1870 /* Stop the counter. */
1871 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
1872 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
1873 }
0d894367
PB		 1874
1875 /* Set the counter values. */
0b368a10 1876 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 1877 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 1878 env->msr_fixed_counters[i]);
1879 }
0b368a10 1880 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 1881 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 1882 env->msr_gp_counters[i]);
9c600a84 1883 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 1884 env->msr_gp_evtsel[i]);
1885 }
0b368a10
JD		 1886 if (has_architectural_pmu_version > 1) {
1887 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
1888 env->msr_global_status);
1889 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
1890 env->msr_global_ovf_ctrl);
1891
1892 /* Now start the PMU. */
1893 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
1894 env->msr_fixed_ctr_ctrl);
1895 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
1896 env->msr_global_ctrl);
1897 }
0d894367 1898 }
da1cc323
EY		 1899 /*
1900 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
1901 * only sync them to KVM on the first cpu
1902 */
1903 if (current_cpu == first_cpu) {
1904 if (has_msr_hv_hypercall) {
1905 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
1906 env->msr_hv_guest_os_id);
1907 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
1908 env->msr_hv_hypercall);
1909 }
1910 if (cpu->hyperv_time) {
1911 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
1912 env->msr_hv_tsc);
1913 }
ba6a4fd9
VK		 1914 if (cpu->hyperv_reenlightenment) {
1915 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
1916 env->msr_hv_reenlightenment_control);
1917 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
1918 env->msr_hv_tsc_emulation_control);
1919 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
1920 env->msr_hv_tsc_emulation_status);
1921 }
eab70139 1922 }
2d5aa872 1923 if (cpu->hyperv_vapic) {
9c600a84 1924 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 1925 env->msr_hv_vapic);
eab70139 1926 }
f2a53c9e
AS		 1927 if (has_msr_hv_crash) {
1928 int j;
1929
5e953812 1930 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 1931 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 1932 env->msr_hv_crash_params[j]);
1933
5e953812 1934 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 1935 }
46eb8f98 1936 if (has_msr_hv_runtime) {
9c600a84 1937 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 1938 }
e9688fab
RK		 1939 if (cpu->hyperv_vpindex && hv_vpindex_settable) {
1940 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX, hyperv_vp_index(cpu));
1941 }
866eea9a
AS		 1942 if (cpu->hyperv_synic) {
1943 int j;
1944
09df29b6
RK		 1945 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
1946
9c600a84 1947 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 1948 env->msr_hv_synic_control);
9c600a84 1949 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 1950 env->msr_hv_synic_evt_page);
9c600a84 1951 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 1952 env->msr_hv_synic_msg_page);
1953
1954 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 1955 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 1956 env->msr_hv_synic_sint[j]);
1957 }
1958 }
ff99aa64
AS		 1959 if (has_msr_hv_stimer) {
1960 int j;
1961
1962 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 1963 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 1964 env->msr_hv_stimer_config[j]);
1965 }
1966
1967 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 1968 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 1969 env->msr_hv_stimer_count[j]);
1970 }
1971 }
1eabfce6 1972 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 1973 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
1974
9c600a84
EH		 1975 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
1976 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
1977 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
1978 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
1979 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
1980 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
1981 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
1982 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
1983 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
1984 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
1985 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
1986 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 1987 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 1988 /* The CPU GPs if we write to a bit above the physical limit of
1989 * the host CPU (and KVM emulates that)
1990 */
1991 uint64_t mask = env->mtrr_var[i].mask;
1992 mask &= phys_mask;
1993
9c600a84
EH		 1994 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
1995 env->mtrr_var[i].base);
112dad69 1996 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 1997 }
1998 }
b77146e9
CP		 1999 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2000 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2001 0x14, 1, R_EAX) & 0x7;
2002
2003 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2004 env->msr_rtit_ctrl);
2005 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2006 env->msr_rtit_status);
2007 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2008 env->msr_rtit_output_base);
2009 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2010 env->msr_rtit_output_mask);
2011 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2012 env->msr_rtit_cr3_match);
2013 for (i = 0; i < addr_num; i++) {
2014 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2015 env->msr_rtit_addrs[i]);
2016 }
2017 }
6bdf863d
JK		 2018
2019 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2020 * kvm_put_msr_feature_control. */
ea643051 2021 }
57780495 2022 if (env->mcg_cap) {
d8da8574 2023 int i;
b9bec74b 2024
9c600a84
EH		 2025 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2026 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2027 if (has_msr_mcg_ext_ctl) {
2028 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2029 }
c34d440a 2030 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2031 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2032 }
2033 }
1a03675d 2034
d71b62a1 2035 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2036 if (ret < 0) {
2037 return ret;
2038 }
05330448 2039
c70b11d1
EH		 2040 if (ret < cpu->kvm_msr_buf->nmsrs) {
2041 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2042 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2043 (uint32_t)e->index, (uint64_t)e->data);
2044 }
2045
9c600a84 2046 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2047 return 0;
05330448
AL		 2048}
2049
2050
1bc22652 2051static int kvm_get_fpu(X86CPU *cpu)
05330448 2052{
1bc22652 2053 CPUX86State *env = &cpu->env;
05330448
AL		 2054 struct kvm_fpu fpu;
2055 int i, ret;
2056
1bc22652 2057 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2058 if (ret < 0) {
05330448 2059 return ret;
b9bec74b 2060 }
05330448
AL		 2061
2062 env->fpstt = (fpu.fsw >> 11) & 7;
2063 env->fpus = fpu.fsw;
2064 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2065 env->fpop = fpu.last_opcode;
2066 env->fpip = fpu.last_ip;
2067 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2068 for (i = 0; i < 8; ++i) {
2069 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2070 }
05330448 2071 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2072 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2073 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2074 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2075 }
05330448
AL		 2076 env->mxcsr = fpu.mxcsr;
2077
2078 return 0;
2079}
2080
1bc22652 2081static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2082{
1bc22652 2083 CPUX86State *env = &cpu->env;
5b8063c4 2084 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2085 int ret;
f1665b21 2086
28143b40 2087 if (!has_xsave) {
1bc22652 2088 return kvm_get_fpu(cpu);
b9bec74b 2089 }
f1665b21 2090
1bc22652 2091 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2092 if (ret < 0) {
f1665b21 2093 return ret;
0f53994f 2094 }
86a57621 2095 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2096
f1665b21 2097 return 0;
f1665b21
SY		 2098}
2099
1bc22652 2100static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2101{
1bc22652 2102 CPUX86State *env = &cpu->env;
f1665b21
SY		 2103 int i, ret;
2104 struct kvm_xcrs xcrs;
2105
28143b40 2106 if (!has_xcrs) {
f1665b21 2107 return 0;
b9bec74b 2108 }
f1665b21 2109
1bc22652 2110 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2111 if (ret < 0) {
f1665b21 2112 return ret;
b9bec74b 2113 }
f1665b21 2114
b9bec74b 2115 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2116 /* Only support xcr0 now */
0fd53fec
PB		 2117 if (xcrs.xcrs[i].xcr == 0) {
2118 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2119 break;
2120 }
b9bec74b 2121 }
f1665b21 2122 return 0;
f1665b21
SY		 2123}
2124
1bc22652 2125static int kvm_get_sregs(X86CPU *cpu)
05330448 2126{
1bc22652 2127 CPUX86State *env = &cpu->env;
05330448 2128 struct kvm_sregs sregs;
0e607a80 2129 int bit, i, ret;
05330448 2130
1bc22652 2131 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2132 if (ret < 0) {
05330448 2133 return ret;
b9bec74b 2134 }
05330448 2135
0e607a80
JK		 2136 /* There can only be one pending IRQ set in the bitmap at a time, so try
2137 to find it and save its number instead (-1 for none). */
2138 env->interrupt_injected = -1;
2139 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2140 if (sregs.interrupt_bitmap[i]) {
2141 bit = ctz64(sregs.interrupt_bitmap[i]);
2142 env->interrupt_injected = i * 64 + bit;
2143 break;
2144 }
2145 }
05330448
AL		 2146
2147 get_seg(&env->segs[R_CS], &sregs.cs);
2148 get_seg(&env->segs[R_DS], &sregs.ds);
2149 get_seg(&env->segs[R_ES], &sregs.es);
2150 get_seg(&env->segs[R_FS], &sregs.fs);
2151 get_seg(&env->segs[R_GS], &sregs.gs);
2152 get_seg(&env->segs[R_SS], &sregs.ss);
2153
2154 get_seg(&env->tr, &sregs.tr);
2155 get_seg(&env->ldt, &sregs.ldt);
2156
2157 env->idt.limit = sregs.idt.limit;
2158 env->idt.base = sregs.idt.base;
2159 env->gdt.limit = sregs.gdt.limit;
2160 env->gdt.base = sregs.gdt.base;
2161
2162 env->cr[0] = sregs.cr0;
2163 env->cr[2] = sregs.cr2;
2164 env->cr[3] = sregs.cr3;
2165 env->cr[4] = sregs.cr4;
2166
05330448 2167 env->efer = sregs.efer;
cce47516
JK		 2168
2169 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2170 x86_update_hflags(env);
05330448
AL		 2171
2172 return 0;
2173}
2174
1bc22652 2175static int kvm_get_msrs(X86CPU *cpu)
05330448 2176{
1bc22652 2177 CPUX86State *env = &cpu->env;
d71b62a1 2178 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2179 int ret, i;
fcc35e7c 2180 uint64_t mtrr_top_bits;
05330448 2181
d71b62a1
EH		 2182 kvm_msr_buf_reset(cpu);
2183
9c600a84
EH		 2184 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2185 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2186 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2187 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2188 if (has_msr_star) {
9c600a84 2189 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2190 }
c3a3a7d3 2191 if (has_msr_hsave_pa) {
9c600a84 2192 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2193 }
c9b8f6b6 2194 if (has_msr_tsc_aux) {
9c600a84 2195 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2196 }
f28558d3 2197 if (has_msr_tsc_adjust) {
9c600a84 2198 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2199 }
aa82ba54 2200 if (has_msr_tsc_deadline) {
9c600a84 2201 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2202 }
21e87c46 2203 if (has_msr_misc_enable) {
9c600a84 2204 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2205 }
fc12d72e 2206 if (has_msr_smbase) {
9c600a84 2207 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2208 }
e13713db
LA		 2209 if (has_msr_smi_count) {
2210 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2211 }
df67696e 2212 if (has_msr_feature_control) {
9c600a84 2213 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2214 }
79e9ebeb 2215 if (has_msr_bndcfgs) {
9c600a84 2216 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2217 }
18cd2c17 2218 if (has_msr_xss) {
9c600a84 2219 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2220 }
a33a2cfe
PB		 2221 if (has_msr_spec_ctrl) {
2222 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2223 }
cfeea0c0
KRW		 2224 if (has_msr_virt_ssbd) {
2225 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2226 }
b8cc45d6 2227 if (!env->tsc_valid) {
9c600a84 2228 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2229 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2230 }
2231
05330448 2232#ifdef TARGET_X86_64
25d2e361 2233 if (lm_capable_kernel) {
9c600a84
EH		 2234 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2235 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2236 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2237 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2238 }
05330448 2239#endif
9c600a84
EH		 2240 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2241 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2242 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2243 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2244 }
55c911a5 2245 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2246 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2247 }
55c911a5 2248 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2249 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2250 }
0b368a10
JD		 2251 if (has_architectural_pmu_version > 0) {
2252 if (has_architectural_pmu_version > 1) {
2253 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2254 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2255 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2256 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2257 }
2258 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2259 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2260 }
0b368a10 2261 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2262 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2263 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2264 }
2265 }
1a03675d 2266
57780495 2267 if (env->mcg_cap) {
9c600a84
EH		 2268 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2269 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2270 if (has_msr_mcg_ext_ctl) {
2271 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2272 }
b9bec74b 2273 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2274 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2275 }
57780495 2276 }
57780495 2277
1c90ef26 2278 if (has_msr_hv_hypercall) {
9c600a84
EH		 2279 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2280 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2281 }
2d5aa872 2282 if (cpu->hyperv_vapic) {
9c600a84 2283 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2284 }
3ddcd2ed 2285 if (cpu->hyperv_time) {
9c600a84 2286 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2287 }
ba6a4fd9
VK		 2288 if (cpu->hyperv_reenlightenment) {
2289 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2290 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2291 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2292 }
f2a53c9e
AS		 2293 if (has_msr_hv_crash) {
2294 int j;
2295
5e953812 2296 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2297 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2298 }
2299 }
46eb8f98 2300 if (has_msr_hv_runtime) {
9c600a84 2301 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2302 }
866eea9a
AS		 2303 if (cpu->hyperv_synic) {
2304 uint32_t msr;
2305
9c600a84 2306 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2307 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2308 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2309 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2310 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2311 }
2312 }
ff99aa64
AS		 2313 if (has_msr_hv_stimer) {
2314 uint32_t msr;
2315
2316 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2317 msr++) {
9c600a84 2318 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2319 }
2320 }
1eabfce6 2321 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2322 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2323 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2324 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2325 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2326 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2327 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2328 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2329 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2330 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2331 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2332 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2333 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2334 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2335 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2336 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2337 }
2338 }
5ef68987 2339
b77146e9
CP		 2340 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2341 int addr_num =
2342 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2343
2344 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2345 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2346 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2347 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2348 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2349 for (i = 0; i < addr_num; i++) {
2350 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2351 }
2352 }
2353
d71b62a1 2354 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2355 if (ret < 0) {
05330448 2356 return ret;
b9bec74b 2357 }
05330448 2358
c70b11d1
EH		 2359 if (ret < cpu->kvm_msr_buf->nmsrs) {
2360 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2361 error_report("error: failed to get MSR 0x%" PRIx32,
2362 (uint32_t)e->index);
2363 }
2364
9c600a84 2365 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2366 /*
2367 * MTRR masks: Each mask consists of 5 parts
2368 * a 10..0: must be zero
2369 * b 11 : valid bit
2370 * c n-1.12: actual mask bits
2371 * d 51..n: reserved must be zero
2372 * e 63.52: reserved must be zero
2373 *
2374 * 'n' is the number of physical bits supported by the CPU and is
2375 * apparently always <= 52. We know our 'n' but don't know what
2376 * the destinations 'n' is; it might be smaller, in which case
2377 * it masks (c) on loading. It might be larger, in which case
2378 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2379 * we're migrating to.
2380 */
2381
2382 if (cpu->fill_mtrr_mask) {
2383 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2384 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2385 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2386 } else {
2387 mtrr_top_bits = 0;
2388 }
2389
05330448 2390 for (i = 0; i < ret; i++) {
0d894367
PB		 2391 uint32_t index = msrs[i].index;
2392 switch (index) {
05330448
AL		 2393 case MSR_IA32_SYSENTER_CS:
2394 env->sysenter_cs = msrs[i].data;
2395 break;
2396 case MSR_IA32_SYSENTER_ESP:
2397 env->sysenter_esp = msrs[i].data;
2398 break;
2399 case MSR_IA32_SYSENTER_EIP:
2400 env->sysenter_eip = msrs[i].data;
2401 break;
0c03266a
JK		 2402 case MSR_PAT:
2403 env->pat = msrs[i].data;
2404 break;
05330448
AL		 2405 case MSR_STAR:
2406 env->star = msrs[i].data;
2407 break;
2408#ifdef TARGET_X86_64
2409 case MSR_CSTAR:
2410 env->cstar = msrs[i].data;
2411 break;
2412 case MSR_KERNELGSBASE:
2413 env->kernelgsbase = msrs[i].data;
2414 break;
2415 case MSR_FMASK:
2416 env->fmask = msrs[i].data;
2417 break;
2418 case MSR_LSTAR:
2419 env->lstar = msrs[i].data;
2420 break;
2421#endif
2422 case MSR_IA32_TSC:
2423 env->tsc = msrs[i].data;
2424 break;
c9b8f6b6
AS		 2425 case MSR_TSC_AUX:
2426 env->tsc_aux = msrs[i].data;
2427 break;
f28558d3
WA		 2428 case MSR_TSC_ADJUST:
2429 env->tsc_adjust = msrs[i].data;
2430 break;
aa82ba54
LJ		 2431 case MSR_IA32_TSCDEADLINE:
2432 env->tsc_deadline = msrs[i].data;
2433 break;
aa851e36
MT		 2434 case MSR_VM_HSAVE_PA:
2435 env->vm_hsave = msrs[i].data;
2436 break;
1a03675d
GC		 2437 case MSR_KVM_SYSTEM_TIME:
2438 env->system_time_msr = msrs[i].data;
2439 break;
2440 case MSR_KVM_WALL_CLOCK:
2441 env->wall_clock_msr = msrs[i].data;
2442 break;
57780495
MT		 2443 case MSR_MCG_STATUS:
2444 env->mcg_status = msrs[i].data;
2445 break;
2446 case MSR_MCG_CTL:
2447 env->mcg_ctl = msrs[i].data;
2448 break;
87f8b626
AR		 2449 case MSR_MCG_EXT_CTL:
2450 env->mcg_ext_ctl = msrs[i].data;
2451 break;
21e87c46
AK		 2452 case MSR_IA32_MISC_ENABLE:
2453 env->msr_ia32_misc_enable = msrs[i].data;
2454 break;
fc12d72e
PB		 2455 case MSR_IA32_SMBASE:
2456 env->smbase = msrs[i].data;
2457 break;
e13713db
LA		 2458 case MSR_SMI_COUNT:
2459 env->msr_smi_count = msrs[i].data;
2460 break;
0779caeb
ACL		 2461 case MSR_IA32_FEATURE_CONTROL:
2462 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2463 break;
79e9ebeb
LJ		 2464 case MSR_IA32_BNDCFGS:
2465 env->msr_bndcfgs = msrs[i].data;
2466 break;
18cd2c17
WL		 2467 case MSR_IA32_XSS:
2468 env->xss = msrs[i].data;
2469 break;
57780495 2470 default:
57780495
MT		 2471 if (msrs[i].index >= MSR_MC0_CTL &&
2472 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2473 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2474 }
d8da8574 2475 break;
f6584ee2
GN		 2476 case MSR_KVM_ASYNC_PF_EN:
2477 env->async_pf_en_msr = msrs[i].data;
2478 break;
bc9a839d
MT		 2479 case MSR_KVM_PV_EOI_EN:
2480 env->pv_eoi_en_msr = msrs[i].data;
2481 break;
917367aa
MT		 2482 case MSR_KVM_STEAL_TIME:
2483 env->steal_time_msr = msrs[i].data;
2484 break;
0d894367
PB		 2485 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2486 env->msr_fixed_ctr_ctrl = msrs[i].data;
2487 break;
2488 case MSR_CORE_PERF_GLOBAL_CTRL:
2489 env->msr_global_ctrl = msrs[i].data;
2490 break;
2491 case MSR_CORE_PERF_GLOBAL_STATUS:
2492 env->msr_global_status = msrs[i].data;
2493 break;
2494 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2495 env->msr_global_ovf_ctrl = msrs[i].data;
2496 break;
2497 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2498 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2499 break;
2500 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2501 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2502 break;
2503 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2504 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2505 break;
1c90ef26
VR		 2506 case HV_X64_MSR_HYPERCALL:
2507 env->msr_hv_hypercall = msrs[i].data;
2508 break;
2509 case HV_X64_MSR_GUEST_OS_ID:
2510 env->msr_hv_guest_os_id = msrs[i].data;
2511 break;
5ef68987
VR		 2512 case HV_X64_MSR_APIC_ASSIST_PAGE:
2513 env->msr_hv_vapic = msrs[i].data;
2514 break;
48a5f3bc
VR		 2515 case HV_X64_MSR_REFERENCE_TSC:
2516 env->msr_hv_tsc = msrs[i].data;
2517 break;
f2a53c9e
AS		 2518 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2519 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2520 break;
46eb8f98
AS		 2521 case HV_X64_MSR_VP_RUNTIME:
2522 env->msr_hv_runtime = msrs[i].data;
2523 break;
866eea9a
AS		 2524 case HV_X64_MSR_SCONTROL:
2525 env->msr_hv_synic_control = msrs[i].data;
2526 break;
866eea9a
AS		 2527 case HV_X64_MSR_SIEFP:
2528 env->msr_hv_synic_evt_page = msrs[i].data;
2529 break;
2530 case HV_X64_MSR_SIMP:
2531 env->msr_hv_synic_msg_page = msrs[i].data;
2532 break;
2533 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2534 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2535 break;
2536 case HV_X64_MSR_STIMER0_CONFIG:
2537 case HV_X64_MSR_STIMER1_CONFIG:
2538 case HV_X64_MSR_STIMER2_CONFIG:
2539 case HV_X64_MSR_STIMER3_CONFIG:
2540 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2541 msrs[i].data;
2542 break;
2543 case HV_X64_MSR_STIMER0_COUNT:
2544 case HV_X64_MSR_STIMER1_COUNT:
2545 case HV_X64_MSR_STIMER2_COUNT:
2546 case HV_X64_MSR_STIMER3_COUNT:
2547 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2548 msrs[i].data;
866eea9a 2549 break;
ba6a4fd9
VK		 2550 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2551 env->msr_hv_reenlightenment_control = msrs[i].data;
2552 break;
2553 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2554 env->msr_hv_tsc_emulation_control = msrs[i].data;
2555 break;
2556 case HV_X64_MSR_TSC_EMULATION_STATUS:
2557 env->msr_hv_tsc_emulation_status = msrs[i].data;
2558 break;
d1ae67f6
AW		 2559 case MSR_MTRRdefType:
2560 env->mtrr_deftype = msrs[i].data;
2561 break;
2562 case MSR_MTRRfix64K_00000:
2563 env->mtrr_fixed[0] = msrs[i].data;
2564 break;
2565 case MSR_MTRRfix16K_80000:
2566 env->mtrr_fixed[1] = msrs[i].data;
2567 break;
2568 case MSR_MTRRfix16K_A0000:
2569 env->mtrr_fixed[2] = msrs[i].data;
2570 break;
2571 case MSR_MTRRfix4K_C0000:
2572 env->mtrr_fixed[3] = msrs[i].data;
2573 break;
2574 case MSR_MTRRfix4K_C8000:
2575 env->mtrr_fixed[4] = msrs[i].data;
2576 break;
2577 case MSR_MTRRfix4K_D0000:
2578 env->mtrr_fixed[5] = msrs[i].data;
2579 break;
2580 case MSR_MTRRfix4K_D8000:
2581 env->mtrr_fixed[6] = msrs[i].data;
2582 break;
2583 case MSR_MTRRfix4K_E0000:
2584 env->mtrr_fixed[7] = msrs[i].data;
2585 break;
2586 case MSR_MTRRfix4K_E8000:
2587 env->mtrr_fixed[8] = msrs[i].data;
2588 break;
2589 case MSR_MTRRfix4K_F0000:
2590 env->mtrr_fixed[9] = msrs[i].data;
2591 break;
2592 case MSR_MTRRfix4K_F8000:
2593 env->mtrr_fixed[10] = msrs[i].data;
2594 break;
2595 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2596 if (index & 1) {
fcc35e7c
DDAG		 2597 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2598 mtrr_top_bits;
d1ae67f6
AW		 2599 } else {
2600 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2601 }
2602 break;
a33a2cfe
PB		 2603 case MSR_IA32_SPEC_CTRL:
2604 env->spec_ctrl = msrs[i].data;
2605 break;
cfeea0c0
KRW		 2606 case MSR_VIRT_SSBD:
2607 env->virt_ssbd = msrs[i].data;
2608 break;
b77146e9
CP		 2609 case MSR_IA32_RTIT_CTL:
2610 env->msr_rtit_ctrl = msrs[i].data;
2611 break;
2612 case MSR_IA32_RTIT_STATUS:
2613 env->msr_rtit_status = msrs[i].data;
2614 break;
2615 case MSR_IA32_RTIT_OUTPUT_BASE:
2616 env->msr_rtit_output_base = msrs[i].data;
2617 break;
2618 case MSR_IA32_RTIT_OUTPUT_MASK:
2619 env->msr_rtit_output_mask = msrs[i].data;
2620 break;
2621 case MSR_IA32_RTIT_CR3_MATCH:
2622 env->msr_rtit_cr3_match = msrs[i].data;
2623 break;
2624 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2625 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2626 break;
05330448
AL		 2627 }
2628 }
2629
2630 return 0;
2631}
2632
1bc22652 2633static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2634{
1bc22652 2635 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2636
1bc22652 2637 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2638}
2639
23d02d9b 2640static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2641{
259186a7 2642 CPUState *cs = CPU(cpu);
23d02d9b 2643 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2644 struct kvm_mp_state mp_state;
2645 int ret;
2646
259186a7 2647 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2648 if (ret < 0) {
2649 return ret;
2650 }
2651 env->mp_state = mp_state.mp_state;
c14750e8 2652 if (kvm_irqchip_in_kernel()) {
259186a7 2653 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2654 }
9bdbe550
HB		 2655 return 0;
2656}
2657
1bc22652 2658static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2659{
02e51483 2660 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2661 struct kvm_lapic_state kapic;
2662 int ret;
2663
3d4b2649 2664 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2665 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2666 if (ret < 0) {
2667 return ret;
2668 }
2669
2670 kvm_get_apic_state(apic, &kapic);
2671 }
2672 return 0;
2673}
2674
1bc22652 2675static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2676{
fc12d72e 2677 CPUState *cs = CPU(cpu);
1bc22652 2678 CPUX86State *env = &cpu->env;
076796f8 2679 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2680
2681 if (!kvm_has_vcpu_events()) {
2682 return 0;
2683 }
2684
31827373
JK		 2685 events.exception.injected = (env->exception_injected >= 0);
2686 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2687 events.exception.has_error_code = env->has_error_code;
2688 events.exception.error_code = env->error_code;
2689
2690 events.interrupt.injected = (env->interrupt_injected >= 0);
2691 events.interrupt.nr = env->interrupt_injected;
2692 events.interrupt.soft = env->soft_interrupt;
2693
2694 events.nmi.injected = env->nmi_injected;
2695 events.nmi.pending = env->nmi_pending;
2696 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2697
2698 events.sipi_vector = env->sipi_vector;
68c6efe0 2699 events.flags = 0;
a0fb002c 2700
fc12d72e
PB		 2701 if (has_msr_smbase) {
2702 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2703 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2704 if (kvm_irqchip_in_kernel()) {
2705 /* As soon as these are moved to the kernel, remove them
2706 * from cs->interrupt_request.
2707 */
2708 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2709 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2710 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2711 } else {
2712 /* Keep these in cs->interrupt_request. */
2713 events.smi.pending = 0;
2714 events.smi.latched_init = 0;
2715 }
fc3a1fd7
DDAG		 2716 /* Stop SMI delivery on old machine types to avoid a reboot
2717 * on an inward migration of an old VM.
2718 */
2719 if (!cpu->kvm_no_smi_migration) {
2720 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2721 }
fc12d72e
PB		 2722 }
2723
ea643051 2724 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2725 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2726 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2727 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2728 }
ea643051 2729 }
aee028b9 2730
1bc22652 2731 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2732}
2733
1bc22652 2734static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2735{
1bc22652 2736 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2737 struct kvm_vcpu_events events;
2738 int ret;
2739
2740 if (!kvm_has_vcpu_events()) {
2741 return 0;
2742 }
2743
fc12d72e 2744 memset(&events, 0, sizeof(events));
1bc22652 2745 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2746 if (ret < 0) {
2747 return ret;
2748 }
31827373 2749 env->exception_injected =
a0fb002c
JK		 2750 events.exception.injected ? events.exception.nr : -1;
2751 env->has_error_code = events.exception.has_error_code;
2752 env->error_code = events.exception.error_code;
2753
2754 env->interrupt_injected =
2755 events.interrupt.injected ? events.interrupt.nr : -1;
2756 env->soft_interrupt = events.interrupt.soft;
2757
2758 env->nmi_injected = events.nmi.injected;
2759 env->nmi_pending = events.nmi.pending;
2760 if (events.nmi.masked) {
2761 env->hflags2 |= HF2_NMI_MASK;
2762 } else {
2763 env->hflags2 &= ~HF2_NMI_MASK;
2764 }
2765
fc12d72e
PB		 2766 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2767 if (events.smi.smm) {
2768 env->hflags |= HF_SMM_MASK;
2769 } else {
2770 env->hflags &= ~HF_SMM_MASK;
2771 }
2772 if (events.smi.pending) {
2773 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2774 } else {
2775 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2776 }
2777 if (events.smi.smm_inside_nmi) {
2778 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2779 } else {
2780 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2781 }
2782 if (events.smi.latched_init) {
2783 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2784 } else {
2785 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2786 }
2787 }
2788
a0fb002c 2789 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2790
2791 return 0;
2792}
2793
1bc22652 2794static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2795{
ed2803da 2796 CPUState *cs = CPU(cpu);
1bc22652 2797 CPUX86State *env = &cpu->env;
b0b1d690 2798 int ret = 0;
b0b1d690
JK		 2799 unsigned long reinject_trap = 0;
2800
2801 if (!kvm_has_vcpu_events()) {
2802 if (env->exception_injected == 1) {
2803 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2804 } else if (env->exception_injected == 3) {
2805 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2806 }
2807 env->exception_injected = -1;
2808 }
2809
2810 /*
2811 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2812 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2813 * by updating the debug state once again if single-stepping is on.
2814 * Another reason to call kvm_update_guest_debug here is a pending debug
2815 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2816 * reinject them via SET_GUEST_DEBUG.
2817 */
2818 if (reinject_trap ||
ed2803da 2819 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2820 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 2821 }
b0b1d690
JK		 2822 return ret;
2823}
2824
1bc22652 2825static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 2826{
1bc22652 2827 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2828 struct kvm_debugregs dbgregs;
2829 int i;
2830
2831 if (!kvm_has_debugregs()) {
2832 return 0;
2833 }
2834
2835 for (i = 0; i < 4; i++) {
2836 dbgregs.db[i] = env->dr[i];
2837 }
2838 dbgregs.dr6 = env->dr[6];
2839 dbgregs.dr7 = env->dr[7];
2840 dbgregs.flags = 0;
2841
1bc22652 2842 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 2843}
2844
1bc22652 2845static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 2846{
1bc22652 2847 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 2848 struct kvm_debugregs dbgregs;
2849 int i, ret;
2850
2851 if (!kvm_has_debugregs()) {
2852 return 0;
2853 }
2854
1bc22652 2855 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 2856 if (ret < 0) {
b9bec74b 2857 return ret;
ff44f1a3
JK		 2858 }
2859 for (i = 0; i < 4; i++) {
2860 env->dr[i] = dbgregs.db[i];
2861 }
2862 env->dr[4] = env->dr[6] = dbgregs.dr6;
2863 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 2864
2865 return 0;
2866}
2867
20d695a9 2868int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 2869{
20d695a9 2870 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 2871 int ret;
2872
2fa45344 2873 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 2874
48e1a45c 2875 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 2876 ret = kvm_put_msr_feature_control(x86_cpu);
2877 if (ret < 0) {
2878 return ret;
2879 }
2880 }
2881
36f96c4b
HZ		 2882 if (level == KVM_PUT_FULL_STATE) {
2883 /* We don't check for kvm_arch_set_tsc_khz() errors here,
2884 * because TSC frequency mismatch shouldn't abort migration,
2885 * unless the user explicitly asked for a more strict TSC
2886 * setting (e.g. using an explicit "tsc-freq" option).
2887 */
2888 kvm_arch_set_tsc_khz(cpu);
2889 }
2890
1bc22652 2891 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 2892 if (ret < 0) {
05330448 2893 return ret;
b9bec74b 2894 }
1bc22652 2895 ret = kvm_put_xsave(x86_cpu);
b9bec74b 2896 if (ret < 0) {
f1665b21 2897 return ret;
b9bec74b 2898 }
1bc22652 2899 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 2900 if (ret < 0) {
05330448 2901 return ret;
b9bec74b 2902 }
1bc22652 2903 ret = kvm_put_sregs(x86_cpu);
b9bec74b 2904 if (ret < 0) {
05330448 2905 return ret;
b9bec74b 2906 }
ab443475 2907 /* must be before kvm_put_msrs */
1bc22652 2908 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 2909 if (ret < 0) {
2910 return ret;
2911 }
1bc22652 2912 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 2913 if (ret < 0) {
05330448 2914 return ret;
b9bec74b 2915 }
4fadfa00
PH		 2916 ret = kvm_put_vcpu_events(x86_cpu, level);
2917 if (ret < 0) {
2918 return ret;
2919 }
ea643051 2920 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 2921 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 2922 if (ret < 0) {
680c1c6f
JK		 2923 return ret;
2924 }
ea643051 2925 }
7477cd38
MT		 2926
2927 ret = kvm_put_tscdeadline_msr(x86_cpu);
2928 if (ret < 0) {
2929 return ret;
2930 }
1bc22652 2931 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 2932 if (ret < 0) {
b0b1d690 2933 return ret;
b9bec74b 2934 }
b0b1d690 2935 /* must be last */
1bc22652 2936 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 2937 if (ret < 0) {
ff44f1a3 2938 return ret;
b9bec74b 2939 }
05330448
AL		 2940 return 0;
2941}
2942
20d695a9 2943int kvm_arch_get_registers(CPUState *cs)
05330448 2944{
20d695a9 2945 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 2946 int ret;
2947
20d695a9 2948 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 2949
4fadfa00 2950 ret = kvm_get_vcpu_events(cpu);
b9bec74b 2951 if (ret < 0) {
f4f1110e 2952 goto out;
b9bec74b 2953 }
4fadfa00
PH		 2954 /*
2955 * KVM_GET_MPSTATE can modify CS and RIP, call it before
2956 * KVM_GET_REGS and KVM_GET_SREGS.
2957 */
2958 ret = kvm_get_mp_state(cpu);
b9bec74b 2959 if (ret < 0) {
f4f1110e 2960 goto out;
b9bec74b 2961 }
4fadfa00 2962 ret = kvm_getput_regs(cpu, 0);
b9bec74b 2963 if (ret < 0) {
f4f1110e 2964 goto out;
b9bec74b 2965 }
4fadfa00 2966 ret = kvm_get_xsave(cpu);
b9bec74b 2967 if (ret < 0) {
f4f1110e 2968 goto out;
b9bec74b 2969 }
4fadfa00 2970 ret = kvm_get_xcrs(cpu);
b9bec74b 2971 if (ret < 0) {
f4f1110e 2972 goto out;
b9bec74b 2973 }
4fadfa00 2974 ret = kvm_get_sregs(cpu);
b9bec74b 2975 if (ret < 0) {
f4f1110e 2976 goto out;
b9bec74b 2977 }
4fadfa00 2978 ret = kvm_get_msrs(cpu);
680c1c6f 2979 if (ret < 0) {
f4f1110e 2980 goto out;
680c1c6f 2981 }
4fadfa00 2982 ret = kvm_get_apic(cpu);
b9bec74b 2983 if (ret < 0) {
f4f1110e 2984 goto out;
b9bec74b 2985 }
1bc22652 2986 ret = kvm_get_debugregs(cpu);
b9bec74b 2987 if (ret < 0) {
f4f1110e 2988 goto out;
b9bec74b 2989 }
f4f1110e
RH		 2990 ret = 0;
2991 out:
2992 cpu_sync_bndcs_hflags(&cpu->env);
2993 return ret;
05330448
AL		 2994}
2995
20d695a9 2996void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 2997{
20d695a9
AF		 2998 X86CPU *x86_cpu = X86_CPU(cpu);
2999 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3000 int ret;
3001
276ce815 3002 /* Inject NMI */
fc12d72e
PB		 3003 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3004 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3005 qemu_mutex_lock_iothread();
3006 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3007 qemu_mutex_unlock_iothread();
3008 DPRINTF("injected NMI\n");
3009 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3010 if (ret < 0) {
3011 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3012 strerror(-ret));
3013 }
3014 }
3015 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3016 qemu_mutex_lock_iothread();
3017 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3018 qemu_mutex_unlock_iothread();
3019 DPRINTF("injected SMI\n");
3020 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3021 if (ret < 0) {
3022 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3023 strerror(-ret));
3024 }
ce377af3 3025 }
276ce815
LJ		 3026 }
3027
15eafc2e 3028 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3029 qemu_mutex_lock_iothread();
3030 }
3031
e0723c45
PB		 3032 /* Force the VCPU out of its inner loop to process any INIT requests
3033 * or (for userspace APIC, but it is cheap to combine the checks here)
3034 * pending TPR access reports.
3035 */
3036 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3037 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3038 !(env->hflags & HF_SMM_MASK)) {
3039 cpu->exit_request = 1;
3040 }
3041 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3042 cpu->exit_request = 1;
3043 }
e0723c45 3044 }
05330448 3045
15eafc2e 3046 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3047 /* Try to inject an interrupt if the guest can accept it */
3048 if (run->ready_for_interrupt_injection &&
259186a7 3049 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3050 (env->eflags & IF_MASK)) {
3051 int irq;
3052
259186a7 3053 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3054 irq = cpu_get_pic_interrupt(env);
3055 if (irq >= 0) {
3056 struct kvm_interrupt intr;
3057
3058 intr.irq = irq;
db1669bc 3059 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3060 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3061 if (ret < 0) {
3062 fprintf(stderr,
3063 "KVM: injection failed, interrupt lost (%s)\n",
3064 strerror(-ret));
3065 }
db1669bc
JK		 3066 }
3067 }
05330448 3068
db1669bc
JK		 3069 /* If we have an interrupt but the guest is not ready to receive an
3070 * interrupt, request an interrupt window exit. This will
3071 * cause a return to userspace as soon as the guest is ready to
3072 * receive interrupts. */
259186a7 3073 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3074 run->request_interrupt_window = 1;
3075 } else {
3076 run->request_interrupt_window = 0;
3077 }
3078
3079 DPRINTF("setting tpr\n");
02e51483 3080 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3081
3082 qemu_mutex_unlock_iothread();
db1669bc 3083 }
05330448
AL		 3084}
3085
4c663752 3086MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3087{
20d695a9
AF		 3088 X86CPU *x86_cpu = X86_CPU(cpu);
3089 CPUX86State *env = &x86_cpu->env;
3090
fc12d72e
PB		 3091 if (run->flags & KVM_RUN_X86_SMM) {
3092 env->hflags |= HF_SMM_MASK;
3093 } else {
f5c052b9 3094 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3095 }
b9bec74b 3096 if (run->if_flag) {
05330448 3097 env->eflags |= IF_MASK;
b9bec74b 3098 } else {
05330448 3099 env->eflags &= ~IF_MASK;
b9bec74b 3100 }
4b8523ee
JK		 3101
3102 /* We need to protect the apic state against concurrent accesses from
3103 * different threads in case the userspace irqchip is used. */
3104 if (!kvm_irqchip_in_kernel()) {
3105 qemu_mutex_lock_iothread();
3106 }
02e51483
CF		 3107 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3108 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3109 if (!kvm_irqchip_in_kernel()) {
3110 qemu_mutex_unlock_iothread();
3111 }
f794aa4a 3112 return cpu_get_mem_attrs(env);
05330448
AL		 3113}
3114
20d695a9 3115int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3116{
20d695a9
AF		 3117 X86CPU *cpu = X86_CPU(cs);
3118 CPUX86State *env = &cpu->env;
232fc23b 3119
259186a7 3120 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3121 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3122 assert(env->mcg_cap);
3123
259186a7 3124 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3125
dd1750d7 3126 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3127
3128 if (env->exception_injected == EXCP08_DBLE) {
3129 /* this means triple fault */
cf83f140 3130 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3131 cs->exit_request = 1;
ab443475
JK		 3132 return 0;
3133 }
3134 env->exception_injected = EXCP12_MCHK;
3135 env->has_error_code = 0;
3136
259186a7 3137 cs->halted = 0;
ab443475
JK		 3138 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3139 env->mp_state = KVM_MP_STATE_RUNNABLE;
3140 }
3141 }
3142
fc12d72e
PB		 3143 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3144 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3145 kvm_cpu_synchronize_state(cs);
3146 do_cpu_init(cpu);
3147 }
3148
db1669bc
JK		 3149 if (kvm_irqchip_in_kernel()) {
3150 return 0;
3151 }
3152
259186a7
AF		 3153 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3154 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3155 apic_poll_irq(cpu->apic_state);
5d62c43a 3156 }
259186a7 3157 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3158 (env->eflags & IF_MASK)) ||
259186a7
AF		 3159 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3160 cs->halted = 0;
6792a57b 3161 }
259186a7 3162 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3163 kvm_cpu_synchronize_state(cs);
232fc23b 3164 do_cpu_sipi(cpu);
0af691d7 3165 }
259186a7
AF		 3166 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3167 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3168 kvm_cpu_synchronize_state(cs);
02e51483 3169 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3170 env->tpr_access_type);
3171 }
0af691d7 3172
259186a7 3173 return cs->halted;
0af691d7
MT		 3174}
3175
839b5630 3176static int kvm_handle_halt(X86CPU *cpu)
05330448 3177{
259186a7 3178 CPUState *cs = CPU(cpu);
839b5630
AF		 3179 CPUX86State *env = &cpu->env;
3180
259186a7 3181 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3182 (env->eflags & IF_MASK)) &&
259186a7
AF		 3183 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3184 cs->halted = 1;
bb4ea393 3185 return EXCP_HLT;
05330448
AL		 3186 }
3187
bb4ea393 3188 return 0;
05330448
AL		 3189}
3190
f7575c96 3191static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3192{
f7575c96
AF		 3193 CPUState *cs = CPU(cpu);
3194 struct kvm_run *run = cs->kvm_run;
d362e757 3195
02e51483 3196 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3197 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3198 : TPR_ACCESS_READ);
3199 return 1;
3200}
3201
f17ec444 3202int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3203{
38972938 3204 static const uint8_t int3 = 0xcc;
64bf3f4e 3205
f17ec444
AF		 3206 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3207 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3208 return -EINVAL;
b9bec74b 3209 }
e22a25c9
AL		 3210 return 0;
3211}
3212
f17ec444 3213int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3214{
3215 uint8_t int3;
3216
f17ec444
AF		 3217 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3218 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3219 return -EINVAL;
b9bec74b 3220 }
e22a25c9
AL		 3221 return 0;
3222}
3223
3224static struct {
3225 target_ulong addr;
3226 int len;
3227 int type;
3228} hw_breakpoint[4];
3229
3230static int nb_hw_breakpoint;
3231
3232static int find_hw_breakpoint(target_ulong addr, int len, int type)
3233{
3234 int n;
3235
b9bec74b 3236 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3237 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3238 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3239 return n;
b9bec74b
JK		 3240 }
3241 }
e22a25c9
AL		 3242 return -1;
3243}
3244
3245int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3246 target_ulong len, int type)
3247{
3248 switch (type) {
3249 case GDB_BREAKPOINT_HW:
3250 len = 1;
3251 break;
3252 case GDB_WATCHPOINT_WRITE:
3253 case GDB_WATCHPOINT_ACCESS:
3254 switch (len) {
3255 case 1:
3256 break;
3257 case 2:
3258 case 4:
3259 case 8:
b9bec74b 3260 if (addr & (len - 1)) {
e22a25c9 3261 return -EINVAL;
b9bec74b 3262 }
e22a25c9
AL		 3263 break;
3264 default:
3265 return -EINVAL;
3266 }
3267 break;
3268 default:
3269 return -ENOSYS;
3270 }
3271
b9bec74b 3272 if (nb_hw_breakpoint == 4) {
e22a25c9 3273 return -ENOBUFS;
b9bec74b
JK		 3274 }
3275 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3276 return -EEXIST;
b9bec74b 3277 }
e22a25c9
AL		 3278 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3279 hw_breakpoint[nb_hw_breakpoint].len = len;
3280 hw_breakpoint[nb_hw_breakpoint].type = type;
3281 nb_hw_breakpoint++;
3282
3283 return 0;
3284}
3285
3286int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3287 target_ulong len, int type)
3288{
3289 int n;
3290
3291 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3292 if (n < 0) {
e22a25c9 3293 return -ENOENT;
b9bec74b 3294 }
e22a25c9
AL		 3295 nb_hw_breakpoint--;
3296 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3297
3298 return 0;
3299}
3300
3301void kvm_arch_remove_all_hw_breakpoints(void)
3302{
3303 nb_hw_breakpoint = 0;
3304}
3305
3306static CPUWatchpoint hw_watchpoint;
3307
a60f24b5 3308static int kvm_handle_debug(X86CPU *cpu,
48405526 3309 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3310{
ed2803da 3311 CPUState *cs = CPU(cpu);
a60f24b5 3312 CPUX86State *env = &cpu->env;
f2574737 3313 int ret = 0;
e22a25c9
AL		 3314 int n;
3315
3316 if (arch_info->exception == 1) {
3317 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3318 if (cs->singlestep_enabled) {
f2574737 3319 ret = EXCP_DEBUG;
b9bec74b 3320 }
e22a25c9 3321 } else {
b9bec74b
JK		 3322 for (n = 0; n < 4; n++) {
3323 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3324 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3325 case 0x0:
f2574737 3326 ret = EXCP_DEBUG;
e22a25c9
AL		 3327 break;
3328 case 0x1:
f2574737 3329 ret = EXCP_DEBUG;
ff4700b0 3330 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3331 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3332 hw_watchpoint.flags = BP_MEM_WRITE;
3333 break;
3334 case 0x3:
f2574737 3335 ret = EXCP_DEBUG;
ff4700b0 3336 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3337 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3338 hw_watchpoint.flags = BP_MEM_ACCESS;
3339 break;
3340 }
b9bec74b
JK		 3341 }
3342 }
e22a25c9 3343 }
ff4700b0 3344 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3345 ret = EXCP_DEBUG;
b9bec74b 3346 }
f2574737 3347 if (ret == 0) {
ff4700b0 3348 cpu_synchronize_state(cs);
48405526 3349 assert(env->exception_injected == -1);
b0b1d690 3350
f2574737 3351 /* pass to guest */
48405526
BS		 3352 env->exception_injected = arch_info->exception;
3353 env->has_error_code = 0;
b0b1d690 3354 }
e22a25c9 3355
f2574737 3356 return ret;
e22a25c9
AL		 3357}
3358
20d695a9 3359void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3360{
3361 const uint8_t type_code[] = {
3362 [GDB_BREAKPOINT_HW] = 0x0,
3363 [GDB_WATCHPOINT_WRITE] = 0x1,
3364 [GDB_WATCHPOINT_ACCESS] = 0x3
3365 };
3366 const uint8_t len_code[] = {
3367 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3368 };
3369 int n;
3370
a60f24b5 3371 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3372 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3373 }
e22a25c9
AL		 3374 if (nb_hw_breakpoint > 0) {
3375 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3376 dbg->arch.debugreg[7] = 0x0600;
3377 for (n = 0; n < nb_hw_breakpoint; n++) {
3378 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3379 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3380 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3381 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3382 }
3383 }
3384}
4513d923 3385
2a4dac83
JK		 3386static bool host_supports_vmx(void)
3387{
3388 uint32_t ecx, unused;
3389
3390 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3391 return ecx & CPUID_EXT_VMX;
3392}
3393
3394#define VMX_INVALID_GUEST_STATE 0x80000021
3395
20d695a9 3396int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3397{
20d695a9 3398 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3399 uint64_t code;
3400 int ret;
3401
3402 switch (run->exit_reason) {
3403 case KVM_EXIT_HLT:
3404 DPRINTF("handle_hlt\n");
4b8523ee 3405 qemu_mutex_lock_iothread();
839b5630 3406 ret = kvm_handle_halt(cpu);
4b8523ee 3407 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3408 break;
3409 case KVM_EXIT_SET_TPR:
3410 ret = 0;
3411 break;
d362e757 3412 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3413 qemu_mutex_lock_iothread();
f7575c96 3414 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3415 qemu_mutex_unlock_iothread();
d362e757 3416 break;
2a4dac83
JK		 3417 case KVM_EXIT_FAIL_ENTRY:
3418 code = run->fail_entry.hardware_entry_failure_reason;
3419 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3420 code);
3421 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3422 fprintf(stderr,
12619721 3423 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3424 "unrestricted mode\n"
3425 "support, the failure can be most likely due to the guest "
3426 "entering an invalid\n"
3427 "state for Intel VT. For example, the guest maybe running "
3428 "in big real mode\n"
3429 "which is not supported on less recent Intel processors."
3430 "\n\n");
3431 }
3432 ret = -1;
3433 break;
3434 case KVM_EXIT_EXCEPTION:
3435 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3436 run->ex.exception, run->ex.error_code);
3437 ret = -1;
3438 break;
f2574737
JK		 3439 case KVM_EXIT_DEBUG:
3440 DPRINTF("kvm_exit_debug\n");
4b8523ee 3441 qemu_mutex_lock_iothread();
a60f24b5 3442 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3443 qemu_mutex_unlock_iothread();
f2574737 3444 break;
50efe82c
AS		 3445 case KVM_EXIT_HYPERV:
3446 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3447 break;
15eafc2e
PB		 3448 case KVM_EXIT_IOAPIC_EOI:
3449 ioapic_eoi_broadcast(run->eoi.vector);
3450 ret = 0;
3451 break;
2a4dac83
JK		 3452 default:
3453 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3454 ret = -1;
3455 break;
3456 }
3457
3458 return ret;
3459}
3460
20d695a9 3461bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3462{
20d695a9
AF		 3463 X86CPU *cpu = X86_CPU(cs);
3464 CPUX86State *env = &cpu->env;
3465
dd1750d7 3466 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3467 return !(env->cr[0] & CR0_PE_MASK) ||
3468 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3469}
84b058d7
JK		 3470
3471void kvm_arch_init_irq_routing(KVMState *s)
3472{
3473 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3474 /* If kernel can't do irq routing, interrupt source
3475 * override 0->2 cannot be set up as required by HPET.
3476 * So we have to disable it.
3477 */
3478 no_hpet = 1;
3479 }
cc7e0ddf 3480 /* We know at this point that we're using the in-kernel
614e41bc 3481 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3482 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3483 */
614e41bc 3484 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3485 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3486
3487 if (kvm_irqchip_is_split()) {
3488 int i;
3489
3490 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3491 MSI routes for signaling interrupts to the local apics. */
3492 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3493 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3494 error_report("Could not enable split IRQ mode.");
3495 exit(1);
3496 }
3497 }
3498 }
3499}
3500
3501int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3502{
3503 int ret;
3504 if (machine_kernel_irqchip_split(ms)) {
3505 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3506 if (ret) {
df3c286c 3507 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3508 strerror(-ret));
3509 exit(1);
3510 } else {
3511 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3512 kvm_split_irqchip = true;
3513 return 1;
3514 }
3515 } else {
3516 return 0;
3517 }
84b058d7 3518}
b139bd30
JK		 3519
3520/* Classic KVM device assignment interface. Will remain x86 only. */
3521int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3522 uint32_t flags, uint32_t *dev_id)
3523{
3524 struct kvm_assigned_pci_dev dev_data = {
3525 .segnr = dev_addr->domain,
3526 .busnr = dev_addr->bus,
3527 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3528 .flags = flags,
3529 };
3530 int ret;
3531
3532 dev_data.assigned_dev_id =
3533 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3534
3535 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3536 if (ret < 0) {
3537 return ret;
3538 }
3539
3540 *dev_id = dev_data.assigned_dev_id;
3541
3542 return 0;
3543}
3544
3545int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3546{
3547 struct kvm_assigned_pci_dev dev_data = {
3548 .assigned_dev_id = dev_id,
3549 };
3550
3551 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3552}
3553
3554static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3555 uint32_t irq_type, uint32_t guest_irq)
3556{
3557 struct kvm_assigned_irq assigned_irq = {
3558 .assigned_dev_id = dev_id,
3559 .guest_irq = guest_irq,
3560 .flags = irq_type,
3561 };
3562
3563 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3564 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3565 } else {
3566 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3567 }
3568}
3569
3570int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3571 uint32_t guest_irq)
3572{
3573 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3574 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3575
3576 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3577}
3578
3579int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3580{
3581 struct kvm_assigned_pci_dev dev_data = {
3582 .assigned_dev_id = dev_id,
3583 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3584 };
3585
3586 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3587}
3588
3589static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3590 uint32_t type)
3591{
3592 struct kvm_assigned_irq assigned_irq = {
3593 .assigned_dev_id = dev_id,
3594 .flags = type,
3595 };
3596
3597 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3598}
3599
3600int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3601{
3602 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3603 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3604}
3605
3606int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3607{
3608 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3609 KVM_DEV_IRQ_GUEST_MSI, virq);
3610}
3611
3612int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3613{
3614 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3615 KVM_DEV_IRQ_HOST_MSI);
3616}
3617
3618bool kvm_device_msix_supported(KVMState *s)
3619{
3620 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3621 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3622 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3623}
3624
3625int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3626 uint32_t nr_vectors)
3627{
3628 struct kvm_assigned_msix_nr msix_nr = {
3629 .assigned_dev_id = dev_id,
3630 .entry_nr = nr_vectors,
3631 };
3632
3633 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3634}
3635
3636int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3637 int virq)
3638{
3639 struct kvm_assigned_msix_entry msix_entry = {
3640 .assigned_dev_id = dev_id,
3641 .gsi = virq,
3642 .entry = vector,
3643 };
3644
3645 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3646}
3647
3648int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3649{
3650 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3651 KVM_DEV_IRQ_GUEST_MSIX, 0);
3652}
3653
3654int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3655{
3656 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3657 KVM_DEV_IRQ_HOST_MSIX);
3658}
9e03a040
FB		 3659
3660int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3661 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3662{
8b5ed7df
PX		 3663 X86IOMMUState *iommu = x86_iommu_get_default();
3664
3665 if (iommu) {
3666 int ret;
3667 MSIMessage src, dst;
3668 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3669
0ea1472d
JK		 3670 if (!class->int_remap) {
3671 return 0;
3672 }
3673
8b5ed7df
PX		 3674 src.address = route->u.msi.address_hi;
3675 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3676 src.address |= route->u.msi.address_lo;
3677 src.data = route->u.msi.data;
3678
3679 ret = class->int_remap(iommu, &src, &dst, dev ? \
3680 pci_requester_id(dev) : \
3681 X86_IOMMU_SID_INVALID);
3682 if (ret) {
3683 trace_kvm_x86_fixup_msi_error(route->gsi);
3684 return 1;
3685 }
3686
3687 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3688 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3689 route->u.msi.data = dst.data;
3690 }
3691
9e03a040
FB		 3692 return 0;
3693}
1850b6b7 3694
38d87493
PX		 3695typedef struct MSIRouteEntry MSIRouteEntry;
3696
3697struct MSIRouteEntry {
3698 PCIDevice *dev; /* Device pointer */
3699 int vector; /* MSI/MSIX vector index */
3700 int virq; /* Virtual IRQ index */
3701 QLIST_ENTRY(MSIRouteEntry) list;
3702};
3703
3704/* List of used GSI routes */
3705static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3706 QLIST_HEAD_INITIALIZER(msi_route_list);
3707
e1d4fb2d
PX		 3708static void kvm_update_msi_routes_all(void *private, bool global,
3709 uint32_t index, uint32_t mask)
3710{
3711 int cnt = 0;
3712 MSIRouteEntry *entry;
3713 MSIMessage msg;
fd563564
PX		 3714 PCIDevice *dev;
3715
e1d4fb2d
PX		 3716 /* TODO: explicit route update */
3717 QLIST_FOREACH(entry, &msi_route_list, list) {
3718 cnt++;
fd563564
PX		 3719 dev = entry->dev;
3720 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3721 continue;
3722 }
3723 msg = pci_get_msi_message(dev, entry->vector);
3724 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3725 }
3f1fea0f 3726 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3727 trace_kvm_x86_update_msi_routes(cnt);
3728}
3729
38d87493
PX		 3730int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3731 int vector, PCIDevice *dev)
3732{
e1d4fb2d 3733 static bool notify_list_inited = false;
38d87493
PX		 3734 MSIRouteEntry *entry;
3735
3736 if (!dev) {
3737 /* These are (possibly) IOAPIC routes only used for split
3738 * kernel irqchip mode, while what we are housekeeping are
3739 * PCI devices only. */
3740 return 0;
3741 }
3742
3743 entry = g_new0(MSIRouteEntry, 1);
3744 entry->dev = dev;
3745 entry->vector = vector;
3746 entry->virq = route->gsi;
3747 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3748
3749 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3750
3751 if (!notify_list_inited) {
3752 /* For the first time we do add route, add ourselves into
3753 * IOMMU's IEC notify list if needed. */
3754 X86IOMMUState *iommu = x86_iommu_get_default();
3755 if (iommu) {
3756 x86_iommu_iec_register_notifier(iommu,
3757 kvm_update_msi_routes_all,
3758 NULL);
3759 }
3760 notify_list_inited = true;
3761 }
38d87493
PX		 3762 return 0;
3763}
3764
3765int kvm_arch_release_virq_post(int virq)
3766{
3767 MSIRouteEntry *entry, *next;
3768 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3769 if (entry->virq == virq) {
3770 trace_kvm_x86_remove_msi_route(virq);
3771 QLIST_REMOVE(entry, list);
01960e6d 3772 g_free(entry);
38d87493
PX		 3773 break;
3774 }
3775 }
9e03a040
FB		 3776 return 0;
3777}
1850b6b7
EA		 3778
3779int kvm_arch_msi_data_to_gsi(uint32_t data)
3780{
3781 abort();
3782}
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