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target/i386: kvm: Add support for save and restore nested state
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c 28#include "hyperv.h"
5e953812 29#include "hyperv-proto.h"
50efe82c 30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
a2cb15b0 42#include "hw/pci/pci.h"
15eafc2e 43#include "hw/pci/msi.h"
fd563564 44#include "hw/pci/msix.h"
795c40b8 45#include "migration/blocker.h"
4c663752 46#include "exec/memattrs.h"
8b5ed7df 47#include "trace.h"
05330448
AL		 48
49//#define DEBUG_KVM
50
51#ifdef DEBUG_KVM
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54#else
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { } while (0)
57#endif
58
1a03675d
GC		 59#define MSR_KVM_WALL_CLOCK 0x11
60#define MSR_KVM_SYSTEM_TIME 0x12
61
d1138251
EH		 62/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64#define MSR_BUF_SIZE 4096
d71b62a1 65
94a8d39a
JK		 66const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71};
25d2e361 72
c3a3a7d3
JK		 73static bool has_msr_star;
74static bool has_msr_hsave_pa;
c9b8f6b6 75static bool has_msr_tsc_aux;
f28558d3 76static bool has_msr_tsc_adjust;
aa82ba54 77static bool has_msr_tsc_deadline;
df67696e 78static bool has_msr_feature_control;
21e87c46 79static bool has_msr_misc_enable;
fc12d72e 80static bool has_msr_smbase;
79e9ebeb 81static bool has_msr_bndcfgs;
25d2e361 82static int lm_capable_kernel;
7bc3d711 83static bool has_msr_hv_hypercall;
f2a53c9e 84static bool has_msr_hv_crash;
744b8a94 85static bool has_msr_hv_reset;
8c145d7c 86static bool has_msr_hv_vpindex;
e9688fab 87static bool hv_vpindex_settable;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
aec5e9c3 97static bool has_msr_arch_capabs;
597360c0 98static bool has_msr_core_capabs;
b827df58 99
0b368a10
JD		 100static uint32_t has_architectural_pmu_version;
101static uint32_t num_architectural_pmu_gp_counters;
102static uint32_t num_architectural_pmu_fixed_counters;
0d894367 103
28143b40
TH		 104static int has_xsave;
105static int has_xcrs;
106static int has_pit_state2;
107
87f8b626
AR		 108static bool has_msr_mcg_ext_ctl;
109
494e95e9 110static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 111static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 112
28143b40
TH		 113int kvm_has_pit_state2(void)
114{
115 return has_pit_state2;
116}
117
355023f2
PB		 118bool kvm_has_smm(void)
119{
120 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
121}
122
6053a86f
MT		 123bool kvm_has_adjust_clock_stable(void)
124{
125 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
126
127 return (ret == KVM_CLOCK_TSC_STABLE);
128}
129
1d31f66b
PM		 130bool kvm_allows_irq0_override(void)
131{
132 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
133}
134
fb506e70
RK		 135static bool kvm_x2apic_api_set_flags(uint64_t flags)
136{
137 KVMState *s = KVM_STATE(current_machine->accelerator);
138
139 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
140}
141
e391c009 142#define MEMORIZE(fn, _result) \
2a138ec3 143 ({ \
2a138ec3
RK		 144 static bool _memorized; \
145 \
146 if (_memorized) { \
147 return _result; \
148 } \
149 _memorized = true; \
150 _result = fn; \
151 })
152
e391c009
IM		 153static bool has_x2apic_api;
154
155bool kvm_has_x2apic_api(void)
156{
157 return has_x2apic_api;
158}
159
fb506e70
RK		 160bool kvm_enable_x2apic(void)
161{
2a138ec3
RK		 162 return MEMORIZE(
163 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 164 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
165 has_x2apic_api);
fb506e70
RK		 166}
167
e9688fab
RK		 168bool kvm_hv_vpindex_settable(void)
169{
170 return hv_vpindex_settable;
171}
172
0fd7e098
LL		 173static int kvm_get_tsc(CPUState *cs)
174{
175 X86CPU *cpu = X86_CPU(cs);
176 CPUX86State *env = &cpu->env;
177 struct {
178 struct kvm_msrs info;
179 struct kvm_msr_entry entries[1];
180 } msr_data;
181 int ret;
182
183 if (env->tsc_valid) {
184 return 0;
185 }
186
187 msr_data.info.nmsrs = 1;
188 msr_data.entries[0].index = MSR_IA32_TSC;
189 env->tsc_valid = !runstate_is_running();
190
191 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
192 if (ret < 0) {
193 return ret;
194 }
195
48e1a45c 196 assert(ret == 1);
0fd7e098
LL		 197 env->tsc = msr_data.entries[0].data;
198 return 0;
199}
200
14e6fe12 201static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 202{
0fd7e098
LL		 203 kvm_get_tsc(cpu);
204}
205
206void kvm_synchronize_all_tsc(void)
207{
208 CPUState *cpu;
209
210 if (kvm_enabled()) {
211 CPU_FOREACH(cpu) {
14e6fe12 212 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 213 }
214 }
215}
216
b827df58
AK		 217static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
218{
219 struct kvm_cpuid2 *cpuid;
220 int r, size;
221
222 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 223 cpuid = g_malloc0(size);
b827df58
AK		 224 cpuid->nent = max;
225 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 226 if (r == 0 && cpuid->nent >= max) {
227 r = -E2BIG;
228 }
b827df58
AK		 229 if (r < 0) {
230 if (r == -E2BIG) {
7267c094 231 g_free(cpuid);
b827df58
AK		 232 return NULL;
233 } else {
234 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
235 strerror(-r));
236 exit(1);
237 }
238 }
239 return cpuid;
240}
241
dd87f8a6
EH		 242/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
243 * for all entries.
244 */
245static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
246{
247 struct kvm_cpuid2 *cpuid;
248 int max = 1;
494e95e9
CP		 249
250 if (cpuid_cache != NULL) {
251 return cpuid_cache;
252 }
dd87f8a6
EH		 253 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
254 max *= 2;
255 }
494e95e9 256 cpuid_cache = cpuid;
dd87f8a6
EH		 257 return cpuid;
258}
259
a443bc34 260static const struct kvm_para_features {
0c31b744
GC		 261 int cap;
262 int feature;
263} para_features[] = {
264 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
265 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
266 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 267 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 268};
269
ba9bc59e 270static int get_para_features(KVMState *s)
0c31b744
GC		 271{
272 int i, features = 0;
273
8e03c100 274 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 275 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 276 features |= (1 << para_features[i].feature);
277 }
278 }
279
280 return features;
281}
0c31b744 282
40e80ee4
EH		 283static bool host_tsx_blacklisted(void)
284{
285 int family, model, stepping;\
286 char vendor[CPUID_VENDOR_SZ + 1];
287
288 host_vendor_fms(vendor, &family, &model, &stepping);
289
290 /* Check if we are running on a Haswell host known to have broken TSX */
291 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
292 (family == 6) &&
293 ((model == 63 && stepping < 4) ||
294 model == 60 || model == 69 || model == 70);
295}
0c31b744 296
829ae2f9
EH		 297/* Returns the value for a specific register on the cpuid entry
298 */
299static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
300{
301 uint32_t ret = 0;
302 switch (reg) {
303 case R_EAX:
304 ret = entry->eax;
305 break;
306 case R_EBX:
307 ret = entry->ebx;
308 break;
309 case R_ECX:
310 ret = entry->ecx;
311 break;
312 case R_EDX:
313 ret = entry->edx;
314 break;
315 }
316 return ret;
317}
318
4fb73f1d
EH		 319/* Find matching entry for function/index on kvm_cpuid2 struct
320 */
321static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
322 uint32_t function,
323 uint32_t index)
324{
325 int i;
326 for (i = 0; i < cpuid->nent; ++i) {
327 if (cpuid->entries[i].function == function &&
328 cpuid->entries[i].index == index) {
329 return &cpuid->entries[i];
330 }
331 }
332 /* not found: */
333 return NULL;
334}
335
ba9bc59e 336uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 337 uint32_t index, int reg)
b827df58
AK		 338{
339 struct kvm_cpuid2 *cpuid;
b827df58
AK		 340 uint32_t ret = 0;
341 uint32_t cpuid_1_edx;
8c723b79 342 bool found = false;
b827df58 343
dd87f8a6 344 cpuid = get_supported_cpuid(s);
b827df58 345
4fb73f1d
EH		 346 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
347 if (entry) {
348 found = true;
349 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 350 }
351
7b46e5ce
EH		 352 /* Fixups for the data returned by KVM, below */
353
c2acb022
EH		 354 if (function == 1 && reg == R_EDX) {
355 /* KVM before 2.6.30 misreports the following features */
356 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 357 } else if (function == 1 && reg == R_ECX) {
358 /* We can set the hypervisor flag, even if KVM does not return it on
359 * GET_SUPPORTED_CPUID
360 */
361 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 362 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
363 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
364 * and the irqchip is in the kernel.
365 */
366 if (kvm_irqchip_in_kernel() &&
367 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
368 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
369 }
41e5e76d
EH		 370
371 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
372 * without the in-kernel irqchip
373 */
374 if (!kvm_irqchip_in_kernel()) {
375 ret &= ~CPUID_EXT_X2APIC;
b827df58 376 }
2266d443
MT		 377
378 if (enable_cpu_pm) {
379 int disable_exits = kvm_check_extension(s,
380 KVM_CAP_X86_DISABLE_EXITS);
381
382 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
383 ret |= CPUID_EXT_MONITOR;
384 }
385 }
28b8e4d0
JK		 386 } else if (function == 6 && reg == R_EAX) {
387 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 388 } else if (function == 7 && index == 0 && reg == R_EBX) {
389 if (host_tsx_blacklisted()) {
390 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
391 }
485b1d25
EH		 392 } else if (function == 7 && index == 0 && reg == R_EDX) {
393 /*
394 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
395 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
396 * returned by KVM_GET_MSR_INDEX_LIST.
397 */
398 if (!has_msr_arch_capabs) {
399 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
400 }
f98bbd83
BM		 401 } else if (function == 0x80000001 && reg == R_ECX) {
402 /*
403 * It's safe to enable TOPOEXT even if it's not returned by
404 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
405 * us to keep CPU models including TOPOEXT runnable on older kernels.
406 */
407 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 408 } else if (function == 0x80000001 && reg == R_EDX) {
409 /* On Intel, kvm returns cpuid according to the Intel spec,
410 * so add missing bits according to the AMD spec:
411 */
412 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
413 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 414 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
415 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
416 * be enabled without the in-kernel irqchip
417 */
418 if (!kvm_irqchip_in_kernel()) {
419 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
420 }
be777326 421 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 422 ret |= 1U << KVM_HINTS_REALTIME;
be777326 423 found = 1;
b827df58
AK		 424 }
425
0c31b744 426 /* fallback for older kernels */
8c723b79 427 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 428 ret = get_para_features(s);
b9bec74b 429 }
0c31b744
GC		 430
431 return ret;
bb0300dc 432}
bb0300dc 433
f57bceb6
RH		 434uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
435{
436 struct {
437 struct kvm_msrs info;
438 struct kvm_msr_entry entries[1];
439 } msr_data;
440 uint32_t ret;
441
442 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
443 return 0;
444 }
445
446 /* Check if requested MSR is supported feature MSR */
447 int i;
448 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
449 if (kvm_feature_msrs->indices[i] == index) {
450 break;
451 }
452 if (i == kvm_feature_msrs->nmsrs) {
453 return 0; /* if the feature MSR is not supported, simply return 0 */
454 }
455
456 msr_data.info.nmsrs = 1;
457 msr_data.entries[0].index = index;
458
459 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
460 if (ret != 1) {
461 error_report("KVM get MSR (index=0x%x) feature failed, %s",
462 index, strerror(-ret));
463 exit(1);
464 }
465
466 return msr_data.entries[0].data;
467}
468
469
3c85e74f
HY		 470typedef struct HWPoisonPage {
471 ram_addr_t ram_addr;
472 QLIST_ENTRY(HWPoisonPage) list;
473} HWPoisonPage;
474
475static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
476 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
477
478static void kvm_unpoison_all(void *param)
479{
480 HWPoisonPage *page, *next_page;
481
482 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
483 QLIST_REMOVE(page, list);
484 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 485 g_free(page);
3c85e74f
HY		 486 }
487}
488
3c85e74f
HY		 489static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
490{
491 HWPoisonPage *page;
492
493 QLIST_FOREACH(page, &hwpoison_page_list, list) {
494 if (page->ram_addr == ram_addr) {
495 return;
496 }
497 }
ab3ad07f 498 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 499 page->ram_addr = ram_addr;
500 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
501}
502
e7701825
MT		 503static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
504 int *max_banks)
505{
506 int r;
507
14a09518 508 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 509 if (r > 0) {
510 *max_banks = r;
511 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
512 }
513 return -ENOSYS;
514}
515
bee615d4 516static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 517{
87f8b626 518 CPUState *cs = CPU(cpu);
bee615d4 519 CPUX86State *env = &cpu->env;
c34d440a
JK		 520 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
521 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
522 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 523 int flags = 0;
e7701825 524
c34d440a
JK		 525 if (code == BUS_MCEERR_AR) {
526 status |= MCI_STATUS_AR | 0x134;
527 mcg_status |= MCG_STATUS_EIPV;
528 } else {
529 status |= 0xc0;
530 mcg_status |= MCG_STATUS_RIPV;
419fb20a 531 }
87f8b626
AR		 532
533 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
534 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
535 * guest kernel back into env->mcg_ext_ctl.
536 */
537 cpu_synchronize_state(cs);
538 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
539 mcg_status |= MCG_STATUS_LMCE;
540 flags = 0;
541 }
542
8c5cf3b6 543 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 544 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 545}
419fb20a
JK		 546
547static void hardware_memory_error(void)
548{
549 fprintf(stderr, "Hardware memory error!\n");
550 exit(1);
551}
552
2ae41db2 553void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 554{
20d695a9
AF		 555 X86CPU *cpu = X86_CPU(c);
556 CPUX86State *env = &cpu->env;
419fb20a 557 ram_addr_t ram_addr;
a8170e5e 558 hwaddr paddr;
419fb20a 559
4d39892c
PB		 560 /* If we get an action required MCE, it has been injected by KVM
561 * while the VM was running. An action optional MCE instead should
562 * be coming from the main thread, which qemu_init_sigbus identifies
563 * as the "early kill" thread.
564 */
a16fc07e 565 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 566
20e0ff59 567 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 568 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 569 if (ram_addr != RAM_ADDR_INVALID &&
570 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
571 kvm_hwpoison_page_add(ram_addr);
572 kvm_mce_inject(cpu, paddr, code);
2ae41db2 573 return;
419fb20a 574 }
20e0ff59
PB		 575
576 fprintf(stderr, "Hardware memory error for memory used by "
577 "QEMU itself instead of guest system!\n");
419fb20a 578 }
20e0ff59
PB		 579
580 if (code == BUS_MCEERR_AR) {
581 hardware_memory_error();
582 }
583
584 /* Hope we are lucky for AO MCE */
419fb20a
JK		 585}
586
1bc22652 587static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 588{
1bc22652
AF		 589 CPUX86State *env = &cpu->env;
590
ab443475
JK		 591 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
592 unsigned int bank, bank_num = env->mcg_cap & 0xff;
593 struct kvm_x86_mce mce;
594
595 env->exception_injected = -1;
596
597 /*
598 * There must be at least one bank in use if an MCE is pending.
599 * Find it and use its values for the event injection.
600 */
601 for (bank = 0; bank < bank_num; bank++) {
602 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
603 break;
604 }
605 }
606 assert(bank < bank_num);
607
608 mce.bank = bank;
609 mce.status = env->mce_banks[bank * 4 + 1];
610 mce.mcg_status = env->mcg_status;
611 mce.addr = env->mce_banks[bank * 4 + 2];
612 mce.misc = env->mce_banks[bank * 4 + 3];
613
1bc22652 614 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 615 }
ab443475
JK		 616 return 0;
617}
618
1dfb4dd9 619static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 620{
317ac620 621 CPUX86State *env = opaque;
b8cc45d6
GC		 622
623 if (running) {
624 env->tsc_valid = false;
625 }
626}
627
83b17af5 628unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 629{
83b17af5 630 X86CPU *cpu = X86_CPU(cs);
7e72a45c 631 return cpu->apic_id;
b164e48e
EH		 632}
633
92067bf4
IM		 634#ifndef KVM_CPUID_SIGNATURE_NEXT
635#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
636#endif
637
92067bf4
IM		 638static bool hyperv_enabled(X86CPU *cpu)
639{
7bc3d711
PB		 640 CPUState *cs = CPU(cpu);
641 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c 642 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
e48ddcc6 643 cpu->hyperv_features || cpu->hyperv_passthrough);
92067bf4
IM		 644}
645
5031283d
HZ		 646static int kvm_arch_set_tsc_khz(CPUState *cs)
647{
648 X86CPU *cpu = X86_CPU(cs);
649 CPUX86State *env = &cpu->env;
650 int r;
651
652 if (!env->tsc_khz) {
653 return 0;
654 }
655
656 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
657 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
658 -ENOTSUP;
659 if (r < 0) {
660 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
661 * TSC frequency doesn't match the one we want.
662 */
663 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
664 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
665 -ENOTSUP;
666 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 667 warn_report("TSC frequency mismatch between "
668 "VM (%" PRId64 " kHz) and host (%d kHz), "
669 "and TSC scaling unavailable",
670 env->tsc_khz, cur_freq);
5031283d
HZ		 671 return r;
672 }
673 }
674
675 return 0;
676}
677
4bb95b82
LP		 678static bool tsc_is_stable_and_known(CPUX86State *env)
679{
680 if (!env->tsc_khz) {
681 return false;
682 }
683 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
684 || env->user_tsc_khz;
685}
686
6760bd20
VK		 687static struct {
688 const char *desc;
689 struct {
690 uint32_t fw;
691 uint32_t bits;
692 } flags[2];
c6861930 693 uint64_t dependencies;
6760bd20
VK		 694} kvm_hyperv_properties[] = {
695 [HYPERV_FEAT_RELAXED] = {
696 .desc = "relaxed timing (hv-relaxed)",
697 .flags = {
698 {.fw = FEAT_HYPERV_EAX,
699 .bits = HV_HYPERCALL_AVAILABLE},
700 {.fw = FEAT_HV_RECOMM_EAX,
701 .bits = HV_RELAXED_TIMING_RECOMMENDED}
702 }
703 },
704 [HYPERV_FEAT_VAPIC] = {
705 .desc = "virtual APIC (hv-vapic)",
706 .flags = {
707 {.fw = FEAT_HYPERV_EAX,
708 .bits = HV_HYPERCALL_AVAILABLE | HV_APIC_ACCESS_AVAILABLE},
709 {.fw = FEAT_HV_RECOMM_EAX,
710 .bits = HV_APIC_ACCESS_RECOMMENDED}
711 }
712 },
713 [HYPERV_FEAT_TIME] = {
714 .desc = "clocksources (hv-time)",
715 .flags = {
716 {.fw = FEAT_HYPERV_EAX,
717 .bits = HV_HYPERCALL_AVAILABLE | HV_TIME_REF_COUNT_AVAILABLE |
718 HV_REFERENCE_TSC_AVAILABLE}
719 }
720 },
721 [HYPERV_FEAT_CRASH] = {
722 .desc = "crash MSRs (hv-crash)",
723 .flags = {
724 {.fw = FEAT_HYPERV_EDX,
725 .bits = HV_GUEST_CRASH_MSR_AVAILABLE}
726 }
727 },
728 [HYPERV_FEAT_RESET] = {
729 .desc = "reset MSR (hv-reset)",
730 .flags = {
731 {.fw = FEAT_HYPERV_EAX,
732 .bits = HV_RESET_AVAILABLE}
733 }
734 },
735 [HYPERV_FEAT_VPINDEX] = {
736 .desc = "VP_INDEX MSR (hv-vpindex)",
737 .flags = {
738 {.fw = FEAT_HYPERV_EAX,
739 .bits = HV_VP_INDEX_AVAILABLE}
740 }
741 },
742 [HYPERV_FEAT_RUNTIME] = {
743 .desc = "VP_RUNTIME MSR (hv-runtime)",
744 .flags = {
745 {.fw = FEAT_HYPERV_EAX,
746 .bits = HV_VP_RUNTIME_AVAILABLE}
747 }
748 },
749 [HYPERV_FEAT_SYNIC] = {
750 .desc = "synthetic interrupt controller (hv-synic)",
751 .flags = {
752 {.fw = FEAT_HYPERV_EAX,
753 .bits = HV_SYNIC_AVAILABLE}
754 }
755 },
756 [HYPERV_FEAT_STIMER] = {
757 .desc = "synthetic timers (hv-stimer)",
758 .flags = {
759 {.fw = FEAT_HYPERV_EAX,
760 .bits = HV_SYNTIMERS_AVAILABLE}
c6861930
VK		 761 },
762 .dependencies = BIT(HYPERV_FEAT_SYNIC) | BIT(HYPERV_FEAT_TIME)
6760bd20
VK		 763 },
764 [HYPERV_FEAT_FREQUENCIES] = {
765 .desc = "frequency MSRs (hv-frequencies)",
766 .flags = {
767 {.fw = FEAT_HYPERV_EAX,
768 .bits = HV_ACCESS_FREQUENCY_MSRS},
769 {.fw = FEAT_HYPERV_EDX,
770 .bits = HV_FREQUENCY_MSRS_AVAILABLE}
771 }
772 },
773 [HYPERV_FEAT_REENLIGHTENMENT] = {
774 .desc = "reenlightenment MSRs (hv-reenlightenment)",
775 .flags = {
776 {.fw = FEAT_HYPERV_EAX,
777 .bits = HV_ACCESS_REENLIGHTENMENTS_CONTROL}
778 }
779 },
780 [HYPERV_FEAT_TLBFLUSH] = {
781 .desc = "paravirtualized TLB flush (hv-tlbflush)",
782 .flags = {
783 {.fw = FEAT_HV_RECOMM_EAX,
784 .bits = HV_REMOTE_TLB_FLUSH_RECOMMENDED |
785 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 786 },
787 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20
VK		 788 },
789 [HYPERV_FEAT_EVMCS] = {
790 .desc = "enlightened VMCS (hv-evmcs)",
791 .flags = {
792 {.fw = FEAT_HV_RECOMM_EAX,
793 .bits = HV_ENLIGHTENED_VMCS_RECOMMENDED}
8caba36d
VK		 794 },
795 .dependencies = BIT(HYPERV_FEAT_VAPIC)
6760bd20
VK		 796 },
797 [HYPERV_FEAT_IPI] = {
798 .desc = "paravirtualized IPI (hv-ipi)",
799 .flags = {
800 {.fw = FEAT_HV_RECOMM_EAX,
801 .bits = HV_CLUSTER_IPI_RECOMMENDED |
802 HV_EX_PROCESSOR_MASKS_RECOMMENDED}
bd59fbdf
VK		 803 },
804 .dependencies = BIT(HYPERV_FEAT_VPINDEX)
6760bd20 805 },
128531d9
VK		 806 [HYPERV_FEAT_STIMER_DIRECT] = {
807 .desc = "direct mode synthetic timers (hv-stimer-direct)",
808 .flags = {
809 {.fw = FEAT_HYPERV_EDX,
810 .bits = HV_STIMER_DIRECT_MODE_AVAILABLE}
811 },
812 .dependencies = BIT(HYPERV_FEAT_STIMER)
813 },
6760bd20
VK		 814};
815
816static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max)
817{
818 struct kvm_cpuid2 *cpuid;
819 int r, size;
820
821 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
822 cpuid = g_malloc0(size);
823 cpuid->nent = max;
824
825 r = kvm_vcpu_ioctl(cs, KVM_GET_SUPPORTED_HV_CPUID, cpuid);
826 if (r == 0 && cpuid->nent >= max) {
827 r = -E2BIG;
828 }
829 if (r < 0) {
830 if (r == -E2BIG) {
831 g_free(cpuid);
832 return NULL;
833 } else {
834 fprintf(stderr, "KVM_GET_SUPPORTED_HV_CPUID failed: %s\n",
835 strerror(-r));
836 exit(1);
837 }
838 }
839 return cpuid;
840}
841
842/*
843 * Run KVM_GET_SUPPORTED_HV_CPUID ioctl(), allocating a buffer large enough
844 * for all entries.
845 */
846static struct kvm_cpuid2 *get_supported_hv_cpuid(CPUState *cs)
847{
848 struct kvm_cpuid2 *cpuid;
849 int max = 7; /* 0x40000000..0x40000005, 0x4000000A */
850
851 /*
852 * When the buffer is too small, KVM_GET_SUPPORTED_HV_CPUID fails with
853 * -E2BIG, however, it doesn't report back the right size. Keep increasing
854 * it and re-trying until we succeed.
855 */
856 while ((cpuid = try_get_hv_cpuid(cs, max)) == NULL) {
857 max++;
858 }
859 return cpuid;
860}
861
862/*
863 * When KVM_GET_SUPPORTED_HV_CPUID is not supported we fill CPUID feature
864 * leaves from KVM_CAP_HYPERV* and present MSRs data.
865 */
866static struct kvm_cpuid2 *get_supported_hv_cpuid_legacy(CPUState *cs)
c35bd19a
EY		 867{
868 X86CPU *cpu = X86_CPU(cs);
6760bd20
VK		 869 struct kvm_cpuid2 *cpuid;
870 struct kvm_cpuid_entry2 *entry_feat, *entry_recomm;
871
872 /* HV_CPUID_FEATURES, HV_CPUID_ENLIGHTMENT_INFO */
873 cpuid = g_malloc0(sizeof(*cpuid) + 2 * sizeof(*cpuid->entries));
874 cpuid->nent = 2;
875
876 /* HV_CPUID_VENDOR_AND_MAX_FUNCTIONS */
877 entry_feat = &cpuid->entries[0];
878 entry_feat->function = HV_CPUID_FEATURES;
879
880 entry_recomm = &cpuid->entries[1];
881 entry_recomm->function = HV_CPUID_ENLIGHTMENT_INFO;
882 entry_recomm->ebx = cpu->hyperv_spinlock_attempts;
883
884 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0) {
885 entry_feat->eax |= HV_HYPERCALL_AVAILABLE;
886 entry_feat->eax |= HV_APIC_ACCESS_AVAILABLE;
887 entry_feat->edx |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
888 entry_recomm->eax |= HV_RELAXED_TIMING_RECOMMENDED;
889 entry_recomm->eax |= HV_APIC_ACCESS_RECOMMENDED;
890 }
c35bd19a 891
6760bd20
VK		 892 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) > 0) {
893 entry_feat->eax |= HV_TIME_REF_COUNT_AVAILABLE;
894 entry_feat->eax |= HV_REFERENCE_TSC_AVAILABLE;
c35bd19a 895 }
6760bd20
VK		 896
897 if (has_msr_hv_frequencies) {
898 entry_feat->eax |= HV_ACCESS_FREQUENCY_MSRS;
899 entry_feat->edx |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 900 }
6760bd20
VK		 901
902 if (has_msr_hv_crash) {
903 entry_feat->edx |= HV_GUEST_CRASH_MSR_AVAILABLE;
9445597b 904 }
6760bd20
VK		 905
906 if (has_msr_hv_reenlightenment) {
907 entry_feat->eax |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
c35bd19a 908 }
6760bd20
VK		 909
910 if (has_msr_hv_reset) {
911 entry_feat->eax |= HV_RESET_AVAILABLE;
c35bd19a 912 }
6760bd20
VK		 913
914 if (has_msr_hv_vpindex) {
915 entry_feat->eax |= HV_VP_INDEX_AVAILABLE;
ba6a4fd9 916 }
6760bd20
VK		 917
918 if (has_msr_hv_runtime) {
919 entry_feat->eax |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 920 }
6760bd20
VK		 921
922 if (has_msr_hv_synic) {
923 unsigned int cap = cpu->hyperv_synic_kvm_only ?
924 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
925
926 if (kvm_check_extension(cs->kvm_state, cap) > 0) {
927 entry_feat->eax |= HV_SYNIC_AVAILABLE;
1221f150 928 }
c35bd19a 929 }
6760bd20
VK		 930
931 if (has_msr_hv_stimer) {
932 entry_feat->eax |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 933 }
9b4cf107 934
6760bd20
VK		 935 if (kvm_check_extension(cs->kvm_state,
936 KVM_CAP_HYPERV_TLBFLUSH) > 0) {
937 entry_recomm->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
938 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
939 }
c35bd19a 940
6760bd20
VK		 941 if (kvm_check_extension(cs->kvm_state,
942 KVM_CAP_HYPERV_ENLIGHTENED_VMCS) > 0) {
943 entry_recomm->eax |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
c35bd19a 944 }
6760bd20
VK		 945
946 if (kvm_check_extension(cs->kvm_state,
947 KVM_CAP_HYPERV_SEND_IPI) > 0) {
948 entry_recomm->eax |= HV_CLUSTER_IPI_RECOMMENDED;
949 entry_recomm->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
c35bd19a 950 }
6760bd20
VK		 951
952 return cpuid;
953}
954
955static int hv_cpuid_get_fw(struct kvm_cpuid2 *cpuid, int fw, uint32_t *r)
956{
957 struct kvm_cpuid_entry2 *entry;
958 uint32_t func;
959 int reg;
960
961 switch (fw) {
962 case FEAT_HYPERV_EAX:
963 reg = R_EAX;
964 func = HV_CPUID_FEATURES;
965 break;
966 case FEAT_HYPERV_EDX:
967 reg = R_EDX;
968 func = HV_CPUID_FEATURES;
969 break;
970 case FEAT_HV_RECOMM_EAX:
971 reg = R_EAX;
972 func = HV_CPUID_ENLIGHTMENT_INFO;
973 break;
974 default:
975 return -EINVAL;
a2b107db 976 }
6760bd20
VK		 977
978 entry = cpuid_find_entry(cpuid, func, 0);
979 if (!entry) {
980 return -ENOENT;
a2b107db 981 }
6760bd20
VK		 982
983 switch (reg) {
984 case R_EAX:
985 *r = entry->eax;
986 break;
987 case R_EDX:
988 *r = entry->edx;
989 break;
990 default:
991 return -EINVAL;
a2b107db 992 }
6760bd20
VK		 993
994 return 0;
995}
996
997static int hv_cpuid_check_and_set(CPUState *cs, struct kvm_cpuid2 *cpuid,
998 int feature)
999{
1000 X86CPU *cpu = X86_CPU(cs);
1001 CPUX86State *env = &cpu->env;
e48ddcc6 1002 uint32_t r, fw, bits;
c6861930
VK		 1003 uint64_t deps;
1004 int i, dep_feat = 0;
6760bd20 1005
e48ddcc6 1006 if (!hyperv_feat_enabled(cpu, feature) && !cpu->hyperv_passthrough) {
6760bd20
VK		 1007 return 0;
1008 }
1009
c6861930
VK		 1010 deps = kvm_hyperv_properties[feature].dependencies;
1011 while ((dep_feat = find_next_bit(&deps, 64, dep_feat)) < 64) {
1012 if (!(hyperv_feat_enabled(cpu, dep_feat))) {
1013 fprintf(stderr,
1014 "Hyper-V %s requires Hyper-V %s\n",
1015 kvm_hyperv_properties[feature].desc,
1016 kvm_hyperv_properties[dep_feat].desc);
1017 return 1;
1018 }
1019 dep_feat++;
1020 }
1021
6760bd20
VK		 1022 for (i = 0; i < ARRAY_SIZE(kvm_hyperv_properties[feature].flags); i++) {
1023 fw = kvm_hyperv_properties[feature].flags[i].fw;
1024 bits = kvm_hyperv_properties[feature].flags[i].bits;
1025
1026 if (!fw) {
1027 continue;
a2b107db 1028 }
6760bd20
VK		 1029
1030 if (hv_cpuid_get_fw(cpuid, fw, &r) || (r & bits) != bits) {
e48ddcc6
VK		 1031 if (hyperv_feat_enabled(cpu, feature)) {
1032 fprintf(stderr,
1033 "Hyper-V %s is not supported by kernel\n",
1034 kvm_hyperv_properties[feature].desc);
1035 return 1;
1036 } else {
1037 return 0;
1038 }
6760bd20
VK		 1039 }
1040
1041 env->features[fw] |= bits;
a2b107db 1042 }
6760bd20 1043
e48ddcc6
VK		 1044 if (cpu->hyperv_passthrough) {
1045 cpu->hyperv_features |= BIT(feature);
1046 }
1047
6760bd20
VK		 1048 return 0;
1049}
1050
2344d22e
VK		 1051/*
1052 * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_ent in
1053 * case of success, errno < 0 in case of failure and 0 when no Hyper-V
1054 * extentions are enabled.
1055 */
1056static int hyperv_handle_properties(CPUState *cs,
1057 struct kvm_cpuid_entry2 *cpuid_ent)
6760bd20
VK		 1058{
1059 X86CPU *cpu = X86_CPU(cs);
1060 CPUX86State *env = &cpu->env;
1061 struct kvm_cpuid2 *cpuid;
2344d22e
VK		 1062 struct kvm_cpuid_entry2 *c;
1063 uint32_t signature[3];
1064 uint32_t cpuid_i = 0;
e48ddcc6 1065 int r;
6760bd20 1066
2344d22e
VK		 1067 if (!hyperv_enabled(cpu))
1068 return 0;
1069
e48ddcc6
VK		 1070 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ||
1071 cpu->hyperv_passthrough) {
a2b107db
VK		 1072 uint16_t evmcs_version;
1073
e48ddcc6
VK		 1074 r = kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
1075 (uintptr_t)&evmcs_version);
1076
1077 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) && r) {
6760bd20
VK		 1078 fprintf(stderr, "Hyper-V %s is not supported by kernel\n",
1079 kvm_hyperv_properties[HYPERV_FEAT_EVMCS].desc);
a2b107db
VK		 1080 return -ENOSYS;
1081 }
e48ddcc6
VK		 1082
1083 if (!r) {
1084 env->features[FEAT_HV_RECOMM_EAX] |=
1085 HV_ENLIGHTENED_VMCS_RECOMMENDED;
1086 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
1087 }
a2b107db
VK		 1088 }
1089
6760bd20
VK		 1090 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_CPUID) > 0) {
1091 cpuid = get_supported_hv_cpuid(cs);
1092 } else {
1093 cpuid = get_supported_hv_cpuid_legacy(cs);
1094 }
1095
e48ddcc6
VK		 1096 if (cpu->hyperv_passthrough) {
1097 memcpy(cpuid_ent, &cpuid->entries[0],
1098 cpuid->nent * sizeof(cpuid->entries[0]));
1099
1100 c = cpuid_find_entry(cpuid, HV_CPUID_FEATURES, 0);
1101 if (c) {
1102 env->features[FEAT_HYPERV_EAX] = c->eax;
1103 env->features[FEAT_HYPERV_EBX] = c->ebx;
1104 env->features[FEAT_HYPERV_EDX] = c->eax;
1105 }
1106 c = cpuid_find_entry(cpuid, HV_CPUID_ENLIGHTMENT_INFO, 0);
1107 if (c) {
1108 env->features[FEAT_HV_RECOMM_EAX] = c->eax;
1109
1110 /* hv-spinlocks may have been overriden */
1111 if (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) {
1112 c->ebx = cpu->hyperv_spinlock_attempts;
1113 }
1114 }
1115 c = cpuid_find_entry(cpuid, HV_CPUID_NESTED_FEATURES, 0);
1116 if (c) {
1117 env->features[FEAT_HV_NESTED_EAX] = c->eax;
1118 }
1119 }
1120
6760bd20 1121 /* Features */
e48ddcc6 1122 r = hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RELAXED);
6760bd20
VK		 1123 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VAPIC);
1124 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TIME);
1125 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_CRASH);
1126 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RESET);
1127 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_VPINDEX);
1128 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_RUNTIME);
1129 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_SYNIC);
1130 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER);
1131 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_FREQUENCIES);
1132 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_REENLIGHTENMENT);
1133 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_TLBFLUSH);
1134 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_EVMCS);
1135 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_IPI);
128531d9 1136 r |= hv_cpuid_check_and_set(cs, cpuid, HYPERV_FEAT_STIMER_DIRECT);
6760bd20 1137
c6861930 1138 /* Additional dependencies not covered by kvm_hyperv_properties[] */
6760bd20
VK		 1139 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC) &&
1140 !cpu->hyperv_synic_kvm_only &&
1141 !hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
c6861930 1142 fprintf(stderr, "Hyper-V %s requires Hyper-V %s\n",
6760bd20
VK		 1143 kvm_hyperv_properties[HYPERV_FEAT_SYNIC].desc,
1144 kvm_hyperv_properties[HYPERV_FEAT_VPINDEX].desc);
1145 r |= 1;
1146 }
1147
1148 /* Not exposed by KVM but needed to make CPU hotplug in Windows work */
1149 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
1150
2344d22e
VK		 1151 if (r) {
1152 r = -ENOSYS;
1153 goto free;
1154 }
1155
e48ddcc6
VK		 1156 if (cpu->hyperv_passthrough) {
1157 /* We already copied all feature words from KVM as is */
1158 r = cpuid->nent;
1159 goto free;
1160 }
1161
2344d22e
VK		 1162 c = &cpuid_ent[cpuid_i++];
1163 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1164 if (!cpu->hyperv_vendor_id) {
1165 memcpy(signature, "Microsoft Hv", 12);
1166 } else {
1167 size_t len = strlen(cpu->hyperv_vendor_id);
1168
1169 if (len > 12) {
1170 error_report("hv-vendor-id truncated to 12 characters");
1171 len = 12;
1172 }
1173 memset(signature, 0, 12);
1174 memcpy(signature, cpu->hyperv_vendor_id, len);
1175 }
1176 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
1177 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
1178 c->ebx = signature[0];
1179 c->ecx = signature[1];
1180 c->edx = signature[2];
1181
1182 c = &cpuid_ent[cpuid_i++];
1183 c->function = HV_CPUID_INTERFACE;
1184 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
1185 c->eax = signature[0];
1186 c->ebx = 0;
1187 c->ecx = 0;
1188 c->edx = 0;
1189
1190 c = &cpuid_ent[cpuid_i++];
1191 c->function = HV_CPUID_VERSION;
1192 c->eax = 0x00001bbc;
1193 c->ebx = 0x00060001;
1194
1195 c = &cpuid_ent[cpuid_i++];
1196 c->function = HV_CPUID_FEATURES;
1197 c->eax = env->features[FEAT_HYPERV_EAX];
1198 c->ebx = env->features[FEAT_HYPERV_EBX];
1199 c->edx = env->features[FEAT_HYPERV_EDX];
1200
1201 c = &cpuid_ent[cpuid_i++];
1202 c->function = HV_CPUID_ENLIGHTMENT_INFO;
1203 c->eax = env->features[FEAT_HV_RECOMM_EAX];
1204 c->ebx = cpu->hyperv_spinlock_attempts;
1205
1206 c = &cpuid_ent[cpuid_i++];
1207 c->function = HV_CPUID_IMPLEMENT_LIMITS;
1208 c->eax = cpu->hv_max_vps;
1209 c->ebx = 0x40;
1210
1211 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
1212 __u32 function;
1213
1214 /* Create zeroed 0x40000006..0x40000009 leaves */
1215 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1216 function < HV_CPUID_NESTED_FEATURES; function++) {
1217 c = &cpuid_ent[cpuid_i++];
1218 c->function = function;
1219 }
1220
1221 c = &cpuid_ent[cpuid_i++];
1222 c->function = HV_CPUID_NESTED_FEATURES;
1223 c->eax = env->features[FEAT_HV_NESTED_EAX];
1224 }
1225 r = cpuid_i;
1226
1227free:
6760bd20
VK		 1228 g_free(cpuid);
1229
2344d22e 1230 return r;
c35bd19a
EY		 1231}
1232
e48ddcc6
VK		 1233static Error *hv_passthrough_mig_blocker;
1234
e9688fab
RK		 1235static int hyperv_init_vcpu(X86CPU *cpu)
1236{
729ce7e1 1237 CPUState *cs = CPU(cpu);
e48ddcc6 1238 Error *local_err = NULL;
729ce7e1
RK		 1239 int ret;
1240
e48ddcc6
VK		 1241 if (cpu->hyperv_passthrough && hv_passthrough_mig_blocker == NULL) {
1242 error_setg(&hv_passthrough_mig_blocker,
1243 "'hv-passthrough' CPU flag prevents migration, use explicit"
1244 " set of hv-* flags instead");
1245 ret = migrate_add_blocker(hv_passthrough_mig_blocker, &local_err);
1246 if (local_err) {
1247 error_report_err(local_err);
1248 error_free(hv_passthrough_mig_blocker);
1249 return ret;
1250 }
1251 }
1252
2d384d7c 1253 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 1254 /*
1255 * the kernel doesn't support setting vp_index; assert that its value
1256 * is in sync
1257 */
e9688fab
RK		 1258 struct {
1259 struct kvm_msrs info;
1260 struct kvm_msr_entry entries[1];
1261 } msr_data = {
1262 .info.nmsrs = 1,
1263 .entries[0].index = HV_X64_MSR_VP_INDEX,
1264 };
1265
729ce7e1 1266 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 1267 if (ret < 0) {
1268 return ret;
1269 }
1270 assert(ret == 1);
1271
701189e3 1272 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 1273 error_report("kernel's vp_index != QEMU's vp_index");
1274 return -ENXIO;
1275 }
1276 }
1277
2d384d7c 1278 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 1279 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
1280 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
1281 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 1282 if (ret < 0) {
1283 error_report("failed to turn on HyperV SynIC in KVM: %s",
1284 strerror(-ret));
1285 return ret;
1286 }
606c34bf 1287
9b4cf107
RK		 1288 if (!cpu->hyperv_synic_kvm_only) {
1289 ret = hyperv_x86_synic_add(cpu);
1290 if (ret < 0) {
1291 error_report("failed to create HyperV SynIC: %s",
1292 strerror(-ret));
1293 return ret;
1294 }
606c34bf 1295 }
729ce7e1
RK		 1296 }
1297
e9688fab
RK		 1298 return 0;
1299}
1300
68bfd0ad 1301static Error *invtsc_mig_blocker;
18ab37ba 1302static Error *nested_virt_mig_blocker;
68bfd0ad 1303
f8bb0565 1304#define KVM_MAX_CPUID_ENTRIES 100
0893d460 1305
20d695a9 1306int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 1307{
1308 struct {
486bd5a2 1309 struct kvm_cpuid2 cpuid;
f8bb0565 1310 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 1311 } cpuid_data;
1312 /*
1313 * The kernel defines these structs with padding fields so there
1314 * should be no extra padding in our cpuid_data struct.
1315 */
1316 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
1317 sizeof(struct kvm_cpuid2) +
1318 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
1319
20d695a9
AF		 1320 X86CPU *cpu = X86_CPU(cs);
1321 CPUX86State *env = &cpu->env;
486bd5a2 1322 uint32_t limit, i, j, cpuid_i;
a33609ca 1323 uint32_t unused;
bb0300dc 1324 struct kvm_cpuid_entry2 *c;
bb0300dc 1325 uint32_t signature[3];
234cc647 1326 int kvm_base = KVM_CPUID_SIGNATURE;
ebbfef2f 1327 int max_nested_state_len;
e7429073 1328 int r;
fe44dc91 1329 Error *local_err = NULL;
05330448 1330
ef4cbe14
SW		 1331 memset(&cpuid_data, 0, sizeof(cpuid_data));
1332
05330448
AL		 1333 cpuid_i = 0;
1334
ddb98b5a
LP		 1335 r = kvm_arch_set_tsc_khz(cs);
1336 if (r < 0) {
6b2341ee 1337 return r;
ddb98b5a
LP		 1338 }
1339
1340 /* vcpu's TSC frequency is either specified by user, or following
1341 * the value used by KVM if the former is not present. In the
1342 * latter case, we query it from KVM and record in env->tsc_khz,
1343 * so that vcpu's TSC frequency can be migrated later via this field.
1344 */
1345 if (!env->tsc_khz) {
1346 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
1347 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
1348 -ENOTSUP;
1349 if (r > 0) {
1350 env->tsc_khz = r;
1351 }
1352 }
1353
bb0300dc 1354 /* Paravirtualization CPUIDs */
2344d22e
VK		 1355 r = hyperv_handle_properties(cs, cpuid_data.entries);
1356 if (r < 0) {
1357 return r;
1358 } else if (r > 0) {
1359 cpuid_i = r;
234cc647 1360 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1361 has_msr_hv_hypercall = true;
eab70139
VR		 1362 }
1363
f522d2ac
AW		 1364 if (cpu->expose_kvm) {
1365 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1366 c = &cpuid_data.entries[cpuid_i++];
1367 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1368 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1369 c->ebx = signature[0];
1370 c->ecx = signature[1];
1371 c->edx = signature[2];
234cc647 1372
f522d2ac
AW		 1373 c = &cpuid_data.entries[cpuid_i++];
1374 c->function = KVM_CPUID_FEATURES | kvm_base;
1375 c->eax = env->features[FEAT_KVM];
be777326 1376 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1377 }
917367aa 1378
a33609ca 1379 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1380
1381 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1382 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1383 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1384 abort();
1385 }
bb0300dc 1386 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1387
1388 switch (i) {
a36b1029
AL		 1389 case 2: {
1390 /* Keep reading function 2 till all the input is received */
1391 int times;
1392
a36b1029 1393 c->function = i;
a33609ca
AL		 1394 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1395 KVM_CPUID_FLAG_STATE_READ_NEXT;
1396 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1397 times = c->eax & 0xff;
a36b1029
AL		 1398
1399 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1400 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1401 fprintf(stderr, "cpuid_data is full, no space for "
1402 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1403 abort();
1404 }
a33609ca 1405 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1406 c->function = i;
a33609ca
AL		 1407 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1408 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1409 }
1410 break;
1411 }
486bd5a2
AL		 1412 case 4:
1413 case 0xb:
1414 case 0xd:
1415 for (j = 0; ; j++) {
31e8c696
AP		 1416 if (i == 0xd && j == 64) {
1417 break;
1418 }
486bd5a2
AL		 1419 c->function = i;
1420 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1421 c->index = j;
a33609ca 1422 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1423
b9bec74b 1424 if (i == 4 && c->eax == 0) {
486bd5a2 1425 break;
b9bec74b
JK		 1426 }
1427 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1428 break;
b9bec74b
JK		 1429 }
1430 if (i == 0xd && c->eax == 0) {
31e8c696 1431 continue;
b9bec74b 1432 }
f8bb0565
IM		 1433 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1434 fprintf(stderr, "cpuid_data is full, no space for "
1435 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1436 abort();
1437 }
a33609ca 1438 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1439 }
1440 break;
e37a5c7f
CP		 1441 case 0x14: {
1442 uint32_t times;
1443
1444 c->function = i;
1445 c->index = 0;
1446 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1447 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1448 times = c->eax;
1449
1450 for (j = 1; j <= times; ++j) {
1451 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1452 fprintf(stderr, "cpuid_data is full, no space for "
1453 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1454 abort();
1455 }
1456 c = &cpuid_data.entries[cpuid_i++];
1457 c->function = i;
1458 c->index = j;
1459 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1460 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1461 }
1462 break;
1463 }
486bd5a2 1464 default:
486bd5a2 1465 c->function = i;
a33609ca
AL		 1466 c->flags = 0;
1467 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1468 break;
1469 }
05330448 1470 }
0d894367
PB		 1471
1472 if (limit >= 0x0a) {
0b368a10 1473 uint32_t eax, edx;
0d894367 1474
0b368a10
JD		 1475 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1476
1477 has_architectural_pmu_version = eax & 0xff;
1478 if (has_architectural_pmu_version > 0) {
1479 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1480
1481 /* Shouldn't be more than 32, since that's the number of bits
1482 * available in EBX to tell us _which_ counters are available.
1483 * Play it safe.
1484 */
0b368a10
JD		 1485 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1486 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1487 }
1488
1489 if (has_architectural_pmu_version > 1) {
1490 num_architectural_pmu_fixed_counters = edx & 0x1f;
1491
1492 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1493 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1494 }
0d894367
PB		 1495 }
1496 }
1497 }
1498
a33609ca 1499 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1500
1501 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1502 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1503 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1504 abort();
1505 }
bb0300dc 1506 c = &cpuid_data.entries[cpuid_i++];
05330448 1507
8f4202fb
BM		 1508 switch (i) {
1509 case 0x8000001d:
1510 /* Query for all AMD cache information leaves */
1511 for (j = 0; ; j++) {
1512 c->function = i;
1513 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1514 c->index = j;
1515 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1516
1517 if (c->eax == 0) {
1518 break;
1519 }
1520 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1521 fprintf(stderr, "cpuid_data is full, no space for "
1522 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1523 abort();
1524 }
1525 c = &cpuid_data.entries[cpuid_i++];
1526 }
1527 break;
1528 default:
1529 c->function = i;
1530 c->flags = 0;
1531 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1532 break;
1533 }
05330448
AL		 1534 }
1535
b3baa152
BW		 1536 /* Call Centaur's CPUID instructions they are supported. */
1537 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1538 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1539
1540 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1541 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1542 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1543 abort();
1544 }
b3baa152
BW		 1545 c = &cpuid_data.entries[cpuid_i++];
1546
1547 c->function = i;
1548 c->flags = 0;
1549 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1550 }
1551 }
1552
05330448
AL		 1553 cpuid_data.cpuid.nent = cpuid_i;
1554
e7701825 1555 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1556 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1557 (CPUID_MCE | CPUID_MCA)
a60f24b5 1558 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1559 uint64_t mcg_cap, unsupported_caps;
e7701825 1560 int banks;
32a42024 1561 int ret;
e7701825 1562
a60f24b5 1563 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1564 if (ret < 0) {
1565 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1566 return ret;
e7701825 1567 }
75d49497 1568
2590f15b 1569 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1570 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1571 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1572 return -ENOTSUP;
75d49497 1573 }
49b69cbf 1574
5120901a
EH		 1575 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1576 if (unsupported_caps) {
87f8b626
AR		 1577 if (unsupported_caps & MCG_LMCE_P) {
1578 error_report("kvm: LMCE not supported");
1579 return -ENOTSUP;
1580 }
3dc6f869
AF		 1581 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1582 unsupported_caps);
5120901a
EH		 1583 }
1584
2590f15b
EH		 1585 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1586 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1587 if (ret < 0) {
1588 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1589 return ret;
1590 }
e7701825 1591 }
e7701825 1592
b8cc45d6
GC		 1593 qemu_add_vm_change_state_handler(cpu_update_state, env);
1594
df67696e
LJ		 1595 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1596 if (c) {
1597 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1598 !!(c->ecx & CPUID_EXT_SMX);
1599 }
1600
18ab37ba
LA		 1601 if (cpu_has_nested_virt(env) && !nested_virt_mig_blocker) {
1602 error_setg(&nested_virt_mig_blocker,
1603 "Nested virtualization does not support live migration yet");
1604 r = migrate_add_blocker(nested_virt_mig_blocker, &local_err);
d98f2607
PB		 1605 if (local_err) {
1606 error_report_err(local_err);
18ab37ba 1607 error_free(nested_virt_mig_blocker);
d98f2607
PB		 1608 return r;
1609 }
1610 }
1611
87f8b626
AR		 1612 if (env->mcg_cap & MCG_LMCE_P) {
1613 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1614 }
1615
d99569d9
EH		 1616 if (!env->user_tsc_khz) {
1617 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1618 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1619 error_setg(&invtsc_mig_blocker,
1620 "State blocked by non-migratable CPU device"
1621 " (invtsc flag)");
fe44dc91
AA		 1622 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1623 if (local_err) {
1624 error_report_err(local_err);
1625 error_free(invtsc_mig_blocker);
6b2341ee 1626 goto fail2;
fe44dc91 1627 }
d99569d9 1628 }
68bfd0ad
MT		 1629 }
1630
9954a158
PDJ		 1631 if (cpu->vmware_cpuid_freq
1632 /* Guests depend on 0x40000000 to detect this feature, so only expose
1633 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1634 && cpu->expose_kvm
1635 && kvm_base == KVM_CPUID_SIGNATURE
1636 /* TSC clock must be stable and known for this feature. */
4bb95b82 1637 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1638
1639 c = &cpuid_data.entries[cpuid_i++];
1640 c->function = KVM_CPUID_SIGNATURE | 0x10;
1641 c->eax = env->tsc_khz;
1642 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1643 * APIC_BUS_CYCLE_NS */
1644 c->ebx = 1000000;
1645 c->ecx = c->edx = 0;
1646
1647 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1648 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1649 }
1650
1651 cpuid_data.cpuid.nent = cpuid_i;
1652
1653 cpuid_data.cpuid.padding = 0;
1654 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1655 if (r) {
1656 goto fail;
1657 }
1658
28143b40 1659 if (has_xsave) {
5b8063c4 1660 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1661 }
ebbfef2f
LA		 1662
1663 max_nested_state_len = kvm_max_nested_state_length();
1664 if (max_nested_state_len > 0) {
1665 assert(max_nested_state_len >= offsetof(struct kvm_nested_state, data));
1666 env->nested_state = g_malloc0(max_nested_state_len);
1667
1668 env->nested_state->size = max_nested_state_len;
1669
1670 if (IS_INTEL_CPU(env)) {
1671 struct kvm_vmx_nested_state_hdr *vmx_hdr =
1672 &env->nested_state->hdr.vmx;
1673
1674 env->nested_state->format = KVM_STATE_NESTED_FORMAT_VMX;
1675 vmx_hdr->vmxon_pa = -1ull;
1676 vmx_hdr->vmcs12_pa = -1ull;
1677 }
1678 }
1679
d71b62a1 1680 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1681
273c515c
PB		 1682 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1683 has_msr_tsc_aux = false;
1684 }
d1ae67f6 1685
e9688fab
RK		 1686 r = hyperv_init_vcpu(cpu);
1687 if (r) {
1688 goto fail;
1689 }
1690
e7429073 1691 return 0;
fe44dc91
AA		 1692
1693 fail:
1694 migrate_del_blocker(invtsc_mig_blocker);
6b2341ee 1695 fail2:
18ab37ba 1696 migrate_del_blocker(nested_virt_mig_blocker);
6b2341ee 1697
fe44dc91 1698 return r;
05330448
AL		 1699}
1700
b1115c99
LA		 1701int kvm_arch_destroy_vcpu(CPUState *cs)
1702{
1703 X86CPU *cpu = X86_CPU(cs);
ebbfef2f 1704 CPUX86State *env = &cpu->env;
b1115c99
LA		 1705
1706 if (cpu->kvm_msr_buf) {
1707 g_free(cpu->kvm_msr_buf);
1708 cpu->kvm_msr_buf = NULL;
1709 }
1710
ebbfef2f
LA		 1711 if (env->nested_state) {
1712 g_free(env->nested_state);
1713 env->nested_state = NULL;
1714 }
1715
b1115c99
LA		 1716 return 0;
1717}
1718
50a2c6e5 1719void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1720{
20d695a9 1721 CPUX86State *env = &cpu->env;
dd673288 1722
1a5e9d2f 1723 env->xcr0 = 1;
ddced198 1724 if (kvm_irqchip_in_kernel()) {
dd673288 1725 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1726 KVM_MP_STATE_UNINITIALIZED;
1727 } else {
1728 env->mp_state = KVM_MP_STATE_RUNNABLE;
1729 }
689141dd 1730
2d384d7c 1731 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1732 int i;
1733 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1734 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1735 }
606c34bf
RK		 1736
1737 hyperv_x86_synic_reset(cpu);
689141dd 1738 }
caa5af0f
JK		 1739}
1740
e0723c45
PB		 1741void kvm_arch_do_init_vcpu(X86CPU *cpu)
1742{
1743 CPUX86State *env = &cpu->env;
1744
1745 /* APs get directly into wait-for-SIPI state. */
1746 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1747 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1748 }
1749}
1750
f57bceb6
RH		 1751static int kvm_get_supported_feature_msrs(KVMState *s)
1752{
1753 int ret = 0;
1754
1755 if (kvm_feature_msrs != NULL) {
1756 return 0;
1757 }
1758
1759 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1760 return 0;
1761 }
1762
1763 struct kvm_msr_list msr_list;
1764
1765 msr_list.nmsrs = 0;
1766 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1767 if (ret < 0 && ret != -E2BIG) {
1768 error_report("Fetch KVM feature MSR list failed: %s",
1769 strerror(-ret));
1770 return ret;
1771 }
1772
1773 assert(msr_list.nmsrs > 0);
1774 kvm_feature_msrs = (struct kvm_msr_list *) \
1775 g_malloc0(sizeof(msr_list) +
1776 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1777
1778 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1779 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1780
1781 if (ret < 0) {
1782 error_report("Fetch KVM feature MSR list failed: %s",
1783 strerror(-ret));
1784 g_free(kvm_feature_msrs);
1785 kvm_feature_msrs = NULL;
1786 return ret;
1787 }
1788
1789 return 0;
1790}
1791
c3a3a7d3 1792static int kvm_get_supported_msrs(KVMState *s)
05330448 1793{
75b10c43 1794 static int kvm_supported_msrs;
c3a3a7d3 1795 int ret = 0;
05330448
AL		 1796
1797 /* first time */
75b10c43 1798 if (kvm_supported_msrs == 0) {
05330448
AL		 1799 struct kvm_msr_list msr_list, *kvm_msr_list;
1800
75b10c43 1801 kvm_supported_msrs = -1;
05330448
AL		 1802
1803 /* Obtain MSR list from KVM. These are the MSRs that we must
1804 * save/restore */
4c9f7372 1805 msr_list.nmsrs = 0;
c3a3a7d3 1806 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1807 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1808 return ret;
6fb6d245 1809 }
d9db889f
JK		 1810 /* Old kernel modules had a bug and could write beyond the provided
1811 memory. Allocate at least a safe amount of 1K. */
7267c094 1812 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1813 msr_list.nmsrs *
1814 sizeof(msr_list.indices[0])));
05330448 1815
55308450 1816 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1817 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1818 if (ret >= 0) {
1819 int i;
1820
1821 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1822 switch (kvm_msr_list->indices[i]) {
1823 case MSR_STAR:
c3a3a7d3 1824 has_msr_star = true;
1d268dec
LP		 1825 break;
1826 case MSR_VM_HSAVE_PA:
c3a3a7d3 1827 has_msr_hsave_pa = true;
1d268dec
LP		 1828 break;
1829 case MSR_TSC_AUX:
c9b8f6b6 1830 has_msr_tsc_aux = true;
1d268dec
LP		 1831 break;
1832 case MSR_TSC_ADJUST:
f28558d3 1833 has_msr_tsc_adjust = true;
1d268dec
LP		 1834 break;
1835 case MSR_IA32_TSCDEADLINE:
aa82ba54 1836 has_msr_tsc_deadline = true;
1d268dec
LP		 1837 break;
1838 case MSR_IA32_SMBASE:
fc12d72e 1839 has_msr_smbase = true;
1d268dec 1840 break;
e13713db
LA		 1841 case MSR_SMI_COUNT:
1842 has_msr_smi_count = true;
1843 break;
1d268dec 1844 case MSR_IA32_MISC_ENABLE:
21e87c46 1845 has_msr_misc_enable = true;
1d268dec
LP		 1846 break;
1847 case MSR_IA32_BNDCFGS:
79e9ebeb 1848 has_msr_bndcfgs = true;
1d268dec
LP		 1849 break;
1850 case MSR_IA32_XSS:
18cd2c17 1851 has_msr_xss = true;
3c254ab8 1852 break;
1d268dec 1853 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1854 has_msr_hv_crash = true;
1d268dec
LP		 1855 break;
1856 case HV_X64_MSR_RESET:
744b8a94 1857 has_msr_hv_reset = true;
1d268dec
LP		 1858 break;
1859 case HV_X64_MSR_VP_INDEX:
8c145d7c 1860 has_msr_hv_vpindex = true;
1d268dec
LP		 1861 break;
1862 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1863 has_msr_hv_runtime = true;
1d268dec
LP		 1864 break;
1865 case HV_X64_MSR_SCONTROL:
866eea9a 1866 has_msr_hv_synic = true;
1d268dec
LP		 1867 break;
1868 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1869 has_msr_hv_stimer = true;
1d268dec 1870 break;
d72bc7f6
LP		 1871 case HV_X64_MSR_TSC_FREQUENCY:
1872 has_msr_hv_frequencies = true;
1873 break;
ba6a4fd9
VK		 1874 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1875 has_msr_hv_reenlightenment = true;
1876 break;
a33a2cfe
PB		 1877 case MSR_IA32_SPEC_CTRL:
1878 has_msr_spec_ctrl = true;
1879 break;
cfeea0c0
KRW		 1880 case MSR_VIRT_SSBD:
1881 has_msr_virt_ssbd = true;
1882 break;
aec5e9c3
BD		 1883 case MSR_IA32_ARCH_CAPABILITIES:
1884 has_msr_arch_capabs = true;
1885 break;
597360c0
XL		 1886 case MSR_IA32_CORE_CAPABILITY:
1887 has_msr_core_capabs = true;
1888 break;
ff99aa64 1889 }
05330448
AL		 1890 }
1891 }
1892
7267c094 1893 g_free(kvm_msr_list);
05330448
AL		 1894 }
1895
c3a3a7d3 1896 return ret;
05330448
AL		 1897}
1898
6410848b
PB		 1899static Notifier smram_machine_done;
1900static KVMMemoryListener smram_listener;
1901static AddressSpace smram_address_space;
1902static MemoryRegion smram_as_root;
1903static MemoryRegion smram_as_mem;
1904
1905static void register_smram_listener(Notifier *n, void *unused)
1906{
1907 MemoryRegion *smram =
1908 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1909
1910 /* Outer container... */
1911 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1912 memory_region_set_enabled(&smram_as_root, true);
1913
1914 /* ... with two regions inside: normal system memory with low
1915 * priority, and...
1916 */
1917 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1918 get_system_memory(), 0, ~0ull);
1919 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1920 memory_region_set_enabled(&smram_as_mem, true);
1921
1922 if (smram) {
1923 /* ... SMRAM with higher priority */
1924 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1925 memory_region_set_enabled(smram, true);
1926 }
1927
1928 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1929 kvm_memory_listener_register(kvm_state, &smram_listener,
1930 &smram_address_space, 1);
1931}
1932
b16565b3 1933int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1934{
11076198 1935 uint64_t identity_base = 0xfffbc000;
39d6960a 1936 uint64_t shadow_mem;
20420430 1937 int ret;
25d2e361 1938 struct utsname utsname;
20420430 1939
28143b40 1940 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1941 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1942 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1943
e9688fab
RK		 1944 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1945
c3a3a7d3 1946 ret = kvm_get_supported_msrs(s);
20420430 1947 if (ret < 0) {
20420430
SY		 1948 return ret;
1949 }
25d2e361 1950
f57bceb6
RH		 1951 kvm_get_supported_feature_msrs(s);
1952
25d2e361
MT		 1953 uname(&utsname);
1954 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1955
4c5b10b7 1956 /*
11076198
JK		 1957 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1958 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1959 * Since these must be part of guest physical memory, we need to allocate
1960 * them, both by setting their start addresses in the kernel and by
1961 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1962 *
1963 * Older KVM versions may not support setting the identity map base. In
1964 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1965 * size.
4c5b10b7 1966 */
11076198
JK		 1967 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1968 /* Allows up to 16M BIOSes. */
1969 identity_base = 0xfeffc000;
1970
1971 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1972 if (ret < 0) {
1973 return ret;
1974 }
4c5b10b7 1975 }
e56ff191 1976
11076198
JK		 1977 /* Set TSS base one page after EPT identity map. */
1978 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1979 if (ret < 0) {
1980 return ret;
1981 }
1982
11076198
JK		 1983 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1984 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1985 if (ret < 0) {
11076198 1986 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1987 return ret;
1988 }
3c85e74f 1989 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1990
4689b77b 1991 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1992 if (shadow_mem != -1) {
1993 shadow_mem /= 4096;
1994 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1995 if (ret < 0) {
1996 return ret;
39d6960a
JK		 1997 }
1998 }
6410848b 1999
d870cfde
GA		 2000 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
2001 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
2002 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 2003 smram_machine_done.notify = register_smram_listener;
2004 qemu_add_machine_init_done_notifier(&smram_machine_done);
2005 }
6f131f13
MT		 2006
2007 if (enable_cpu_pm) {
2008 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
2009 int ret;
2010
2011/* Work around for kernel header with a typo. TODO: fix header and drop. */
2012#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
2013#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
2014#endif
2015 if (disable_exits) {
2016 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
2017 KVM_X86_DISABLE_EXITS_HLT |
2018 KVM_X86_DISABLE_EXITS_PAUSE);
2019 }
2020
2021 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
2022 disable_exits);
2023 if (ret < 0) {
2024 error_report("kvm: guest stopping CPU not supported: %s",
2025 strerror(-ret));
2026 }
2027 }
2028
11076198 2029 return 0;
05330448 2030}
b9bec74b 2031
05330448
AL		 2032static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2033{
2034 lhs->selector = rhs->selector;
2035 lhs->base = rhs->base;
2036 lhs->limit = rhs->limit;
2037 lhs->type = 3;
2038 lhs->present = 1;
2039 lhs->dpl = 3;
2040 lhs->db = 0;
2041 lhs->s = 1;
2042 lhs->l = 0;
2043 lhs->g = 0;
2044 lhs->avl = 0;
2045 lhs->unusable = 0;
2046}
2047
2048static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
2049{
2050 unsigned flags = rhs->flags;
2051 lhs->selector = rhs->selector;
2052 lhs->base = rhs->base;
2053 lhs->limit = rhs->limit;
2054 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
2055 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 2056 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 2057 lhs->db = (flags >> DESC_B_SHIFT) & 1;
2058 lhs->s = (flags & DESC_S_MASK) != 0;
2059 lhs->l = (flags >> DESC_L_SHIFT) & 1;
2060 lhs->g = (flags & DESC_G_MASK) != 0;
2061 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 2062 lhs->unusable = !lhs->present;
7e680753 2063 lhs->padding = 0;
05330448
AL		 2064}
2065
2066static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
2067{
2068 lhs->selector = rhs->selector;
2069 lhs->base = rhs->base;
2070 lhs->limit = rhs->limit;
d45fc087
RP		 2071 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
2072 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
2073 (rhs->dpl << DESC_DPL_SHIFT) |
2074 (rhs->db << DESC_B_SHIFT) |
2075 (rhs->s * DESC_S_MASK) |
2076 (rhs->l << DESC_L_SHIFT) |
2077 (rhs->g * DESC_G_MASK) |
2078 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 2079}
2080
2081static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
2082{
b9bec74b 2083 if (set) {
05330448 2084 *kvm_reg = *qemu_reg;
b9bec74b 2085 } else {
05330448 2086 *qemu_reg = *kvm_reg;
b9bec74b 2087 }
05330448
AL		 2088}
2089
1bc22652 2090static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 2091{
1bc22652 2092 CPUX86State *env = &cpu->env;
05330448
AL		 2093 struct kvm_regs regs;
2094 int ret = 0;
2095
2096 if (!set) {
1bc22652 2097 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 2098 if (ret < 0) {
05330448 2099 return ret;
b9bec74b 2100 }
05330448
AL		 2101 }
2102
2103 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
2104 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
2105 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
2106 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
2107 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
2108 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
2109 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
2110 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
2111#ifdef TARGET_X86_64
2112 kvm_getput_reg(&regs.r8, &env->regs[8], set);
2113 kvm_getput_reg(&regs.r9, &env->regs[9], set);
2114 kvm_getput_reg(&regs.r10, &env->regs[10], set);
2115 kvm_getput_reg(&regs.r11, &env->regs[11], set);
2116 kvm_getput_reg(&regs.r12, &env->regs[12], set);
2117 kvm_getput_reg(&regs.r13, &env->regs[13], set);
2118 kvm_getput_reg(&regs.r14, &env->regs[14], set);
2119 kvm_getput_reg(&regs.r15, &env->regs[15], set);
2120#endif
2121
2122 kvm_getput_reg(&regs.rflags, &env->eflags, set);
2123 kvm_getput_reg(&regs.rip, &env->eip, set);
2124
b9bec74b 2125 if (set) {
1bc22652 2126 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 2127 }
05330448
AL		 2128
2129 return ret;
2130}
2131
1bc22652 2132static int kvm_put_fpu(X86CPU *cpu)
05330448 2133{
1bc22652 2134 CPUX86State *env = &cpu->env;
05330448
AL		 2135 struct kvm_fpu fpu;
2136 int i;
2137
2138 memset(&fpu, 0, sizeof fpu);
2139 fpu.fsw = env->fpus & ~(7 << 11);
2140 fpu.fsw |= (env->fpstt & 7) << 11;
2141 fpu.fcw = env->fpuc;
42cc8fa6
JK		 2142 fpu.last_opcode = env->fpop;
2143 fpu.last_ip = env->fpip;
2144 fpu.last_dp = env->fpdp;
b9bec74b
JK		 2145 for (i = 0; i < 8; ++i) {
2146 fpu.ftwx |= (!env->fptags[i]) << i;
2147 }
05330448 2148 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 2149 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2150 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
2151 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 2152 }
05330448
AL		 2153 fpu.mxcsr = env->mxcsr;
2154
1bc22652 2155 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 2156}
2157
6b42494b
JK		 2158#define XSAVE_FCW_FSW 0
2159#define XSAVE_FTW_FOP 1
f1665b21
SY		 2160#define XSAVE_CWD_RIP 2
2161#define XSAVE_CWD_RDP 4
2162#define XSAVE_MXCSR 6
2163#define XSAVE_ST_SPACE 8
2164#define XSAVE_XMM_SPACE 40
2165#define XSAVE_XSTATE_BV 128
2166#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 2167#define XSAVE_BNDREGS 240
2168#define XSAVE_BNDCSR 256
9aecd6f8
CP		 2169#define XSAVE_OPMASK 272
2170#define XSAVE_ZMM_Hi256 288
2171#define XSAVE_Hi16_ZMM 416
f74eefe0 2172#define XSAVE_PKRU 672
f1665b21 2173
b503717d 2174#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 2175 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 2176
2177#define ASSERT_OFFSET(word_offset, field) \
2178 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
2179 offsetof(X86XSaveArea, field))
2180
2181ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
2182ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
2183ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
2184ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
2185ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
2186ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
2187ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
2188ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
2189ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
2190ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
2191ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
2192ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
2193ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
2194ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
2195ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
2196
1bc22652 2197static int kvm_put_xsave(X86CPU *cpu)
f1665b21 2198{
1bc22652 2199 CPUX86State *env = &cpu->env;
5b8063c4 2200 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 2201
28143b40 2202 if (!has_xsave) {
1bc22652 2203 return kvm_put_fpu(cpu);
b9bec74b 2204 }
86a57621 2205 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 2206
9be38598 2207 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 2208}
2209
1bc22652 2210static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 2211{
1bc22652 2212 CPUX86State *env = &cpu->env;
bdfc8480 2213 struct kvm_xcrs xcrs = {};
f1665b21 2214
28143b40 2215 if (!has_xcrs) {
f1665b21 2216 return 0;
b9bec74b 2217 }
f1665b21
SY		 2218
2219 xcrs.nr_xcrs = 1;
2220 xcrs.flags = 0;
2221 xcrs.xcrs[0].xcr = 0;
2222 xcrs.xcrs[0].value = env->xcr0;
1bc22652 2223 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 2224}
2225
1bc22652 2226static int kvm_put_sregs(X86CPU *cpu)
05330448 2227{
1bc22652 2228 CPUX86State *env = &cpu->env;
05330448
AL		 2229 struct kvm_sregs sregs;
2230
0e607a80
JK		 2231 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
2232 if (env->interrupt_injected >= 0) {
2233 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
2234 (uint64_t)1 << (env->interrupt_injected % 64);
2235 }
05330448
AL		 2236
2237 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 2238 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
2239 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
2240 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
2241 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
2242 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
2243 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 2244 } else {
b9bec74b
JK		 2245 set_seg(&sregs.cs, &env->segs[R_CS]);
2246 set_seg(&sregs.ds, &env->segs[R_DS]);
2247 set_seg(&sregs.es, &env->segs[R_ES]);
2248 set_seg(&sregs.fs, &env->segs[R_FS]);
2249 set_seg(&sregs.gs, &env->segs[R_GS]);
2250 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 2251 }
2252
2253 set_seg(&sregs.tr, &env->tr);
2254 set_seg(&sregs.ldt, &env->ldt);
2255
2256 sregs.idt.limit = env->idt.limit;
2257 sregs.idt.base = env->idt.base;
7e680753 2258 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 2259 sregs.gdt.limit = env->gdt.limit;
2260 sregs.gdt.base = env->gdt.base;
7e680753 2261 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 2262
2263 sregs.cr0 = env->cr[0];
2264 sregs.cr2 = env->cr[2];
2265 sregs.cr3 = env->cr[3];
2266 sregs.cr4 = env->cr[4];
2267
02e51483
CF		 2268 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
2269 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 2270
2271 sregs.efer = env->efer;
2272
1bc22652 2273 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 2274}
2275
d71b62a1
EH		 2276static void kvm_msr_buf_reset(X86CPU *cpu)
2277{
2278 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
2279}
2280
9c600a84
EH		 2281static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
2282{
2283 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
2284 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
2285 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
2286
2287 assert((void *)(entry + 1) <= limit);
2288
1abc2cae
EH		 2289 entry->index = index;
2290 entry->reserved = 0;
2291 entry->data = value;
9c600a84
EH		 2292 msrs->nmsrs++;
2293}
2294
73e1b8f2
PB		 2295static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
2296{
2297 kvm_msr_buf_reset(cpu);
2298 kvm_msr_entry_add(cpu, index, value);
2299
2300 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2301}
2302
f8d9ccf8
DDAG		 2303void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
2304{
2305 int ret;
2306
2307 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
2308 assert(ret == 1);
2309}
2310
7477cd38
MT		 2311static int kvm_put_tscdeadline_msr(X86CPU *cpu)
2312{
2313 CPUX86State *env = &cpu->env;
48e1a45c 2314 int ret;
7477cd38
MT		 2315
2316 if (!has_msr_tsc_deadline) {
2317 return 0;
2318 }
2319
73e1b8f2 2320 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 2321 if (ret < 0) {
2322 return ret;
2323 }
2324
2325 assert(ret == 1);
2326 return 0;
7477cd38
MT		 2327}
2328
6bdf863d
JK		 2329/*
2330 * Provide a separate write service for the feature control MSR in order to
2331 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
2332 * before writing any other state because forcibly leaving nested mode
2333 * invalidates the VCPU state.
2334 */
2335static int kvm_put_msr_feature_control(X86CPU *cpu)
2336{
48e1a45c
PB		 2337 int ret;
2338
2339 if (!has_msr_feature_control) {
2340 return 0;
2341 }
6bdf863d 2342
73e1b8f2
PB		 2343 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
2344 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 2345 if (ret < 0) {
2346 return ret;
2347 }
2348
2349 assert(ret == 1);
2350 return 0;
6bdf863d
JK		 2351}
2352
1bc22652 2353static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 2354{
1bc22652 2355 CPUX86State *env = &cpu->env;
9c600a84 2356 int i;
48e1a45c 2357 int ret;
05330448 2358
d71b62a1
EH		 2359 kvm_msr_buf_reset(cpu);
2360
9c600a84
EH		 2361 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
2362 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
2363 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
2364 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 2365 if (has_msr_star) {
9c600a84 2366 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 2367 }
c3a3a7d3 2368 if (has_msr_hsave_pa) {
9c600a84 2369 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 2370 }
c9b8f6b6 2371 if (has_msr_tsc_aux) {
9c600a84 2372 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 2373 }
f28558d3 2374 if (has_msr_tsc_adjust) {
9c600a84 2375 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 2376 }
21e87c46 2377 if (has_msr_misc_enable) {
9c600a84 2378 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 2379 env->msr_ia32_misc_enable);
2380 }
fc12d72e 2381 if (has_msr_smbase) {
9c600a84 2382 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 2383 }
e13713db
LA		 2384 if (has_msr_smi_count) {
2385 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
2386 }
439d19f2 2387 if (has_msr_bndcfgs) {
9c600a84 2388 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2389 }
18cd2c17 2390 if (has_msr_xss) {
9c600a84 2391 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2392 }
a33a2cfe
PB		 2393 if (has_msr_spec_ctrl) {
2394 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2395 }
cfeea0c0
KRW		 2396 if (has_msr_virt_ssbd) {
2397 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2398 }
2399
05330448 2400#ifdef TARGET_X86_64
25d2e361 2401 if (lm_capable_kernel) {
9c600a84
EH		 2402 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2403 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2404 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2405 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2406 }
05330448 2407#endif
a33a2cfe 2408
d86f9636 2409 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2410 if (has_msr_arch_capabs) {
2411 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2412 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2413 }
2414
597360c0
XL		 2415 if (has_msr_core_capabs) {
2416 kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
2417 env->features[FEAT_CORE_CAPABILITY]);
2418 }
2419
ff5c186b 2420 /*
0d894367
PB		 2421 * The following MSRs have side effects on the guest or are too heavy
2422 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2423 */
2424 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2425 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2426 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2427 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2428 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2429 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2430 }
55c911a5 2431 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2432 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2433 }
55c911a5 2434 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2435 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2436 }
0b368a10
JD		 2437 if (has_architectural_pmu_version > 0) {
2438 if (has_architectural_pmu_version > 1) {
2439 /* Stop the counter. */
2440 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2441 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2442 }
0d894367
PB		 2443
2444 /* Set the counter values. */
0b368a10 2445 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2446 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2447 env->msr_fixed_counters[i]);
2448 }
0b368a10 2449 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2450 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2451 env->msr_gp_counters[i]);
9c600a84 2452 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2453 env->msr_gp_evtsel[i]);
2454 }
0b368a10
JD		 2455 if (has_architectural_pmu_version > 1) {
2456 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2457 env->msr_global_status);
2458 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2459 env->msr_global_ovf_ctrl);
2460
2461 /* Now start the PMU. */
2462 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2463 env->msr_fixed_ctr_ctrl);
2464 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2465 env->msr_global_ctrl);
2466 }
0d894367 2467 }
da1cc323
EY		 2468 /*
2469 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2470 * only sync them to KVM on the first cpu
2471 */
2472 if (current_cpu == first_cpu) {
2473 if (has_msr_hv_hypercall) {
2474 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2475 env->msr_hv_guest_os_id);
2476 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2477 env->msr_hv_hypercall);
2478 }
2d384d7c 2479 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2480 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2481 env->msr_hv_tsc);
2482 }
2d384d7c 2483 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2484 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2485 env->msr_hv_reenlightenment_control);
2486 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2487 env->msr_hv_tsc_emulation_control);
2488 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2489 env->msr_hv_tsc_emulation_status);
2490 }
eab70139 2491 }
2d384d7c 2492 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2493 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2494 env->msr_hv_vapic);
eab70139 2495 }
f2a53c9e
AS		 2496 if (has_msr_hv_crash) {
2497 int j;
2498
5e953812 2499 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2500 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2501 env->msr_hv_crash_params[j]);
2502
5e953812 2503 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2504 }
46eb8f98 2505 if (has_msr_hv_runtime) {
9c600a84 2506 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2507 }
2d384d7c
VK		 2508 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2509 && hv_vpindex_settable) {
701189e3
RK		 2510 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2511 hyperv_vp_index(CPU(cpu)));
e9688fab 2512 }
2d384d7c 2513 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2514 int j;
2515
09df29b6
RK		 2516 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2517
9c600a84 2518 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2519 env->msr_hv_synic_control);
9c600a84 2520 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2521 env->msr_hv_synic_evt_page);
9c600a84 2522 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2523 env->msr_hv_synic_msg_page);
2524
2525 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2526 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2527 env->msr_hv_synic_sint[j]);
2528 }
2529 }
ff99aa64
AS		 2530 if (has_msr_hv_stimer) {
2531 int j;
2532
2533 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2534 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2535 env->msr_hv_stimer_config[j]);
2536 }
2537
2538 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2539 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2540 env->msr_hv_stimer_count[j]);
2541 }
2542 }
1eabfce6 2543 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2544 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2545
9c600a84
EH		 2546 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2547 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2548 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2549 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2550 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2551 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2552 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2553 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2554 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2555 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2556 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2557 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2558 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2559 /* The CPU GPs if we write to a bit above the physical limit of
2560 * the host CPU (and KVM emulates that)
2561 */
2562 uint64_t mask = env->mtrr_var[i].mask;
2563 mask &= phys_mask;
2564
9c600a84
EH		 2565 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2566 env->mtrr_var[i].base);
112dad69 2567 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2568 }
2569 }
b77146e9
CP		 2570 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2571 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2572 0x14, 1, R_EAX) & 0x7;
2573
2574 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2575 env->msr_rtit_ctrl);
2576 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2577 env->msr_rtit_status);
2578 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2579 env->msr_rtit_output_base);
2580 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2581 env->msr_rtit_output_mask);
2582 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2583 env->msr_rtit_cr3_match);
2584 for (i = 0; i < addr_num; i++) {
2585 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2586 env->msr_rtit_addrs[i]);
2587 }
2588 }
6bdf863d
JK		 2589
2590 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2591 * kvm_put_msr_feature_control. */
ea643051 2592 }
57780495 2593 if (env->mcg_cap) {
d8da8574 2594 int i;
b9bec74b 2595
9c600a84
EH		 2596 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2597 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2598 if (has_msr_mcg_ext_ctl) {
2599 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2600 }
c34d440a 2601 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2602 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2603 }
2604 }
1a03675d 2605
d71b62a1 2606 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2607 if (ret < 0) {
2608 return ret;
2609 }
05330448 2610
c70b11d1
EH		 2611 if (ret < cpu->kvm_msr_buf->nmsrs) {
2612 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2613 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2614 (uint32_t)e->index, (uint64_t)e->data);
2615 }
2616
9c600a84 2617 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2618 return 0;
05330448
AL		 2619}
2620
2621
1bc22652 2622static int kvm_get_fpu(X86CPU *cpu)
05330448 2623{
1bc22652 2624 CPUX86State *env = &cpu->env;
05330448
AL		 2625 struct kvm_fpu fpu;
2626 int i, ret;
2627
1bc22652 2628 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2629 if (ret < 0) {
05330448 2630 return ret;
b9bec74b 2631 }
05330448
AL		 2632
2633 env->fpstt = (fpu.fsw >> 11) & 7;
2634 env->fpus = fpu.fsw;
2635 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2636 env->fpop = fpu.last_opcode;
2637 env->fpip = fpu.last_ip;
2638 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2639 for (i = 0; i < 8; ++i) {
2640 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2641 }
05330448 2642 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2643 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2644 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2645 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2646 }
05330448
AL		 2647 env->mxcsr = fpu.mxcsr;
2648
2649 return 0;
2650}
2651
1bc22652 2652static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2653{
1bc22652 2654 CPUX86State *env = &cpu->env;
5b8063c4 2655 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2656 int ret;
f1665b21 2657
28143b40 2658 if (!has_xsave) {
1bc22652 2659 return kvm_get_fpu(cpu);
b9bec74b 2660 }
f1665b21 2661
1bc22652 2662 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2663 if (ret < 0) {
f1665b21 2664 return ret;
0f53994f 2665 }
86a57621 2666 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2667
f1665b21 2668 return 0;
f1665b21
SY		 2669}
2670
1bc22652 2671static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2672{
1bc22652 2673 CPUX86State *env = &cpu->env;
f1665b21
SY		 2674 int i, ret;
2675 struct kvm_xcrs xcrs;
2676
28143b40 2677 if (!has_xcrs) {
f1665b21 2678 return 0;
b9bec74b 2679 }
f1665b21 2680
1bc22652 2681 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2682 if (ret < 0) {
f1665b21 2683 return ret;
b9bec74b 2684 }
f1665b21 2685
b9bec74b 2686 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2687 /* Only support xcr0 now */
0fd53fec
PB		 2688 if (xcrs.xcrs[i].xcr == 0) {
2689 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2690 break;
2691 }
b9bec74b 2692 }
f1665b21 2693 return 0;
f1665b21
SY		 2694}
2695
1bc22652 2696static int kvm_get_sregs(X86CPU *cpu)
05330448 2697{
1bc22652 2698 CPUX86State *env = &cpu->env;
05330448 2699 struct kvm_sregs sregs;
0e607a80 2700 int bit, i, ret;
05330448 2701
1bc22652 2702 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2703 if (ret < 0) {
05330448 2704 return ret;
b9bec74b 2705 }
05330448 2706
0e607a80
JK		 2707 /* There can only be one pending IRQ set in the bitmap at a time, so try
2708 to find it and save its number instead (-1 for none). */
2709 env->interrupt_injected = -1;
2710 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2711 if (sregs.interrupt_bitmap[i]) {
2712 bit = ctz64(sregs.interrupt_bitmap[i]);
2713 env->interrupt_injected = i * 64 + bit;
2714 break;
2715 }
2716 }
05330448
AL		 2717
2718 get_seg(&env->segs[R_CS], &sregs.cs);
2719 get_seg(&env->segs[R_DS], &sregs.ds);
2720 get_seg(&env->segs[R_ES], &sregs.es);
2721 get_seg(&env->segs[R_FS], &sregs.fs);
2722 get_seg(&env->segs[R_GS], &sregs.gs);
2723 get_seg(&env->segs[R_SS], &sregs.ss);
2724
2725 get_seg(&env->tr, &sregs.tr);
2726 get_seg(&env->ldt, &sregs.ldt);
2727
2728 env->idt.limit = sregs.idt.limit;
2729 env->idt.base = sregs.idt.base;
2730 env->gdt.limit = sregs.gdt.limit;
2731 env->gdt.base = sregs.gdt.base;
2732
2733 env->cr[0] = sregs.cr0;
2734 env->cr[2] = sregs.cr2;
2735 env->cr[3] = sregs.cr3;
2736 env->cr[4] = sregs.cr4;
2737
05330448 2738 env->efer = sregs.efer;
cce47516
JK		 2739
2740 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2741 x86_update_hflags(env);
05330448
AL		 2742
2743 return 0;
2744}
2745
1bc22652 2746static int kvm_get_msrs(X86CPU *cpu)
05330448 2747{
1bc22652 2748 CPUX86State *env = &cpu->env;
d71b62a1 2749 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2750 int ret, i;
fcc35e7c 2751 uint64_t mtrr_top_bits;
05330448 2752
d71b62a1
EH		 2753 kvm_msr_buf_reset(cpu);
2754
9c600a84
EH		 2755 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2756 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2757 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2758 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2759 if (has_msr_star) {
9c600a84 2760 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2761 }
c3a3a7d3 2762 if (has_msr_hsave_pa) {
9c600a84 2763 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2764 }
c9b8f6b6 2765 if (has_msr_tsc_aux) {
9c600a84 2766 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2767 }
f28558d3 2768 if (has_msr_tsc_adjust) {
9c600a84 2769 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2770 }
aa82ba54 2771 if (has_msr_tsc_deadline) {
9c600a84 2772 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2773 }
21e87c46 2774 if (has_msr_misc_enable) {
9c600a84 2775 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2776 }
fc12d72e 2777 if (has_msr_smbase) {
9c600a84 2778 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2779 }
e13713db
LA		 2780 if (has_msr_smi_count) {
2781 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2782 }
df67696e 2783 if (has_msr_feature_control) {
9c600a84 2784 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2785 }
79e9ebeb 2786 if (has_msr_bndcfgs) {
9c600a84 2787 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2788 }
18cd2c17 2789 if (has_msr_xss) {
9c600a84 2790 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2791 }
a33a2cfe
PB		 2792 if (has_msr_spec_ctrl) {
2793 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2794 }
cfeea0c0
KRW		 2795 if (has_msr_virt_ssbd) {
2796 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2797 }
b8cc45d6 2798 if (!env->tsc_valid) {
9c600a84 2799 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2800 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2801 }
2802
05330448 2803#ifdef TARGET_X86_64
25d2e361 2804 if (lm_capable_kernel) {
9c600a84
EH		 2805 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2806 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2807 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2808 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2809 }
05330448 2810#endif
9c600a84
EH		 2811 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2812 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2813 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2814 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2815 }
55c911a5 2816 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2817 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2818 }
55c911a5 2819 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2820 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2821 }
0b368a10
JD		 2822 if (has_architectural_pmu_version > 0) {
2823 if (has_architectural_pmu_version > 1) {
2824 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2825 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2826 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2827 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2828 }
2829 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2830 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2831 }
0b368a10 2832 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2833 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2834 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2835 }
2836 }
1a03675d 2837
57780495 2838 if (env->mcg_cap) {
9c600a84
EH		 2839 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2840 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2841 if (has_msr_mcg_ext_ctl) {
2842 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2843 }
b9bec74b 2844 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2845 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2846 }
57780495 2847 }
57780495 2848
1c90ef26 2849 if (has_msr_hv_hypercall) {
9c600a84
EH		 2850 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2851 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2852 }
2d384d7c 2853 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2854 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2855 }
2d384d7c 2856 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 2857 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2858 }
2d384d7c 2859 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2860 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2861 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2862 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2863 }
f2a53c9e
AS		 2864 if (has_msr_hv_crash) {
2865 int j;
2866
5e953812 2867 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2868 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2869 }
2870 }
46eb8f98 2871 if (has_msr_hv_runtime) {
9c600a84 2872 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2873 }
2d384d7c 2874 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2875 uint32_t msr;
2876
9c600a84 2877 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2878 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2879 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2880 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2881 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2882 }
2883 }
ff99aa64
AS		 2884 if (has_msr_hv_stimer) {
2885 uint32_t msr;
2886
2887 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2888 msr++) {
9c600a84 2889 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2890 }
2891 }
1eabfce6 2892 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2893 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2894 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2895 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2896 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2897 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2898 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2899 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2900 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2901 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2902 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2903 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2904 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2905 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2906 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2907 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2908 }
2909 }
5ef68987 2910
b77146e9
CP		 2911 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2912 int addr_num =
2913 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2914
2915 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2916 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2917 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2918 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2919 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2920 for (i = 0; i < addr_num; i++) {
2921 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2922 }
2923 }
2924
d71b62a1 2925 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2926 if (ret < 0) {
05330448 2927 return ret;
b9bec74b 2928 }
05330448 2929
c70b11d1
EH		 2930 if (ret < cpu->kvm_msr_buf->nmsrs) {
2931 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2932 error_report("error: failed to get MSR 0x%" PRIx32,
2933 (uint32_t)e->index);
2934 }
2935
9c600a84 2936 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2937 /*
2938 * MTRR masks: Each mask consists of 5 parts
2939 * a 10..0: must be zero
2940 * b 11 : valid bit
2941 * c n-1.12: actual mask bits
2942 * d 51..n: reserved must be zero
2943 * e 63.52: reserved must be zero
2944 *
2945 * 'n' is the number of physical bits supported by the CPU and is
2946 * apparently always <= 52. We know our 'n' but don't know what
2947 * the destinations 'n' is; it might be smaller, in which case
2948 * it masks (c) on loading. It might be larger, in which case
2949 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2950 * we're migrating to.
2951 */
2952
2953 if (cpu->fill_mtrr_mask) {
2954 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2955 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2956 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2957 } else {
2958 mtrr_top_bits = 0;
2959 }
2960
05330448 2961 for (i = 0; i < ret; i++) {
0d894367
PB		 2962 uint32_t index = msrs[i].index;
2963 switch (index) {
05330448
AL		 2964 case MSR_IA32_SYSENTER_CS:
2965 env->sysenter_cs = msrs[i].data;
2966 break;
2967 case MSR_IA32_SYSENTER_ESP:
2968 env->sysenter_esp = msrs[i].data;
2969 break;
2970 case MSR_IA32_SYSENTER_EIP:
2971 env->sysenter_eip = msrs[i].data;
2972 break;
0c03266a
JK		 2973 case MSR_PAT:
2974 env->pat = msrs[i].data;
2975 break;
05330448
AL		 2976 case MSR_STAR:
2977 env->star = msrs[i].data;
2978 break;
2979#ifdef TARGET_X86_64
2980 case MSR_CSTAR:
2981 env->cstar = msrs[i].data;
2982 break;
2983 case MSR_KERNELGSBASE:
2984 env->kernelgsbase = msrs[i].data;
2985 break;
2986 case MSR_FMASK:
2987 env->fmask = msrs[i].data;
2988 break;
2989 case MSR_LSTAR:
2990 env->lstar = msrs[i].data;
2991 break;
2992#endif
2993 case MSR_IA32_TSC:
2994 env->tsc = msrs[i].data;
2995 break;
c9b8f6b6
AS		 2996 case MSR_TSC_AUX:
2997 env->tsc_aux = msrs[i].data;
2998 break;
f28558d3
WA		 2999 case MSR_TSC_ADJUST:
3000 env->tsc_adjust = msrs[i].data;
3001 break;
aa82ba54
LJ		 3002 case MSR_IA32_TSCDEADLINE:
3003 env->tsc_deadline = msrs[i].data;
3004 break;
aa851e36
MT		 3005 case MSR_VM_HSAVE_PA:
3006 env->vm_hsave = msrs[i].data;
3007 break;
1a03675d
GC		 3008 case MSR_KVM_SYSTEM_TIME:
3009 env->system_time_msr = msrs[i].data;
3010 break;
3011 case MSR_KVM_WALL_CLOCK:
3012 env->wall_clock_msr = msrs[i].data;
3013 break;
57780495
MT		 3014 case MSR_MCG_STATUS:
3015 env->mcg_status = msrs[i].data;
3016 break;
3017 case MSR_MCG_CTL:
3018 env->mcg_ctl = msrs[i].data;
3019 break;
87f8b626
AR		 3020 case MSR_MCG_EXT_CTL:
3021 env->mcg_ext_ctl = msrs[i].data;
3022 break;
21e87c46
AK		 3023 case MSR_IA32_MISC_ENABLE:
3024 env->msr_ia32_misc_enable = msrs[i].data;
3025 break;
fc12d72e
PB		 3026 case MSR_IA32_SMBASE:
3027 env->smbase = msrs[i].data;
3028 break;
e13713db
LA		 3029 case MSR_SMI_COUNT:
3030 env->msr_smi_count = msrs[i].data;
3031 break;
0779caeb
ACL		 3032 case MSR_IA32_FEATURE_CONTROL:
3033 env->msr_ia32_feature_control = msrs[i].data;
df67696e 3034 break;
79e9ebeb
LJ		 3035 case MSR_IA32_BNDCFGS:
3036 env->msr_bndcfgs = msrs[i].data;
3037 break;
18cd2c17
WL		 3038 case MSR_IA32_XSS:
3039 env->xss = msrs[i].data;
3040 break;
57780495 3041 default:
57780495
MT		 3042 if (msrs[i].index >= MSR_MC0_CTL &&
3043 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
3044 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 3045 }
d8da8574 3046 break;
f6584ee2
GN		 3047 case MSR_KVM_ASYNC_PF_EN:
3048 env->async_pf_en_msr = msrs[i].data;
3049 break;
bc9a839d
MT		 3050 case MSR_KVM_PV_EOI_EN:
3051 env->pv_eoi_en_msr = msrs[i].data;
3052 break;
917367aa
MT		 3053 case MSR_KVM_STEAL_TIME:
3054 env->steal_time_msr = msrs[i].data;
3055 break;
0d894367
PB		 3056 case MSR_CORE_PERF_FIXED_CTR_CTRL:
3057 env->msr_fixed_ctr_ctrl = msrs[i].data;
3058 break;
3059 case MSR_CORE_PERF_GLOBAL_CTRL:
3060 env->msr_global_ctrl = msrs[i].data;
3061 break;
3062 case MSR_CORE_PERF_GLOBAL_STATUS:
3063 env->msr_global_status = msrs[i].data;
3064 break;
3065 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
3066 env->msr_global_ovf_ctrl = msrs[i].data;
3067 break;
3068 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
3069 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
3070 break;
3071 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
3072 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
3073 break;
3074 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
3075 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
3076 break;
1c90ef26
VR		 3077 case HV_X64_MSR_HYPERCALL:
3078 env->msr_hv_hypercall = msrs[i].data;
3079 break;
3080 case HV_X64_MSR_GUEST_OS_ID:
3081 env->msr_hv_guest_os_id = msrs[i].data;
3082 break;
5ef68987
VR		 3083 case HV_X64_MSR_APIC_ASSIST_PAGE:
3084 env->msr_hv_vapic = msrs[i].data;
3085 break;
48a5f3bc
VR		 3086 case HV_X64_MSR_REFERENCE_TSC:
3087 env->msr_hv_tsc = msrs[i].data;
3088 break;
f2a53c9e
AS		 3089 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
3090 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
3091 break;
46eb8f98
AS		 3092 case HV_X64_MSR_VP_RUNTIME:
3093 env->msr_hv_runtime = msrs[i].data;
3094 break;
866eea9a
AS		 3095 case HV_X64_MSR_SCONTROL:
3096 env->msr_hv_synic_control = msrs[i].data;
3097 break;
866eea9a
AS		 3098 case HV_X64_MSR_SIEFP:
3099 env->msr_hv_synic_evt_page = msrs[i].data;
3100 break;
3101 case HV_X64_MSR_SIMP:
3102 env->msr_hv_synic_msg_page = msrs[i].data;
3103 break;
3104 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
3105 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 3106 break;
3107 case HV_X64_MSR_STIMER0_CONFIG:
3108 case HV_X64_MSR_STIMER1_CONFIG:
3109 case HV_X64_MSR_STIMER2_CONFIG:
3110 case HV_X64_MSR_STIMER3_CONFIG:
3111 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
3112 msrs[i].data;
3113 break;
3114 case HV_X64_MSR_STIMER0_COUNT:
3115 case HV_X64_MSR_STIMER1_COUNT:
3116 case HV_X64_MSR_STIMER2_COUNT:
3117 case HV_X64_MSR_STIMER3_COUNT:
3118 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
3119 msrs[i].data;
866eea9a 3120 break;
ba6a4fd9
VK		 3121 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
3122 env->msr_hv_reenlightenment_control = msrs[i].data;
3123 break;
3124 case HV_X64_MSR_TSC_EMULATION_CONTROL:
3125 env->msr_hv_tsc_emulation_control = msrs[i].data;
3126 break;
3127 case HV_X64_MSR_TSC_EMULATION_STATUS:
3128 env->msr_hv_tsc_emulation_status = msrs[i].data;
3129 break;
d1ae67f6
AW		 3130 case MSR_MTRRdefType:
3131 env->mtrr_deftype = msrs[i].data;
3132 break;
3133 case MSR_MTRRfix64K_00000:
3134 env->mtrr_fixed[0] = msrs[i].data;
3135 break;
3136 case MSR_MTRRfix16K_80000:
3137 env->mtrr_fixed[1] = msrs[i].data;
3138 break;
3139 case MSR_MTRRfix16K_A0000:
3140 env->mtrr_fixed[2] = msrs[i].data;
3141 break;
3142 case MSR_MTRRfix4K_C0000:
3143 env->mtrr_fixed[3] = msrs[i].data;
3144 break;
3145 case MSR_MTRRfix4K_C8000:
3146 env->mtrr_fixed[4] = msrs[i].data;
3147 break;
3148 case MSR_MTRRfix4K_D0000:
3149 env->mtrr_fixed[5] = msrs[i].data;
3150 break;
3151 case MSR_MTRRfix4K_D8000:
3152 env->mtrr_fixed[6] = msrs[i].data;
3153 break;
3154 case MSR_MTRRfix4K_E0000:
3155 env->mtrr_fixed[7] = msrs[i].data;
3156 break;
3157 case MSR_MTRRfix4K_E8000:
3158 env->mtrr_fixed[8] = msrs[i].data;
3159 break;
3160 case MSR_MTRRfix4K_F0000:
3161 env->mtrr_fixed[9] = msrs[i].data;
3162 break;
3163 case MSR_MTRRfix4K_F8000:
3164 env->mtrr_fixed[10] = msrs[i].data;
3165 break;
3166 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
3167 if (index & 1) {
fcc35e7c
DDAG		 3168 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
3169 mtrr_top_bits;
d1ae67f6
AW		 3170 } else {
3171 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
3172 }
3173 break;
a33a2cfe
PB		 3174 case MSR_IA32_SPEC_CTRL:
3175 env->spec_ctrl = msrs[i].data;
3176 break;
cfeea0c0
KRW		 3177 case MSR_VIRT_SSBD:
3178 env->virt_ssbd = msrs[i].data;
3179 break;
b77146e9
CP		 3180 case MSR_IA32_RTIT_CTL:
3181 env->msr_rtit_ctrl = msrs[i].data;
3182 break;
3183 case MSR_IA32_RTIT_STATUS:
3184 env->msr_rtit_status = msrs[i].data;
3185 break;
3186 case MSR_IA32_RTIT_OUTPUT_BASE:
3187 env->msr_rtit_output_base = msrs[i].data;
3188 break;
3189 case MSR_IA32_RTIT_OUTPUT_MASK:
3190 env->msr_rtit_output_mask = msrs[i].data;
3191 break;
3192 case MSR_IA32_RTIT_CR3_MATCH:
3193 env->msr_rtit_cr3_match = msrs[i].data;
3194 break;
3195 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
3196 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
3197 break;
05330448
AL		 3198 }
3199 }
3200
3201 return 0;
3202}
3203
1bc22652 3204static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 3205{
1bc22652 3206 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 3207
1bc22652 3208 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 3209}
3210
23d02d9b 3211static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 3212{
259186a7 3213 CPUState *cs = CPU(cpu);
23d02d9b 3214 CPUX86State *env = &cpu->env;
9bdbe550
HB		 3215 struct kvm_mp_state mp_state;
3216 int ret;
3217
259186a7 3218 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 3219 if (ret < 0) {
3220 return ret;
3221 }
3222 env->mp_state = mp_state.mp_state;
c14750e8 3223 if (kvm_irqchip_in_kernel()) {
259186a7 3224 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 3225 }
9bdbe550
HB		 3226 return 0;
3227}
3228
1bc22652 3229static int kvm_get_apic(X86CPU *cpu)
680c1c6f 3230{
02e51483 3231 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 3232 struct kvm_lapic_state kapic;
3233 int ret;
3234
3d4b2649 3235 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 3236 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 3237 if (ret < 0) {
3238 return ret;
3239 }
3240
3241 kvm_get_apic_state(apic, &kapic);
3242 }
3243 return 0;
3244}
3245
1bc22652 3246static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 3247{
fc12d72e 3248 CPUState *cs = CPU(cpu);
1bc22652 3249 CPUX86State *env = &cpu->env;
076796f8 3250 struct kvm_vcpu_events events = {};
a0fb002c
JK		 3251
3252 if (!kvm_has_vcpu_events()) {
3253 return 0;
3254 }
3255
31827373
JK		 3256 events.exception.injected = (env->exception_injected >= 0);
3257 events.exception.nr = env->exception_injected;
a0fb002c
JK		 3258 events.exception.has_error_code = env->has_error_code;
3259 events.exception.error_code = env->error_code;
3260
3261 events.interrupt.injected = (env->interrupt_injected >= 0);
3262 events.interrupt.nr = env->interrupt_injected;
3263 events.interrupt.soft = env->soft_interrupt;
3264
3265 events.nmi.injected = env->nmi_injected;
3266 events.nmi.pending = env->nmi_pending;
3267 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
3268
3269 events.sipi_vector = env->sipi_vector;
68c6efe0 3270 events.flags = 0;
a0fb002c 3271
fc12d72e
PB		 3272 if (has_msr_smbase) {
3273 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
3274 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
3275 if (kvm_irqchip_in_kernel()) {
3276 /* As soon as these are moved to the kernel, remove them
3277 * from cs->interrupt_request.
3278 */
3279 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
3280 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
3281 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
3282 } else {
3283 /* Keep these in cs->interrupt_request. */
3284 events.smi.pending = 0;
3285 events.smi.latched_init = 0;
3286 }
fc3a1fd7
DDAG		 3287 /* Stop SMI delivery on old machine types to avoid a reboot
3288 * on an inward migration of an old VM.
3289 */
3290 if (!cpu->kvm_no_smi_migration) {
3291 events.flags |= KVM_VCPUEVENT_VALID_SMM;
3292 }
fc12d72e
PB		 3293 }
3294
ea643051 3295 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 3296 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
3297 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
3298 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
3299 }
ea643051 3300 }
aee028b9 3301
1bc22652 3302 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 3303}
3304
1bc22652 3305static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 3306{
1bc22652 3307 CPUX86State *env = &cpu->env;
a0fb002c
JK		 3308 struct kvm_vcpu_events events;
3309 int ret;
3310
3311 if (!kvm_has_vcpu_events()) {
3312 return 0;
3313 }
3314
fc12d72e 3315 memset(&events, 0, sizeof(events));
1bc22652 3316 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 3317 if (ret < 0) {
3318 return ret;
3319 }
31827373 3320 env->exception_injected =
a0fb002c
JK		 3321 events.exception.injected ? events.exception.nr : -1;
3322 env->has_error_code = events.exception.has_error_code;
3323 env->error_code = events.exception.error_code;
3324
3325 env->interrupt_injected =
3326 events.interrupt.injected ? events.interrupt.nr : -1;
3327 env->soft_interrupt = events.interrupt.soft;
3328
3329 env->nmi_injected = events.nmi.injected;
3330 env->nmi_pending = events.nmi.pending;
3331 if (events.nmi.masked) {
3332 env->hflags2 |= HF2_NMI_MASK;
3333 } else {
3334 env->hflags2 &= ~HF2_NMI_MASK;
3335 }
3336
fc12d72e
PB		 3337 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
3338 if (events.smi.smm) {
3339 env->hflags |= HF_SMM_MASK;
3340 } else {
3341 env->hflags &= ~HF_SMM_MASK;
3342 }
3343 if (events.smi.pending) {
3344 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3345 } else {
3346 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
3347 }
3348 if (events.smi.smm_inside_nmi) {
3349 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
3350 } else {
3351 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
3352 }
3353 if (events.smi.latched_init) {
3354 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3355 } else {
3356 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
3357 }
3358 }
3359
a0fb002c 3360 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 3361
3362 return 0;
3363}
3364
1bc22652 3365static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 3366{
ed2803da 3367 CPUState *cs = CPU(cpu);
1bc22652 3368 CPUX86State *env = &cpu->env;
b0b1d690 3369 int ret = 0;
b0b1d690
JK		 3370 unsigned long reinject_trap = 0;
3371
3372 if (!kvm_has_vcpu_events()) {
37936ac7 3373 if (env->exception_injected == EXCP01_DB) {
b0b1d690 3374 reinject_trap = KVM_GUESTDBG_INJECT_DB;
37936ac7 3375 } else if (env->exception_injected == EXCP03_INT3) {
b0b1d690
JK		 3376 reinject_trap = KVM_GUESTDBG_INJECT_BP;
3377 }
3378 env->exception_injected = -1;
3379 }
3380
3381 /*
3382 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
3383 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
3384 * by updating the debug state once again if single-stepping is on.
3385 * Another reason to call kvm_update_guest_debug here is a pending debug
3386 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
3387 * reinject them via SET_GUEST_DEBUG.
3388 */
3389 if (reinject_trap ||
ed2803da 3390 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 3391 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3392 }
b0b1d690
JK		 3393 return ret;
3394}
3395
1bc22652 3396static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3397{
1bc22652 3398 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3399 struct kvm_debugregs dbgregs;
3400 int i;
3401
3402 if (!kvm_has_debugregs()) {
3403 return 0;
3404 }
3405
3406 for (i = 0; i < 4; i++) {
3407 dbgregs.db[i] = env->dr[i];
3408 }
3409 dbgregs.dr6 = env->dr[6];
3410 dbgregs.dr7 = env->dr[7];
3411 dbgregs.flags = 0;
3412
1bc22652 3413 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3414}
3415
1bc22652 3416static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3417{
1bc22652 3418 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3419 struct kvm_debugregs dbgregs;
3420 int i, ret;
3421
3422 if (!kvm_has_debugregs()) {
3423 return 0;
3424 }
3425
1bc22652 3426 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3427 if (ret < 0) {
b9bec74b 3428 return ret;
ff44f1a3
JK		 3429 }
3430 for (i = 0; i < 4; i++) {
3431 env->dr[i] = dbgregs.db[i];
3432 }
3433 env->dr[4] = env->dr[6] = dbgregs.dr6;
3434 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3435
3436 return 0;
3437}
3438
ebbfef2f
LA		 3439static int kvm_put_nested_state(X86CPU *cpu)
3440{
3441 CPUX86State *env = &cpu->env;
3442 int max_nested_state_len = kvm_max_nested_state_length();
3443
3444 if (max_nested_state_len <= 0) {
3445 return 0;
3446 }
3447
3448 assert(env->nested_state->size <= max_nested_state_len);
3449 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_NESTED_STATE, env->nested_state);
3450}
3451
3452static int kvm_get_nested_state(X86CPU *cpu)
3453{
3454 CPUX86State *env = &cpu->env;
3455 int max_nested_state_len = kvm_max_nested_state_length();
3456 int ret;
3457
3458 if (max_nested_state_len <= 0) {
3459 return 0;
3460 }
3461
3462 /*
3463 * It is possible that migration restored a smaller size into
3464 * nested_state->hdr.size than what our kernel support.
3465 * We preserve migration origin nested_state->hdr.size for
3466 * call to KVM_SET_NESTED_STATE but wish that our next call
3467 * to KVM_GET_NESTED_STATE will use max size our kernel support.
3468 */
3469 env->nested_state->size = max_nested_state_len;
3470
3471 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_NESTED_STATE, env->nested_state);
3472 if (ret < 0) {
3473 return ret;
3474 }
3475
3476 if (env->nested_state->flags & KVM_STATE_NESTED_GUEST_MODE) {
3477 env->hflags |= HF_GUEST_MASK;
3478 } else {
3479 env->hflags &= ~HF_GUEST_MASK;
3480 }
3481
3482 return ret;
3483}
3484
20d695a9 3485int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3486{
20d695a9 3487 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3488 int ret;
3489
2fa45344 3490 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3491
ebbfef2f
LA		 3492 ret = kvm_put_nested_state(x86_cpu);
3493 if (ret < 0) {
3494 return ret;
3495 }
3496
48e1a45c 3497 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 3498 ret = kvm_put_msr_feature_control(x86_cpu);
3499 if (ret < 0) {
3500 return ret;
3501 }
3502 }
3503
36f96c4b
HZ		 3504 if (level == KVM_PUT_FULL_STATE) {
3505 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3506 * because TSC frequency mismatch shouldn't abort migration,
3507 * unless the user explicitly asked for a more strict TSC
3508 * setting (e.g. using an explicit "tsc-freq" option).
3509 */
3510 kvm_arch_set_tsc_khz(cpu);
3511 }
3512
1bc22652 3513 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3514 if (ret < 0) {
05330448 3515 return ret;
b9bec74b 3516 }
1bc22652 3517 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3518 if (ret < 0) {
f1665b21 3519 return ret;
b9bec74b 3520 }
1bc22652 3521 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3522 if (ret < 0) {
05330448 3523 return ret;
b9bec74b 3524 }
1bc22652 3525 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3526 if (ret < 0) {
05330448 3527 return ret;
b9bec74b 3528 }
ab443475 3529 /* must be before kvm_put_msrs */
1bc22652 3530 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3531 if (ret < 0) {
3532 return ret;
3533 }
1bc22652 3534 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3535 if (ret < 0) {
05330448 3536 return ret;
b9bec74b 3537 }
4fadfa00
PH		 3538 ret = kvm_put_vcpu_events(x86_cpu, level);
3539 if (ret < 0) {
3540 return ret;
3541 }
ea643051 3542 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3543 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3544 if (ret < 0) {
680c1c6f
JK		 3545 return ret;
3546 }
ea643051 3547 }
7477cd38
MT		 3548
3549 ret = kvm_put_tscdeadline_msr(x86_cpu);
3550 if (ret < 0) {
3551 return ret;
3552 }
1bc22652 3553 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3554 if (ret < 0) {
b0b1d690 3555 return ret;
b9bec74b 3556 }
b0b1d690 3557 /* must be last */
1bc22652 3558 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3559 if (ret < 0) {
ff44f1a3 3560 return ret;
b9bec74b 3561 }
05330448
AL		 3562 return 0;
3563}
3564
20d695a9 3565int kvm_arch_get_registers(CPUState *cs)
05330448 3566{
20d695a9 3567 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3568 int ret;
3569
20d695a9 3570 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3571
4fadfa00 3572 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3573 if (ret < 0) {
f4f1110e 3574 goto out;
b9bec74b 3575 }
4fadfa00
PH		 3576 /*
3577 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3578 * KVM_GET_REGS and KVM_GET_SREGS.
3579 */
3580 ret = kvm_get_mp_state(cpu);
b9bec74b 3581 if (ret < 0) {
f4f1110e 3582 goto out;
b9bec74b 3583 }
4fadfa00 3584 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3585 if (ret < 0) {
f4f1110e 3586 goto out;
b9bec74b 3587 }
4fadfa00 3588 ret = kvm_get_xsave(cpu);
b9bec74b 3589 if (ret < 0) {
f4f1110e 3590 goto out;
b9bec74b 3591 }
4fadfa00 3592 ret = kvm_get_xcrs(cpu);
b9bec74b 3593 if (ret < 0) {
f4f1110e 3594 goto out;
b9bec74b 3595 }
4fadfa00 3596 ret = kvm_get_sregs(cpu);
b9bec74b 3597 if (ret < 0) {
f4f1110e 3598 goto out;
b9bec74b 3599 }
4fadfa00 3600 ret = kvm_get_msrs(cpu);
680c1c6f 3601 if (ret < 0) {
f4f1110e 3602 goto out;
680c1c6f 3603 }
4fadfa00 3604 ret = kvm_get_apic(cpu);
b9bec74b 3605 if (ret < 0) {
f4f1110e 3606 goto out;
b9bec74b 3607 }
1bc22652 3608 ret = kvm_get_debugregs(cpu);
b9bec74b 3609 if (ret < 0) {
f4f1110e 3610 goto out;
b9bec74b 3611 }
ebbfef2f
LA		 3612 ret = kvm_get_nested_state(cpu);
3613 if (ret < 0) {
3614 goto out;
3615 }
f4f1110e
RH		 3616 ret = 0;
3617 out:
3618 cpu_sync_bndcs_hflags(&cpu->env);
3619 return ret;
05330448
AL		 3620}
3621
20d695a9 3622void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3623{
20d695a9
AF		 3624 X86CPU *x86_cpu = X86_CPU(cpu);
3625 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3626 int ret;
3627
276ce815 3628 /* Inject NMI */
fc12d72e
PB		 3629 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3630 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3631 qemu_mutex_lock_iothread();
3632 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3633 qemu_mutex_unlock_iothread();
3634 DPRINTF("injected NMI\n");
3635 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3636 if (ret < 0) {
3637 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3638 strerror(-ret));
3639 }
3640 }
3641 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3642 qemu_mutex_lock_iothread();
3643 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3644 qemu_mutex_unlock_iothread();
3645 DPRINTF("injected SMI\n");
3646 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3647 if (ret < 0) {
3648 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3649 strerror(-ret));
3650 }
ce377af3 3651 }
276ce815
LJ		 3652 }
3653
15eafc2e 3654 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3655 qemu_mutex_lock_iothread();
3656 }
3657
e0723c45
PB		 3658 /* Force the VCPU out of its inner loop to process any INIT requests
3659 * or (for userspace APIC, but it is cheap to combine the checks here)
3660 * pending TPR access reports.
3661 */
3662 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3663 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3664 !(env->hflags & HF_SMM_MASK)) {
3665 cpu->exit_request = 1;
3666 }
3667 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3668 cpu->exit_request = 1;
3669 }
e0723c45 3670 }
05330448 3671
15eafc2e 3672 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3673 /* Try to inject an interrupt if the guest can accept it */
3674 if (run->ready_for_interrupt_injection &&
259186a7 3675 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3676 (env->eflags & IF_MASK)) {
3677 int irq;
3678
259186a7 3679 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3680 irq = cpu_get_pic_interrupt(env);
3681 if (irq >= 0) {
3682 struct kvm_interrupt intr;
3683
3684 intr.irq = irq;
db1669bc 3685 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3686 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3687 if (ret < 0) {
3688 fprintf(stderr,
3689 "KVM: injection failed, interrupt lost (%s)\n",
3690 strerror(-ret));
3691 }
db1669bc
JK		 3692 }
3693 }
05330448 3694
db1669bc
JK		 3695 /* If we have an interrupt but the guest is not ready to receive an
3696 * interrupt, request an interrupt window exit. This will
3697 * cause a return to userspace as soon as the guest is ready to
3698 * receive interrupts. */
259186a7 3699 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3700 run->request_interrupt_window = 1;
3701 } else {
3702 run->request_interrupt_window = 0;
3703 }
3704
3705 DPRINTF("setting tpr\n");
02e51483 3706 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3707
3708 qemu_mutex_unlock_iothread();
db1669bc 3709 }
05330448
AL		 3710}
3711
4c663752 3712MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3713{
20d695a9
AF		 3714 X86CPU *x86_cpu = X86_CPU(cpu);
3715 CPUX86State *env = &x86_cpu->env;
3716
fc12d72e
PB		 3717 if (run->flags & KVM_RUN_X86_SMM) {
3718 env->hflags |= HF_SMM_MASK;
3719 } else {
f5c052b9 3720 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3721 }
b9bec74b 3722 if (run->if_flag) {
05330448 3723 env->eflags |= IF_MASK;
b9bec74b 3724 } else {
05330448 3725 env->eflags &= ~IF_MASK;
b9bec74b 3726 }
4b8523ee
JK		 3727
3728 /* We need to protect the apic state against concurrent accesses from
3729 * different threads in case the userspace irqchip is used. */
3730 if (!kvm_irqchip_in_kernel()) {
3731 qemu_mutex_lock_iothread();
3732 }
02e51483
CF		 3733 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3734 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3735 if (!kvm_irqchip_in_kernel()) {
3736 qemu_mutex_unlock_iothread();
3737 }
f794aa4a 3738 return cpu_get_mem_attrs(env);
05330448
AL		 3739}
3740
20d695a9 3741int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3742{
20d695a9
AF		 3743 X86CPU *cpu = X86_CPU(cs);
3744 CPUX86State *env = &cpu->env;
232fc23b 3745
259186a7 3746 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3747 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3748 assert(env->mcg_cap);
3749
259186a7 3750 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3751
dd1750d7 3752 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3753
3754 if (env->exception_injected == EXCP08_DBLE) {
3755 /* this means triple fault */
cf83f140 3756 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3757 cs->exit_request = 1;
ab443475
JK		 3758 return 0;
3759 }
3760 env->exception_injected = EXCP12_MCHK;
3761 env->has_error_code = 0;
3762
259186a7 3763 cs->halted = 0;
ab443475
JK		 3764 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3765 env->mp_state = KVM_MP_STATE_RUNNABLE;
3766 }
3767 }
3768
fc12d72e
PB		 3769 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3770 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3771 kvm_cpu_synchronize_state(cs);
3772 do_cpu_init(cpu);
3773 }
3774
db1669bc
JK		 3775 if (kvm_irqchip_in_kernel()) {
3776 return 0;
3777 }
3778
259186a7
AF		 3779 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3780 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3781 apic_poll_irq(cpu->apic_state);
5d62c43a 3782 }
259186a7 3783 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3784 (env->eflags & IF_MASK)) ||
259186a7
AF		 3785 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3786 cs->halted = 0;
6792a57b 3787 }
259186a7 3788 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3789 kvm_cpu_synchronize_state(cs);
232fc23b 3790 do_cpu_sipi(cpu);
0af691d7 3791 }
259186a7
AF		 3792 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3793 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3794 kvm_cpu_synchronize_state(cs);
02e51483 3795 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3796 env->tpr_access_type);
3797 }
0af691d7 3798
259186a7 3799 return cs->halted;
0af691d7
MT		 3800}
3801
839b5630 3802static int kvm_handle_halt(X86CPU *cpu)
05330448 3803{
259186a7 3804 CPUState *cs = CPU(cpu);
839b5630
AF		 3805 CPUX86State *env = &cpu->env;
3806
259186a7 3807 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3808 (env->eflags & IF_MASK)) &&
259186a7
AF		 3809 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3810 cs->halted = 1;
bb4ea393 3811 return EXCP_HLT;
05330448
AL		 3812 }
3813
bb4ea393 3814 return 0;
05330448
AL		 3815}
3816
f7575c96 3817static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3818{
f7575c96
AF		 3819 CPUState *cs = CPU(cpu);
3820 struct kvm_run *run = cs->kvm_run;
d362e757 3821
02e51483 3822 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3823 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3824 : TPR_ACCESS_READ);
3825 return 1;
3826}
3827
f17ec444 3828int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3829{
38972938 3830 static const uint8_t int3 = 0xcc;
64bf3f4e 3831
f17ec444
AF		 3832 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3833 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3834 return -EINVAL;
b9bec74b 3835 }
e22a25c9
AL		 3836 return 0;
3837}
3838
f17ec444 3839int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3840{
3841 uint8_t int3;
3842
f17ec444
AF		 3843 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3844 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3845 return -EINVAL;
b9bec74b 3846 }
e22a25c9
AL		 3847 return 0;
3848}
3849
3850static struct {
3851 target_ulong addr;
3852 int len;
3853 int type;
3854} hw_breakpoint[4];
3855
3856static int nb_hw_breakpoint;
3857
3858static int find_hw_breakpoint(target_ulong addr, int len, int type)
3859{
3860 int n;
3861
b9bec74b 3862 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3863 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3864 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3865 return n;
b9bec74b
JK		 3866 }
3867 }
e22a25c9
AL		 3868 return -1;
3869}
3870
3871int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3872 target_ulong len, int type)
3873{
3874 switch (type) {
3875 case GDB_BREAKPOINT_HW:
3876 len = 1;
3877 break;
3878 case GDB_WATCHPOINT_WRITE:
3879 case GDB_WATCHPOINT_ACCESS:
3880 switch (len) {
3881 case 1:
3882 break;
3883 case 2:
3884 case 4:
3885 case 8:
b9bec74b 3886 if (addr & (len - 1)) {
e22a25c9 3887 return -EINVAL;
b9bec74b 3888 }
e22a25c9
AL		 3889 break;
3890 default:
3891 return -EINVAL;
3892 }
3893 break;
3894 default:
3895 return -ENOSYS;
3896 }
3897
b9bec74b 3898 if (nb_hw_breakpoint == 4) {
e22a25c9 3899 return -ENOBUFS;
b9bec74b
JK		 3900 }
3901 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3902 return -EEXIST;
b9bec74b 3903 }
e22a25c9
AL		 3904 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3905 hw_breakpoint[nb_hw_breakpoint].len = len;
3906 hw_breakpoint[nb_hw_breakpoint].type = type;
3907 nb_hw_breakpoint++;
3908
3909 return 0;
3910}
3911
3912int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3913 target_ulong len, int type)
3914{
3915 int n;
3916
3917 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3918 if (n < 0) {
e22a25c9 3919 return -ENOENT;
b9bec74b 3920 }
e22a25c9
AL		 3921 nb_hw_breakpoint--;
3922 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3923
3924 return 0;
3925}
3926
3927void kvm_arch_remove_all_hw_breakpoints(void)
3928{
3929 nb_hw_breakpoint = 0;
3930}
3931
3932static CPUWatchpoint hw_watchpoint;
3933
a60f24b5 3934static int kvm_handle_debug(X86CPU *cpu,
48405526 3935 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3936{
ed2803da 3937 CPUState *cs = CPU(cpu);
a60f24b5 3938 CPUX86State *env = &cpu->env;
f2574737 3939 int ret = 0;
e22a25c9
AL		 3940 int n;
3941
37936ac7
LA		 3942 if (arch_info->exception == EXCP01_DB) {
3943 if (arch_info->dr6 & DR6_BS) {
ed2803da 3944 if (cs->singlestep_enabled) {
f2574737 3945 ret = EXCP_DEBUG;
b9bec74b 3946 }
e22a25c9 3947 } else {
b9bec74b
JK		 3948 for (n = 0; n < 4; n++) {
3949 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3950 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3951 case 0x0:
f2574737 3952 ret = EXCP_DEBUG;
e22a25c9
AL		 3953 break;
3954 case 0x1:
f2574737 3955 ret = EXCP_DEBUG;
ff4700b0 3956 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3957 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3958 hw_watchpoint.flags = BP_MEM_WRITE;
3959 break;
3960 case 0x3:
f2574737 3961 ret = EXCP_DEBUG;
ff4700b0 3962 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3963 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3964 hw_watchpoint.flags = BP_MEM_ACCESS;
3965 break;
3966 }
b9bec74b
JK		 3967 }
3968 }
e22a25c9 3969 }
ff4700b0 3970 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3971 ret = EXCP_DEBUG;
b9bec74b 3972 }
f2574737 3973 if (ret == 0) {
ff4700b0 3974 cpu_synchronize_state(cs);
48405526 3975 assert(env->exception_injected == -1);
b0b1d690 3976
f2574737 3977 /* pass to guest */
48405526
BS		 3978 env->exception_injected = arch_info->exception;
3979 env->has_error_code = 0;
bceeeef9
LA		 3980 if (arch_info->exception == EXCP01_DB) {
3981 env->dr[6] = arch_info->dr6;
3982 }
b0b1d690 3983 }
e22a25c9 3984
f2574737 3985 return ret;
e22a25c9
AL		 3986}
3987
20d695a9 3988void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3989{
3990 const uint8_t type_code[] = {
3991 [GDB_BREAKPOINT_HW] = 0x0,
3992 [GDB_WATCHPOINT_WRITE] = 0x1,
3993 [GDB_WATCHPOINT_ACCESS] = 0x3
3994 };
3995 const uint8_t len_code[] = {
3996 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3997 };
3998 int n;
3999
a60f24b5 4000 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 4001 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 4002 }
e22a25c9
AL		 4003 if (nb_hw_breakpoint > 0) {
4004 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
4005 dbg->arch.debugreg[7] = 0x0600;
4006 for (n = 0; n < nb_hw_breakpoint; n++) {
4007 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
4008 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
4009 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 4010 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 4011 }
4012 }
4013}
4513d923 4014
2a4dac83
JK		 4015static bool host_supports_vmx(void)
4016{
4017 uint32_t ecx, unused;
4018
4019 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
4020 return ecx & CPUID_EXT_VMX;
4021}
4022
4023#define VMX_INVALID_GUEST_STATE 0x80000021
4024
20d695a9 4025int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 4026{
20d695a9 4027 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 4028 uint64_t code;
4029 int ret;
4030
4031 switch (run->exit_reason) {
4032 case KVM_EXIT_HLT:
4033 DPRINTF("handle_hlt\n");
4b8523ee 4034 qemu_mutex_lock_iothread();
839b5630 4035 ret = kvm_handle_halt(cpu);
4b8523ee 4036 qemu_mutex_unlock_iothread();
2a4dac83
JK		 4037 break;
4038 case KVM_EXIT_SET_TPR:
4039 ret = 0;
4040 break;
d362e757 4041 case KVM_EXIT_TPR_ACCESS:
4b8523ee 4042 qemu_mutex_lock_iothread();
f7575c96 4043 ret = kvm_handle_tpr_access(cpu);
4b8523ee 4044 qemu_mutex_unlock_iothread();
d362e757 4045 break;
2a4dac83
JK		 4046 case KVM_EXIT_FAIL_ENTRY:
4047 code = run->fail_entry.hardware_entry_failure_reason;
4048 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
4049 code);
4050 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
4051 fprintf(stderr,
12619721 4052 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 4053 "unrestricted mode\n"
4054 "support, the failure can be most likely due to the guest "
4055 "entering an invalid\n"
4056 "state for Intel VT. For example, the guest maybe running "
4057 "in big real mode\n"
4058 "which is not supported on less recent Intel processors."
4059 "\n\n");
4060 }
4061 ret = -1;
4062 break;
4063 case KVM_EXIT_EXCEPTION:
4064 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
4065 run->ex.exception, run->ex.error_code);
4066 ret = -1;
4067 break;
f2574737
JK		 4068 case KVM_EXIT_DEBUG:
4069 DPRINTF("kvm_exit_debug\n");
4b8523ee 4070 qemu_mutex_lock_iothread();
a60f24b5 4071 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 4072 qemu_mutex_unlock_iothread();
f2574737 4073 break;
50efe82c
AS		 4074 case KVM_EXIT_HYPERV:
4075 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
4076 break;
15eafc2e
PB		 4077 case KVM_EXIT_IOAPIC_EOI:
4078 ioapic_eoi_broadcast(run->eoi.vector);
4079 ret = 0;
4080 break;
2a4dac83
JK		 4081 default:
4082 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
4083 ret = -1;
4084 break;
4085 }
4086
4087 return ret;
4088}
4089
20d695a9 4090bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 4091{
20d695a9
AF		 4092 X86CPU *cpu = X86_CPU(cs);
4093 CPUX86State *env = &cpu->env;
4094
dd1750d7 4095 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 4096 return !(env->cr[0] & CR0_PE_MASK) ||
4097 ((env->segs[R_CS].selector & 3) != 3);
4513d923 4098}
84b058d7
JK		 4099
4100void kvm_arch_init_irq_routing(KVMState *s)
4101{
4102 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
4103 /* If kernel can't do irq routing, interrupt source
4104 * override 0->2 cannot be set up as required by HPET.
4105 * So we have to disable it.
4106 */
4107 no_hpet = 1;
4108 }
cc7e0ddf 4109 /* We know at this point that we're using the in-kernel
614e41bc 4110 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 4111 * we can use msi via irqfd and GSI routing.
cc7e0ddf 4112 */
614e41bc 4113 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 4114 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 4115
4116 if (kvm_irqchip_is_split()) {
4117 int i;
4118
4119 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
4120 MSI routes for signaling interrupts to the local apics. */
4121 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 4122 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 4123 error_report("Could not enable split IRQ mode.");
4124 exit(1);
4125 }
4126 }
4127 }
4128}
4129
4130int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
4131{
4132 int ret;
4133 if (machine_kernel_irqchip_split(ms)) {
4134 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
4135 if (ret) {
df3c286c 4136 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 4137 strerror(-ret));
4138 exit(1);
4139 } else {
4140 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
4141 kvm_split_irqchip = true;
4142 return 1;
4143 }
4144 } else {
4145 return 0;
4146 }
84b058d7 4147}
b139bd30
JK		 4148
4149/* Classic KVM device assignment interface. Will remain x86 only. */
4150int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
4151 uint32_t flags, uint32_t *dev_id)
4152{
4153 struct kvm_assigned_pci_dev dev_data = {
4154 .segnr = dev_addr->domain,
4155 .busnr = dev_addr->bus,
4156 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
4157 .flags = flags,
4158 };
4159 int ret;
4160
4161 dev_data.assigned_dev_id =
4162 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
4163
4164 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
4165 if (ret < 0) {
4166 return ret;
4167 }
4168
4169 *dev_id = dev_data.assigned_dev_id;
4170
4171 return 0;
4172}
4173
4174int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
4175{
4176 struct kvm_assigned_pci_dev dev_data = {
4177 .assigned_dev_id = dev_id,
4178 };
4179
4180 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
4181}
4182
4183static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
4184 uint32_t irq_type, uint32_t guest_irq)
4185{
4186 struct kvm_assigned_irq assigned_irq = {
4187 .assigned_dev_id = dev_id,
4188 .guest_irq = guest_irq,
4189 .flags = irq_type,
4190 };
4191
4192 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
4193 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
4194 } else {
4195 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
4196 }
4197}
4198
4199int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
4200 uint32_t guest_irq)
4201{
4202 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
4203 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
4204
4205 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
4206}
4207
4208int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
4209{
4210 struct kvm_assigned_pci_dev dev_data = {
4211 .assigned_dev_id = dev_id,
4212 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
4213 };
4214
4215 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
4216}
4217
4218static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
4219 uint32_t type)
4220{
4221 struct kvm_assigned_irq assigned_irq = {
4222 .assigned_dev_id = dev_id,
4223 .flags = type,
4224 };
4225
4226 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
4227}
4228
4229int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
4230{
4231 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
4232 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
4233}
4234
4235int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
4236{
4237 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
4238 KVM_DEV_IRQ_GUEST_MSI, virq);
4239}
4240
4241int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
4242{
4243 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
4244 KVM_DEV_IRQ_HOST_MSI);
4245}
4246
4247bool kvm_device_msix_supported(KVMState *s)
4248{
4249 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
4250 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
4251 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
4252}
4253
4254int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
4255 uint32_t nr_vectors)
4256{
4257 struct kvm_assigned_msix_nr msix_nr = {
4258 .assigned_dev_id = dev_id,
4259 .entry_nr = nr_vectors,
4260 };
4261
4262 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
4263}
4264
4265int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
4266 int virq)
4267{
4268 struct kvm_assigned_msix_entry msix_entry = {
4269 .assigned_dev_id = dev_id,
4270 .gsi = virq,
4271 .entry = vector,
4272 };
4273
4274 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
4275}
4276
4277int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
4278{
4279 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
4280 KVM_DEV_IRQ_GUEST_MSIX, 0);
4281}
4282
4283int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
4284{
4285 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
4286 KVM_DEV_IRQ_HOST_MSIX);
4287}
9e03a040
FB		 4288
4289int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 4290 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 4291{
8b5ed7df
PX		 4292 X86IOMMUState *iommu = x86_iommu_get_default();
4293
4294 if (iommu) {
4295 int ret;
4296 MSIMessage src, dst;
4297 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
4298
0ea1472d
JK		 4299 if (!class->int_remap) {
4300 return 0;
4301 }
4302
8b5ed7df
PX		 4303 src.address = route->u.msi.address_hi;
4304 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
4305 src.address |= route->u.msi.address_lo;
4306 src.data = route->u.msi.data;
4307
4308 ret = class->int_remap(iommu, &src, &dst, dev ? \
4309 pci_requester_id(dev) : \
4310 X86_IOMMU_SID_INVALID);
4311 if (ret) {
4312 trace_kvm_x86_fixup_msi_error(route->gsi);
4313 return 1;
4314 }
4315
4316 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
4317 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
4318 route->u.msi.data = dst.data;
4319 }
4320
9e03a040
FB		 4321 return 0;
4322}
1850b6b7 4323
38d87493
PX		 4324typedef struct MSIRouteEntry MSIRouteEntry;
4325
4326struct MSIRouteEntry {
4327 PCIDevice *dev; /* Device pointer */
4328 int vector; /* MSI/MSIX vector index */
4329 int virq; /* Virtual IRQ index */
4330 QLIST_ENTRY(MSIRouteEntry) list;
4331};
4332
4333/* List of used GSI routes */
4334static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
4335 QLIST_HEAD_INITIALIZER(msi_route_list);
4336
e1d4fb2d
PX		 4337static void kvm_update_msi_routes_all(void *private, bool global,
4338 uint32_t index, uint32_t mask)
4339{
a56de056 4340 int cnt = 0, vector;
e1d4fb2d
PX		 4341 MSIRouteEntry *entry;
4342 MSIMessage msg;
fd563564
PX		 4343 PCIDevice *dev;
4344
e1d4fb2d
PX		 4345 /* TODO: explicit route update */
4346 QLIST_FOREACH(entry, &msi_route_list, list) {
4347 cnt++;
a56de056 4348 vector = entry->vector;
fd563564 4349 dev = entry->dev;
a56de056
PX		 4350 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
4351 msg = msix_get_message(dev, vector);
4352 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
4353 msg = msi_get_message(dev, vector);
4354 } else {
4355 /*
4356 * Either MSI/MSIX is disabled for the device, or the
4357 * specific message was masked out. Skip this one.
4358 */
fd563564
PX		 4359 continue;
4360 }
fd563564 4361 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 4362 }
3f1fea0f 4363 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 4364 trace_kvm_x86_update_msi_routes(cnt);
4365}
4366
38d87493
PX		 4367int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
4368 int vector, PCIDevice *dev)
4369{
e1d4fb2d 4370 static bool notify_list_inited = false;
38d87493
PX		 4371 MSIRouteEntry *entry;
4372
4373 if (!dev) {
4374 /* These are (possibly) IOAPIC routes only used for split
4375 * kernel irqchip mode, while what we are housekeeping are
4376 * PCI devices only. */
4377 return 0;
4378 }
4379
4380 entry = g_new0(MSIRouteEntry, 1);
4381 entry->dev = dev;
4382 entry->vector = vector;
4383 entry->virq = route->gsi;
4384 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
4385
4386 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 4387
4388 if (!notify_list_inited) {
4389 /* For the first time we do add route, add ourselves into
4390 * IOMMU's IEC notify list if needed. */
4391 X86IOMMUState *iommu = x86_iommu_get_default();
4392 if (iommu) {
4393 x86_iommu_iec_register_notifier(iommu,
4394 kvm_update_msi_routes_all,
4395 NULL);
4396 }
4397 notify_list_inited = true;
4398 }
38d87493
PX		 4399 return 0;
4400}
4401
4402int kvm_arch_release_virq_post(int virq)
4403{
4404 MSIRouteEntry *entry, *next;
4405 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
4406 if (entry->virq == virq) {
4407 trace_kvm_x86_remove_msi_route(virq);
4408 QLIST_REMOVE(entry, list);
01960e6d 4409 g_free(entry);
38d87493
PX		 4410 break;
4411 }
4412 }
9e03a040
FB		 4413 return 0;
4414}
1850b6b7
EA		 4415
4416int kvm_arch_msi_data_to_gsi(uint32_t data)
4417{
4418 abort();
4419}
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