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target-arm: Convert cp15 cache ID registers
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31 1#include "cpu.h"
9ee6e8bb 2#include "gdbstub.h"
7b59220e 3#include "helper.h"
7bbcb0af 4#include "host-utils.h"
0b03bdfc
PM		 5#include "sysemu.h"
6
4a501606
PM		 7#ifndef CONFIG_USER_ONLY
8static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9 int access_type, int is_user,
10 uint32_t *phys_ptr, int *prot,
11 target_ulong *page_size);
12#endif
13
0ecb72a5 14static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 15{
16 int nregs;
17
18 /* VFP data registers are always little-endian. */
19 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
20 if (reg < nregs) {
21 stfq_le_p(buf, env->vfp.regs[reg]);
22 return 8;
23 }
24 if (arm_feature(env, ARM_FEATURE_NEON)) {
25 /* Aliases for Q regs. */
26 nregs += 16;
27 if (reg < nregs) {
28 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
29 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
30 return 16;
31 }
32 }
33 switch (reg - nregs) {
34 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
35 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
36 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
37 }
38 return 0;
39}
40
0ecb72a5 41static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
56aebc89
PB		 42{
43 int nregs;
44
45 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
46 if (reg < nregs) {
47 env->vfp.regs[reg] = ldfq_le_p(buf);
48 return 8;
49 }
50 if (arm_feature(env, ARM_FEATURE_NEON)) {
51 nregs += 16;
52 if (reg < nregs) {
53 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
54 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
55 return 16;
56 }
57 }
58 switch (reg - nregs) {
59 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
60 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
71b3c3de 61 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
56aebc89
PB		 62 }
63 return 0;
64}
65
c983fe6c
PM		 66static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
67{
68 env->cp15.c3 = value;
69 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
70 return 0;
71}
72
08de207b
PM		 73static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
74{
75 if (env->cp15.c13_fcse != value) {
76 /* Unlike real hardware the qemu TLB uses virtual addresses,
77 * not modified virtual addresses, so this causes a TLB flush.
78 */
79 tlb_flush(env, 1);
80 env->cp15.c13_fcse = value;
81 }
82 return 0;
83}
84static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
85 uint64_t value)
86{
87 if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
88 /* For VMSA (when not using the LPAE long descriptor page table
89 * format) this register includes the ASID, so do a TLB flush.
90 * For PMSA it is purely a process ID and no action is needed.
91 */
92 tlb_flush(env, 1);
93 }
94 env->cp15.c13_context = value;
95 return 0;
96}
97
d929823f
PM		 98static int tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
99 uint64_t value)
100{
101 /* Invalidate all (TLBIALL) */
102 tlb_flush(env, 1);
103 return 0;
104}
105
106static int tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
107 uint64_t value)
108{
109 /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
110 tlb_flush_page(env, value & TARGET_PAGE_MASK);
111 return 0;
112}
113
114static int tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
115 uint64_t value)
116{
117 /* Invalidate by ASID (TLBIASID) */
118 tlb_flush(env, value == 0);
119 return 0;
120}
121
122static int tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
123 uint64_t value)
124{
125 /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
126 tlb_flush_page(env, value & TARGET_PAGE_MASK);
127 return 0;
128}
129
e9aa6c21
PM		 130static const ARMCPRegInfo cp_reginfo[] = {
131 /* DBGDIDR: just RAZ. In particular this means the "debug architecture
132 * version" bits will read as a reserved value, which should cause
133 * Linux to not try to use the debug hardware.
134 */
135 { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
136 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
c983fe6c
PM		 137 /* MMU Domain access control / MPU write buffer control */
138 { .name = "DACR", .cp = 15,
139 .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
140 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
141 .resetvalue = 0, .writefn = dacr_write },
08de207b
PM		 142 { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
143 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
144 .resetvalue = 0, .writefn = fcse_write },
145 { .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
146 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
147 .resetvalue = 0, .writefn = contextidr_write },
4fdd17dd
PM		 148 /* ??? This covers not just the impdef TLB lockdown registers but also
149 * some v7VMSA registers relating to TEX remap, so it is overly broad.
150 */
151 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
152 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
d929823f
PM		 153 /* MMU TLB control. Note that the wildcarding means we cover not just
154 * the unified TLB ops but also the dside/iside/inner-shareable variants.
155 */
156 { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
157 .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write, },
158 { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
159 .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write, },
160 { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
161 .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write, },
162 { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
163 .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write, },
c4804214
PM		 164 /* Cache maintenance ops; some of this space may be overridden later. */
165 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
166 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
167 .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
e9aa6c21
PM		 168 REGINFO_SENTINEL
169};
170
7d57f408
PM		 171static const ARMCPRegInfo not_v6_cp_reginfo[] = {
172 /* Not all pre-v6 cores implemented this WFI, so this is slightly
173 * over-broad.
174 */
175 { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
176 .access = PL1_W, .type = ARM_CP_WFI },
177 REGINFO_SENTINEL
178};
179
180static const ARMCPRegInfo not_v7_cp_reginfo[] = {
181 /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
182 * is UNPREDICTABLE; we choose to NOP as most implementations do).
183 */
184 { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
185 .access = PL1_W, .type = ARM_CP_WFI },
34f90529
PM		 186 /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
187 * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
188 * OMAPCP will override this space.
189 */
190 { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
191 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
192 .resetvalue = 0 },
193 { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
194 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
195 .resetvalue = 0 },
776d4e5c
PM		 196 /* v6 doesn't have the cache ID registers but Linux reads them anyway */
197 { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
198 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 199 REGINFO_SENTINEL
200};
201
2771db27
PM		 202static int cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
203{
204 if (env->cp15.c1_coproc != value) {
205 env->cp15.c1_coproc = value;
206 /* ??? Is this safe when called from within a TB? */
207 tb_flush(env);
208 }
209 return 0;
210}
211
7d57f408
PM		 212static const ARMCPRegInfo v6_cp_reginfo[] = {
213 /* prefetch by MVA in v6, NOP in v7 */
214 { .name = "MVA_prefetch",
215 .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
216 .access = PL1_W, .type = ARM_CP_NOP },
217 { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
218 .access = PL0_W, .type = ARM_CP_NOP },
219 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
220 .access = PL0_W, .type = ARM_CP_NOP },
221 { .name = "ISB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
222 .access = PL0_W, .type = ARM_CP_NOP },
06d76f31
PM		 223 { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
224 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_insn),
225 .resetvalue = 0, },
226 /* Watchpoint Fault Address Register : should actually only be present
227 * for 1136, 1176, 11MPCore.
228 */
229 { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
230 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
2771db27
PM		 231 { .name = "CPACR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
232 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
233 .resetvalue = 0, .writefn = cpacr_write },
7d57f408
PM		 234 REGINFO_SENTINEL
235};
236
200ac0ef
PM		 237static int pmreg_read(CPUARMState *env, const ARMCPRegInfo *ri,
238 uint64_t *value)
239{
240 /* Generic performance monitor register read function for where
241 * user access may be allowed by PMUSERENR.
242 */
243 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
244 return EXCP_UDEF;
245 }
246 *value = CPREG_FIELD32(env, ri);
247 return 0;
248}
249
250static int pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
251 uint64_t value)
252{
253 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
254 return EXCP_UDEF;
255 }
256 /* only the DP, X, D and E bits are writable */
257 env->cp15.c9_pmcr &= ~0x39;
258 env->cp15.c9_pmcr |= (value & 0x39);
259 return 0;
260}
261
262static int pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
263 uint64_t value)
264{
265 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
266 return EXCP_UDEF;
267 }
268 value &= (1 << 31);
269 env->cp15.c9_pmcnten |= value;
270 return 0;
271}
272
273static int pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
274 uint64_t value)
275{
276 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
277 return EXCP_UDEF;
278 }
279 value &= (1 << 31);
280 env->cp15.c9_pmcnten &= ~value;
281 return 0;
282}
283
284static int pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
285 uint64_t value)
286{
287 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
288 return EXCP_UDEF;
289 }
290 env->cp15.c9_pmovsr &= ~value;
291 return 0;
292}
293
294static int pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
295 uint64_t value)
296{
297 if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
298 return EXCP_UDEF;
299 }
300 env->cp15.c9_pmxevtyper = value & 0xff;
301 return 0;
302}
303
304static int pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
305 uint64_t value)
306{
307 env->cp15.c9_pmuserenr = value & 1;
308 return 0;
309}
310
311static int pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
312 uint64_t value)
313{
314 /* We have no event counters so only the C bit can be changed */
315 value &= (1 << 31);
316 env->cp15.c9_pminten |= value;
317 return 0;
318}
319
320static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
321 uint64_t value)
322{
323 value &= (1 << 31);
324 env->cp15.c9_pminten &= ~value;
325 return 0;
326}
327
776d4e5c
PM		 328static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri,
329 uint64_t *value)
330{
331 ARMCPU *cpu = arm_env_get_cpu(env);
332 *value = cpu->ccsidr[env->cp15.c0_cssel];
333 return 0;
334}
335
336static int csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
337 uint64_t value)
338{
339 env->cp15.c0_cssel = value & 0xf;
340 return 0;
341}
342
e9aa6c21
PM		 343static const ARMCPRegInfo v7_cp_reginfo[] = {
344 /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
345 * debug components
346 */
347 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
348 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
349 { .name = "DBGDRAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
350 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
7d57f408
PM		 351 /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
352 { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
353 .access = PL1_W, .type = ARM_CP_NOP },
200ac0ef
PM		 354 /* Performance monitors are implementation defined in v7,
355 * but with an ARM recommended set of registers, which we
356 * follow (although we don't actually implement any counters)
357 *
358 * Performance registers fall into three categories:
359 * (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
360 * (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
361 * (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
362 * For the cases controlled by PMUSERENR we must set .access to PL0_RW
363 * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
364 */
365 { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
366 .access = PL0_RW, .resetvalue = 0,
367 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
368 .readfn = pmreg_read, .writefn = pmcntenset_write },
369 { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
370 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
371 .readfn = pmreg_read, .writefn = pmcntenclr_write },
372 { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
373 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
374 .readfn = pmreg_read, .writefn = pmovsr_write },
375 /* Unimplemented so WI. Strictly speaking write accesses in PL0 should
376 * respect PMUSERENR.
377 */
378 { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
379 .access = PL0_W, .type = ARM_CP_NOP },
380 /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
381 * We choose to RAZ/WI. XXX should respect PMUSERENR.
382 */
383 { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
384 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
385 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
386 { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
387 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
388 { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
389 .access = PL0_RW,
390 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
391 .readfn = pmreg_read, .writefn = pmxevtyper_write },
392 /* Unimplemented, RAZ/WI. XXX PMUSERENR */
393 { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
394 .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
395 { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
396 .access = PL0_R | PL1_RW,
397 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
398 .resetvalue = 0,
399 .writefn = pmuserenr_write },
400 { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
401 .access = PL1_RW,
402 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
403 .resetvalue = 0,
404 .writefn = pmintenset_write },
405 { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
406 .access = PL1_RW,
407 .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
408 .resetvalue = 0,
409 .writefn = pmintenclr_write },
2771db27
PM		 410 { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
411 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
412 .resetvalue = 0, },
776d4e5c
PM		 413 { .name = "CCSIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
414 .access = PL1_R, .readfn = ccsidr_read },
415 { .name = "CSSELR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
416 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
417 .writefn = csselr_write, .resetvalue = 0 },
418 /* Auxiliary ID register: this actually has an IMPDEF value but for now
419 * just RAZ for all cores:
420 */
421 { .name = "AIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 7,
422 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
e9aa6c21
PM		 423 REGINFO_SENTINEL
424};
425
c326b979
PM		 426static int teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
427{
428 value &= 1;
429 env->teecr = value;
430 return 0;
431}
432
433static int teehbr_read(CPUARMState *env, const ARMCPRegInfo *ri,
434 uint64_t *value)
435{
436 /* This is a helper function because the user access rights
437 * depend on the value of the TEECR.
438 */
439 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
440 return EXCP_UDEF;
441 }
442 *value = env->teehbr;
443 return 0;
444}
445
446static int teehbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
447 uint64_t value)
448{
449 if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
450 return EXCP_UDEF;
451 }
452 env->teehbr = value;
453 return 0;
454}
455
456static const ARMCPRegInfo t2ee_cp_reginfo[] = {
457 { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
458 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
459 .resetvalue = 0,
460 .writefn = teecr_write },
461 { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
462 .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
463 .resetvalue = 0,
464 .readfn = teehbr_read, .writefn = teehbr_write },
465 REGINFO_SENTINEL
466};
467
4d31c596
PM		 468static const ARMCPRegInfo v6k_cp_reginfo[] = {
469 { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
470 .access = PL0_RW,
471 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls1),
472 .resetvalue = 0 },
473 { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
474 .access = PL0_R|PL1_W,
475 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls2),
476 .resetvalue = 0 },
477 { .name = "TPIDRPRW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 4,
478 .access = PL1_RW,
479 .fieldoffset = offsetof(CPUARMState, cp15.c13_tls3),
480 .resetvalue = 0 },
481 REGINFO_SENTINEL
482};
483
6cc7a3ae
PM		 484static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
485 /* Dummy implementation: RAZ/WI the whole crn=14 space */
486 { .name = "GENERIC_TIMER", .cp = 15, .crn = 14,
487 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
488 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
489 REGINFO_SENTINEL
490};
491
4a501606
PM		 492static int par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
493{
494 if (arm_feature(env, ARM_FEATURE_V7)) {
495 env->cp15.c7_par = value & 0xfffff6ff;
496 } else {
497 env->cp15.c7_par = value & 0xfffff1ff;
498 }
499 return 0;
500}
501
502#ifndef CONFIG_USER_ONLY
503/* get_phys_addr() isn't present for user-mode-only targets */
504static int ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
505{
506 uint32_t phys_addr;
507 target_ulong page_size;
508 int prot;
509 int ret, is_user = ri->opc2 & 2;
510 int access_type = ri->opc2 & 1;
511
512 if (ri->opc2 & 4) {
513 /* Other states are only available with TrustZone */
514 return EXCP_UDEF;
515 }
516 ret = get_phys_addr(env, value, access_type, is_user,
517 &phys_addr, &prot, &page_size);
518 if (ret == 0) {
519 /* We do not set any attribute bits in the PAR */
520 if (page_size == (1 << 24)
521 && arm_feature(env, ARM_FEATURE_V7)) {
522 env->cp15.c7_par = (phys_addr & 0xff000000) | 1 << 1;
523 } else {
524 env->cp15.c7_par = phys_addr & 0xfffff000;
525 }
526 } else {
527 env->cp15.c7_par = ((ret & (10 << 1)) >> 5) |
528 ((ret & (12 << 1)) >> 6) |
529 ((ret & 0xf) << 1) | 1;
530 }
531 return 0;
532}
533#endif
534
535static const ARMCPRegInfo vapa_cp_reginfo[] = {
536 { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
537 .access = PL1_RW, .resetvalue = 0,
538 .fieldoffset = offsetof(CPUARMState, cp15.c7_par),
539 .writefn = par_write },
540#ifndef CONFIG_USER_ONLY
541 { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
542 .access = PL1_W, .writefn = ats_write },
543#endif
544 REGINFO_SENTINEL
545};
546
18032bec
PM		 547/* Return basic MPU access permission bits. */
548static uint32_t simple_mpu_ap_bits(uint32_t val)
549{
550 uint32_t ret;
551 uint32_t mask;
552 int i;
553 ret = 0;
554 mask = 3;
555 for (i = 0; i < 16; i += 2) {
556 ret |= (val >> i) & mask;
557 mask <<= 2;
558 }
559 return ret;
560}
561
562/* Pad basic MPU access permission bits to extended format. */
563static uint32_t extended_mpu_ap_bits(uint32_t val)
564{
565 uint32_t ret;
566 uint32_t mask;
567 int i;
568 ret = 0;
569 mask = 3;
570 for (i = 0; i < 16; i += 2) {
571 ret |= (val & mask) << i;
572 mask <<= 2;
573 }
574 return ret;
575}
576
577static int pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
578 uint64_t value)
579{
580 env->cp15.c5_data = extended_mpu_ap_bits(value);
581 return 0;
582}
583
584static int pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
585 uint64_t *value)
586{
587 *value = simple_mpu_ap_bits(env->cp15.c5_data);
588 return 0;
589}
590
591static int pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
592 uint64_t value)
593{
594 env->cp15.c5_insn = extended_mpu_ap_bits(value);
595 return 0;
596}
597
598static int pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri,
599 uint64_t *value)
600{
601 *value = simple_mpu_ap_bits(env->cp15.c5_insn);
602 return 0;
603}
604
06d76f31
PM		 605static int arm946_prbs_read(CPUARMState *env, const ARMCPRegInfo *ri,
606 uint64_t *value)
607{
608 if (ri->crm > 8) {
609 return EXCP_UDEF;
610 }
611 *value = env->cp15.c6_region[ri->crm];
612 return 0;
613}
614
615static int arm946_prbs_write(CPUARMState *env, const ARMCPRegInfo *ri,
616 uint64_t value)
617{
618 if (ri->crm > 8) {
619 return EXCP_UDEF;
620 }
621 env->cp15.c6_region[ri->crm] = value;
622 return 0;
623}
624
18032bec
PM		 625static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
626 { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
627 .access = PL1_RW,
628 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0,
629 .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
630 { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
631 .access = PL1_RW,
632 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0,
633 .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
634 { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
635 .access = PL1_RW,
636 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
637 { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
638 .access = PL1_RW,
639 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 640 { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
641 .access = PL1_RW,
642 .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
643 { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
644 .access = PL1_RW,
645 .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
06d76f31
PM		 646 /* Protection region base and size registers */
647 { .name = "946_PRBS", .cp = 15, .crn = 6, .crm = CP_ANY, .opc1 = 0,
648 .opc2 = CP_ANY, .access = PL1_RW,
649 .readfn = arm946_prbs_read, .writefn = arm946_prbs_write, },
18032bec
PM		 650 REGINFO_SENTINEL
651};
652
ecce5c3c
PM		 653static int vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
654 uint64_t value)
655{
656 value &= 7;
657 env->cp15.c2_control = value;
658 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> value);
659 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> value);
660 return 0;
661}
662
663static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
664{
665 env->cp15.c2_base_mask = 0xffffc000u;
666 env->cp15.c2_control = 0;
667 env->cp15.c2_mask = 0;
668}
669
18032bec
PM		 670static const ARMCPRegInfo vmsa_cp_reginfo[] = {
671 { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
672 .access = PL1_RW,
673 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
674 { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
675 .access = PL1_RW,
676 .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, },
ecce5c3c
PM		 677 { .name = "TTBR0", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
678 .access = PL1_RW,
679 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
680 { .name = "TTBR1", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
681 .access = PL1_RW,
682 .fieldoffset = offsetof(CPUARMState, cp15.c2_base0), .resetvalue = 0, },
683 { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
684 .access = PL1_RW, .writefn = vmsa_ttbcr_write,
685 .resetfn = vmsa_ttbcr_reset,
686 .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
06d76f31
PM		 687 { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
688 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c6_data),
689 .resetvalue = 0, },
18032bec
PM		 690 REGINFO_SENTINEL
691};
692
1047b9d7
PM		 693static int omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
694 uint64_t value)
695{
696 env->cp15.c15_ticonfig = value & 0xe7;
697 /* The OS_TYPE bit in this register changes the reported CPUID! */
698 env->cp15.c0_cpuid = (value & (1 << 5)) ?
699 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
700 return 0;
701}
702
703static int omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
704 uint64_t value)
705{
706 env->cp15.c15_threadid = value & 0xffff;
707 return 0;
708}
709
710static int omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
711 uint64_t value)
712{
713 /* Wait-for-interrupt (deprecated) */
714 cpu_interrupt(env, CPU_INTERRUPT_HALT);
715 return 0;
716}
717
c4804214
PM		 718static int omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
719 uint64_t value)
720{
721 /* On OMAP there are registers indicating the max/min index of dcache lines
722 * containing a dirty line; cache flush operations have to reset these.
723 */
724 env->cp15.c15_i_max = 0x000;
725 env->cp15.c15_i_min = 0xff0;
726 return 0;
727}
728
18032bec
PM		 729static const ARMCPRegInfo omap_cp_reginfo[] = {
730 { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
731 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
732 .fieldoffset = offsetof(CPUARMState, cp15.c5_data), .resetvalue = 0, },
1047b9d7
PM		 733 { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
734 .access = PL1_RW, .type = ARM_CP_NOP },
735 { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
736 .access = PL1_RW,
737 .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
738 .writefn = omap_ticonfig_write },
739 { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
740 .access = PL1_RW,
741 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
742 { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
743 .access = PL1_RW, .resetvalue = 0xff0,
744 .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
745 { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
746 .access = PL1_RW,
747 .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
748 .writefn = omap_threadid_write },
749 { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
750 .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
751 .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
752 /* TODO: Peripheral port remap register:
753 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
754 * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
755 * when MMU is off.
756 */
c4804214
PM		 757 { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
758 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_OVERRIDE,
759 .writefn = omap_cachemaint_write },
34f90529
PM		 760 { .name = "C9", .cp = 15, .crn = 9,
761 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
762 .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1047b9d7
PM		 763 REGINFO_SENTINEL
764};
765
766static int xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
767 uint64_t value)
768{
769 value &= 0x3fff;
770 if (env->cp15.c15_cpar != value) {
771 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
772 tb_flush(env);
773 env->cp15.c15_cpar = value;
774 }
775 return 0;
776}
777
778static const ARMCPRegInfo xscale_cp_reginfo[] = {
779 { .name = "XSCALE_CPAR",
780 .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
781 .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
782 .writefn = xscale_cpar_write, },
2771db27
PM		 783 { .name = "XSCALE_AUXCR",
784 .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
785 .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
786 .resetvalue = 0, },
1047b9d7
PM		 787 REGINFO_SENTINEL
788};
789
790static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
791 /* RAZ/WI the whole crn=15 space, when we don't have a more specific
792 * implementation of this implementation-defined space.
793 * Ideally this should eventually disappear in favour of actually
794 * implementing the correct behaviour for all cores.
795 */
796 { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
797 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
798 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
18032bec
PM		 799 REGINFO_SENTINEL
800};
801
c4804214
PM		 802static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
803 /* Cache status: RAZ because we have no cache so it's always clean */
804 { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
805 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
806 REGINFO_SENTINEL
807};
808
809static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
810 /* We never have a a block transfer operation in progress */
811 { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
812 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
813 REGINFO_SENTINEL
814};
815
816static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
817 /* The cache test-and-clean instructions always return (1 << 30)
818 * to indicate that there are no dirty cache lines.
819 */
820 { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
821 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
822 { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
823 .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = (1 << 30) },
824 REGINFO_SENTINEL
825};
826
34f90529
PM		 827static const ARMCPRegInfo strongarm_cp_reginfo[] = {
828 /* Ignore ReadBuffer accesses */
829 { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
830 .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
831 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
832 .resetvalue = 0 },
833 REGINFO_SENTINEL
834};
835
2771db27
PM		 836static int sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
837{
838 env->cp15.c1_sys = value;
839 /* ??? Lots of these bits are not implemented. */
840 /* This may enable/disable the MMU, so do a TLB flush. */
841 tlb_flush(env, 1);
842 return 0;
843}
844
2ceb98c0
PM		 845void register_cp_regs_for_features(ARMCPU *cpu)
846{
847 /* Register all the coprocessor registers based on feature bits */
848 CPUARMState *env = &cpu->env;
849 if (arm_feature(env, ARM_FEATURE_M)) {
850 /* M profile has no coprocessor registers */
851 return;
852 }
853
e9aa6c21 854 define_arm_cp_regs(cpu, cp_reginfo);
7d57f408 855 if (arm_feature(env, ARM_FEATURE_V6)) {
8515a092
PM		 856 /* The ID registers all have impdef reset values */
857 ARMCPRegInfo v6_idregs[] = {
858 { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
859 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
860 .resetvalue = cpu->id_pfr0 },
861 { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
862 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
863 .resetvalue = cpu->id_pfr1 },
864 { .name = "ID_DFR0", .cp = 15, .crn = 0, .crm = 1,
865 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
866 .resetvalue = cpu->id_dfr0 },
867 { .name = "ID_AFR0", .cp = 15, .crn = 0, .crm = 1,
868 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
869 .resetvalue = cpu->id_afr0 },
870 { .name = "ID_MMFR0", .cp = 15, .crn = 0, .crm = 1,
871 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
872 .resetvalue = cpu->id_mmfr0 },
873 { .name = "ID_MMFR1", .cp = 15, .crn = 0, .crm = 1,
874 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
875 .resetvalue = cpu->id_mmfr1 },
876 { .name = "ID_MMFR2", .cp = 15, .crn = 0, .crm = 1,
877 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
878 .resetvalue = cpu->id_mmfr2 },
879 { .name = "ID_MMFR3", .cp = 15, .crn = 0, .crm = 1,
880 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
881 .resetvalue = cpu->id_mmfr3 },
882 { .name = "ID_ISAR0", .cp = 15, .crn = 0, .crm = 2,
883 .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
884 .resetvalue = cpu->id_isar0 },
885 { .name = "ID_ISAR1", .cp = 15, .crn = 0, .crm = 2,
886 .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
887 .resetvalue = cpu->id_isar1 },
888 { .name = "ID_ISAR2", .cp = 15, .crn = 0, .crm = 2,
889 .opc1 = 0, .opc2 = 2, .access = PL1_R, .type = ARM_CP_CONST,
890 .resetvalue = cpu->id_isar2 },
891 { .name = "ID_ISAR3", .cp = 15, .crn = 0, .crm = 2,
892 .opc1 = 0, .opc2 = 3, .access = PL1_R, .type = ARM_CP_CONST,
893 .resetvalue = cpu->id_isar3 },
894 { .name = "ID_ISAR4", .cp = 15, .crn = 0, .crm = 2,
895 .opc1 = 0, .opc2 = 4, .access = PL1_R, .type = ARM_CP_CONST,
896 .resetvalue = cpu->id_isar4 },
897 { .name = "ID_ISAR5", .cp = 15, .crn = 0, .crm = 2,
898 .opc1 = 0, .opc2 = 5, .access = PL1_R, .type = ARM_CP_CONST,
899 .resetvalue = cpu->id_isar5 },
900 /* 6..7 are as yet unallocated and must RAZ */
901 { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
902 .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
903 .resetvalue = 0 },
904 { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
905 .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
906 .resetvalue = 0 },
907 REGINFO_SENTINEL
908 };
909 define_arm_cp_regs(cpu, v6_idregs);
7d57f408
PM		 910 define_arm_cp_regs(cpu, v6_cp_reginfo);
911 } else {
912 define_arm_cp_regs(cpu, not_v6_cp_reginfo);
913 }
4d31c596
PM		 914 if (arm_feature(env, ARM_FEATURE_V6K)) {
915 define_arm_cp_regs(cpu, v6k_cp_reginfo);
916 }
e9aa6c21 917 if (arm_feature(env, ARM_FEATURE_V7)) {
200ac0ef
PM		 918 /* v7 performance monitor control register: same implementor
919 * field as main ID register, and we implement no event counters.
920 */
921 ARMCPRegInfo pmcr = {
922 .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
923 .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
924 .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
925 .readfn = pmreg_read, .writefn = pmcr_write
926 };
776d4e5c
PM		 927 ARMCPRegInfo clidr = {
928 .name = "CLIDR", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
929 .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
930 };
200ac0ef 931 define_one_arm_cp_reg(cpu, &pmcr);
776d4e5c 932 define_one_arm_cp_reg(cpu, &clidr);
e9aa6c21 933 define_arm_cp_regs(cpu, v7_cp_reginfo);
7d57f408
PM		 934 } else {
935 define_arm_cp_regs(cpu, not_v7_cp_reginfo);
e9aa6c21 936 }
18032bec
PM		 937 if (arm_feature(env, ARM_FEATURE_MPU)) {
938 /* These are the MPU registers prior to PMSAv6. Any new
939 * PMSA core later than the ARM946 will require that we
940 * implement the PMSAv6 or PMSAv7 registers, which are
941 * completely different.
942 */
943 assert(!arm_feature(env, ARM_FEATURE_V6));
944 define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
945 } else {
946 define_arm_cp_regs(cpu, vmsa_cp_reginfo);
947 }
c326b979
PM		 948 if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
949 define_arm_cp_regs(cpu, t2ee_cp_reginfo);
950 }
6cc7a3ae
PM		 951 if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
952 define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
953 }
4a501606
PM		 954 if (arm_feature(env, ARM_FEATURE_VAPA)) {
955 define_arm_cp_regs(cpu, vapa_cp_reginfo);
956 }
c4804214
PM		 957 if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
958 define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
959 }
960 if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
961 define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
962 }
963 if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
964 define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
965 }
18032bec
PM		 966 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
967 define_arm_cp_regs(cpu, omap_cp_reginfo);
968 }
34f90529
PM		 969 if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
970 define_arm_cp_regs(cpu, strongarm_cp_reginfo);
971 }
1047b9d7
PM		 972 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
973 define_arm_cp_regs(cpu, xscale_cp_reginfo);
974 }
975 if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
976 define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
977 }
2771db27
PM		 978 if (arm_feature(env, ARM_FEATURE_AUXCR)) {
979 ARMCPRegInfo auxcr = {
980 .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
981 .access = PL1_RW, .type = ARM_CP_CONST,
982 .resetvalue = cpu->reset_auxcr
983 };
984 define_one_arm_cp_reg(cpu, &auxcr);
985 }
986
987 /* Generic registers whose values depend on the implementation */
988 {
989 ARMCPRegInfo sctlr = {
990 .name = "SCTLR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
991 .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
992 .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr
993 };
994 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
995 /* Normally we would always end the TB on an SCTLR write, but Linux
996 * arch/arm/mach-pxa/sleep.S expects two instructions following
997 * an MMU enable to execute from cache. Imitate this behaviour.
998 */
999 sctlr.type |= ARM_CP_SUPPRESS_TB_END;
1000 }
1001 define_one_arm_cp_reg(cpu, &sctlr);
1002 }
2ceb98c0
PM		 1003}
1004
778c3a06 1005ARMCPU *cpu_arm_init(const char *cpu_model)
40f137e1 1006{
dec9c2d4 1007 ARMCPU *cpu;
40f137e1 1008 CPUARMState *env;
b26eefb6 1009 static int inited = 0;
40f137e1 1010
777dc784 1011 if (!object_class_by_name(cpu_model)) {
aaed909a 1012 return NULL;
777dc784
PM		 1013 }
1014 cpu = ARM_CPU(object_new(cpu_model));
dec9c2d4 1015 env = &cpu->env;
777dc784 1016 env->cpu_model_str = cpu_model;
581be094 1017 arm_cpu_realize(cpu);
777dc784 1018
f4fc247b 1019 if (tcg_enabled() && !inited) {
b26eefb6
PB		 1020 inited = 1;
1021 arm_translate_init();
1022 }
1023
df90dadb 1024 cpu_reset(CPU(cpu));
56aebc89
PB		 1025 if (arm_feature(env, ARM_FEATURE_NEON)) {
1026 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1027 51, "arm-neon.xml", 0);
1028 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
1029 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1030 35, "arm-vfp3.xml", 0);
1031 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
1032 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
1033 19, "arm-vfp.xml", 0);
1034 }
0bf46a40 1035 qemu_init_vcpu(env);
778c3a06 1036 return cpu;
40f137e1
PB		 1037}
1038
777dc784
PM		 1039typedef struct ARMCPUListState {
1040 fprintf_function cpu_fprintf;
1041 FILE *file;
1042} ARMCPUListState;
3371d272 1043
777dc784
PM		 1044/* Sort alphabetically by type name, except for "any". */
1045static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
5adb4839 1046{
777dc784
PM		 1047 ObjectClass *class_a = (ObjectClass *)a;
1048 ObjectClass *class_b = (ObjectClass *)b;
1049 const char *name_a, *name_b;
5adb4839 1050
777dc784
PM		 1051 name_a = object_class_get_name(class_a);
1052 name_b = object_class_get_name(class_b);
1053 if (strcmp(name_a, "any") == 0) {
1054 return 1;
1055 } else if (strcmp(name_b, "any") == 0) {
1056 return -1;
1057 } else {
1058 return strcmp(name_a, name_b);
5adb4839
PB		 1059 }
1060}
1061
777dc784 1062static void arm_cpu_list_entry(gpointer data, gpointer user_data)
40f137e1 1063{
777dc784
PM		 1064 ObjectClass *oc = data;
1065 ARMCPUListState *s = user_data;
3371d272 1066
777dc784
PM		 1067 (*s->cpu_fprintf)(s->file, " %s\n",
1068 object_class_get_name(oc));
1069}
1070
1071void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1072{
1073 ARMCPUListState s = {
1074 .file = f,
1075 .cpu_fprintf = cpu_fprintf,
1076 };
1077 GSList *list;
1078
1079 list = object_class_get_list(TYPE_ARM_CPU, false);
1080 list = g_slist_sort(list, arm_cpu_list_compare);
1081 (*cpu_fprintf)(f, "Available CPUs:\n");
1082 g_slist_foreach(list, arm_cpu_list_entry, &s);
1083 g_slist_free(list);
40f137e1
PB		 1084}
1085
4b6a83fb
PM		 1086void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
1087 const ARMCPRegInfo *r, void *opaque)
1088{
1089 /* Define implementations of coprocessor registers.
1090 * We store these in a hashtable because typically
1091 * there are less than 150 registers in a space which
1092 * is 16*16*16*8*8 = 262144 in size.
1093 * Wildcarding is supported for the crm, opc1 and opc2 fields.
1094 * If a register is defined twice then the second definition is
1095 * used, so this can be used to define some generic registers and
1096 * then override them with implementation specific variations.
1097 * At least one of the original and the second definition should
1098 * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
1099 * against accidental use.
1100 */
1101 int crm, opc1, opc2;
1102 int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
1103 int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
1104 int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
1105 int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
1106 int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
1107 int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
1108 /* 64 bit registers have only CRm and Opc1 fields */
1109 assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
1110 /* Check that the register definition has enough info to handle
1111 * reads and writes if they are permitted.
1112 */
1113 if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
1114 if (r->access & PL3_R) {
1115 assert(r->fieldoffset || r->readfn);
1116 }
1117 if (r->access & PL3_W) {
1118 assert(r->fieldoffset || r->writefn);
1119 }
1120 }
1121 /* Bad type field probably means missing sentinel at end of reg list */
1122 assert(cptype_valid(r->type));
1123 for (crm = crmmin; crm <= crmmax; crm++) {
1124 for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
1125 for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
1126 uint32_t *key = g_new(uint32_t, 1);
1127 ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
1128 int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
1129 *key = ENCODE_CP_REG(r->cp, is64, r->crn, crm, opc1, opc2);
1130 r2->opaque = opaque;
1131 /* Make sure reginfo passed to helpers for wildcarded regs
1132 * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
1133 */
1134 r2->crm = crm;
1135 r2->opc1 = opc1;
1136 r2->opc2 = opc2;
1137 /* Overriding of an existing definition must be explicitly
1138 * requested.
1139 */
1140 if (!(r->type & ARM_CP_OVERRIDE)) {
1141 ARMCPRegInfo *oldreg;
1142 oldreg = g_hash_table_lookup(cpu->cp_regs, key);
1143 if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
1144 fprintf(stderr, "Register redefined: cp=%d %d bit "
1145 "crn=%d crm=%d opc1=%d opc2=%d, "
1146 "was %s, now %s\n", r2->cp, 32 + 32 * is64,
1147 r2->crn, r2->crm, r2->opc1, r2->opc2,
1148 oldreg->name, r2->name);
1149 assert(0);
1150 }
1151 }
1152 g_hash_table_insert(cpu->cp_regs, key, r2);
1153 }
1154 }
1155 }
1156}
1157
1158void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
1159 const ARMCPRegInfo *regs, void *opaque)
1160{
1161 /* Define a whole list of registers */
1162 const ARMCPRegInfo *r;
1163 for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
1164 define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
1165 }
1166}
1167
1168const ARMCPRegInfo *get_arm_cp_reginfo(ARMCPU *cpu, uint32_t encoded_cp)
1169{
1170 return g_hash_table_lookup(cpu->cp_regs, &encoded_cp);
1171}
1172
1173int arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
1174 uint64_t value)
1175{
1176 /* Helper coprocessor write function for write-ignore registers */
1177 return 0;
1178}
1179
1180int arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value)
1181{
1182 /* Helper coprocessor write function for read-as-zero registers */
1183 *value = 0;
1184 return 0;
1185}
1186
0ecb72a5 1187static int bad_mode_switch(CPUARMState *env, int mode)
37064a8b
PM		 1188{
1189 /* Return true if it is not valid for us to switch to
1190 * this CPU mode (ie all the UNPREDICTABLE cases in
1191 * the ARM ARM CPSRWriteByInstr pseudocode).
1192 */
1193 switch (mode) {
1194 case ARM_CPU_MODE_USR:
1195 case ARM_CPU_MODE_SYS:
1196 case ARM_CPU_MODE_SVC:
1197 case ARM_CPU_MODE_ABT:
1198 case ARM_CPU_MODE_UND:
1199 case ARM_CPU_MODE_IRQ:
1200 case ARM_CPU_MODE_FIQ:
1201 return 0;
1202 default:
1203 return 1;
1204 }
1205}
1206
2f4a40e5
AZ		 1207uint32_t cpsr_read(CPUARMState *env)
1208{
1209 int ZF;
6fbe23d5
PB		 1210 ZF = (env->ZF == 0);
1211 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 1212 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
1213 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
1214 | ((env->condexec_bits & 0xfc) << 8)
1215 | (env->GE << 16);
1216}
1217
1218void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
1219{
2f4a40e5 1220 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 1221 env->ZF = (~val) & CPSR_Z;
1222 env->NF = val;
2f4a40e5
AZ		 1223 env->CF = (val >> 29) & 1;
1224 env->VF = (val << 3) & 0x80000000;
1225 }
1226 if (mask & CPSR_Q)
1227 env->QF = ((val & CPSR_Q) != 0);
1228 if (mask & CPSR_T)
1229 env->thumb = ((val & CPSR_T) != 0);
1230 if (mask & CPSR_IT_0_1) {
1231 env->condexec_bits &= ~3;
1232 env->condexec_bits |= (val >> 25) & 3;
1233 }
1234 if (mask & CPSR_IT_2_7) {
1235 env->condexec_bits &= 3;
1236 env->condexec_bits |= (val >> 8) & 0xfc;
1237 }
1238 if (mask & CPSR_GE) {
1239 env->GE = (val >> 16) & 0xf;
1240 }
1241
1242 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
37064a8b
PM		 1243 if (bad_mode_switch(env, val & CPSR_M)) {
1244 /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
1245 * We choose to ignore the attempt and leave the CPSR M field
1246 * untouched.
1247 */
1248 mask &= ~CPSR_M;
1249 } else {
1250 switch_mode(env, val & CPSR_M);
1251 }
2f4a40e5
AZ		 1252 }
1253 mask &= ~CACHED_CPSR_BITS;
1254 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
1255}
1256
b26eefb6
PB		 1257/* Sign/zero extend */
1258uint32_t HELPER(sxtb16)(uint32_t x)
1259{
1260 uint32_t res;
1261 res = (uint16_t)(int8_t)x;
1262 res |= (uint32_t)(int8_t)(x >> 16) << 16;
1263 return res;
1264}
1265
1266uint32_t HELPER(uxtb16)(uint32_t x)
1267{
1268 uint32_t res;
1269 res = (uint16_t)(uint8_t)x;
1270 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
1271 return res;
1272}
1273
f51bbbfe
PB		 1274uint32_t HELPER(clz)(uint32_t x)
1275{
7bbcb0af 1276 return clz32(x);
f51bbbfe
PB		 1277}
1278
3670669c
PB		 1279int32_t HELPER(sdiv)(int32_t num, int32_t den)
1280{
1281 if (den == 0)
1282 return 0;
686eeb93
AJ		 1283 if (num == INT_MIN && den == -1)
1284 return INT_MIN;
3670669c
PB		 1285 return num / den;
1286}
1287
1288uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
1289{
1290 if (den == 0)
1291 return 0;
1292 return num / den;
1293}
1294
1295uint32_t HELPER(rbit)(uint32_t x)
1296{
1297 x = ((x & 0xff000000) >> 24)
1298 | ((x & 0x00ff0000) >> 8)
1299 | ((x & 0x0000ff00) << 8)
1300 | ((x & 0x000000ff) << 24);
1301 x = ((x & 0xf0f0f0f0) >> 4)
1302 | ((x & 0x0f0f0f0f) << 4);
1303 x = ((x & 0x88888888) >> 3)
1304 | ((x & 0x44444444) >> 1)
1305 | ((x & 0x22222222) << 1)
1306 | ((x & 0x11111111) << 3);
1307 return x;
1308}
1309
ad69471c
PB		 1310uint32_t HELPER(abs)(uint32_t x)
1311{
1312 return ((int32_t)x < 0) ? -x : x;
1313}
1314
5fafdf24 1315#if defined(CONFIG_USER_ONLY)
b5ff1b31 1316
0ecb72a5 1317void do_interrupt (CPUARMState *env)
b5ff1b31
FB		 1318{
1319 env->exception_index = -1;
1320}
1321
0ecb72a5 1322int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
97b348e7 1323 int mmu_idx)
b5ff1b31
FB		 1324{
1325 if (rw == 2) {
1326 env->exception_index = EXCP_PREFETCH_ABORT;
1327 env->cp15.c6_insn = address;
1328 } else {
1329 env->exception_index = EXCP_DATA_ABORT;
1330 env->cp15.c6_data = address;
1331 }
1332 return 1;
1333}
1334
0ecb72a5 1335void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 1336{
1337 cpu_abort(env, "cp15 insn %08x\n", insn);
1338}
1339
0ecb72a5 1340uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31
FB		 1341{
1342 cpu_abort(env, "cp15 insn %08x\n", insn);
b5ff1b31
FB		 1343}
1344
9ee6e8bb 1345/* These should probably raise undefined insn exceptions. */
0ecb72a5 1346void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1347{
1348 cpu_abort(env, "v7m_mrs %d\n", reg);
1349}
1350
0ecb72a5 1351uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 1352{
1353 cpu_abort(env, "v7m_mrs %d\n", reg);
1354 return 0;
1355}
1356
0ecb72a5 1357void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1358{
1359 if (mode != ARM_CPU_MODE_USR)
1360 cpu_abort(env, "Tried to switch out of user mode\n");
1361}
1362
0ecb72a5 1363void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1364{
1365 cpu_abort(env, "banked r13 write\n");
1366}
1367
0ecb72a5 1368uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb
PB		 1369{
1370 cpu_abort(env, "banked r13 read\n");
1371 return 0;
1372}
1373
b5ff1b31
FB		 1374#else
1375
1376/* Map CPU modes onto saved register banks. */
0ecb72a5 1377static inline int bank_number(CPUARMState *env, int mode)
b5ff1b31
FB		 1378{
1379 switch (mode) {
1380 case ARM_CPU_MODE_USR:
1381 case ARM_CPU_MODE_SYS:
1382 return 0;
1383 case ARM_CPU_MODE_SVC:
1384 return 1;
1385 case ARM_CPU_MODE_ABT:
1386 return 2;
1387 case ARM_CPU_MODE_UND:
1388 return 3;
1389 case ARM_CPU_MODE_IRQ:
1390 return 4;
1391 case ARM_CPU_MODE_FIQ:
1392 return 5;
1393 }
1b9e01c1 1394 cpu_abort(env, "Bad mode %x\n", mode);
b5ff1b31
FB		 1395 return -1;
1396}
1397
0ecb72a5 1398void switch_mode(CPUARMState *env, int mode)
b5ff1b31
FB		 1399{
1400 int old_mode;
1401 int i;
1402
1403 old_mode = env->uncached_cpsr & CPSR_M;
1404 if (mode == old_mode)
1405 return;
1406
1407 if (old_mode == ARM_CPU_MODE_FIQ) {
1408 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1409 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1410 } else if (mode == ARM_CPU_MODE_FIQ) {
1411 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 1412 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 1413 }
1414
1b9e01c1 1415 i = bank_number(env, old_mode);
b5ff1b31
FB		 1416 env->banked_r13[i] = env->regs[13];
1417 env->banked_r14[i] = env->regs[14];
1418 env->banked_spsr[i] = env->spsr;
1419
1b9e01c1 1420 i = bank_number(env, mode);
b5ff1b31
FB		 1421 env->regs[13] = env->banked_r13[i];
1422 env->regs[14] = env->banked_r14[i];
1423 env->spsr = env->banked_spsr[i];
1424}
1425
9ee6e8bb
PB		 1426static void v7m_push(CPUARMState *env, uint32_t val)
1427{
1428 env->regs[13] -= 4;
1429 stl_phys(env->regs[13], val);
1430}
1431
1432static uint32_t v7m_pop(CPUARMState *env)
1433{
1434 uint32_t val;
1435 val = ldl_phys(env->regs[13]);
1436 env->regs[13] += 4;
1437 return val;
1438}
1439
1440/* Switch to V7M main or process stack pointer. */
1441static void switch_v7m_sp(CPUARMState *env, int process)
1442{
1443 uint32_t tmp;
1444 if (env->v7m.current_sp != process) {
1445 tmp = env->v7m.other_sp;
1446 env->v7m.other_sp = env->regs[13];
1447 env->regs[13] = tmp;
1448 env->v7m.current_sp = process;
1449 }
1450}
1451
1452static void do_v7m_exception_exit(CPUARMState *env)
1453{
1454 uint32_t type;
1455 uint32_t xpsr;
1456
1457 type = env->regs[15];
1458 if (env->v7m.exception != 0)
983fe826 1459 armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
9ee6e8bb
PB		 1460
1461 /* Switch to the target stack. */
1462 switch_v7m_sp(env, (type & 4) != 0);
1463 /* Pop registers. */
1464 env->regs[0] = v7m_pop(env);
1465 env->regs[1] = v7m_pop(env);
1466 env->regs[2] = v7m_pop(env);
1467 env->regs[3] = v7m_pop(env);
1468 env->regs[12] = v7m_pop(env);
1469 env->regs[14] = v7m_pop(env);
1470 env->regs[15] = v7m_pop(env);
1471 xpsr = v7m_pop(env);
1472 xpsr_write(env, xpsr, 0xfffffdff);
1473 /* Undo stack alignment. */
1474 if (xpsr & 0x200)
1475 env->regs[13] |= 4;
1476 /* ??? The exception return type specifies Thread/Handler mode. However
1477 this is also implied by the xPSR value. Not sure what to do
1478 if there is a mismatch. */
1479 /* ??? Likewise for mismatches between the CONTROL register and the stack
1480 pointer. */
1481}
1482
2b3ea315 1483static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 1484{
1485 uint32_t xpsr = xpsr_read(env);
1486 uint32_t lr;
1487 uint32_t addr;
1488
1489 lr = 0xfffffff1;
1490 if (env->v7m.current_sp)
1491 lr |= 4;
1492 if (env->v7m.exception == 0)
1493 lr |= 8;
1494
1495 /* For exceptions we just mark as pending on the NVIC, and let that
1496 handle it. */
1497 /* TODO: Need to escalate if the current priority is higher than the
1498 one we're raising. */
1499 switch (env->exception_index) {
1500 case EXCP_UDEF:
983fe826 1501 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
9ee6e8bb
PB		 1502 return;
1503 case EXCP_SWI:
1504 env->regs[15] += 2;
983fe826 1505 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
9ee6e8bb
PB		 1506 return;
1507 case EXCP_PREFETCH_ABORT:
1508 case EXCP_DATA_ABORT:
983fe826 1509 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
9ee6e8bb
PB		 1510 return;
1511 case EXCP_BKPT:
2ad207d4
PB		 1512 if (semihosting_enabled) {
1513 int nr;
d8fd2954 1514 nr = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
2ad207d4
PB		 1515 if (nr == 0xab) {
1516 env->regs[15] += 2;
1517 env->regs[0] = do_arm_semihosting(env);
1518 return;
1519 }
1520 }
983fe826 1521 armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
9ee6e8bb
PB		 1522 return;
1523 case EXCP_IRQ:
983fe826 1524 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
9ee6e8bb
PB		 1525 break;
1526 case EXCP_EXCEPTION_EXIT:
1527 do_v7m_exception_exit(env);
1528 return;
1529 default:
1530 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1531 return; /* Never happens. Keep compiler happy. */
1532 }
1533
1534 /* Align stack pointer. */
1535 /* ??? Should only do this if Configuration Control Register
1536 STACKALIGN bit is set. */
1537 if (env->regs[13] & 4) {
ab19b0ec 1538 env->regs[13] -= 4;
9ee6e8bb
PB		 1539 xpsr |= 0x200;
1540 }
6c95676b 1541 /* Switch to the handler mode. */
9ee6e8bb
PB		 1542 v7m_push(env, xpsr);
1543 v7m_push(env, env->regs[15]);
1544 v7m_push(env, env->regs[14]);
1545 v7m_push(env, env->regs[12]);
1546 v7m_push(env, env->regs[3]);
1547 v7m_push(env, env->regs[2]);
1548 v7m_push(env, env->regs[1]);
1549 v7m_push(env, env->regs[0]);
1550 switch_v7m_sp(env, 0);
c98d174c
PM		 1551 /* Clear IT bits */
1552 env->condexec_bits = 0;
9ee6e8bb
PB		 1553 env->regs[14] = lr;
1554 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
1555 env->regs[15] = addr & 0xfffffffe;
1556 env->thumb = addr & 1;
1557}
1558
b5ff1b31
FB		 1559/* Handle a CPU exception. */
1560void do_interrupt(CPUARMState *env)
1561{
1562 uint32_t addr;
1563 uint32_t mask;
1564 int new_mode;
1565 uint32_t offset;
1566
9ee6e8bb
PB		 1567 if (IS_M(env)) {
1568 do_interrupt_v7m(env);
1569 return;
1570 }
b5ff1b31
FB		 1571 /* TODO: Vectored interrupt controller. */
1572 switch (env->exception_index) {
1573 case EXCP_UDEF:
1574 new_mode = ARM_CPU_MODE_UND;
1575 addr = 0x04;
1576 mask = CPSR_I;
1577 if (env->thumb)
1578 offset = 2;
1579 else
1580 offset = 4;
1581 break;
1582 case EXCP_SWI:
8e71621f
PB		 1583 if (semihosting_enabled) {
1584 /* Check for semihosting interrupt. */
1585 if (env->thumb) {
d8fd2954 1586 mask = arm_lduw_code(env->regs[15] - 2, env->bswap_code) & 0xff;
8e71621f 1587 } else {
d8fd2954
PB		 1588 mask = arm_ldl_code(env->regs[15] - 4, env->bswap_code)
1589 & 0xffffff;
8e71621f
PB		 1590 }
1591 /* Only intercept calls from privileged modes, to provide some
1592 semblance of security. */
1593 if (((mask == 0x123456 && !env->thumb)
1594 || (mask == 0xab && env->thumb))
1595 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1596 env->regs[0] = do_arm_semihosting(env);
1597 return;
1598 }
1599 }
b5ff1b31
FB		 1600 new_mode = ARM_CPU_MODE_SVC;
1601 addr = 0x08;
1602 mask = CPSR_I;
601d70b9 1603 /* The PC already points to the next instruction. */
b5ff1b31
FB		 1604 offset = 0;
1605 break;
06c949e6 1606 case EXCP_BKPT:
9ee6e8bb 1607 /* See if this is a semihosting syscall. */
2ad207d4 1608 if (env->thumb && semihosting_enabled) {
d8fd2954 1609 mask = arm_lduw_code(env->regs[15], env->bswap_code) & 0xff;
9ee6e8bb
PB		 1610 if (mask == 0xab
1611 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
1612 env->regs[15] += 2;
1613 env->regs[0] = do_arm_semihosting(env);
1614 return;
1615 }
1616 }
81c05daf 1617 env->cp15.c5_insn = 2;
9ee6e8bb
PB		 1618 /* Fall through to prefetch abort. */
1619 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 1620 new_mode = ARM_CPU_MODE_ABT;
1621 addr = 0x0c;
1622 mask = CPSR_A | CPSR_I;
1623 offset = 4;
1624 break;
1625 case EXCP_DATA_ABORT:
1626 new_mode = ARM_CPU_MODE_ABT;
1627 addr = 0x10;
1628 mask = CPSR_A | CPSR_I;
1629 offset = 8;
1630 break;
1631 case EXCP_IRQ:
1632 new_mode = ARM_CPU_MODE_IRQ;
1633 addr = 0x18;
1634 /* Disable IRQ and imprecise data aborts. */
1635 mask = CPSR_A | CPSR_I;
1636 offset = 4;
1637 break;
1638 case EXCP_FIQ:
1639 new_mode = ARM_CPU_MODE_FIQ;
1640 addr = 0x1c;
1641 /* Disable FIQ, IRQ and imprecise data aborts. */
1642 mask = CPSR_A | CPSR_I | CPSR_F;
1643 offset = 4;
1644 break;
1645 default:
1646 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
1647 return; /* Never happens. Keep compiler happy. */
1648 }
1649 /* High vectors. */
1650 if (env->cp15.c1_sys & (1 << 13)) {
1651 addr += 0xffff0000;
1652 }
1653 switch_mode (env, new_mode);
1654 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 1655 /* Clear IT bits. */
1656 env->condexec_bits = 0;
30a8cac1 1657 /* Switch to the new mode, and to the correct instruction set. */
6d7e6326 1658 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 1659 env->uncached_cpsr |= mask;
be5e7a76
DES		 1660 /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
1661 * and we should just guard the thumb mode on V4 */
1662 if (arm_feature(env, ARM_FEATURE_V4T)) {
1663 env->thumb = (env->cp15.c1_sys & (1 << 30)) != 0;
1664 }
b5ff1b31
FB		 1665 env->regs[14] = env->regs[15] + offset;
1666 env->regs[15] = addr;
1667 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
1668}
1669
1670/* Check section/page access permissions.
1671 Returns the page protection flags, or zero if the access is not
1672 permitted. */
0ecb72a5 1673static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
dd4ebc2e 1674 int access_type, int is_user)
b5ff1b31 1675{
9ee6e8bb
PB		 1676 int prot_ro;
1677
dd4ebc2e 1678 if (domain_prot == 3) {
b5ff1b31 1679 return PAGE_READ | PAGE_WRITE;
dd4ebc2e 1680 }
b5ff1b31 1681
9ee6e8bb
PB		 1682 if (access_type == 1)
1683 prot_ro = 0;
1684 else
1685 prot_ro = PAGE_READ;
1686
b5ff1b31
FB		 1687 switch (ap) {
1688 case 0:
78600320 1689 if (access_type == 1)
b5ff1b31
FB		 1690 return 0;
1691 switch ((env->cp15.c1_sys >> 8) & 3) {
1692 case 1:
1693 return is_user ? 0 : PAGE_READ;
1694 case 2:
1695 return PAGE_READ;
1696 default:
1697 return 0;
1698 }
1699 case 1:
1700 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
1701 case 2:
1702 if (is_user)
9ee6e8bb 1703 return prot_ro;
b5ff1b31
FB		 1704 else
1705 return PAGE_READ | PAGE_WRITE;
1706 case 3:
1707 return PAGE_READ | PAGE_WRITE;
d4934d18 1708 case 4: /* Reserved. */
9ee6e8bb
PB		 1709 return 0;
1710 case 5:
1711 return is_user ? 0 : prot_ro;
1712 case 6:
1713 return prot_ro;
d4934d18 1714 case 7:
0ab06d83 1715 if (!arm_feature (env, ARM_FEATURE_V6K))
d4934d18
PB		 1716 return 0;
1717 return prot_ro;
b5ff1b31
FB		 1718 default:
1719 abort();
1720 }
1721}
1722
0ecb72a5 1723static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
b2fa1797
PB		 1724{
1725 uint32_t table;
1726
1727 if (address & env->cp15.c2_mask)
1728 table = env->cp15.c2_base1 & 0xffffc000;
1729 else
1730 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
1731
1732 table |= (address >> 18) & 0x3ffc;
1733 return table;
1734}
1735
0ecb72a5 1736static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1737 int is_user, uint32_t *phys_ptr, int *prot,
1738 target_ulong *page_size)
b5ff1b31
FB		 1739{
1740 int code;
1741 uint32_t table;
1742 uint32_t desc;
1743 int type;
1744 int ap;
1745 int domain;
dd4ebc2e 1746 int domain_prot;
b5ff1b31
FB		 1747 uint32_t phys_addr;
1748
9ee6e8bb
PB		 1749 /* Pagetable walk. */
1750 /* Lookup l1 descriptor. */
b2fa1797 1751 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1752 desc = ldl_phys(table);
1753 type = (desc & 3);
dd4ebc2e
JCD		 1754 domain = (desc >> 5) & 0x0f;
1755 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
9ee6e8bb 1756 if (type == 0) {
601d70b9 1757 /* Section translation fault. */
9ee6e8bb
PB		 1758 code = 5;
1759 goto do_fault;
1760 }
dd4ebc2e 1761 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1762 if (type == 2)
1763 code = 9; /* Section domain fault. */
1764 else
1765 code = 11; /* Page domain fault. */
1766 goto do_fault;
1767 }
1768 if (type == 2) {
1769 /* 1Mb section. */
1770 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
1771 ap = (desc >> 10) & 3;
1772 code = 13;
d4c430a8 1773 *page_size = 1024 * 1024;
9ee6e8bb
PB		 1774 } else {
1775 /* Lookup l2 entry. */
1776 if (type == 1) {
1777 /* Coarse pagetable. */
1778 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1779 } else {
1780 /* Fine pagetable. */
1781 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
1782 }
1783 desc = ldl_phys(table);
1784 switch (desc & 3) {
1785 case 0: /* Page translation fault. */
1786 code = 7;
1787 goto do_fault;
1788 case 1: /* 64k page. */
1789 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1790 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1791 *page_size = 0x10000;
ce819861 1792 break;
9ee6e8bb
PB		 1793 case 2: /* 4k page. */
1794 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1795 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
d4c430a8 1796 *page_size = 0x1000;
ce819861 1797 break;
9ee6e8bb
PB		 1798 case 3: /* 1k page. */
1799 if (type == 1) {
1800 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1801 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1802 } else {
1803 /* Page translation fault. */
1804 code = 7;
1805 goto do_fault;
1806 }
1807 } else {
1808 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1809 }
1810 ap = (desc >> 4) & 3;
d4c430a8 1811 *page_size = 0x400;
ce819861
PB		 1812 break;
1813 default:
9ee6e8bb
PB		 1814 /* Never happens, but compiler isn't smart enough to tell. */
1815 abort();
ce819861 1816 }
9ee6e8bb
PB		 1817 code = 15;
1818 }
dd4ebc2e 1819 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
9ee6e8bb
PB		 1820 if (!*prot) {
1821 /* Access permission fault. */
1822 goto do_fault;
1823 }
3ad493fc 1824 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1825 *phys_ptr = phys_addr;
1826 return 0;
1827do_fault:
1828 return code | (domain << 4);
1829}
1830
0ecb72a5 1831static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
d4c430a8
PB		 1832 int is_user, uint32_t *phys_ptr, int *prot,
1833 target_ulong *page_size)
9ee6e8bb
PB		 1834{
1835 int code;
1836 uint32_t table;
1837 uint32_t desc;
1838 uint32_t xn;
1839 int type;
1840 int ap;
1841 int domain;
dd4ebc2e 1842 int domain_prot;
9ee6e8bb
PB		 1843 uint32_t phys_addr;
1844
1845 /* Pagetable walk. */
1846 /* Lookup l1 descriptor. */
b2fa1797 1847 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1848 desc = ldl_phys(table);
1849 type = (desc & 3);
1850 if (type == 0) {
601d70b9 1851 /* Section translation fault. */
9ee6e8bb
PB		 1852 code = 5;
1853 domain = 0;
1854 goto do_fault;
1855 } else if (type == 2 && (desc & (1 << 18))) {
1856 /* Supersection. */
1857 domain = 0;
b5ff1b31 1858 } else {
9ee6e8bb 1859 /* Section or page. */
dd4ebc2e 1860 domain = (desc >> 5) & 0x0f;
9ee6e8bb 1861 }
dd4ebc2e
JCD		 1862 domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
1863 if (domain_prot == 0 || domain_prot == 2) {
9ee6e8bb
PB		 1864 if (type == 2)
1865 code = 9; /* Section domain fault. */
1866 else
1867 code = 11; /* Page domain fault. */
1868 goto do_fault;
1869 }
1870 if (type == 2) {
1871 if (desc & (1 << 18)) {
1872 /* Supersection. */
1873 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
d4c430a8 1874 *page_size = 0x1000000;
b5ff1b31 1875 } else {
9ee6e8bb
PB		 1876 /* Section. */
1877 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
d4c430a8 1878 *page_size = 0x100000;
b5ff1b31 1879 }
9ee6e8bb
PB		 1880 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1881 xn = desc & (1 << 4);
1882 code = 13;
1883 } else {
1884 /* Lookup l2 entry. */
1885 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1886 desc = ldl_phys(table);
1887 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1888 switch (desc & 3) {
1889 case 0: /* Page translation fault. */
1890 code = 7;
b5ff1b31 1891 goto do_fault;
9ee6e8bb
PB		 1892 case 1: /* 64k page. */
1893 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1894 xn = desc & (1 << 15);
d4c430a8 1895 *page_size = 0x10000;
9ee6e8bb
PB		 1896 break;
1897 case 2: case 3: /* 4k page. */
1898 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1899 xn = desc & 1;
d4c430a8 1900 *page_size = 0x1000;
9ee6e8bb
PB		 1901 break;
1902 default:
1903 /* Never happens, but compiler isn't smart enough to tell. */
1904 abort();
b5ff1b31 1905 }
9ee6e8bb
PB		 1906 code = 15;
1907 }
dd4ebc2e 1908 if (domain_prot == 3) {
c0034328
JR		 1909 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
1910 } else {
1911 if (xn && access_type == 2)
1912 goto do_fault;
9ee6e8bb 1913
c0034328
JR		 1914 /* The simplified model uses AP[0] as an access control bit. */
1915 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1916 /* Access flag fault. */
1917 code = (code == 15) ? 6 : 3;
1918 goto do_fault;
1919 }
dd4ebc2e 1920 *prot = check_ap(env, ap, domain_prot, access_type, is_user);
c0034328
JR		 1921 if (!*prot) {
1922 /* Access permission fault. */
1923 goto do_fault;
1924 }
1925 if (!xn) {
1926 *prot |= PAGE_EXEC;
1927 }
3ad493fc 1928 }
9ee6e8bb 1929 *phys_ptr = phys_addr;
b5ff1b31
FB		 1930 return 0;
1931do_fault:
1932 return code | (domain << 4);
1933}
1934
0ecb72a5 1935static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type,
9ee6e8bb
PB		 1936 int is_user, uint32_t *phys_ptr, int *prot)
1937{
1938 int n;
1939 uint32_t mask;
1940 uint32_t base;
1941
1942 *phys_ptr = address;
1943 for (n = 7; n >= 0; n--) {
1944 base = env->cp15.c6_region[n];
1945 if ((base & 1) == 0)
1946 continue;
1947 mask = 1 << ((base >> 1) & 0x1f);
1948 /* Keep this shift separate from the above to avoid an
1949 (undefined) << 32. */
1950 mask = (mask << 1) - 1;
1951 if (((base ^ address) & ~mask) == 0)
1952 break;
1953 }
1954 if (n < 0)
1955 return 2;
1956
1957 if (access_type == 2) {
1958 mask = env->cp15.c5_insn;
1959 } else {
1960 mask = env->cp15.c5_data;
1961 }
1962 mask = (mask >> (n * 4)) & 0xf;
1963 switch (mask) {
1964 case 0:
1965 return 1;
1966 case 1:
1967 if (is_user)
1968 return 1;
1969 *prot = PAGE_READ | PAGE_WRITE;
1970 break;
1971 case 2:
1972 *prot = PAGE_READ;
1973 if (!is_user)
1974 *prot |= PAGE_WRITE;
1975 break;
1976 case 3:
1977 *prot = PAGE_READ | PAGE_WRITE;
1978 break;
1979 case 5:
1980 if (is_user)
1981 return 1;
1982 *prot = PAGE_READ;
1983 break;
1984 case 6:
1985 *prot = PAGE_READ;
1986 break;
1987 default:
1988 /* Bad permission. */
1989 return 1;
1990 }
3ad493fc 1991 *prot |= PAGE_EXEC;
9ee6e8bb
PB		 1992 return 0;
1993}
1994
0ecb72a5 1995static inline int get_phys_addr(CPUARMState *env, uint32_t address,
9ee6e8bb 1996 int access_type, int is_user,
d4c430a8
PB		 1997 uint32_t *phys_ptr, int *prot,
1998 target_ulong *page_size)
9ee6e8bb
PB		 1999{
2000 /* Fast Context Switch Extension. */
2001 if (address < 0x02000000)
2002 address += env->cp15.c13_fcse;
2003
2004 if ((env->cp15.c1_sys & 1) == 0) {
2005 /* MMU/MPU disabled. */
2006 *phys_ptr = address;
3ad493fc 2007 *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
d4c430a8 2008 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2009 return 0;
2010 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
d4c430a8 2011 *page_size = TARGET_PAGE_SIZE;
9ee6e8bb
PB		 2012 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
2013 prot);
2014 } else if (env->cp15.c1_sys & (1 << 23)) {
2015 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
d4c430a8 2016 prot, page_size);
9ee6e8bb
PB		 2017 } else {
2018 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
d4c430a8 2019 prot, page_size);
9ee6e8bb
PB		 2020 }
2021}
2022
0ecb72a5 2023int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
97b348e7 2024 int access_type, int mmu_idx)
b5ff1b31
FB		 2025{
2026 uint32_t phys_addr;
d4c430a8 2027 target_ulong page_size;
b5ff1b31 2028 int prot;
6ebbf390 2029 int ret, is_user;
b5ff1b31 2030
6ebbf390 2031 is_user = mmu_idx == MMU_USER_IDX;
d4c430a8
PB		 2032 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
2033 &page_size);
b5ff1b31
FB		 2034 if (ret == 0) {
2035 /* Map a single [sub]page. */
2036 phys_addr &= ~(uint32_t)0x3ff;
2037 address &= ~(uint32_t)0x3ff;
3ad493fc 2038 tlb_set_page (env, address, phys_addr, prot, mmu_idx, page_size);
d4c430a8 2039 return 0;
b5ff1b31
FB		 2040 }
2041
2042 if (access_type == 2) {
2043 env->cp15.c5_insn = ret;
2044 env->cp15.c6_insn = address;
2045 env->exception_index = EXCP_PREFETCH_ABORT;
2046 } else {
2047 env->cp15.c5_data = ret;
9ee6e8bb
PB		 2048 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
2049 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 2050 env->cp15.c6_data = address;
2051 env->exception_index = EXCP_DATA_ABORT;
2052 }
2053 return 1;
2054}
2055
0ecb72a5 2056target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
b5ff1b31
FB		 2057{
2058 uint32_t phys_addr;
d4c430a8 2059 target_ulong page_size;
b5ff1b31
FB		 2060 int prot;
2061 int ret;
2062
d4c430a8 2063 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot, &page_size);
b5ff1b31
FB		 2064
2065 if (ret != 0)
2066 return -1;
2067
2068 return phys_addr;
2069}
2070
0ecb72a5 2071void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
b5ff1b31 2072{
9ee6e8bb
PB		 2073 int op1;
2074 int op2;
2075 int crm;
b5ff1b31 2076
9ee6e8bb 2077 op1 = (insn >> 21) & 7;
b5ff1b31 2078 op2 = (insn >> 5) & 7;
ce819861 2079 crm = insn & 0xf;
b5ff1b31 2080 switch ((insn >> 16) & 0xf) {
9ee6e8bb 2081 case 0:
9ee6e8bb 2082 /* ID codes. */
610c3c8a
AZ		 2083 if (arm_feature(env, ARM_FEATURE_XSCALE))
2084 break;
c3d2689d
AZ		 2085 if (arm_feature(env, ARM_FEATURE_OMAPCP))
2086 break;
b5ff1b31 2087 goto bad_reg;
b5ff1b31
FB		 2088 case 4: /* Reserved. */
2089 goto bad_reg;
b5ff1b31
FB		 2090 case 12: /* Reserved. */
2091 goto bad_reg;
b5ff1b31
FB		 2092 }
2093 return;
2094bad_reg:
2095 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2096 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
2097 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2098}
2099
0ecb72a5 2100uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
b5ff1b31 2101{
9ee6e8bb
PB		 2102 int op1;
2103 int op2;
2104 int crm;
b5ff1b31 2105
9ee6e8bb 2106 op1 = (insn >> 21) & 7;
b5ff1b31 2107 op2 = (insn >> 5) & 7;
c3d2689d 2108 crm = insn & 0xf;
b5ff1b31
FB		 2109 switch ((insn >> 16) & 0xf) {
2110 case 0: /* ID codes. */
9ee6e8bb
PB		 2111 switch (op1) {
2112 case 0:
2113 switch (crm) {
2114 case 0:
2115 switch (op2) {
2116 case 0: /* Device ID. */
2117 return env->cp15.c0_cpuid;
2118 case 1: /* Cache Type. */
2119 return env->cp15.c0_cachetype;
2120 case 2: /* TCM status. */
2121 return 0;
2122 case 3: /* TLB type register. */
2123 return 0; /* No lockable TLB entries. */
607b4b08
PM		 2124 case 5: /* MPIDR */
2125 /* The MPIDR was standardised in v7; prior to
2126 * this it was implemented only in the 11MPCore.
2127 * For all other pre-v7 cores it does not exist.
2128 */
2129 if (arm_feature(env, ARM_FEATURE_V7) ||
2130 ARM_CPUID(env) == ARM_CPUID_ARM11MPCORE) {
2131 int mpidr = env->cpu_index;
2132 /* We don't support setting cluster ID ([8..11])
2133 * so these bits always RAZ.
2134 */
2135 if (arm_feature(env, ARM_FEATURE_V7MP)) {
2136 mpidr |= (1 << 31);
2137 /* Cores which are uniprocessor (non-coherent)
2138 * but still implement the MP extensions set
2139 * bit 30. (For instance, A9UP.) However we do
2140 * not currently model any of those cores.
2141 */
2142 }
2143 return mpidr;
10055562 2144 }
607b4b08 2145 /* otherwise fall through to the unimplemented-reg case */
9ee6e8bb
PB		 2146 default:
2147 goto bad_reg;
2148 }
9ee6e8bb
PB		 2149 case 3: case 4: case 5: case 6: case 7:
2150 return 0;
2151 default:
2152 goto bad_reg;
2153 }
9ee6e8bb
PB		 2154 default:
2155 goto bad_reg;
b5ff1b31 2156 }
b5ff1b31
FB		 2157 case 4: /* Reserved. */
2158 goto bad_reg;
b5ff1b31
FB		 2159 case 11: /* TCM DMA control. */
2160 case 12: /* Reserved. */
2161 goto bad_reg;
b5ff1b31
FB		 2162 }
2163bad_reg:
2164 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 2165 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
2166 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 2167 return 0;
2168}
2169
0ecb72a5 2170void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
9ee6e8bb 2171{
39ea3d4e
PM		 2172 if ((env->uncached_cpsr & CPSR_M) == mode) {
2173 env->regs[13] = val;
2174 } else {
1b9e01c1 2175 env->banked_r13[bank_number(env, mode)] = val;
39ea3d4e 2176 }
9ee6e8bb
PB		 2177}
2178
0ecb72a5 2179uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
9ee6e8bb 2180{
39ea3d4e
PM		 2181 if ((env->uncached_cpsr & CPSR_M) == mode) {
2182 return env->regs[13];
2183 } else {
1b9e01c1 2184 return env->banked_r13[bank_number(env, mode)];
39ea3d4e 2185 }
9ee6e8bb
PB		 2186}
2187
0ecb72a5 2188uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
9ee6e8bb
PB		 2189{
2190 switch (reg) {
2191 case 0: /* APSR */
2192 return xpsr_read(env) & 0xf8000000;
2193 case 1: /* IAPSR */
2194 return xpsr_read(env) & 0xf80001ff;
2195 case 2: /* EAPSR */
2196 return xpsr_read(env) & 0xff00fc00;
2197 case 3: /* xPSR */
2198 return xpsr_read(env) & 0xff00fdff;
2199 case 5: /* IPSR */
2200 return xpsr_read(env) & 0x000001ff;
2201 case 6: /* EPSR */
2202 return xpsr_read(env) & 0x0700fc00;
2203 case 7: /* IEPSR */
2204 return xpsr_read(env) & 0x0700edff;
2205 case 8: /* MSP */
2206 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
2207 case 9: /* PSP */
2208 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
2209 case 16: /* PRIMASK */
2210 return (env->uncached_cpsr & CPSR_I) != 0;
82845826
SH		 2211 case 17: /* BASEPRI */
2212 case 18: /* BASEPRI_MAX */
9ee6e8bb 2213 return env->v7m.basepri;
82845826
SH		 2214 case 19: /* FAULTMASK */
2215 return (env->uncached_cpsr & CPSR_F) != 0;
9ee6e8bb
PB		 2216 case 20: /* CONTROL */
2217 return env->v7m.control;
2218 default:
2219 /* ??? For debugging only. */
2220 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
2221 return 0;
2222 }
2223}
2224
0ecb72a5 2225void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 2226{
2227 switch (reg) {
2228 case 0: /* APSR */
2229 xpsr_write(env, val, 0xf8000000);
2230 break;
2231 case 1: /* IAPSR */
2232 xpsr_write(env, val, 0xf8000000);
2233 break;
2234 case 2: /* EAPSR */
2235 xpsr_write(env, val, 0xfe00fc00);
2236 break;
2237 case 3: /* xPSR */
2238 xpsr_write(env, val, 0xfe00fc00);
2239 break;
2240 case 5: /* IPSR */
2241 /* IPSR bits are readonly. */
2242 break;
2243 case 6: /* EPSR */
2244 xpsr_write(env, val, 0x0600fc00);
2245 break;
2246 case 7: /* IEPSR */
2247 xpsr_write(env, val, 0x0600fc00);
2248 break;
2249 case 8: /* MSP */
2250 if (env->v7m.current_sp)
2251 env->v7m.other_sp = val;
2252 else
2253 env->regs[13] = val;
2254 break;
2255 case 9: /* PSP */
2256 if (env->v7m.current_sp)
2257 env->regs[13] = val;
2258 else
2259 env->v7m.other_sp = val;
2260 break;
2261 case 16: /* PRIMASK */
2262 if (val & 1)
2263 env->uncached_cpsr |= CPSR_I;
2264 else
2265 env->uncached_cpsr &= ~CPSR_I;
2266 break;
82845826 2267 case 17: /* BASEPRI */
9ee6e8bb
PB		 2268 env->v7m.basepri = val & 0xff;
2269 break;
82845826 2270 case 18: /* BASEPRI_MAX */
9ee6e8bb
PB		 2271 val &= 0xff;
2272 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
2273 env->v7m.basepri = val;
2274 break;
82845826
SH		 2275 case 19: /* FAULTMASK */
2276 if (val & 1)
2277 env->uncached_cpsr |= CPSR_F;
2278 else
2279 env->uncached_cpsr &= ~CPSR_F;
2280 break;
9ee6e8bb
PB		 2281 case 20: /* CONTROL */
2282 env->v7m.control = val & 3;
2283 switch_v7m_sp(env, (val & 2) != 0);
2284 break;
2285 default:
2286 /* ??? For debugging only. */
2287 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
2288 return;
2289 }
2290}
2291
b5ff1b31 2292#endif
6ddbc6e4
PB		 2293
2294/* Note that signed overflow is undefined in C. The following routines are
2295 careful to use unsigned types where modulo arithmetic is required.
2296 Failure to do so _will_ break on newer gcc. */
2297
2298/* Signed saturating arithmetic. */
2299
1654b2d6 2300/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2301static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2302{
2303 uint16_t res;
2304
2305 res = a + b;
2306 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2307 if (a & 0x8000)
2308 res = 0x8000;
2309 else
2310 res = 0x7fff;
2311 }
2312 return res;
2313}
2314
1654b2d6 2315/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2316static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2317{
2318 uint8_t res;
2319
2320 res = a + b;
2321 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2322 if (a & 0x80)
2323 res = 0x80;
2324 else
2325 res = 0x7f;
2326 }
2327 return res;
2328}
2329
1654b2d6 2330/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2331static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2332{
2333 uint16_t res;
2334
2335 res = a - b;
2336 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2337 if (a & 0x8000)
2338 res = 0x8000;
2339 else
2340 res = 0x7fff;
2341 }
2342 return res;
2343}
2344
1654b2d6 2345/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2346static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2347{
2348 uint8_t res;
2349
2350 res = a - b;
2351 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2352 if (a & 0x80)
2353 res = 0x80;
2354 else
2355 res = 0x7f;
2356 }
2357 return res;
2358}
2359
2360#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2361#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2362#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2363#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2364#define PFX q
2365
2366#include "op_addsub.h"
2367
2368/* Unsigned saturating arithmetic. */
460a09c1 2369static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2370{
2371 uint16_t res;
2372 res = a + b;
2373 if (res < a)
2374 res = 0xffff;
2375 return res;
2376}
2377
460a09c1 2378static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4 2379{
4c4fd3f8 2380 if (a > b)
6ddbc6e4
PB		 2381 return a - b;
2382 else
2383 return 0;
2384}
2385
2386static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2387{
2388 uint8_t res;
2389 res = a + b;
2390 if (res < a)
2391 res = 0xff;
2392 return res;
2393}
2394
2395static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2396{
4c4fd3f8 2397 if (a > b)
6ddbc6e4
PB		 2398 return a - b;
2399 else
2400 return 0;
2401}
2402
2403#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2404#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2405#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2406#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2407#define PFX uq
2408
2409#include "op_addsub.h"
2410
2411/* Signed modulo arithmetic. */
2412#define SARITH16(a, b, n, op) do { \
2413 int32_t sum; \
db6e2e65 2414 sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
6ddbc6e4
PB		 2415 RESULT(sum, n, 16); \
2416 if (sum >= 0) \
2417 ge |= 3 << (n * 2); \
2418 } while(0)
2419
2420#define SARITH8(a, b, n, op) do { \
2421 int32_t sum; \
db6e2e65 2422 sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
6ddbc6e4
PB		 2423 RESULT(sum, n, 8); \
2424 if (sum >= 0) \
2425 ge |= 1 << n; \
2426 } while(0)
2427
2428
2429#define ADD16(a, b, n) SARITH16(a, b, n, +)
2430#define SUB16(a, b, n) SARITH16(a, b, n, -)
2431#define ADD8(a, b, n) SARITH8(a, b, n, +)
2432#define SUB8(a, b, n) SARITH8(a, b, n, -)
2433#define PFX s
2434#define ARITH_GE
2435
2436#include "op_addsub.h"
2437
2438/* Unsigned modulo arithmetic. */
2439#define ADD16(a, b, n) do { \
2440 uint32_t sum; \
2441 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2442 RESULT(sum, n, 16); \
a87aa10b 2443 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2444 ge |= 3 << (n * 2); \
2445 } while(0)
2446
2447#define ADD8(a, b, n) do { \
2448 uint32_t sum; \
2449 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2450 RESULT(sum, n, 8); \
a87aa10b
AZ		 2451 if ((sum >> 8) == 1) \
2452 ge |= 1 << n; \
6ddbc6e4
PB		 2453 } while(0)
2454
2455#define SUB16(a, b, n) do { \
2456 uint32_t sum; \
2457 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2458 RESULT(sum, n, 16); \
2459 if ((sum >> 16) == 0) \
2460 ge |= 3 << (n * 2); \
2461 } while(0)
2462
2463#define SUB8(a, b, n) do { \
2464 uint32_t sum; \
2465 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2466 RESULT(sum, n, 8); \
2467 if ((sum >> 8) == 0) \
a87aa10b 2468 ge |= 1 << n; \
6ddbc6e4
PB		 2469 } while(0)
2470
2471#define PFX u
2472#define ARITH_GE
2473
2474#include "op_addsub.h"
2475
2476/* Halved signed arithmetic. */
2477#define ADD16(a, b, n) \
2478 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2479#define SUB16(a, b, n) \
2480 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2481#define ADD8(a, b, n) \
2482 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2483#define SUB8(a, b, n) \
2484 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2485#define PFX sh
2486
2487#include "op_addsub.h"
2488
2489/* Halved unsigned arithmetic. */
2490#define ADD16(a, b, n) \
2491 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2492#define SUB16(a, b, n) \
2493 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2494#define ADD8(a, b, n) \
2495 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2496#define SUB8(a, b, n) \
2497 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2498#define PFX uh
2499
2500#include "op_addsub.h"
2501
2502static inline uint8_t do_usad(uint8_t a, uint8_t b)
2503{
2504 if (a > b)
2505 return a - b;
2506 else
2507 return b - a;
2508}
2509
2510/* Unsigned sum of absolute byte differences. */
2511uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2512{
2513 uint32_t sum;
2514 sum = do_usad(a, b);
2515 sum += do_usad(a >> 8, b >> 8);
2516 sum += do_usad(a >> 16, b >>16);
2517 sum += do_usad(a >> 24, b >> 24);
2518 return sum;
2519}
2520
2521/* For ARMv6 SEL instruction. */
2522uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2523{
2524 uint32_t mask;
2525
2526 mask = 0;
2527 if (flags & 1)
2528 mask |= 0xff;
2529 if (flags & 2)
2530 mask |= 0xff00;
2531 if (flags & 4)
2532 mask |= 0xff0000;
2533 if (flags & 8)
2534 mask |= 0xff000000;
2535 return (a & mask) | (b & ~mask);
2536}
2537
5e3f878a
PB		 2538uint32_t HELPER(logicq_cc)(uint64_t val)
2539{
2540 return (val >> 32) | (val != 0);
2541}
4373f3ce
PB		 2542
2543/* VFP support. We follow the convention used for VFP instrunctions:
2544 Single precition routines have a "s" suffix, double precision a
2545 "d" suffix. */
2546
2547/* Convert host exception flags to vfp form. */
2548static inline int vfp_exceptbits_from_host(int host_bits)
2549{
2550 int target_bits = 0;
2551
2552 if (host_bits & float_flag_invalid)
2553 target_bits |= 1;
2554 if (host_bits & float_flag_divbyzero)
2555 target_bits |= 2;
2556 if (host_bits & float_flag_overflow)
2557 target_bits |= 4;
36802b6b 2558 if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4373f3ce
PB		 2559 target_bits |= 8;
2560 if (host_bits & float_flag_inexact)
2561 target_bits |= 0x10;
cecd8504
PM		 2562 if (host_bits & float_flag_input_denormal)
2563 target_bits |= 0x80;
4373f3ce
PB		 2564 return target_bits;
2565}
2566
0ecb72a5 2567uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4373f3ce
PB		 2568{
2569 int i;
2570 uint32_t fpscr;
2571
2572 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2573 | (env->vfp.vec_len << 16)
2574 | (env->vfp.vec_stride << 20);
2575 i = get_float_exception_flags(&env->vfp.fp_status);
3a492f3a 2576 i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4373f3ce
PB		 2577 fpscr |= vfp_exceptbits_from_host(i);
2578 return fpscr;
2579}
2580
0ecb72a5 2581uint32_t vfp_get_fpscr(CPUARMState *env)
01653295
PM		 2582{
2583 return HELPER(vfp_get_fpscr)(env);
2584}
2585
4373f3ce
PB		 2586/* Convert vfp exception flags to target form. */
2587static inline int vfp_exceptbits_to_host(int target_bits)
2588{
2589 int host_bits = 0;
2590
2591 if (target_bits & 1)
2592 host_bits |= float_flag_invalid;
2593 if (target_bits & 2)
2594 host_bits |= float_flag_divbyzero;
2595 if (target_bits & 4)
2596 host_bits |= float_flag_overflow;
2597 if (target_bits & 8)
2598 host_bits |= float_flag_underflow;
2599 if (target_bits & 0x10)
2600 host_bits |= float_flag_inexact;
cecd8504
PM		 2601 if (target_bits & 0x80)
2602 host_bits |= float_flag_input_denormal;
4373f3ce
PB		 2603 return host_bits;
2604}
2605
0ecb72a5 2606void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4373f3ce
PB		 2607{
2608 int i;
2609 uint32_t changed;
2610
2611 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2612 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2613 env->vfp.vec_len = (val >> 16) & 7;
2614 env->vfp.vec_stride = (val >> 20) & 3;
2615
2616 changed ^= val;
2617 if (changed & (3 << 22)) {
2618 i = (val >> 22) & 3;
2619 switch (i) {
2620 case 0:
2621 i = float_round_nearest_even;
2622 break;
2623 case 1:
2624 i = float_round_up;
2625 break;
2626 case 2:
2627 i = float_round_down;
2628 break;
2629 case 3:
2630 i = float_round_to_zero;
2631 break;
2632 }
2633 set_float_rounding_mode(i, &env->vfp.fp_status);
2634 }
cecd8504 2635 if (changed & (1 << 24)) {
fe76d976 2636 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
cecd8504
PM		 2637 set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
2638 }
5c7908ed
PB		 2639 if (changed & (1 << 25))
2640 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce 2641
b12c390b 2642 i = vfp_exceptbits_to_host(val);
4373f3ce 2643 set_float_exception_flags(i, &env->vfp.fp_status);
3a492f3a 2644 set_float_exception_flags(0, &env->vfp.standard_fp_status);
4373f3ce
PB		 2645}
2646
0ecb72a5 2647void vfp_set_fpscr(CPUARMState *env, uint32_t val)
01653295
PM		 2648{
2649 HELPER(vfp_set_fpscr)(env, val);
2650}
2651
4373f3ce
PB		 2652#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2653
2654#define VFP_BINOP(name) \
ae1857ec 2655float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4373f3ce 2656{ \
ae1857ec
PM		 2657 float_status *fpst = fpstp; \
2658 return float32_ ## name(a, b, fpst); \
4373f3ce 2659} \
ae1857ec 2660float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4373f3ce 2661{ \
ae1857ec
PM		 2662 float_status *fpst = fpstp; \
2663 return float64_ ## name(a, b, fpst); \
4373f3ce
PB		 2664}
2665VFP_BINOP(add)
2666VFP_BINOP(sub)
2667VFP_BINOP(mul)
2668VFP_BINOP(div)
2669#undef VFP_BINOP
2670
2671float32 VFP_HELPER(neg, s)(float32 a)
2672{
2673 return float32_chs(a);
2674}
2675
2676float64 VFP_HELPER(neg, d)(float64 a)
2677{
66230e0d 2678 return float64_chs(a);
4373f3ce
PB		 2679}
2680
2681float32 VFP_HELPER(abs, s)(float32 a)
2682{
2683 return float32_abs(a);
2684}
2685
2686float64 VFP_HELPER(abs, d)(float64 a)
2687{
66230e0d 2688 return float64_abs(a);
4373f3ce
PB		 2689}
2690
0ecb72a5 2691float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4373f3ce
PB		 2692{
2693 return float32_sqrt(a, &env->vfp.fp_status);
2694}
2695
0ecb72a5 2696float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4373f3ce
PB		 2697{
2698 return float64_sqrt(a, &env->vfp.fp_status);
2699}
2700
2701/* XXX: check quiet/signaling case */
2702#define DO_VFP_cmp(p, type) \
0ecb72a5 2703void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2704{ \
2705 uint32_t flags; \
2706 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2707 case 0: flags = 0x6; break; \
2708 case -1: flags = 0x8; break; \
2709 case 1: flags = 0x2; break; \
2710 default: case 2: flags = 0x3; break; \
2711 } \
2712 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2713 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2714} \
0ecb72a5 2715void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4373f3ce
PB		 2716{ \
2717 uint32_t flags; \
2718 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2719 case 0: flags = 0x6; break; \
2720 case -1: flags = 0x8; break; \
2721 case 1: flags = 0x2; break; \
2722 default: case 2: flags = 0x3; break; \
2723 } \
2724 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2725 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2726}
2727DO_VFP_cmp(s, float32)
2728DO_VFP_cmp(d, float64)
2729#undef DO_VFP_cmp
2730
5500b06c 2731/* Integer to float and float to integer conversions */
4373f3ce 2732
5500b06c
PM		 2733#define CONV_ITOF(name, fsz, sign) \
2734 float##fsz HELPER(name)(uint32_t x, void *fpstp) \
2735{ \
2736 float_status *fpst = fpstp; \
85836979 2737 return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4373f3ce
PB		 2738}
2739
5500b06c
PM		 2740#define CONV_FTOI(name, fsz, sign, round) \
2741uint32_t HELPER(name)(float##fsz x, void *fpstp) \
2742{ \
2743 float_status *fpst = fpstp; \
2744 if (float##fsz##_is_any_nan(x)) { \
2745 float_raise(float_flag_invalid, fpst); \
2746 return 0; \
2747 } \
2748 return float##fsz##_to_##sign##int32##round(x, fpst); \
4373f3ce
PB		 2749}
2750
5500b06c
PM		 2751#define FLOAT_CONVS(name, p, fsz, sign) \
2752CONV_ITOF(vfp_##name##to##p, fsz, sign) \
2753CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
2754CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4373f3ce 2755
5500b06c
PM		 2756FLOAT_CONVS(si, s, 32, )
2757FLOAT_CONVS(si, d, 64, )
2758FLOAT_CONVS(ui, s, 32, u)
2759FLOAT_CONVS(ui, d, 64, u)
4373f3ce 2760
5500b06c
PM		 2761#undef CONV_ITOF
2762#undef CONV_FTOI
2763#undef FLOAT_CONVS
4373f3ce
PB		 2764
2765/* floating point conversion */
0ecb72a5 2766float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4373f3ce 2767{
2d627737
PM		 2768 float64 r = float32_to_float64(x, &env->vfp.fp_status);
2769 /* ARM requires that S<->D conversion of any kind of NaN generates
2770 * a quiet NaN by forcing the most significant frac bit to 1.
2771 */
2772 return float64_maybe_silence_nan(r);
4373f3ce
PB		 2773}
2774
0ecb72a5 2775float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4373f3ce 2776{
2d627737
PM		 2777 float32 r = float64_to_float32(x, &env->vfp.fp_status);
2778 /* ARM requires that S<->D conversion of any kind of NaN generates
2779 * a quiet NaN by forcing the most significant frac bit to 1.
2780 */
2781 return float32_maybe_silence_nan(r);
4373f3ce
PB		 2782}
2783
2784/* VFP3 fixed point conversion. */
622465e1 2785#define VFP_CONV_FIX(name, p, fsz, itype, sign) \
5500b06c
PM		 2786float##fsz HELPER(vfp_##name##to##p)(uint##fsz##_t x, uint32_t shift, \
2787 void *fpstp) \
4373f3ce 2788{ \
5500b06c 2789 float_status *fpst = fpstp; \
622465e1 2790 float##fsz tmp; \
5500b06c
PM		 2791 tmp = sign##int32_to_##float##fsz((itype##_t)x, fpst); \
2792 return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4373f3ce 2793} \
5500b06c
PM		 2794uint##fsz##_t HELPER(vfp_to##name##p)(float##fsz x, uint32_t shift, \
2795 void *fpstp) \
4373f3ce 2796{ \
5500b06c 2797 float_status *fpst = fpstp; \
622465e1
PM		 2798 float##fsz tmp; \
2799 if (float##fsz##_is_any_nan(x)) { \
5500b06c 2800 float_raise(float_flag_invalid, fpst); \
622465e1 2801 return 0; \
09d9487f 2802 } \
5500b06c
PM		 2803 tmp = float##fsz##_scalbn(x, shift, fpst); \
2804 return float##fsz##_to_##itype##_round_to_zero(tmp, fpst); \
622465e1
PM		 2805}
2806
2807VFP_CONV_FIX(sh, d, 64, int16, )
2808VFP_CONV_FIX(sl, d, 64, int32, )
2809VFP_CONV_FIX(uh, d, 64, uint16, u)
2810VFP_CONV_FIX(ul, d, 64, uint32, u)
2811VFP_CONV_FIX(sh, s, 32, int16, )
2812VFP_CONV_FIX(sl, s, 32, int32, )
2813VFP_CONV_FIX(uh, s, 32, uint16, u)
2814VFP_CONV_FIX(ul, s, 32, uint32, u)
4373f3ce
PB		 2815#undef VFP_CONV_FIX
2816
60011498 2817/* Half precision conversions. */
0ecb72a5 2818static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
60011498 2819{
60011498 2820 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2821 float32 r = float16_to_float32(make_float16(a), ieee, s);
2822 if (ieee) {
2823 return float32_maybe_silence_nan(r);
2824 }
2825 return r;
60011498
PB		 2826}
2827
0ecb72a5 2828static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
60011498 2829{
60011498 2830 int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
fb91678d
PM		 2831 float16 r = float32_to_float16(a, ieee, s);
2832 if (ieee) {
2833 r = float16_maybe_silence_nan(r);
2834 }
2835 return float16_val(r);
60011498
PB		 2836}
2837
0ecb72a5 2838float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2839{
2840 return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
2841}
2842
0ecb72a5 2843uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2844{
2845 return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
2846}
2847
0ecb72a5 2848float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
2d981da7
PM		 2849{
2850 return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
2851}
2852
0ecb72a5 2853uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
2d981da7
PM		 2854{
2855 return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
2856}
2857
dda3ec49 2858#define float32_two make_float32(0x40000000)
6aae3df1
PM		 2859#define float32_three make_float32(0x40400000)
2860#define float32_one_point_five make_float32(0x3fc00000)
dda3ec49 2861
0ecb72a5 2862float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2863{
dda3ec49
PM		 2864 float_status *s = &env->vfp.standard_fp_status;
2865 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2866 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2867 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2868 float_raise(float_flag_input_denormal, s);
2869 }
dda3ec49
PM		 2870 return float32_two;
2871 }
2872 return float32_sub(float32_two, float32_mul(a, b, s), s);
4373f3ce
PB		 2873}
2874
0ecb72a5 2875float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4373f3ce 2876{
71826966 2877 float_status *s = &env->vfp.standard_fp_status;
9ea62f57
PM		 2878 float32 product;
2879 if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
2880 (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
43fe9bdb
PM		 2881 if (!(float32_is_zero(a) || float32_is_zero(b))) {
2882 float_raise(float_flag_input_denormal, s);
2883 }
6aae3df1 2884 return float32_one_point_five;
9ea62f57 2885 }
6aae3df1
PM		 2886 product = float32_mul(a, b, s);
2887 return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4373f3ce
PB		 2888}
2889
8f8e3aa4
PB		 2890/* NEON helpers. */
2891
56bf4fe2
CL		 2892/* Constants 256 and 512 are used in some helpers; we avoid relying on
2893 * int->float conversions at run-time. */
2894#define float64_256 make_float64(0x4070000000000000LL)
2895#define float64_512 make_float64(0x4080000000000000LL)
2896
fe0e4872
CL		 2897/* The algorithm that must be used to calculate the estimate
2898 * is specified by the ARM ARM.
2899 */
0ecb72a5 2900static float64 recip_estimate(float64 a, CPUARMState *env)
fe0e4872 2901{
1146a817
PM		 2902 /* These calculations mustn't set any fp exception flags,
2903 * so we use a local copy of the fp_status.
2904 */
2905 float_status dummy_status = env->vfp.standard_fp_status;
2906 float_status *s = &dummy_status;
fe0e4872
CL		 2907 /* q = (int)(a * 512.0) */
2908 float64 q = float64_mul(float64_512, a, s);
2909 int64_t q_int = float64_to_int64_round_to_zero(q, s);
2910
2911 /* r = 1.0 / (((double)q + 0.5) / 512.0) */
2912 q = int64_to_float64(q_int, s);
2913 q = float64_add(q, float64_half, s);
2914 q = float64_div(q, float64_512, s);
2915 q = float64_div(float64_one, q, s);
2916
2917 /* s = (int)(256.0 * r + 0.5) */
2918 q = float64_mul(q, float64_256, s);
2919 q = float64_add(q, float64_half, s);
2920 q_int = float64_to_int64_round_to_zero(q, s);
2921
2922 /* return (double)s / 256.0 */
2923 return float64_div(int64_to_float64(q_int, s), float64_256, s);
2924}
2925
0ecb72a5 2926float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
4373f3ce 2927{
fe0e4872
CL		 2928 float_status *s = &env->vfp.standard_fp_status;
2929 float64 f64;
2930 uint32_t val32 = float32_val(a);
2931
2932 int result_exp;
2933 int a_exp = (val32 & 0x7f800000) >> 23;
2934 int sign = val32 & 0x80000000;
2935
2936 if (float32_is_any_nan(a)) {
2937 if (float32_is_signaling_nan(a)) {
2938 float_raise(float_flag_invalid, s);
2939 }
2940 return float32_default_nan;
2941 } else if (float32_is_infinity(a)) {
2942 return float32_set_sign(float32_zero, float32_is_neg(a));
2943 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 2944 if (!float32_is_zero(a)) {
2945 float_raise(float_flag_input_denormal, s);
2946 }
fe0e4872
CL		 2947 float_raise(float_flag_divbyzero, s);
2948 return float32_set_sign(float32_infinity, float32_is_neg(a));
2949 } else if (a_exp >= 253) {
2950 float_raise(float_flag_underflow, s);
2951 return float32_set_sign(float32_zero, float32_is_neg(a));
2952 }
2953
2954 f64 = make_float64((0x3feULL << 52)
2955 | ((int64_t)(val32 & 0x7fffff) << 29));
2956
2957 result_exp = 253 - a_exp;
2958
2959 f64 = recip_estimate(f64, env);
2960
2961 val32 = sign
2962 | ((result_exp & 0xff) << 23)
2963 | ((float64_val(f64) >> 29) & 0x7fffff);
2964 return make_float32(val32);
4373f3ce
PB		 2965}
2966
e07be5d2
CL		 2967/* The algorithm that must be used to calculate the estimate
2968 * is specified by the ARM ARM.
2969 */
0ecb72a5 2970static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
e07be5d2 2971{
1146a817
PM		 2972 /* These calculations mustn't set any fp exception flags,
2973 * so we use a local copy of the fp_status.
2974 */
2975 float_status dummy_status = env->vfp.standard_fp_status;
2976 float_status *s = &dummy_status;
e07be5d2
CL		 2977 float64 q;
2978 int64_t q_int;
2979
2980 if (float64_lt(a, float64_half, s)) {
2981 /* range 0.25 <= a < 0.5 */
2982
2983 /* a in units of 1/512 rounded down */
2984 /* q0 = (int)(a * 512.0); */
2985 q = float64_mul(float64_512, a, s);
2986 q_int = float64_to_int64_round_to_zero(q, s);
2987
2988 /* reciprocal root r */
2989 /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0); */
2990 q = int64_to_float64(q_int, s);
2991 q = float64_add(q, float64_half, s);
2992 q = float64_div(q, float64_512, s);
2993 q = float64_sqrt(q, s);
2994 q = float64_div(float64_one, q, s);
2995 } else {
2996 /* range 0.5 <= a < 1.0 */
2997
2998 /* a in units of 1/256 rounded down */
2999 /* q1 = (int)(a * 256.0); */
3000 q = float64_mul(float64_256, a, s);
3001 int64_t q_int = float64_to_int64_round_to_zero(q, s);
3002
3003 /* reciprocal root r */
3004 /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
3005 q = int64_to_float64(q_int, s);
3006 q = float64_add(q, float64_half, s);
3007 q = float64_div(q, float64_256, s);
3008 q = float64_sqrt(q, s);
3009 q = float64_div(float64_one, q, s);
3010 }
3011 /* r in units of 1/256 rounded to nearest */
3012 /* s = (int)(256.0 * r + 0.5); */
3013
3014 q = float64_mul(q, float64_256,s );
3015 q = float64_add(q, float64_half, s);
3016 q_int = float64_to_int64_round_to_zero(q, s);
3017
3018 /* return (double)s / 256.0;*/
3019 return float64_div(int64_to_float64(q_int, s), float64_256, s);
3020}
3021
0ecb72a5 3022float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
4373f3ce 3023{
e07be5d2
CL		 3024 float_status *s = &env->vfp.standard_fp_status;
3025 int result_exp;
3026 float64 f64;
3027 uint32_t val;
3028 uint64_t val64;
3029
3030 val = float32_val(a);
3031
3032 if (float32_is_any_nan(a)) {
3033 if (float32_is_signaling_nan(a)) {
3034 float_raise(float_flag_invalid, s);
3035 }
3036 return float32_default_nan;
3037 } else if (float32_is_zero_or_denormal(a)) {
43fe9bdb
PM		 3038 if (!float32_is_zero(a)) {
3039 float_raise(float_flag_input_denormal, s);
3040 }
e07be5d2
CL		 3041 float_raise(float_flag_divbyzero, s);
3042 return float32_set_sign(float32_infinity, float32_is_neg(a));
3043 } else if (float32_is_neg(a)) {
3044 float_raise(float_flag_invalid, s);
3045 return float32_default_nan;
3046 } else if (float32_is_infinity(a)) {
3047 return float32_zero;
3048 }
3049
3050 /* Normalize to a double-precision value between 0.25 and 1.0,
3051 * preserving the parity of the exponent. */
3052 if ((val & 0x800000) == 0) {
3053 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3054 | (0x3feULL << 52)
3055 | ((uint64_t)(val & 0x7fffff) << 29));
3056 } else {
3057 f64 = make_float64(((uint64_t)(val & 0x80000000) << 32)
3058 | (0x3fdULL << 52)
3059 | ((uint64_t)(val & 0x7fffff) << 29));
3060 }
3061
3062 result_exp = (380 - ((val & 0x7f800000) >> 23)) / 2;
3063
3064 f64 = recip_sqrt_estimate(f64, env);
3065
3066 val64 = float64_val(f64);
3067
26cc6abf 3068 val = ((result_exp & 0xff) << 23)
e07be5d2
CL		 3069 | ((val64 >> 29) & 0x7fffff);
3070 return make_float32(val);
4373f3ce
PB		 3071}
3072
0ecb72a5 3073uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3074{
fe0e4872
CL		 3075 float64 f64;
3076
3077 if ((a & 0x80000000) == 0) {
3078 return 0xffffffff;
3079 }
3080
3081 f64 = make_float64((0x3feULL << 52)
3082 | ((int64_t)(a & 0x7fffffff) << 21));
3083
3084 f64 = recip_estimate (f64, env);
3085
3086 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce
PB		 3087}
3088
0ecb72a5 3089uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
4373f3ce 3090{
e07be5d2
CL		 3091 float64 f64;
3092
3093 if ((a & 0xc0000000) == 0) {
3094 return 0xffffffff;
3095 }
3096
3097 if (a & 0x80000000) {
3098 f64 = make_float64((0x3feULL << 52)
3099 | ((uint64_t)(a & 0x7fffffff) << 21));
3100 } else { /* bits 31-30 == '01' */
3101 f64 = make_float64((0x3fdULL << 52)
3102 | ((uint64_t)(a & 0x3fffffff) << 22));
3103 }
3104
3105 f64 = recip_sqrt_estimate(f64, env);
3106
3107 return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
4373f3ce 3108}
fe1479c3 3109
da97f52c
PM		 3110/* VFPv4 fused multiply-accumulate */
3111float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
3112{
3113 float_status *fpst = fpstp;
3114 return float32_muladd(a, b, c, 0, fpst);
3115}
3116
3117float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
3118{
3119 float_status *fpst = fpstp;
3120 return float64_muladd(a, b, c, 0, fpst);
3121}
Qemu copy for testing