[mirror_edk2.git] / ArmPkg / Include / Library / ArmLib.h

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
  Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#ifndef __ARM_LIB__\r
#define __ARM_LIB__\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
#ifdef MDE_CPU_ARM\r
  #include <Chipset/ArmV7.h>\r
#elif defined(MDE_CPU_AARCH64)\r
  #include <Chipset/AArch64.h>\r
#else\r
 #error "Unknown chipset."\r
#endif\r
\r
#define EFI_MEMORY_CACHETYPE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
                                     EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
                                     EFI_MEMORY_UCE)\r
\r
/**\r
 * The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
 *\r
 * The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
 * be used in Secure World to distinguished Secure to Non-Secure memory.\r
 */\r
typedef enum {\r
  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
  ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
} ARM_MEMORY_REGION_ATTRIBUTES;\r
\r
#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
\r
typedef struct {\r
  EFI_PHYSICAL_ADDRESS          PhysicalBase;\r
  EFI_VIRTUAL_ADDRESS           VirtualBase;\r
  UINT64                        Length;\r
  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
typedef VOID (*CACHE_OPERATION)(VOID);\r
typedef VOID (*LINE_OPERATION)(UINTN);\r
\r
//\r
// ARM Processor Mode\r
//\r
typedef enum {\r
  ARM_PROCESSOR_MODE_USER       = 0x10,\r
  ARM_PROCESSOR_MODE_FIQ        = 0x11,\r
  ARM_PROCESSOR_MODE_IRQ        = 0x12,\r
  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
  ARM_PROCESSOR_MODE_ABORT      = 0x17,\r
  ARM_PROCESSOR_MODE_HYP        = 0x1A,\r
  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,\r
  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,\r
  ARM_PROCESSOR_MODE_MASK       = 0x1F\r
} ARM_PROCESSOR_MODE;\r
\r
//\r
// ARM Cpu IDs\r
//\r
#define ARM_CPU_IMPLEMENTER_MASK          (0xFFU << 24)\r
#define ARM_CPU_IMPLEMENTER_ARMLTD        (0x41U << 24)\r
#define ARM_CPU_IMPLEMENTER_DEC           (0x44U << 24)\r
#define ARM_CPU_IMPLEMENTER_MOT           (0x4DU << 24)\r
#define ARM_CPU_IMPLEMENTER_QUALCOMM      (0x51U << 24)\r
#define ARM_CPU_IMPLEMENTER_MARVELL       (0x56U << 24)\r
\r
#define ARM_CPU_PRIMARY_PART_MASK         (0xFFF << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA5     (0xC05 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA7     (0xC07 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA8     (0xC08 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA9     (0xC09 << 4)\r
#define ARM_CPU_PRIMARY_PART_CORTEXA15    (0xC0F << 4)\r
\r
//\r
// ARM MP Core IDs\r
//\r
#define ARM_CORE_AFF0         0xFF\r
#define ARM_CORE_AFF1         (0xFF << 8)\r
#define ARM_CORE_AFF2         (0xFF << 16)\r
#define ARM_CORE_AFF3         (0xFFULL << 32)\r
\r
#define ARM_CORE_MASK         ARM_CORE_AFF0\r
#define ARM_CLUSTER_MASK      ARM_CORE_AFF1\r
#define GET_CORE_ID(MpId)     ((MpId) & ARM_CORE_MASK)\r
#define GET_CLUSTER_ID(MpId)  (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
#define GET_MPID(ClusterId, CoreId)   (((ClusterId) << 8) | (CoreId))\r
#define PRIMARY_CORE_ID       (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
\r
UINTN\r
EFIAPI\r
ArmDataCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmInstructionCacheLineLength (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheWritebackGranule (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmIsArchTimerImplemented (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr0 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadIdPfr1 (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmCacheInfo (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmIsMpCore (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCache (\r
  VOID\r
  );\r
\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryByMVA (\r
IN  UINTN   Address\r
);\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryByMVA (\r
  IN  UINTN   Address\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanDataCacheEntryBySetWay (\r
  IN  UINTN  SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCleanInvalidateDataCacheEntryBySetWay (\r
  IN  UINTN   SetWayFormat\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableDataCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableInstructionCache (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableCachesAndMmu (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableInterrupts (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableInterrupts (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetInterruptState (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableAsynchronousAbort (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableAsynchronousAbort (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableIrq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableIrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableFiq (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmDisableFiq (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmGetFiqState (\r
  VOID\r
  );\r
\r
/**\r
 * Invalidate Data and Instruction TLBs\r
 */\r
VOID\r
EFIAPI\r
ArmInvalidateTlb (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUpdateTranslationTableEntry (\r
  IN  VOID     *TranslationTableEntry,\r
  IN  VOID     *Mva\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetDomainAccessControl (\r
  IN  UINT32  Domain\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBR0 (\r
  IN  VOID  *TranslationTableBase\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetTTBCR (\r
  IN  UINT32 Bits\r
  );\r
\r
VOID *\r
EFIAPI\r
ArmGetTTBR0BaseAddress (\r
  VOID\r
  );\r
\r
BOOLEAN\r
EFIAPI\r
ArmMmuEnabled (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDisableBranchPrediction (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetLowVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetHighVectors (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataMemoryBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmDataSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmInstructionSynchronizationBarrier (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteVBar (\r
  IN  UINTN   VectorBase\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteAuxCr (\r
  IN  UINT32    Bit\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadAuxCr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetAuxCrBit (\r
  IN  UINT32    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallSEV (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFE (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmCallWFI (\r
\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMpidr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadMidr (\r
  VOID\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadCpacr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpacr (\r
  IN  UINT32   Access\r
  );\r
\r
VOID\r
EFIAPI\r
ArmEnableVFP (\r
  VOID\r
  );\r
\r
/**\r
  Get the Secure Configuration Register value\r
\r
  @return   Value read from the Secure Configuration Register\r
\r
**/\r
UINT32\r
EFIAPI\r
ArmReadScr (\r
  VOID\r
  );\r
\r
/**\r
  Set the Secure Configuration Register\r
\r
  @param Value   Value to write to the Secure Configuration Register\r
\r
**/\r
VOID\r
EFIAPI\r
ArmWriteScr (\r
  IN  UINT32   Value\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadMVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteMVBar (\r
  IN  UINT32   VectorMonitorBase\r
  );\r
\r
UINT32\r
EFIAPI\r
ArmReadSctlr (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadHVBar (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteHVBar (\r
  IN  UINTN   HypModeVectorBase\r
  );\r
\r
\r
//\r
// Helper functions for accessing CPU ACTLR\r
//\r
\r
UINTN\r
EFIAPI\r
ArmReadCpuActlr (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCpuActlr (\r
  IN  UINTN Val\r
  );\r
\r
VOID\r
EFIAPI\r
ArmSetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
VOID\r
EFIAPI\r
ArmUnsetCpuActlrBit (\r
  IN  UINTN    Bits\r
  );\r
\r
//\r
// Accessors for the architected generic timer registers\r
//\r
\r
#define ARM_ARCH_TIMER_ENABLE           (1 << 0)\r
#define ARM_ARCH_TIMER_IMASK            (1 << 1)\r
#define ARM_ARCH_TIMER_ISTATUS          (1 << 2)\r
\r
UINTN\r
EFIAPI\r
ArmReadCntFrq (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntFrq (\r
  UINTN   FreqInHz\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntPct (\r
  VOID\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntkCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntkCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntpCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCtl (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvTval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvTval (\r
  UINTN   Val\r
  );\r
\r
UINTN\r
EFIAPI\r
ArmReadCntvCtl (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCtl (\r
  UINTN   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCt (\r
  VOID\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntpCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntpCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvCval (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvCval (\r
  UINT64   Val\r
  );\r
\r
UINT64\r
EFIAPI\r
ArmReadCntvOff (\r
  VOID\r
  );\r
\r
VOID\r
EFIAPI\r
ArmWriteCntvOff (\r
  UINT64   Val\r
  );\r
\r
#endif // __ARM_LIB__\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
ff1f27c0	4	Copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>\r
1e57a462	5	\r
	6	This program and the accompanying materials\r
	7	are licensed and made available under the terms and conditions of the BSD License\r
	8	which accompanies this distribution. The full text of the license may be found at\r
	9	http://opensource.org/licenses/bsd-license.php\r
	10	\r
	11	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	12	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	13	\r
	14	**/\r
	15	\r
	16	#ifndef __ARM_LIB__\r
	17	#define __ARM_LIB__\r
	18	\r
	19	#include <Uefi/UefiBaseType.h>\r
	20	\r
25402f5d	21	#ifdef MDE_CPU_ARM\r
70119d27	22	#include <Chipset/ArmV7.h>\r
25402f5d HL	23	#elif defined(MDE_CPU_AARCH64)\r
25402f5d HL	24	#include <Chipset/AArch64.h>\r
1e57a462	25	#else\r
25402f5d	26	#error "Unknown chipset."\r
1e57a462	27	#endif\r
1e57a462	28	\r
e0307a7d AB	29	#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC \| EFI_MEMORY_WC \| \\r
	30	EFI_MEMORY_WT \| EFI_MEMORY_WB \| \\r
	31	EFI_MEMORY_UCE)\r
	32	\r
1e57a462	33	/**\r
	34	* The UEFI firmware must not use the ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_* attributes.\r
	35	*\r
	36	* The Non Secure memory attribute (ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_*) should only\r
	37	* be used in Secure World to distinguished Secure to Non-Secure memory.\r
	38	*/\r
	39	typedef enum {\r
	40	ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED = 0,\r
	41	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED,\r
	42	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,\r
	43	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK,\r
	44	ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,\r
	45	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH,\r
	46	ARM_MEMORY_REGION_ATTRIBUTE_DEVICE,\r
	47	ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE\r
	48	} ARM_MEMORY_REGION_ATTRIBUTES;\r
	49	\r
	50	#define IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(attr) ((UINT32)(attr) & 1)\r
	51	\r
	52	typedef struct {\r
	53	EFI_PHYSICAL_ADDRESS PhysicalBase;\r
	54	EFI_VIRTUAL_ADDRESS VirtualBase;\r
c357fd6a	55	UINT64 Length;\r
1e57a462	56	ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
	57	} ARM_MEMORY_REGION_DESCRIPTOR;\r
	58	\r
	59	typedef VOID (*CACHE_OPERATION)(VOID);\r
	60	typedef VOID (*LINE_OPERATION)(UINTN);\r
	61	\r
	62	//\r
	63	// ARM Processor Mode\r
	64	//\r
	65	typedef enum {\r
	66	ARM_PROCESSOR_MODE_USER = 0x10,\r
	67	ARM_PROCESSOR_MODE_FIQ = 0x11,\r
	68	ARM_PROCESSOR_MODE_IRQ = 0x12,\r
	69	ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,\r
	70	ARM_PROCESSOR_MODE_ABORT = 0x17,\r
	71	ARM_PROCESSOR_MODE_HYP = 0x1A,\r
	72	ARM_PROCESSOR_MODE_UNDEFINED = 0x1B,\r
	73	ARM_PROCESSOR_MODE_SYSTEM = 0x1F,\r
	74	ARM_PROCESSOR_MODE_MASK = 0x1F\r
	75	} ARM_PROCESSOR_MODE;\r
	76	\r
	77	//\r
	78	// ARM Cpu IDs\r
	79	//\r
	80	#define ARM_CPU_IMPLEMENTER_MASK (0xFFU << 24)\r
	81	#define ARM_CPU_IMPLEMENTER_ARMLTD (0x41U << 24)\r
	82	#define ARM_CPU_IMPLEMENTER_DEC (0x44U << 24)\r
	83	#define ARM_CPU_IMPLEMENTER_MOT (0x4DU << 24)\r
	84	#define ARM_CPU_IMPLEMENTER_QUALCOMM (0x51U << 24)\r
	85	#define ARM_CPU_IMPLEMENTER_MARVELL (0x56U << 24)\r
	86	\r
	87	#define ARM_CPU_PRIMARY_PART_MASK (0xFFF << 4)\r
	88	#define ARM_CPU_PRIMARY_PART_CORTEXA5 (0xC05 << 4)\r
	89	#define ARM_CPU_PRIMARY_PART_CORTEXA7 (0xC07 << 4)\r
	90	#define ARM_CPU_PRIMARY_PART_CORTEXA8 (0xC08 << 4)\r
	91	#define ARM_CPU_PRIMARY_PART_CORTEXA9 (0xC09 << 4)\r
	92	#define ARM_CPU_PRIMARY_PART_CORTEXA15 (0xC0F << 4)\r
	93	\r
	94	//\r
	95	// ARM MP Core IDs\r
	96	//\r
90ed18ca OM	97	#define ARM_CORE_AFF0 0xFF\r
	98	#define ARM_CORE_AFF1 (0xFF << 8)\r
	99	#define ARM_CORE_AFF2 (0xFF << 16)\r
	100	#define ARM_CORE_AFF3 (0xFFULL << 32)\r
	101	\r
	102	#define ARM_CORE_MASK ARM_CORE_AFF0\r
	103	#define ARM_CLUSTER_MASK ARM_CORE_AFF1\r
1e57a462	104	#define GET_CORE_ID(MpId) ((MpId) & ARM_CORE_MASK)\r
1e57a462	105	#define GET_CLUSTER_ID(MpId) (((MpId) & ARM_CLUSTER_MASK) >> 8)\r
e359565e	106	#define GET_MPID(ClusterId, CoreId) (((ClusterId) << 8) \| (CoreId))\r
1e57a462	107	#define PRIMARY_CORE_ID (PcdGet32(PcdArmPrimaryCore) & ARM_CORE_MASK)\r
1e57a462	108	\r
1e57a462	109	UINTN\r
	110	EFIAPI\r
	111	ArmDataCacheLineLength (\r
	112	VOID\r
	113	);\r
3402aac7	114	\r
1e57a462	115	UINTN\r
	116	EFIAPI\r
	117	ArmInstructionCacheLineLength (\r
	118	VOID\r
	119	);\r
168d7245	120	\r
c653fc2a AB	121	UINTN\r
	122	EFIAPI\r
	123	ArmCacheWritebackGranule (\r
	124	VOID\r
	125	);\r
	126	\r
168d7245 OM	127	UINTN\r
	128	EFIAPI\r
	129	ArmIsArchTimerImplemented (\r
	130	VOID\r
	131	);\r
	132	\r
	133	UINTN\r
	134	EFIAPI\r
	135	ArmReadIdPfr0 (\r
	136	VOID\r
	137	);\r
	138	\r
	139	UINTN\r
	140	EFIAPI\r
	141	ArmReadIdPfr1 (\r
	142	VOID\r
	143	);\r
	144	\r
64751727	145	UINTN\r
1e57a462	146	EFIAPI\r
64751727	147	ArmCacheInfo (\r
1e57a462	148	VOID\r
	149	);\r
	150	\r
	151	BOOLEAN\r
	152	EFIAPI\r
	153	ArmIsMpCore (\r
	154	VOID\r
	155	);\r
	156	\r
	157	VOID\r
	158	EFIAPI\r
	159	ArmInvalidateDataCache (\r
	160	VOID\r
	161	);\r
	162	\r
	163	\r
	164	VOID\r
	165	EFIAPI\r
	166	ArmCleanInvalidateDataCache (\r
	167	VOID\r
	168	);\r
	169	\r
	170	VOID\r
	171	EFIAPI\r
	172	ArmCleanDataCache (\r
	173	VOID\r
	174	);\r
	175	\r
1e57a462	176	VOID\r
	177	EFIAPI\r
	178	ArmInvalidateInstructionCache (\r
	179	VOID\r
	180	);\r
	181	\r
	182	VOID\r
	183	EFIAPI\r
	184	ArmInvalidateDataCacheEntryByMVA (\r
	185	IN UINTN Address\r
	186	);\r
	187	\r
	188	VOID\r
	189	EFIAPI\r
cf580da1	190	ArmCleanDataCacheEntryToPoUByMVA (\r
1e57a462	191	IN UINTN Address\r
	192	);\r
	193	\r
b7de7e3c EC	194	VOID\r
b7de7e3c EC	195	EFIAPI\r
cf580da1 AB	196	ArmInvalidateInstructionCacheEntryToPoUByMVA (\r
	197	IN UINTN Address\r
	198	);\r
	199	\r
	200	VOID\r
	201	EFIAPI\r
	202	ArmCleanDataCacheEntryByMVA (\r
b7de7e3c EC	203	IN UINTN Address\r
	204	);\r
	205	\r
1e57a462	206	VOID\r
	207	EFIAPI\r
	208	ArmCleanInvalidateDataCacheEntryByMVA (\r
	209	IN UINTN Address\r
	210	);\r
	211	\r
0ff0e414 OM	212	VOID\r
	213	EFIAPI\r
	214	ArmInvalidateDataCacheEntryBySetWay (\r
	215	IN UINTN SetWayFormat\r
	216	);\r
	217	\r
	218	VOID\r
	219	EFIAPI\r
	220	ArmCleanDataCacheEntryBySetWay (\r
	221	IN UINTN SetWayFormat\r
	222	);\r
	223	\r
	224	VOID\r
	225	EFIAPI\r
	226	ArmCleanInvalidateDataCacheEntryBySetWay (\r
	227	IN UINTN SetWayFormat\r
	228	);\r
	229	\r
1e57a462	230	VOID\r
	231	EFIAPI\r
	232	ArmEnableDataCache (\r
	233	VOID\r
	234	);\r
	235	\r
	236	VOID\r
	237	EFIAPI\r
	238	ArmDisableDataCache (\r
	239	VOID\r
	240	);\r
	241	\r
	242	VOID\r
	243	EFIAPI\r
	244	ArmEnableInstructionCache (\r
	245	VOID\r
	246	);\r
	247	\r
	248	VOID\r
	249	EFIAPI\r
	250	ArmDisableInstructionCache (\r
	251	VOID\r
	252	);\r
3402aac7	253	\r
1e57a462	254	VOID\r
	255	EFIAPI\r
	256	ArmEnableMmu (\r
	257	VOID\r
	258	);\r
	259	\r
	260	VOID\r
	261	EFIAPI\r
	262	ArmDisableMmu (\r
	263	VOID\r
	264	);\r
	265	\r
0ff0e414 OM	266	VOID\r
	267	EFIAPI\r
	268	ArmEnableCachesAndMmu (\r
	269	VOID\r
	270	);\r
	271	\r
1e57a462	272	VOID\r
	273	EFIAPI\r
	274	ArmDisableCachesAndMmu (\r
	275	VOID\r
	276	);\r
	277	\r
1e57a462	278	VOID\r
	279	EFIAPI\r
	280	ArmEnableInterrupts (\r
	281	VOID\r
	282	);\r
	283	\r
	284	UINTN\r
	285	EFIAPI\r
	286	ArmDisableInterrupts (\r
	287	VOID\r
	288	);\r
47585ed5	289	\r
1e57a462	290	BOOLEAN\r
	291	EFIAPI\r
	292	ArmGetInterruptState (\r
	293	VOID\r
	294	);\r
	295	\r
0ff0e414 OM	296	VOID\r
	297	EFIAPI\r
	298	ArmEnableAsynchronousAbort (\r
	299	VOID\r
	300	);\r
	301	\r
47585ed5	302	UINTN\r
47585ed5	303	EFIAPI\r
0ff0e414	304	ArmDisableAsynchronousAbort (\r
47585ed5	305	VOID\r
	306	);\r
	307	\r
	308	VOID\r
	309	EFIAPI\r
	310	ArmEnableIrq (\r
	311	VOID\r
	312	);\r
	313	\r
0ff0e414 OM	314	UINTN\r
	315	EFIAPI\r
	316	ArmDisableIrq (\r
	317	VOID\r
	318	);\r
	319	\r
1e57a462	320	VOID\r
	321	EFIAPI\r
	322	ArmEnableFiq (\r
	323	VOID\r
	324	);\r
	325	\r
	326	UINTN\r
	327	EFIAPI\r
	328	ArmDisableFiq (\r
	329	VOID\r
	330	);\r
3402aac7	331	\r
1e57a462	332	BOOLEAN\r
	333	EFIAPI\r
	334	ArmGetFiqState (\r
	335	VOID\r
	336	);\r
	337	\r
8dd618d2 OM	338	/**\r
	339	* Invalidate Data and Instruction TLBs\r
	340	*/\r
1e57a462	341	VOID\r
	342	EFIAPI\r
	343	ArmInvalidateTlb (\r
	344	VOID\r
	345	);\r
3402aac7	346	\r
1e57a462	347	VOID\r
	348	EFIAPI\r
	349	ArmUpdateTranslationTableEntry (\r
	350	IN VOID *TranslationTableEntry,\r
	351	IN VOID *Mva\r
	352	);\r
3402aac7	353	\r
1e57a462	354	VOID\r
	355	EFIAPI\r
	356	ArmSetDomainAccessControl (\r
	357	IN UINT32 Domain\r
	358	);\r
	359	\r
	360	VOID\r
	361	EFIAPI\r
	362	ArmSetTTBR0 (\r
	363	IN VOID *TranslationTableBase\r
	364	);\r
	365	\r
ff1f27c0 EL	366	VOID\r
	367	EFIAPI\r
	368	ArmSetTTBCR (\r
	369	IN UINT32 Bits\r
	370	);\r
	371	\r
1e57a462	372	VOID *\r
	373	EFIAPI\r
	374	ArmGetTTBR0BaseAddress (\r
	375	VOID\r
	376	);\r
	377	\r
1e57a462	378	BOOLEAN\r
	379	EFIAPI\r
	380	ArmMmuEnabled (\r
	381	VOID\r
	382	);\r
3402aac7	383	\r
1e57a462	384	VOID\r
	385	EFIAPI\r
	386	ArmEnableBranchPrediction (\r
	387	VOID\r
	388	);\r
	389	\r
	390	VOID\r
	391	EFIAPI\r
	392	ArmDisableBranchPrediction (\r
	393	VOID\r
	394	);\r
	395	\r
	396	VOID\r
	397	EFIAPI\r
	398	ArmSetLowVectors (\r
	399	VOID\r
	400	);\r
	401	\r
	402	VOID\r
	403	EFIAPI\r
	404	ArmSetHighVectors (\r
	405	VOID\r
	406	);\r
	407	\r
	408	VOID\r
	409	EFIAPI\r
	410	ArmDataMemoryBarrier (\r
	411	VOID\r
	412	);\r
3402aac7	413	\r
1e57a462	414	VOID\r
1e57a462	415	EFIAPI\r
cf93a378	416	ArmDataSynchronizationBarrier (\r
1e57a462	417	VOID\r
1e57a462	418	);\r
3402aac7	419	\r
1e57a462	420	VOID\r
	421	EFIAPI\r
	422	ArmInstructionSynchronizationBarrier (\r
	423	VOID\r
	424	);\r
	425	\r
	426	VOID\r
	427	EFIAPI\r
	428	ArmWriteVBar (\r
4e57d6d7	429	IN UINTN VectorBase\r
1e57a462	430	);\r
1e57a462	431	\r
4e57d6d7	432	UINTN\r
1e57a462	433	EFIAPI\r
	434	ArmReadVBar (\r
	435	VOID\r
	436	);\r
	437	\r
	438	VOID\r
	439	EFIAPI\r
	440	ArmWriteAuxCr (\r
	441	IN UINT32 Bit\r
	442	);\r
	443	\r
	444	UINT32\r
	445	EFIAPI\r
	446	ArmReadAuxCr (\r
	447	VOID\r
	448	);\r
	449	\r
	450	VOID\r
	451	EFIAPI\r
	452	ArmSetAuxCrBit (\r
	453	IN UINT32 Bits\r
	454	);\r
	455	\r
	456	VOID\r
	457	EFIAPI\r
	458	ArmUnsetAuxCrBit (\r
	459	IN UINT32 Bits\r
	460	);\r
	461	\r
	462	VOID\r
	463	EFIAPI\r
	464	ArmCallSEV (\r
	465	VOID\r
	466	);\r
	467	\r
	468	VOID\r
	469	EFIAPI\r
	470	ArmCallWFE (\r
	471	VOID\r
	472	);\r
	473	\r
	474	VOID\r
	475	EFIAPI\r
	476	ArmCallWFI (\r
25402f5d	477	\r
1e57a462	478	VOID\r
	479	);\r
	480	\r
	481	UINTN\r
	482	EFIAPI\r
	483	ArmReadMpidr (\r
	484	VOID\r
	485	);\r
	486	\r
9401d6f4 OM	487	UINTN\r
	488	EFIAPI\r
	489	ArmReadMidr (\r
	490	VOID\r
	491	);\r
	492	\r
1e57a462	493	UINT32\r
	494	EFIAPI\r
	495	ArmReadCpacr (\r
	496	VOID\r
	497	);\r
	498	\r
	499	VOID\r
	500	EFIAPI\r
	501	ArmWriteCpacr (\r
	502	IN UINT32 Access\r
	503	);\r
	504	\r
	505	VOID\r
	506	EFIAPI\r
	507	ArmEnableVFP (\r
	508	VOID\r
	509	);\r
	510	\r
46d4d75c OM	511	/**\r
	512	Get the Secure Configuration Register value\r
	513	\r
	514	@return Value read from the Secure Configuration Register\r
	515	\r
	516	**/\r
1e57a462	517	UINT32\r
	518	EFIAPI\r
	519	ArmReadScr (\r
	520	VOID\r
	521	);\r
	522	\r
46d4d75c OM	523	/**\r
	524	Set the Secure Configuration Register\r
	525	\r
	526	@param Value Value to write to the Secure Configuration Register\r
	527	\r
	528	**/\r
1e57a462	529	VOID\r
	530	EFIAPI\r
	531	ArmWriteScr (\r
46d4d75c	532	IN UINT32 Value\r
1e57a462	533	);\r
	534	\r
	535	UINT32\r
	536	EFIAPI\r
	537	ArmReadMVBar (\r
	538	VOID\r
	539	);\r
	540	\r
	541	VOID\r
	542	EFIAPI\r
	543	ArmWriteMVBar (\r
	544	IN UINT32 VectorMonitorBase\r
	545	);\r
	546	\r
	547	UINT32\r
	548	EFIAPI\r
	549	ArmReadSctlr (\r
	550	VOID\r
	551	);\r
	552	\r
5ea2c2d3	553	UINTN\r
	554	EFIAPI\r
	555	ArmReadHVBar (\r
	556	VOID\r
	557	);\r
	558	\r
	559	VOID\r
	560	EFIAPI\r
	561	ArmWriteHVBar (\r
	562	IN UINTN HypModeVectorBase\r
	563	);\r
	564	\r
52d44f77 OM	565	\r
	566	//\r
	567	// Helper functions for accessing CPU ACTLR\r
	568	//\r
	569	\r
	570	UINTN\r
	571	EFIAPI\r
	572	ArmReadCpuActlr (\r
	573	VOID\r
	574	);\r
	575	\r
	576	VOID\r
	577	EFIAPI\r
	578	ArmWriteCpuActlr (\r
	579	IN UINTN Val\r
	580	);\r
	581	\r
	582	VOID\r
	583	EFIAPI\r
	584	ArmSetCpuActlrBit (\r
	585	IN UINTN Bits\r
	586	);\r
	587	\r
	588	VOID\r
	589	EFIAPI\r
	590	ArmUnsetCpuActlrBit (\r
	591	IN UINTN Bits\r
	592	);\r
	593	\r
734bd6cc AB	594	//\r
	595	// Accessors for the architected generic timer registers\r
	596	//\r
	597	\r
	598	#define ARM_ARCH_TIMER_ENABLE (1 << 0)\r
	599	#define ARM_ARCH_TIMER_IMASK (1 << 1)\r
	600	#define ARM_ARCH_TIMER_ISTATUS (1 << 2)\r
	601	\r
	602	UINTN\r
	603	EFIAPI\r
	604	ArmReadCntFrq (\r
	605	VOID\r
	606	);\r
	607	\r
	608	VOID\r
	609	EFIAPI\r
	610	ArmWriteCntFrq (\r
	611	UINTN FreqInHz\r
	612	);\r
	613	\r
	614	UINT64\r
	615	EFIAPI\r
	616	ArmReadCntPct (\r
	617	VOID\r
	618	);\r
	619	\r
	620	UINTN\r
	621	EFIAPI\r
	622	ArmReadCntkCtl (\r
	623	VOID\r
	624	);\r
	625	\r
	626	VOID\r
	627	EFIAPI\r
	628	ArmWriteCntkCtl (\r
	629	UINTN Val\r
	630	);\r
	631	\r
	632	UINTN\r
	633	EFIAPI\r
	634	ArmReadCntpTval (\r
	635	VOID\r
	636	);\r
	637	\r
	638	VOID\r
	639	EFIAPI\r
	640	ArmWriteCntpTval (\r
	641	UINTN Val\r
	642	);\r
	643	\r
	644	UINTN\r
	645	EFIAPI\r
	646	ArmReadCntpCtl (\r
	647	VOID\r
	648	);\r
	649	\r
	650	VOID\r
	651	EFIAPI\r
	652	ArmWriteCntpCtl (\r
	653	UINTN Val\r
	654	);\r
	655	\r
	656	UINTN\r
	657	EFIAPI\r
658	ArmReadCntvTval (\r
659	VOID\r
660	);\r
661	\r
662	VOID\r
663	EFIAPI\r
664	ArmWriteCntvTval (\r
665	UINTN Val\r
666	);\r
667	\r
668	UINTN\r
669	EFIAPI\r
670	ArmReadCntvCtl (\r
671	VOID\r
672	);\r
673	\r
674	VOID\r
675	EFIAPI\r
676	ArmWriteCntvCtl (\r
677	UINTN Val\r
678	);\r
679	\r
680	UINT64\r
681	EFIAPI\r
682	ArmReadCntvCt (\r
683	VOID\r
684	);\r
685	\r
686	UINT64\r
687	EFIAPI\r
688	ArmReadCntpCval (\r
689	VOID\r
690	);\r
691	\r
692	VOID\r
693	EFIAPI\r
694	ArmWriteCntpCval (\r
695	UINT64 Val\r
696	);\r
697	\r
698	UINT64\r
699	EFIAPI\r
700	ArmReadCntvCval (\r
701	VOID\r
702	);\r
703	\r
704	VOID\r
705	EFIAPI\r
706	ArmWriteCntvCval (\r
707	UINT64 Val\r
708	);\r
709	\r
710	UINT64\r
711	EFIAPI\r
712	ArmReadCntvOff (\r
713	VOID\r
714	);\r
715	\r
716	VOID\r
717	EFIAPI\r
718	ArmWriteCntvOff (\r
719	UINT64 Val\r
720	);\r
721	\r
1e57a462	722	#endif // __ARM_LIB__\r