[mirror_edk2.git] / OvmfPkg / PlatformPei / Platform.c

/**@file\r
  Platform PEI driver\r
\r
  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <PiPei.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Guid/MemoryTypeInformation.h>\r
#include <Ppi/MasterBootMode.h>\r
#include <IndustryStandard/Pci22.h>\r
#include <IndustryStandard/SmBios.h>\r
#include <OvmfPlatforms.h>\r
\r
#include "Platform.h"\r
#include "Cmos.h"\r
\r
EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
  { EfiACPIMemoryNVS,       0x004 },\r
  { EfiACPIReclaimMemory,   0x008 },\r
  { EfiReservedMemoryType,  0x004 },\r
  { EfiRuntimeServicesData, 0x024 },\r
  { EfiRuntimeServicesCode, 0x030 },\r
  { EfiBootServicesCode,    0x180 },\r
  { EfiBootServicesData,    0xF00 },\r
  { EfiMaxMemoryType,       0x000 }\r
};\r
\r
\r
EFI_PEI_PPI_DESCRIPTOR   mPpiBootMode[] = {\r
  {\r
    EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
    &gEfiPeiMasterBootModePpiGuid,\r
    NULL\r
  }\r
};\r
\r
\r
UINT16 mHostBridgeDevId;\r
\r
EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
\r
BOOLEAN mS3Supported = FALSE;\r
\r
\r
VOID\r
AddIoMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddReservedMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_RESERVED,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
AddIoMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
AddMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
\r
VOID\r
AddMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
\r
VOID\r
AddUntestedMemoryBaseSizeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  UINT64                      MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
      EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
      EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
      EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
\r
VOID\r
AddUntestedMemoryRangeHob (\r
  EFI_PHYSICAL_ADDRESS        MemoryBase,\r
  EFI_PHYSICAL_ADDRESS        MemoryLimit\r
  )\r
{\r
  AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
VOID\r
MemMapInitialization (\r
  VOID\r
  )\r
{\r
  //\r
  // Create Memory Type Information HOB\r
  //\r
  BuildGuidDataHob (\r
    &gEfiMemoryTypeInformationGuid,\r
    mDefaultMemoryTypeInformation,\r
    sizeof(mDefaultMemoryTypeInformation)\r
    );\r
\r
  //\r
  // Add PCI IO Port space available for PCI resource allocations.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_IO,\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
    0xC000,\r
    0x4000\r
    );\r
\r
  //\r
  // Video memory + Legacy BIOS region\r
  //\r
  AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
\r
  if (!mXen) {\r
    UINT32  TopOfLowRam;\r
    TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
\r
    //\r
    // address       purpose   size\r
    // ------------  --------  -------------------------\r
    // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
    // 0xFC000000    gap                           44 MB\r
    // 0xFEC00000    IO-APIC                        4 KB\r
    // 0xFEC01000    gap                         1020 KB\r
    // 0xFED00000    HPET                           1 KB\r
    // 0xFED00400    gap                          111 KB\r
    // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
    // 0xFED20000    gap                          896 KB\r
    // 0xFEE00000    LAPIC                          1 MB\r
    //\r
    AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
                         BASE_2GB : TopOfLowRam, 0xFC000000);\r
    AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
    AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
    if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
      AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
    }\r
    AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
  }\r
}\r
\r
\r
VOID\r
MiscInitialization (\r
  VOID\r
  )\r
{\r
  UINTN  PmCmd;\r
  UINTN  Pmba;\r
  UINTN  AcpiCtlReg;\r
  UINT8  AcpiEnBit;\r
\r
  //\r
  // Disable A20 Mask\r
  //\r
  IoOr8 (0x92, BIT1);\r
\r
  //\r
  // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
  // S3 resume as well, so we build it unconditionally.)\r
  //\r
  BuildCpuHob (mPhysMemAddressWidth, 16);\r
\r
  //\r
  // Determine platform type and save Host Bridge DID to PCD\r
  //\r
  switch (mHostBridgeDevId) {\r
    case INTEL_82441_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
      break;\r
    case INTEL_Q35_MCH_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
      break;\r
    default:\r
      DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
        __FUNCTION__, mHostBridgeDevId));\r
      ASSERT (FALSE);\r
      return;\r
  }\r
  PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
\r
  //\r
  // If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
  // has been configured (e.g., by Xen) and skip the setup here.\r
  // This matches the logic in AcpiTimerLibConstructor ().\r
  //\r
  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
    //\r
    // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
    // 1. set PMBA\r
    //\r
    PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
\r
    //\r
    // 2. set PCICMD/IOSE\r
    //\r
    PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
\r
    //\r
    // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
    //\r
    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
  }\r
\r
  if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    //\r
    // Set Root Complex Register Block BAR\r
    //\r
    PciWrite32 (\r
      POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
      ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
      );\r
  }\r
}\r
\r
\r
VOID\r
BootModeInitialization (\r
  VOID\r
  )\r
{\r
  EFI_STATUS    Status;\r
\r
  if (CmosRead8 (0xF) == 0xFE) {\r
    mBootMode = BOOT_ON_S3_RESUME;\r
  }\r
\r
  Status = PeiServicesSetBootMode (mBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  Status = PeiServicesInstallPpi (mPpiBootMode);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
VOID\r
ReserveEmuVariableNvStore (\r
  )\r
{\r
  EFI_PHYSICAL_ADDRESS VariableStore;\r
\r
  //\r
  // Allocate storage for NV variables early on so it will be\r
  // at a consistent address.  Since VM memory is preserved\r
  // across reboots, this allows the NV variable storage to survive\r
  // a VM reboot.\r
  //\r
  VariableStore =\r
    (EFI_PHYSICAL_ADDRESS)(UINTN)\r
      AllocateAlignedRuntimePages (\r
        EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
        PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
        );\r
  DEBUG ((EFI_D_INFO,\r
          "Reserved variable store memory: 0x%lX; size: %dkb\n",\r
          VariableStore,\r
          (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
        ));\r
  PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
}\r
\r
\r
VOID\r
DebugDumpCmos (\r
  VOID\r
  )\r
{\r
  UINT32 Loop;\r
\r
  DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
\r
  for (Loop = 0; Loop < 0x80; Loop++) {\r
    if ((Loop % 0x10) == 0) {\r
      DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
    }\r
    DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
    if ((Loop % 0x10) == 0xf) {\r
      DEBUG ((EFI_D_INFO, "\n"));\r
    }\r
  }\r
}\r
\r
\r
/**\r
  Set the SMBIOS entry point version for the generic SmbiosDxe driver.\r
**/\r
STATIC\r
VOID\r
SmbiosVersionInitialization (\r
  VOID\r
  )\r
{\r
  FIRMWARE_CONFIG_ITEM     Anchor;\r
  UINTN                    AnchorSize;\r
  SMBIOS_TABLE_ENTRY_POINT QemuAnchor;\r
  UINT16                   SmbiosVersion;\r
\r
  if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,\r
                      &AnchorSize)) ||\r
      AnchorSize != sizeof QemuAnchor) {\r
    return;\r
  }\r
\r
  QemuFwCfgSelectItem (Anchor);\r
  QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);\r
  if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 ||\r
      CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {\r
    return;\r
  }\r
\r
  SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 |\r
                           QemuAnchor.MinorVersion);\r
  DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,\r
    SmbiosVersion));\r
  PcdSet16 (PcdSmbiosVersion, SmbiosVersion);\r
}\r
\r
\r
/**\r
  Perform Platform PEI initialization.\r
\r
  @param  FileHandle      Handle of the file being invoked.\r
  @param  PeiServices     Describes the list of possible PEI Services.\r
\r
  @return EFI_SUCCESS     The PEIM initialized successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
InitializePlatform (\r
  IN       EFI_PEI_FILE_HANDLE  FileHandle,\r
  IN CONST EFI_PEI_SERVICES     **PeiServices\r
  )\r
{\r
  DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
\r
  DebugDumpCmos ();\r
\r
  XenDetect ();\r
\r
  if (QemuFwCfgS3Enabled ()) {\r
    DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
    mS3Supported = TRUE;\r
  }\r
\r
  BootModeInitialization ();\r
  AddressWidthInitialization ();\r
\r
  PublishPeiMemory ();\r
\r
  InitializeRamRegions ();\r
\r
  if (mXen) {\r
    DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
    InitializeXen ();\r
  }\r
\r
  //\r
  // Query Host Bridge DID\r
  //\r
  mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
\r
  if (mBootMode != BOOT_ON_S3_RESUME) {\r
    ReserveEmuVariableNvStore ();\r
\r
    PeiFvInitialization ();\r
\r
    MemMapInitialization ();\r
\r
    SmbiosVersionInitialization ();\r
  }\r
\r
  MiscInitialization ();\r
\r
  return EFI_SUCCESS;\r
}\r
Commit	Line	Data
49ba9447	1	/**@file\r
	2	Platform PEI driver\r
	3	\r
869b17cc	4	Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>\r
eec7d420	5	Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
eec7d420	6	\r
56d7640a	7	This program and the accompanying materials\r
49ba9447	8	are licensed and made available under the terms and conditions of the BSD License\r
	9	which accompanies this distribution. The full text of the license may be found at\r
	10	http://opensource.org/licenses/bsd-license.php\r
	11	\r
	12	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	\r
	15	**/\r
	16	\r
	17	//\r
	18	// The package level header files this module uses\r
	19	//\r
	20	#include <PiPei.h>\r
	21	\r
	22	//\r
	23	// The Library classes this module consumes\r
	24	//\r
	25	#include <Library/DebugLib.h>\r
	26	#include <Library/HobLib.h>\r
	27	#include <Library/IoLib.h>\r
77ba993c	28	#include <Library/MemoryAllocationLib.h>\r
77ba993c	29	#include <Library/PcdLib.h>\r
49ba9447	30	#include <Library/PciLib.h>\r
49ba9447	31	#include <Library/PeimEntryPoint.h>\r
9ed65b10	32	#include <Library/PeiServicesLib.h>\r
7cdba634	33	#include <Library/QemuFwCfgLib.h>\r
49ba9447	34	#include <Library/ResourcePublicationLib.h>\r
37baf06b	35	#include <Library/BaseMemoryLib.h>\r
49ba9447	36	#include <Guid/MemoryTypeInformation.h>\r
9ed65b10	37	#include <Ppi/MasterBootMode.h>\r
931a0c74	38	#include <IndustryStandard/Pci22.h>\r
37baf06b	39	#include <IndustryStandard/SmBios.h>\r
97380beb	40	#include <OvmfPlatforms.h>\r
49ba9447	41	\r
49ba9447	42	#include "Platform.h"\r
3ca15914	43	#include "Cmos.h"\r
49ba9447	44	\r
	45	EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
	46	{ EfiACPIMemoryNVS, 0x004 },\r
991d9563	47	{ EfiACPIReclaimMemory, 0x008 },\r
55cdb67a	48	{ EfiReservedMemoryType, 0x004 },\r
991d9563	49	{ EfiRuntimeServicesData, 0x024 },\r
	50	{ EfiRuntimeServicesCode, 0x030 },\r
	51	{ EfiBootServicesCode, 0x180 },\r
	52	{ EfiBootServicesData, 0xF00 },\r
49ba9447	53	{ EfiMaxMemoryType, 0x000 }\r
	54	};\r
	55	\r
	56	\r
9ed65b10	57	EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] = {\r
	58	{\r
	59	EFI_PEI_PPI_DESCRIPTOR_PPI \| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,\r
	60	&gEfiPeiMasterBootModePpiGuid,\r
	61	NULL\r
	62	}\r
	63	};\r
	64	\r
	65	\r
589756c7 PA	66	UINT16 mHostBridgeDevId;\r
589756c7 PA	67	\r
979420df JJ	68	EFI_BOOT_MODE mBootMode = BOOT_WITH_FULL_CONFIGURATION;\r
979420df JJ	69	\r
7cdba634 JJ	70	BOOLEAN mS3Supported = FALSE;\r
7cdba634 JJ	71	\r
979420df	72	\r
49ba9447	73	VOID\r
	74	AddIoMemoryBaseSizeHob (\r
	75	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	76	UINT64 MemorySize\r
	77	)\r
	78	{\r
991d9563	79	BuildResourceDescriptorHob (\r
991d9563	80	EFI_RESOURCE_MEMORY_MAPPED_IO,\r
49ba9447	81	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	82	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	83	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
991d9563	84	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447	85	MemoryBase,\r
	86	MemorySize\r
	87	);\r
	88	}\r
	89	\r
eec7d420	90	VOID\r
	91	AddReservedMemoryBaseSizeHob (\r
	92	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	93	UINT64 MemorySize\r
	94	)\r
	95	{\r
	96	BuildResourceDescriptorHob (\r
	97	EFI_RESOURCE_MEMORY_RESERVED,\r
	98	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	99	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	100	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	101	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
	102	MemoryBase,\r
	103	MemorySize\r
	104	);\r
	105	}\r
49ba9447	106	\r
	107	VOID\r
	108	AddIoMemoryRangeHob (\r
	109	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	110	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	111	)\r
	112	{\r
	113	AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	114	}\r
	115	\r
	116	\r
	117	VOID\r
	118	AddMemoryBaseSizeHob (\r
	119	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	120	UINT64 MemorySize\r
	121	)\r
	122	{\r
991d9563	123	BuildResourceDescriptorHob (\r
991d9563	124	EFI_RESOURCE_SYSTEM_MEMORY,\r
49ba9447	125	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	126	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	127	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	128	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	129	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	130	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE \|\r
991d9563	131	EFI_RESOURCE_ATTRIBUTE_TESTED,\r
49ba9447	132	MemoryBase,\r
	133	MemorySize\r
	134	);\r
	135	}\r
	136	\r
	137	\r
	138	VOID\r
	139	AddMemoryRangeHob (\r
	140	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	141	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	142	)\r
	143	{\r
	144	AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	145	}\r
	146	\r
c0e10976	147	\r
	148	VOID\r
	149	AddUntestedMemoryBaseSizeHob (\r
	150	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	151	UINT64 MemorySize\r
	152	)\r
	153	{\r
	154	BuildResourceDescriptorHob (\r
	155	EFI_RESOURCE_SYSTEM_MEMORY,\r
	156	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	157	EFI_RESOURCE_ATTRIBUTE_INITIALIZED \|\r
	158	EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE \|\r
	159	EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE \|\r
	160	EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE \|\r
	161	EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,\r
	162	MemoryBase,\r
	163	MemorySize\r
	164	);\r
	165	}\r
	166	\r
	167	\r
	168	VOID\r
	169	AddUntestedMemoryRangeHob (\r
	170	EFI_PHYSICAL_ADDRESS MemoryBase,\r
	171	EFI_PHYSICAL_ADDRESS MemoryLimit\r
	172	)\r
	173	{\r
	174	AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
	175	}\r
	176	\r
bb6a9a93	177	VOID\r
4b455f7b	178	MemMapInitialization (\r
bb6a9a93 WL	179	VOID\r
	180	)\r
	181	{\r
bb6a9a93 WL	182	//\r
	183	// Create Memory Type Information HOB\r
	184	//\r
	185	BuildGuidDataHob (\r
	186	&gEfiMemoryTypeInformationGuid,\r
	187	mDefaultMemoryTypeInformation,\r
	188	sizeof(mDefaultMemoryTypeInformation)\r
	189	);\r
	190	\r
	191	//\r
	192	// Add PCI IO Port space available for PCI resource allocations.\r
	193	//\r
	194	BuildResourceDescriptorHob (\r
	195	EFI_RESOURCE_IO,\r
	196	EFI_RESOURCE_ATTRIBUTE_PRESENT \|\r
	197	EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
	198	0xC000,\r
	199	0x4000\r
	200	);\r
	201	\r
	202	//\r
	203	// Video memory + Legacy BIOS region\r
	204	//\r
	205	AddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
	206	\r
4b455f7b JJ	207	if (!mXen) {\r
	208	UINT32 TopOfLowRam;\r
	209	TopOfLowRam = GetSystemMemorySizeBelow4gb ();\r
49ba9447	210	\r
4b455f7b JJ	211	//\r
	212	// address purpose size\r
	213	// ------------ -------- -------------------------\r
	214	// max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g)\r
	215	// 0xFC000000 gap 44 MB\r
	216	// 0xFEC00000 IO-APIC 4 KB\r
	217	// 0xFEC01000 gap 1020 KB\r
	218	// 0xFED00000 HPET 1 KB\r
90721ba5 PA	219	// 0xFED00400 gap 111 KB\r
	220	// 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB\r
	221	// 0xFED20000 gap 896 KB\r
4b455f7b JJ	222	// 0xFEE00000 LAPIC 1 MB\r
	223	//\r
	224	AddIoMemoryRangeHob (TopOfLowRam < BASE_2GB ?\r
	225	BASE_2GB : TopOfLowRam, 0xFC000000);\r
	226	AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
	227	AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
90721ba5 PA	228	if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
	229	AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
	230	}\r
4b455f7b	231	AddIoMemoryBaseSizeHob (PcdGet32(PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
4b455f7b	232	}\r
49ba9447	233	}\r
	234	\r
	235	\r
	236	VOID\r
	237	MiscInitialization (\r
0e20a186	238	VOID\r
49ba9447	239	)\r
49ba9447	240	{\r
97380beb GS	241	UINTN PmCmd;\r
97380beb GS	242	UINTN Pmba;\r
e2ab3f81 GS	243	UINTN AcpiCtlReg;\r
e2ab3f81 GS	244	UINT8 AcpiEnBit;\r
97380beb	245	\r
49ba9447	246	//\r
	247	// Disable A20 Mask\r
	248	//\r
55cdb67a	249	IoOr8 (0x92, BIT1);\r
49ba9447	250	\r
49ba9447	251	//\r
86a14b0a LE	252	// Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
	253	// of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
	254	// S3 resume as well, so we build it unconditionally.)\r
49ba9447	255	//\r
86a14b0a	256	BuildCpuHob (mPhysMemAddressWidth, 16);\r
c756b2ab	257	\r
97380beb	258	//\r
589756c7	259	// Determine platform type and save Host Bridge DID to PCD\r
97380beb	260	//\r
589756c7	261	switch (mHostBridgeDevId) {\r
97380beb	262	case INTEL_82441_DEVICE_ID:\r
e2ab3f81	263	PmCmd = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
da372167 LE	264	Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
	265	AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
	266	AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;\r
97380beb GS	267	break;\r
97380beb GS	268	case INTEL_Q35_MCH_DEVICE_ID:\r
e2ab3f81	269	PmCmd = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
bc9d05d6 LE	270	Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
	271	AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
	272	AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;\r
97380beb GS	273	break;\r
	274	default:\r
	275	DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
589756c7	276	__FUNCTION__, mHostBridgeDevId));\r
97380beb GS	277	ASSERT (FALSE);\r
	278	return;\r
	279	}\r
589756c7	280	PcdSet16 (PcdOvmfHostBridgePciDevId, mHostBridgeDevId);\r
97380beb	281	\r
0e20a186	282	//\r
e2ab3f81 GS	283	// If the appropriate IOspace enable bit is set, assume the ACPI PMBA\r
	284	// has been configured (e.g., by Xen) and skip the setup here.\r
	285	// This matches the logic in AcpiTimerLibConstructor ().\r
0e20a186	286	//\r
e2ab3f81	287	if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
eec7d420	288	//\r
e2ab3f81	289	// The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
931a0c74	290	// 1. set PMBA\r
eec7d420	291	//\r
97380beb	292	PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));\r
931a0c74	293	\r
	294	//\r
	295	// 2. set PCICMD/IOSE\r
	296	//\r
97380beb	297	PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
931a0c74	298	\r
931a0c74	299	//\r
e2ab3f81	300	// 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
931a0c74	301	//\r
e2ab3f81	302	PciOr8 (AcpiCtlReg, AcpiEnBit);\r
eec7d420	303	}\r
90721ba5 PA	304	\r
	305	if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
	306	//\r
	307	// Set Root Complex Register Block BAR\r
	308	//\r
	309	PciWrite32 (\r
	310	POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
	311	ICH9_ROOT_COMPLEX_BASE \| ICH9_RCBA_EN\r
	312	);\r
	313	}\r
49ba9447	314	}\r
	315	\r
	316	\r
9ed65b10	317	VOID\r
9ed65b10	318	BootModeInitialization (\r
8f5ca05b	319	VOID\r
9ed65b10	320	)\r
9ed65b10	321	{\r
8f5ca05b LE	322	EFI_STATUS Status;\r
	323	\r
	324	if (CmosRead8 (0xF) == 0xFE) {\r
979420df	325	mBootMode = BOOT_ON_S3_RESUME;\r
8f5ca05b	326	}\r
667bf1e4	327	\r
979420df	328	Status = PeiServicesSetBootMode (mBootMode);\r
667bf1e4	329	ASSERT_EFI_ERROR (Status);\r
	330	\r
	331	Status = PeiServicesInstallPpi (mPpiBootMode);\r
	332	ASSERT_EFI_ERROR (Status);\r
9ed65b10	333	}\r
	334	\r
	335	\r
77ba993c	336	VOID\r
	337	ReserveEmuVariableNvStore (\r
	338	)\r
	339	{\r
	340	EFI_PHYSICAL_ADDRESS VariableStore;\r
	341	\r
	342	//\r
	343	// Allocate storage for NV variables early on so it will be\r
	344	// at a consistent address. Since VM memory is preserved\r
	345	// across reboots, this allows the NV variable storage to survive\r
	346	// a VM reboot.\r
	347	//\r
	348	VariableStore =\r
	349	(EFI_PHYSICAL_ADDRESS)(UINTN)\r
9edb2933	350	AllocateAlignedRuntimePages (\r
cce992ac WL	351	EFI_SIZE_TO_PAGES (2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)),\r
cce992ac WL	352	PcdGet32 (PcdFlashNvStorageFtwSpareSize)\r
27f58ea1	353	);\r
77ba993c	354	DEBUG ((EFI_D_INFO,\r
	355	"Reserved variable store memory: 0x%lX; size: %dkb\n",\r
	356	VariableStore,\r
29a3f139	357	(2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize)) / 1024\r
77ba993c	358	));\r
	359	PcdSet64 (PcdEmuVariableNvStoreReserved, VariableStore);\r
	360	}\r
	361	\r
	362	\r
3ca15914	363	VOID\r
	364	DebugDumpCmos (\r
	365	VOID\r
	366	)\r
	367	{\r
6394c35a	368	UINT32 Loop;\r
3ca15914	369	\r
	370	DEBUG ((EFI_D_INFO, "CMOS:\n"));\r
	371	\r
	372	for (Loop = 0; Loop < 0x80; Loop++) {\r
	373	if ((Loop % 0x10) == 0) {\r
	374	DEBUG ((EFI_D_INFO, "%02x:", Loop));\r
	375	}\r
	376	DEBUG ((EFI_D_INFO, " %02x", CmosRead8 (Loop)));\r
	377	if ((Loop % 0x10) == 0xf) {\r
	378	DEBUG ((EFI_D_INFO, "\n"));\r
	379	}\r
	380	}\r
	381	}\r
	382	\r
	383	\r
37baf06b LE	384	/**\r
	385	Set the SMBIOS entry point version for the generic SmbiosDxe driver.\r
	386	**/\r
	387	STATIC\r
	388	VOID\r
	389	SmbiosVersionInitialization (\r
	390	VOID\r
	391	)\r
	392	{\r
	393	FIRMWARE_CONFIG_ITEM Anchor;\r
	394	UINTN AnchorSize;\r
	395	SMBIOS_TABLE_ENTRY_POINT QemuAnchor;\r
	396	UINT16 SmbiosVersion;\r
	397	\r
	398	if (RETURN_ERROR (QemuFwCfgFindFile ("etc/smbios/smbios-anchor", &Anchor,\r
	399	&AnchorSize)) \|\|\r
	400	AnchorSize != sizeof QemuAnchor) {\r
	401	return;\r
	402	}\r
	403	\r
	404	QemuFwCfgSelectItem (Anchor);\r
	405	QemuFwCfgReadBytes (AnchorSize, &QemuAnchor);\r
	406	if (CompareMem (QemuAnchor.AnchorString, "_SM_", 4) != 0 \|\|\r
	407	CompareMem (QemuAnchor.IntermediateAnchorString, "_DMI_", 5) != 0) {\r
	408	return;\r
	409	}\r
	410	\r
	411	SmbiosVersion = (UINT16)(QemuAnchor.MajorVersion << 8 \|\r
	412	QemuAnchor.MinorVersion);\r
	413	DEBUG ((EFI_D_INFO, "%a: SMBIOS version from QEMU: 0x%04x\n", __FUNCTION__,\r
	414	SmbiosVersion));\r
	415	PcdSet16 (PcdSmbiosVersion, SmbiosVersion);\r
	416	}\r
	417	\r
	418	\r
49ba9447	419	/**\r
	420	Perform Platform PEI initialization.\r
	421	\r
	422	@param FileHandle Handle of the file being invoked.\r
	423	@param PeiServices Describes the list of possible PEI Services.\r
	424	\r
	425	@return EFI_SUCCESS The PEIM initialized successfully.\r
	426	\r
	427	**/\r
	428	EFI_STATUS\r
	429	EFIAPI\r
	430	InitializePlatform (\r
	431	IN EFI_PEI_FILE_HANDLE FileHandle,\r
	432	IN CONST EFI_PEI_SERVICES **PeiServices\r
	433	)\r
	434	{\r
	435	DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
	436	\r
3ca15914	437	DebugDumpCmos ();\r
3ca15914	438	\r
b98b4941	439	XenDetect ();\r
c7ea55b9	440	\r
7cdba634 JJ	441	if (QemuFwCfgS3Enabled ()) {\r
	442	DEBUG ((EFI_D_INFO, "S3 support was detected on QEMU\n"));\r
	443	mS3Supported = TRUE;\r
	444	}\r
	445	\r
869b17cc	446	BootModeInitialization ();\r
bc89fe48	447	AddressWidthInitialization ();\r
869b17cc	448	\r
f76e9eba JJ	449	PublishPeiMemory ();\r
f76e9eba JJ	450	\r
2818c158	451	InitializeRamRegions ();\r
49ba9447	452	\r
b621bb0a	453	if (mXen) {\r
c7ea55b9	454	DEBUG ((EFI_D_INFO, "Xen was detected\n"));\r
b98b4941	455	InitializeXen ();\r
c7ea55b9	456	}\r
eec7d420	457	\r
589756c7 PA	458	//\r
	459	// Query Host Bridge DID\r
	460	//\r
	461	mHostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r
	462	\r
bd386eaf JJ	463	if (mBootMode != BOOT_ON_S3_RESUME) {\r
bd386eaf JJ	464	ReserveEmuVariableNvStore ();\r
77ba993c	465	\r
bd386eaf	466	PeiFvInitialization ();\r
49ba9447	467	\r
bd386eaf	468	MemMapInitialization ();\r
37baf06b LE	469	\r
37baf06b LE	470	SmbiosVersionInitialization ();\r
bd386eaf	471	}\r
49ba9447	472	\r
0e20a186	473	MiscInitialization ();\r
49ba9447	474	\r
	475	return EFI_SUCCESS;\r
	476	}\r