[mirror_edk2.git] / UefiCpuPkg / UefiCpuPkg.dec

## @file  UefiCpuPkg.dec\r
# This Package provides UEFI compatible CPU modules and libraries.\r
#\r
# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = UefiCpuPkg\r
  PACKAGE_UNI_FILE               = UefiCpuPkg.uni\r
  PACKAGE_GUID                   = 2171df9b-0d39-45aa-ac37-2de190010d23\r
  PACKAGE_VERSION                = 0.90\r
\r
[Includes]\r
  Include\r
\r
[LibraryClasses]\r
  ##  @libraryclass  Defines some routines that are generic for IA32 family CPU\r
  ##                 to be UEFI specification compliant.\r
  ##\r
  UefiCpuLib|Include/Library/UefiCpuLib.h\r
\r
  ##  @libraryclass  Defines some routines that are used to register/manage/program\r
  ##                 CPU features.\r
  ##\r
  RegisterCpuFeaturesLib|Include/Library/RegisterCpuFeaturesLib.h\r
\r
[LibraryClasses.IA32, LibraryClasses.X64]\r
  ##  @libraryclass  Provides functions to manage MTRR settings on IA32 and X64 CPUs.\r
  ##\r
  MtrrLib|Include/Library/MtrrLib.h\r
\r
  ##  @libraryclass  Provides functions to manage the Local APIC on IA32 and X64 CPUs.\r
  ##\r
  LocalApicLib|Include/Library/LocalApicLib.h\r
\r
  ##  @libraryclass  Provides platform specific initialization functions in the SEC phase.\r
  ##\r
  PlatformSecLib|Include/Library/PlatformSecLib.h\r
\r
  ##  @libraryclass  Public include file for the SMM CPU Platform Hook Library.\r
  ##\r
  SmmCpuPlatformHookLib|Include/Library/SmmCpuPlatformHookLib.h\r
\r
  ##  @libraryclass  Provides the CPU specific programming for PiSmmCpuDxeSmm module.\r
  ##\r
  SmmCpuFeaturesLib|Include/Library/SmmCpuFeaturesLib.h\r
\r
  ##  @libraryclass  Provides functions to support MP services on CpuMpPei and CpuDxe module.\r
  ##\r
  MpInitLib|Include/Library/MpInitLib.h\r
\r
  ##  @libraryclass  Provides function to support VMGEXIT processing.\r
  VmgExitLib|Include/Library/VmgExitLib.h\r
\r
  ##  @libraryclass  Provides function to get CPU cache information.\r
  CpuCacheInfoLib|Include/Library/CpuCacheInfoLib.h\r
\r
  ##  @libraryclass  Provides function for loading microcode.\r
  MicrocodeLib|Include/Library/MicrocodeLib.h\r
\r
[Guids]\r
  gUefiCpuPkgTokenSpaceGuid      = { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa, 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }}\r
  gMsegSmramGuid                 = { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1, 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }}\r
\r
  ## Include/Guid/CpuFeaturesSetDone.h\r
  gEdkiiCpuFeaturesSetDoneGuid   = { 0xa82485ce, 0xad6b, 0x4101, { 0x99, 0xd3, 0xe1, 0x35, 0x8c, 0x9e, 0x7e, 0x37 }}\r
\r
  ## Include/Guid/CpuFeaturesInitDone.h\r
  gEdkiiCpuFeaturesInitDoneGuid  = { 0xc77c3a41, 0x61ab, 0x4143, { 0x98, 0x3e, 0x33, 0x39, 0x28, 0x6, 0x28, 0xe5 }}\r
\r
  ## Include/Guid/MicrocodePatchHob.h\r
  gEdkiiMicrocodePatchHobGuid    = { 0xd178f11d, 0x8716, 0x418e, { 0xa1, 0x31, 0x96, 0x7d, 0x2a, 0xc4, 0x28, 0x43 }}\r
\r
[Protocols]\r
  ## Include/Protocol/SmmCpuService.h\r
  gEfiSmmCpuServiceProtocolGuid   = { 0x1d202cab, 0xc8ab, 0x4d5c, { 0x94, 0xf7, 0x3c, 0xfc, 0xc0, 0xd3, 0xd3, 0x35 }}\r
  gEdkiiSmmCpuRendezvousProtocolGuid = { 0xaa00d50b, 0x4911, 0x428f, { 0xb9, 0x1a, 0xa5, 0x9d, 0xdb, 0x13, 0xe2, 0x4c }}\r
\r
  ## Include/Protocol/SmMonitorInit.h\r
  gEfiSmMonitorInitProtocolGuid  = { 0x228f344d, 0xb3de, 0x43bb, { 0xa4, 0xd7, 0xea, 0x20, 0xb, 0x1b, 0x14, 0x82 }}\r
\r
#\r
# [Error.gUefiCpuPkgTokenSpaceGuid]\r
#   0x80000001 | Invalid value provided.\r
#\r
\r
[Ppis]\r
  gEdkiiPeiMpServices2PpiGuid =    { 0x5cb9cb3d, 0x31a4, 0x480c, { 0x94, 0x98, 0x29, 0xd2, 0x69, 0xba, 0xcf, 0xba}}\r
\r
  ## Include/Ppi/ShadowMicrocode.h\r
  gEdkiiPeiShadowMicrocodePpiGuid = { 0x430f6965, 0x9a69, 0x41c5, { 0x93, 0xed, 0x8b, 0xf0, 0x64, 0x35, 0xc1, 0xc6 }}\r
\r
  ## Include/Ppi/RepublishSecPpi.h\r
  gRepublishSecPpiPpiGuid   = { 0x27a71b1e, 0x73ee, 0x43d6, { 0xac, 0xe3, 0x52, 0x1a, 0x2d, 0xc5, 0xd0, 0x92 }}\r
\r
[PcdsFeatureFlag]\r
  ## Indicates if SMM Profile will be enabled.\r
  #  If enabled, instruction executions in and data accesses to memory outside of SMRAM will be logged.\r
  #  In X64 build, it could not be enabled when PcdCpuSmmRestrictedMemoryAccess is TRUE.\r
  #  In IA32 build, the page table memory is not marked as read-only when it is enabled.\r
  #  This PCD is only for validation purpose. It should be set to false in production.<BR><BR>\r
  #   TRUE  - SMM Profile will be enabled.<BR>\r
  #   FALSE - SMM Profile will be disabled.<BR>\r
  # @Prompt Enable SMM Profile.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE|BOOLEAN|0x32132109\r
\r
  ## Indicates if the SMM profile log buffer is a ring buffer.\r
  #  If disabled, no additional log can be done when the buffer is full.<BR><BR>\r
  #   TRUE  - the SMM profile log buffer is a ring buffer.<BR>\r
  #   FALSE - the SMM profile log buffer is a normal buffer.<BR>\r
  # @Prompt The SMM profile log buffer is a ring buffer.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileRingBuffer|FALSE|BOOLEAN|0x3213210a\r
\r
  ## Indicates if SMM Startup AP in a blocking fashion.\r
  #   TRUE  - SMM Startup AP in a blocking fashion.<BR>\r
  #   FALSE - SMM Startup AP in a non-blocking fashion.<BR>\r
  # @Prompt SMM Startup AP in a blocking fashion.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmBlockStartupThisAp|FALSE|BOOLEAN|0x32132108\r
\r
  ## Indicates if SMM Stack Guard will be enabled.\r
  #  If enabled, stack overflow in SMM can be caught, preventing chaotic consequences.<BR><BR>\r
  #   TRUE  - SMM Stack Guard will be enabled.<BR>\r
  #   FALSE - SMM Stack Guard will be disabled.<BR>\r
  # @Prompt Enable SMM Stack Guard.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|TRUE|BOOLEAN|0x1000001C\r
\r
  ## Indicates if BSP election in SMM will be enabled.\r
  #  If enabled, a BSP will be dynamically elected among all processors in each SMI.\r
  #  Otherwise, processor 0 is always as BSP in each SMI.<BR><BR>\r
  #   TRUE  - BSP election in SMM will be enabled.<BR>\r
  #   FALSE - BSP election in SMM will be disabled.<BR>\r
  # @Prompt Enable BSP election in SMM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE|BOOLEAN|0x32132106\r
\r
  ## Indicates if CPU SMM hot-plug will be enabled.<BR><BR>\r
  #   TRUE  - SMM CPU hot-plug will be enabled.<BR>\r
  #   FALSE - SMM CPU hot-plug will be disabled.<BR>\r
  # @Prompt SMM CPU hot-plug.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE|BOOLEAN|0x3213210C\r
\r
  ## Indicates if SMM Debug will be enabled.\r
  #  If enabled, hardware breakpoints in SMRAM can be set outside of SMM mode and take effect in SMM.<BR><BR>\r
  #   TRUE  - SMM Debug will be enabled.<BR>\r
  #   FALSE - SMM Debug will be disabled.<BR>\r
  # @Prompt Enable SMM Debug.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE|BOOLEAN|0x1000001B\r
\r
  ## Indicates if lock SMM Feature Control MSR.<BR><BR>\r
  #   TRUE  - SMM Feature Control MSR will be locked.<BR>\r
  #   FALSE - SMM Feature Control MSR will not be locked.<BR>\r
  # @Prompt Lock SMM Feature Control MSR.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x3213210B\r
\r
[PcdsFixedAtBuild]\r
  ## List of exception vectors which need switching stack.\r
  #  This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
  #  By default exception #DD(8), #PF(14) are supported.\r
  # @Prompt Specify exception vectors which need switching stack.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList|{0x08, 0x0E}|VOID*|0x30002000\r
\r
  ## Size of good stack for an exception.\r
  #  This PCD will only take into effect if PcdCpuStackGuard is enabled.\r
  # @Prompt Specify size of good stack of exception which need switching stack.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize|2048|UINT32|0x30002001\r
\r
  ## Count of pre allocated SMM MP tokens per chunk.\r
  # @Prompt Specify the count of pre allocated SMM MP tokens per chunk.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x30002002\r
\r
  ## Area of memory where the SEV-ES work area block lives.\r
  # @Prompt Configure the SEV-ES work area base\r
  gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005\r
\r
  ## Size of teh area of memory where the SEV-ES work area block lives.\r
  # @Prompt Configure the SEV-ES work area base\r
  gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006\r
\r
[PcdsFixedAtBuild, PcdsPatchableInModule]\r
  ## This value is the CPU Local APIC base address, which aligns the address on a 4-KByte boundary.\r
  # @Prompt Configure base address of CPU Local APIC\r
  # @Expression  0x80000001 | (gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress & 0xfff) == 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress|0xfee00000|UINT32|0x00000001\r
\r
  ## Specifies delay value in microseconds after sending out an INIT IPI.\r
  # @Prompt Configure delay value after send an INIT IPI\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10000|UINT32|0x30000002\r
\r
  ## This value specifies the Application Processor (AP) stack size, used for Mp Service, which must\r
  ## aligns the address on a 4-KByte boundary.\r
  # @Prompt Configure stack size for Application Processor (AP)\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x8000|UINT32|0x00000003\r
\r
  ## Specifies stack size in the temporary RAM. 0 means half of TemporaryRamSize.\r
  # @Prompt Stack size in the temporary RAM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x10001003\r
\r
  ## Specifies buffer size in bytes to save SMM profile data. The value should be a multiple of 4KB.\r
  # @Prompt SMM profile data buffer size.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileSize|0x200000|UINT32|0x32132107\r
\r
  ## Specifies stack size in bytes for each processor in SMM.\r
  # @Prompt Processor stack size in SMM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x2000|UINT32|0x32132105\r
\r
  ## Specifies shadow stack size in bytes for each processor in SMM.\r
  # @Prompt Processor shadow stack size in SMM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmShadowStackSize|0x2000|UINT32|0x3213210E\r
\r
  ## Indicates if SMM Code Access Check is enabled.\r
  #  If enabled, the SMM handler cannot execute the code outside SMM regions.\r
  #  This PCD is suggested to TRUE in production image.<BR><BR>\r
  #   TRUE  - SMM Code Access Check will be enabled.<BR>\r
  #   FALSE - SMM Code Access Check will be disabled.<BR>\r
  # @Prompt SMM Code Access Check.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x60000013\r
\r
  ## Specifies the number of variable MTRRs reserved for OS use. The default number of\r
  #  MTRRs reserved for OS use is 2.\r
  # @Prompt Number of reserved variable MTRRs.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x2|UINT32|0x00000015\r
\r
  ## Specifies buffer size in bytes for STM exception stack. The value should be a multiple of 4KB.\r
  # @Prompt STM exception stack size.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStmExceptionStackSize|0x1000|UINT32|0x32132111\r
\r
  ## Specifies buffer size in bytes of MSEG. The value should be a multiple of 4KB.\r
  # @Prompt MSEG size.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuMsegSize|0x200000|UINT32|0x32132112\r
\r
  ## Specifies the supported CPU features bit in array.\r
  # @Prompt Supported CPU features.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSupport|{0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}|VOID*|0x00000016\r
\r
  ## Specifies if CPU features will be initialized after SMM relocation.\r
  # @Prompt If CPU features will be initialized after SMM relocation.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitAfterSmmRelocation|FALSE|BOOLEAN|0x0000001C\r
\r
  ## Specifies if CPU features will be initialized during S3 resume.\r
  # @Prompt If CPU features will be initialized during S3 resume.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesInitOnS3Resume|FALSE|BOOLEAN|0x0000001D\r
\r
  ## Specifies CPUID Leaf 0x15 Time Stamp Counter and Nominal Core Crystal Clock Frequency.\r
  # TSC Frequency = ECX (core crystal clock frequency) * EBX/EAX.\r
  #   Intel Xeon Processor Scalable Family with CPUID signature 06_55H = 25000000 (25MHz)\r
  #   6th and 7th generation Intel Core processors and Intel Xeon W Processor Family = 24000000 (24MHz)\r
  #   Intel Atom processors based on Goldmont Microarchitecture with CPUID signature 06_5CH = 19200000 (19.2MHz)\r
  # @Prompt This PCD is the nominal frequency of the core crystal clock in Hz as is CPUID Leaf 0x15:ECX\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuCoreCrystalClockFrequency|24000000|UINT64|0x32132113\r
\r
  ## Specifies the periodic interval value in microseconds for the status check\r
  #  of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking\r
  #  mode in DXE phase.\r
  # @Prompt Periodic interval value in microseconds for AP status check in DXE.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds|100000|UINT32|0x0000001E\r
\r
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
  ## Specifies max supported number of Logical Processors.\r
  # @Prompt Configure max supported number of Logical Processors\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|64|UINT32|0x00000002\r
  ## Specifies timeout value in microseconds for the BSP to detect all APs for the first time.\r
  # @Prompt Timeout for the BSP to detect all APs for the first time.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000|UINT32|0x00000004\r
  ## Specifies the number of Logical Processors that are available in the\r
  #  preboot environment after platform reset, including BSP and APs. Possible\r
  #  values:<BR><BR>\r
  #  zero (default) - PcdCpuBootLogicalProcessorNumber is ignored, and\r
  #                   PcdCpuApInitTimeOutInMicroSeconds limits the initial AP\r
  #                   detection by the BSP.<BR>\r
  #  nonzero        - PcdCpuApInitTimeOutInMicroSeconds is ignored. The initial\r
  #                   AP detection finishes only when the detected CPU count\r
  #                   (BSP plus APs) reaches the value of\r
  #                   PcdCpuBootLogicalProcessorNumber, regardless of how long\r
  #                   that takes.<BR>\r
  # @Prompt Number of Logical Processors available after platform reset.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber|0|UINT32|0x00000008\r
  ## Specifies the base address of the first microcode Patch in the microcode Region.\r
  # @Prompt Microcode Region base address.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x00000005\r
  ## Specifies the size of the microcode Region.\r
  # @Prompt Microcode Region size.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x0|UINT64|0x00000006\r
  ## Specifies the AP wait loop state during POST phase.\r
  #  The value is defined as below.<BR><BR>\r
  #  1: Place AP in the Hlt-Loop state.<BR>\r
  #  2: Place AP in the Mwait-Loop state.<BR>\r
  #  3: Place AP in the Run-Loop state.<BR>\r
  # @Prompt The AP wait loop state.\r
  # @ValidRange  0x80000001 | 1 - 3\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|1|UINT8|0x60008006\r
  ## Specifies the AP target C-state for Mwait during POST phase.\r
  #  The default value 0 means C1 state.\r
  #  The value is defined as below.<BR><BR>\r
  # @Prompt The specified AP target C-state for Mwait.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0|UINT8|0x00000007\r
\r
  ## Specifies timeout value in microseconds for the BSP in SMM to wait for all APs to come into SMM.\r
  # @Prompt AP synchronization timeout value in SMM.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|1000000|UINT64|0x32132104\r
\r
  ## Indicates the CPU synchronization method used when processing an SMI.\r
  #   0x00  - Traditional CPU synchronization method.<BR>\r
  #   0x01  - Relaxed CPU synchronization method.<BR>\r
  # @Prompt SMM CPU Synchronization Method.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode|0x00|UINT8|0x60000014\r
\r
  ## Specifies the On-demand clock modulation duty cycle when ACPI feature is enabled.\r
  # @Prompt The encoded values for target duty cycle modulation.\r
  # @ValidRange  0x80000001 | 0 - 15\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle|0x0|UINT8|0x0000001A\r
\r
  ## Indicates if the current boot is a power-on reset.<BR><BR>\r
  #   TRUE  - Current boot is a power-on reset.<BR>\r
  #   FALSE - Current boot is not a power-on reset.<BR>\r
  # @Prompt Current boot is a power-on reset.\r
  gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset|FALSE|BOOLEAN|0x0000001B\r
\r
[PcdsFixedAtBuild.X64, PcdsPatchableInModule.X64, PcdsDynamic.X64, PcdsDynamicEx.X64]\r
  ## Indicate access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
  #  MMIO access is always allowed regardless of the value of this PCD.\r
  #  Loose of such restriction is only required by RAS components in X64 platforms.\r
  #  The PCD value is considered as constantly TRUE in IA32 platforms.\r
  #  When the PCD value is TRUE, page table is initialized to cover all memory spaces\r
  #  and the memory occupied by page table is protected by page table itself as read-only.\r
  #  In X64 build, it cannot be enabled at the same time with SMM profile feature (PcdCpuSmmProfileEnable).\r
  #  In X64 build, it could not be enabled also at the same time with heap guard feature for SMM\r
  #  (PcdHeapGuardPropertyMask in MdeModulePkg).\r
  #  In IA32 build, page table memory is not marked as read-only when either SMM profile feature (PcdCpuSmmProfileEnable)\r
  #  or heap guard feature for SMM (PcdHeapGuardPropertyMask in MdeModulePkg) is enabled.\r
  #   TRUE  - Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.<BR>\r
  #   FALSE - Access to any type of non-SMRAM memory after SmmReadyToLock is allowed.<BR>\r
  # @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F\r
\r
[PcdsDynamic, PcdsDynamicEx]\r
  ## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.\r
  # @Prompt The pointer to a CPU S3 data buffer.\r
  # @ValidList   0x80000001 | 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0x0|UINT64|0x60000010\r
\r
  ## Contains the pointer to a CPU Hot Plug Data structure if CPU hot-plug is supported.\r
  # @Prompt The pointer to CPU Hot Plug Data.\r
  # @ValidList   0x80000001 | 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0x0|UINT64|0x60000011\r
\r
  ## Indicates processor feature capabilities, each bit corresponding to a specific feature.\r
  # @Prompt Processor feature capabilities.\r
  # @ValidList   0x80000001 | 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesCapability|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000018\r
\r
  ## As input, specifies user's desired settings for enabling/disabling processor features.\r
  ## As output, specifies actual settings for processor features, each bit corresponding to a specific feature.\r
  # @Prompt As input, specifies user's desired processor feature settings. As output, specifies actual processor feature settings.\r
  # @ValidList   0x80000001 | 0\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuFeaturesSetting|{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}|VOID*|0x00000019\r
\r
  ## Contains the size of memory required when CPU processor trace is enabled.<BR><BR>\r
  #  Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
  #  This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
  #  Default value is 0x00 which means 4KB of memory is allocated if CPU processor trace is enabled.<BR>\r
  #  0x0  -  4K.<BR>\r
  #  0x1  -  8K.<BR>\r
  #  0x2  -  16K.<BR>\r
  #  0x3  -  32K.<BR>\r
  #  0x4  -  64K.<BR>\r
  #  0x5  -  128K.<BR>\r
  #  0x6  -  256K.<BR>\r
  #  0x7  -  512K.<BR>\r
  #  0x8  -  1M.<BR>\r
  #  0x9  -  2M.<BR>\r
  #  0xA  -  4M.<BR>\r
  #  0xB  -  8M.<BR>\r
  #  0xC  -  16M.<BR>\r
  #  0xD  -  32M.<BR>\r
  #  0xE  -  64M.<BR>\r
  #  0xF  -  128M.<BR>\r
  # @Prompt The memory size used for processor trace if processor trace is enabled.\r
  # @ValidRange  0x80000001 | 0 - 0xF\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceMemSize|0x0|UINT32|0x60000012\r
\r
  ## Contains the processor trace output scheme when CPU processor trace is enabled.<BR><BR>\r
  #  Processor trace is enabled through set BIT44(CPU_FEATURE_PROC_TRACE) in PcdCpuFeaturesSetting.<BR><BR>\r
  #  This PCD is ignored if CPU processor trace is disabled.<BR><BR>\r
  #  Default value is 0 which means single range output scheme will be used if CPU processor trace is enabled.<BR>\r
  #  0 - Single Range output scheme.<BR>\r
  #  1 - ToPA(Table of physical address) scheme.<BR>\r
  # @Prompt The processor trace output scheme used when processor trace is enabled.\r
  # @ValidRange  0x80000001 | 0 - 1\r
  gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x60000015\r
\r
  ## This dynamic PCD indicates whether SEV-ES is enabled\r
  #   TRUE  - SEV-ES is enabled\r
  #   FALSE - SEV-ES is not enabled\r
  # @Prompt SEV-ES Status\r
  gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016\r
\r
  ## This dynamic PCD contains the hypervisor features value obtained through the GHCB HYPERVISOR\r
  #  features VMGEXIT defined in the version 2 of GHCB spec.\r
  # @Prompt GHCB Hypervisor Features\r
  gUefiCpuPkgTokenSpaceGuid.PcdGhcbHypervisorFeatures|0x0|UINT64|0x60000018\r
\r
[UserExtensions.TianoCore."ExtraFiles"]\r
  UefiCpuPkgExtra.uni\r