+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = CTA9x4ArmVExpressLib\r
- FILE_GUID = aac05341-56df-4a77-b20f-f5daa456bd90\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformSecLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- ArmLib\r
- ArmTrustZoneLib\r
- ArmPlatformLib\r
- ArmPlatformSysConfigLib\r
- ArmPlatformSecExtraActionLib\r
- IoLib\r
- L2X0CacheLib\r
- PL301AxiLib\r
- PL341DmcLib\r
- PL35xSmcLib\r
- SerialPortLib\r
-\r
-[Sources.common]\r
- CTA9x4Sec.c\r
- CTA9x4Boot.asm | RVCT\r
- CTA9x4Boot.S | GCC\r
-\r
-[FeaturePcd]\r
- gArmPlatformTokenSpaceGuid.PcdStandalone\r
- gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdTrustzoneSupport\r
-\r
- gArmTokenSpaceGuid.PcdL2x0ControllerBase\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Drivers/PL35xSmc.h>\r
-#include <ArmPlatform.h>\r
-\r
-//\r
-// For each Chip Select: ChipSelect / SetCycle / SetOpMode\r
-//\r
-VersatileExpressSmcConfiguration:\r
- // NOR Flash 0\r
- .word PL350_SMC_DIRECT_CMD_ADDR_CS(0)\r
- .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
- .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV\r
-\r
- // NOR Flash 1\r
- .word PL350_SMC_DIRECT_CMD_ADDR_CS(4)\r
- .word PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) | PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) | PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) | PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) | PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
- .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT | PL350_SMC_SET_OPMODE_SET_ADV\r
-\r
- // SRAM\r
- .word PL350_SMC_DIRECT_CMD_ADDR_CS(2)\r
- .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
- .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_ADV\r
-\r
- // Usb/Eth/VRAM\r
- .word PL350_SMC_DIRECT_CMD_ADDR_CS(3)\r
- .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)\r
- .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
-\r
- // Memory Mapped Peripherals\r
- .word PL350_SMC_DIRECT_CMD_ADDR_CS(7)\r
- .word PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) | PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) | PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) | PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) | PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
- .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
-\r
- // VRAM\r
- .word PL350_SMC_DIRECT_CMD_ADDR_CS(1)\r
- .word 0x00049249\r
- .word PL350_SMC_SET_OPMODE_MEM_WIDTH_32 | PL350_SMC_SET_OPMODE_SET_RD_SYNC | PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
-VersatileExpressSmcConfigurationEnd:\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ASM_FUNC(ArmPlatformSecBootAction)\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_FUNC(ArmPlatformSecBootMemoryInit)\r
- mov r5, lr\r
-\r
- //\r
- // Initialize PL354 SMC\r
- //\r
- MOV32 (r1, ARM_VE_SMC_CTRL_BASE)\r
- MOV32 (r2, VersatileExpressSmcConfiguration)\r
- MOV32 (r3, VersatileExpressSmcConfigurationEnd)\r
- blx ASM_PFX(PL35xSmcInitialize)\r
-\r
- //\r
- // Page mode setup for VRAM\r
- //\r
- MOV32 (r2, VRAM_MOTHERBOARD_BASE)\r
-\r
- // Read current state\r
- ldr r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
-\r
- // Enable page mode\r
- ldr r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0]\r
- ldr r0, = 0x00900090\r
- str r0, [r2, #0]\r
-\r
- // Confirm page mode enabled\r
- ldr r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
-\r
- bx r5\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Base.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Drivers/PL35xSmc.h>\r
-#include <ArmPlatform.h>\r
-#include <AutoGen.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmPlatformSecBootAction\r
- EXPORT ArmPlatformSecBootMemoryInit\r
- IMPORT PL35xSmcInitialize\r
-\r
- PRESERVE8\r
- AREA CTA9x4BootMode, CODE, READONLY\r
-\r
-//\r
-// For each Chip Select: ChipSelect / SetCycle / SetOpMode\r
-//\r
-VersatileExpressSmcConfiguration\r
- // NOR Flash 0\r
- DCD PL350_SMC_DIRECT_CMD_ADDR_CS(0)\r
- DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
- DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV\r
-\r
- // NOR Flash 1\r
- DCD PL350_SMC_DIRECT_CMD_ADDR_CS(4)\r
- DCD PL350_SMC_SET_CYCLE_NAND_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_NAND_T_WC(0x3) :OR: PL350_SMC_SET_CYCLE_NAND_T_REA(0x1) :OR: PL350_SMC_SET_CYCLE_NAND_T_WP(0x7) :OR: PL350_SMC_SET_CYCLE_NAND_T_AR(0x1)\r
- DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL350_SMC_SET_OPMODE_SET_ADV\r
-\r
- // SRAM\r
- DCD PL350_SMC_DIRECT_CMD_ADDR_CS(2)\r
- DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x8) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
- DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_ADV\r
-\r
- // Usb/Eth/VRAM\r
- DCD PL350_SMC_DIRECT_CMD_ADDR_CS(3)\r
- DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0xA) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x3) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x6)\r
- DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
-\r
- // Memory Mapped Peripherals\r
- DCD PL350_SMC_DIRECT_CMD_ADDR_CS(7)\r
- DCD PL350_SMC_SET_CYCLE_SRAM_T_RC(0x6) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WC(0x5) :OR: PL350_SMC_SET_CYCLE_SRAM_T_CEOE(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_WP(0x2) :OR: PL350_SMC_SET_CYCLE_SRAM_T_PC(0x1) :OR: PL350_SMC_SET_CYCLE_SRAM_T_TR(0x1)\r
- DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
-\r
- // VRAM\r
- DCD PL350_SMC_DIRECT_CMD_ADDR_CS(1)\r
- DCD 0x00049249\r
- DCD PL350_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL350_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL350_SMC_SET_OPMODE_SET_WR_SYNC\r
-VersatileExpressSmcConfigurationEnd\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ArmPlatformSecBootAction\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ArmPlatformSecBootMemoryInit\r
- mov r5, lr\r
-\r
- //\r
- // Initialize PL354 SMC\r
- //\r
- mov32 r1, ARM_VE_SMC_CTRL_BASE\r
- ldr r2, =VersatileExpressSmcConfiguration\r
- ldr r3, =VersatileExpressSmcConfigurationEnd\r
- blx PL35xSmcInitialize\r
-\r
- //\r
- // Page mode setup for VRAM\r
- //\r
- mov32 r2, VRAM_MOTHERBOARD_BASE\r
-\r
- // Read current state\r
- ldr r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
-\r
- // Enable page mode\r
- ldr r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0]\r
- ldr r0, = 0x00900090\r
- str r0, [r2, #0]\r
-\r
- // Confirm page mode enabled\r
- ldr r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
- ldr r0, = 0x00000000\r
- str r0, [r2, #0]\r
- ldr r0, [r2, #0]\r
-\r
- bx r5\r
-\r
- END\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/ArmPlatformSysConfigLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/IoLib.h>\r
-#include <Library/PcdLib.h>\r
-#include <Library/SerialPortLib.h>\r
-\r
-#include <Drivers/ArmTrustzone.h>\r
-#include <Drivers/PL310L2Cache.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1)\r
-\r
-/**\r
- Initialize the Secure peripherals and memory regions\r
-\r
- If Trustzone is supported by your platform then this function makes the required initialization\r
- of the secure peripherals and memory regions.\r
-\r
-**/\r
-VOID\r
-ArmPlatformSecTrustzoneInit (\r
- IN UINTN MpId\r
- )\r
-{\r
- // Nothing to do\r
- if (!ArmPlatformIsPrimaryCore (MpId)) {\r
- return;\r
- }\r
-\r
- //\r
- // Setup TZ Protection Controller\r
- //\r
-\r
- if (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK) {\r
- ASSERT (PcdGetBool (PcdTrustzoneSupport) == TRUE);\r
- } else {\r
- ASSERT (PcdGetBool (PcdTrustzoneSupport) == FALSE);\r
- }\r
-\r
- // Set Non Secure access for all devices\r
- TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0, 0xFFFFFFFF);\r
- TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_1, 0xFFFFFFFF);\r
- TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2, 0xFFFFFFFF);\r
-\r
- // Remove Non secure access to secure devices\r
- TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0,\r
- ARM_VE_DECPROT_BIT_TZPC | ARM_VE_DECPROT_BIT_DMC_TZASC | ARM_VE_DECPROT_BIT_NMC_TZASC | ARM_VE_DECPROT_BIT_SMC_TZASC);\r
-\r
- TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2,\r
- ARM_VE_DECPROT_BIT_EXT_MAST_TZ | ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK);\r
-\r
- //\r
- // Setup TZ Address Space Controller for the SMC. Create 5 Non Secure regions (NOR0, NOR1, SRAM, SMC Peripheral regions)\r
- //\r
-\r
- // NOR Flash 0 non secure (BootMon)\r
- TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED,\r
- ARM_VE_SMB_NOR0_BASE,0,\r
- TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, 0);\r
-\r
- // NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin)\r
- if (PcdGetBool (PcdTrustzoneSupport) == TRUE) {\r
- //Note: Your OS Kernel must be aware of the secure regions before to enable this region\r
- TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,\r
- ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0,\r
- TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, 0);\r
- } else {\r
- TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,\r
- ARM_VE_SMB_NOR1_BASE,0,\r
- TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, 0);\r
- }\r
-\r
- // Base of SRAM. Only half of SRAM in Non Secure world\r
- // First half non secure (16MB) + Second Half secure (16MB) = 32MB of SRAM\r
- if (PcdGetBool (PcdTrustzoneSupport) == TRUE) {\r
- //Note: Your OS Kernel must be aware of the secure regions before to enable this region\r
- TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,\r
- ARM_VE_SMB_SRAM_BASE,0,\r
- TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW, 0);\r
- } else {\r
- TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,\r
- ARM_VE_SMB_SRAM_BASE,0,\r
- TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW, 0);\r
- }\r
-\r
- // Memory Mapped Peripherals. All in non secure world\r
- TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED,\r
- ARM_VE_SMB_PERIPH_BASE,0,\r
- TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW, 0);\r
-\r
- // MotherBoard Peripherals and On-chip peripherals.\r
- TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED,\r
- ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0,\r
- TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW, 0);\r
-}\r
-\r
-/**\r
- Initialize controllers that must setup at the early stage\r
-\r
- Some peripherals must be initialized in Secure World.\r
- For example, some L2x0 requires to be initialized in Secure World\r
-\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformSecInitialize (\r
- IN UINTN MpId\r
- )\r
-{\r
- UINT32 Value;\r
-\r
- // If the DRAM is remapped at 0x0 then we need to wake up the secondary cores from wfe\r
- // (waiting for the memory to be initialized) as the instruction is still in the remapped\r
- // flash region at 0x0 to jump in the C-code which lives in the NOR1 at 0x44000000 before\r
- // the region 0x0 is remapped as DRAM.\r
- if (!FeaturePcdGet (PcdNorFlashRemapping)) {\r
- if (!ArmPlatformIsPrimaryCore (MpId)) {\r
- // Replaced ArmCallWFE () in ArmPlatformPkg/Sec/SecEntryPoint.(S|asm)\r
- ArmCallWFE ();\r
- } else {\r
- // Wake up the secondary core from ArmCallWFE () in ArmPlatformPkg/Sec/SecEntryPoint.(S|asm)\r
- ArmCallSEV ();\r
- }\r
- }\r
-\r
- // If it is not the primary core then there is nothing to do\r
- if (!ArmPlatformIsPrimaryCore (MpId)) {\r
- return RETURN_SUCCESS;\r
- }\r
-\r
- // The L2x0 controller must be intialize in Secure World\r
- L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase),\r
- PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),\r
- PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),\r
- 0,~0, // Use default setting for the Auxiliary Control Register\r
- FALSE);\r
-\r
- // Initialize the System Configuration\r
- ArmPlatformSysConfigInitialize ();\r
-\r
- // If we skip the PEI Core we could want to initialize the DRAM in the SEC phase.\r
- // If we are in standalone, we need the initialization to copy the UEFI firmware into DRAM\r
- if ((FeaturePcdGet (PcdSystemMemoryInitializeInSec)) || (FeaturePcdGet (PcdStandalone) == FALSE)) {\r
- // If it is not a standalone build ensure the PcdSystemMemoryInitializeInSec has been set\r
- ASSERT(FeaturePcdGet (PcdSystemMemoryInitializeInSec) == TRUE);\r
-\r
- // Initialize system memory (DRAM)\r
- ArmPlatformInitializeSystemMemory ();\r
- }\r
-\r
- // Memory Map remapping\r
- if (FeaturePcdGet (PcdNorFlashRemapping)) {\r
- SerialPrint ("Secure ROM at 0x0\n\r");\r
- } else {\r
- Value = MmioRead32 (ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1\r
- // Remap the DRAM to 0x0\r
- MmioWrite32 (ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);\r
- }\r
-\r
- return RETURN_SUCCESS;\r
-}\r
+++ /dev/null
-//\r
-// Copyright (c) 2013-2014, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Chipset/AArch64.h>\r
-\r
-#ifndef __clang__\r
-// Register definitions used by GCC for GICv3 access.\r
-// These are defined by ARMCC, so keep them in the GCC specific code for now.\r
-#define ICC_SRE_EL2 S3_4_C12_C9_5\r
-#define ICC_SRE_EL3 S3_6_C12_C12_5\r
-#define ICC_CTLR_EL1 S3_0_C12_C12_4\r
-#define ICC_CTLR_EL3 S3_6_C12_C12_4\r
-#define ICC_PMR_EL1 S3_0_C4_C6_0\r
-#endif\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(InitializeGicV3)\r
-\r
-/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */\r
-ASM_PFX(InitializeGicV3):\r
- // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup\r
- // to allow Linux to use GICv3 if it chooses.\r
-\r
- // In order to setup NS side we need to enable it first.\r
- mrs x0, scr_el3\r
- orr x0, x0, #1\r
- msr scr_el3, x0\r
-\r
- // Enable SRE at EL3 and ICC_SRE_EL2 access\r
- mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE\r
- mrs x1, ICC_SRE_EL3\r
- orr x1, x1, x0\r
- msr ICC_SRE_EL3, x1\r
- isb\r
-\r
- // Enable SRE at EL2 and ICC_SRE_EL1 access..\r
- mrs x1, ICC_SRE_EL2\r
- orr x1, x1, x0\r
- msr ICC_SRE_EL2, x1\r
- isb\r
-\r
- // Configure CPU interface\r
- msr ICC_CTLR_EL3, xzr\r
- isb\r
- msr ICC_CTLR_EL1, xzr\r
- isb\r
-\r
- // The MemoryMap view and Register view may not be consistent, So Set PMR again.\r
- mov w1, #1 << 7 // allow NS access to GICC_PMR\r
- msr ICC_PMR_EL1, x1\r
- isb\r
-\r
- // Remove the SCR.NS bit\r
- mrs x0, scr_el3\r
- and x0, x0, #~SCR_NS\r
- msr scr_el3, x0\r
- ret\r
+++ /dev/null
-//\r
-// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Base.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <AutoGen.h>\r
-#include <ArmPlatform.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
-GCC_ASM_EXPORT(ArmSecMpCoreSecondariesWrite)\r
-GCC_ASM_EXPORT(ArmSecMpCoreSecondariesRead)\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootAction):\r
- ret\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootMemoryInit):\r
- // The SMC does not need to be initialized for RTSM\r
- ret\r
-\r
-/* Write the flag register used to start Secondary cores */\r
-ASM_PFX(ArmSecMpCoreSecondariesWrite):\r
- // Write to the CPU Mailbox\r
- ret\r
-\r
-/* Read the flag register used to start Secondary cores */\r
-ASM_PFX(ArmSecMpCoreSecondariesRead):\r
- // Return the value from the CPU Mailbox\r
- mov x0, #0\r
- ret\r
-\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Base.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <AutoGen.h>\r
-#include <ArmPlatform.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
-GCC_ASM_EXPORT(ArmSecMpCoreSecondariesWrite)\r
-GCC_ASM_EXPORT(ArmSecMpCoreSecondariesRead)\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootAction):\r
- ret\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the stack has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootMemoryInit):\r
- // The SMC does not need to be initialized for RTSM\r
- ret\r
-\r
-\r
-// NOTE:\r
-// The foundation model does not have the VE_SYS_REGS like all the other VE\r
-// platforms. We pick a spot in RAM that *should* be safe in the simple case\r
-// of no UEFI apps interfering (Only the Linux loader getting used). By the\r
-// time we come to load Linux we should have all the cores in a safe place.\r
-// The image expects to be loaded at 0xa0000000. We also place the mailboxes\r
-// here as it does not matter if we corrupt the image at this time.\r
-// NOTE also see: "ArmVExpressLibRTSM/RTSMFoundation.c"\r
-\r
-/* Write the flag register used to start Secondary cores */\r
-ASM_PFX(ArmSecMpCoreSecondariesWrite):\r
- ldr x1, =0xa0000000\r
- str w0, [x1]\r
- ret\r
-\r
-\r
-/* Read the flag register used to start Secondary cores */\r
-ASM_PFX(ArmSecMpCoreSecondariesRead):\r
- ldr x1, =0xa0000000\r
- ldr w0, [x1]\r
- ret\r
+++ /dev/null
-//\r
-// Copyright (c) 2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(InitializeGicV3)\r
-\r
-/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */\r
-ASM_PFX(InitializeGicV3):\r
- // GICv3 Initialization not Supported yet\r
- bx lr\r
+++ /dev/null
-//\r
-// Copyright (c) 2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT InitializeGicV3\r
-\r
- PRESERVE8\r
- AREA GicV3, CODE, READONLY\r
-\r
-/* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */\r
-InitializeGicV3 FUNCTION\r
- // GICv3 Initialization not Supported yet\r
- bx lr\r
- ENDFUNC\r
-\r
- END\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <AutoGen.h>\r
-#include <ArmPlatform.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootAction):\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootMemoryInit):\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
+++ /dev/null
-//\r
-// Copyright (c) 2011, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AsmMacroIoLib.h>\r
-#include <Base.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <AutoGen.h>\r
-#include <ArmPlatform.h>\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- EXPORT ArmPlatformSecBootAction\r
- EXPORT ArmPlatformSecBootMemoryInit\r
-\r
- PRESERVE8\r
- AREA RTSMVExpressBootMode, CODE, READONLY\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ArmPlatformSecBootAction\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ArmPlatformSecBootMemoryInit\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = RTSMArmVExpressSecLib\r
- FILE_GUID = 1fdaabb0-ab7d-480c-91ff-428dc1546f3a\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformSecLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- EmbeddedPkg/EmbeddedPkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- IoLib\r
- ArmLib\r
- SerialPortLib\r
-\r
-[Sources.common]\r
- RTSMSec.c\r
-\r
-[Sources.ARM]\r
- Arm/RTSMBoot.asm | RVCT\r
- Arm/RTSMBoot.S | GCC\r
- Arm/GicV3.asm | RVCT\r
- Arm/GicV3.S | GCC\r
-\r
-[Sources.AARCH64]\r
- AArch64/RTSMBoot.S\r
- AArch64/GicV3.S\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/IoLib.h>\r
-#include <Library/ArmGicLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#include <Drivers/PL310L2Cache.h>\r
-#include <Drivers/SP804Timer.h>\r
-\r
-#include <ArmPlatform.h>\r
-\r
-// Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet\r
-VOID\r
-InitializeGicV3 (\r
- VOID\r
- );\r
-\r
-/**\r
- Initialize the Secure peripherals and memory regions\r
-\r
- If Trustzone is supported by your platform then this function makes the required initialization\r
- of the secure peripherals and memory regions.\r
-\r
-**/\r
-VOID\r
-ArmPlatformSecTrustzoneInit (\r
- IN UINTN MpId\r
- )\r
-{\r
- // No TZPC or TZASC on RTSM to initialize\r
-}\r
-\r
-/**\r
- Initialize controllers that must setup at the early stage\r
-\r
- Some peripherals must be initialized in Secure World.\r
- For example, some L2x0 requires to be initialized in Secure World\r
-\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformSecInitialize (\r
- IN UINTN MpId\r
- )\r
-{\r
- UINT32 Identification;\r
-\r
- // If it is not the primary core then there is nothing to do\r
- if (!ArmPlatformIsPrimaryCore (MpId)) {\r
- return RETURN_SUCCESS;\r
- }\r
-\r
- // Configure periodic timer (TIMER0) for 1MHz operation\r
- MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);\r
- // Configure 1MHz clock\r
- MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);\r
- // Configure SP810 to use 1MHz clock and disable\r
- MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);\r
- // Configure SP810 to use 1MHz clock and disable\r
- MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);\r
-\r
- // Read the GIC Identification Register\r
- Identification = ArmGicGetInterfaceIdentification (PcdGet64 (PcdGicInterruptInterfaceBase));\r
-\r
- // Check if we are GICv3\r
- if (ARM_GIC_ICCIIDR_GET_ARCH_VERSION(Identification) >= 0x3) {\r
- InitializeGicV3 ();\r
- }\r
-\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/**\r
- Call before jumping to Normal World\r
-\r
- This function allows the firmware platform to do extra actions before\r
- jumping to the Normal World\r
-\r
-**/\r
-VOID\r
-ArmPlatformSecExtraAction (\r
- IN UINTN MpId,\r
- OUT UINTN* JumpAddress\r
- )\r
-{\r
- *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
-}\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef _ARMPLATFORMSECLIB_H_\r
-#define _ARMPLATFORMSECLIB_H_\r
-\r
-#define ARM_SEC_BOOT_MASK ~0\r
-#define ARM_SEC_COLD_BOOT (1 << 0)\r
-#define ARM_SEC_SECONDARY_COLD_BOOT (1 << 1)\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-VOID\r
-ArmPlatformSecBootMemoryInit (\r
- VOID\r
- );\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-VOID\r
-ArmPlatformSecBootAction (\r
- VOID\r
- );\r
-\r
-/**\r
- Initialize controllers that must setup at the early stage\r
-\r
- Some peripherals must be initialized in Secure World.\r
- For example: Some L2 controller, interconnect, clock, DMC, etc\r
-\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformSecInitialize (\r
- IN UINTN MpId\r
- );\r
-\r
-/**\r
- Call before jumping to Normal World\r
-\r
- This function allows the firmware platform to do extra actions before\r
- jumping to the Normal World\r
-\r
-**/\r
-VOID\r
-ArmPlatformSecExtraAction (\r
- IN UINTN MpId,\r
- OUT UINTN* JumpAddress\r
- );\r
-\r
-/**\r
- Initialize the Secure peripherals and memory regions\r
-\r
- If Trustzone is supported by your platform then this function makes the required initialization\r
- of the secure peripherals and memory regions.\r
-\r
-**/\r
-VOID\r
-ArmPlatformSecTrustzoneInit (\r
- IN UINTN MpId\r
- );\r
-\r
-#endif\r
+++ /dev/null
-//\r
-// Copyright (c) 2011 - 2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Base.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
-GCC_ASM_EXPORT(ArmSecMpCoreSecondariesWrite)\r
-GCC_ASM_EXPORT(ArmSecMpCoreSecondariesRead)\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootAction):\r
- ret\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootMemoryInit):\r
- // The SMC does not need to be initialized for RTSM\r
- ret\r
-\r
-/* Write the flag register used to start Secondary cores */\r
-ASM_PFX(ArmSecMpCoreSecondariesWrite):\r
- // Write to the CPU Mailbox\r
- ret\r
-\r
-\r
-/* Read the flag register used to start Secondary cores */\r
-ASM_PFX(ArmSecMpCoreSecondariesRead):\r
- // Return the value from the CPU Mailbox\r
- mov x0, #0\r
- ret\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Base.h>\r
-#include <AutoGen.h>\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootAction):\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ASM_PFX(ArmPlatformSecBootMemoryInit):\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <Base.h>\r
-#include <AutoGen.h>\r
-\r
- EXPORT ArmPlatformSecBootAction\r
- EXPORT ArmPlatformSecBootMemoryInit\r
-\r
- PRESERVE8\r
- AREA ArmPlatformSecLibBoot, CODE, READONLY\r
-\r
-/**\r
- Call at the beginning of the platform boot up\r
-\r
- This function allows the firmware platform to do extra actions at the early\r
- stage of the platform power up.\r
-\r
- Note: This function must be implemented in assembler as there is no stack set up yet\r
-\r
-**/\r
-ArmPlatformSecBootAction\r
- bx lr\r
-\r
-/**\r
- Initialize the memory where the initial stacks will reside\r
-\r
- This memory can contain the initial stacks (Secure and Secure Monitor stacks).\r
- In some platform, this region is already initialized and the implementation of this function can\r
- do nothing. This memory can also represent the Secure RAM.\r
- This function is called before the satck has been set up. Its implementation must ensure the stack\r
- pointer is not used (probably required to use assembly language)\r
-\r
-**/\r
-ArmPlatformSecBootMemoryInit\r
- // The SMC does not need to be initialized for RTSM\r
- bx lr\r
-\r
- END\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-/**\r
- Initialize the Secure peripherals and memory regions\r
-\r
- If Trustzone is supported by your platform then this function makes the required initialization\r
- of the secure peripherals and memory regions.\r
-\r
-**/\r
-VOID\r
-ArmPlatformSecTrustzoneInit (\r
- IN UINTN MpId\r
- )\r
-{\r
- // Secondary cores might have to set the Secure SGIs into the GICD_IGROUPR0\r
- if (!ArmPlatformIsPrimaryCore (MpId)) {\r
- return;\r
- }\r
-\r
- ASSERT(FALSE);\r
-}\r
-\r
-/**\r
- Initialize controllers that must setup at the early stage\r
-\r
- Some peripherals must be initialized in Secure World.\r
- For example, some L2x0 requires to be initialized in Secure World\r
-\r
-**/\r
-RETURN_STATUS\r
-ArmPlatformSecInitialize (\r
- IN UINTN MpId\r
- )\r
-{\r
- // If it is not the primary core then there is nothing to do\r
- if (!ArmPlatformIsPrimaryCore (MpId)) {\r
- return RETURN_SUCCESS;\r
- }\r
-\r
- // Do nothing yet\r
- return RETURN_SUCCESS;\r
-}\r
-\r
-/**\r
- Call before jumping to Normal World\r
-\r
- This function allows the firmware platform to do extra actions before\r
- jumping to the Normal World\r
-\r
-**/\r
-VOID\r
-ArmPlatformSecExtraAction (\r
- IN UINTN MpId,\r
- OUT UINTN* JumpAddress\r
- )\r
-{\r
- *JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
-}\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmPlatformLibSecNull\r
- FILE_GUID = a2cf63c6-d44f-4cd0-8af6-722a0138c021\r
- MODULE_TYPE = BASE\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = ArmPlatformSecLib\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- ArmLib\r
- DebugLib\r
-\r
-[Sources.common]\r
- ArmPlatformLibNullSec.c\r
-\r
-[Sources.ARM]\r
- Arm/ArmPlatformLibNullBoot.asm | RVCT\r
- Arm/ArmPlatformLibNullBoot.S | GCC\r
-\r
-[Sources.AARCH64]\r
- AArch64/ArmPlatformLibNullBoot.S\r
-\r
-\r
-[FixedPcd]\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
projects / mirror_edk2.git / commitdiff