# System Memory (DRAM): These PCDs define the region of in-built system memory\r
# Some platforms can get DRAM extensions, these additional regions will be declared\r
# to UEFI by ArmPLatformPlib \r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT32|0x00000029\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT32|0x0000002A\r
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029\r
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A\r
\r
# Use ClusterId + CoreId to identify the PrimaryCore\r
gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031\r
typedef struct {\r
EFI_PHYSICAL_ADDRESS PhysicalBase;\r
EFI_VIRTUAL_ADDRESS VirtualBase;\r
- UINTN Length;\r
+ UINT64 Length;\r
ARM_MEMORY_REGION_ATTRIBUTES Attributes;\r
} ARM_MEMORY_REGION_DESCRIPTOR;\r
\r
\r
// Try to put the kernel at the start of RAM so as to give it access to all memory.\r
// If that fails fall back to try loading it within LINUX_KERNEL_MAX_OFFSET of memory start.\r
- LinuxImage = PcdGet32(PcdSystemMemoryBase) + 0x80000;\r
+ LinuxImage = PcdGet64 (PcdSystemMemoryBase) + 0x80000;\r
Status = BdsLoadImage (LinuxKernelDevicePath, AllocateAddress, &LinuxImage, &LinuxImageSize);\r
if (EFI_ERROR(Status)) {\r
// Try again but give the loader more freedom of where to put the image.\r
/** @file\r
*\r
-* Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
* \r
* This program and the accompanying materials \r
* are licensed and made available under the terms and conditions of the BSD License \r
#define __BDSLINUXLOADER_H\r
\r
#define LINUX_UIMAGE_SIGNATURE 0x56190527\r
-#define LINUX_KERNEL_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxKernelMaxOffset))\r
-#define LINUX_ATAG_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxAtagMaxOffset))\r
-#define LINUX_FDT_MAX_OFFSET (PcdGet32(PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxFdtMaxOffset))\r
+#define LINUX_KERNEL_MAX_OFFSET (PcdGet64 (PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxKernelMaxOffset))\r
+#define LINUX_ATAG_MAX_OFFSET (PcdGet64 (PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxAtagMaxOffset))\r
+#define LINUX_FDT_MAX_OFFSET (PcdGet64 (PcdSystemMemoryBase) + PcdGet32(PcdArmLinuxFdtMaxOffset))\r
\r
// Additional size that could be used for FDT entries added by the UEFI OS Loader\r
// Estimation based on: EDID (300bytes) + bootargs (200bytes) + initrd region (20bytes)\r
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
\r
// DDR\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemorySize);\r
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r
VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
\r
// SMC CS7\r
#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB\r
\r
// DRAM\r
-#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase)\r
-#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize)\r
+#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)\r
+#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)\r
// Inside the DRAM we allocate a section for the VRAM (Video RAM)\r
#define LCD_VRAM_CORE_TILE_BASE 0x64000000\r
\r
#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB\r
\r
// DRAM\r
-#define ARM_VE_DRAM_BASE PcdGet32 (PcdSystemMemoryBase)\r
-#define ARM_VE_DRAM_SZ PcdGet32 (PcdSystemMemorySize)\r
+#define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase)\r
+#define ARM_VE_DRAM_SZ PcdGet64 (PcdSystemMemorySize)\r
\r
// This can be any value since we only support motherboard PL111\r
#define LCD_VRAM_CORE_TILE_BASE 0x00000000\r
\r
#ifndef ARM_BIGLITTLE_TC2\r
// Workaround for SRAM bug in RTSM\r
- if (PcdGet32 (PcdSystemMemoryBase) != 0x80000000) {\r
+ if (PcdGet64 (PcdSystemMemoryBase) != 0x80000000) {\r
VirtualMemoryTable[++Index].PhysicalBase = 0x80000000;\r
VirtualMemoryTable[Index].VirtualBase = 0x80000000;\r
- VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemoryBase) - 0x80000000;\r
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemoryBase) - 0x80000000;\r
VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
}\r
#endif\r
\r
// DDR\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].Length = PcdGet32 (PcdSystemMemorySize);\r
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r
VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
\r
// Detect if it is a 1GB or 2GB Test Chip\r
EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
EFI_RESOURCE_ATTRIBUTE_TESTED,\r
- PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize),\r
+ PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize),\r
SIZE_1GB\r
);\r
\r
// Map the additional 1GB into the MMU\r
- VirtualMemoryTable[++Index].PhysicalBase = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize);\r
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);\r
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize);\r
VirtualMemoryTable[Index].Length = SIZE_1GB;\r
VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
}\r
#include <Library/PcdLib.h>\r
#include <Library/DebugLib.h>\r
\r
-#define IS_XIP() (((UINT32)PcdGet32 (PcdFdBaseAddress) > (UINT32)(PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize))) || \\r
- ((PcdGet32 (PcdFdBaseAddress) + PcdGet32 (PcdFdSize)) < PcdGet32 (PcdSystemMemoryBase)))\r
+#define IS_XIP() (((UINT32)PcdGet32 (PcdFdBaseAddress) > (UINT32)(PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize))) || \\r
+ ((PcdGet32 (PcdFdBaseAddress) + PcdGet32 (PcdFdSize)) < PcdGet64 (PcdSystemMemoryBase)))\r
\r
// Declared by ArmPlatformPkg/PrePi Module\r
extern UINTN mGlobalVariableBase;\r
if (IS_XIP()) {\r
// In Case of XIP, we expect the Primary Stack at the top of the System Memory\r
// The size must be 64bit aligned to allow 64bit variable to be aligned\r
- GlobalVariableBase = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize) - ALIGN_VALUE(PcdGet32 (PcdPeiGlobalVariableSize),0x8);\r
+ GlobalVariableBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize) - ALIGN_VALUE(PcdGet32 (PcdPeiGlobalVariableSize),0x8);\r
} else {\r
GlobalVariableBase = mGlobalVariableBase;\r
}\r
if (IS_XIP()) {\r
// In Case of XIP, we expect the Primary Stack at the top of the System Memory\r
// The size must be 64bit aligned to allow 64bit variable to be aligned\r
- GlobalVariableBase = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize) - ALIGN_VALUE(PcdGet32 (PcdPeiGlobalVariableSize),0x8);\r
+ GlobalVariableBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize) - ALIGN_VALUE(PcdGet32 (PcdPeiGlobalVariableSize),0x8);\r
} else {\r
GlobalVariableBase = mGlobalVariableBase;\r
}\r
if (IS_XIP()) {\r
// In Case of XIP, we expect the Primary Stack at the top of the System Memory\r
// The size must be 64bit aligned to allow 64bit variable to be aligned\r
- GlobalVariableBase = PcdGet32 (PcdSystemMemoryBase) + PcdGet32 (PcdSystemMemorySize) - ALIGN_VALUE(PcdGet32 (PcdPeiGlobalVariableSize),0x8);\r
+ GlobalVariableBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize) - ALIGN_VALUE(PcdGet32 (PcdPeiGlobalVariableSize),0x8);\r
} else {\r
GlobalVariableBase = mGlobalVariableBase;\r
}\r
BOOLEAN Found;\r
\r
// Ensure PcdSystemMemorySize has been set\r
- ASSERT (PcdGet32 (PcdSystemMemorySize) != 0);\r
+ ASSERT (PcdGet64 (PcdSystemMemorySize) != 0);\r
\r
//\r
// Now, the permanent memory has been installed, we can call AllocatePages()\r
BuildResourceDescriptorHob (\r
EFI_RESOURCE_SYSTEM_MEMORY,\r
ResourceAttributes,\r
- PcdGet32 (PcdSystemMemoryBase),\r
- PcdGet32 (PcdSystemMemorySize)\r
+ PcdGet64 (PcdSystemMemoryBase),\r
+ PcdGet64 (PcdSystemMemorySize)\r
);\r
\r
- SystemMemoryTop = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdSystemMemoryBase) + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdSystemMemorySize);\r
+ SystemMemoryTop = (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemoryBase) + (EFI_PHYSICAL_ADDRESS)PcdGet64 (PcdSystemMemorySize);\r
FdTop = (EFI_PHYSICAL_ADDRESS)PcdGet32(PcdFdBaseAddress) + (EFI_PHYSICAL_ADDRESS)PcdGet32(PcdFdSize);\r
\r
// EDK2 does not have the concept of boot firmware copied into DRAM. To avoid the DXE\r
// core to overwrite this area we must mark the region with the attribute non-present\r
- if ((PcdGet32 (PcdFdBaseAddress) >= PcdGet32 (PcdSystemMemoryBase)) && (FdTop <= SystemMemoryTop)) {\r
+ if ((PcdGet32 (PcdFdBaseAddress) >= PcdGet64 (PcdSystemMemoryBase)) && (FdTop <= SystemMemoryTop)) {\r
Found = FALSE;\r
\r
// Search for System Memory Hob that contains the firmware\r
DEBUG ((EFI_D_ERROR, "Memory Init PEIM Loaded\n"));\r
\r
// Ensure PcdSystemMemorySize has been set\r
- ASSERT (FixedPcdGet32 (PcdSystemMemorySize) != 0);\r
+ ASSERT (FixedPcdGet64 (PcdSystemMemorySize) != 0);\r
\r
- SystemMemoryBase = (UINTN)FixedPcdGet32 (PcdSystemMemoryBase);\r
- SystemMemoryTop = SystemMemoryBase + (UINTN)FixedPcdGet32 (PcdSystemMemorySize);\r
+ SystemMemoryBase = (UINTN)FixedPcdGet64 (PcdSystemMemoryBase);\r
+ SystemMemoryTop = SystemMemoryBase + (UINTN)FixedPcdGet64 (PcdSystemMemorySize);\r
FdBase = (UINTN)PcdGet32 (PcdFdBaseAddress);\r
FdTop = FdBase + (UINTN)PcdGet32 (PcdFdSize);\r
\r
// at the top of the DRAM)\r
_SetupStackPosition:\r
// Compute Top of System Memory\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), x1)\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), x2)\r
+ LoadConstantToReg (FixedPcdGet64 (PcdSystemMemoryBase), x1)\r
+ LoadConstantToReg (FixedPcdGet64 (PcdSystemMemorySize), x2)\r
sub x2, x2, #1\r
add x1, x1, x2 // x1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
\r
// at the top of the DRAM)\r
_SetupStackPosition:\r
// Compute Top of System Memory\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r
+ LoadConstantToReg (FixedPcdGet64 (PcdSystemMemoryBase), r1)\r
+ LoadConstantToReg (FixedPcdGet64 (PcdSystemMemorySize), r2)\r
sub r2, r2, #1\r
add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
\r
// at the top of the DRAM)\r
_SetupStackPosition\r
// Compute Top of System Memory\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r
+ LoadConstantToReg (FixedPcdGet64 (PcdSystemMemoryBase), r1)\r
+ LoadConstantToReg (FixedPcdGet64 (PcdSystemMemorySize), r2)\r
sub r2, r2, #1\r
add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
\r
#include "PrePi.h"\r
#include "LzmaDecompress.h"\r
\r
-#define IS_XIP() (((UINT32)FixedPcdGet32 (PcdFdBaseAddress) > (UINT32)(FixedPcdGet32 (PcdSystemMemoryBase) + FixedPcdGet32 (PcdSystemMemorySize))) || \\r
- ((FixedPcdGet32 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet32 (PcdSystemMemoryBase)))\r
+#define IS_XIP() (((UINT32)FixedPcdGet32 (PcdFdBaseAddress) > (UINT32)(FixedPcdGet64 (PcdSystemMemoryBase) + FixedPcdGet32 (PcdSystemMemorySize))) || \\r
+ ((FixedPcdGet32 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) < FixedPcdGet64 (PcdSystemMemoryBase)))\r
\r
// Not used when PrePi in run in XIP mode\r
UINTN mGlobalVariableBase = 0;\r
\r
// If ensure the FD is either part of the System Memory or totally outside of the System Memory (XIP)\r
ASSERT (IS_XIP() || \r
- ((FixedPcdGet32 (PcdFdBaseAddress) >= FixedPcdGet32 (PcdSystemMemoryBase)) &&\r
- ((UINT32)(FixedPcdGet32 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT32)(FixedPcdGet32 (PcdSystemMemoryBase) + FixedPcdGet32 (PcdSystemMemorySize)))));\r
+ ((FixedPcdGet32 (PcdFdBaseAddress) >= FixedPcdGet64 (PcdSystemMemoryBase)) &&\r
+ ((UINT32)(FixedPcdGet32 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSize)) <= (UINT32)(FixedPcdGet64 (PcdSystemMemoryBase) + FixedPcdGet64 (PcdSystemMemorySize)))));\r
\r
// Initialize the architecture specific bits\r
ArchInitialize ();\r
}\r
\r
// ReMap (Either NOR Flash or DRAM)\r
- VirtualMemoryTable[Index].PhysicalBase = PcdGet32(PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].VirtualBase = PcdGet32(PcdSystemMemoryBase);\r
- VirtualMemoryTable[Index].Length = PcdGet32(PcdSystemMemorySize);\r
+ VirtualMemoryTable[Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase);\r
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize);\r
VirtualMemoryTable[Index].Attributes = CacheAttributes;\r
\r
// SOC Registers. L3 interconnects\r