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aspeed: Create SRAM name from first CPU index
[mirror_qemu.git] / hw / arm / aspeed.c
CommitLineData
327d8e4e
AJ		 1/*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12#include "qemu/osdep.h"
da34e65c 13#include "qapi/error.h"
12ec8bd5 14#include "hw/arm/boot.h"
fca9ca1b 15#include "hw/arm/aspeed.h"
00442402 16#include "hw/arm/aspeed_soc.h"
3ec75e39 17#include "hw/i2c/i2c_mux_pca954x.h"
93198b6c 18#include "hw/i2c/smbus_eeprom.h"
044475f3 19#include "hw/misc/pca9552.h"
5e9ae4b1 20#include "hw/sensor/tmp105.h"
7cfbde5e 21#include "hw/misc/led.h"
a27bd6c7 22#include "hw/qdev-properties.h"
e1ad9bc4 23#include "sysemu/block-backend.h"
fa699e80 24#include "sysemu/reset.h"
d769a1da
CLG		 25#include "hw/loader.h"
26#include "qemu/error-report.h"
a9df9622 27#include "qemu/units.h"
66c895b8 28#include "hw/qdev-clock.h"
327d8e4e 29
74fb1f38 30static struct arm_boot_info aspeed_board_binfo = {
b033271f 31 .board_id = -1, /* device-tree-only board */
327d8e4e
AJ		 32};
33
612b219a 34struct AspeedMachineState {
888b2b03
PMD		 35 /* Private */
36 MachineState parent_obj;
37 /* Public */
38
ff90606f 39 AspeedSoCState soc;
ad1a9782 40 MemoryRegion ram_container;
ebe31c0a 41 MemoryRegion max_ram;
888b2b03 42 bool mmio_exec;
9820e52f
CLG		 43 char *fmc_model;
44 char *spi_model;
ea066d39 45};
327d8e4e 46
ef17f836 47/* Palmetto hardware value: 0x120CE416 */
8da33ef7
CLG		 48#define PALMETTO_BMC_HW_STRAP1 ( \
49 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
50 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
51 SCU_AST2400_HW_STRAP_ACPI_DIS | \
52 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
53 SCU_HW_STRAP_VGA_CLASS_CODE | \
54 SCU_HW_STRAP_LPC_RESET_PIN | \
55 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
56 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
57 SCU_HW_STRAP_SPI_WIDTH | \
58 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
59 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
60
40a38df5
ES		 61/* TODO: Find the actual hardware value */
62#define SUPERMICROX11_BMC_HW_STRAP1 ( \
63 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
64 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
65 SCU_AST2400_HW_STRAP_ACPI_DIS | \
66 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
67 SCU_HW_STRAP_VGA_CLASS_CODE | \
68 SCU_HW_STRAP_LPC_RESET_PIN | \
69 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
70 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
71 SCU_HW_STRAP_SPI_WIDTH | \
72 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
73 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
74
ef17f836 75/* AST2500 evb hardware value: 0xF100C2E6 */
9a7c1750
CLG		 76#define AST2500_EVB_HW_STRAP1 (( \
77 AST2500_HW_STRAP1_DEFAULTS | \
78 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
79 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
80 SCU_AST2500_HW_STRAP_UART_DEBUG | \
81 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
82 SCU_HW_STRAP_MAC1_RGMII | \
83 SCU_HW_STRAP_MAC0_RGMII) & \
84 ~SCU_HW_STRAP_2ND_BOOT_WDT)
85
ef17f836
CLG		 86/* Romulus hardware value: 0xF10AD206 */
87#define ROMULUS_BMC_HW_STRAP1 ( \
88 AST2500_HW_STRAP1_DEFAULTS | \
89 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
90 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
91 SCU_AST2500_HW_STRAP_UART_DEBUG | \
92 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
93 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
94 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
95
143b040f
PW		 96/* Sonorapass hardware value: 0xF100D216 */
97#define SONORAPASS_BMC_HW_STRAP1 ( \
98 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
99 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
100 SCU_AST2500_HW_STRAP_UART_DEBUG | \
101 SCU_AST2500_HW_STRAP_RESERVED28 | \
102 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
103 SCU_HW_STRAP_VGA_CLASS_CODE | \
104 SCU_HW_STRAP_LPC_RESET_PIN | \
105 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
106 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
107 SCU_HW_STRAP_VGA_BIOS_ROM | \
108 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
109 SCU_AST2500_HW_STRAP_RESERVED1)
110
95f068c8
JW		 111#define G220A_BMC_HW_STRAP1 ( \
112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
114 SCU_AST2500_HW_STRAP_UART_DEBUG | \
115 SCU_AST2500_HW_STRAP_RESERVED28 | \
116 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
117 SCU_HW_STRAP_2ND_BOOT_WDT | \
118 SCU_HW_STRAP_VGA_CLASS_CODE | \
119 SCU_HW_STRAP_LPC_RESET_PIN | \
120 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
121 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
122 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
123 SCU_AST2500_HW_STRAP_RESERVED1)
124
82b6a3f6
JW		 125/* FP5280G2 hardware value: 0XF100D286 */
126#define FP5280G2_BMC_HW_STRAP1 ( \
127 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
128 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
129 SCU_AST2500_HW_STRAP_UART_DEBUG | \
130 SCU_AST2500_HW_STRAP_RESERVED28 | \
131 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
132 SCU_HW_STRAP_VGA_CLASS_CODE | \
133 SCU_HW_STRAP_LPC_RESET_PIN | \
134 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
135 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
136 SCU_HW_STRAP_MAC1_RGMII | \
137 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
138 SCU_AST2500_HW_STRAP_RESERVED1)
139
62c2c2eb
CLG		 140/* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
141#define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
142
9cccb912
PV		 143/* Quanta-Q71l hardware value */
144#define QUANTA_Q71L_BMC_HW_STRAP1 ( \
145 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
146 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
147 SCU_AST2400_HW_STRAP_ACPI_DIS | \
148 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
149 SCU_HW_STRAP_VGA_CLASS_CODE | \
150 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
151 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
152 SCU_HW_STRAP_SPI_WIDTH | \
153 SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
154 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
155
ccc2c418
CLG		 156/* AST2600 evb hardware value */
157#define AST2600_EVB_HW_STRAP1 0x000000C0
158#define AST2600_EVB_HW_STRAP2 0x00000003
159
63ceb818
CLG		 160/* Tacoma hardware value */
161#define TACOMA_BMC_HW_STRAP1 0x00000000
7582591a 162#define TACOMA_BMC_HW_STRAP2 0x00000040
63ceb818 163
58e52bdb 164/* Rainier hardware value: (QEMU prototype) */
b6d1df64
JS		 165#define RAINIER_BMC_HW_STRAP1 0x00422016
166#define RAINIER_BMC_HW_STRAP2 0x80000848
58e52bdb 167
febbe308
PD		 168/* Fuji hardware value */
169#define FUJI_BMC_HW_STRAP1 0x00000000
170#define FUJI_BMC_HW_STRAP2 0x00000000
171
a20c54b1
PW		 172/* Bletchley hardware value */
173/* TODO: Leave same as EVB for now. */
174#define BLETCHLEY_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
175#define BLETCHLEY_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
176
fb6b3c8d
JHY		 177/* Qualcomm DC-SCM hardware value */
178#define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
179#define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
180
9bb6d140
JS		 181#define AST_SMP_MAILBOX_BASE 0x1e6e2180
182#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
183#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
184#define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
185#define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
186#define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
187#define AST_SMP_MBOX_GOSIGN 0xabbaab00
188
189static void aspeed_write_smpboot(ARMCPU *cpu,
190 const struct arm_boot_info *info)
191{
192 static const uint32_t poll_mailbox_ready[] = {
193 /*
194 * r2 = per-cpu go sign value
195 * r1 = AST_SMP_MBOX_FIELD_ENTRY
196 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
197 */
198 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
199 0xe21000ff, /* ands r0, r0, #255 */
200 0xe59f201c, /* ldr r2, [pc, #28] */
201 0xe1822000, /* orr r2, r2, r0 */
202
203 0xe59f1018, /* ldr r1, [pc, #24] */
204 0xe59f0018, /* ldr r0, [pc, #24] */
205
206 0xe320f002, /* wfe */
207 0xe5904000, /* ldr r4, [r0] */
208 0xe1520004, /* cmp r2, r4 */
209 0x1afffffb, /* bne <wfe> */
210 0xe591f000, /* ldr pc, [r1] */
211 AST_SMP_MBOX_GOSIGN,
212 AST_SMP_MBOX_FIELD_ENTRY,
213 AST_SMP_MBOX_FIELD_GOSIGN,
214 };
215
216 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
217 sizeof(poll_mailbox_ready),
218 info->smp_loader_start);
219}
220
221static void aspeed_reset_secondary(ARMCPU *cpu,
222 const struct arm_boot_info *info)
223{
224 AddressSpace *as = arm_boot_address_space(cpu, info);
225 CPUState *cs = CPU(cpu);
226
227 /* info->smp_bootreg_addr */
228 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
229 MEMTXATTRS_UNSPECIFIED, NULL);
230 cpu_set_pc(cs, info->smp_loader_start);
231}
232
d769a1da
CLG		 233#define FIRMWARE_ADDR 0x0
234
235static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
236 Error **errp)
237{
238 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
05e6e40a 239 g_autofree void *storage = NULL;
0c7209be
CLG		 240 int64_t size;
241
242 /* The block backend size should have already been 'validated' by
243 * the creation of the m25p80 object.
244 */
245 size = blk_getlength(blk);
246 if (size <= 0) {
247 error_setg(errp, "failed to get flash size");
248 return;
249 }
d769a1da 250
0c7209be
CLG		 251 if (rom_size > size) {
252 rom_size = size;
d769a1da
CLG		 253 }
254
05e6e40a 255 storage = g_malloc0(rom_size);
a9262f55 256 if (blk_pread(blk, 0, rom_size, storage, 0) < 0) {
d769a1da
CLG		 257 error_setg(errp, "failed to read the initial flash content");
258 return;
259 }
260
261 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
d769a1da
CLG		 262}
263
9bd4ac61
CLG		 264static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
265 unsigned int count, int unit0)
e1ad9bc4 266{
179b2058
PW		 267 int i;
268
269 if (!flashtype) {
270 return;
271 }
e1ad9bc4 272
9bd4ac61 273 for (i = 0; i < count; ++i) {
8ec239f2 274 DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
e1ad9bc4 275 qemu_irq cs_line;
a7d78bef 276 DeviceState *dev;
e1ad9bc4 277
a7d78bef 278 dev = qdev_new(flashtype);
e1ad9bc4 279 if (dinfo) {
a7d78bef 280 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo));
e1ad9bc4 281 }
a7d78bef 282 qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal);
e1ad9bc4 283
a7d78bef 284 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
e1ad9bc4
CLG		 285 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
286 }
287}
288
a29e3e12
AJ		 289static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
290{
291 DeviceState *card;
292
756f739b
PMD		 293 if (!dinfo) {
294 return;
a29e3e12 295 }
756f739b
PMD		 296 card = qdev_new(TYPE_SD_CARD);
297 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
298 &error_fatal);
3e80f690
MA		 299 qdev_realize_and_unref(card,
300 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
301 &error_fatal);
a29e3e12
AJ		 302}
303
baa4732b 304static void aspeed_machine_init(MachineState *machine)
327d8e4e 305{
888b2b03 306 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
baa4732b 307 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
b033271f 308 AspeedSoCClass *sc;
d769a1da 309 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
2bea128c 310 int i;
d3bad7e7 311 NICInfo *nd = &nd_table[0];
327d8e4e 312
9fc7fc4d 313 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
327d8e4e 314
b033271f
CLG		 315 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
316
533eb415 317 /*
346160cb
CLG		 318 * This will error out if the RAM size is not supported by the
319 * memory controller of the SoC.
533eb415 320 */
6e504a98 321 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
533eb415
IM		 322 &error_fatal);
323
d3bad7e7
CLG		 324 for (i = 0; i < sc->macs_num; i++) {
325 if ((amc->macs_mask & (1 << i)) && nd->used) {
326 qemu_check_nic_model(nd, TYPE_FTGMAC100);
327 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
328 nd++;
329 }
330 }
331
5325cc34 332 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
87e79af0 333 &error_abort);
5325cc34 334 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
ccc2c418 335 &error_abort);
4dd9d554
PD		 336 object_property_set_link(OBJECT(&bmc->soc), "memory",
337 OBJECT(get_system_memory()), &error_abort);
5325cc34 338 object_property_set_link(OBJECT(&bmc->soc), "dram",
0df2d9a6 339 OBJECT(machine->ram), &error_abort);
b6e70d1d
JS		 340 if (machine->kernel_filename) {
341 /*
342 * When booting with a -kernel command line there is no u-boot
343 * that runs to unlock the SCU. In this case set the default to
344 * be unlocked as the kernel expects
345 */
5325cc34
MA		 346 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
347 ASPEED_SCU_PROT_KEY, &error_abort);
b6e70d1d 348 }
5d63d0c7
PD		 349 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
350 amc->uart_default);
ce189ab2 351 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
327d8e4e 352
8ec239f2
MA		 353 aspeed_board_init_flashes(&bmc->soc.fmc,
354 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
9bd4ac61 355 amc->num_cs, 0);
8ec239f2
MA		 356 aspeed_board_init_flashes(&bmc->soc.spi[0],
357 bmc->spi_model ? bmc->spi_model : amc->spi_model,
9bd4ac61 358 1, amc->num_cs);
74fb1f38 359
d769a1da
CLG		 360 /* Install first FMC flash content as a boot rom. */
361 if (drive0) {
362 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
363 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
6bb55e79 364 uint64_t size = memory_region_size(&fl->mmio);
d769a1da
CLG		 365
366 /*
367 * create a ROM region using the default mapping window size of
93bf276d
CLG		 368 * the flash module. The window size is 64MB for the AST2400
369 * SoC and 128MB for the AST2500 SoC, which is twice as big as
370 * needed by the flash modules of the Aspeed machines.
d769a1da 371 */
1a15311a 372 if (ASPEED_MACHINE(machine)->mmio_exec) {
f489960d 373 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
6bb55e79 374 &fl->mmio, 0, size);
1a15311a
CLG		 375 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
376 boot_rom);
377 } else {
f489960d 378 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
6bb55e79 379 size, &error_abort);
1a15311a
CLG		 380 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
381 boot_rom);
6bb55e79 382 write_boot_rom(drive0, FIRMWARE_ADDR, size, &error_abort);
1a15311a 383 }
d769a1da
CLG		 384 }
385
b7f1a0cb 386 if (machine->kernel_filename && sc->num_cpus > 1) {
9bb6d140
JS		 387 /* With no u-boot we must set up a boot stub for the secondary CPU */
388 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
f489960d 389 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
9bb6d140
JS		 390 0x80, &error_abort);
391 memory_region_add_subregion(get_system_memory(),
392 AST_SMP_MAILBOX_BASE, smpboot);
393
394 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
395 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
396 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
397 }
398
6e504a98 399 aspeed_board_binfo.ram_size = machine->ram_size;
347df6f8 400 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
e1ad9bc4 401
baa4732b
CLG		 402 if (amc->i2c_init) {
403 amc->i2c_init(bmc);
2cf6cb50
CLG		 404 }
405
0e2c24c6 406 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
8ec239f2
MA		 407 sdhci_attach_drive(&bmc->soc.sdhci.slots[i],
408 drive_get(IF_SD, 0, i));
a29e3e12 409 }
2bea128c 410
a29e3e12 411 if (bmc->soc.emmc.num_slots) {
8ec239f2
MA		 412 sdhci_attach_drive(&bmc->soc.emmc.slots[0],
413 drive_get(IF_SD, 0, bmc->soc.sdhci.num_slots));
2bea128c
EJ		 414 }
415
2744ece8 416 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
74fb1f38 417}
b033271f 418
82b6a3f6
JW		 419static void at24c_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
420{
421 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
422 DeviceState *dev = DEVICE(i2c_dev);
423
424 qdev_prop_set_uint32(dev, "rom-size", rsize);
425 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
426}
427
612b219a 428static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
2cf6cb50
CLG		 429{
430 AspeedSoCState *soc = &bmc->soc;
a87e81b9 431 DeviceState *dev;
3d165f12 432 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
2cf6cb50
CLG		 433
434 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
435 * enough to provide basic RTC features. Alarms will be missing */
1373b15b 436 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
a87e81b9 437
7a204cbd 438 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
3d165f12
CLG		 439 eeprom_buf);
440
a87e81b9 441 /* add a TMP423 temperature sensor */
1373b15b
PMD		 442 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
443 "tmp423", 0x4c));
5325cc34
MA		 444 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
445 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
446 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
447 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
2cf6cb50
CLG		 448}
449
9cccb912
PV		 450static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
451{
452 AspeedSoCState *soc = &bmc->soc;
453
454 /*
455 * The quanta-q71l platform expects tmp75s which are compatible with
456 * tmp105s.
457 */
458 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
459 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
460 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
461
462 /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
463 /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
464 /* TODO: Add Memory Riser i2c mux and eeproms. */
465
3ec75e39
PV		 466 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
467 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
468
9cccb912 469 /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
3ec75e39
PV		 470
471 /* i2c-7 */
472 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
9cccb912
PV		 473 /* - i2c@0: pmbus@59 */
474 /* - i2c@1: pmbus@58 */
475 /* - i2c@2: pmbus@58 */
476 /* - i2c@3: pmbus@59 */
3ec75e39 477
9cccb912
PV		 478 /* TODO: i2c-7: Add PDB FRU eeprom@52 */
479 /* TODO: i2c-8: Add BMC FRU eeprom@50 */
480}
481
612b219a 482static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
2cf6cb50
CLG		 483{
484 AspeedSoCState *soc = &bmc->soc;
3d165f12
CLG		 485 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
486
7a204cbd 487 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
3d165f12 488 eeprom_buf);
2cf6cb50
CLG		 489
490 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
1373b15b 491 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
044475f3 492 TYPE_TMP105, 0x4d);
2cf6cb50
CLG		 493}
494
612b219a 495static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
ccc2c418 496{
52bcd997
HC		 497 AspeedSoCState *soc = &bmc->soc;
498 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
499
500 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
501 eeprom_buf);
502
503 /* LM75 is compatible with TMP105 driver */
504 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
505 TYPE_TMP105, 0x4d);
ccc2c418
CLG		 506}
507
612b219a 508static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
6c4567c7
CLG		 509{
510 AspeedSoCState *soc = &bmc->soc;
511
512 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
513 * good enough */
1373b15b 514 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
6c4567c7
CLG		 515}
516
f4aec252
CLG		 517static void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
518{
519 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
520 TYPE_PCA9552, addr);
521}
522
612b219a 523static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
143b040f
PW		 524{
525 AspeedSoCState *soc = &bmc->soc;
526
527 /* bus 2 : */
1373b15b
PMD		 528 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
529 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
143b040f
PW		 530 /* bus 2 : pca9546 @ 0x73 */
531
532 /* bus 3 : pca9548 @ 0x70 */
533
534 /* bus 4 : */
535 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
7a204cbd 536 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
143b040f
PW		 537 eeprom4_54);
538 /* PCA9539 @ 0x76, but PCA9552 is compatible */
f4aec252 539 create_pca9552(soc, 4, 0x76);
143b040f 540 /* PCA9539 @ 0x77, but PCA9552 is compatible */
f4aec252 541 create_pca9552(soc, 4, 0x77);
143b040f
PW		 542
543 /* bus 6 : */
1373b15b
PMD		 544 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
545 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
143b040f
PW		 546 /* bus 6 : pca9546 @ 0x73 */
547
548 /* bus 8 : */
549 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
7a204cbd 550 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
143b040f 551 eeprom8_56);
f4aec252
CLG		 552 create_pca9552(soc, 8, 0x60);
553 create_pca9552(soc, 8, 0x61);
143b040f
PW		 554 /* bus 8 : adc128d818 @ 0x1d */
555 /* bus 8 : adc128d818 @ 0x1f */
556
557 /*
558 * bus 13 : pca9548 @ 0x71
559 * - channel 3:
560 * - tmm421 @ 0x4c
561 * - tmp421 @ 0x4e
562 * - tmp421 @ 0x4f
563 */
564
565}
566
612b219a 567static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
62c2c2eb 568{
7cfbde5e
PMD		 569 static const struct {
570 unsigned gpio_id;
571 LEDColor color;
572 const char *description;
573 bool gpio_polarity;
574 } pca1_leds[] = {
575 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
576 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
577 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
578 };
62c2c2eb 579 AspeedSoCState *soc = &bmc->soc;
3d165f12 580 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
15ce12cf 581 DeviceState *dev;
7cfbde5e 582 LEDState *led;
62c2c2eb 583
63ceb818 584 /* Bus 3: TODO bmp280@77 */
db437ca6 585 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
15ce12cf 586 qdev_prop_set_string(dev, "description", "pca1");
2616f572
PMD		 587 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
588 aspeed_i2c_get_bus(&soc->i2c, 3),
589 &error_fatal);
8c9a61d7 590
7cfbde5e
PMD		 591 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
592 led = led_create_simple(OBJECT(bmc),
593 pca1_leds[i].gpio_polarity,
594 pca1_leds[i].color,
595 pca1_leds[i].description);
596 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
597 qdev_get_gpio_in(DEVICE(led), 0));
598 }
b61ea6e7 599 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "dps310", 0x76);
2a75e8c3 600 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "max31785", 0x52);
1373b15b
PMD		 601 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
602 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
62c2c2eb
CLG		 603
604 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
1373b15b 605 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
044475f3 606 0x4a);
6c4567c7
CLG		 607
608 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
609 * good enough */
1373b15b 610 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
3d165f12 611
7a204cbd 612 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
3d165f12 613 eeprom_buf);
db437ca6 614 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
15ce12cf 615 qdev_prop_set_string(dev, "description", "pca0");
2616f572
PMD		 616 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
617 aspeed_i2c_get_bus(&soc->i2c, 11),
618 &error_fatal);
63ceb818 619 /* Bus 11: TODO ucd90160@64 */
62c2c2eb
CLG		 620}
621
95f068c8
JW		 622static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
623{
624 AspeedSoCState *soc = &bmc->soc;
625 DeviceState *dev;
626
627 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
628 "emc1413", 0x4c));
629 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
630 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
631 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
632
633 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
634 "emc1413", 0x4c));
635 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
636 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
637 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
638
639 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
640 "emc1413", 0x4c));
641 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
642 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
643 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
6f5f6507
JW		 644
645 static uint8_t eeprom_buf[2 * 1024] = {
646 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
647 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
648 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
649 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
650 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
651 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
652 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
653 };
654 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
655 eeprom_buf);
95f068c8
JW		 656}
657
fa6d98c0
JS		 658static void aspeed_eeprom_init(I2CBus *bus, uint8_t addr, uint32_t rsize)
659{
660 I2CSlave *i2c_dev = i2c_slave_new("at24c-eeprom", addr);
661 DeviceState *dev = DEVICE(i2c_dev);
662
663 qdev_prop_set_uint32(dev, "rom-size", rsize);
664 i2c_slave_realize_and_unref(i2c_dev, bus, &error_abort);
665}
666
82b6a3f6
JW		 667static void fp5280g2_bmc_i2c_init(AspeedMachineState *bmc)
668{
669 AspeedSoCState *soc = &bmc->soc;
670 I2CSlave *i2c_mux;
671
672 /* The at24c256 */
673 at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 1), 0x50, 32768);
674
675 /* The fp5280g2 expects a TMP112 but a TMP105 is compatible */
676 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
677 0x48);
678 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), TYPE_TMP105,
679 0x49);
680
681 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
682 "pca9546", 0x70);
683 /* It expects a TMP112 but a TMP105 is compatible */
684 i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 0), TYPE_TMP105,
685 0x4a);
686
687 /* It expects a ds3232 but a ds1338 is good enough */
688 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "ds1338", 0x68);
689
690 /* It expects a pca9555 but a pca9552 is compatible */
f4aec252 691 create_pca9552(soc, 8, 0x30);
82b6a3f6
JW		 692}
693
58e52bdb
CLG		 694static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
695{
696 AspeedSoCState *soc = &bmc->soc;
fa6d98c0
JS		 697 I2CSlave *i2c_mux;
698
699 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
58e52bdb 700
f4aec252 701 create_pca9552(soc, 3, 0x61);
bcb122f8 702
58e52bdb
CLG		 703 /* The rainier expects a TMP275 but a TMP105 is compatible */
704 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
705 0x48);
706 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
707 0x49);
708 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
709 0x4a);
fa6d98c0
JS		 710 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
711 "pca9546", 0x70);
712 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
713 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
714 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
f4aec252 715 create_pca9552(soc, 4, 0x60);
58e52bdb
CLG		 716
717 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
718 0x48);
719 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
720 0x49);
f4aec252
CLG		 721 create_pca9552(soc, 5, 0x60);
722 create_pca9552(soc, 5, 0x61);
fa6d98c0
JS		 723 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
724 "pca9546", 0x70);
725 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
726 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
58e52bdb
CLG		 727
728 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
729 0x48);
730 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
731 0x4a);
732 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
733 0x4b);
fa6d98c0
JS		 734 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
735 "pca9546", 0x70);
736 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
737 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
738 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
739 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
58e52bdb 740
f4aec252
CLG		 741 create_pca9552(soc, 7, 0x30);
742 create_pca9552(soc, 7, 0x31);
743 create_pca9552(soc, 7, 0x32);
744 create_pca9552(soc, 7, 0x33);
f4aec252
CLG		 745 create_pca9552(soc, 7, 0x60);
746 create_pca9552(soc, 7, 0x61);
b61ea6e7 747 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
58e52bdb
CLG		 748 /* Bus 7: TODO si7021-a20@20 */
749 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
750 0x48);
2a75e8c3 751 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
fa6d98c0
JS		 752 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
753 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
58e52bdb
CLG		 754
755 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
756 0x48);
757 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
758 0x4a);
fa6d98c0
JS		 759 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50, 64 * KiB);
760 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51, 64 * KiB);
f4aec252
CLG		 761 create_pca9552(soc, 8, 0x60);
762 create_pca9552(soc, 8, 0x61);
58e52bdb
CLG		 763 /* Bus 8: ucd90320@11 */
764 /* Bus 8: ucd90320@b */
765 /* Bus 8: ucd90320@c */
766
767 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
768 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
fa6d98c0 769 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
58e52bdb
CLG		 770
771 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
772 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
fa6d98c0 773 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
58e52bdb
CLG		 774
775 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
776 0x48);
777 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
778 0x49);
fa6d98c0
JS		 779 i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
780 "pca9546", 0x70);
781 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
782 aspeed_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
f4aec252 783 create_pca9552(soc, 11, 0x60);
fa6d98c0
JS		 784
785
786 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
f4aec252 787 create_pca9552(soc, 13, 0x60);
fa6d98c0
JS		 788
789 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
f4aec252 790 create_pca9552(soc, 14, 0x60);
fa6d98c0
JS		 791
792 aspeed_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
f4aec252 793 create_pca9552(soc, 15, 0x60);
58e52bdb
CLG		 794}
795
febbe308
PD		 796static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
797 I2CBus **channels)
798{
799 I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
800 for (int i = 0; i < 8; i++) {
801 channels[i] = pca954x_i2c_get_bus(mux, i);
802 }
803}
804
805#define TYPE_LM75 TYPE_TMP105
806#define TYPE_TMP75 TYPE_TMP105
807#define TYPE_TMP422 "tmp422"
808
809static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
810{
811 AspeedSoCState *soc = &bmc->soc;
812 I2CBus *i2c[144] = {};
813
814 for (int i = 0; i < 16; i++) {
815 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
816 }
817 I2CBus *i2c180 = i2c[2];
818 I2CBus *i2c480 = i2c[8];
819 I2CBus *i2c600 = i2c[11];
820
821 get_pca9548_channels(i2c180, 0x70, &i2c[16]);
822 get_pca9548_channels(i2c480, 0x70, &i2c[24]);
823 /* NOTE: The device tree skips [32, 40) in the alias numbering */
824 get_pca9548_channels(i2c600, 0x77, &i2c[40]);
825 get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
826 get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
827 get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
828 get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
829 for (int i = 0; i < 8; i++) {
830 get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
831 }
832
833 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
834 i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
835
836 aspeed_eeprom_init(i2c[19], 0x52, 64 * KiB);
837 aspeed_eeprom_init(i2c[20], 0x50, 2 * KiB);
838 aspeed_eeprom_init(i2c[22], 0x52, 2 * KiB);
839
840 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
841 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
842 i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
843 i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
844
845 aspeed_eeprom_init(i2c[8], 0x51, 64 * KiB);
846 i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
847
848 i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
849 aspeed_eeprom_init(i2c[50], 0x52, 64 * KiB);
850 i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
851 i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
852
853 i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
854 i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
855
856 aspeed_eeprom_init(i2c[65], 0x53, 64 * KiB);
857 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
858 i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
859 aspeed_eeprom_init(i2c[68], 0x52, 64 * KiB);
860 aspeed_eeprom_init(i2c[69], 0x52, 64 * KiB);
861 aspeed_eeprom_init(i2c[70], 0x52, 64 * KiB);
862 aspeed_eeprom_init(i2c[71], 0x52, 64 * KiB);
863
864 aspeed_eeprom_init(i2c[73], 0x53, 64 * KiB);
865 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
866 i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
867 aspeed_eeprom_init(i2c[76], 0x52, 64 * KiB);
868 aspeed_eeprom_init(i2c[77], 0x52, 64 * KiB);
869 aspeed_eeprom_init(i2c[78], 0x52, 64 * KiB);
870 aspeed_eeprom_init(i2c[79], 0x52, 64 * KiB);
871 aspeed_eeprom_init(i2c[28], 0x50, 2 * KiB);
872
873 for (int i = 0; i < 8; i++) {
874 aspeed_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
875 i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
876 i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
877 i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
878 }
879}
880
a20c54b1
PW		 881#define TYPE_TMP421 "tmp421"
882
883static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
884{
885 AspeedSoCState *soc = &bmc->soc;
886 I2CBus *i2c[13] = {};
887 for (int i = 0; i < 13; i++) {
888 if ((i == 8) || (i == 11)) {
889 continue;
890 }
891 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
892 }
893
894 /* Bus 0 - 5 all have the same config. */
895 for (int i = 0; i < 6; i++) {
896 /* Missing model: ti,ina230 @ 0x45 */
897 /* Missing model: mps,mp5023 @ 0x40 */
898 i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
899 /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
900 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
901 i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
902 /* Missing model: fsc,fusb302 @ 0x22 */
903 }
904
905 /* Bus 6 */
906 at24c_eeprom_init(i2c[6], 0x56, 65536);
907 /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
908 i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
909
910
911 /* Bus 7 */
912 at24c_eeprom_init(i2c[7], 0x54, 65536);
913
914 /* Bus 9 */
915 i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
916
917 /* Bus 10 */
918 i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
919 /* Missing model: ti,hdc1080 @ 0x40 */
920 i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
921
922 /* Bus 12 */
923 /* Missing model: adi,adm1278 @ 0x11 */
924 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
925 i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
926 i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
927}
928
fa699e80
PD		 929static void fby35_i2c_init(AspeedMachineState *bmc)
930{
931 AspeedSoCState *soc = &bmc->soc;
932 I2CBus *i2c[16];
933
934 for (int i = 0; i < 16; i++) {
935 i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
936 }
937
938 i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
939 i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
940 /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
941 i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
942 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
943 i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
944
945 aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB);
946 aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB);
947 aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB);
948 aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB);
949 aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB);
950
951 /*
952 * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
953 * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
954 * each.
955 */
956}
957
fb6b3c8d
JHY		 958static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
959{
960 AspeedSoCState *soc = &bmc->soc;
961
962 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
963}
964
ece4cccd
GG		 965static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
966{
967 AspeedSoCState *soc = &bmc->soc;
2a7a5d5c 968 I2CSlave *therm_mux, *cpuvr_mux;
ece4cccd
GG		 969
970 /* Create the generic DC-SCM hardware */
971 qcom_dc_scm_bmc_i2c_init(bmc);
972
973 /* Now create the Firework specific hardware */
2a75e8c3 974
2a7a5d5c
JHY		 975 /* I2C7 CPUVR MUX */
976 cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
977 "pca9546", 0x70);
978 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
979 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
980 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
981 i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
982
cfc68f16
MK		 983 /* I2C8 Thermal Diodes*/
984 therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
985 "pca9548", 0x70);
986 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
987 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
988 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
989 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
990 i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
991
2a75e8c3
MK		 992 /* I2C9 Fan Controller (MAX31785) */
993 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
994 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
ece4cccd
GG		 995}
996
1a15311a
CLG		 997static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
998{
999 return ASPEED_MACHINE(obj)->mmio_exec;
1000}
1001
1002static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
1003{
1004 ASPEED_MACHINE(obj)->mmio_exec = value;
1005}
1006
1007static void aspeed_machine_instance_init(Object *obj)
1008{
1009 ASPEED_MACHINE(obj)->mmio_exec = false;
1010}
1011
9820e52f
CLG		 1012static char *aspeed_get_fmc_model(Object *obj, Error **errp)
1013{
1014 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1015 return g_strdup(bmc->fmc_model);
1016}
1017
1018static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
1019{
1020 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1021
1022 g_free(bmc->fmc_model);
1023 bmc->fmc_model = g_strdup(value);
1024}
1025
1026static char *aspeed_get_spi_model(Object *obj, Error **errp)
1027{
1028 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1029 return g_strdup(bmc->spi_model);
1030}
1031
1032static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
1033{
1034 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
1035
1036 g_free(bmc->spi_model);
1037 bmc->spi_model = g_strdup(value);
1038}
1039
1a15311a
CLG		 1040static void aspeed_machine_class_props_init(ObjectClass *oc)
1041{
1042 object_class_property_add_bool(oc, "execute-in-place",
1043 aspeed_get_mmio_exec,
d2623129 1044 aspeed_set_mmio_exec);
1a15311a 1045 object_class_property_set_description(oc, "execute-in-place",
7eecec7d 1046 "boot directly from CE0 flash device");
9820e52f
CLG		 1047
1048 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
1049 aspeed_set_fmc_model);
1050 object_class_property_set_description(oc, "fmc-model",
1051 "Change the FMC Flash model");
1052 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
1053 aspeed_set_spi_model);
1054 object_class_property_set_description(oc, "spi-model",
1055 "Change the SPI Flash model");
1a15311a
CLG		 1056}
1057
b7f1a0cb
CLG		 1058static int aspeed_soc_num_cpus(const char *soc_name)
1059{
1060 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
1061 return sc->num_cpus;
1062}
1063
fca9ca1b 1064static void aspeed_machine_class_init(ObjectClass *oc, void *data)
62c2c2eb
CLG		 1065{
1066 MachineClass *mc = MACHINE_CLASS(oc);
d3bad7e7 1067 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
62c2c2eb 1068
fca9ca1b 1069 mc->init = aspeed_machine_init;
62c2c2eb
CLG		 1070 mc->no_floppy = 1;
1071 mc->no_cdrom = 1;
1072 mc->no_parallel = 1;
afcbaed6 1073 mc->default_ram_id = "ram";
d3bad7e7 1074 amc->macs_mask = ASPEED_MAC0_ON;
5d63d0c7 1075 amc->uart_default = ASPEED_DEV_UART5;
1a15311a
CLG		 1076
1077 aspeed_machine_class_props_init(oc);
62c2c2eb
CLG		 1078}
1079
baa4732b
CLG		 1080static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
1081{
1082 MachineClass *mc = MACHINE_CLASS(oc);
1083 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1084
1085 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
1086 amc->soc_name = "ast2400-a1";
1087 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
1088 amc->fmc_model = "n25q256a";
1089 amc->spi_model = "mx25l25635e";
1090 amc->num_cs = 1;
1091 amc->i2c_init = palmetto_bmc_i2c_init;
1092 mc->default_ram_size = 256 * MiB;
b7f1a0cb
CLG		 1093 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1094 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1095};
1096
9cccb912
PV		 1097static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data)
1098{
1099 MachineClass *mc = MACHINE_CLASS(oc);
1100 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1101
1102 mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
1103 amc->soc_name = "ast2400-a1";
1104 amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
1105 amc->fmc_model = "n25q256a";
1106 amc->spi_model = "mx25l25635e";
1107 amc->num_cs = 1;
1108 amc->i2c_init = quanta_q71l_bmc_i2c_init;
1109 mc->default_ram_size = 128 * MiB;
1110 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1111 aspeed_soc_num_cpus(amc->soc_name);
1112}
1113
40a38df5
ES		 1114static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
1115 void *data)
1116{
1117 MachineClass *mc = MACHINE_CLASS(oc);
1118 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1119
1120 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
1121 amc->soc_name = "ast2400-a1";
1122 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
1123 amc->fmc_model = "mx25l25635e";
1124 amc->spi_model = "mx25l25635e";
1125 amc->num_cs = 1;
1126 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1127 amc->i2c_init = palmetto_bmc_i2c_init;
1128 mc->default_ram_size = 256 * MiB;
1129}
1130
baa4732b
CLG		 1131static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
1132{
1133 MachineClass *mc = MACHINE_CLASS(oc);
1134 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1135
1136 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
1137 amc->soc_name = "ast2500-a1";
1138 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
753abfc4 1139 amc->fmc_model = "mx25l25635e";
baa4732b
CLG		 1140 amc->spi_model = "mx25l25635e";
1141 amc->num_cs = 1;
1142 amc->i2c_init = ast2500_evb_i2c_init;
1143 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1144 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1145 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1146};
1147
1148static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
1149{
1150 MachineClass *mc = MACHINE_CLASS(oc);
1151 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1152
1153 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
1154 amc->soc_name = "ast2500-a1";
1155 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
1156 amc->fmc_model = "n25q256a";
1157 amc->spi_model = "mx66l1g45g";
1158 amc->num_cs = 2;
1159 amc->i2c_init = romulus_bmc_i2c_init;
1160 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1161 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1162 aspeed_soc_num_cpus(amc->soc_name);
fca9ca1b
CLG		 1163};
1164
143b040f
PW		 1165static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
1166{
1167 MachineClass *mc = MACHINE_CLASS(oc);
1168 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1169
1170 mc->desc = "OCP SonoraPass BMC (ARM1176)";
1171 amc->soc_name = "ast2500-a1";
1172 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
1173 amc->fmc_model = "mx66l1g45g";
1174 amc->spi_model = "mx66l1g45g";
1175 amc->num_cs = 2;
1176 amc->i2c_init = sonorapass_bmc_i2c_init;
1177 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1178 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1179 aspeed_soc_num_cpus(amc->soc_name);
143b040f
PW		 1180};
1181
baa4732b
CLG		 1182static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
1183{
1184 MachineClass *mc = MACHINE_CLASS(oc);
1185 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1186
1187 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
1188 amc->soc_name = "ast2500-a1";
1189 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
1190 amc->fmc_model = "mx25l25635e";
1191 amc->spi_model = "mx66l1g45g";
1192 amc->num_cs = 2;
1193 amc->i2c_init = witherspoon_bmc_i2c_init;
1194 mc->default_ram_size = 512 * MiB;
b7f1a0cb
CLG		 1195 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1196 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1197};
1198
1199static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
1200{
1201 MachineClass *mc = MACHINE_CLASS(oc);
1202 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1203
f548f201 1204 mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
c5811bb3 1205 amc->soc_name = "ast2600-a3";
baa4732b
CLG		 1206 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
1207 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
753abfc4 1208 amc->fmc_model = "mx66u51235f";
baa4732b
CLG		 1209 amc->spi_model = "mx66u51235f";
1210 amc->num_cs = 1;
29193286
GR		 1211 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
1212 ASPEED_MAC3_ON;
baa4732b
CLG		 1213 amc->i2c_init = ast2600_evb_i2c_init;
1214 mc->default_ram_size = 1 * GiB;
b7f1a0cb
CLG		 1215 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1216 aspeed_soc_num_cpus(amc->soc_name);
baa4732b
CLG		 1217};
1218
63ceb818
CLG		 1219static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
1220{
1221 MachineClass *mc = MACHINE_CLASS(oc);
1222 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1223
f548f201 1224 mc->desc = "OpenPOWER Tacoma BMC (Cortex-A7)";
c5811bb3 1225 amc->soc_name = "ast2600-a3";
63ceb818
CLG		 1226 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
1227 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
1228 amc->fmc_model = "mx66l1g45g";
1229 amc->spi_model = "mx66l1g45g";
1230 amc->num_cs = 2;
d3bad7e7 1231 amc->macs_mask = ASPEED_MAC2_ON;
63ceb818
CLG		 1232 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
1233 mc->default_ram_size = 1 * GiB;
b7f1a0cb
CLG		 1234 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1235 aspeed_soc_num_cpus(amc->soc_name);
63ceb818
CLG		 1236};
1237
95f068c8
JW		 1238static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
1239{
1240 MachineClass *mc = MACHINE_CLASS(oc);
1241 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1242
1243 mc->desc = "Bytedance G220A BMC (ARM1176)";
1244 amc->soc_name = "ast2500-a1";
1245 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
1246 amc->fmc_model = "n25q512a";
1247 amc->spi_model = "mx25l25635e";
1248 amc->num_cs = 2;
5bb825c8 1249 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
95f068c8
JW		 1250 amc->i2c_init = g220a_bmc_i2c_init;
1251 mc->default_ram_size = 1024 * MiB;
1252 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1253 aspeed_soc_num_cpus(amc->soc_name);
1254};
1255
82b6a3f6
JW		 1256static void aspeed_machine_fp5280g2_class_init(ObjectClass *oc, void *data)
1257{
1258 MachineClass *mc = MACHINE_CLASS(oc);
1259 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1260
1261 mc->desc = "Inspur FP5280G2 BMC (ARM1176)";
1262 amc->soc_name = "ast2500-a1";
1263 amc->hw_strap1 = FP5280G2_BMC_HW_STRAP1;
1264 amc->fmc_model = "n25q512a";
1265 amc->spi_model = "mx25l25635e";
1266 amc->num_cs = 2;
1267 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
1268 amc->i2c_init = fp5280g2_bmc_i2c_init;
1269 mc->default_ram_size = 512 * MiB;
1270 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1271 aspeed_soc_num_cpus(amc->soc_name);
1272};
1273
58e52bdb
CLG		 1274static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data)
1275{
1276 MachineClass *mc = MACHINE_CLASS(oc);
1277 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1278
f548f201 1279 mc->desc = "IBM Rainier BMC (Cortex-A7)";
c5811bb3 1280 amc->soc_name = "ast2600-a3";
58e52bdb
CLG		 1281 amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
1282 amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
1283 amc->fmc_model = "mx66l1g45g";
1284 amc->spi_model = "mx66l1g45g";
1285 amc->num_cs = 2;
1286 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1287 amc->i2c_init = rainier_bmc_i2c_init;
1288 mc->default_ram_size = 1 * GiB;
1289 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1290 aspeed_soc_num_cpus(amc->soc_name);
1291};
1292
febbe308
PD		 1293/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
1294#if HOST_LONG_BITS == 32
1295#define FUJI_BMC_RAM_SIZE (1 * GiB)
1296#else
1297#define FUJI_BMC_RAM_SIZE (2 * GiB)
1298#endif
1299
1300static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data)
1301{
1302 MachineClass *mc = MACHINE_CLASS(oc);
1303 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1304
1305 mc->desc = "Facebook Fuji BMC (Cortex-A7)";
1306 amc->soc_name = "ast2600-a3";
1307 amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
1308 amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
1309 amc->fmc_model = "mx66l1g45g";
1310 amc->spi_model = "mx66l1g45g";
1311 amc->num_cs = 2;
1312 amc->macs_mask = ASPEED_MAC3_ON;
1313 amc->i2c_init = fuji_bmc_i2c_init;
1314 amc->uart_default = ASPEED_DEV_UART1;
1315 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1316 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1317 aspeed_soc_num_cpus(amc->soc_name);
1318};
1319
a20c54b1
PW		 1320static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data)
1321{
1322 MachineClass *mc = MACHINE_CLASS(oc);
1323 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1324
1325 mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
1326 amc->soc_name = "ast2600-a3";
1327 amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
1328 amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
1329 amc->fmc_model = "w25q01jvq";
1330 amc->spi_model = NULL;
1331 amc->num_cs = 2;
1332 amc->macs_mask = ASPEED_MAC2_ON;
1333 amc->i2c_init = bletchley_bmc_i2c_init;
1334 mc->default_ram_size = 512 * MiB;
1335 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1336 aspeed_soc_num_cpus(amc->soc_name);
1337}
1338
fa699e80
PD		 1339static void fby35_reset(MachineState *state)
1340{
1341 AspeedMachineState *bmc = ASPEED_MACHINE(state);
1342 AspeedGPIOState *gpio = &bmc->soc.gpio;
1343
1344 qemu_devices_reset();
1345
1346 /* Board ID */
1347 object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
1348 object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
1349 object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
1350 object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
1351}
1352
1353static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data)
1354{
1355 MachineClass *mc = MACHINE_CLASS(oc);
1356 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1357
1358 mc->desc = "Facebook fby35 BMC (Cortex-A7)";
1359 mc->reset = fby35_reset;
1360 amc->fmc_model = "mx66l1g45g";
1361 amc->num_cs = 2;
1362 amc->macs_mask = ASPEED_MAC3_ON;
1363 amc->i2c_init = fby35_i2c_init;
1364 /* FIXME: Replace this macro with something more general */
1365 mc->default_ram_size = FUJI_BMC_RAM_SIZE;
1366}
1367
66c895b8
JL		 1368#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
1369/* Main SYSCLK frequency in Hz (200MHz) */
1370#define SYSCLK_FRQ 200000000ULL
1371
1372static void aspeed_minibmc_machine_init(MachineState *machine)
1373{
1374 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
1375 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
1376 Clock *sysclk;
1377
1378 sysclk = clock_new(OBJECT(machine), "SYSCLK");
1379 clock_set_hz(sysclk, SYSCLK_FRQ);
1380
1381 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
1382 qdev_connect_clock_in(DEVICE(&bmc->soc), "sysclk", sysclk);
1383
4dd9d554
PD		 1384 object_property_set_link(OBJECT(&bmc->soc), "memory",
1385 OBJECT(get_system_memory()), &error_abort);
66c895b8
JL		 1386 qdev_prop_set_uint32(DEVICE(&bmc->soc), "uart-default",
1387 amc->uart_default);
1388 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
1389
1390 aspeed_board_init_flashes(&bmc->soc.fmc,
1391 bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
1392 amc->num_cs,
1393 0);
1394
1395 aspeed_board_init_flashes(&bmc->soc.spi[0],
1396 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1397 amc->num_cs, amc->num_cs);
1398
1399 aspeed_board_init_flashes(&bmc->soc.spi[1],
1400 bmc->spi_model ? bmc->spi_model : amc->spi_model,
1401 amc->num_cs, (amc->num_cs * 2));
1402
1403 if (amc->i2c_init) {
1404 amc->i2c_init(bmc);
1405 }
1406
1407 armv7m_load_kernel(ARM_CPU(first_cpu),
1408 machine->kernel_filename,
1409 AST1030_INTERNAL_FLASH_SIZE);
1410}
1411
4c70ab16
TL		 1412static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
1413{
1414 AspeedSoCState *soc = &bmc->soc;
1415
1416 /* U10 24C08 connects to SDA/SCL Groupt 1 by default */
1417 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
1418 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
1419
1420 /* U11 LM75 connects to SDA/SCL Group 2 by default */
1421 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
1422}
1423
66c895b8
JL		 1424static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
1425 void *data)
1426{
1427 MachineClass *mc = MACHINE_CLASS(oc);
1428 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1429
1430 mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
1431 amc->soc_name = "ast1030-a1";
1432 amc->hw_strap1 = 0;
1433 amc->hw_strap2 = 0;
1434 mc->init = aspeed_minibmc_machine_init;
4c70ab16 1435 amc->i2c_init = ast1030_evb_i2c_init;
66c895b8
JL		 1436 mc->default_ram_size = 0;
1437 mc->default_cpus = mc->min_cpus = mc->max_cpus = 1;
1438 amc->fmc_model = "sst25vf032b";
1439 amc->spi_model = "sst25vf032b";
1440 amc->num_cs = 2;
1441 amc->macs_mask = 0;
1442}
1443
fb6b3c8d
JHY		 1444static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
1445 void *data)
1446{
1447 MachineClass *mc = MACHINE_CLASS(oc);
1448 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1449
1450 mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
1451 amc->soc_name = "ast2600-a3";
1452 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1453 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1454 amc->fmc_model = "n25q512a";
1455 amc->spi_model = "n25q512a";
1456 amc->num_cs = 2;
1457 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1458 amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
1459 mc->default_ram_size = 1 * GiB;
1460 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1461 aspeed_soc_num_cpus(amc->soc_name);
1462};
1463
ece4cccd
GG		 1464static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
1465 void *data)
1466{
1467 MachineClass *mc = MACHINE_CLASS(oc);
1468 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
1469
1470 mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
1471 amc->soc_name = "ast2600-a3";
1472 amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
1473 amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
1474 amc->fmc_model = "n25q512a";
1475 amc->spi_model = "n25q512a";
1476 amc->num_cs = 2;
1477 amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
1478 amc->i2c_init = qcom_dc_scm_firework_i2c_init;
1479 mc->default_ram_size = 1 * GiB;
1480 mc->default_cpus = mc->min_cpus = mc->max_cpus =
1481 aspeed_soc_num_cpus(amc->soc_name);
1482};
1483
baa4732b 1484static const TypeInfo aspeed_machine_types[] = {
fca9ca1b 1485 {
baa4732b
CLG		 1486 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
1487 .parent = TYPE_ASPEED_MACHINE,
1488 .class_init = aspeed_machine_palmetto_class_init,
40a38df5
ES		 1489 }, {
1490 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
1491 .parent = TYPE_ASPEED_MACHINE,
1492 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
fca9ca1b 1493 }, {
baa4732b
CLG		 1494 .name = MACHINE_TYPE_NAME("ast2500-evb"),
1495 .parent = TYPE_ASPEED_MACHINE,
1496 .class_init = aspeed_machine_ast2500_evb_class_init,
fca9ca1b 1497 }, {
baa4732b
CLG		 1498 .name = MACHINE_TYPE_NAME("romulus-bmc"),
1499 .parent = TYPE_ASPEED_MACHINE,
1500 .class_init = aspeed_machine_romulus_class_init,
143b040f
PW		 1501 }, {
1502 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
1503 .parent = TYPE_ASPEED_MACHINE,
1504 .class_init = aspeed_machine_sonorapass_class_init,
fca9ca1b 1505 }, {
baa4732b
CLG		 1506 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
1507 .parent = TYPE_ASPEED_MACHINE,
1508 .class_init = aspeed_machine_witherspoon_class_init,
ccc2c418 1509 }, {
baa4732b
CLG		 1510 .name = MACHINE_TYPE_NAME("ast2600-evb"),
1511 .parent = TYPE_ASPEED_MACHINE,
1512 .class_init = aspeed_machine_ast2600_evb_class_init,
63ceb818
CLG		 1513 }, {
1514 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
1515 .parent = TYPE_ASPEED_MACHINE,
1516 .class_init = aspeed_machine_tacoma_class_init,
95f068c8
JW		 1517 }, {
1518 .name = MACHINE_TYPE_NAME("g220a-bmc"),
1519 .parent = TYPE_ASPEED_MACHINE,
1520 .class_init = aspeed_machine_g220a_class_init,
fb6b3c8d
JHY		 1521 }, {
1522 .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
1523 .parent = TYPE_ASPEED_MACHINE,
1524 .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
ece4cccd
GG		 1525 }, {
1526 .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
1527 .parent = TYPE_ASPEED_MACHINE,
1528 .class_init = aspeed_machine_qcom_firework_class_init,
82b6a3f6
JW		 1529 }, {
1530 .name = MACHINE_TYPE_NAME("fp5280g2-bmc"),
1531 .parent = TYPE_ASPEED_MACHINE,
1532 .class_init = aspeed_machine_fp5280g2_class_init,
9cccb912
PV		 1533 }, {
1534 .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
1535 .parent = TYPE_ASPEED_MACHINE,
1536 .class_init = aspeed_machine_quanta_q71l_class_init,
58e52bdb
CLG		 1537 }, {
1538 .name = MACHINE_TYPE_NAME("rainier-bmc"),
1539 .parent = TYPE_ASPEED_MACHINE,
1540 .class_init = aspeed_machine_rainier_class_init,
febbe308
PD		 1541 }, {
1542 .name = MACHINE_TYPE_NAME("fuji-bmc"),
1543 .parent = TYPE_ASPEED_MACHINE,
1544 .class_init = aspeed_machine_fuji_class_init,
a20c54b1
PW		 1545 }, {
1546 .name = MACHINE_TYPE_NAME("bletchley-bmc"),
1547 .parent = TYPE_ASPEED_MACHINE,
1548 .class_init = aspeed_machine_bletchley_class_init,
fa699e80
PD		 1549 }, {
1550 .name = MACHINE_TYPE_NAME("fby35-bmc"),
1551 .parent = MACHINE_TYPE_NAME("ast2600-evb"),
1552 .class_init = aspeed_machine_fby35_class_init,
66c895b8
JL		 1553 }, {
1554 .name = MACHINE_TYPE_NAME("ast1030-evb"),
1555 .parent = TYPE_ASPEED_MACHINE,
1556 .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
baa4732b
CLG		 1557 }, {
1558 .name = TYPE_ASPEED_MACHINE,
1559 .parent = TYPE_MACHINE,
888b2b03 1560 .instance_size = sizeof(AspeedMachineState),
1a15311a 1561 .instance_init = aspeed_machine_instance_init,
baa4732b
CLG		 1562 .class_size = sizeof(AspeedMachineClass),
1563 .class_init = aspeed_machine_class_init,
1564 .abstract = true,
fca9ca1b 1565 }
baa4732b 1566};
74fb1f38 1567
baa4732b 1568DEFINE_TYPES(aspeed_machine_types)
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