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intel-iommu: send PSI always even if across PDEs
[mirror_qemu.git] / hw / i386 / intel_iommu.c
CommitLineData
1da12ec4
LT		 1/*
2 * QEMU emulation of an Intel IOMMU (VT-d)
3 * (DMA Remapping device)
4 *
5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com>
6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
b6a0aa05 22#include "qemu/osdep.h"
4684a204 23#include "qemu/error-report.h"
6333e93c 24#include "qapi/error.h"
1da12ec4
LT		 25#include "hw/sysbus.h"
26#include "exec/address-spaces.h"
27#include "intel_iommu_internal.h"
7df953bd 28#include "hw/pci/pci.h"
3cb3b154 29#include "hw/pci/pci_bus.h"
621d983a 30#include "hw/i386/pc.h"
dea651a9 31#include "hw/i386/apic-msidef.h"
04af0e18
PX		 32#include "hw/boards.h"
33#include "hw/i386/x86-iommu.h"
cb135f59 34#include "hw/pci-host/q35.h"
4684a204 35#include "sysemu/kvm.h"
32946019 36#include "hw/i386/apic_internal.h"
fb506e70 37#include "kvm_i386.h"
bc535e59 38#include "trace.h"
1da12ec4 39
1da12ec4
LT		 40static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
41 uint64_t wmask, uint64_t w1cmask)
42{
43 stq_le_p(&s->csr[addr], val);
44 stq_le_p(&s->wmask[addr], wmask);
45 stq_le_p(&s->w1cmask[addr], w1cmask);
46}
47
48static void vtd_define_quad_wo(IntelIOMMUState *s, hwaddr addr, uint64_t mask)
49{
50 stq_le_p(&s->womask[addr], mask);
51}
52
53static void vtd_define_long(IntelIOMMUState *s, hwaddr addr, uint32_t val,
54 uint32_t wmask, uint32_t w1cmask)
55{
56 stl_le_p(&s->csr[addr], val);
57 stl_le_p(&s->wmask[addr], wmask);
58 stl_le_p(&s->w1cmask[addr], w1cmask);
59}
60
61static void vtd_define_long_wo(IntelIOMMUState *s, hwaddr addr, uint32_t mask)
62{
63 stl_le_p(&s->womask[addr], mask);
64}
65
66/* "External" get/set operations */
67static void vtd_set_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val)
68{
69 uint64_t oldval = ldq_le_p(&s->csr[addr]);
70 uint64_t wmask = ldq_le_p(&s->wmask[addr]);
71 uint64_t w1cmask = ldq_le_p(&s->w1cmask[addr]);
72 stq_le_p(&s->csr[addr],
73 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
74}
75
76static void vtd_set_long(IntelIOMMUState *s, hwaddr addr, uint32_t val)
77{
78 uint32_t oldval = ldl_le_p(&s->csr[addr]);
79 uint32_t wmask = ldl_le_p(&s->wmask[addr]);
80 uint32_t w1cmask = ldl_le_p(&s->w1cmask[addr]);
81 stl_le_p(&s->csr[addr],
82 ((oldval & ~wmask) | (val & wmask)) & ~(w1cmask & val));
83}
84
85static uint64_t vtd_get_quad(IntelIOMMUState *s, hwaddr addr)
86{
87 uint64_t val = ldq_le_p(&s->csr[addr]);
88 uint64_t womask = ldq_le_p(&s->womask[addr]);
89 return val & ~womask;
90}
91
92static uint32_t vtd_get_long(IntelIOMMUState *s, hwaddr addr)
93{
94 uint32_t val = ldl_le_p(&s->csr[addr]);
95 uint32_t womask = ldl_le_p(&s->womask[addr]);
96 return val & ~womask;
97}
98
99/* "Internal" get/set operations */
100static uint64_t vtd_get_quad_raw(IntelIOMMUState *s, hwaddr addr)
101{
102 return ldq_le_p(&s->csr[addr]);
103}
104
105static uint32_t vtd_get_long_raw(IntelIOMMUState *s, hwaddr addr)
106{
107 return ldl_le_p(&s->csr[addr]);
108}
109
110static void vtd_set_quad_raw(IntelIOMMUState *s, hwaddr addr, uint64_t val)
111{
112 stq_le_p(&s->csr[addr], val);
113}
114
115static uint32_t vtd_set_clear_mask_long(IntelIOMMUState *s, hwaddr addr,
116 uint32_t clear, uint32_t mask)
117{
118 uint32_t new_val = (ldl_le_p(&s->csr[addr]) & ~clear) | mask;
119 stl_le_p(&s->csr[addr], new_val);
120 return new_val;
121}
122
123static uint64_t vtd_set_clear_mask_quad(IntelIOMMUState *s, hwaddr addr,
124 uint64_t clear, uint64_t mask)
125{
126 uint64_t new_val = (ldq_le_p(&s->csr[addr]) & ~clear) | mask;
127 stq_le_p(&s->csr[addr], new_val);
128 return new_val;
129}
130
b5a280c0
LT		 131/* GHashTable functions */
132static gboolean vtd_uint64_equal(gconstpointer v1, gconstpointer v2)
133{
134 return *((const uint64_t *)v1) == *((const uint64_t *)v2);
135}
136
137static guint vtd_uint64_hash(gconstpointer v)
138{
139 return (guint)*(const uint64_t *)v;
140}
141
142static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value,
143 gpointer user_data)
144{
145 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
146 uint16_t domain_id = *(uint16_t *)user_data;
147 return entry->domain_id == domain_id;
148}
149
d66b969b
JW		 150/* The shift of an addr for a certain level of paging structure */
151static inline uint32_t vtd_slpt_level_shift(uint32_t level)
152{
7e58326a 153 assert(level != 0);
d66b969b
JW		 154 return VTD_PAGE_SHIFT_4K + (level - 1) * VTD_SL_LEVEL_BITS;
155}
156
157static inline uint64_t vtd_slpt_level_page_mask(uint32_t level)
158{
159 return ~((1ULL << vtd_slpt_level_shift(level)) - 1);
160}
161
b5a280c0
LT		 162static gboolean vtd_hash_remove_by_page(gpointer key, gpointer value,
163 gpointer user_data)
164{
165 VTDIOTLBEntry *entry = (VTDIOTLBEntry *)value;
166 VTDIOTLBPageInvInfo *info = (VTDIOTLBPageInvInfo *)user_data;
d66b969b
JW		 167 uint64_t gfn = (info->addr >> VTD_PAGE_SHIFT_4K) & info->mask;
168 uint64_t gfn_tlb = (info->addr & entry->mask) >> VTD_PAGE_SHIFT_4K;
b5a280c0 169 return (entry->domain_id == info->domain_id) &&
d66b969b
JW		 170 (((entry->gfn & info->mask) == gfn) ||
171 (entry->gfn == gfn_tlb));
b5a280c0
LT		 172}
173
d92fa2dc
LT		 174/* Reset all the gen of VTDAddressSpace to zero and set the gen of
175 * IntelIOMMUState to 1.
176 */
177static void vtd_reset_context_cache(IntelIOMMUState *s)
178{
d92fa2dc 179 VTDAddressSpace *vtd_as;
7df953bd
KO		 180 VTDBus *vtd_bus;
181 GHashTableIter bus_it;
d92fa2dc
LT		 182 uint32_t devfn_it;
183
7feb51b7
PX		 184 trace_vtd_context_cache_reset();
185
7df953bd
KO		 186 g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr);
187
7df953bd 188 while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) {
bf33cc75 189 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 190 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc
LT		 191 if (!vtd_as) {
192 continue;
193 }
194 vtd_as->context_cache_entry.context_cache_gen = 0;
195 }
196 }
197 s->context_cache_gen = 1;
198}
199
b5a280c0
LT		 200static void vtd_reset_iotlb(IntelIOMMUState *s)
201{
202 assert(s->iotlb);
203 g_hash_table_remove_all(s->iotlb);
204}
205
bacabb0a 206static uint64_t vtd_get_iotlb_key(uint64_t gfn, uint16_t source_id,
d66b969b
JW		 207 uint32_t level)
208{
209 return gfn | ((uint64_t)(source_id) << VTD_IOTLB_SID_SHIFT) |
210 ((uint64_t)(level) << VTD_IOTLB_LVL_SHIFT);
211}
212
213static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)
214{
215 return (addr & vtd_slpt_level_page_mask(level)) >> VTD_PAGE_SHIFT_4K;
216}
217
b5a280c0
LT		 218static VTDIOTLBEntry *vtd_lookup_iotlb(IntelIOMMUState *s, uint16_t source_id,
219 hwaddr addr)
220{
d66b969b 221 VTDIOTLBEntry *entry;
b5a280c0 222 uint64_t key;
d66b969b
JW		 223 int level;
224
225 for (level = VTD_SL_PT_LEVEL; level < VTD_SL_PML4_LEVEL; level++) {
226 key = vtd_get_iotlb_key(vtd_get_iotlb_gfn(addr, level),
227 source_id, level);
228 entry = g_hash_table_lookup(s->iotlb, &key);
229 if (entry) {
230 goto out;
231 }
232 }
b5a280c0 233
d66b969b
JW		 234out:
235 return entry;
b5a280c0
LT		 236}
237
238static void vtd_update_iotlb(IntelIOMMUState *s, uint16_t source_id,
239 uint16_t domain_id, hwaddr addr, uint64_t slpte,
07f7b733 240 uint8_t access_flags, uint32_t level)
b5a280c0
LT		 241{
242 VTDIOTLBEntry *entry = g_malloc(sizeof(*entry));
243 uint64_t *key = g_malloc(sizeof(*key));
d66b969b 244 uint64_t gfn = vtd_get_iotlb_gfn(addr, level);
b5a280c0 245
6c441e1d 246 trace_vtd_iotlb_page_update(source_id, addr, slpte, domain_id);
b5a280c0 247 if (g_hash_table_size(s->iotlb) >= VTD_IOTLB_MAX_SIZE) {
6c441e1d 248 trace_vtd_iotlb_reset("iotlb exceeds size limit");
b5a280c0
LT		 249 vtd_reset_iotlb(s);
250 }
251
252 entry->gfn = gfn;
253 entry->domain_id = domain_id;
254 entry->slpte = slpte;
07f7b733 255 entry->access_flags = access_flags;
d66b969b
JW		 256 entry->mask = vtd_slpt_level_page_mask(level);
257 *key = vtd_get_iotlb_key(gfn, source_id, level);
b5a280c0
LT		 258 g_hash_table_replace(s->iotlb, key, entry);
259}
260
1da12ec4
LT		 261/* Given the reg addr of both the message data and address, generate an
262 * interrupt via MSI.
263 */
264static void vtd_generate_interrupt(IntelIOMMUState *s, hwaddr mesg_addr_reg,
265 hwaddr mesg_data_reg)
266{
32946019 267 MSIMessage msi;
1da12ec4
LT		 268
269 assert(mesg_data_reg < DMAR_REG_SIZE);
270 assert(mesg_addr_reg < DMAR_REG_SIZE);
271
32946019
RK		 272 msi.address = vtd_get_long_raw(s, mesg_addr_reg);
273 msi.data = vtd_get_long_raw(s, mesg_data_reg);
1da12ec4 274
7feb51b7
PX		 275 trace_vtd_irq_generate(msi.address, msi.data);
276
32946019 277 apic_get_class()->send_msi(&msi);
1da12ec4
LT		 278}
279
280/* Generate a fault event to software via MSI if conditions are met.
281 * Notice that the value of FSTS_REG being passed to it should be the one
282 * before any update.
283 */
284static void vtd_generate_fault_event(IntelIOMMUState *s, uint32_t pre_fsts)
285{
286 if (pre_fsts & VTD_FSTS_PPF || pre_fsts & VTD_FSTS_PFO ||
287 pre_fsts & VTD_FSTS_IQE) {
7feb51b7
PX		 288 trace_vtd_err("There are previous interrupt conditions "
289 "to be serviced by software, fault event "
290 "is not generated.");
1da12ec4
LT		 291 return;
292 }
293 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, 0, VTD_FECTL_IP);
294 if (vtd_get_long_raw(s, DMAR_FECTL_REG) & VTD_FECTL_IM) {
7feb51b7 295 trace_vtd_err("Interrupt Mask set, irq is not generated.");
1da12ec4
LT		 296 } else {
297 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
298 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
299 }
300}
301
302/* Check if the Fault (F) field of the Fault Recording Register referenced by
303 * @index is Set.
304 */
305static bool vtd_is_frcd_set(IntelIOMMUState *s, uint16_t index)
306{
307 /* Each reg is 128-bit */
308 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
309 addr += 8; /* Access the high 64-bit half */
310
311 assert(index < DMAR_FRCD_REG_NR);
312
313 return vtd_get_quad_raw(s, addr) & VTD_FRCD_F;
314}
315
316/* Update the PPF field of Fault Status Register.
317 * Should be called whenever change the F field of any fault recording
318 * registers.
319 */
320static void vtd_update_fsts_ppf(IntelIOMMUState *s)
321{
322 uint32_t i;
323 uint32_t ppf_mask = 0;
324
325 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
326 if (vtd_is_frcd_set(s, i)) {
327 ppf_mask = VTD_FSTS_PPF;
328 break;
329 }
330 }
331 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_PPF, ppf_mask);
7feb51b7 332 trace_vtd_fsts_ppf(!!ppf_mask);
1da12ec4
LT		 333}
334
335static void vtd_set_frcd_and_update_ppf(IntelIOMMUState *s, uint16_t index)
336{
337 /* Each reg is 128-bit */
338 hwaddr addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
339 addr += 8; /* Access the high 64-bit half */
340
341 assert(index < DMAR_FRCD_REG_NR);
342
343 vtd_set_clear_mask_quad(s, addr, 0, VTD_FRCD_F);
344 vtd_update_fsts_ppf(s);
345}
346
347/* Must not update F field now, should be done later */
348static void vtd_record_frcd(IntelIOMMUState *s, uint16_t index,
349 uint16_t source_id, hwaddr addr,
350 VTDFaultReason fault, bool is_write)
351{
352 uint64_t hi = 0, lo;
353 hwaddr frcd_reg_addr = DMAR_FRCD_REG_OFFSET + (((uint64_t)index) << 4);
354
355 assert(index < DMAR_FRCD_REG_NR);
356
357 lo = VTD_FRCD_FI(addr);
358 hi = VTD_FRCD_SID(source_id) | VTD_FRCD_FR(fault);
359 if (!is_write) {
360 hi |= VTD_FRCD_T;
361 }
362 vtd_set_quad_raw(s, frcd_reg_addr, lo);
363 vtd_set_quad_raw(s, frcd_reg_addr + 8, hi);
7feb51b7
PX		 364
365 trace_vtd_frr_new(index, hi, lo);
1da12ec4
LT		 366}
367
368/* Try to collapse multiple pending faults from the same requester */
369static bool vtd_try_collapse_fault(IntelIOMMUState *s, uint16_t source_id)
370{
371 uint32_t i;
372 uint64_t frcd_reg;
373 hwaddr addr = DMAR_FRCD_REG_OFFSET + 8; /* The high 64-bit half */
374
375 for (i = 0; i < DMAR_FRCD_REG_NR; i++) {
376 frcd_reg = vtd_get_quad_raw(s, addr);
1da12ec4
LT		 377 if ((frcd_reg & VTD_FRCD_F) &&
378 ((frcd_reg & VTD_FRCD_SID_MASK) == source_id)) {
379 return true;
380 }
381 addr += 16; /* 128-bit for each */
382 }
383 return false;
384}
385
386/* Log and report an DMAR (address translation) fault to software */
387static void vtd_report_dmar_fault(IntelIOMMUState *s, uint16_t source_id,
388 hwaddr addr, VTDFaultReason fault,
389 bool is_write)
390{
391 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
392
393 assert(fault < VTD_FR_MAX);
394
395 if (fault == VTD_FR_RESERVED_ERR) {
396 /* This is not a normal fault reason case. Drop it. */
397 return;
398 }
7feb51b7
PX		 399
400 trace_vtd_dmar_fault(source_id, fault, addr, is_write);
401
1da12ec4 402 if (fsts_reg & VTD_FSTS_PFO) {
7feb51b7
PX		 403 trace_vtd_err("New fault is not recorded due to "
404 "Primary Fault Overflow.");
1da12ec4
LT		 405 return;
406 }
7feb51b7 407
1da12ec4 408 if (vtd_try_collapse_fault(s, source_id)) {
7feb51b7
PX		 409 trace_vtd_err("New fault is not recorded due to "
410 "compression of faults.");
1da12ec4
LT		 411 return;
412 }
7feb51b7 413
1da12ec4 414 if (vtd_is_frcd_set(s, s->next_frcd_reg)) {
7feb51b7
PX		 415 trace_vtd_err("Next Fault Recording Reg is used, "
416 "new fault is not recorded, set PFO field.");
1da12ec4
LT		 417 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_PFO);
418 return;
419 }
420
421 vtd_record_frcd(s, s->next_frcd_reg, source_id, addr, fault, is_write);
422
423 if (fsts_reg & VTD_FSTS_PPF) {
7feb51b7
PX		 424 trace_vtd_err("There are pending faults already, "
425 "fault event is not generated.");
1da12ec4
LT		 426 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg);
427 s->next_frcd_reg++;
428 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
429 s->next_frcd_reg = 0;
430 }
431 } else {
432 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, VTD_FSTS_FRI_MASK,
433 VTD_FSTS_FRI(s->next_frcd_reg));
434 vtd_set_frcd_and_update_ppf(s, s->next_frcd_reg); /* Will set PPF */
435 s->next_frcd_reg++;
436 if (s->next_frcd_reg == DMAR_FRCD_REG_NR) {
437 s->next_frcd_reg = 0;
438 }
439 /* This case actually cause the PPF to be Set.
440 * So generate fault event (interrupt).
441 */
442 vtd_generate_fault_event(s, fsts_reg);
443 }
444}
445
ed7b8fbc
LT		 446/* Handle Invalidation Queue Errors of queued invalidation interface error
447 * conditions.
448 */
449static void vtd_handle_inv_queue_error(IntelIOMMUState *s)
450{
451 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
452
453 vtd_set_clear_mask_long(s, DMAR_FSTS_REG, 0, VTD_FSTS_IQE);
454 vtd_generate_fault_event(s, fsts_reg);
455}
456
457/* Set the IWC field and try to generate an invalidation completion interrupt */
458static void vtd_generate_completion_event(IntelIOMMUState *s)
459{
ed7b8fbc 460 if (vtd_get_long_raw(s, DMAR_ICS_REG) & VTD_ICS_IWC) {
bc535e59 461 trace_vtd_inv_desc_wait_irq("One pending, skip current");
ed7b8fbc
LT		 462 return;
463 }
464 vtd_set_clear_mask_long(s, DMAR_ICS_REG, 0, VTD_ICS_IWC);
465 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, 0, VTD_IECTL_IP);
466 if (vtd_get_long_raw(s, DMAR_IECTL_REG) & VTD_IECTL_IM) {
bc535e59
PX		 467 trace_vtd_inv_desc_wait_irq("IM in IECTL_REG is set, "
468 "new event not generated");
ed7b8fbc
LT		 469 return;
470 } else {
471 /* Generate the interrupt event */
bc535e59 472 trace_vtd_inv_desc_wait_irq("Generating complete event");
ed7b8fbc
LT		 473 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
474 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
475 }
476}
477
1da12ec4
LT		 478static inline bool vtd_root_entry_present(VTDRootEntry *root)
479{
480 return root->val & VTD_ROOT_ENTRY_P;
481}
482
483static int vtd_get_root_entry(IntelIOMMUState *s, uint8_t index,
484 VTDRootEntry *re)
485{
486 dma_addr_t addr;
487
488 addr = s->root + index * sizeof(*re);
489 if (dma_memory_read(&address_space_memory, addr, re, sizeof(*re))) {
6c441e1d 490 trace_vtd_re_invalid(re->rsvd, re->val);
1da12ec4
LT		 491 re->val = 0;
492 return -VTD_FR_ROOT_TABLE_INV;
493 }
494 re->val = le64_to_cpu(re->val);
495 return 0;
496}
497
8f7d7161 498static inline bool vtd_ce_present(VTDContextEntry *context)
1da12ec4
LT		 499{
500 return context->lo & VTD_CONTEXT_ENTRY_P;
501}
502
503static int vtd_get_context_entry_from_root(VTDRootEntry *root, uint8_t index,
504 VTDContextEntry *ce)
505{
506 dma_addr_t addr;
507
6c441e1d 508 /* we have checked that root entry is present */
1da12ec4
LT		 509 addr = (root->val & VTD_ROOT_ENTRY_CTP) + index * sizeof(*ce);
510 if (dma_memory_read(&address_space_memory, addr, ce, sizeof(*ce))) {
6c441e1d 511 trace_vtd_re_invalid(root->rsvd, root->val);
1da12ec4
LT		 512 return -VTD_FR_CONTEXT_TABLE_INV;
513 }
514 ce->lo = le64_to_cpu(ce->lo);
515 ce->hi = le64_to_cpu(ce->hi);
516 return 0;
517}
518
8f7d7161 519static inline dma_addr_t vtd_ce_get_slpt_base(VTDContextEntry *ce)
1da12ec4
LT		 520{
521 return ce->lo & VTD_CONTEXT_ENTRY_SLPTPTR;
522}
523
37f51384 524static inline uint64_t vtd_get_slpte_addr(uint64_t slpte, uint8_t aw)
1da12ec4 525{
37f51384 526 return slpte & VTD_SL_PT_BASE_ADDR_MASK(aw);
1da12ec4
LT		 527}
528
529/* Whether the pte indicates the address of the page frame */
530static inline bool vtd_is_last_slpte(uint64_t slpte, uint32_t level)
531{
532 return level == VTD_SL_PT_LEVEL || (slpte & VTD_SL_PT_PAGE_SIZE_MASK);
533}
534
535/* Get the content of a spte located in @base_addr[@index] */
536static uint64_t vtd_get_slpte(dma_addr_t base_addr, uint32_t index)
537{
538 uint64_t slpte;
539
540 assert(index < VTD_SL_PT_ENTRY_NR);
541
542 if (dma_memory_read(&address_space_memory,
543 base_addr + index * sizeof(slpte), &slpte,
544 sizeof(slpte))) {
545 slpte = (uint64_t)-1;
546 return slpte;
547 }
548 slpte = le64_to_cpu(slpte);
549 return slpte;
550}
551
6e905564
PX		 552/* Given an iova and the level of paging structure, return the offset
553 * of current level.
1da12ec4 554 */
6e905564 555static inline uint32_t vtd_iova_level_offset(uint64_t iova, uint32_t level)
1da12ec4 556{
6e905564 557 return (iova >> vtd_slpt_level_shift(level)) &
1da12ec4
LT		 558 ((1ULL << VTD_SL_LEVEL_BITS) - 1);
559}
560
561/* Check Capability Register to see if the @level of page-table is supported */
562static inline bool vtd_is_level_supported(IntelIOMMUState *s, uint32_t level)
563{
564 return VTD_CAP_SAGAW_MASK & s->cap &
565 (1ULL << (level - 2 + VTD_CAP_SAGAW_SHIFT));
566}
567
568/* Get the page-table level that hardware should use for the second-level
569 * page-table walk from the Address Width field of context-entry.
570 */
8f7d7161 571static inline uint32_t vtd_ce_get_level(VTDContextEntry *ce)
1da12ec4
LT		 572{
573 return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
574}
575
8f7d7161 576static inline uint32_t vtd_ce_get_agaw(VTDContextEntry *ce)
1da12ec4
LT		 577{
578 return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
579}
580
127ff5c3
PX		 581static inline uint32_t vtd_ce_get_type(VTDContextEntry *ce)
582{
583 return ce->lo & VTD_CONTEXT_ENTRY_TT;
584}
585
f80c9874
PX		 586/* Return true if check passed, otherwise false */
587static inline bool vtd_ce_type_check(X86IOMMUState *x86_iommu,
588 VTDContextEntry *ce)
589{
590 switch (vtd_ce_get_type(ce)) {
591 case VTD_CONTEXT_TT_MULTI_LEVEL:
592 /* Always supported */
593 break;
594 case VTD_CONTEXT_TT_DEV_IOTLB:
595 if (!x86_iommu->dt_supported) {
596 return false;
597 }
598 break;
dbaabb25
PX		 599 case VTD_CONTEXT_TT_PASS_THROUGH:
600 if (!x86_iommu->pt_supported) {
601 return false;
602 }
603 break;
f80c9874
PX		 604 default:
605 /* Unknwon type */
606 return false;
607 }
608 return true;
609}
610
37f51384 611static inline uint64_t vtd_iova_limit(VTDContextEntry *ce, uint8_t aw)
f06a696d 612{
8f7d7161 613 uint32_t ce_agaw = vtd_ce_get_agaw(ce);
37f51384 614 return 1ULL << MIN(ce_agaw, aw);
f06a696d
PX		 615}
616
617/* Return true if IOVA passes range check, otherwise false. */
37f51384
PS		 618static inline bool vtd_iova_range_check(uint64_t iova, VTDContextEntry *ce,
619 uint8_t aw)
f06a696d
PX		 620{
621 /*
622 * Check if @iova is above 2^X-1, where X is the minimum of MGAW
623 * in CAP_REG and AW in context-entry.
624 */
37f51384 625 return !(iova & ~(vtd_iova_limit(ce, aw) - 1));
f06a696d
PX		 626}
627
92e5d85e
PS		 628/*
629 * Rsvd field masks for spte:
630 * Index [1] to [4] 4k pages
631 * Index [5] to [8] large pages
632 */
633static uint64_t vtd_paging_entry_rsvd_field[9];
1da12ec4
LT		 634
635static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, uint32_t level)
636{
637 if (slpte & VTD_SL_PT_PAGE_SIZE_MASK) {
638 /* Maybe large page */
639 return slpte & vtd_paging_entry_rsvd_field[level + 4];
640 } else {
641 return slpte & vtd_paging_entry_rsvd_field[level];
642 }
643}
644
dbaabb25
PX		 645/* Find the VTD address space associated with a given bus number */
646static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_num)
647{
648 VTDBus *vtd_bus = s->vtd_as_by_bus_num[bus_num];
649 if (!vtd_bus) {
650 /*
651 * Iterate over the registered buses to find the one which
652 * currently hold this bus number, and update the bus_num
653 * lookup table:
654 */
655 GHashTableIter iter;
656
657 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
658 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
659 if (pci_bus_num(vtd_bus->bus) == bus_num) {
660 s->vtd_as_by_bus_num[bus_num] = vtd_bus;
661 return vtd_bus;
662 }
663 }
664 }
665 return vtd_bus;
666}
667
6e905564 668/* Given the @iova, get relevant @slptep. @slpte_level will be the last level
1da12ec4
LT		 669 * of the translation, can be used for deciding the size of large page.
670 */
6e905564
PX		 671static int vtd_iova_to_slpte(VTDContextEntry *ce, uint64_t iova, bool is_write,
672 uint64_t *slptep, uint32_t *slpte_level,
37f51384 673 bool *reads, bool *writes, uint8_t aw_bits)
1da12ec4 674{
8f7d7161
PX		 675 dma_addr_t addr = vtd_ce_get_slpt_base(ce);
676 uint32_t level = vtd_ce_get_level(ce);
1da12ec4
LT		 677 uint32_t offset;
678 uint64_t slpte;
1da12ec4
LT		 679 uint64_t access_right_check;
680
37f51384 681 if (!vtd_iova_range_check(iova, ce, aw_bits)) {
7feb51b7 682 trace_vtd_err_dmar_iova_overflow(iova);
1da12ec4
LT		 683 return -VTD_FR_ADDR_BEYOND_MGAW;
684 }
685
686 /* FIXME: what is the Atomics request here? */
687 access_right_check = is_write ? VTD_SL_W : VTD_SL_R;
688
689 while (true) {
6e905564 690 offset = vtd_iova_level_offset(iova, level);
1da12ec4
LT		 691 slpte = vtd_get_slpte(addr, offset);
692
693 if (slpte == (uint64_t)-1) {
7feb51b7 694 trace_vtd_err_dmar_slpte_read_error(iova, level);
8f7d7161 695 if (level == vtd_ce_get_level(ce)) {
1da12ec4
LT		 696 /* Invalid programming of context-entry */
697 return -VTD_FR_CONTEXT_ENTRY_INV;
698 } else {
699 return -VTD_FR_PAGING_ENTRY_INV;
700 }
701 }
702 *reads = (*reads) && (slpte & VTD_SL_R);
703 *writes = (*writes) && (slpte & VTD_SL_W);
704 if (!(slpte & access_right_check)) {
7feb51b7 705 trace_vtd_err_dmar_slpte_perm_error(iova, level, slpte, is_write);
1da12ec4
LT		 706 return is_write ? -VTD_FR_WRITE : -VTD_FR_READ;
707 }
708 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
7feb51b7 709 trace_vtd_err_dmar_slpte_resv_error(iova, level, slpte);
1da12ec4
LT		 710 return -VTD_FR_PAGING_ENTRY_RSVD;
711 }
712
713 if (vtd_is_last_slpte(slpte, level)) {
714 *slptep = slpte;
715 *slpte_level = level;
716 return 0;
717 }
37f51384 718 addr = vtd_get_slpte_addr(slpte, aw_bits);
1da12ec4
LT		 719 level--;
720 }
721}
722
f06a696d
PX		 723typedef int (*vtd_page_walk_hook)(IOMMUTLBEntry *entry, void *private);
724
36d2d52b
PX		 725static int vtd_page_walk_one(IOMMUTLBEntry *entry, int level,
726 vtd_page_walk_hook hook_fn, void *private)
727{
728 assert(hook_fn);
729 trace_vtd_page_walk_one(level, entry->iova, entry->translated_addr,
730 entry->addr_mask, entry->perm);
731 return hook_fn(entry, private);
732}
733
f06a696d
PX		 734/**
735 * vtd_page_walk_level - walk over specific level for IOVA range
736 *
737 * @addr: base GPA addr to start the walk
738 * @start: IOVA range start address
739 * @end: IOVA range end address (start <= addr < end)
740 * @hook_fn: hook func to be called when detected page
741 * @private: private data to be passed into hook func
742 * @read: whether parent level has read permission
743 * @write: whether parent level has write permission
744 * @notify_unmap: whether we should notify invalid entries
37f51384 745 * @aw: maximum address width
f06a696d
PX		 746 */
747static int vtd_page_walk_level(dma_addr_t addr, uint64_t start,
748 uint64_t end, vtd_page_walk_hook hook_fn,
37f51384
PS		 749 void *private, uint32_t level, bool read,
750 bool write, bool notify_unmap, uint8_t aw)
f06a696d
PX		 751{
752 bool read_cur, write_cur, entry_valid;
753 uint32_t offset;
754 uint64_t slpte;
755 uint64_t subpage_size, subpage_mask;
756 IOMMUTLBEntry entry;
757 uint64_t iova = start;
758 uint64_t iova_next;
759 int ret = 0;
760
761 trace_vtd_page_walk_level(addr, level, start, end);
762
763 subpage_size = 1ULL << vtd_slpt_level_shift(level);
764 subpage_mask = vtd_slpt_level_page_mask(level);
765
766 while (iova < end) {
767 iova_next = (iova & subpage_mask) + subpage_size;
768
769 offset = vtd_iova_level_offset(iova, level);
770 slpte = vtd_get_slpte(addr, offset);
771
772 if (slpte == (uint64_t)-1) {
773 trace_vtd_page_walk_skip_read(iova, iova_next);
774 goto next;
775 }
776
777 if (vtd_slpte_nonzero_rsvd(slpte, level)) {
778 trace_vtd_page_walk_skip_reserve(iova, iova_next);
779 goto next;
780 }
781
782 /* Permissions are stacked with parents' */
783 read_cur = read && (slpte & VTD_SL_R);
784 write_cur = write && (slpte & VTD_SL_W);
785
786 /*
787 * As long as we have either read/write permission, this is a
788 * valid entry. The rule works for both page entries and page
789 * table entries.
790 */
791 entry_valid = read_cur | write_cur;
792
36d2d52b
PX		 793 entry.target_as = &address_space_memory;
794 entry.iova = iova & subpage_mask;
795 entry.perm = IOMMU_ACCESS_FLAG(read_cur, write_cur);
796 entry.addr_mask = ~subpage_mask;
797
f06a696d 798 if (vtd_is_last_slpte(slpte, level)) {
f06a696d 799 /* NOTE: this is only meaningful if entry_valid == true */
37f51384 800 entry.translated_addr = vtd_get_slpte_addr(slpte, aw);
f06a696d
PX		 801 if (!entry_valid && !notify_unmap) {
802 trace_vtd_page_walk_skip_perm(iova, iova_next);
803 goto next;
804 }
36d2d52b
PX		 805 ret = vtd_page_walk_one(&entry, level, hook_fn, private);
806 if (ret < 0) {
807 return ret;
f06a696d
PX		 808 }
809 } else {
810 if (!entry_valid) {
36d2d52b
PX		 811 if (notify_unmap) {
812 /*
813 * The whole entry is invalid; unmap it all.
814 * Translated address is meaningless, zero it.
815 */
816 entry.translated_addr = 0x0;
817 ret = vtd_page_walk_one(&entry, level, hook_fn, private);
818 if (ret < 0) {
819 return ret;
820 }
821 } else {
822 trace_vtd_page_walk_skip_perm(iova, iova_next);
823 }
f06a696d
PX		 824 goto next;
825 }
37f51384 826 ret = vtd_page_walk_level(vtd_get_slpte_addr(slpte, aw), iova,
f06a696d
PX		 827 MIN(iova_next, end), hook_fn, private,
828 level - 1, read_cur, write_cur,
37f51384 829 notify_unmap, aw);
f06a696d
PX		 830 if (ret < 0) {
831 return ret;
832 }
833 }
834
835next:
836 iova = iova_next;
837 }
838
839 return 0;
840}
841
842/**
843 * vtd_page_walk - walk specific IOVA range, and call the hook
844 *
845 * @ce: context entry to walk upon
846 * @start: IOVA address to start the walk
847 * @end: IOVA range end address (start <= addr < end)
848 * @hook_fn: the hook that to be called for each detected area
849 * @private: private data for the hook function
37f51384 850 * @aw: maximum address width
f06a696d
PX		 851 */
852static int vtd_page_walk(VTDContextEntry *ce, uint64_t start, uint64_t end,
dd4d607e 853 vtd_page_walk_hook hook_fn, void *private,
37f51384 854 bool notify_unmap, uint8_t aw)
f06a696d 855{
8f7d7161
PX		 856 dma_addr_t addr = vtd_ce_get_slpt_base(ce);
857 uint32_t level = vtd_ce_get_level(ce);
f06a696d 858
37f51384 859 if (!vtd_iova_range_check(start, ce, aw)) {
f06a696d
PX		 860 return -VTD_FR_ADDR_BEYOND_MGAW;
861 }
862
37f51384 863 if (!vtd_iova_range_check(end, ce, aw)) {
f06a696d 864 /* Fix end so that it reaches the maximum */
37f51384 865 end = vtd_iova_limit(ce, aw);
f06a696d
PX		 866 }
867
868 return vtd_page_walk_level(addr, start, end, hook_fn, private,
37f51384 869 level, true, true, notify_unmap, aw);
f06a696d
PX		 870}
871
1da12ec4
LT		 872/* Map a device to its corresponding domain (context-entry) */
873static int vtd_dev_to_context_entry(IntelIOMMUState *s, uint8_t bus_num,
874 uint8_t devfn, VTDContextEntry *ce)
875{
876 VTDRootEntry re;
877 int ret_fr;
f80c9874 878 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
1da12ec4
LT		 879
880 ret_fr = vtd_get_root_entry(s, bus_num, &re);
881 if (ret_fr) {
882 return ret_fr;
883 }
884
885 if (!vtd_root_entry_present(&re)) {
6c441e1d
PX		 886 /* Not error - it's okay we don't have root entry. */
887 trace_vtd_re_not_present(bus_num);
1da12ec4 888 return -VTD_FR_ROOT_ENTRY_P;
f80c9874
PX		 889 }
890
37f51384 891 if (re.rsvd || (re.val & VTD_ROOT_ENTRY_RSVD(s->aw_bits))) {
6c441e1d 892 trace_vtd_re_invalid(re.rsvd, re.val);
1da12ec4
LT		 893 return -VTD_FR_ROOT_ENTRY_RSVD;
894 }
895
896 ret_fr = vtd_get_context_entry_from_root(&re, devfn, ce);
897 if (ret_fr) {
898 return ret_fr;
899 }
900
8f7d7161 901 if (!vtd_ce_present(ce)) {
6c441e1d
PX		 902 /* Not error - it's okay we don't have context entry. */
903 trace_vtd_ce_not_present(bus_num, devfn);
1da12ec4 904 return -VTD_FR_CONTEXT_ENTRY_P;
f80c9874
PX		 905 }
906
907 if ((ce->hi & VTD_CONTEXT_ENTRY_RSVD_HI) ||
37f51384 908 (ce->lo & VTD_CONTEXT_ENTRY_RSVD_LO(s->aw_bits))) {
6c441e1d 909 trace_vtd_ce_invalid(ce->hi, ce->lo);
1da12ec4
LT		 910 return -VTD_FR_CONTEXT_ENTRY_RSVD;
911 }
f80c9874 912
1da12ec4 913 /* Check if the programming of context-entry is valid */
8f7d7161 914 if (!vtd_is_level_supported(s, vtd_ce_get_level(ce))) {
6c441e1d 915 trace_vtd_ce_invalid(ce->hi, ce->lo);
1da12ec4 916 return -VTD_FR_CONTEXT_ENTRY_INV;
1da12ec4 917 }
f80c9874
PX		 918
919 /* Do translation type check */
920 if (!vtd_ce_type_check(x86_iommu, ce)) {
921 trace_vtd_ce_invalid(ce->hi, ce->lo);
922 return -VTD_FR_CONTEXT_ENTRY_INV;
923 }
924
1da12ec4
LT		 925 return 0;
926}
927
dbaabb25
PX		 928/*
929 * Fetch translation type for specific device. Returns <0 if error
930 * happens, otherwise return the shifted type to check against
931 * VTD_CONTEXT_TT_*.
932 */
933static int vtd_dev_get_trans_type(VTDAddressSpace *as)
934{
935 IntelIOMMUState *s;
936 VTDContextEntry ce;
937 int ret;
938
939 s = as->iommu_state;
940
941 ret = vtd_dev_to_context_entry(s, pci_bus_num(as->bus),
942 as->devfn, &ce);
943 if (ret) {
944 return ret;
945 }
946
947 return vtd_ce_get_type(&ce);
948}
949
950static bool vtd_dev_pt_enabled(VTDAddressSpace *as)
951{
952 int ret;
953
954 assert(as);
955
956 ret = vtd_dev_get_trans_type(as);
957 if (ret < 0) {
958 /*
959 * Possibly failed to parse the context entry for some reason
960 * (e.g., during init, or any guest configuration errors on
961 * context entries). We should assume PT not enabled for
962 * safety.
963 */
964 return false;
965 }
966
967 return ret == VTD_CONTEXT_TT_PASS_THROUGH;
968}
969
970/* Return whether the device is using IOMMU translation. */
971static bool vtd_switch_address_space(VTDAddressSpace *as)
972{
973 bool use_iommu;
66a4a031
PX		 974 /* Whether we need to take the BQL on our own */
975 bool take_bql = !qemu_mutex_iothread_locked();
dbaabb25
PX		 976
977 assert(as);
978
979 use_iommu = as->iommu_state->dmar_enabled & !vtd_dev_pt_enabled(as);
980
981 trace_vtd_switch_address_space(pci_bus_num(as->bus),
982 VTD_PCI_SLOT(as->devfn),
983 VTD_PCI_FUNC(as->devfn),
984 use_iommu);
985
66a4a031
PX		 986 /*
987 * It's possible that we reach here without BQL, e.g., when called
988 * from vtd_pt_enable_fast_path(). However the memory APIs need
989 * it. We'd better make sure we have had it already, or, take it.
990 */
991 if (take_bql) {
992 qemu_mutex_lock_iothread();
993 }
994
dbaabb25
PX		 995 /* Turn off first then on the other */
996 if (use_iommu) {
997 memory_region_set_enabled(&as->sys_alias, false);
3df9d748 998 memory_region_set_enabled(MEMORY_REGION(&as->iommu), true);
dbaabb25 999 } else {
3df9d748 1000 memory_region_set_enabled(MEMORY_REGION(&as->iommu), false);
dbaabb25
PX		 1001 memory_region_set_enabled(&as->sys_alias, true);
1002 }
1003
66a4a031
PX		 1004 if (take_bql) {
1005 qemu_mutex_unlock_iothread();
1006 }
1007
dbaabb25
PX		 1008 return use_iommu;
1009}
1010
1011static void vtd_switch_address_space_all(IntelIOMMUState *s)
1012{
1013 GHashTableIter iter;
1014 VTDBus *vtd_bus;
1015 int i;
1016
1017 g_hash_table_iter_init(&iter, s->vtd_as_by_busptr);
1018 while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) {
bf33cc75 1019 for (i = 0; i < PCI_DEVFN_MAX; i++) {
dbaabb25
PX		 1020 if (!vtd_bus->dev_as[i]) {
1021 continue;
1022 }
1023 vtd_switch_address_space(vtd_bus->dev_as[i]);
1024 }
1025 }
1026}
1027
1da12ec4
LT		 1028static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn)
1029{
1030 return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL);
1031}
1032
1033static const bool vtd_qualified_faults[] = {
1034 [VTD_FR_RESERVED] = false,
1035 [VTD_FR_ROOT_ENTRY_P] = false,
1036 [VTD_FR_CONTEXT_ENTRY_P] = true,
1037 [VTD_FR_CONTEXT_ENTRY_INV] = true,
1038 [VTD_FR_ADDR_BEYOND_MGAW] = true,
1039 [VTD_FR_WRITE] = true,
1040 [VTD_FR_READ] = true,
1041 [VTD_FR_PAGING_ENTRY_INV] = true,
1042 [VTD_FR_ROOT_TABLE_INV] = false,
1043 [VTD_FR_CONTEXT_TABLE_INV] = false,
1044 [VTD_FR_ROOT_ENTRY_RSVD] = false,
1045 [VTD_FR_PAGING_ENTRY_RSVD] = true,
1046 [VTD_FR_CONTEXT_ENTRY_TT] = true,
1047 [VTD_FR_RESERVED_ERR] = false,
1048 [VTD_FR_MAX] = false,
1049};
1050
1051/* To see if a fault condition is "qualified", which is reported to software
1052 * only if the FPD field in the context-entry used to process the faulting
1053 * request is 0.
1054 */
1055static inline bool vtd_is_qualified_fault(VTDFaultReason fault)
1056{
1057 return vtd_qualified_faults[fault];
1058}
1059
1060static inline bool vtd_is_interrupt_addr(hwaddr addr)
1061{
1062 return VTD_INTERRUPT_ADDR_FIRST <= addr && addr <= VTD_INTERRUPT_ADDR_LAST;
1063}
1064
dbaabb25
PX		 1065static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id)
1066{
1067 VTDBus *vtd_bus;
1068 VTDAddressSpace *vtd_as;
1069 bool success = false;
1070
1071 vtd_bus = vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id));
1072 if (!vtd_bus) {
1073 goto out;
1074 }
1075
1076 vtd_as = vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)];
1077 if (!vtd_as) {
1078 goto out;
1079 }
1080
1081 if (vtd_switch_address_space(vtd_as) == false) {
1082 /* We switched off IOMMU region successfully. */
1083 success = true;
1084 }
1085
1086out:
1087 trace_vtd_pt_enable_fast_path(source_id, success);
1088}
1089
1da12ec4
LT		 1090/* Map dev to context-entry then do a paging-structures walk to do a iommu
1091 * translation.
79e2b9ae
PB		 1092 *
1093 * Called from RCU critical section.
1094 *
1da12ec4
LT		 1095 * @bus_num: The bus number
1096 * @devfn: The devfn, which is the combined of device and function number
1097 * @is_write: The access is a write operation
1098 * @entry: IOMMUTLBEntry that contain the addr to be translated and result
b9313021
PX		 1099 *
1100 * Returns true if translation is successful, otherwise false.
1da12ec4 1101 */
b9313021 1102static bool vtd_do_iommu_translate(VTDAddressSpace *vtd_as, PCIBus *bus,
1da12ec4
LT		 1103 uint8_t devfn, hwaddr addr, bool is_write,
1104 IOMMUTLBEntry *entry)
1105{
d92fa2dc 1106 IntelIOMMUState *s = vtd_as->iommu_state;
1da12ec4 1107 VTDContextEntry ce;
7df953bd 1108 uint8_t bus_num = pci_bus_num(bus);
d92fa2dc 1109 VTDContextCacheEntry *cc_entry = &vtd_as->context_cache_entry;
d66b969b 1110 uint64_t slpte, page_mask;
1da12ec4
LT		 1111 uint32_t level;
1112 uint16_t source_id = vtd_make_source_id(bus_num, devfn);
1113 int ret_fr;
1114 bool is_fpd_set = false;
1115 bool reads = true;
1116 bool writes = true;
07f7b733 1117 uint8_t access_flags;
b5a280c0 1118 VTDIOTLBEntry *iotlb_entry;
1da12ec4 1119
046ab7e9
PX		 1120 /*
1121 * We have standalone memory region for interrupt addresses, we
1122 * should never receive translation requests in this region.
1123 */
1124 assert(!vtd_is_interrupt_addr(addr));
1125
b5a280c0
LT		 1126 /* Try to fetch slpte form IOTLB */
1127 iotlb_entry = vtd_lookup_iotlb(s, source_id, addr);
1128 if (iotlb_entry) {
6c441e1d
PX		 1129 trace_vtd_iotlb_page_hit(source_id, addr, iotlb_entry->slpte,
1130 iotlb_entry->domain_id);
b5a280c0 1131 slpte = iotlb_entry->slpte;
07f7b733 1132 access_flags = iotlb_entry->access_flags;
d66b969b 1133 page_mask = iotlb_entry->mask;
b5a280c0
LT		 1134 goto out;
1135 }
b9313021 1136
d92fa2dc
LT		 1137 /* Try to fetch context-entry from cache first */
1138 if (cc_entry->context_cache_gen == s->context_cache_gen) {
6c441e1d
PX		 1139 trace_vtd_iotlb_cc_hit(bus_num, devfn, cc_entry->context_entry.hi,
1140 cc_entry->context_entry.lo,
1141 cc_entry->context_cache_gen);
d92fa2dc
LT		 1142 ce = cc_entry->context_entry;
1143 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1144 } else {
1145 ret_fr = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
1146 is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD;
1147 if (ret_fr) {
1148 ret_fr = -ret_fr;
1149 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
6c441e1d 1150 trace_vtd_fault_disabled();
d92fa2dc
LT		 1151 } else {
1152 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
1153 }
b9313021 1154 goto error;
1da12ec4 1155 }
d92fa2dc 1156 /* Update context-cache */
6c441e1d
PX		 1157 trace_vtd_iotlb_cc_update(bus_num, devfn, ce.hi, ce.lo,
1158 cc_entry->context_cache_gen,
1159 s->context_cache_gen);
d92fa2dc
LT		 1160 cc_entry->context_entry = ce;
1161 cc_entry->context_cache_gen = s->context_cache_gen;
1da12ec4
LT		 1162 }
1163
dbaabb25
PX		 1164 /*
1165 * We don't need to translate for pass-through context entries.
1166 * Also, let's ignore IOTLB caching as well for PT devices.
1167 */
1168 if (vtd_ce_get_type(&ce) == VTD_CONTEXT_TT_PASS_THROUGH) {
892721d9 1169 entry->iova = addr & VTD_PAGE_MASK_4K;
dbaabb25 1170 entry->translated_addr = entry->iova;
892721d9 1171 entry->addr_mask = ~VTD_PAGE_MASK_4K;
dbaabb25
PX		 1172 entry->perm = IOMMU_RW;
1173 trace_vtd_translate_pt(source_id, entry->iova);
1174
1175 /*
1176 * When this happens, it means firstly caching-mode is not
1177 * enabled, and this is the first passthrough translation for
1178 * the device. Let's enable the fast path for passthrough.
1179 *
1180 * When passthrough is disabled again for the device, we can
1181 * capture it via the context entry invalidation, then the
1182 * IOMMU region can be swapped back.
1183 */
1184 vtd_pt_enable_fast_path(s, source_id);
1185
b9313021 1186 return true;
dbaabb25
PX		 1187 }
1188
6e905564 1189 ret_fr = vtd_iova_to_slpte(&ce, addr, is_write, &slpte, &level,
37f51384 1190 &reads, &writes, s->aw_bits);
1da12ec4
LT		 1191 if (ret_fr) {
1192 ret_fr = -ret_fr;
1193 if (is_fpd_set && vtd_is_qualified_fault(ret_fr)) {
6c441e1d 1194 trace_vtd_fault_disabled();
1da12ec4
LT		 1195 } else {
1196 vtd_report_dmar_fault(s, source_id, addr, ret_fr, is_write);
1197 }
b9313021 1198 goto error;
1da12ec4
LT		 1199 }
1200
d66b969b 1201 page_mask = vtd_slpt_level_page_mask(level);
07f7b733 1202 access_flags = IOMMU_ACCESS_FLAG(reads, writes);
b5a280c0 1203 vtd_update_iotlb(s, source_id, VTD_CONTEXT_ENTRY_DID(ce.hi), addr, slpte,
07f7b733 1204 access_flags, level);
b5a280c0 1205out:
d66b969b 1206 entry->iova = addr & page_mask;
37f51384 1207 entry->translated_addr = vtd_get_slpte_addr(slpte, s->aw_bits) & page_mask;
d66b969b 1208 entry->addr_mask = ~page_mask;
07f7b733 1209 entry->perm = access_flags;
b9313021
PX		 1210 return true;
1211
1212error:
1213 entry->iova = 0;
1214 entry->translated_addr = 0;
1215 entry->addr_mask = 0;
1216 entry->perm = IOMMU_NONE;
1217 return false;
1da12ec4
LT		 1218}
1219
1220static void vtd_root_table_setup(IntelIOMMUState *s)
1221{
1222 s->root = vtd_get_quad_raw(s, DMAR_RTADDR_REG);
1223 s->root_extended = s->root & VTD_RTADDR_RTT;
37f51384 1224 s->root &= VTD_RTADDR_ADDR_MASK(s->aw_bits);
1da12ec4 1225
7feb51b7 1226 trace_vtd_reg_dmar_root(s->root, s->root_extended);
1da12ec4
LT		 1227}
1228
02a2cbc8
PX		 1229static void vtd_iec_notify_all(IntelIOMMUState *s, bool global,
1230 uint32_t index, uint32_t mask)
1231{
1232 x86_iommu_iec_notify_all(X86_IOMMU_DEVICE(s), global, index, mask);
1233}
1234
a5861439
PX		 1235static void vtd_interrupt_remap_table_setup(IntelIOMMUState *s)
1236{
1237 uint64_t value = 0;
1238 value = vtd_get_quad_raw(s, DMAR_IRTA_REG);
1239 s->intr_size = 1UL << ((value & VTD_IRTA_SIZE_MASK) + 1);
37f51384 1240 s->intr_root = value & VTD_IRTA_ADDR_MASK(s->aw_bits);
28589311 1241 s->intr_eime = value & VTD_IRTA_EIME;
a5861439 1242
02a2cbc8
PX		 1243 /* Notify global invalidation */
1244 vtd_iec_notify_all(s, true, 0, 0);
a5861439 1245
7feb51b7 1246 trace_vtd_reg_ir_root(s->intr_root, s->intr_size);
a5861439
PX		 1247}
1248
dd4d607e
PX		 1249static void vtd_iommu_replay_all(IntelIOMMUState *s)
1250{
1251 IntelIOMMUNotifierNode *node;
1252
1253 QLIST_FOREACH(node, &s->notifiers_list, next) {
1254 memory_region_iommu_replay_all(&node->vtd_as->iommu);
1255 }
1256}
1257
d92fa2dc
LT		 1258static void vtd_context_global_invalidate(IntelIOMMUState *s)
1259{
bc535e59 1260 trace_vtd_inv_desc_cc_global();
d92fa2dc
LT		 1261 s->context_cache_gen++;
1262 if (s->context_cache_gen == VTD_CONTEXT_CACHE_GEN_MAX) {
1263 vtd_reset_context_cache(s);
1264 }
dbaabb25 1265 vtd_switch_address_space_all(s);
dd4d607e
PX		 1266 /*
1267 * From VT-d spec 6.5.2.1, a global context entry invalidation
1268 * should be followed by a IOTLB global invalidation, so we should
1269 * be safe even without this. Hoewever, let's replay the region as
1270 * well to be safer, and go back here when we need finer tunes for
1271 * VT-d emulation codes.
1272 */
1273 vtd_iommu_replay_all(s);
d92fa2dc
LT		 1274}
1275
1276/* Do a context-cache device-selective invalidation.
1277 * @func_mask: FM field after shifting
1278 */
1279static void vtd_context_device_invalidate(IntelIOMMUState *s,
1280 uint16_t source_id,
1281 uint16_t func_mask)
1282{
1283 uint16_t mask;
7df953bd 1284 VTDBus *vtd_bus;
d92fa2dc 1285 VTDAddressSpace *vtd_as;
bc535e59 1286 uint8_t bus_n, devfn;
d92fa2dc
LT		 1287 uint16_t devfn_it;
1288
bc535e59
PX		 1289 trace_vtd_inv_desc_cc_devices(source_id, func_mask);
1290
d92fa2dc
LT		 1291 switch (func_mask & 3) {
1292 case 0:
1293 mask = 0; /* No bits in the SID field masked */
1294 break;
1295 case 1:
1296 mask = 4; /* Mask bit 2 in the SID field */
1297 break;
1298 case 2:
1299 mask = 6; /* Mask bit 2:1 in the SID field */
1300 break;
1301 case 3:
1302 mask = 7; /* Mask bit 2:0 in the SID field */
1303 break;
1304 }
6cb99acc 1305 mask = ~mask;
bc535e59
PX		 1306
1307 bus_n = VTD_SID_TO_BUS(source_id);
1308 vtd_bus = vtd_find_as_from_bus_num(s, bus_n);
7df953bd 1309 if (vtd_bus) {
d92fa2dc 1310 devfn = VTD_SID_TO_DEVFN(source_id);
bf33cc75 1311 for (devfn_it = 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) {
7df953bd 1312 vtd_as = vtd_bus->dev_as[devfn_it];
d92fa2dc 1313 if (vtd_as && ((devfn_it & mask) == (devfn & mask))) {
bc535e59
PX		 1314 trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it),
1315 VTD_PCI_FUNC(devfn_it));
d92fa2dc 1316 vtd_as->context_cache_entry.context_cache_gen = 0;
dbaabb25
PX		 1317 /*
1318 * Do switch address space when needed, in case if the
1319 * device passthrough bit is switched.
1320 */
1321 vtd_switch_address_space(vtd_as);
dd4d607e
PX		 1322 /*
1323 * So a device is moving out of (or moving into) a
1324 * domain, a replay() suites here to notify all the
1325 * IOMMU_NOTIFIER_MAP registers about this change.
1326 * This won't bring bad even if we have no such
1327 * notifier registered - the IOMMU notification
1328 * framework will skip MAP notifications if that
1329 * happened.
1330 */
1331 memory_region_iommu_replay_all(&vtd_as->iommu);
d92fa2dc
LT		 1332 }
1333 }
1334 }
1335}
1336
1da12ec4
LT		 1337/* Context-cache invalidation
1338 * Returns the Context Actual Invalidation Granularity.
1339 * @val: the content of the CCMD_REG
1340 */
1341static uint64_t vtd_context_cache_invalidate(IntelIOMMUState *s, uint64_t val)
1342{
1343 uint64_t caig;
1344 uint64_t type = val & VTD_CCMD_CIRG_MASK;
1345
1346 switch (type) {
d92fa2dc 1347 case VTD_CCMD_DOMAIN_INVL:
d92fa2dc 1348 /* Fall through */
1da12ec4 1349 case VTD_CCMD_GLOBAL_INVL:
1da12ec4 1350 caig = VTD_CCMD_GLOBAL_INVL_A;
d92fa2dc 1351 vtd_context_global_invalidate(s);
1da12ec4
LT		 1352 break;
1353
1354 case VTD_CCMD_DEVICE_INVL:
1da12ec4 1355 caig = VTD_CCMD_DEVICE_INVL_A;
d92fa2dc 1356 vtd_context_device_invalidate(s, VTD_CCMD_SID(val), VTD_CCMD_FM(val));
1da12ec4
LT		 1357 break;
1358
1359 default:
7feb51b7 1360 trace_vtd_err("Context cache invalidate type error.");
1da12ec4
LT		 1361 caig = 0;
1362 }
1363 return caig;
1364}
1365
b5a280c0
LT		 1366static void vtd_iotlb_global_invalidate(IntelIOMMUState *s)
1367{
7feb51b7 1368 trace_vtd_inv_desc_iotlb_global();
b5a280c0 1369 vtd_reset_iotlb(s);
dd4d607e 1370 vtd_iommu_replay_all(s);
b5a280c0
LT		 1371}
1372
1373static void vtd_iotlb_domain_invalidate(IntelIOMMUState *s, uint16_t domain_id)
1374{
dd4d607e
PX		 1375 IntelIOMMUNotifierNode *node;
1376 VTDContextEntry ce;
1377 VTDAddressSpace *vtd_as;
1378
7feb51b7
PX		 1379 trace_vtd_inv_desc_iotlb_domain(domain_id);
1380
b5a280c0
LT		 1381 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_domain,
1382 &domain_id);
dd4d607e
PX		 1383
1384 QLIST_FOREACH(node, &s->notifiers_list, next) {
1385 vtd_as = node->vtd_as;
1386 if (!vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1387 vtd_as->devfn, &ce) &&
1388 domain_id == VTD_CONTEXT_ENTRY_DID(ce.hi)) {
1389 memory_region_iommu_replay_all(&vtd_as->iommu);
1390 }
1391 }
1392}
1393
1394static int vtd_page_invalidate_notify_hook(IOMMUTLBEntry *entry,
1395 void *private)
1396{
3df9d748 1397 memory_region_notify_iommu((IOMMUMemoryRegion *)private, *entry);
dd4d607e
PX		 1398 return 0;
1399}
1400
1401static void vtd_iotlb_page_invalidate_notify(IntelIOMMUState *s,
1402 uint16_t domain_id, hwaddr addr,
1403 uint8_t am)
1404{
1405 IntelIOMMUNotifierNode *node;
1406 VTDContextEntry ce;
1407 int ret;
1408
1409 QLIST_FOREACH(node, &(s->notifiers_list), next) {
1410 VTDAddressSpace *vtd_as = node->vtd_as;
1411 ret = vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus),
1412 vtd_as->devfn, &ce);
1413 if (!ret && domain_id == VTD_CONTEXT_ENTRY_DID(ce.hi)) {
1414 vtd_page_walk(&ce, addr, addr + (1 << am) * VTD_PAGE_SIZE,
1415 vtd_page_invalidate_notify_hook,
37f51384 1416 (void *)&vtd_as->iommu, true, s->aw_bits);
dd4d607e
PX		 1417 }
1418 }
b5a280c0
LT		 1419}
1420
1421static void vtd_iotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain_id,
1422 hwaddr addr, uint8_t am)
1423{
1424 VTDIOTLBPageInvInfo info;
1425
7feb51b7
PX		 1426 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am);
1427
b5a280c0
LT		 1428 assert(am <= VTD_MAMV);
1429 info.domain_id = domain_id;
d66b969b 1430 info.addr = addr;
b5a280c0
LT		 1431 info.mask = ~((1 << am) - 1);
1432 g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page, &info);
dd4d607e 1433 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am);
b5a280c0
LT		 1434}
1435
1da12ec4
LT		 1436/* Flush IOTLB
1437 * Returns the IOTLB Actual Invalidation Granularity.
1438 * @val: the content of the IOTLB_REG
1439 */
1440static uint64_t vtd_iotlb_flush(IntelIOMMUState *s, uint64_t val)
1441{
1442 uint64_t iaig;
1443 uint64_t type = val & VTD_TLB_FLUSH_GRANU_MASK;
b5a280c0
LT		 1444 uint16_t domain_id;
1445 hwaddr addr;
1446 uint8_t am;
1da12ec4
LT		 1447
1448 switch (type) {
1449 case VTD_TLB_GLOBAL_FLUSH:
1da12ec4 1450 iaig = VTD_TLB_GLOBAL_FLUSH_A;
b5a280c0 1451 vtd_iotlb_global_invalidate(s);
1da12ec4
LT		 1452 break;
1453
1454 case VTD_TLB_DSI_FLUSH:
b5a280c0 1455 domain_id = VTD_TLB_DID(val);
1da12ec4 1456 iaig = VTD_TLB_DSI_FLUSH_A;
b5a280c0 1457 vtd_iotlb_domain_invalidate(s, domain_id);
1da12ec4
LT		 1458 break;
1459
1460 case VTD_TLB_PSI_FLUSH:
b5a280c0
LT		 1461 domain_id = VTD_TLB_DID(val);
1462 addr = vtd_get_quad_raw(s, DMAR_IVA_REG);
1463 am = VTD_IVA_AM(addr);
1464 addr = VTD_IVA_ADDR(addr);
b5a280c0 1465 if (am > VTD_MAMV) {
7feb51b7 1466 trace_vtd_err("IOTLB PSI flush: address mask overflow.");
b5a280c0
LT		 1467 iaig = 0;
1468 break;
1469 }
1da12ec4 1470 iaig = VTD_TLB_PSI_FLUSH_A;
b5a280c0 1471 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1da12ec4
LT		 1472 break;
1473
1474 default:
7feb51b7 1475 trace_vtd_err("IOTLB flush: invalid granularity.");
1da12ec4
LT		 1476 iaig = 0;
1477 }
1478 return iaig;
1479}
1480
8991c460 1481static void vtd_fetch_inv_desc(IntelIOMMUState *s);
ed7b8fbc
LT		 1482
1483static inline bool vtd_queued_inv_disable_check(IntelIOMMUState *s)
1484{
1485 return s->qi_enabled && (s->iq_tail == s->iq_head) &&
1486 (s->iq_last_desc_type == VTD_INV_DESC_WAIT);
1487}
1488
1489static void vtd_handle_gcmd_qie(IntelIOMMUState *s, bool en)
1490{
1491 uint64_t iqa_val = vtd_get_quad_raw(s, DMAR_IQA_REG);
1492
7feb51b7
PX		 1493 trace_vtd_inv_qi_enable(en);
1494
ed7b8fbc 1495 if (en) {
37f51384 1496 s->iq = iqa_val & VTD_IQA_IQA_MASK(s->aw_bits);
8991c460
LP		 1497 /* 2^(x+8) entries */
1498 s->iq_size = 1UL << ((iqa_val & VTD_IQA_QS) + 8);
1499 s->qi_enabled = true;
1500 trace_vtd_inv_qi_setup(s->iq, s->iq_size);
1501 /* Ok - report back to driver */
1502 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_QIES);
1503
1504 if (s->iq_tail != 0) {
1505 /*
1506 * This is a spec violation but Windows guests are known to set up
1507 * Queued Invalidation this way so we allow the write and process
1508 * Invalidation Descriptors right away.
1509 */
1510 trace_vtd_warn_invalid_qi_tail(s->iq_tail);
1511 if (!(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
1512 vtd_fetch_inv_desc(s);
1513 }
ed7b8fbc
LT		 1514 }
1515 } else {
1516 if (vtd_queued_inv_disable_check(s)) {
1517 /* disable Queued Invalidation */
1518 vtd_set_quad_raw(s, DMAR_IQH_REG, 0);
1519 s->iq_head = 0;
1520 s->qi_enabled = false;
1521 /* Ok - report back to driver */
1522 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_QIES, 0);
1523 } else {
7feb51b7 1524 trace_vtd_err_qi_disable(s->iq_head, s->iq_tail, s->iq_last_desc_type);
ed7b8fbc
LT		 1525 }
1526 }
1527}
1528
1da12ec4
LT		 1529/* Set Root Table Pointer */
1530static void vtd_handle_gcmd_srtp(IntelIOMMUState *s)
1531{
1da12ec4
LT		 1532 vtd_root_table_setup(s);
1533 /* Ok - report back to driver */
1534 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS);
1535}
1536
a5861439
PX		 1537/* Set Interrupt Remap Table Pointer */
1538static void vtd_handle_gcmd_sirtp(IntelIOMMUState *s)
1539{
a5861439
PX		 1540 vtd_interrupt_remap_table_setup(s);
1541 /* Ok - report back to driver */
1542 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRTPS);
1543}
1544
1da12ec4
LT		 1545/* Handle Translation Enable/Disable */
1546static void vtd_handle_gcmd_te(IntelIOMMUState *s, bool en)
1547{
558e0024
PX		 1548 if (s->dmar_enabled == en) {
1549 return;
1550 }
1551
7feb51b7 1552 trace_vtd_dmar_enable(en);
1da12ec4
LT		 1553
1554 if (en) {
1555 s->dmar_enabled = true;
1556 /* Ok - report back to driver */
1557 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_TES);
1558 } else {
1559 s->dmar_enabled = false;
1560
1561 /* Clear the index of Fault Recording Register */
1562 s->next_frcd_reg = 0;
1563 /* Ok - report back to driver */
1564 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_TES, 0);
1565 }
558e0024
PX		 1566
1567 vtd_switch_address_space_all(s);
1da12ec4
LT		 1568}
1569
80de52ba
PX		 1570/* Handle Interrupt Remap Enable/Disable */
1571static void vtd_handle_gcmd_ire(IntelIOMMUState *s, bool en)
1572{
7feb51b7 1573 trace_vtd_ir_enable(en);
80de52ba
PX		 1574
1575 if (en) {
1576 s->intr_enabled = true;
1577 /* Ok - report back to driver */
1578 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_IRES);
1579 } else {
1580 s->intr_enabled = false;
1581 /* Ok - report back to driver */
1582 vtd_set_clear_mask_long(s, DMAR_GSTS_REG, VTD_GSTS_IRES, 0);
1583 }
1584}
1585
1da12ec4
LT		 1586/* Handle write to Global Command Register */
1587static void vtd_handle_gcmd_write(IntelIOMMUState *s)
1588{
1589 uint32_t status = vtd_get_long_raw(s, DMAR_GSTS_REG);
1590 uint32_t val = vtd_get_long_raw(s, DMAR_GCMD_REG);
1591 uint32_t changed = status ^ val;
1592
7feb51b7 1593 trace_vtd_reg_write_gcmd(status, val);
1da12ec4
LT		 1594 if (changed & VTD_GCMD_TE) {
1595 /* Translation enable/disable */
1596 vtd_handle_gcmd_te(s, val & VTD_GCMD_TE);
1597 }
1598 if (val & VTD_GCMD_SRTP) {
1599 /* Set/update the root-table pointer */
1600 vtd_handle_gcmd_srtp(s);
1601 }
ed7b8fbc
LT		 1602 if (changed & VTD_GCMD_QIE) {
1603 /* Queued Invalidation Enable */
1604 vtd_handle_gcmd_qie(s, val & VTD_GCMD_QIE);
1605 }
a5861439
PX		 1606 if (val & VTD_GCMD_SIRTP) {
1607 /* Set/update the interrupt remapping root-table pointer */
1608 vtd_handle_gcmd_sirtp(s);
1609 }
80de52ba
PX		 1610 if (changed & VTD_GCMD_IRE) {
1611 /* Interrupt remap enable/disable */
1612 vtd_handle_gcmd_ire(s, val & VTD_GCMD_IRE);
1613 }
1da12ec4
LT		 1614}
1615
1616/* Handle write to Context Command Register */
1617static void vtd_handle_ccmd_write(IntelIOMMUState *s)
1618{
1619 uint64_t ret;
1620 uint64_t val = vtd_get_quad_raw(s, DMAR_CCMD_REG);
1621
1622 /* Context-cache invalidation request */
1623 if (val & VTD_CCMD_ICC) {
ed7b8fbc 1624 if (s->qi_enabled) {
7feb51b7
PX		 1625 trace_vtd_err("Queued Invalidation enabled, "
1626 "should not use register-based invalidation");
ed7b8fbc
LT		 1627 return;
1628 }
1da12ec4
LT		 1629 ret = vtd_context_cache_invalidate(s, val);
1630 /* Invalidation completed. Change something to show */
1631 vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_ICC, 0ULL);
1632 ret = vtd_set_clear_mask_quad(s, DMAR_CCMD_REG, VTD_CCMD_CAIG_MASK,
1633 ret);
1da12ec4
LT		 1634 }
1635}
1636
1637/* Handle write to IOTLB Invalidation Register */
1638static void vtd_handle_iotlb_write(IntelIOMMUState *s)
1639{
1640 uint64_t ret;
1641 uint64_t val = vtd_get_quad_raw(s, DMAR_IOTLB_REG);
1642
1643 /* IOTLB invalidation request */
1644 if (val & VTD_TLB_IVT) {
ed7b8fbc 1645 if (s->qi_enabled) {
7feb51b7
PX		 1646 trace_vtd_err("Queued Invalidation enabled, "
1647 "should not use register-based invalidation.");
ed7b8fbc
LT		 1648 return;
1649 }
1da12ec4
LT		 1650 ret = vtd_iotlb_flush(s, val);
1651 /* Invalidation completed. Change something to show */
1652 vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG, VTD_TLB_IVT, 0ULL);
1653 ret = vtd_set_clear_mask_quad(s, DMAR_IOTLB_REG,
1654 VTD_TLB_FLUSH_GRANU_MASK_A, ret);
1da12ec4
LT		 1655 }
1656}
1657
ed7b8fbc
LT		 1658/* Fetch an Invalidation Descriptor from the Invalidation Queue */
1659static bool vtd_get_inv_desc(dma_addr_t base_addr, uint32_t offset,
1660 VTDInvDesc *inv_desc)
1661{
1662 dma_addr_t addr = base_addr + offset * sizeof(*inv_desc);
1663 if (dma_memory_read(&address_space_memory, addr, inv_desc,
1664 sizeof(*inv_desc))) {
7feb51b7 1665 trace_vtd_err("Read INV DESC failed.");
ed7b8fbc
LT		 1666 inv_desc->lo = 0;
1667 inv_desc->hi = 0;
ed7b8fbc
LT		 1668 return false;
1669 }
1670 inv_desc->lo = le64_to_cpu(inv_desc->lo);
1671 inv_desc->hi = le64_to_cpu(inv_desc->hi);
1672 return true;
1673}
1674
1675static bool vtd_process_wait_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1676{
1677 if ((inv_desc->hi & VTD_INV_DESC_WAIT_RSVD_HI) ||
1678 (inv_desc->lo & VTD_INV_DESC_WAIT_RSVD_LO)) {
bc535e59 1679 trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1680 return false;
1681 }
1682 if (inv_desc->lo & VTD_INV_DESC_WAIT_SW) {
1683 /* Status Write */
1684 uint32_t status_data = (uint32_t)(inv_desc->lo >>
1685 VTD_INV_DESC_WAIT_DATA_SHIFT);
1686
1687 assert(!(inv_desc->lo & VTD_INV_DESC_WAIT_IF));
1688
1689 /* FIXME: need to be masked with HAW? */
1690 dma_addr_t status_addr = inv_desc->hi;
bc535e59 1691 trace_vtd_inv_desc_wait_sw(status_addr, status_data);
ed7b8fbc
LT		 1692 status_data = cpu_to_le32(status_data);
1693 if (dma_memory_write(&address_space_memory, status_addr, &status_data,
1694 sizeof(status_data))) {
bc535e59 1695 trace_vtd_inv_desc_wait_write_fail(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1696 return false;
1697 }
1698 } else if (inv_desc->lo & VTD_INV_DESC_WAIT_IF) {
1699 /* Interrupt flag */
ed7b8fbc
LT		 1700 vtd_generate_completion_event(s);
1701 } else {
bc535e59 1702 trace_vtd_inv_desc_wait_invalid(inv_desc->hi, inv_desc->lo);
ed7b8fbc
LT		 1703 return false;
1704 }
1705 return true;
1706}
1707
d92fa2dc
LT		 1708static bool vtd_process_context_cache_desc(IntelIOMMUState *s,
1709 VTDInvDesc *inv_desc)
1710{
bc535e59
PX		 1711 uint16_t sid, fmask;
1712
d92fa2dc 1713 if ((inv_desc->lo & VTD_INV_DESC_CC_RSVD) || inv_desc->hi) {
bc535e59 1714 trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
d92fa2dc
LT		 1715 return false;
1716 }
1717 switch (inv_desc->lo & VTD_INV_DESC_CC_G) {
1718 case VTD_INV_DESC_CC_DOMAIN:
bc535e59
PX		 1719 trace_vtd_inv_desc_cc_domain(
1720 (uint16_t)VTD_INV_DESC_CC_DID(inv_desc->lo));
d92fa2dc
LT		 1721 /* Fall through */
1722 case VTD_INV_DESC_CC_GLOBAL:
d92fa2dc
LT		 1723 vtd_context_global_invalidate(s);
1724 break;
1725
1726 case VTD_INV_DESC_CC_DEVICE:
bc535e59
PX		 1727 sid = VTD_INV_DESC_CC_SID(inv_desc->lo);
1728 fmask = VTD_INV_DESC_CC_FM(inv_desc->lo);
1729 vtd_context_device_invalidate(s, sid, fmask);
d92fa2dc
LT		 1730 break;
1731
1732 default:
bc535e59 1733 trace_vtd_inv_desc_cc_invalid(inv_desc->hi, inv_desc->lo);
d92fa2dc
LT		 1734 return false;
1735 }
1736 return true;
1737}
1738
b5a280c0
LT		 1739static bool vtd_process_iotlb_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc)
1740{
1741 uint16_t domain_id;
1742 uint8_t am;
1743 hwaddr addr;
1744
1745 if ((inv_desc->lo & VTD_INV_DESC_IOTLB_RSVD_LO) ||
1746 (inv_desc->hi & VTD_INV_DESC_IOTLB_RSVD_HI)) {
bc535e59 1747 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1748 return false;
1749 }
1750
1751 switch (inv_desc->lo & VTD_INV_DESC_IOTLB_G) {
1752 case VTD_INV_DESC_IOTLB_GLOBAL:
b5a280c0
LT		 1753 vtd_iotlb_global_invalidate(s);
1754 break;
1755
1756 case VTD_INV_DESC_IOTLB_DOMAIN:
1757 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
b5a280c0
LT		 1758 vtd_iotlb_domain_invalidate(s, domain_id);
1759 break;
1760
1761 case VTD_INV_DESC_IOTLB_PAGE:
1762 domain_id = VTD_INV_DESC_IOTLB_DID(inv_desc->lo);
1763 addr = VTD_INV_DESC_IOTLB_ADDR(inv_desc->hi);
1764 am = VTD_INV_DESC_IOTLB_AM(inv_desc->hi);
b5a280c0 1765 if (am > VTD_MAMV) {
bc535e59 1766 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1767 return false;
1768 }
1769 vtd_iotlb_page_invalidate(s, domain_id, addr, am);
1770 break;
1771
1772 default:
bc535e59 1773 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
b5a280c0
LT		 1774 return false;
1775 }
1776 return true;
1777}
1778
02a2cbc8
PX		 1779static bool vtd_process_inv_iec_desc(IntelIOMMUState *s,
1780 VTDInvDesc *inv_desc)
1781{
7feb51b7
PX		 1782 trace_vtd_inv_desc_iec(inv_desc->iec.granularity,
1783 inv_desc->iec.index,
1784 inv_desc->iec.index_mask);
02a2cbc8
PX		 1785
1786 vtd_iec_notify_all(s, !inv_desc->iec.granularity,
1787 inv_desc->iec.index,
1788 inv_desc->iec.index_mask);
554f5e16
JW		 1789 return true;
1790}
1791
1792static bool vtd_process_device_iotlb_desc(IntelIOMMUState *s,
1793 VTDInvDesc *inv_desc)
1794{
1795 VTDAddressSpace *vtd_dev_as;
1796 IOMMUTLBEntry entry;
1797 struct VTDBus *vtd_bus;
1798 hwaddr addr;
1799 uint64_t sz;
1800 uint16_t sid;
1801 uint8_t devfn;
1802 bool size;
1803 uint8_t bus_num;
1804
1805 addr = VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi);
1806 sid = VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo);
1807 devfn = sid & 0xff;
1808 bus_num = sid >> 8;
1809 size = VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi);
1810
1811 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) ||
1812 (inv_desc->hi & VTD_INV_DESC_DEVICE_IOTLB_RSVD_HI)) {
7feb51b7 1813 trace_vtd_inv_desc_iotlb_invalid(inv_desc->hi, inv_desc->lo);
554f5e16
JW		 1814 return false;
1815 }
1816
1817 vtd_bus = vtd_find_as_from_bus_num(s, bus_num);
1818 if (!vtd_bus) {
1819 goto done;
1820 }
1821
1822 vtd_dev_as = vtd_bus->dev_as[devfn];
1823 if (!vtd_dev_as) {
1824 goto done;
1825 }
1826
04eb6247
JW		 1827 /* According to ATS spec table 2.4:
1828 * S = 0, bits 15:12 = xxxx range size: 4K
1829 * S = 1, bits 15:12 = xxx0 range size: 8K
1830 * S = 1, bits 15:12 = xx01 range size: 16K
1831 * S = 1, bits 15:12 = x011 range size: 32K
1832 * S = 1, bits 15:12 = 0111 range size: 64K
1833 * ...
1834 */
554f5e16 1835 if (size) {
04eb6247 1836 sz = (VTD_PAGE_SIZE * 2) << cto64(addr >> VTD_PAGE_SHIFT);
554f5e16
JW		 1837 addr &= ~(sz - 1);
1838 } else {
1839 sz = VTD_PAGE_SIZE;
1840 }
02a2cbc8 1841
554f5e16
JW		 1842 entry.target_as = &vtd_dev_as->as;
1843 entry.addr_mask = sz - 1;
1844 entry.iova = addr;
1845 entry.perm = IOMMU_NONE;
1846 entry.translated_addr = 0;
10315b9b 1847 memory_region_notify_iommu(&vtd_dev_as->iommu, entry);
554f5e16
JW		 1848
1849done:
02a2cbc8
PX		 1850 return true;
1851}
1852
ed7b8fbc
LT		 1853static bool vtd_process_inv_desc(IntelIOMMUState *s)
1854{
1855 VTDInvDesc inv_desc;
1856 uint8_t desc_type;
1857
7feb51b7 1858 trace_vtd_inv_qi_head(s->iq_head);
ed7b8fbc
LT		 1859 if (!vtd_get_inv_desc(s->iq, s->iq_head, &inv_desc)) {
1860 s->iq_last_desc_type = VTD_INV_DESC_NONE;
1861 return false;
1862 }
1863 desc_type = inv_desc.lo & VTD_INV_DESC_TYPE;
1864 /* FIXME: should update at first or at last? */
1865 s->iq_last_desc_type = desc_type;
1866
1867 switch (desc_type) {
1868 case VTD_INV_DESC_CC:
bc535e59 1869 trace_vtd_inv_desc("context-cache", inv_desc.hi, inv_desc.lo);
d92fa2dc
LT		 1870 if (!vtd_process_context_cache_desc(s, &inv_desc)) {
1871 return false;
1872 }
ed7b8fbc
LT		 1873 break;
1874
1875 case VTD_INV_DESC_IOTLB:
bc535e59 1876 trace_vtd_inv_desc("iotlb", inv_desc.hi, inv_desc.lo);
b5a280c0
LT		 1877 if (!vtd_process_iotlb_desc(s, &inv_desc)) {
1878 return false;
1879 }
ed7b8fbc
LT		 1880 break;
1881
1882 case VTD_INV_DESC_WAIT:
bc535e59 1883 trace_vtd_inv_desc("wait", inv_desc.hi, inv_desc.lo);
ed7b8fbc
LT		 1884 if (!vtd_process_wait_desc(s, &inv_desc)) {
1885 return false;
1886 }
1887 break;
1888
b7910472 1889 case VTD_INV_DESC_IEC:
bc535e59 1890 trace_vtd_inv_desc("iec", inv_desc.hi, inv_desc.lo);
02a2cbc8
PX		 1891 if (!vtd_process_inv_iec_desc(s, &inv_desc)) {
1892 return false;
1893 }
b7910472
PX		 1894 break;
1895
554f5e16 1896 case VTD_INV_DESC_DEVICE:
7feb51b7 1897 trace_vtd_inv_desc("device", inv_desc.hi, inv_desc.lo);
554f5e16
JW		 1898 if (!vtd_process_device_iotlb_desc(s, &inv_desc)) {
1899 return false;
1900 }
1901 break;
1902
ed7b8fbc 1903 default:
bc535e59 1904 trace_vtd_inv_desc_invalid(inv_desc.hi, inv_desc.lo);
ed7b8fbc
LT		 1905 return false;
1906 }
1907 s->iq_head++;
1908 if (s->iq_head == s->iq_size) {
1909 s->iq_head = 0;
1910 }
1911 return true;
1912}
1913
1914/* Try to fetch and process more Invalidation Descriptors */
1915static void vtd_fetch_inv_desc(IntelIOMMUState *s)
1916{
7feb51b7
PX		 1917 trace_vtd_inv_qi_fetch();
1918
ed7b8fbc
LT		 1919 if (s->iq_tail >= s->iq_size) {
1920 /* Detects an invalid Tail pointer */
7feb51b7 1921 trace_vtd_err_qi_tail(s->iq_tail, s->iq_size);
ed7b8fbc
LT		 1922 vtd_handle_inv_queue_error(s);
1923 return;
1924 }
1925 while (s->iq_head != s->iq_tail) {
1926 if (!vtd_process_inv_desc(s)) {
1927 /* Invalidation Queue Errors */
1928 vtd_handle_inv_queue_error(s);
1929 break;
1930 }
1931 /* Must update the IQH_REG in time */
1932 vtd_set_quad_raw(s, DMAR_IQH_REG,
1933 (((uint64_t)(s->iq_head)) << VTD_IQH_QH_SHIFT) &
1934 VTD_IQH_QH_MASK);
1935 }
1936}
1937
1938/* Handle write to Invalidation Queue Tail Register */
1939static void vtd_handle_iqt_write(IntelIOMMUState *s)
1940{
1941 uint64_t val = vtd_get_quad_raw(s, DMAR_IQT_REG);
1942
1943 s->iq_tail = VTD_IQT_QT(val);
7feb51b7
PX		 1944 trace_vtd_inv_qi_tail(s->iq_tail);
1945
ed7b8fbc
LT		 1946 if (s->qi_enabled && !(vtd_get_long_raw(s, DMAR_FSTS_REG) & VTD_FSTS_IQE)) {
1947 /* Process Invalidation Queue here */
1948 vtd_fetch_inv_desc(s);
1949 }
1950}
1951
1da12ec4
LT		 1952static void vtd_handle_fsts_write(IntelIOMMUState *s)
1953{
1954 uint32_t fsts_reg = vtd_get_long_raw(s, DMAR_FSTS_REG);
1955 uint32_t fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
1956 uint32_t status_fields = VTD_FSTS_PFO | VTD_FSTS_PPF | VTD_FSTS_IQE;
1957
1958 if ((fectl_reg & VTD_FECTL_IP) && !(fsts_reg & status_fields)) {
1959 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
7feb51b7 1960 trace_vtd_fsts_clear_ip();
1da12ec4 1961 }
ed7b8fbc
LT		 1962 /* FIXME: when IQE is Clear, should we try to fetch some Invalidation
1963 * Descriptors if there are any when Queued Invalidation is enabled?
1964 */
1da12ec4
LT		 1965}
1966
1967static void vtd_handle_fectl_write(IntelIOMMUState *s)
1968{
1969 uint32_t fectl_reg;
1970 /* FIXME: when software clears the IM field, check the IP field. But do we
1971 * need to compare the old value and the new value to conclude that
1972 * software clears the IM field? Or just check if the IM field is zero?
1973 */
1974 fectl_reg = vtd_get_long_raw(s, DMAR_FECTL_REG);
7feb51b7
PX		 1975
1976 trace_vtd_reg_write_fectl(fectl_reg);
1977
1da12ec4
LT		 1978 if ((fectl_reg & VTD_FECTL_IP) && !(fectl_reg & VTD_FECTL_IM)) {
1979 vtd_generate_interrupt(s, DMAR_FEADDR_REG, DMAR_FEDATA_REG);
1980 vtd_set_clear_mask_long(s, DMAR_FECTL_REG, VTD_FECTL_IP, 0);
1da12ec4
LT		 1981 }
1982}
1983
ed7b8fbc
LT		 1984static void vtd_handle_ics_write(IntelIOMMUState *s)
1985{
1986 uint32_t ics_reg = vtd_get_long_raw(s, DMAR_ICS_REG);
1987 uint32_t iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
1988
1989 if ((iectl_reg & VTD_IECTL_IP) && !(ics_reg & VTD_ICS_IWC)) {
7feb51b7 1990 trace_vtd_reg_ics_clear_ip();
ed7b8fbc 1991 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
ed7b8fbc
LT		 1992 }
1993}
1994
1995static void vtd_handle_iectl_write(IntelIOMMUState *s)
1996{
1997 uint32_t iectl_reg;
1998 /* FIXME: when software clears the IM field, check the IP field. But do we
1999 * need to compare the old value and the new value to conclude that
2000 * software clears the IM field? Or just check if the IM field is zero?
2001 */
2002 iectl_reg = vtd_get_long_raw(s, DMAR_IECTL_REG);
7feb51b7
PX		 2003
2004 trace_vtd_reg_write_iectl(iectl_reg);
2005
ed7b8fbc
LT		 2006 if ((iectl_reg & VTD_IECTL_IP) && !(iectl_reg & VTD_IECTL_IM)) {
2007 vtd_generate_interrupt(s, DMAR_IEADDR_REG, DMAR_IEDATA_REG);
2008 vtd_set_clear_mask_long(s, DMAR_IECTL_REG, VTD_IECTL_IP, 0);
ed7b8fbc
LT		 2009 }
2010}
2011
1da12ec4
LT		 2012static uint64_t vtd_mem_read(void *opaque, hwaddr addr, unsigned size)
2013{
2014 IntelIOMMUState *s = opaque;
2015 uint64_t val;
2016
7feb51b7
PX		 2017 trace_vtd_reg_read(addr, size);
2018
1da12ec4 2019 if (addr + size > DMAR_REG_SIZE) {
7feb51b7 2020 trace_vtd_err("Read MMIO over range.");
1da12ec4
LT		 2021 return (uint64_t)-1;
2022 }
2023
2024 switch (addr) {
2025 /* Root Table Address Register, 64-bit */
2026 case DMAR_RTADDR_REG:
2027 if (size == 4) {
2028 val = s->root & ((1ULL << 32) - 1);
2029 } else {
2030 val = s->root;
2031 }
2032 break;
2033
2034 case DMAR_RTADDR_REG_HI:
2035 assert(size == 4);
2036 val = s->root >> 32;
2037 break;
2038
ed7b8fbc
LT		 2039 /* Invalidation Queue Address Register, 64-bit */
2040 case DMAR_IQA_REG:
2041 val = s->iq | (vtd_get_quad(s, DMAR_IQA_REG) & VTD_IQA_QS);
2042 if (size == 4) {
2043 val = val & ((1ULL << 32) - 1);
2044 }
2045 break;
2046
2047 case DMAR_IQA_REG_HI:
2048 assert(size == 4);
2049 val = s->iq >> 32;
2050 break;
2051
1da12ec4
LT		 2052 default:
2053 if (size == 4) {
2054 val = vtd_get_long(s, addr);
2055 } else {
2056 val = vtd_get_quad(s, addr);
2057 }
2058 }
7feb51b7 2059
1da12ec4
LT		 2060 return val;
2061}
2062
2063static void vtd_mem_write(void *opaque, hwaddr addr,
2064 uint64_t val, unsigned size)
2065{
2066 IntelIOMMUState *s = opaque;
2067
7feb51b7
PX		 2068 trace_vtd_reg_write(addr, size, val);
2069
1da12ec4 2070 if (addr + size > DMAR_REG_SIZE) {
7feb51b7 2071 trace_vtd_err("Write MMIO over range.");
1da12ec4
LT		 2072 return;
2073 }
2074
2075 switch (addr) {
2076 /* Global Command Register, 32-bit */
2077 case DMAR_GCMD_REG:
1da12ec4
LT		 2078 vtd_set_long(s, addr, val);
2079 vtd_handle_gcmd_write(s);
2080 break;
2081
2082 /* Context Command Register, 64-bit */
2083 case DMAR_CCMD_REG:
1da12ec4
LT		 2084 if (size == 4) {
2085 vtd_set_long(s, addr, val);
2086 } else {
2087 vtd_set_quad(s, addr, val);
2088 vtd_handle_ccmd_write(s);
2089 }
2090 break;
2091
2092 case DMAR_CCMD_REG_HI:
1da12ec4
LT		 2093 assert(size == 4);
2094 vtd_set_long(s, addr, val);
2095 vtd_handle_ccmd_write(s);
2096 break;
2097
2098 /* IOTLB Invalidation Register, 64-bit */
2099 case DMAR_IOTLB_REG:
1da12ec4
LT		 2100 if (size == 4) {
2101 vtd_set_long(s, addr, val);
2102 } else {
2103 vtd_set_quad(s, addr, val);
2104 vtd_handle_iotlb_write(s);
2105 }
2106 break;
2107
2108 case DMAR_IOTLB_REG_HI:
1da12ec4
LT		 2109 assert(size == 4);
2110 vtd_set_long(s, addr, val);
2111 vtd_handle_iotlb_write(s);
2112 break;
2113
b5a280c0
LT		 2114 /* Invalidate Address Register, 64-bit */
2115 case DMAR_IVA_REG:
b5a280c0
LT		 2116 if (size == 4) {
2117 vtd_set_long(s, addr, val);
2118 } else {
2119 vtd_set_quad(s, addr, val);
2120 }
2121 break;
2122
2123 case DMAR_IVA_REG_HI:
b5a280c0
LT		 2124 assert(size == 4);
2125 vtd_set_long(s, addr, val);
2126 break;
2127
1da12ec4
LT		 2128 /* Fault Status Register, 32-bit */
2129 case DMAR_FSTS_REG:
1da12ec4
LT		 2130 assert(size == 4);
2131 vtd_set_long(s, addr, val);
2132 vtd_handle_fsts_write(s);
2133 break;
2134
2135 /* Fault Event Control Register, 32-bit */
2136 case DMAR_FECTL_REG:
1da12ec4
LT		 2137 assert(size == 4);
2138 vtd_set_long(s, addr, val);
2139 vtd_handle_fectl_write(s);
2140 break;
2141
2142 /* Fault Event Data Register, 32-bit */
2143 case DMAR_FEDATA_REG:
1da12ec4
LT		 2144 assert(size == 4);
2145 vtd_set_long(s, addr, val);
2146 break;
2147
2148 /* Fault Event Address Register, 32-bit */
2149 case DMAR_FEADDR_REG:
b7a7bb35
JK		 2150 if (size == 4) {
2151 vtd_set_long(s, addr, val);
2152 } else {
2153 /*
2154 * While the register is 32-bit only, some guests (Xen...) write to
2155 * it with 64-bit.
2156 */
2157 vtd_set_quad(s, addr, val);
2158 }
1da12ec4
LT		 2159 break;
2160
2161 /* Fault Event Upper Address Register, 32-bit */
2162 case DMAR_FEUADDR_REG:
1da12ec4
LT		 2163 assert(size == 4);
2164 vtd_set_long(s, addr, val);
2165 break;
2166
2167 /* Protected Memory Enable Register, 32-bit */
2168 case DMAR_PMEN_REG:
1da12ec4
LT		 2169 assert(size == 4);
2170 vtd_set_long(s, addr, val);
2171 break;
2172
2173 /* Root Table Address Register, 64-bit */
2174 case DMAR_RTADDR_REG:
1da12ec4
LT		 2175 if (size == 4) {
2176 vtd_set_long(s, addr, val);
2177 } else {
2178 vtd_set_quad(s, addr, val);
2179 }
2180 break;
2181
2182 case DMAR_RTADDR_REG_HI:
1da12ec4
LT		 2183 assert(size == 4);
2184 vtd_set_long(s, addr, val);
2185 break;
2186
ed7b8fbc
LT		 2187 /* Invalidation Queue Tail Register, 64-bit */
2188 case DMAR_IQT_REG:
ed7b8fbc
LT		 2189 if (size == 4) {
2190 vtd_set_long(s, addr, val);
2191 } else {
2192 vtd_set_quad(s, addr, val);
2193 }
2194 vtd_handle_iqt_write(s);
2195 break;
2196
2197 case DMAR_IQT_REG_HI:
ed7b8fbc
LT		 2198 assert(size == 4);
2199 vtd_set_long(s, addr, val);
2200 /* 19:63 of IQT_REG is RsvdZ, do nothing here */
2201 break;
2202
2203 /* Invalidation Queue Address Register, 64-bit */
2204 case DMAR_IQA_REG:
ed7b8fbc
LT		 2205 if (size == 4) {
2206 vtd_set_long(s, addr, val);
2207 } else {
2208 vtd_set_quad(s, addr, val);
2209 }
2210 break;
2211
2212 case DMAR_IQA_REG_HI:
ed7b8fbc
LT		 2213 assert(size == 4);
2214 vtd_set_long(s, addr, val);
2215 break;
2216
2217 /* Invalidation Completion Status Register, 32-bit */
2218 case DMAR_ICS_REG:
ed7b8fbc
LT		 2219 assert(size == 4);
2220 vtd_set_long(s, addr, val);
2221 vtd_handle_ics_write(s);
2222 break;
2223
2224 /* Invalidation Event Control Register, 32-bit */
2225 case DMAR_IECTL_REG:
ed7b8fbc
LT		 2226 assert(size == 4);
2227 vtd_set_long(s, addr, val);
2228 vtd_handle_iectl_write(s);
2229 break;
2230
2231 /* Invalidation Event Data Register, 32-bit */
2232 case DMAR_IEDATA_REG:
ed7b8fbc
LT		 2233 assert(size == 4);
2234 vtd_set_long(s, addr, val);
2235 break;
2236
2237 /* Invalidation Event Address Register, 32-bit */
2238 case DMAR_IEADDR_REG:
ed7b8fbc
LT		 2239 assert(size == 4);
2240 vtd_set_long(s, addr, val);
2241 break;
2242
2243 /* Invalidation Event Upper Address Register, 32-bit */
2244 case DMAR_IEUADDR_REG:
ed7b8fbc
LT		 2245 assert(size == 4);
2246 vtd_set_long(s, addr, val);
2247 break;
2248
1da12ec4
LT		 2249 /* Fault Recording Registers, 128-bit */
2250 case DMAR_FRCD_REG_0_0:
1da12ec4
LT		 2251 if (size == 4) {
2252 vtd_set_long(s, addr, val);
2253 } else {
2254 vtd_set_quad(s, addr, val);
2255 }
2256 break;
2257
2258 case DMAR_FRCD_REG_0_1:
1da12ec4
LT		 2259 assert(size == 4);
2260 vtd_set_long(s, addr, val);
2261 break;
2262
2263 case DMAR_FRCD_REG_0_2:
1da12ec4
LT		 2264 if (size == 4) {
2265 vtd_set_long(s, addr, val);
2266 } else {
2267 vtd_set_quad(s, addr, val);
2268 /* May clear bit 127 (Fault), update PPF */
2269 vtd_update_fsts_ppf(s);
2270 }
2271 break;
2272
2273 case DMAR_FRCD_REG_0_3:
1da12ec4
LT		 2274 assert(size == 4);
2275 vtd_set_long(s, addr, val);
2276 /* May clear bit 127 (Fault), update PPF */
2277 vtd_update_fsts_ppf(s);
2278 break;
2279
a5861439 2280 case DMAR_IRTA_REG:
a5861439
PX		 2281 if (size == 4) {
2282 vtd_set_long(s, addr, val);
2283 } else {
2284 vtd_set_quad(s, addr, val);
2285 }
2286 break;
2287
2288 case DMAR_IRTA_REG_HI:
a5861439
PX		 2289 assert(size == 4);
2290 vtd_set_long(s, addr, val);
2291 break;
2292
1da12ec4 2293 default:
1da12ec4
LT		 2294 if (size == 4) {
2295 vtd_set_long(s, addr, val);
2296 } else {
2297 vtd_set_quad(s, addr, val);
2298 }
2299 }
2300}
2301
3df9d748 2302static IOMMUTLBEntry vtd_iommu_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
bf55b7af 2303 IOMMUAccessFlags flag)
1da12ec4
LT		 2304{
2305 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
2306 IntelIOMMUState *s = vtd_as->iommu_state;
b9313021
PX		 2307 IOMMUTLBEntry iotlb = {
2308 /* We'll fill in the rest later. */
1da12ec4 2309 .target_as = &address_space_memory,
1da12ec4 2310 };
b9313021 2311 bool success;
1da12ec4 2312
b9313021
PX		 2313 if (likely(s->dmar_enabled)) {
2314 success = vtd_do_iommu_translate(vtd_as, vtd_as->bus, vtd_as->devfn,
2315 addr, flag & IOMMU_WO, &iotlb);
2316 } else {
1da12ec4 2317 /* DMAR disabled, passthrough, use 4k-page*/
b9313021
PX		 2318 iotlb.iova = addr & VTD_PAGE_MASK_4K;
2319 iotlb.translated_addr = addr & VTD_PAGE_MASK_4K;
2320 iotlb.addr_mask = ~VTD_PAGE_MASK_4K;
2321 iotlb.perm = IOMMU_RW;
2322 success = true;
1da12ec4
LT		 2323 }
2324
b9313021
PX		 2325 if (likely(success)) {
2326 trace_vtd_dmar_translate(pci_bus_num(vtd_as->bus),
2327 VTD_PCI_SLOT(vtd_as->devfn),
2328 VTD_PCI_FUNC(vtd_as->devfn),
2329 iotlb.iova, iotlb.translated_addr,
2330 iotlb.addr_mask);
2331 } else {
2332 trace_vtd_err_dmar_translate(pci_bus_num(vtd_as->bus),
2333 VTD_PCI_SLOT(vtd_as->devfn),
2334 VTD_PCI_FUNC(vtd_as->devfn),
2335 iotlb.iova);
2336 }
7feb51b7 2337
b9313021 2338 return iotlb;
1da12ec4
LT		 2339}
2340
3df9d748 2341static void vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu,
5bf3d319
PX		 2342 IOMMUNotifierFlag old,
2343 IOMMUNotifierFlag new)
3cb3b154
AW		 2344{
2345 VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu);
dd4d607e
PX		 2346 IntelIOMMUState *s = vtd_as->iommu_state;
2347 IntelIOMMUNotifierNode *node = NULL;
2348 IntelIOMMUNotifierNode *next_node = NULL;
3cb3b154 2349
dd4d607e 2350 if (!s->caching_mode && new & IOMMU_NOTIFIER_MAP) {
4c427a4c 2351 error_report("We need to set caching-mode=1 for intel-iommu to enable "
dd4d607e 2352 "device assignment with IOMMU protection.");
a3276f78
PX		 2353 exit(1);
2354 }
dd4d607e
PX		 2355
2356 if (old == IOMMU_NOTIFIER_NONE) {
2357 node = g_malloc0(sizeof(*node));
2358 node->vtd_as = vtd_as;
2359 QLIST_INSERT_HEAD(&s->notifiers_list, node, next);
2360 return;
2361 }
2362
2363 /* update notifier node with new flags */
2364 QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) {
2365 if (node->vtd_as == vtd_as) {
2366 if (new == IOMMU_NOTIFIER_NONE) {
2367 QLIST_REMOVE(node, next);
2368 g_free(node);
2369 }
2370 return;
2371 }
2372 }
3cb3b154
AW		 2373}
2374
552a1e01
PX		 2375static int vtd_post_load(void *opaque, int version_id)
2376{
2377 IntelIOMMUState *iommu = opaque;
2378
2379 /*
2380 * Memory regions are dynamically turned on/off depending on
2381 * context entry configurations from the guest. After migration,
2382 * we need to make sure the memory regions are still correct.
2383 */
2384 vtd_switch_address_space_all(iommu);
2385
2386 return 0;
2387}
2388
1da12ec4
LT		 2389static const VMStateDescription vtd_vmstate = {
2390 .name = "iommu-intel",
8cdcf3c1
PX		 2391 .version_id = 1,
2392 .minimum_version_id = 1,
2393 .priority = MIG_PRI_IOMMU,
552a1e01 2394 .post_load = vtd_post_load,
8cdcf3c1
PX		 2395 .fields = (VMStateField[]) {
2396 VMSTATE_UINT64(root, IntelIOMMUState),
2397 VMSTATE_UINT64(intr_root, IntelIOMMUState),
2398 VMSTATE_UINT64(iq, IntelIOMMUState),
2399 VMSTATE_UINT32(intr_size, IntelIOMMUState),
2400 VMSTATE_UINT16(iq_head, IntelIOMMUState),
2401 VMSTATE_UINT16(iq_tail, IntelIOMMUState),
2402 VMSTATE_UINT16(iq_size, IntelIOMMUState),
2403 VMSTATE_UINT16(next_frcd_reg, IntelIOMMUState),
2404 VMSTATE_UINT8_ARRAY(csr, IntelIOMMUState, DMAR_REG_SIZE),
2405 VMSTATE_UINT8(iq_last_desc_type, IntelIOMMUState),
2406 VMSTATE_BOOL(root_extended, IntelIOMMUState),
2407 VMSTATE_BOOL(dmar_enabled, IntelIOMMUState),
2408 VMSTATE_BOOL(qi_enabled, IntelIOMMUState),
2409 VMSTATE_BOOL(intr_enabled, IntelIOMMUState),
2410 VMSTATE_BOOL(intr_eime, IntelIOMMUState),
2411 VMSTATE_END_OF_LIST()
2412 }
1da12ec4
LT		 2413};
2414
2415static const MemoryRegionOps vtd_mem_ops = {
2416 .read = vtd_mem_read,
2417 .write = vtd_mem_write,
2418 .endianness = DEVICE_LITTLE_ENDIAN,
2419 .impl = {
2420 .min_access_size = 4,
2421 .max_access_size = 8,
2422 },
2423 .valid = {
2424 .min_access_size = 4,
2425 .max_access_size = 8,
2426 },
2427};
2428
2429static Property vtd_properties[] = {
2430 DEFINE_PROP_UINT32("version", IntelIOMMUState, version, 0),
e6b6af05
RK		 2431 DEFINE_PROP_ON_OFF_AUTO("eim", IntelIOMMUState, intr_eim,
2432 ON_OFF_AUTO_AUTO),
fb506e70 2433 DEFINE_PROP_BOOL("x-buggy-eim", IntelIOMMUState, buggy_eim, false),
37f51384
PS		 2434 DEFINE_PROP_UINT8("x-aw-bits", IntelIOMMUState, aw_bits,
2435 VTD_HOST_ADDRESS_WIDTH),
3b40f0e5 2436 DEFINE_PROP_BOOL("caching-mode", IntelIOMMUState, caching_mode, FALSE),
1da12ec4
LT		 2437 DEFINE_PROP_END_OF_LIST(),
2438};
2439
651e4cef
PX		 2440/* Read IRTE entry with specific index */
2441static int vtd_irte_get(IntelIOMMUState *iommu, uint16_t index,
bc38ee10 2442 VTD_IR_TableEntry *entry, uint16_t sid)
651e4cef 2443{
ede9c94a
PX		 2444 static const uint16_t vtd_svt_mask[VTD_SQ_MAX] = \
2445 {0xffff, 0xfffb, 0xfff9, 0xfff8};
651e4cef 2446 dma_addr_t addr = 0x00;
ede9c94a
PX		 2447 uint16_t mask, source_id;
2448 uint8_t bus, bus_max, bus_min;
651e4cef
PX		 2449
2450 addr = iommu->intr_root + index * sizeof(*entry);
2451 if (dma_memory_read(&address_space_memory, addr, entry,
2452 sizeof(*entry))) {
7feb51b7 2453 trace_vtd_err("Memory read failed for IRTE.");
651e4cef
PX		 2454 return -VTD_FR_IR_ROOT_INVAL;
2455 }
2456
7feb51b7
PX		 2457 trace_vtd_ir_irte_get(index, le64_to_cpu(entry->data[1]),
2458 le64_to_cpu(entry->data[0]));
2459
bc38ee10 2460 if (!entry->irte.present) {
7feb51b7
PX		 2461 trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]),
2462 le64_to_cpu(entry->data[0]));
651e4cef
PX		 2463 return -VTD_FR_IR_ENTRY_P;
2464 }
2465
bc38ee10
MT		 2466 if (entry->irte.__reserved_0 || entry->irte.__reserved_1 ||
2467 entry->irte.__reserved_2) {
7feb51b7
PX		 2468 trace_vtd_err_irte(index, le64_to_cpu(entry->data[1]),
2469 le64_to_cpu(entry->data[0]));
651e4cef
PX		 2470 return -VTD_FR_IR_IRTE_RSVD;
2471 }
2472
ede9c94a
PX		 2473 if (sid != X86_IOMMU_SID_INVALID) {
2474 /* Validate IRTE SID */
bc38ee10
MT		 2475 source_id = le32_to_cpu(entry->irte.source_id);
2476 switch (entry->irte.sid_vtype) {
ede9c94a 2477 case VTD_SVT_NONE:
ede9c94a
PX		 2478 break;
2479
2480 case VTD_SVT_ALL:
bc38ee10 2481 mask = vtd_svt_mask[entry->irte.sid_q];
ede9c94a 2482 if ((source_id & mask) != (sid & mask)) {
7feb51b7 2483 trace_vtd_err_irte_sid(index, sid, source_id);
ede9c94a
PX		 2484 return -VTD_FR_IR_SID_ERR;
2485 }
2486 break;
2487
2488 case VTD_SVT_BUS:
2489 bus_max = source_id >> 8;
2490 bus_min = source_id & 0xff;
2491 bus = sid >> 8;
2492 if (bus > bus_max || bus < bus_min) {
7feb51b7 2493 trace_vtd_err_irte_sid_bus(index, bus, bus_min, bus_max);
ede9c94a
PX		 2494 return -VTD_FR_IR_SID_ERR;
2495 }
2496 break;
2497
2498 default:
7feb51b7 2499 trace_vtd_err_irte_svt(index, entry->irte.sid_vtype);
ede9c94a
PX		 2500 /* Take this as verification failure. */
2501 return -VTD_FR_IR_SID_ERR;
2502 break;
2503 }
2504 }
651e4cef
PX		 2505
2506 return 0;
2507}
2508
2509/* Fetch IRQ information of specific IR index */
ede9c94a
PX		 2510static int vtd_remap_irq_get(IntelIOMMUState *iommu, uint16_t index,
2511 VTDIrq *irq, uint16_t sid)
651e4cef 2512{
bc38ee10 2513 VTD_IR_TableEntry irte = {};
651e4cef
PX		 2514 int ret = 0;
2515
ede9c94a 2516 ret = vtd_irte_get(iommu, index, &irte, sid);
651e4cef
PX		 2517 if (ret) {
2518 return ret;
2519 }
2520
bc38ee10
MT		 2521 irq->trigger_mode = irte.irte.trigger_mode;
2522 irq->vector = irte.irte.vector;
2523 irq->delivery_mode = irte.irte.delivery_mode;
2524 irq->dest = le32_to_cpu(irte.irte.dest_id);
28589311 2525 if (!iommu->intr_eime) {
651e4cef
PX		 2526#define VTD_IR_APIC_DEST_MASK (0xff00ULL)
2527#define VTD_IR_APIC_DEST_SHIFT (8)
28589311
JK		 2528 irq->dest = (irq->dest & VTD_IR_APIC_DEST_MASK) >>
2529 VTD_IR_APIC_DEST_SHIFT;
2530 }
bc38ee10
MT		 2531 irq->dest_mode = irte.irte.dest_mode;
2532 irq->redir_hint = irte.irte.redir_hint;
651e4cef 2533
7feb51b7
PX		 2534 trace_vtd_ir_remap(index, irq->trigger_mode, irq->vector,
2535 irq->delivery_mode, irq->dest, irq->dest_mode);
651e4cef
PX		 2536
2537 return 0;
2538}
2539
2540/* Generate one MSI message from VTDIrq info */
2541static void vtd_generate_msi_message(VTDIrq *irq, MSIMessage *msg_out)
2542{
2543 VTD_MSIMessage msg = {};
2544
2545 /* Generate address bits */
2546 msg.dest_mode = irq->dest_mode;
2547 msg.redir_hint = irq->redir_hint;
2548 msg.dest = irq->dest;
32946019 2549 msg.__addr_hi = irq->dest & 0xffffff00;
651e4cef
PX		 2550 msg.__addr_head = cpu_to_le32(0xfee);
2551 /* Keep this from original MSI address bits */
2552 msg.__not_used = irq->msi_addr_last_bits;
2553
2554 /* Generate data bits */
2555 msg.vector = irq->vector;
2556 msg.delivery_mode = irq->delivery_mode;
2557 msg.level = 1;
2558 msg.trigger_mode = irq->trigger_mode;
2559
2560 msg_out->address = msg.msi_addr;
2561 msg_out->data = msg.msi_data;
2562}
2563
2564/* Interrupt remapping for MSI/MSI-X entry */
2565static int vtd_interrupt_remap_msi(IntelIOMMUState *iommu,
2566 MSIMessage *origin,
ede9c94a
PX		 2567 MSIMessage *translated,
2568 uint16_t sid)
651e4cef
PX		 2569{
2570 int ret = 0;
2571 VTD_IR_MSIAddress addr;
2572 uint16_t index;
09cd058a 2573 VTDIrq irq = {};
651e4cef
PX		 2574
2575 assert(origin && translated);
2576
7feb51b7
PX		 2577 trace_vtd_ir_remap_msi_req(origin->address, origin->data);
2578
651e4cef 2579 if (!iommu || !iommu->intr_enabled) {
e7a3b91f
PX		 2580 memcpy(translated, origin, sizeof(*origin));
2581 goto out;
651e4cef
PX		 2582 }
2583
2584 if (origin->address & VTD_MSI_ADDR_HI_MASK) {
7feb51b7
PX		 2585 trace_vtd_err("MSI address high 32 bits non-zero when "
2586 "Interrupt Remapping enabled.");
651e4cef
PX		 2587 return -VTD_FR_IR_REQ_RSVD;
2588 }
2589
2590 addr.data = origin->address & VTD_MSI_ADDR_LO_MASK;
1a43713b 2591 if (addr.addr.__head != 0xfee) {
7feb51b7 2592 trace_vtd_err("MSI addr low 32 bit invalid.");
651e4cef
PX		 2593 return -VTD_FR_IR_REQ_RSVD;
2594 }
2595
2596 /* This is compatible mode. */
bc38ee10 2597 if (addr.addr.int_mode != VTD_IR_INT_FORMAT_REMAP) {
e7a3b91f
PX		 2598 memcpy(translated, origin, sizeof(*origin));
2599 goto out;
651e4cef
PX		 2600 }
2601
bc38ee10 2602 index = addr.addr.index_h << 15 | le16_to_cpu(addr.addr.index_l);
651e4cef
PX		 2603
2604#define VTD_IR_MSI_DATA_SUBHANDLE (0x0000ffff)
2605#define VTD_IR_MSI_DATA_RESERVED (0xffff0000)
2606
bc38ee10 2607 if (addr.addr.sub_valid) {
651e4cef
PX		 2608 /* See VT-d spec 5.1.2.2 and 5.1.3 on subhandle */
2609 index += origin->data & VTD_IR_MSI_DATA_SUBHANDLE;
2610 }
2611
ede9c94a 2612 ret = vtd_remap_irq_get(iommu, index, &irq, sid);
651e4cef
PX		 2613 if (ret) {
2614 return ret;
2615 }
2616
bc38ee10 2617 if (addr.addr.sub_valid) {
7feb51b7 2618 trace_vtd_ir_remap_type("MSI");
651e4cef 2619 if (origin->data & VTD_IR_MSI_DATA_RESERVED) {
7feb51b7 2620 trace_vtd_err_ir_msi_invalid(sid, origin->address, origin->data);
651e4cef
PX		 2621 return -VTD_FR_IR_REQ_RSVD;
2622 }
2623 } else {
2624 uint8_t vector = origin->data & 0xff;
dea651a9
FW		 2625 uint8_t trigger_mode = (origin->data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
2626
7feb51b7 2627 trace_vtd_ir_remap_type("IOAPIC");
651e4cef
PX		 2628 /* IOAPIC entry vector should be aligned with IRTE vector
2629 * (see vt-d spec 5.1.5.1). */
2630 if (vector != irq.vector) {
7feb51b7 2631 trace_vtd_warn_ir_vector(sid, index, vector, irq.vector);
651e4cef 2632 }
dea651a9
FW		 2633
2634 /* The Trigger Mode field must match the Trigger Mode in the IRTE.
2635 * (see vt-d spec 5.1.5.1). */
2636 if (trigger_mode != irq.trigger_mode) {
7feb51b7
PX		 2637 trace_vtd_warn_ir_trigger(sid, index, trigger_mode,
2638 irq.trigger_mode);
dea651a9 2639 }
651e4cef
PX		 2640 }
2641
2642 /*
2643 * We'd better keep the last two bits, assuming that guest OS
2644 * might modify it. Keep it does not hurt after all.
2645 */
bc38ee10 2646 irq.msi_addr_last_bits = addr.addr.__not_care;
651e4cef
PX		 2647
2648 /* Translate VTDIrq to MSI message */
2649 vtd_generate_msi_message(&irq, translated);
2650
e7a3b91f 2651out:
7feb51b7
PX		 2652 trace_vtd_ir_remap_msi(origin->address, origin->data,
2653 translated->address, translated->data);
651e4cef
PX		 2654 return 0;
2655}
2656
8b5ed7df
PX		 2657static int vtd_int_remap(X86IOMMUState *iommu, MSIMessage *src,
2658 MSIMessage *dst, uint16_t sid)
2659{
ede9c94a
PX		 2660 return vtd_interrupt_remap_msi(INTEL_IOMMU_DEVICE(iommu),
2661 src, dst, sid);
8b5ed7df
PX		 2662}
2663
651e4cef
PX		 2664static MemTxResult vtd_mem_ir_read(void *opaque, hwaddr addr,
2665 uint64_t *data, unsigned size,
2666 MemTxAttrs attrs)
2667{
2668 return MEMTX_OK;
2669}
2670
2671static MemTxResult vtd_mem_ir_write(void *opaque, hwaddr addr,
2672 uint64_t value, unsigned size,
2673 MemTxAttrs attrs)
2674{
2675 int ret = 0;
09cd058a 2676 MSIMessage from = {}, to = {};
ede9c94a 2677 uint16_t sid = X86_IOMMU_SID_INVALID;
651e4cef
PX		 2678
2679 from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
2680 from.data = (uint32_t) value;
2681
ede9c94a
PX		 2682 if (!attrs.unspecified) {
2683 /* We have explicit Source ID */
2684 sid = attrs.requester_id;
2685 }
2686
2687 ret = vtd_interrupt_remap_msi(opaque, &from, &to, sid);
651e4cef
PX		 2688 if (ret) {
2689 /* TODO: report error */
651e4cef
PX		 2690 /* Drop this interrupt */
2691 return MEMTX_ERROR;
2692 }
2693
32946019 2694 apic_get_class()->send_msi(&to);
651e4cef
PX		 2695
2696 return MEMTX_OK;
2697}
2698
2699static const MemoryRegionOps vtd_mem_ir_ops = {
2700 .read_with_attrs = vtd_mem_ir_read,
2701 .write_with_attrs = vtd_mem_ir_write,
2702 .endianness = DEVICE_LITTLE_ENDIAN,
2703 .impl = {
2704 .min_access_size = 4,
2705 .max_access_size = 4,
2706 },
2707 .valid = {
2708 .min_access_size = 4,
2709 .max_access_size = 4,
2710 },
2711};
7df953bd
KO		 2712
2713VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
2714{
2715 uintptr_t key = (uintptr_t)bus;
2716 VTDBus *vtd_bus = g_hash_table_lookup(s->vtd_as_by_busptr, &key);
2717 VTDAddressSpace *vtd_dev_as;
e0a3c8cc 2718 char name[128];
7df953bd
KO		 2719
2720 if (!vtd_bus) {
2d3fc581
JW		 2721 uintptr_t *new_key = g_malloc(sizeof(*new_key));
2722 *new_key = (uintptr_t)bus;
7df953bd 2723 /* No corresponding free() */
04af0e18 2724 vtd_bus = g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) * \
bf33cc75 2725 PCI_DEVFN_MAX);
7df953bd 2726 vtd_bus->bus = bus;
2d3fc581 2727 g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus);
7df953bd
KO		 2728 }
2729
2730 vtd_dev_as = vtd_bus->dev_as[devfn];
2731
2732 if (!vtd_dev_as) {
e0a3c8cc 2733 snprintf(name, sizeof(name), "intel_iommu_devfn_%d", devfn);
7df953bd
KO		 2734 vtd_bus->dev_as[devfn] = vtd_dev_as = g_malloc0(sizeof(VTDAddressSpace));
2735
2736 vtd_dev_as->bus = bus;
2737 vtd_dev_as->devfn = (uint8_t)devfn;
2738 vtd_dev_as->iommu_state = s;
2739 vtd_dev_as->context_cache_entry.context_cache_gen = 0;
558e0024
PX		 2740
2741 /*
2742 * Memory region relationships looks like (Address range shows
2743 * only lower 32 bits to make it short in length...):
2744 *
2745 * |-----------------+-------------------+----------|
2746 * | Name | Address range | Priority |
2747 * |-----------------+-------------------+----------+
2748 * | vtd_root | 00000000-ffffffff | 0 |
2749 * | intel_iommu | 00000000-ffffffff | 1 |
2750 * | vtd_sys_alias | 00000000-ffffffff | 1 |
2751 * | intel_iommu_ir | fee00000-feefffff | 64 |
2752 * |-----------------+-------------------+----------|
2753 *
2754 * We enable/disable DMAR by switching enablement for
2755 * vtd_sys_alias and intel_iommu regions. IR region is always
2756 * enabled.
2757 */
1221a474
AK		 2758 memory_region_init_iommu(&vtd_dev_as->iommu, sizeof(vtd_dev_as->iommu),
2759 TYPE_INTEL_IOMMU_MEMORY_REGION, OBJECT(s),
2760 "intel_iommu_dmar",
558e0024
PX		 2761 UINT64_MAX);
2762 memory_region_init_alias(&vtd_dev_as->sys_alias, OBJECT(s),
2763 "vtd_sys_alias", get_system_memory(),
2764 0, memory_region_size(get_system_memory()));
651e4cef
PX		 2765 memory_region_init_io(&vtd_dev_as->iommu_ir, OBJECT(s),
2766 &vtd_mem_ir_ops, s, "intel_iommu_ir",
2767 VTD_INTERRUPT_ADDR_SIZE);
558e0024
PX		 2768 memory_region_init(&vtd_dev_as->root, OBJECT(s),
2769 "vtd_root", UINT64_MAX);
2770 memory_region_add_subregion_overlap(&vtd_dev_as->root,
2771 VTD_INTERRUPT_ADDR_FIRST,
2772 &vtd_dev_as->iommu_ir, 64);
2773 address_space_init(&vtd_dev_as->as, &vtd_dev_as->root, name);
2774 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
2775 &vtd_dev_as->sys_alias, 1);
2776 memory_region_add_subregion_overlap(&vtd_dev_as->root, 0,
3df9d748
AK		 2777 MEMORY_REGION(&vtd_dev_as->iommu),
2778 1);
558e0024 2779 vtd_switch_address_space(vtd_dev_as);
7df953bd
KO		 2780 }
2781 return vtd_dev_as;
2782}
2783
dd4d607e
PX		 2784/* Unmap the whole range in the notifier's scope. */
2785static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n)
2786{
2787 IOMMUTLBEntry entry;
2788 hwaddr size;
2789 hwaddr start = n->start;
2790 hwaddr end = n->end;
37f51384 2791 IntelIOMMUState *s = as->iommu_state;
dd4d607e
PX		 2792
2793 /*
2794 * Note: all the codes in this function has a assumption that IOVA
2795 * bits are no more than VTD_MGAW bits (which is restricted by
2796 * VT-d spec), otherwise we need to consider overflow of 64 bits.
2797 */
2798
37f51384 2799 if (end > VTD_ADDRESS_SIZE(s->aw_bits)) {
dd4d607e
PX		 2800 /*
2801 * Don't need to unmap regions that is bigger than the whole
2802 * VT-d supported address space size
2803 */
37f51384 2804 end = VTD_ADDRESS_SIZE(s->aw_bits);
dd4d607e
PX		 2805 }
2806
2807 assert(start <= end);
2808 size = end - start;
2809
2810 if (ctpop64(size) != 1) {
2811 /*
2812 * This size cannot format a correct mask. Let's enlarge it to
2813 * suite the minimum available mask.
2814 */
2815 int n = 64 - clz64(size);
37f51384 2816 if (n > s->aw_bits) {
dd4d607e 2817 /* should not happen, but in case it happens, limit it */
37f51384 2818 n = s->aw_bits;
dd4d607e
PX		 2819 }
2820 size = 1ULL << n;
2821 }
2822
2823 entry.target_as = &address_space_memory;
2824 /* Adjust iova for the size */
2825 entry.iova = n->start & ~(size - 1);
2826 /* This field is meaningless for unmap */
2827 entry.translated_addr = 0;
2828 entry.perm = IOMMU_NONE;
2829 entry.addr_mask = size - 1;
2830
2831 trace_vtd_as_unmap_whole(pci_bus_num(as->bus),
2832 VTD_PCI_SLOT(as->devfn),
2833 VTD_PCI_FUNC(as->devfn),
2834 entry.iova, size);
2835
2836 memory_region_notify_one(n, &entry);
2837}
2838
2839static void vtd_address_space_unmap_all(IntelIOMMUState *s)
2840{
2841 IntelIOMMUNotifierNode *node;
2842 VTDAddressSpace *vtd_as;
2843 IOMMUNotifier *n;
2844
2845 QLIST_FOREACH(node, &s->notifiers_list, next) {
2846 vtd_as = node->vtd_as;
2847 IOMMU_NOTIFIER_FOREACH(n, &vtd_as->iommu) {
2848 vtd_address_space_unmap(vtd_as, n);
2849 }
2850 }
2851}
2852
f06a696d
PX		 2853static int vtd_replay_hook(IOMMUTLBEntry *entry, void *private)
2854{
2855 memory_region_notify_one((IOMMUNotifier *)private, entry);
2856 return 0;
2857}
2858
3df9d748 2859static void vtd_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
f06a696d 2860{
3df9d748 2861 VTDAddressSpace *vtd_as = container_of(iommu_mr, VTDAddressSpace, iommu);
f06a696d
PX		 2862 IntelIOMMUState *s = vtd_as->iommu_state;
2863 uint8_t bus_n = pci_bus_num(vtd_as->bus);
2864 VTDContextEntry ce;
2865
dd4d607e
PX		 2866 /*
2867 * The replay can be triggered by either a invalidation or a newly
2868 * created entry. No matter what, we release existing mappings
2869 * (it means flushing caches for UNMAP-only registers).
2870 */
2871 vtd_address_space_unmap(vtd_as, n);
2872
f06a696d 2873 if (vtd_dev_to_context_entry(s, bus_n, vtd_as->devfn, &ce) == 0) {
f06a696d
PX		 2874 trace_vtd_replay_ce_valid(bus_n, PCI_SLOT(vtd_as->devfn),
2875 PCI_FUNC(vtd_as->devfn),
2876 VTD_CONTEXT_ENTRY_DID(ce.hi),
2877 ce.hi, ce.lo);
37f51384
PS		 2878 vtd_page_walk(&ce, 0, ~0ULL, vtd_replay_hook, (void *)n, false,
2879 s->aw_bits);
f06a696d
PX		 2880 } else {
2881 trace_vtd_replay_ce_invalid(bus_n, PCI_SLOT(vtd_as->devfn),
2882 PCI_FUNC(vtd_as->devfn));
2883 }
2884
2885 return;
2886}
2887
1da12ec4
LT		 2888/* Do the initialization. It will also be called when reset, so pay
2889 * attention when adding new initialization stuff.
2890 */
2891static void vtd_init(IntelIOMMUState *s)
2892{
d54bd7f8
PX		 2893 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
2894
1da12ec4
LT		 2895 memset(s->csr, 0, DMAR_REG_SIZE);
2896 memset(s->wmask, 0, DMAR_REG_SIZE);
2897 memset(s->w1cmask, 0, DMAR_REG_SIZE);
2898 memset(s->womask, 0, DMAR_REG_SIZE);
2899
1da12ec4
LT		 2900 s->root = 0;
2901 s->root_extended = false;
2902 s->dmar_enabled = false;
2903 s->iq_head = 0;
2904 s->iq_tail = 0;
2905 s->iq = 0;
2906 s->iq_size = 0;
2907 s->qi_enabled = false;
2908 s->iq_last_desc_type = VTD_INV_DESC_NONE;
2909 s->next_frcd_reg = 0;
92e5d85e
PS		 2910 s->cap = VTD_CAP_FRO | VTD_CAP_NFR | VTD_CAP_ND |
2911 VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS |
37f51384
PS		 2912 VTD_CAP_SAGAW_39bit | VTD_CAP_MGAW(s->aw_bits);
2913 if (s->aw_bits == VTD_HOST_AW_48BIT) {
2914 s->cap |= VTD_CAP_SAGAW_48bit;
2915 }
ed7b8fbc 2916 s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO;
1da12ec4 2917
92e5d85e
PS		 2918 /*
2919 * Rsvd field masks for spte
2920 */
2921 vtd_paging_entry_rsvd_field[0] = ~0ULL;
37f51384
PS		 2922 vtd_paging_entry_rsvd_field[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
2923 vtd_paging_entry_rsvd_field[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
2924 vtd_paging_entry_rsvd_field[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
2925 vtd_paging_entry_rsvd_field[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
2926 vtd_paging_entry_rsvd_field[5] = VTD_SPTE_LPAGE_L1_RSVD_MASK(s->aw_bits);
2927 vtd_paging_entry_rsvd_field[6] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
2928 vtd_paging_entry_rsvd_field[7] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
2929 vtd_paging_entry_rsvd_field[8] = VTD_SPTE_LPAGE_L4_RSVD_MASK(s->aw_bits);
92e5d85e 2930
d54bd7f8 2931 if (x86_iommu->intr_supported) {
e6b6af05
RK		 2932 s->ecap |= VTD_ECAP_IR | VTD_ECAP_MHMV;
2933 if (s->intr_eim == ON_OFF_AUTO_ON) {
2934 s->ecap |= VTD_ECAP_EIM;
2935 }
2936 assert(s->intr_eim != ON_OFF_AUTO_AUTO);
d54bd7f8
PX		 2937 }
2938
554f5e16
JW		 2939 if (x86_iommu->dt_supported) {
2940 s->ecap |= VTD_ECAP_DT;
2941 }
2942
dbaabb25
PX		 2943 if (x86_iommu->pt_supported) {
2944 s->ecap |= VTD_ECAP_PT;
2945 }
2946
3b40f0e5
ABD		 2947 if (s->caching_mode) {
2948 s->cap |= VTD_CAP_CM;
2949 }
2950
d92fa2dc 2951 vtd_reset_context_cache(s);
b5a280c0 2952 vtd_reset_iotlb(s);
d92fa2dc 2953
1da12ec4
LT		 2954 /* Define registers with default values and bit semantics */
2955 vtd_define_long(s, DMAR_VER_REG, 0x10UL, 0, 0);
2956 vtd_define_quad(s, DMAR_CAP_REG, s->cap, 0, 0);
2957 vtd_define_quad(s, DMAR_ECAP_REG, s->ecap, 0, 0);
2958 vtd_define_long(s, DMAR_GCMD_REG, 0, 0xff800000UL, 0);
2959 vtd_define_long_wo(s, DMAR_GCMD_REG, 0xff800000UL);
2960 vtd_define_long(s, DMAR_GSTS_REG, 0, 0, 0);
2961 vtd_define_quad(s, DMAR_RTADDR_REG, 0, 0xfffffffffffff000ULL, 0);
2962 vtd_define_quad(s, DMAR_CCMD_REG, 0, 0xe0000003ffffffffULL, 0);
2963 vtd_define_quad_wo(s, DMAR_CCMD_REG, 0x3ffff0000ULL);
2964
2965 /* Advanced Fault Logging not supported */
2966 vtd_define_long(s, DMAR_FSTS_REG, 0, 0, 0x11UL);
2967 vtd_define_long(s, DMAR_FECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2968 vtd_define_long(s, DMAR_FEDATA_REG, 0, 0x0000ffffUL, 0);
2969 vtd_define_long(s, DMAR_FEADDR_REG, 0, 0xfffffffcUL, 0);
2970
2971 /* Treated as RsvdZ when EIM in ECAP_REG is not supported
2972 * vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0xffffffffUL, 0);
2973 */
2974 vtd_define_long(s, DMAR_FEUADDR_REG, 0, 0, 0);
2975
2976 /* Treated as RO for implementations that PLMR and PHMR fields reported
2977 * as Clear in the CAP_REG.
2978 * vtd_define_long(s, DMAR_PMEN_REG, 0, 0x80000000UL, 0);
2979 */
2980 vtd_define_long(s, DMAR_PMEN_REG, 0, 0, 0);
2981
ed7b8fbc
LT		 2982 vtd_define_quad(s, DMAR_IQH_REG, 0, 0, 0);
2983 vtd_define_quad(s, DMAR_IQT_REG, 0, 0x7fff0ULL, 0);
2984 vtd_define_quad(s, DMAR_IQA_REG, 0, 0xfffffffffffff007ULL, 0);
2985 vtd_define_long(s, DMAR_ICS_REG, 0, 0, 0x1UL);
2986 vtd_define_long(s, DMAR_IECTL_REG, 0x80000000UL, 0x80000000UL, 0);
2987 vtd_define_long(s, DMAR_IEDATA_REG, 0, 0xffffffffUL, 0);
2988 vtd_define_long(s, DMAR_IEADDR_REG, 0, 0xfffffffcUL, 0);
2989 /* Treadted as RsvdZ when EIM in ECAP_REG is not supported */
2990 vtd_define_long(s, DMAR_IEUADDR_REG, 0, 0, 0);
2991
1da12ec4
LT		 2992 /* IOTLB registers */
2993 vtd_define_quad(s, DMAR_IOTLB_REG, 0, 0Xb003ffff00000000ULL, 0);
2994 vtd_define_quad(s, DMAR_IVA_REG, 0, 0xfffffffffffff07fULL, 0);
2995 vtd_define_quad_wo(s, DMAR_IVA_REG, 0xfffffffffffff07fULL);
2996
2997 /* Fault Recording Registers, 128-bit */
2998 vtd_define_quad(s, DMAR_FRCD_REG_0_0, 0, 0, 0);
2999 vtd_define_quad(s, DMAR_FRCD_REG_0_2, 0, 0, 0x8000000000000000ULL);
a5861439
PX		 3000
3001 /*
28589311 3002 * Interrupt remapping registers.
a5861439 3003 */
28589311 3004 vtd_define_quad(s, DMAR_IRTA_REG, 0, 0xfffffffffffff80fULL, 0);
1da12ec4
LT		 3005}
3006
3007/* Should not reset address_spaces when reset because devices will still use
3008 * the address space they got at first (won't ask the bus again).
3009 */
3010static void vtd_reset(DeviceState *dev)
3011{
3012 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
3013
1da12ec4 3014 vtd_init(s);
dd4d607e
PX		 3015
3016 /*
3017 * When device reset, throw away all mappings and external caches
3018 */
3019 vtd_address_space_unmap_all(s);
1da12ec4
LT		 3020}
3021
621d983a
MA		 3022static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, void *opaque, int devfn)
3023{
3024 IntelIOMMUState *s = opaque;
3025 VTDAddressSpace *vtd_as;
3026
bf33cc75 3027 assert(0 <= devfn && devfn < PCI_DEVFN_MAX);
621d983a
MA		 3028
3029 vtd_as = vtd_find_add_as(s, bus, devfn);
3030 return &vtd_as->as;
3031}
3032
e6b6af05 3033static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)
6333e93c 3034{
e6b6af05
RK		 3035 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
3036
6333e93c
RK		 3037 /* Currently Intel IOMMU IR only support "kernel-irqchip={off|split}" */
3038 if (x86_iommu->intr_supported && kvm_irqchip_in_kernel() &&
3039 !kvm_irqchip_is_split()) {
3040 error_setg(errp, "Intel Interrupt Remapping cannot work with "
3041 "kernel-irqchip=on, please use 'split|off'.");
3042 return false;
3043 }
e6b6af05
RK		 3044 if (s->intr_eim == ON_OFF_AUTO_ON && !x86_iommu->intr_supported) {
3045 error_setg(errp, "eim=on cannot be selected without intremap=on");
3046 return false;
3047 }
3048
3049 if (s->intr_eim == ON_OFF_AUTO_AUTO) {
fb506e70
RK		 3050 s->intr_eim = (kvm_irqchip_in_kernel() || s->buggy_eim)
3051 && x86_iommu->intr_supported ?
e6b6af05
RK		 3052 ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;
3053 }
fb506e70
RK		 3054 if (s->intr_eim == ON_OFF_AUTO_ON && !s->buggy_eim) {
3055 if (!kvm_irqchip_in_kernel()) {
3056 error_setg(errp, "eim=on requires accel=kvm,kernel-irqchip=split");
3057 return false;
3058 }
3059 if (!kvm_enable_x2apic()) {
3060 error_setg(errp, "eim=on requires support on the KVM side"
3061 "(X2APIC_API, first shipped in v4.7)");
3062 return false;
3063 }
3064 }
e6b6af05 3065
37f51384
PS		 3066 /* Currently only address widths supported are 39 and 48 bits */
3067 if ((s->aw_bits != VTD_HOST_AW_39BIT) &&
3068 (s->aw_bits != VTD_HOST_AW_48BIT)) {
3069 error_setg(errp, "Supported values for x-aw-bits are: %d, %d",
3070 VTD_HOST_AW_39BIT, VTD_HOST_AW_48BIT);
3071 return false;
3072 }
3073
6333e93c
RK		 3074 return true;
3075}
3076
1da12ec4
LT		 3077static void vtd_realize(DeviceState *dev, Error **errp)
3078{
ef0e8fc7 3079 MachineState *ms = MACHINE(qdev_get_machine());
29396ed9
MG		 3080 PCMachineState *pcms = PC_MACHINE(ms);
3081 PCIBus *bus = pcms->bus;
1da12ec4 3082 IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
4684a204 3083 X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(dev);
1da12ec4 3084
fb9f5926 3085 x86_iommu->type = TYPE_INTEL;
6333e93c 3086
e6b6af05 3087 if (!vtd_decide_config(s, errp)) {
6333e93c
RK		 3088 return;
3089 }
3090
dd4d607e 3091 QLIST_INIT(&s->notifiers_list);
7df953bd 3092 memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num));
1da12ec4
LT		 3093 memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s,
3094 "intel_iommu", DMAR_REG_SIZE);
3095 sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->csrmem);
b5a280c0
LT		 3096 /* No corresponding destroy */
3097 s->iotlb = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3098 g_free, g_free);
7df953bd
KO		 3099 s->vtd_as_by_busptr = g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal,
3100 g_free, g_free);
1da12ec4 3101 vtd_init(s);
621d983a
MA		 3102 sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR);
3103 pci_setup_iommu(bus, vtd_host_dma_iommu, dev);
cb135f59
PX		 3104 /* Pseudo address space under root PCI bus. */
3105 pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC);
1da12ec4
LT		 3106}
3107
3108static void vtd_class_init(ObjectClass *klass, void *data)
3109{
3110 DeviceClass *dc = DEVICE_CLASS(klass);
1c7955c4 3111 X86IOMMUClass *x86_class = X86_IOMMU_CLASS(klass);
1da12ec4
LT		 3112
3113 dc->reset = vtd_reset;
1da12ec4
LT		 3114 dc->vmsd = &vtd_vmstate;
3115 dc->props = vtd_properties;
621d983a 3116 dc->hotpluggable = false;
1c7955c4 3117 x86_class->realize = vtd_realize;
8b5ed7df 3118 x86_class->int_remap = vtd_int_remap;
8ab5700c 3119 /* Supported by the pc-q35-* machine types */
e4f4fb1e 3120 dc->user_creatable = true;
1da12ec4
LT		 3121}
3122
3123static const TypeInfo vtd_info = {
3124 .name = TYPE_INTEL_IOMMU_DEVICE,
1c7955c4 3125 .parent = TYPE_X86_IOMMU_DEVICE,
1da12ec4
LT		 3126 .instance_size = sizeof(IntelIOMMUState),
3127 .class_init = vtd_class_init,
3128};
3129
1221a474
AK		 3130static void vtd_iommu_memory_region_class_init(ObjectClass *klass,
3131 void *data)
3132{
3133 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
3134
3135 imrc->translate = vtd_iommu_translate;
3136 imrc->notify_flag_changed = vtd_iommu_notify_flag_changed;
3137 imrc->replay = vtd_iommu_replay;
3138}
3139
3140static const TypeInfo vtd_iommu_memory_region_info = {
3141 .parent = TYPE_IOMMU_MEMORY_REGION,
3142 .name = TYPE_INTEL_IOMMU_MEMORY_REGION,
3143 .class_init = vtd_iommu_memory_region_class_init,
3144};
3145
1da12ec4
LT		 3146static void vtd_register_types(void)
3147{
1da12ec4 3148 type_register_static(&vtd_info);
1221a474 3149 type_register_static(&vtd_iommu_memory_region_info);
1da12ec4
LT		 3150}
3151
3152type_init(vtd_register_types)
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