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Commit | Line | Data |
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3475187d | 1 | /* |
c7ba218d | 2 | * QEMU Sun4u/Sun4v System Emulator |
5fafdf24 | 3 | * |
3475187d | 4 | * Copyright (c) 2005 Fabrice Bellard |
5fafdf24 | 5 | * |
3475187d FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
db5ebe5f | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
4771d756 PB |
26 | #include "qemu-common.h" |
27 | #include "cpu.h" | |
83c9f4ca PB |
28 | #include "hw/hw.h" |
29 | #include "hw/pci/pci.h" | |
0d09e41a PB |
30 | #include "hw/pci-host/apb.h" |
31 | #include "hw/i386/pc.h" | |
32 | #include "hw/char/serial.h" | |
33 | #include "hw/timer/m48t59.h" | |
34 | #include "hw/block/fdc.h" | |
1422e32d | 35 | #include "net/net.h" |
1de7afc9 | 36 | #include "qemu/timer.h" |
9c17d615 | 37 | #include "sysemu/sysemu.h" |
83c9f4ca | 38 | #include "hw/boards.h" |
c6363bae | 39 | #include "hw/nvram/sun_nvram.h" |
2024c014 | 40 | #include "hw/nvram/chrp_nvram.h" |
fff54d22 | 41 | #include "hw/sparc/sparc64.h" |
0d09e41a | 42 | #include "hw/nvram/fw_cfg.h" |
83c9f4ca PB |
43 | #include "hw/sysbus.h" |
44 | #include "hw/ide.h" | |
45 | #include "hw/loader.h" | |
ca20cf32 | 46 | #include "elf.h" |
f348b6d1 | 47 | #include "qemu/cutils.h" |
3475187d | 48 | |
b430a225 | 49 | //#define DEBUG_EBUS |
b430a225 BS |
50 | |
51 | #ifdef DEBUG_EBUS | |
52 | #define EBUS_DPRINTF(fmt, ...) \ | |
53 | do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0) | |
54 | #else | |
55 | #define EBUS_DPRINTF(fmt, ...) | |
9d926598 BS |
56 | #endif |
57 | ||
83469015 FB |
58 | #define KERNEL_LOAD_ADDR 0x00404000 |
59 | #define CMDLINE_ADDR 0x003ff000 | |
ac2e9d66 | 60 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
f930d07e | 61 | #define PROM_VADDR 0x000ffd00000ULL |
83469015 | 62 | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
f930d07e | 63 | #define APB_MEM_BASE 0x1ff00000000ULL |
d63baf92 | 64 | #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) |
f930d07e | 65 | #define PROM_FILENAME "openbios-sparc64" |
83469015 | 66 | #define NVRAM_SIZE 0x2000 |
e4bcb14c | 67 | #define MAX_IDE_BUS 2 |
3cce6243 | 68 | #define BIOS_CFG_IOPORT 0x510 |
7589690c BS |
69 | #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) |
70 | #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01) | |
71 | #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02) | |
3475187d | 72 | |
852e82f3 | 73 | #define IVEC_MAX 0x40 |
9d926598 | 74 | |
c7ba218d BS |
75 | struct hwdef { |
76 | const char * const default_cpu_model; | |
905fdcb5 | 77 | uint16_t machine_id; |
e87231d4 BS |
78 | uint64_t prom_addr; |
79 | uint64_t console_serial_base; | |
c7ba218d BS |
80 | }; |
81 | ||
c5e6fb7e AK |
82 | typedef struct EbusState { |
83 | PCIDevice pci_dev; | |
84 | MemoryRegion bar0; | |
85 | MemoryRegion bar1; | |
86 | } EbusState; | |
87 | ||
57146941 | 88 | void DMA_init(ISABus *bus, int high_page_enable) |
4556bd8b BS |
89 | { |
90 | } | |
91 | ||
ddcd5531 GA |
92 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
93 | Error **errp) | |
81864572 | 94 | { |
48779e50 | 95 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
96 | } |
97 | ||
31688246 | 98 | static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size, |
43a34704 BS |
99 | const char *arch, ram_addr_t RAM_size, |
100 | const char *boot_devices, | |
101 | uint32_t kernel_image, uint32_t kernel_size, | |
102 | const char *cmdline, | |
103 | uint32_t initrd_image, uint32_t initrd_size, | |
104 | uint32_t NVRAM_image, | |
105 | int width, int height, int depth, | |
106 | const uint8_t *macaddr) | |
83469015 | 107 | { |
66508601 | 108 | unsigned int i; |
2024c014 | 109 | int sysp_end; |
d2c63fc1 | 110 | uint8_t image[0x1ff0]; |
31688246 | 111 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
112 | |
113 | memset(image, '\0', sizeof(image)); | |
114 | ||
2024c014 TH |
115 | /* OpenBIOS nvram variables partition */ |
116 | sysp_end = chrp_nvram_create_system_partition(image, 0); | |
83469015 | 117 | |
2024c014 TH |
118 | /* Free space partition */ |
119 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 120 | |
0d31cb99 BS |
121 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
122 | ||
31688246 HP |
123 | for (i = 0; i < sizeof(image); i++) { |
124 | (k->write)(nvram, i, image[i]); | |
125 | } | |
66508601 | 126 | |
83469015 | 127 | return 0; |
3475187d | 128 | } |
5f2bf0fe BS |
129 | |
130 | static uint64_t sun4u_load_kernel(const char *kernel_filename, | |
131 | const char *initrd_filename, | |
132 | ram_addr_t RAM_size, uint64_t *initrd_size, | |
133 | uint64_t *initrd_addr, uint64_t *kernel_addr, | |
134 | uint64_t *kernel_entry) | |
636aa70a BS |
135 | { |
136 | int linux_boot; | |
137 | unsigned int i; | |
138 | long kernel_size; | |
6908d9ce | 139 | uint8_t *ptr; |
5f2bf0fe | 140 | uint64_t kernel_top; |
636aa70a BS |
141 | |
142 | linux_boot = (kernel_filename != NULL); | |
143 | ||
144 | kernel_size = 0; | |
145 | if (linux_boot) { | |
ca20cf32 BS |
146 | int bswap_needed; |
147 | ||
148 | #ifdef BSWAP_NEEDED | |
149 | bswap_needed = 1; | |
150 | #else | |
151 | bswap_needed = 0; | |
152 | #endif | |
5f2bf0fe | 153 | kernel_size = load_elf(kernel_filename, NULL, NULL, kernel_entry, |
7ef295ea | 154 | kernel_addr, &kernel_top, 1, EM_SPARCV9, 0, 0); |
5f2bf0fe BS |
155 | if (kernel_size < 0) { |
156 | *kernel_addr = KERNEL_LOAD_ADDR; | |
157 | *kernel_entry = KERNEL_LOAD_ADDR; | |
636aa70a | 158 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
159 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
160 | TARGET_PAGE_SIZE); | |
5f2bf0fe BS |
161 | } |
162 | if (kernel_size < 0) { | |
636aa70a BS |
163 | kernel_size = load_image_targphys(kernel_filename, |
164 | KERNEL_LOAD_ADDR, | |
165 | RAM_size - KERNEL_LOAD_ADDR); | |
5f2bf0fe | 166 | } |
636aa70a BS |
167 | if (kernel_size < 0) { |
168 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
169 | kernel_filename); | |
170 | exit(1); | |
171 | } | |
5f2bf0fe | 172 | /* load initrd above kernel */ |
636aa70a BS |
173 | *initrd_size = 0; |
174 | if (initrd_filename) { | |
5f2bf0fe BS |
175 | *initrd_addr = TARGET_PAGE_ALIGN(kernel_top); |
176 | ||
636aa70a | 177 | *initrd_size = load_image_targphys(initrd_filename, |
5f2bf0fe BS |
178 | *initrd_addr, |
179 | RAM_size - *initrd_addr); | |
180 | if ((int)*initrd_size < 0) { | |
636aa70a BS |
181 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
182 | initrd_filename); | |
183 | exit(1); | |
184 | } | |
185 | } | |
186 | if (*initrd_size > 0) { | |
187 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
5f2bf0fe | 188 | ptr = rom_ptr(*kernel_addr + i); |
6908d9ce | 189 | if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */ |
5f2bf0fe | 190 | stl_p(ptr + 24, *initrd_addr + *kernel_addr); |
6908d9ce | 191 | stl_p(ptr + 28, *initrd_size); |
636aa70a BS |
192 | break; |
193 | } | |
194 | } | |
195 | } | |
196 | } | |
197 | return kernel_size; | |
198 | } | |
3475187d | 199 | |
e87231d4 | 200 | typedef struct ResetData { |
403d7a2d | 201 | SPARCCPU *cpu; |
44a99354 | 202 | uint64_t prom_addr; |
e87231d4 BS |
203 | } ResetData; |
204 | ||
361dea40 | 205 | static void isa_irq_handler(void *opaque, int n, int level) |
1387fe4a | 206 | { |
361dea40 BS |
207 | static const int isa_irq_to_ivec[16] = { |
208 | [1] = 0x29, /* keyboard */ | |
209 | [4] = 0x2b, /* serial */ | |
210 | [6] = 0x27, /* floppy */ | |
211 | [7] = 0x22, /* parallel */ | |
212 | [12] = 0x2a, /* mouse */ | |
213 | }; | |
214 | qemu_irq *irqs = opaque; | |
215 | int ivec; | |
216 | ||
1f6fb58d | 217 | assert(n < ARRAY_SIZE(isa_irq_to_ivec)); |
361dea40 BS |
218 | ivec = isa_irq_to_ivec[n]; |
219 | EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec); | |
220 | if (ivec) { | |
221 | qemu_set_irq(irqs[ivec], level); | |
222 | } | |
1387fe4a BS |
223 | } |
224 | ||
c190ea07 | 225 | /* EBUS (Eight bit bus) bridge */ |
48a18b3c | 226 | static ISABus * |
e1030ca5 | 227 | pci_ebus_init(PCIDevice *pci_dev, qemu_irq *irqs) |
c190ea07 | 228 | { |
1387fe4a | 229 | qemu_irq *isa_irq; |
48a18b3c | 230 | ISABus *isa_bus; |
1387fe4a | 231 | |
2ae0e48d | 232 | isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); |
361dea40 | 233 | isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16); |
48a18b3c HP |
234 | isa_bus_irqs(isa_bus, isa_irq); |
235 | return isa_bus; | |
53e3c4f9 | 236 | } |
c190ea07 | 237 | |
3a80cead | 238 | static void pci_ebus_realize(PCIDevice *pci_dev, Error **errp) |
53e3c4f9 | 239 | { |
c5e6fb7e AK |
240 | EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev); |
241 | ||
d10e5432 MA |
242 | if (!isa_bus_new(DEVICE(pci_dev), get_system_memory(), |
243 | pci_address_space_io(pci_dev), errp)) { | |
244 | return; | |
245 | } | |
c5e6fb7e AK |
246 | |
247 | pci_dev->config[0x04] = 0x06; // command = bus master, pci mem | |
248 | pci_dev->config[0x05] = 0x00; | |
249 | pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error | |
250 | pci_dev->config[0x07] = 0x03; // status = medium devsel | |
251 | pci_dev->config[0x09] = 0x00; // programming i/f | |
252 | pci_dev->config[0x0D] = 0x0a; // latency_timer | |
253 | ||
0a70e094 PB |
254 | memory_region_init_alias(&s->bar0, OBJECT(s), "bar0", get_system_io(), |
255 | 0, 0x1000000); | |
e824b2cc | 256 | pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); |
0a70e094 | 257 | memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), |
f3b18f35 | 258 | 0, 0x4000); |
a1cf8be5 | 259 | pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); |
c190ea07 BS |
260 | } |
261 | ||
40021f08 AL |
262 | static void ebus_class_init(ObjectClass *klass, void *data) |
263 | { | |
264 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); | |
265 | ||
3a80cead | 266 | k->realize = pci_ebus_realize; |
40021f08 AL |
267 | k->vendor_id = PCI_VENDOR_ID_SUN; |
268 | k->device_id = PCI_DEVICE_ID_SUN_EBUS; | |
269 | k->revision = 0x01; | |
270 | k->class_id = PCI_CLASS_BRIDGE_OTHER; | |
271 | } | |
272 | ||
8c43a6f0 | 273 | static const TypeInfo ebus_info = { |
39bffca2 AL |
274 | .name = "ebus", |
275 | .parent = TYPE_PCI_DEVICE, | |
276 | .instance_size = sizeof(EbusState), | |
277 | .class_init = ebus_class_init, | |
fd3b02c8 EH |
278 | .interfaces = (InterfaceInfo[]) { |
279 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, | |
280 | { }, | |
281 | }, | |
53e3c4f9 BS |
282 | }; |
283 | ||
13575cf6 AF |
284 | #define TYPE_OPENPROM "openprom" |
285 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
286 | ||
d4edce38 | 287 | typedef struct PROMState { |
13575cf6 AF |
288 | SysBusDevice parent_obj; |
289 | ||
d4edce38 AK |
290 | MemoryRegion prom; |
291 | } PROMState; | |
292 | ||
409dbce5 AJ |
293 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
294 | { | |
a8170e5e | 295 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
296 | return addr + *base_addr - PROM_VADDR; |
297 | } | |
298 | ||
1baffa46 | 299 | /* Boot PROM (OpenBIOS) */ |
a8170e5e | 300 | static void prom_init(hwaddr addr, const char *bios_name) |
1baffa46 BS |
301 | { |
302 | DeviceState *dev; | |
303 | SysBusDevice *s; | |
304 | char *filename; | |
305 | int ret; | |
306 | ||
13575cf6 | 307 | dev = qdev_create(NULL, TYPE_OPENPROM); |
e23a1b33 | 308 | qdev_init_nofail(dev); |
1356b98d | 309 | s = SYS_BUS_DEVICE(dev); |
1baffa46 BS |
310 | |
311 | sysbus_mmio_map(s, 0, addr); | |
312 | ||
313 | /* load boot prom */ | |
314 | if (bios_name == NULL) { | |
315 | bios_name = PROM_FILENAME; | |
316 | } | |
317 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
318 | if (filename) { | |
409dbce5 | 319 | ret = load_elf(filename, translate_prom_address, &addr, |
7ef295ea | 320 | NULL, NULL, NULL, 1, EM_SPARCV9, 0, 0); |
1baffa46 BS |
321 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
322 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
323 | } | |
7267c094 | 324 | g_free(filename); |
1baffa46 BS |
325 | } else { |
326 | ret = -1; | |
327 | } | |
328 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
329 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
330 | exit(1); | |
331 | } | |
332 | } | |
333 | ||
78fb261d | 334 | static void prom_init1(Object *obj) |
1baffa46 | 335 | { |
78fb261d XZ |
336 | PROMState *s = OPENPROM(obj); |
337 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
1baffa46 | 338 | |
1cfe48c1 | 339 | memory_region_init_ram_nomigrate(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX, |
f8ed85ac | 340 | &error_fatal); |
c5705a77 | 341 | vmstate_register_ram_global(&s->prom); |
d4edce38 | 342 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 343 | sysbus_init_mmio(dev, &s->prom); |
1baffa46 BS |
344 | } |
345 | ||
999e12bb AL |
346 | static Property prom_properties[] = { |
347 | {/* end of property list */}, | |
348 | }; | |
349 | ||
350 | static void prom_class_init(ObjectClass *klass, void *data) | |
351 | { | |
39bffca2 | 352 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 353 | |
39bffca2 | 354 | dc->props = prom_properties; |
999e12bb AL |
355 | } |
356 | ||
8c43a6f0 | 357 | static const TypeInfo prom_info = { |
13575cf6 | 358 | .name = TYPE_OPENPROM, |
39bffca2 AL |
359 | .parent = TYPE_SYS_BUS_DEVICE, |
360 | .instance_size = sizeof(PROMState), | |
361 | .class_init = prom_class_init, | |
78fb261d | 362 | .instance_init = prom_init1, |
1baffa46 BS |
363 | }; |
364 | ||
bda42033 | 365 | |
88c034d5 AF |
366 | #define TYPE_SUN4U_MEMORY "memory" |
367 | #define SUN4U_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4U_MEMORY) | |
368 | ||
369 | typedef struct RamDevice { | |
370 | SysBusDevice parent_obj; | |
371 | ||
d4edce38 | 372 | MemoryRegion ram; |
04843626 | 373 | uint64_t size; |
bda42033 BS |
374 | } RamDevice; |
375 | ||
376 | /* System RAM */ | |
78fb261d | 377 | static void ram_realize(DeviceState *dev, Error **errp) |
bda42033 | 378 | { |
88c034d5 | 379 | RamDevice *d = SUN4U_RAM(dev); |
78fb261d | 380 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
bda42033 | 381 | |
1cfe48c1 | 382 | memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size, |
f8ed85ac | 383 | &error_fatal); |
c5705a77 | 384 | vmstate_register_ram_global(&d->ram); |
78fb261d | 385 | sysbus_init_mmio(sbd, &d->ram); |
bda42033 BS |
386 | } |
387 | ||
a8170e5e | 388 | static void ram_init(hwaddr addr, ram_addr_t RAM_size) |
bda42033 BS |
389 | { |
390 | DeviceState *dev; | |
391 | SysBusDevice *s; | |
392 | RamDevice *d; | |
393 | ||
394 | /* allocate RAM */ | |
88c034d5 | 395 | dev = qdev_create(NULL, TYPE_SUN4U_MEMORY); |
1356b98d | 396 | s = SYS_BUS_DEVICE(dev); |
bda42033 | 397 | |
88c034d5 | 398 | d = SUN4U_RAM(dev); |
bda42033 | 399 | d->size = RAM_size; |
e23a1b33 | 400 | qdev_init_nofail(dev); |
bda42033 BS |
401 | |
402 | sysbus_mmio_map(s, 0, addr); | |
403 | } | |
404 | ||
999e12bb AL |
405 | static Property ram_properties[] = { |
406 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
407 | DEFINE_PROP_END_OF_LIST(), | |
408 | }; | |
409 | ||
410 | static void ram_class_init(ObjectClass *klass, void *data) | |
411 | { | |
39bffca2 | 412 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 413 | |
78fb261d | 414 | dc->realize = ram_realize; |
39bffca2 | 415 | dc->props = ram_properties; |
999e12bb AL |
416 | } |
417 | ||
8c43a6f0 | 418 | static const TypeInfo ram_info = { |
88c034d5 | 419 | .name = TYPE_SUN4U_MEMORY, |
39bffca2 AL |
420 | .parent = TYPE_SYS_BUS_DEVICE, |
421 | .instance_size = sizeof(RamDevice), | |
422 | .class_init = ram_class_init, | |
bda42033 BS |
423 | }; |
424 | ||
38bc50f7 | 425 | static void sun4uv_init(MemoryRegion *address_space_mem, |
3ef96221 | 426 | MachineState *machine, |
7b833f5b BS |
427 | const struct hwdef *hwdef) |
428 | { | |
f9d1465f | 429 | SPARCCPU *cpu; |
31688246 | 430 | Nvram *nvram; |
7b833f5b | 431 | unsigned int i; |
5f2bf0fe | 432 | uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; |
311f2b7a | 433 | PCIBus *pci_bus, *pci_busA, *pci_busB; |
8d932971 | 434 | PCIDevice *ebus, *pci_dev; |
48a18b3c | 435 | ISABus *isa_bus; |
f3b18f35 | 436 | SysBusDevice *s; |
361dea40 | 437 | qemu_irq *ivec_irqs, *pbm_irqs; |
f455e98c | 438 | DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
fd8014e1 | 439 | DriveInfo *fd[MAX_FD]; |
c3ae40e1 | 440 | DeviceState *dev; |
a88b362c | 441 | FWCfgState *fw_cfg; |
8d932971 MCA |
442 | NICInfo *nd; |
443 | int onboard_nic_idx; | |
7b833f5b | 444 | |
7b833f5b | 445 | /* init CPUs */ |
fff54d22 AT |
446 | cpu = sparc64_cpu_devinit(machine->cpu_model, hwdef->default_cpu_model, |
447 | hwdef->prom_addr); | |
7b833f5b | 448 | |
bda42033 | 449 | /* set up devices */ |
3ef96221 | 450 | ram_init(0, machine->ram_size); |
3475187d | 451 | |
1baffa46 | 452 | prom_init(hwdef->prom_addr, bios_name); |
3475187d | 453 | |
fff54d22 | 454 | ivec_irqs = qemu_allocate_irqs(sparc64_cpu_set_ivec_irq, cpu, IVEC_MAX); |
311f2b7a MCA |
455 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_busA, |
456 | &pci_busB, &pbm_irqs); | |
f2898771 | 457 | pci_vga_init(pci_bus); |
83469015 | 458 | |
311f2b7a | 459 | /* XXX Should be pci_busA */ |
e1030ca5 MCA |
460 | ebus = pci_create_simple(pci_bus, -1, "ebus"); |
461 | isa_bus = pci_ebus_init(ebus, pbm_irqs); | |
c190ea07 | 462 | |
e87231d4 BS |
463 | i = 0; |
464 | if (hwdef->console_serial_base) { | |
38bc50f7 | 465 | serial_mm_init(address_space_mem, hwdef->console_serial_base, 0, |
39186d8a | 466 | NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN); |
e87231d4 BS |
467 | i++; |
468 | } | |
83469015 | 469 | |
4496dc49 | 470 | serial_hds_isa_init(isa_bus, i, MAX_SERIAL_PORTS); |
07dc7880 | 471 | parallel_hds_isa_init(isa_bus, MAX_PARALLEL_PORTS); |
83469015 | 472 | |
8d932971 MCA |
473 | onboard_nic_idx = -1; |
474 | for (i = 0; i < nb_nics; i++) { | |
475 | nd = &nd_table[i]; | |
476 | ||
477 | if (onboard_nic_idx == -1 && | |
478 | (!nd->model || strcmp(nd->model, "sunhme") == 0)) { | |
479 | pci_dev = pci_create(pci_bus, -1, "sunhme"); | |
480 | dev = &pci_dev->qdev; | |
481 | qdev_set_nic_properties(dev, nd); | |
482 | qdev_init_nofail(dev); | |
483 | ||
484 | onboard_nic_idx = i; | |
485 | } else { | |
486 | pci_nic_init_nofail(nd, pci_bus, "ne2k_pci", NULL); | |
487 | } | |
488 | } | |
489 | onboard_nic_idx = MAX(onboard_nic_idx, 0); | |
83469015 | 490 | |
d8f94e1b | 491 | ide_drive_get(hd, ARRAY_SIZE(hd)); |
e4bcb14c | 492 | |
3b898dda BS |
493 | pci_cmd646_ide_init(pci_bus, hd, 1); |
494 | ||
48a18b3c | 495 | isa_create_simple(isa_bus, "i8042"); |
c3ae40e1 HP |
496 | |
497 | /* Floppy */ | |
e4bcb14c | 498 | for(i = 0; i < MAX_FD; i++) { |
fd8014e1 | 499 | fd[i] = drive_get(IF_FLOPPY, 0, i); |
e4bcb14c | 500 | } |
c3ae40e1 HP |
501 | dev = DEVICE(isa_create(isa_bus, TYPE_ISA_FDC)); |
502 | if (fd[0]) { | |
503 | qdev_prop_set_drive(dev, "driveA", blk_by_legacy_dinfo(fd[0]), | |
504 | &error_abort); | |
505 | } | |
506 | if (fd[1]) { | |
507 | qdev_prop_set_drive(dev, "driveB", blk_by_legacy_dinfo(fd[1]), | |
508 | &error_abort); | |
509 | } | |
510 | qdev_prop_set_uint32(dev, "dma", -1); | |
511 | qdev_init_nofail(dev); | |
636aa70a | 512 | |
f3b18f35 MCA |
513 | /* Map NVRAM into I/O (ebus) space */ |
514 | nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59); | |
515 | s = SYS_BUS_DEVICE(nvram); | |
07c84741 | 516 | memory_region_add_subregion(pci_address_space_io(ebus), 0x2000, |
f3b18f35 MCA |
517 | sysbus_mmio_get_region(s, 0)); |
518 | ||
636aa70a | 519 | initrd_size = 0; |
5f2bf0fe | 520 | initrd_addr = 0; |
3ef96221 MA |
521 | kernel_size = sun4u_load_kernel(machine->kernel_filename, |
522 | machine->initrd_filename, | |
5f2bf0fe BS |
523 | ram_size, &initrd_size, &initrd_addr, |
524 | &kernel_addr, &kernel_entry); | |
636aa70a | 525 | |
3ef96221 MA |
526 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size, |
527 | machine->boot_order, | |
5f2bf0fe | 528 | kernel_addr, kernel_size, |
3ef96221 | 529 | machine->kernel_cmdline, |
5f2bf0fe | 530 | initrd_addr, initrd_size, |
0d31cb99 BS |
531 | /* XXX: need an option to load a NVRAM image */ |
532 | 0, | |
533 | graphic_width, graphic_height, graphic_depth, | |
8d932971 | 534 | (uint8_t *)&nd_table[onboard_nic_idx].macaddr); |
83469015 | 535 | |
d6acc8a5 MCA |
536 | dev = qdev_create(NULL, TYPE_FW_CFG_IO); |
537 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
07c84741 | 538 | object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev), NULL); |
d6acc8a5 | 539 | qdev_init_nofail(dev); |
07c84741 | 540 | memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT, |
d6acc8a5 MCA |
541 | &FW_CFG_IO(dev)->comb_iomem); |
542 | ||
543 | fw_cfg = FW_CFG(dev); | |
5836d168 | 544 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
70db9222 | 545 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
905fdcb5 BS |
546 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
547 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
5f2bf0fe BS |
548 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry); |
549 | fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 550 | if (machine->kernel_cmdline) { |
9c9b0512 | 551 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 MA |
552 | strlen(machine->kernel_cmdline) + 1); |
553 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
513f789f | 554 | } else { |
9c9b0512 | 555 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f | 556 | } |
5f2bf0fe BS |
557 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr); |
558 | fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); | |
3ef96221 | 559 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
7589690c BS |
560 | |
561 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width); | |
562 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height); | |
563 | fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth); | |
564 | ||
513f789f | 565 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
3475187d FB |
566 | } |
567 | ||
905fdcb5 BS |
568 | enum { |
569 | sun4u_id = 0, | |
570 | sun4v_id = 64, | |
571 | }; | |
572 | ||
c7ba218d BS |
573 | static const struct hwdef hwdefs[] = { |
574 | /* Sun4u generic PC-like machine */ | |
575 | { | |
5910b047 | 576 | .default_cpu_model = "TI UltraSparc IIi", |
905fdcb5 | 577 | .machine_id = sun4u_id, |
e87231d4 BS |
578 | .prom_addr = 0x1fff0000000ULL, |
579 | .console_serial_base = 0, | |
c7ba218d BS |
580 | }, |
581 | /* Sun4v generic PC-like machine */ | |
582 | { | |
583 | .default_cpu_model = "Sun UltraSparc T1", | |
905fdcb5 | 584 | .machine_id = sun4v_id, |
e87231d4 BS |
585 | .prom_addr = 0x1fff0000000ULL, |
586 | .console_serial_base = 0, | |
587 | }, | |
c7ba218d BS |
588 | }; |
589 | ||
590 | /* Sun4u hardware initialisation */ | |
3ef96221 | 591 | static void sun4u_init(MachineState *machine) |
5f072e1f | 592 | { |
3ef96221 | 593 | sun4uv_init(get_system_memory(), machine, &hwdefs[0]); |
c7ba218d BS |
594 | } |
595 | ||
596 | /* Sun4v hardware initialisation */ | |
3ef96221 | 597 | static void sun4v_init(MachineState *machine) |
5f072e1f | 598 | { |
3ef96221 | 599 | sun4uv_init(get_system_memory(), machine, &hwdefs[1]); |
c7ba218d BS |
600 | } |
601 | ||
8a661aea | 602 | static void sun4u_class_init(ObjectClass *oc, void *data) |
e264d29d | 603 | { |
8a661aea AF |
604 | MachineClass *mc = MACHINE_CLASS(oc); |
605 | ||
e264d29d EH |
606 | mc->desc = "Sun4u platform"; |
607 | mc->init = sun4u_init; | |
2059839b | 608 | mc->block_default_type = IF_IDE; |
e264d29d EH |
609 | mc->max_cpus = 1; /* XXX for now */ |
610 | mc->is_default = 1; | |
611 | mc->default_boot_order = "c"; | |
612 | } | |
c7ba218d | 613 | |
8a661aea AF |
614 | static const TypeInfo sun4u_type = { |
615 | .name = MACHINE_TYPE_NAME("sun4u"), | |
616 | .parent = TYPE_MACHINE, | |
617 | .class_init = sun4u_class_init, | |
618 | }; | |
e87231d4 | 619 | |
8a661aea | 620 | static void sun4v_class_init(ObjectClass *oc, void *data) |
e264d29d | 621 | { |
8a661aea AF |
622 | MachineClass *mc = MACHINE_CLASS(oc); |
623 | ||
e264d29d EH |
624 | mc->desc = "Sun4v platform"; |
625 | mc->init = sun4v_init; | |
2059839b | 626 | mc->block_default_type = IF_IDE; |
e264d29d EH |
627 | mc->max_cpus = 1; /* XXX for now */ |
628 | mc->default_boot_order = "c"; | |
629 | } | |
630 | ||
8a661aea AF |
631 | static const TypeInfo sun4v_type = { |
632 | .name = MACHINE_TYPE_NAME("sun4v"), | |
633 | .parent = TYPE_MACHINE, | |
634 | .class_init = sun4v_class_init, | |
635 | }; | |
e264d29d | 636 | |
83f7d43a AF |
637 | static void sun4u_register_types(void) |
638 | { | |
639 | type_register_static(&ebus_info); | |
640 | type_register_static(&prom_info); | |
641 | type_register_static(&ram_info); | |
83f7d43a | 642 | |
8a661aea AF |
643 | type_register_static(&sun4u_type); |
644 | type_register_static(&sun4v_type); | |
8a661aea AF |
645 | } |
646 | ||
83f7d43a | 647 | type_init(sun4u_register_types) |