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i386/kvm: convert hyperv enlightenments properties from bools to bits
[mirror_qemu.git] / target / i386 / kvm.c
CommitLineData
05330448
AL		 1/*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
b6a0aa05 15#include "qemu/osdep.h"
da34e65c 16#include "qapi/error.h"
05330448 17#include <sys/ioctl.h>
25d2e361 18#include <sys/utsname.h>
05330448
AL		 19
20#include <linux/kvm.h>
1814eab6 21#include "standard-headers/asm-x86/kvm_para.h"
05330448 22
33c11879 23#include "cpu.h"
9c17d615 24#include "sysemu/sysemu.h"
b3946626 25#include "sysemu/hw_accel.h"
6410848b 26#include "sysemu/kvm_int.h"
1d31f66b 27#include "kvm_i386.h"
50efe82c 28#include "hyperv.h"
5e953812 29#include "hyperv-proto.h"
50efe82c 30
022c62cb 31#include "exec/gdbstub.h"
1de7afc9
PB		 32#include "qemu/host-utils.h"
33#include "qemu/config-file.h"
1c4a55db 34#include "qemu/error-report.h"
0d09e41a
PB		 35#include "hw/i386/pc.h"
36#include "hw/i386/apic.h"
e0723c45
PB		 37#include "hw/i386/apic_internal.h"
38#include "hw/i386/apic-msidef.h"
8b5ed7df 39#include "hw/i386/intel_iommu.h"
e1d4fb2d 40#include "hw/i386/x86-iommu.h"
50efe82c 41
a2cb15b0 42#include "hw/pci/pci.h"
15eafc2e 43#include "hw/pci/msi.h"
fd563564 44#include "hw/pci/msix.h"
795c40b8 45#include "migration/blocker.h"
4c663752 46#include "exec/memattrs.h"
8b5ed7df 47#include "trace.h"
05330448
AL		 48
49//#define DEBUG_KVM
50
51#ifdef DEBUG_KVM
8c0d577e 52#define DPRINTF(fmt, ...) \
05330448
AL		 53 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
54#else
8c0d577e 55#define DPRINTF(fmt, ...) \
05330448
AL		 56 do { } while (0)
57#endif
58
1a03675d
GC		 59#define MSR_KVM_WALL_CLOCK 0x11
60#define MSR_KVM_SYSTEM_TIME 0x12
61
d1138251
EH		 62/* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
63 * 255 kvm_msr_entry structs */
64#define MSR_BUF_SIZE 4096
d71b62a1 65
94a8d39a
JK		 66const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
67 KVM_CAP_INFO(SET_TSS_ADDR),
68 KVM_CAP_INFO(EXT_CPUID),
69 KVM_CAP_INFO(MP_STATE),
70 KVM_CAP_LAST_INFO
71};
25d2e361 72
c3a3a7d3
JK		 73static bool has_msr_star;
74static bool has_msr_hsave_pa;
c9b8f6b6 75static bool has_msr_tsc_aux;
f28558d3 76static bool has_msr_tsc_adjust;
aa82ba54 77static bool has_msr_tsc_deadline;
df67696e 78static bool has_msr_feature_control;
21e87c46 79static bool has_msr_misc_enable;
fc12d72e 80static bool has_msr_smbase;
79e9ebeb 81static bool has_msr_bndcfgs;
25d2e361 82static int lm_capable_kernel;
7bc3d711 83static bool has_msr_hv_hypercall;
f2a53c9e 84static bool has_msr_hv_crash;
744b8a94 85static bool has_msr_hv_reset;
8c145d7c 86static bool has_msr_hv_vpindex;
e9688fab 87static bool hv_vpindex_settable;
46eb8f98 88static bool has_msr_hv_runtime;
866eea9a 89static bool has_msr_hv_synic;
ff99aa64 90static bool has_msr_hv_stimer;
d72bc7f6 91static bool has_msr_hv_frequencies;
ba6a4fd9 92static bool has_msr_hv_reenlightenment;
18cd2c17 93static bool has_msr_xss;
a33a2cfe 94static bool has_msr_spec_ctrl;
cfeea0c0 95static bool has_msr_virt_ssbd;
e13713db 96static bool has_msr_smi_count;
aec5e9c3 97static bool has_msr_arch_capabs;
b827df58 98
0b368a10
JD		 99static uint32_t has_architectural_pmu_version;
100static uint32_t num_architectural_pmu_gp_counters;
101static uint32_t num_architectural_pmu_fixed_counters;
0d894367 102
28143b40
TH		 103static int has_xsave;
104static int has_xcrs;
105static int has_pit_state2;
106
87f8b626
AR		 107static bool has_msr_mcg_ext_ctl;
108
494e95e9 109static struct kvm_cpuid2 *cpuid_cache;
f57bceb6 110static struct kvm_msr_list *kvm_feature_msrs;
494e95e9 111
28143b40
TH		 112int kvm_has_pit_state2(void)
113{
114 return has_pit_state2;
115}
116
355023f2
PB		 117bool kvm_has_smm(void)
118{
119 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
120}
121
6053a86f
MT		 122bool kvm_has_adjust_clock_stable(void)
123{
124 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
125
126 return (ret == KVM_CLOCK_TSC_STABLE);
127}
128
1d31f66b
PM		 129bool kvm_allows_irq0_override(void)
130{
131 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
132}
133
fb506e70
RK		 134static bool kvm_x2apic_api_set_flags(uint64_t flags)
135{
136 KVMState *s = KVM_STATE(current_machine->accelerator);
137
138 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
139}
140
e391c009 141#define MEMORIZE(fn, _result) \
2a138ec3 142 ({ \
2a138ec3
RK		 143 static bool _memorized; \
144 \
145 if (_memorized) { \
146 return _result; \
147 } \
148 _memorized = true; \
149 _result = fn; \
150 })
151
e391c009
IM		 152static bool has_x2apic_api;
153
154bool kvm_has_x2apic_api(void)
155{
156 return has_x2apic_api;
157}
158
fb506e70
RK		 159bool kvm_enable_x2apic(void)
160{
2a138ec3
RK		 161 return MEMORIZE(
162 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
e391c009
IM		 163 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
164 has_x2apic_api);
fb506e70
RK		 165}
166
e9688fab
RK		 167bool kvm_hv_vpindex_settable(void)
168{
169 return hv_vpindex_settable;
170}
171
0fd7e098
LL		 172static int kvm_get_tsc(CPUState *cs)
173{
174 X86CPU *cpu = X86_CPU(cs);
175 CPUX86State *env = &cpu->env;
176 struct {
177 struct kvm_msrs info;
178 struct kvm_msr_entry entries[1];
179 } msr_data;
180 int ret;
181
182 if (env->tsc_valid) {
183 return 0;
184 }
185
186 msr_data.info.nmsrs = 1;
187 msr_data.entries[0].index = MSR_IA32_TSC;
188 env->tsc_valid = !runstate_is_running();
189
190 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
191 if (ret < 0) {
192 return ret;
193 }
194
48e1a45c 195 assert(ret == 1);
0fd7e098
LL		 196 env->tsc = msr_data.entries[0].data;
197 return 0;
198}
199
14e6fe12 200static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
0fd7e098 201{
0fd7e098
LL		 202 kvm_get_tsc(cpu);
203}
204
205void kvm_synchronize_all_tsc(void)
206{
207 CPUState *cpu;
208
209 if (kvm_enabled()) {
210 CPU_FOREACH(cpu) {
14e6fe12 211 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
0fd7e098
LL		 212 }
213 }
214}
215
b827df58
AK		 216static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
217{
218 struct kvm_cpuid2 *cpuid;
219 int r, size;
220
221 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
e42a92ae 222 cpuid = g_malloc0(size);
b827df58
AK		 223 cpuid->nent = max;
224 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
76ae317f
MM		 225 if (r == 0 && cpuid->nent >= max) {
226 r = -E2BIG;
227 }
b827df58
AK		 228 if (r < 0) {
229 if (r == -E2BIG) {
7267c094 230 g_free(cpuid);
b827df58
AK		 231 return NULL;
232 } else {
233 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
234 strerror(-r));
235 exit(1);
236 }
237 }
238 return cpuid;
239}
240
dd87f8a6
EH		 241/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
242 * for all entries.
243 */
244static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
245{
246 struct kvm_cpuid2 *cpuid;
247 int max = 1;
494e95e9
CP		 248
249 if (cpuid_cache != NULL) {
250 return cpuid_cache;
251 }
dd87f8a6
EH		 252 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
253 max *= 2;
254 }
494e95e9 255 cpuid_cache = cpuid;
dd87f8a6
EH		 256 return cpuid;
257}
258
a443bc34 259static const struct kvm_para_features {
0c31b744
GC		 260 int cap;
261 int feature;
262} para_features[] = {
263 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
264 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
265 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
0c31b744 266 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
0c31b744
GC		 267};
268
ba9bc59e 269static int get_para_features(KVMState *s)
0c31b744
GC		 270{
271 int i, features = 0;
272
8e03c100 273 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
ba9bc59e 274 if (kvm_check_extension(s, para_features[i].cap)) {
0c31b744
GC		 275 features |= (1 << para_features[i].feature);
276 }
277 }
278
279 return features;
280}
0c31b744 281
40e80ee4
EH		 282static bool host_tsx_blacklisted(void)
283{
284 int family, model, stepping;\
285 char vendor[CPUID_VENDOR_SZ + 1];
286
287 host_vendor_fms(vendor, &family, &model, &stepping);
288
289 /* Check if we are running on a Haswell host known to have broken TSX */
290 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
291 (family == 6) &&
292 ((model == 63 && stepping < 4) ||
293 model == 60 || model == 69 || model == 70);
294}
0c31b744 295
829ae2f9
EH		 296/* Returns the value for a specific register on the cpuid entry
297 */
298static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
299{
300 uint32_t ret = 0;
301 switch (reg) {
302 case R_EAX:
303 ret = entry->eax;
304 break;
305 case R_EBX:
306 ret = entry->ebx;
307 break;
308 case R_ECX:
309 ret = entry->ecx;
310 break;
311 case R_EDX:
312 ret = entry->edx;
313 break;
314 }
315 return ret;
316}
317
4fb73f1d
EH		 318/* Find matching entry for function/index on kvm_cpuid2 struct
319 */
320static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
321 uint32_t function,
322 uint32_t index)
323{
324 int i;
325 for (i = 0; i < cpuid->nent; ++i) {
326 if (cpuid->entries[i].function == function &&
327 cpuid->entries[i].index == index) {
328 return &cpuid->entries[i];
329 }
330 }
331 /* not found: */
332 return NULL;
333}
334
ba9bc59e 335uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
c958a8bd 336 uint32_t index, int reg)
b827df58
AK		 337{
338 struct kvm_cpuid2 *cpuid;
b827df58
AK		 339 uint32_t ret = 0;
340 uint32_t cpuid_1_edx;
8c723b79 341 bool found = false;
b827df58 342
dd87f8a6 343 cpuid = get_supported_cpuid(s);
b827df58 344
4fb73f1d
EH		 345 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
346 if (entry) {
347 found = true;
348 ret = cpuid_entry_get_reg(entry, reg);
b827df58
AK		 349 }
350
7b46e5ce
EH		 351 /* Fixups for the data returned by KVM, below */
352
c2acb022
EH		 353 if (function == 1 && reg == R_EDX) {
354 /* KVM before 2.6.30 misreports the following features */
355 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
84bd945c
EH		 356 } else if (function == 1 && reg == R_ECX) {
357 /* We can set the hypervisor flag, even if KVM does not return it on
358 * GET_SUPPORTED_CPUID
359 */
360 ret |= CPUID_EXT_HYPERVISOR;
ac67ee26
EH		 361 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
362 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
363 * and the irqchip is in the kernel.
364 */
365 if (kvm_irqchip_in_kernel() &&
366 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
367 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
368 }
41e5e76d
EH		 369
370 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
371 * without the in-kernel irqchip
372 */
373 if (!kvm_irqchip_in_kernel()) {
374 ret &= ~CPUID_EXT_X2APIC;
b827df58 375 }
2266d443
MT		 376
377 if (enable_cpu_pm) {
378 int disable_exits = kvm_check_extension(s,
379 KVM_CAP_X86_DISABLE_EXITS);
380
381 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
382 ret |= CPUID_EXT_MONITOR;
383 }
384 }
28b8e4d0
JK		 385 } else if (function == 6 && reg == R_EAX) {
386 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
40e80ee4
EH		 387 } else if (function == 7 && index == 0 && reg == R_EBX) {
388 if (host_tsx_blacklisted()) {
389 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
390 }
485b1d25
EH		 391 } else if (function == 7 && index == 0 && reg == R_EDX) {
392 /*
393 * Linux v4.17-v4.20 incorrectly return ARCH_CAPABILITIES on SVM hosts.
394 * We can detect the bug by checking if MSR_IA32_ARCH_CAPABILITIES is
395 * returned by KVM_GET_MSR_INDEX_LIST.
396 */
397 if (!has_msr_arch_capabs) {
398 ret &= ~CPUID_7_0_EDX_ARCH_CAPABILITIES;
399 }
f98bbd83
BM		 400 } else if (function == 0x80000001 && reg == R_ECX) {
401 /*
402 * It's safe to enable TOPOEXT even if it's not returned by
403 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
404 * us to keep CPU models including TOPOEXT runnable on older kernels.
405 */
406 ret |= CPUID_EXT3_TOPOEXT;
c2acb022
EH		 407 } else if (function == 0x80000001 && reg == R_EDX) {
408 /* On Intel, kvm returns cpuid according to the Intel spec,
409 * so add missing bits according to the AMD spec:
410 */
411 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
412 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
64877477
EH		 413 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
414 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
415 * be enabled without the in-kernel irqchip
416 */
417 if (!kvm_irqchip_in_kernel()) {
418 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
419 }
be777326 420 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
2af1acad 421 ret |= 1U << KVM_HINTS_REALTIME;
be777326 422 found = 1;
b827df58
AK		 423 }
424
0c31b744 425 /* fallback for older kernels */
8c723b79 426 if ((function == KVM_CPUID_FEATURES) && !found) {
ba9bc59e 427 ret = get_para_features(s);
b9bec74b 428 }
0c31b744
GC		 429
430 return ret;
bb0300dc 431}
bb0300dc 432
f57bceb6
RH		 433uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
434{
435 struct {
436 struct kvm_msrs info;
437 struct kvm_msr_entry entries[1];
438 } msr_data;
439 uint32_t ret;
440
441 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
442 return 0;
443 }
444
445 /* Check if requested MSR is supported feature MSR */
446 int i;
447 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
448 if (kvm_feature_msrs->indices[i] == index) {
449 break;
450 }
451 if (i == kvm_feature_msrs->nmsrs) {
452 return 0; /* if the feature MSR is not supported, simply return 0 */
453 }
454
455 msr_data.info.nmsrs = 1;
456 msr_data.entries[0].index = index;
457
458 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
459 if (ret != 1) {
460 error_report("KVM get MSR (index=0x%x) feature failed, %s",
461 index, strerror(-ret));
462 exit(1);
463 }
464
465 return msr_data.entries[0].data;
466}
467
468
3c85e74f
HY		 469typedef struct HWPoisonPage {
470 ram_addr_t ram_addr;
471 QLIST_ENTRY(HWPoisonPage) list;
472} HWPoisonPage;
473
474static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
475 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
476
477static void kvm_unpoison_all(void *param)
478{
479 HWPoisonPage *page, *next_page;
480
481 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
482 QLIST_REMOVE(page, list);
483 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
7267c094 484 g_free(page);
3c85e74f
HY		 485 }
486}
487
3c85e74f
HY		 488static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
489{
490 HWPoisonPage *page;
491
492 QLIST_FOREACH(page, &hwpoison_page_list, list) {
493 if (page->ram_addr == ram_addr) {
494 return;
495 }
496 }
ab3ad07f 497 page = g_new(HWPoisonPage, 1);
3c85e74f
HY		 498 page->ram_addr = ram_addr;
499 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
500}
501
e7701825
MT		 502static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
503 int *max_banks)
504{
505 int r;
506
14a09518 507 r = kvm_check_extension(s, KVM_CAP_MCE);
e7701825
MT		 508 if (r > 0) {
509 *max_banks = r;
510 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
511 }
512 return -ENOSYS;
513}
514
bee615d4 515static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
e7701825 516{
87f8b626 517 CPUState *cs = CPU(cpu);
bee615d4 518 CPUX86State *env = &cpu->env;
c34d440a
JK		 519 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
520 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
521 uint64_t mcg_status = MCG_STATUS_MCIP;
87f8b626 522 int flags = 0;
e7701825 523
c34d440a
JK		 524 if (code == BUS_MCEERR_AR) {
525 status |= MCI_STATUS_AR | 0x134;
526 mcg_status |= MCG_STATUS_EIPV;
527 } else {
528 status |= 0xc0;
529 mcg_status |= MCG_STATUS_RIPV;
419fb20a 530 }
87f8b626
AR		 531
532 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
533 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
534 * guest kernel back into env->mcg_ext_ctl.
535 */
536 cpu_synchronize_state(cs);
537 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
538 mcg_status |= MCG_STATUS_LMCE;
539 flags = 0;
540 }
541
8c5cf3b6 542 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
87f8b626 543 (MCM_ADDR_PHYS << 6) | 0xc, flags);
419fb20a 544}
419fb20a
JK		 545
546static void hardware_memory_error(void)
547{
548 fprintf(stderr, "Hardware memory error!\n");
549 exit(1);
550}
551
2ae41db2 552void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
419fb20a 553{
20d695a9
AF		 554 X86CPU *cpu = X86_CPU(c);
555 CPUX86State *env = &cpu->env;
419fb20a 556 ram_addr_t ram_addr;
a8170e5e 557 hwaddr paddr;
419fb20a 558
4d39892c
PB		 559 /* If we get an action required MCE, it has been injected by KVM
560 * while the VM was running. An action optional MCE instead should
561 * be coming from the main thread, which qemu_init_sigbus identifies
562 * as the "early kill" thread.
563 */
a16fc07e 564 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
20e0ff59 565
20e0ff59 566 if ((env->mcg_cap & MCG_SER_P) && addr) {
07bdaa41 567 ram_addr = qemu_ram_addr_from_host(addr);
20e0ff59
PB		 568 if (ram_addr != RAM_ADDR_INVALID &&
569 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
570 kvm_hwpoison_page_add(ram_addr);
571 kvm_mce_inject(cpu, paddr, code);
2ae41db2 572 return;
419fb20a 573 }
20e0ff59
PB		 574
575 fprintf(stderr, "Hardware memory error for memory used by "
576 "QEMU itself instead of guest system!\n");
419fb20a 577 }
20e0ff59
PB		 578
579 if (code == BUS_MCEERR_AR) {
580 hardware_memory_error();
581 }
582
583 /* Hope we are lucky for AO MCE */
419fb20a
JK		 584}
585
1bc22652 586static int kvm_inject_mce_oldstyle(X86CPU *cpu)
ab443475 587{
1bc22652
AF		 588 CPUX86State *env = &cpu->env;
589
ab443475
JK		 590 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
591 unsigned int bank, bank_num = env->mcg_cap & 0xff;
592 struct kvm_x86_mce mce;
593
594 env->exception_injected = -1;
595
596 /*
597 * There must be at least one bank in use if an MCE is pending.
598 * Find it and use its values for the event injection.
599 */
600 for (bank = 0; bank < bank_num; bank++) {
601 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
602 break;
603 }
604 }
605 assert(bank < bank_num);
606
607 mce.bank = bank;
608 mce.status = env->mce_banks[bank * 4 + 1];
609 mce.mcg_status = env->mcg_status;
610 mce.addr = env->mce_banks[bank * 4 + 2];
611 mce.misc = env->mce_banks[bank * 4 + 3];
612
1bc22652 613 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
ab443475 614 }
ab443475
JK		 615 return 0;
616}
617
1dfb4dd9 618static void cpu_update_state(void *opaque, int running, RunState state)
b8cc45d6 619{
317ac620 620 CPUX86State *env = opaque;
b8cc45d6
GC		 621
622 if (running) {
623 env->tsc_valid = false;
624 }
625}
626
83b17af5 627unsigned long kvm_arch_vcpu_id(CPUState *cs)
b164e48e 628{
83b17af5 629 X86CPU *cpu = X86_CPU(cs);
7e72a45c 630 return cpu->apic_id;
b164e48e
EH		 631}
632
92067bf4
IM		 633#ifndef KVM_CPUID_SIGNATURE_NEXT
634#define KVM_CPUID_SIGNATURE_NEXT 0x40000100
635#endif
636
92067bf4
IM		 637static bool hyperv_enabled(X86CPU *cpu)
638{
7bc3d711
PB		 639 CPUState *cs = CPU(cpu);
640 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
2d384d7c
VK		 641 ((cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY) ||
642 cpu->hyperv_features);
92067bf4
IM		 643}
644
5031283d
HZ		 645static int kvm_arch_set_tsc_khz(CPUState *cs)
646{
647 X86CPU *cpu = X86_CPU(cs);
648 CPUX86State *env = &cpu->env;
649 int r;
650
651 if (!env->tsc_khz) {
652 return 0;
653 }
654
655 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
656 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
657 -ENOTSUP;
658 if (r < 0) {
659 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
660 * TSC frequency doesn't match the one we want.
661 */
662 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
663 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
664 -ENOTSUP;
665 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
3dc6f869
AF		 666 warn_report("TSC frequency mismatch between "
667 "VM (%" PRId64 " kHz) and host (%d kHz), "
668 "and TSC scaling unavailable",
669 env->tsc_khz, cur_freq);
5031283d
HZ		 670 return r;
671 }
672 }
673
674 return 0;
675}
676
4bb95b82
LP		 677static bool tsc_is_stable_and_known(CPUX86State *env)
678{
679 if (!env->tsc_khz) {
680 return false;
681 }
682 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
683 || env->user_tsc_khz;
684}
685
c35bd19a
EY		 686static int hyperv_handle_properties(CPUState *cs)
687{
688 X86CPU *cpu = X86_CPU(cs);
689 CPUX86State *env = &cpu->env;
690
2d384d7c 691 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RELAXED)) {
5e953812 692 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
c35bd19a 693 }
2d384d7c 694 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
5e953812
RK		 695 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
696 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
c35bd19a 697 }
2d384d7c 698 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
1221f150
RK		 699 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
700 fprintf(stderr, "Hyper-V clocksources "
701 "(requested by 'hv-time' cpu flag) "
702 "are not supported by kernel\n");
703 return -ENOSYS;
704 }
5e953812
RK		 705 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
706 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
707 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
9445597b 708 }
2d384d7c 709 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_FREQUENCIES)) {
9445597b
RK		 710 if (!has_msr_hv_frequencies) {
711 fprintf(stderr, "Hyper-V frequency MSRs "
712 "(requested by 'hv-frequencies' cpu flag) "
713 "are not supported by kernel\n");
714 return -ENOSYS;
d72bc7f6 715 }
9445597b
RK		 716 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
717 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
c35bd19a 718 }
2d384d7c 719 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_CRASH)) {
1221f150
RK		 720 if (!has_msr_hv_crash) {
721 fprintf(stderr, "Hyper-V crash MSRs "
722 "(requested by 'hv-crash' cpu flag) "
723 "are not supported by kernel\n");
724 return -ENOSYS;
725 }
5e953812 726 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
c35bd19a 727 }
2d384d7c 728 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 729 if (!has_msr_hv_reenlightenment) {
730 fprintf(stderr,
731 "Hyper-V Reenlightenment MSRs "
732 "(requested by 'hv-reenlightenment' cpu flag) "
733 "are not supported by kernel\n");
734 return -ENOSYS;
735 }
736 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
737 }
5e953812 738 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
2d384d7c 739 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RESET)) {
1221f150
RK		 740 if (!has_msr_hv_reset) {
741 fprintf(stderr, "Hyper-V reset MSR "
742 "(requested by 'hv-reset' cpu flag) "
743 "is not supported by kernel\n");
744 return -ENOSYS;
745 }
5e953812 746 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
c35bd19a 747 }
2d384d7c 748 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
1221f150
RK		 749 if (!has_msr_hv_vpindex) {
750 fprintf(stderr, "Hyper-V VP_INDEX MSR "
751 "(requested by 'hv-vpindex' cpu flag) "
752 "is not supported by kernel\n");
753 return -ENOSYS;
754 }
5e953812 755 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
c35bd19a 756 }
2d384d7c 757 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RUNTIME)) {
1221f150
RK		 758 if (!has_msr_hv_runtime) {
759 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
760 "(requested by 'hv-runtime' cpu flag) "
761 "is not supported by kernel\n");
762 return -ENOSYS;
763 }
5e953812 764 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
c35bd19a 765 }
2d384d7c 766 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 767 unsigned int cap = KVM_CAP_HYPERV_SYNIC;
768 if (!cpu->hyperv_synic_kvm_only) {
2d384d7c 769 if (!hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)) {
9b4cf107
RK		 770 fprintf(stderr, "Hyper-V SynIC "
771 "(requested by 'hv-synic' cpu flag) "
772 "requires Hyper-V VP_INDEX ('hv-vpindex')\n");
773 return -ENOSYS;
774 }
775 cap = KVM_CAP_HYPERV_SYNIC2;
776 }
777
778 if (!has_msr_hv_synic || !kvm_check_extension(cs->kvm_state, cap)) {
729ce7e1
RK		 779 fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
780 "is not supported by kernel\n");
c35bd19a
EY		 781 return -ENOSYS;
782 }
783
5e953812 784 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
c35bd19a 785 }
2d384d7c 786 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_STIMER)) {
c35bd19a
EY		 787 if (!has_msr_hv_stimer) {
788 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
789 return -ENOSYS;
790 }
5e953812 791 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
c35bd19a 792 }
2d384d7c 793 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_RELAXED)) {
a2b107db
VK		 794 env->features[FEAT_HV_RECOMM_EAX] |= HV_RELAXED_TIMING_RECOMMENDED;
795 }
2d384d7c 796 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
a2b107db
VK		 797 env->features[FEAT_HV_RECOMM_EAX] |= HV_APIC_ACCESS_RECOMMENDED;
798 }
2d384d7c 799 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TLBFLUSH)) {
a2b107db
VK		 800 if (kvm_check_extension(cs->kvm_state,
801 KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
802 fprintf(stderr, "Hyper-V TLB flush support "
803 "(requested by 'hv-tlbflush' cpu flag) "
804 " is not supported by kernel\n");
805 return -ENOSYS;
806 }
807 env->features[FEAT_HV_RECOMM_EAX] |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
808 env->features[FEAT_HV_RECOMM_EAX] |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
809 }
2d384d7c 810 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_IPI)) {
a2b107db
VK		 811 if (kvm_check_extension(cs->kvm_state,
812 KVM_CAP_HYPERV_SEND_IPI) <= 0) {
813 fprintf(stderr, "Hyper-V IPI send support "
814 "(requested by 'hv-ipi' cpu flag) "
815 " is not supported by kernel\n");
816 return -ENOSYS;
817 }
818 env->features[FEAT_HV_RECOMM_EAX] |= HV_CLUSTER_IPI_RECOMMENDED;
819 env->features[FEAT_HV_RECOMM_EAX] |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
820 }
2d384d7c 821 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
a2b107db
VK		 822 uint16_t evmcs_version;
823
824 if (kvm_vcpu_enable_cap(cs, KVM_CAP_HYPERV_ENLIGHTENED_VMCS, 0,
825 (uintptr_t)&evmcs_version)) {
826 fprintf(stderr, "Hyper-V Enlightened VMCS "
827 "(requested by 'hv-evmcs' cpu flag) "
828 "is not supported by kernel\n");
829 return -ENOSYS;
830 }
831 env->features[FEAT_HV_RECOMM_EAX] |= HV_ENLIGHTENED_VMCS_RECOMMENDED;
832 env->features[FEAT_HV_NESTED_EAX] = evmcs_version;
833 }
834
c35bd19a
EY		 835 return 0;
836}
837
e9688fab
RK		 838static int hyperv_init_vcpu(X86CPU *cpu)
839{
729ce7e1
RK		 840 CPUState *cs = CPU(cpu);
841 int ret;
842
2d384d7c 843 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !hv_vpindex_settable) {
e9688fab
RK		 844 /*
845 * the kernel doesn't support setting vp_index; assert that its value
846 * is in sync
847 */
e9688fab
RK		 848 struct {
849 struct kvm_msrs info;
850 struct kvm_msr_entry entries[1];
851 } msr_data = {
852 .info.nmsrs = 1,
853 .entries[0].index = HV_X64_MSR_VP_INDEX,
854 };
855
729ce7e1 856 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
e9688fab
RK		 857 if (ret < 0) {
858 return ret;
859 }
860 assert(ret == 1);
861
701189e3 862 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
e9688fab
RK		 863 error_report("kernel's vp_index != QEMU's vp_index");
864 return -ENXIO;
865 }
866 }
867
2d384d7c 868 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
9b4cf107
RK		 869 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
870 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
871 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
729ce7e1
RK		 872 if (ret < 0) {
873 error_report("failed to turn on HyperV SynIC in KVM: %s",
874 strerror(-ret));
875 return ret;
876 }
606c34bf 877
9b4cf107
RK		 878 if (!cpu->hyperv_synic_kvm_only) {
879 ret = hyperv_x86_synic_add(cpu);
880 if (ret < 0) {
881 error_report("failed to create HyperV SynIC: %s",
882 strerror(-ret));
883 return ret;
884 }
606c34bf 885 }
729ce7e1
RK		 886 }
887
e9688fab
RK		 888 return 0;
889}
890
68bfd0ad 891static Error *invtsc_mig_blocker;
d98f2607 892static Error *vmx_mig_blocker;
68bfd0ad 893
f8bb0565 894#define KVM_MAX_CPUID_ENTRIES 100
0893d460 895
20d695a9 896int kvm_arch_init_vcpu(CPUState *cs)
05330448
AL		 897{
898 struct {
486bd5a2 899 struct kvm_cpuid2 cpuid;
f8bb0565 900 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
9115bb12
PM		 901 } cpuid_data;
902 /*
903 * The kernel defines these structs with padding fields so there
904 * should be no extra padding in our cpuid_data struct.
905 */
906 QEMU_BUILD_BUG_ON(sizeof(cpuid_data) !=
907 sizeof(struct kvm_cpuid2) +
908 sizeof(struct kvm_cpuid_entry2) * KVM_MAX_CPUID_ENTRIES);
909
20d695a9
AF		 910 X86CPU *cpu = X86_CPU(cs);
911 CPUX86State *env = &cpu->env;
486bd5a2 912 uint32_t limit, i, j, cpuid_i;
a33609ca 913 uint32_t unused;
bb0300dc 914 struct kvm_cpuid_entry2 *c;
bb0300dc 915 uint32_t signature[3];
234cc647 916 int kvm_base = KVM_CPUID_SIGNATURE;
e7429073 917 int r;
fe44dc91 918 Error *local_err = NULL;
05330448 919
ef4cbe14
SW		 920 memset(&cpuid_data, 0, sizeof(cpuid_data));
921
05330448
AL		 922 cpuid_i = 0;
923
ddb98b5a
LP		 924 r = kvm_arch_set_tsc_khz(cs);
925 if (r < 0) {
926 goto fail;
927 }
928
929 /* vcpu's TSC frequency is either specified by user, or following
930 * the value used by KVM if the former is not present. In the
931 * latter case, we query it from KVM and record in env->tsc_khz,
932 * so that vcpu's TSC frequency can be migrated later via this field.
933 */
934 if (!env->tsc_khz) {
935 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
936 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
937 -ENOTSUP;
938 if (r > 0) {
939 env->tsc_khz = r;
940 }
941 }
942
bb0300dc 943 /* Paravirtualization CPUIDs */
234cc647
PB		 944 if (hyperv_enabled(cpu)) {
945 c = &cpuid_data.entries[cpuid_i++];
5e953812 946 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
1c4a55db
AW		 947 if (!cpu->hyperv_vendor_id) {
948 memcpy(signature, "Microsoft Hv", 12);
949 } else {
950 size_t len = strlen(cpu->hyperv_vendor_id);
951
952 if (len > 12) {
953 error_report("hv-vendor-id truncated to 12 characters");
954 len = 12;
955 }
956 memset(signature, 0, 12);
957 memcpy(signature, cpu->hyperv_vendor_id, len);
958 }
2d384d7c 959 c->eax = hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ?
e204ac61 960 HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS;
234cc647
PB		 961 c->ebx = signature[0];
962 c->ecx = signature[1];
963 c->edx = signature[2];
0c31b744 964
234cc647 965 c = &cpuid_data.entries[cpuid_i++];
5e953812 966 c->function = HV_CPUID_INTERFACE;
eab70139
VR		 967 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
968 c->eax = signature[0];
234cc647
PB		 969 c->ebx = 0;
970 c->ecx = 0;
971 c->edx = 0;
eab70139
VR		 972
973 c = &cpuid_data.entries[cpuid_i++];
5e953812 974 c->function = HV_CPUID_VERSION;
eab70139
VR		 975 c->eax = 0x00001bbc;
976 c->ebx = 0x00060001;
977
978 c = &cpuid_data.entries[cpuid_i++];
5e953812 979 c->function = HV_CPUID_FEATURES;
c35bd19a
EY		 980 r = hyperv_handle_properties(cs);
981 if (r) {
982 return r;
46eb8f98 983 }
c35bd19a
EY		 984 c->eax = env->features[FEAT_HYPERV_EAX];
985 c->ebx = env->features[FEAT_HYPERV_EBX];
986 c->edx = env->features[FEAT_HYPERV_EDX];
866eea9a 987
eab70139 988 c = &cpuid_data.entries[cpuid_i++];
5e953812 989 c->function = HV_CPUID_ENLIGHTMENT_INFO;
a2b107db
VK		 990
991 c->eax = env->features[FEAT_HV_RECOMM_EAX];
92067bf4 992 c->ebx = cpu->hyperv_spinlock_attempts;
eab70139
VR		 993
994 c = &cpuid_data.entries[cpuid_i++];
5e953812 995 c->function = HV_CPUID_IMPLEMENT_LIMITS;
6c69dfb6
GA		 996
997 c->eax = cpu->hv_max_vps;
eab70139
VR		 998 c->ebx = 0x40;
999
234cc647 1000 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
7bc3d711 1001 has_msr_hv_hypercall = true;
e204ac61 1002
2d384d7c 1003 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) {
e204ac61
VK		 1004 __u32 function;
1005
1006 /* Create zeroed 0x40000006..0x40000009 leaves */
1007 for (function = HV_CPUID_IMPLEMENT_LIMITS + 1;
1008 function < HV_CPUID_NESTED_FEATURES; function++) {
1009 c = &cpuid_data.entries[cpuid_i++];
1010 c->function = function;
1011 }
1012
1013 c = &cpuid_data.entries[cpuid_i++];
1014 c->function = HV_CPUID_NESTED_FEATURES;
a2b107db 1015 c->eax = env->features[FEAT_HV_NESTED_EAX];
e204ac61 1016 }
eab70139
VR		 1017 }
1018
f522d2ac
AW		 1019 if (cpu->expose_kvm) {
1020 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
1021 c = &cpuid_data.entries[cpuid_i++];
1022 c->function = KVM_CPUID_SIGNATURE | kvm_base;
79b6f2f6 1023 c->eax = KVM_CPUID_FEATURES | kvm_base;
f522d2ac
AW		 1024 c->ebx = signature[0];
1025 c->ecx = signature[1];
1026 c->edx = signature[2];
234cc647 1027
f522d2ac
AW		 1028 c = &cpuid_data.entries[cpuid_i++];
1029 c->function = KVM_CPUID_FEATURES | kvm_base;
1030 c->eax = env->features[FEAT_KVM];
be777326 1031 c->edx = env->features[FEAT_KVM_HINTS];
f522d2ac 1032 }
917367aa 1033
a33609ca 1034 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1035
1036 for (i = 0; i <= limit; i++) {
f8bb0565
IM		 1037 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1038 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1039 abort();
1040 }
bb0300dc 1041 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1042
1043 switch (i) {
a36b1029
AL		 1044 case 2: {
1045 /* Keep reading function 2 till all the input is received */
1046 int times;
1047
a36b1029 1048 c->function = i;
a33609ca
AL		 1049 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1050 KVM_CPUID_FLAG_STATE_READ_NEXT;
1051 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1052 times = c->eax & 0xff;
a36b1029
AL		 1053
1054 for (j = 1; j < times; ++j) {
f8bb0565
IM		 1055 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1056 fprintf(stderr, "cpuid_data is full, no space for "
1057 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1058 abort();
1059 }
a33609ca 1060 c = &cpuid_data.entries[cpuid_i++];
a36b1029 1061 c->function = i;
a33609ca
AL		 1062 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1063 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
a36b1029
AL		 1064 }
1065 break;
1066 }
486bd5a2
AL		 1067 case 4:
1068 case 0xb:
1069 case 0xd:
1070 for (j = 0; ; j++) {
31e8c696
AP		 1071 if (i == 0xd && j == 64) {
1072 break;
1073 }
486bd5a2
AL		 1074 c->function = i;
1075 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1076 c->index = j;
a33609ca 1077 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2 1078
b9bec74b 1079 if (i == 4 && c->eax == 0) {
486bd5a2 1080 break;
b9bec74b
JK		 1081 }
1082 if (i == 0xb && !(c->ecx & 0xff00)) {
486bd5a2 1083 break;
b9bec74b
JK		 1084 }
1085 if (i == 0xd && c->eax == 0) {
31e8c696 1086 continue;
b9bec74b 1087 }
f8bb0565
IM		 1088 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1089 fprintf(stderr, "cpuid_data is full, no space for "
1090 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1091 abort();
1092 }
a33609ca 1093 c = &cpuid_data.entries[cpuid_i++];
486bd5a2
AL		 1094 }
1095 break;
e37a5c7f
CP		 1096 case 0x14: {
1097 uint32_t times;
1098
1099 c->function = i;
1100 c->index = 0;
1101 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1102 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1103 times = c->eax;
1104
1105 for (j = 1; j <= times; ++j) {
1106 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1107 fprintf(stderr, "cpuid_data is full, no space for "
1108 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1109 abort();
1110 }
1111 c = &cpuid_data.entries[cpuid_i++];
1112 c->function = i;
1113 c->index = j;
1114 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1115 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1116 }
1117 break;
1118 }
486bd5a2 1119 default:
486bd5a2 1120 c->function = i;
a33609ca
AL		 1121 c->flags = 0;
1122 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
486bd5a2
AL		 1123 break;
1124 }
05330448 1125 }
0d894367
PB		 1126
1127 if (limit >= 0x0a) {
0b368a10 1128 uint32_t eax, edx;
0d894367 1129
0b368a10
JD		 1130 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1131
1132 has_architectural_pmu_version = eax & 0xff;
1133 if (has_architectural_pmu_version > 0) {
1134 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
0d894367
PB		 1135
1136 /* Shouldn't be more than 32, since that's the number of bits
1137 * available in EBX to tell us _which_ counters are available.
1138 * Play it safe.
1139 */
0b368a10
JD		 1140 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1141 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1142 }
1143
1144 if (has_architectural_pmu_version > 1) {
1145 num_architectural_pmu_fixed_counters = edx & 0x1f;
1146
1147 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1148 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1149 }
0d894367
PB		 1150 }
1151 }
1152 }
1153
a33609ca 1154 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
05330448
AL		 1155
1156 for (i = 0x80000000; i <= limit; i++) {
f8bb0565
IM		 1157 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1158 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1159 abort();
1160 }
bb0300dc 1161 c = &cpuid_data.entries[cpuid_i++];
05330448 1162
8f4202fb
BM		 1163 switch (i) {
1164 case 0x8000001d:
1165 /* Query for all AMD cache information leaves */
1166 for (j = 0; ; j++) {
1167 c->function = i;
1168 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1169 c->index = j;
1170 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1171
1172 if (c->eax == 0) {
1173 break;
1174 }
1175 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1176 fprintf(stderr, "cpuid_data is full, no space for "
1177 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1178 abort();
1179 }
1180 c = &cpuid_data.entries[cpuid_i++];
1181 }
1182 break;
1183 default:
1184 c->function = i;
1185 c->flags = 0;
1186 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1187 break;
1188 }
05330448
AL		 1189 }
1190
b3baa152
BW		 1191 /* Call Centaur's CPUID instructions they are supported. */
1192 if (env->cpuid_xlevel2 > 0) {
b3baa152
BW		 1193 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1194
1195 for (i = 0xC0000000; i <= limit; i++) {
f8bb0565
IM		 1196 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1197 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1198 abort();
1199 }
b3baa152
BW		 1200 c = &cpuid_data.entries[cpuid_i++];
1201
1202 c->function = i;
1203 c->flags = 0;
1204 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1205 }
1206 }
1207
05330448
AL		 1208 cpuid_data.cpuid.nent = cpuid_i;
1209
e7701825 1210 if (((env->cpuid_version >> 8)&0xF) >= 6
0514ef2f 1211 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
fc7a504c 1212 (CPUID_MCE | CPUID_MCA)
a60f24b5 1213 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
5120901a 1214 uint64_t mcg_cap, unsupported_caps;
e7701825 1215 int banks;
32a42024 1216 int ret;
e7701825 1217
a60f24b5 1218 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
75d49497
JK		 1219 if (ret < 0) {
1220 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1221 return ret;
e7701825 1222 }
75d49497 1223
2590f15b 1224 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
49b69cbf 1225 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
2590f15b 1226 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
49b69cbf 1227 return -ENOTSUP;
75d49497 1228 }
49b69cbf 1229
5120901a
EH		 1230 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1231 if (unsupported_caps) {
87f8b626
AR		 1232 if (unsupported_caps & MCG_LMCE_P) {
1233 error_report("kvm: LMCE not supported");
1234 return -ENOTSUP;
1235 }
3dc6f869
AF		 1236 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1237 unsupported_caps);
5120901a
EH		 1238 }
1239
2590f15b
EH		 1240 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1241 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
75d49497
JK		 1242 if (ret < 0) {
1243 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1244 return ret;
1245 }
e7701825 1246 }
e7701825 1247
b8cc45d6
GC		 1248 qemu_add_vm_change_state_handler(cpu_update_state, env);
1249
df67696e
LJ		 1250 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1251 if (c) {
1252 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1253 !!(c->ecx & CPUID_EXT_SMX);
1254 }
1255
d98f2607
PB		 1256 if ((env->features[FEAT_1_ECX] & CPUID_EXT_VMX) && !vmx_mig_blocker) {
1257 error_setg(&vmx_mig_blocker,
1258 "Nested VMX virtualization does not support live migration yet");
1259 r = migrate_add_blocker(vmx_mig_blocker, &local_err);
1260 if (local_err) {
1261 error_report_err(local_err);
1262 error_free(vmx_mig_blocker);
1263 return r;
1264 }
1265 }
1266
87f8b626
AR		 1267 if (env->mcg_cap & MCG_LMCE_P) {
1268 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1269 }
1270
d99569d9
EH		 1271 if (!env->user_tsc_khz) {
1272 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1273 invtsc_mig_blocker == NULL) {
d99569d9
EH		 1274 error_setg(&invtsc_mig_blocker,
1275 "State blocked by non-migratable CPU device"
1276 " (invtsc flag)");
fe44dc91
AA		 1277 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1278 if (local_err) {
1279 error_report_err(local_err);
1280 error_free(invtsc_mig_blocker);
0c2ed83f 1281 return r;
fe44dc91 1282 }
d99569d9 1283 }
68bfd0ad
MT		 1284 }
1285
9954a158
PDJ		 1286 if (cpu->vmware_cpuid_freq
1287 /* Guests depend on 0x40000000 to detect this feature, so only expose
1288 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1289 && cpu->expose_kvm
1290 && kvm_base == KVM_CPUID_SIGNATURE
1291 /* TSC clock must be stable and known for this feature. */
4bb95b82 1292 && tsc_is_stable_and_known(env)) {
9954a158
PDJ		 1293
1294 c = &cpuid_data.entries[cpuid_i++];
1295 c->function = KVM_CPUID_SIGNATURE | 0x10;
1296 c->eax = env->tsc_khz;
1297 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1298 * APIC_BUS_CYCLE_NS */
1299 c->ebx = 1000000;
1300 c->ecx = c->edx = 0;
1301
1302 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1303 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1304 }
1305
1306 cpuid_data.cpuid.nent = cpuid_i;
1307
1308 cpuid_data.cpuid.padding = 0;
1309 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1310 if (r) {
1311 goto fail;
1312 }
1313
28143b40 1314 if (has_xsave) {
5b8063c4 1315 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
fabacc0f 1316 }
d71b62a1 1317 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
fabacc0f 1318
273c515c
PB		 1319 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1320 has_msr_tsc_aux = false;
1321 }
d1ae67f6 1322
e9688fab
RK		 1323 r = hyperv_init_vcpu(cpu);
1324 if (r) {
1325 goto fail;
1326 }
1327
e7429073 1328 return 0;
fe44dc91
AA		 1329
1330 fail:
1331 migrate_del_blocker(invtsc_mig_blocker);
1332 return r;
05330448
AL		 1333}
1334
50a2c6e5 1335void kvm_arch_reset_vcpu(X86CPU *cpu)
caa5af0f 1336{
20d695a9 1337 CPUX86State *env = &cpu->env;
dd673288 1338
1a5e9d2f 1339 env->xcr0 = 1;
ddced198 1340 if (kvm_irqchip_in_kernel()) {
dd673288 1341 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
ddced198
MT		 1342 KVM_MP_STATE_UNINITIALIZED;
1343 } else {
1344 env->mp_state = KVM_MP_STATE_RUNNABLE;
1345 }
689141dd 1346
2d384d7c 1347 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
689141dd
RK		 1348 int i;
1349 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1350 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1351 }
606c34bf
RK		 1352
1353 hyperv_x86_synic_reset(cpu);
689141dd 1354 }
caa5af0f
JK		 1355}
1356
e0723c45
PB		 1357void kvm_arch_do_init_vcpu(X86CPU *cpu)
1358{
1359 CPUX86State *env = &cpu->env;
1360
1361 /* APs get directly into wait-for-SIPI state. */
1362 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1363 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1364 }
1365}
1366
f57bceb6
RH		 1367static int kvm_get_supported_feature_msrs(KVMState *s)
1368{
1369 int ret = 0;
1370
1371 if (kvm_feature_msrs != NULL) {
1372 return 0;
1373 }
1374
1375 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1376 return 0;
1377 }
1378
1379 struct kvm_msr_list msr_list;
1380
1381 msr_list.nmsrs = 0;
1382 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1383 if (ret < 0 && ret != -E2BIG) {
1384 error_report("Fetch KVM feature MSR list failed: %s",
1385 strerror(-ret));
1386 return ret;
1387 }
1388
1389 assert(msr_list.nmsrs > 0);
1390 kvm_feature_msrs = (struct kvm_msr_list *) \
1391 g_malloc0(sizeof(msr_list) +
1392 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1393
1394 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1395 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1396
1397 if (ret < 0) {
1398 error_report("Fetch KVM feature MSR list failed: %s",
1399 strerror(-ret));
1400 g_free(kvm_feature_msrs);
1401 kvm_feature_msrs = NULL;
1402 return ret;
1403 }
1404
1405 return 0;
1406}
1407
c3a3a7d3 1408static int kvm_get_supported_msrs(KVMState *s)
05330448 1409{
75b10c43 1410 static int kvm_supported_msrs;
c3a3a7d3 1411 int ret = 0;
05330448
AL		 1412
1413 /* first time */
75b10c43 1414 if (kvm_supported_msrs == 0) {
05330448
AL		 1415 struct kvm_msr_list msr_list, *kvm_msr_list;
1416
75b10c43 1417 kvm_supported_msrs = -1;
05330448
AL		 1418
1419 /* Obtain MSR list from KVM. These are the MSRs that we must
1420 * save/restore */
4c9f7372 1421 msr_list.nmsrs = 0;
c3a3a7d3 1422 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
6fb6d245 1423 if (ret < 0 && ret != -E2BIG) {
c3a3a7d3 1424 return ret;
6fb6d245 1425 }
d9db889f
JK		 1426 /* Old kernel modules had a bug and could write beyond the provided
1427 memory. Allocate at least a safe amount of 1K. */
7267c094 1428 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
d9db889f
JK		 1429 msr_list.nmsrs *
1430 sizeof(msr_list.indices[0])));
05330448 1431
55308450 1432 kvm_msr_list->nmsrs = msr_list.nmsrs;
c3a3a7d3 1433 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
05330448
AL		 1434 if (ret >= 0) {
1435 int i;
1436
1437 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1d268dec
LP		 1438 switch (kvm_msr_list->indices[i]) {
1439 case MSR_STAR:
c3a3a7d3 1440 has_msr_star = true;
1d268dec
LP		 1441 break;
1442 case MSR_VM_HSAVE_PA:
c3a3a7d3 1443 has_msr_hsave_pa = true;
1d268dec
LP		 1444 break;
1445 case MSR_TSC_AUX:
c9b8f6b6 1446 has_msr_tsc_aux = true;
1d268dec
LP		 1447 break;
1448 case MSR_TSC_ADJUST:
f28558d3 1449 has_msr_tsc_adjust = true;
1d268dec
LP		 1450 break;
1451 case MSR_IA32_TSCDEADLINE:
aa82ba54 1452 has_msr_tsc_deadline = true;
1d268dec
LP		 1453 break;
1454 case MSR_IA32_SMBASE:
fc12d72e 1455 has_msr_smbase = true;
1d268dec 1456 break;
e13713db
LA		 1457 case MSR_SMI_COUNT:
1458 has_msr_smi_count = true;
1459 break;
1d268dec 1460 case MSR_IA32_MISC_ENABLE:
21e87c46 1461 has_msr_misc_enable = true;
1d268dec
LP		 1462 break;
1463 case MSR_IA32_BNDCFGS:
79e9ebeb 1464 has_msr_bndcfgs = true;
1d268dec
LP		 1465 break;
1466 case MSR_IA32_XSS:
18cd2c17 1467 has_msr_xss = true;
3c254ab8 1468 break;
1d268dec 1469 case HV_X64_MSR_CRASH_CTL:
f2a53c9e 1470 has_msr_hv_crash = true;
1d268dec
LP		 1471 break;
1472 case HV_X64_MSR_RESET:
744b8a94 1473 has_msr_hv_reset = true;
1d268dec
LP		 1474 break;
1475 case HV_X64_MSR_VP_INDEX:
8c145d7c 1476 has_msr_hv_vpindex = true;
1d268dec
LP		 1477 break;
1478 case HV_X64_MSR_VP_RUNTIME:
46eb8f98 1479 has_msr_hv_runtime = true;
1d268dec
LP		 1480 break;
1481 case HV_X64_MSR_SCONTROL:
866eea9a 1482 has_msr_hv_synic = true;
1d268dec
LP		 1483 break;
1484 case HV_X64_MSR_STIMER0_CONFIG:
ff99aa64 1485 has_msr_hv_stimer = true;
1d268dec 1486 break;
d72bc7f6
LP		 1487 case HV_X64_MSR_TSC_FREQUENCY:
1488 has_msr_hv_frequencies = true;
1489 break;
ba6a4fd9
VK		 1490 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1491 has_msr_hv_reenlightenment = true;
1492 break;
a33a2cfe
PB		 1493 case MSR_IA32_SPEC_CTRL:
1494 has_msr_spec_ctrl = true;
1495 break;
cfeea0c0
KRW		 1496 case MSR_VIRT_SSBD:
1497 has_msr_virt_ssbd = true;
1498 break;
aec5e9c3
BD		 1499 case MSR_IA32_ARCH_CAPABILITIES:
1500 has_msr_arch_capabs = true;
1501 break;
ff99aa64 1502 }
05330448
AL		 1503 }
1504 }
1505
7267c094 1506 g_free(kvm_msr_list);
05330448
AL		 1507 }
1508
c3a3a7d3 1509 return ret;
05330448
AL		 1510}
1511
6410848b
PB		 1512static Notifier smram_machine_done;
1513static KVMMemoryListener smram_listener;
1514static AddressSpace smram_address_space;
1515static MemoryRegion smram_as_root;
1516static MemoryRegion smram_as_mem;
1517
1518static void register_smram_listener(Notifier *n, void *unused)
1519{
1520 MemoryRegion *smram =
1521 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1522
1523 /* Outer container... */
1524 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1525 memory_region_set_enabled(&smram_as_root, true);
1526
1527 /* ... with two regions inside: normal system memory with low
1528 * priority, and...
1529 */
1530 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1531 get_system_memory(), 0, ~0ull);
1532 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1533 memory_region_set_enabled(&smram_as_mem, true);
1534
1535 if (smram) {
1536 /* ... SMRAM with higher priority */
1537 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1538 memory_region_set_enabled(smram, true);
1539 }
1540
1541 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1542 kvm_memory_listener_register(kvm_state, &smram_listener,
1543 &smram_address_space, 1);
1544}
1545
b16565b3 1546int kvm_arch_init(MachineState *ms, KVMState *s)
20420430 1547{
11076198 1548 uint64_t identity_base = 0xfffbc000;
39d6960a 1549 uint64_t shadow_mem;
20420430 1550 int ret;
25d2e361 1551 struct utsname utsname;
20420430 1552
28143b40 1553 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
28143b40 1554 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
28143b40 1555 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
28143b40 1556
e9688fab
RK		 1557 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1558
c3a3a7d3 1559 ret = kvm_get_supported_msrs(s);
20420430 1560 if (ret < 0) {
20420430
SY		 1561 return ret;
1562 }
25d2e361 1563
f57bceb6
RH		 1564 kvm_get_supported_feature_msrs(s);
1565
25d2e361
MT		 1566 uname(&utsname);
1567 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1568
4c5b10b7 1569 /*
11076198
JK		 1570 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1571 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1572 * Since these must be part of guest physical memory, we need to allocate
1573 * them, both by setting their start addresses in the kernel and by
1574 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1575 *
1576 * Older KVM versions may not support setting the identity map base. In
1577 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1578 * size.
4c5b10b7 1579 */
11076198
JK		 1580 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1581 /* Allows up to 16M BIOSes. */
1582 identity_base = 0xfeffc000;
1583
1584 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1585 if (ret < 0) {
1586 return ret;
1587 }
4c5b10b7 1588 }
e56ff191 1589
11076198
JK		 1590 /* Set TSS base one page after EPT identity map. */
1591 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
20420430
SY		 1592 if (ret < 0) {
1593 return ret;
1594 }
1595
11076198
JK		 1596 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1597 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
20420430 1598 if (ret < 0) {
11076198 1599 fprintf(stderr, "e820_add_entry() table is full\n");
20420430
SY		 1600 return ret;
1601 }
3c85e74f 1602 qemu_register_reset(kvm_unpoison_all, NULL);
20420430 1603
4689b77b 1604 shadow_mem = machine_kvm_shadow_mem(ms);
36ad0e94
MA		 1605 if (shadow_mem != -1) {
1606 shadow_mem /= 4096;
1607 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1608 if (ret < 0) {
1609 return ret;
39d6960a
JK		 1610 }
1611 }
6410848b 1612
d870cfde
GA		 1613 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1614 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1615 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
6410848b
PB		 1616 smram_machine_done.notify = register_smram_listener;
1617 qemu_add_machine_init_done_notifier(&smram_machine_done);
1618 }
6f131f13
MT		 1619
1620 if (enable_cpu_pm) {
1621 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1622 int ret;
1623
1624/* Work around for kernel header with a typo. TODO: fix header and drop. */
1625#if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1626#define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1627#endif
1628 if (disable_exits) {
1629 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1630 KVM_X86_DISABLE_EXITS_HLT |
1631 KVM_X86_DISABLE_EXITS_PAUSE);
1632 }
1633
1634 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1635 disable_exits);
1636 if (ret < 0) {
1637 error_report("kvm: guest stopping CPU not supported: %s",
1638 strerror(-ret));
1639 }
1640 }
1641
11076198 1642 return 0;
05330448 1643}
b9bec74b 1644
05330448
AL		 1645static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1646{
1647 lhs->selector = rhs->selector;
1648 lhs->base = rhs->base;
1649 lhs->limit = rhs->limit;
1650 lhs->type = 3;
1651 lhs->present = 1;
1652 lhs->dpl = 3;
1653 lhs->db = 0;
1654 lhs->s = 1;
1655 lhs->l = 0;
1656 lhs->g = 0;
1657 lhs->avl = 0;
1658 lhs->unusable = 0;
1659}
1660
1661static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1662{
1663 unsigned flags = rhs->flags;
1664 lhs->selector = rhs->selector;
1665 lhs->base = rhs->base;
1666 lhs->limit = rhs->limit;
1667 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1668 lhs->present = (flags & DESC_P_MASK) != 0;
acaa7550 1669 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
05330448
AL		 1670 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1671 lhs->s = (flags & DESC_S_MASK) != 0;
1672 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1673 lhs->g = (flags & DESC_G_MASK) != 0;
1674 lhs->avl = (flags & DESC_AVL_MASK) != 0;
4cae9c97 1675 lhs->unusable = !lhs->present;
7e680753 1676 lhs->padding = 0;
05330448
AL		 1677}
1678
1679static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1680{
1681 lhs->selector = rhs->selector;
1682 lhs->base = rhs->base;
1683 lhs->limit = rhs->limit;
d45fc087
RP		 1684 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1685 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1686 (rhs->dpl << DESC_DPL_SHIFT) |
1687 (rhs->db << DESC_B_SHIFT) |
1688 (rhs->s * DESC_S_MASK) |
1689 (rhs->l << DESC_L_SHIFT) |
1690 (rhs->g * DESC_G_MASK) |
1691 (rhs->avl * DESC_AVL_MASK);
05330448
AL		 1692}
1693
1694static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1695{
b9bec74b 1696 if (set) {
05330448 1697 *kvm_reg = *qemu_reg;
b9bec74b 1698 } else {
05330448 1699 *qemu_reg = *kvm_reg;
b9bec74b 1700 }
05330448
AL		 1701}
1702
1bc22652 1703static int kvm_getput_regs(X86CPU *cpu, int set)
05330448 1704{
1bc22652 1705 CPUX86State *env = &cpu->env;
05330448
AL		 1706 struct kvm_regs regs;
1707 int ret = 0;
1708
1709 if (!set) {
1bc22652 1710 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
b9bec74b 1711 if (ret < 0) {
05330448 1712 return ret;
b9bec74b 1713 }
05330448
AL		 1714 }
1715
1716 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1717 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1718 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1719 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1720 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1721 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1722 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1723 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1724#ifdef TARGET_X86_64
1725 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1726 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1727 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1728 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1729 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1730 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1731 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1732 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1733#endif
1734
1735 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1736 kvm_getput_reg(&regs.rip, &env->eip, set);
1737
b9bec74b 1738 if (set) {
1bc22652 1739 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
b9bec74b 1740 }
05330448
AL		 1741
1742 return ret;
1743}
1744
1bc22652 1745static int kvm_put_fpu(X86CPU *cpu)
05330448 1746{
1bc22652 1747 CPUX86State *env = &cpu->env;
05330448
AL		 1748 struct kvm_fpu fpu;
1749 int i;
1750
1751 memset(&fpu, 0, sizeof fpu);
1752 fpu.fsw = env->fpus & ~(7 << 11);
1753 fpu.fsw |= (env->fpstt & 7) << 11;
1754 fpu.fcw = env->fpuc;
42cc8fa6
JK		 1755 fpu.last_opcode = env->fpop;
1756 fpu.last_ip = env->fpip;
1757 fpu.last_dp = env->fpdp;
b9bec74b
JK		 1758 for (i = 0; i < 8; ++i) {
1759 fpu.ftwx |= (!env->fptags[i]) << i;
1760 }
05330448 1761 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
bee81887 1762 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 1763 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1764 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
bee81887 1765 }
05330448
AL		 1766 fpu.mxcsr = env->mxcsr;
1767
1bc22652 1768 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
05330448
AL		 1769}
1770
6b42494b
JK		 1771#define XSAVE_FCW_FSW 0
1772#define XSAVE_FTW_FOP 1
f1665b21
SY		 1773#define XSAVE_CWD_RIP 2
1774#define XSAVE_CWD_RDP 4
1775#define XSAVE_MXCSR 6
1776#define XSAVE_ST_SPACE 8
1777#define XSAVE_XMM_SPACE 40
1778#define XSAVE_XSTATE_BV 128
1779#define XSAVE_YMMH_SPACE 144
79e9ebeb
LJ		 1780#define XSAVE_BNDREGS 240
1781#define XSAVE_BNDCSR 256
9aecd6f8
CP		 1782#define XSAVE_OPMASK 272
1783#define XSAVE_ZMM_Hi256 288
1784#define XSAVE_Hi16_ZMM 416
f74eefe0 1785#define XSAVE_PKRU 672
f1665b21 1786
b503717d 1787#define XSAVE_BYTE_OFFSET(word_offset) \
f18793b0 1788 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
b503717d
EH		 1789
1790#define ASSERT_OFFSET(word_offset, field) \
1791 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1792 offsetof(X86XSaveArea, field))
1793
1794ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1795ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1796ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1797ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1798ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1799ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1800ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1801ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1802ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1803ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1804ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1805ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1806ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1807ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1808ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1809
1bc22652 1810static int kvm_put_xsave(X86CPU *cpu)
f1665b21 1811{
1bc22652 1812 CPUX86State *env = &cpu->env;
5b8063c4 1813 X86XSaveArea *xsave = env->xsave_buf;
f1665b21 1814
28143b40 1815 if (!has_xsave) {
1bc22652 1816 return kvm_put_fpu(cpu);
b9bec74b 1817 }
86a57621 1818 x86_cpu_xsave_all_areas(cpu, xsave);
f1665b21 1819
9be38598 1820 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
f1665b21
SY		 1821}
1822
1bc22652 1823static int kvm_put_xcrs(X86CPU *cpu)
f1665b21 1824{
1bc22652 1825 CPUX86State *env = &cpu->env;
bdfc8480 1826 struct kvm_xcrs xcrs = {};
f1665b21 1827
28143b40 1828 if (!has_xcrs) {
f1665b21 1829 return 0;
b9bec74b 1830 }
f1665b21
SY		 1831
1832 xcrs.nr_xcrs = 1;
1833 xcrs.flags = 0;
1834 xcrs.xcrs[0].xcr = 0;
1835 xcrs.xcrs[0].value = env->xcr0;
1bc22652 1836 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
f1665b21
SY		 1837}
1838
1bc22652 1839static int kvm_put_sregs(X86CPU *cpu)
05330448 1840{
1bc22652 1841 CPUX86State *env = &cpu->env;
05330448
AL		 1842 struct kvm_sregs sregs;
1843
0e607a80
JK		 1844 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1845 if (env->interrupt_injected >= 0) {
1846 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1847 (uint64_t)1 << (env->interrupt_injected % 64);
1848 }
05330448
AL		 1849
1850 if ((env->eflags & VM_MASK)) {
b9bec74b
JK		 1851 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1852 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1853 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1854 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1855 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1856 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
05330448 1857 } else {
b9bec74b
JK		 1858 set_seg(&sregs.cs, &env->segs[R_CS]);
1859 set_seg(&sregs.ds, &env->segs[R_DS]);
1860 set_seg(&sregs.es, &env->segs[R_ES]);
1861 set_seg(&sregs.fs, &env->segs[R_FS]);
1862 set_seg(&sregs.gs, &env->segs[R_GS]);
1863 set_seg(&sregs.ss, &env->segs[R_SS]);
05330448
AL		 1864 }
1865
1866 set_seg(&sregs.tr, &env->tr);
1867 set_seg(&sregs.ldt, &env->ldt);
1868
1869 sregs.idt.limit = env->idt.limit;
1870 sregs.idt.base = env->idt.base;
7e680753 1871 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
05330448
AL		 1872 sregs.gdt.limit = env->gdt.limit;
1873 sregs.gdt.base = env->gdt.base;
7e680753 1874 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
05330448
AL		 1875
1876 sregs.cr0 = env->cr[0];
1877 sregs.cr2 = env->cr[2];
1878 sregs.cr3 = env->cr[3];
1879 sregs.cr4 = env->cr[4];
1880
02e51483
CF		 1881 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1882 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
05330448
AL		 1883
1884 sregs.efer = env->efer;
1885
1bc22652 1886 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
05330448
AL		 1887}
1888
d71b62a1
EH		 1889static void kvm_msr_buf_reset(X86CPU *cpu)
1890{
1891 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1892}
1893
9c600a84
EH		 1894static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1895{
1896 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1897 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1898 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1899
1900 assert((void *)(entry + 1) <= limit);
1901
1abc2cae
EH		 1902 entry->index = index;
1903 entry->reserved = 0;
1904 entry->data = value;
9c600a84
EH		 1905 msrs->nmsrs++;
1906}
1907
73e1b8f2
PB		 1908static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1909{
1910 kvm_msr_buf_reset(cpu);
1911 kvm_msr_entry_add(cpu, index, value);
1912
1913 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1914}
1915
f8d9ccf8
DDAG		 1916void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1917{
1918 int ret;
1919
1920 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1921 assert(ret == 1);
1922}
1923
7477cd38
MT		 1924static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1925{
1926 CPUX86State *env = &cpu->env;
48e1a45c 1927 int ret;
7477cd38
MT		 1928
1929 if (!has_msr_tsc_deadline) {
1930 return 0;
1931 }
1932
73e1b8f2 1933 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
48e1a45c
PB		 1934 if (ret < 0) {
1935 return ret;
1936 }
1937
1938 assert(ret == 1);
1939 return 0;
7477cd38
MT		 1940}
1941
6bdf863d
JK		 1942/*
1943 * Provide a separate write service for the feature control MSR in order to
1944 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1945 * before writing any other state because forcibly leaving nested mode
1946 * invalidates the VCPU state.
1947 */
1948static int kvm_put_msr_feature_control(X86CPU *cpu)
1949{
48e1a45c
PB		 1950 int ret;
1951
1952 if (!has_msr_feature_control) {
1953 return 0;
1954 }
6bdf863d 1955
73e1b8f2
PB		 1956 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1957 cpu->env.msr_ia32_feature_control);
48e1a45c
PB		 1958 if (ret < 0) {
1959 return ret;
1960 }
1961
1962 assert(ret == 1);
1963 return 0;
6bdf863d
JK		 1964}
1965
1bc22652 1966static int kvm_put_msrs(X86CPU *cpu, int level)
05330448 1967{
1bc22652 1968 CPUX86State *env = &cpu->env;
9c600a84 1969 int i;
48e1a45c 1970 int ret;
05330448 1971
d71b62a1
EH		 1972 kvm_msr_buf_reset(cpu);
1973
9c600a84
EH		 1974 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1975 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1976 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1977 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
c3a3a7d3 1978 if (has_msr_star) {
9c600a84 1979 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
b9bec74b 1980 }
c3a3a7d3 1981 if (has_msr_hsave_pa) {
9c600a84 1982 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
b9bec74b 1983 }
c9b8f6b6 1984 if (has_msr_tsc_aux) {
9c600a84 1985 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
c9b8f6b6 1986 }
f28558d3 1987 if (has_msr_tsc_adjust) {
9c600a84 1988 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
f28558d3 1989 }
21e87c46 1990 if (has_msr_misc_enable) {
9c600a84 1991 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
21e87c46
AK		 1992 env->msr_ia32_misc_enable);
1993 }
fc12d72e 1994 if (has_msr_smbase) {
9c600a84 1995 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
fc12d72e 1996 }
e13713db
LA		 1997 if (has_msr_smi_count) {
1998 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1999 }
439d19f2 2000 if (has_msr_bndcfgs) {
9c600a84 2001 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
439d19f2 2002 }
18cd2c17 2003 if (has_msr_xss) {
9c600a84 2004 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
18cd2c17 2005 }
a33a2cfe
PB		 2006 if (has_msr_spec_ctrl) {
2007 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
2008 }
cfeea0c0
KRW		 2009 if (has_msr_virt_ssbd) {
2010 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
2011 }
2012
05330448 2013#ifdef TARGET_X86_64
25d2e361 2014 if (lm_capable_kernel) {
9c600a84
EH		 2015 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
2016 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
2017 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
2018 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
25d2e361 2019 }
05330448 2020#endif
a33a2cfe 2021
d86f9636 2022 /* If host supports feature MSR, write down. */
aec5e9c3
BD		 2023 if (has_msr_arch_capabs) {
2024 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
2025 env->features[FEAT_ARCH_CAPABILITIES]);
d86f9636
RH		 2026 }
2027
ff5c186b 2028 /*
0d894367
PB		 2029 * The following MSRs have side effects on the guest or are too heavy
2030 * for normal writeback. Limit them to reset or full state updates.
ff5c186b
JK		 2031 */
2032 if (level >= KVM_PUT_RESET_STATE) {
9c600a84
EH		 2033 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
2034 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
2035 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
55c911a5 2036 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2037 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
c5999bfc 2038 }
55c911a5 2039 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2040 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
bc9a839d 2041 }
55c911a5 2042 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2043 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
917367aa 2044 }
0b368a10
JD		 2045 if (has_architectural_pmu_version > 0) {
2046 if (has_architectural_pmu_version > 1) {
2047 /* Stop the counter. */
2048 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2049 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2050 }
0d894367
PB		 2051
2052 /* Set the counter values. */
0b368a10 2053 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2054 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
0d894367
PB		 2055 env->msr_fixed_counters[i]);
2056 }
0b368a10 2057 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84 2058 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
0d894367 2059 env->msr_gp_counters[i]);
9c600a84 2060 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
0d894367
PB		 2061 env->msr_gp_evtsel[i]);
2062 }
0b368a10
JD		 2063 if (has_architectural_pmu_version > 1) {
2064 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2065 env->msr_global_status);
2066 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2067 env->msr_global_ovf_ctrl);
2068
2069 /* Now start the PMU. */
2070 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2071 env->msr_fixed_ctr_ctrl);
2072 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2073 env->msr_global_ctrl);
2074 }
0d894367 2075 }
da1cc323
EY		 2076 /*
2077 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2078 * only sync them to KVM on the first cpu
2079 */
2080 if (current_cpu == first_cpu) {
2081 if (has_msr_hv_hypercall) {
2082 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2083 env->msr_hv_guest_os_id);
2084 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2085 env->msr_hv_hypercall);
2086 }
2d384d7c 2087 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
da1cc323
EY		 2088 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2089 env->msr_hv_tsc);
2090 }
2d384d7c 2091 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2092 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2093 env->msr_hv_reenlightenment_control);
2094 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2095 env->msr_hv_tsc_emulation_control);
2096 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2097 env->msr_hv_tsc_emulation_status);
2098 }
eab70139 2099 }
2d384d7c 2100 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2101 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
5ef68987 2102 env->msr_hv_vapic);
eab70139 2103 }
f2a53c9e
AS		 2104 if (has_msr_hv_crash) {
2105 int j;
2106
5e953812 2107 for (j = 0; j < HV_CRASH_PARAMS; j++)
9c600a84 2108 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
f2a53c9e
AS		 2109 env->msr_hv_crash_params[j]);
2110
5e953812 2111 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
f2a53c9e 2112 }
46eb8f98 2113 if (has_msr_hv_runtime) {
9c600a84 2114 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
46eb8f98 2115 }
2d384d7c
VK		 2116 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX)
2117 && hv_vpindex_settable) {
701189e3
RK		 2118 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2119 hyperv_vp_index(CPU(cpu)));
e9688fab 2120 }
2d384d7c 2121 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2122 int j;
2123
09df29b6
RK		 2124 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2125
9c600a84 2126 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
866eea9a 2127 env->msr_hv_synic_control);
9c600a84 2128 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
866eea9a 2129 env->msr_hv_synic_evt_page);
9c600a84 2130 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
866eea9a
AS		 2131 env->msr_hv_synic_msg_page);
2132
2133 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
9c600a84 2134 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
866eea9a
AS		 2135 env->msr_hv_synic_sint[j]);
2136 }
2137 }
ff99aa64
AS		 2138 if (has_msr_hv_stimer) {
2139 int j;
2140
2141 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
9c600a84 2142 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
ff99aa64
AS		 2143 env->msr_hv_stimer_config[j]);
2144 }
2145
2146 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
9c600a84 2147 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
ff99aa64
AS		 2148 env->msr_hv_stimer_count[j]);
2149 }
2150 }
1eabfce6 2151 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
112dad69
DDAG		 2152 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2153
9c600a84
EH		 2154 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2155 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2156 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2157 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2158 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2159 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2160 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2161 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2162 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2163 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2164 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2165 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
d1ae67f6 2166 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
112dad69
DDAG		 2167 /* The CPU GPs if we write to a bit above the physical limit of
2168 * the host CPU (and KVM emulates that)
2169 */
2170 uint64_t mask = env->mtrr_var[i].mask;
2171 mask &= phys_mask;
2172
9c600a84
EH		 2173 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2174 env->mtrr_var[i].base);
112dad69 2175 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
d1ae67f6
AW		 2176 }
2177 }
b77146e9
CP		 2178 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2179 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2180 0x14, 1, R_EAX) & 0x7;
2181
2182 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2183 env->msr_rtit_ctrl);
2184 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2185 env->msr_rtit_status);
2186 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2187 env->msr_rtit_output_base);
2188 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2189 env->msr_rtit_output_mask);
2190 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2191 env->msr_rtit_cr3_match);
2192 for (i = 0; i < addr_num; i++) {
2193 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2194 env->msr_rtit_addrs[i]);
2195 }
2196 }
6bdf863d
JK		 2197
2198 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2199 * kvm_put_msr_feature_control. */
ea643051 2200 }
57780495 2201 if (env->mcg_cap) {
d8da8574 2202 int i;
b9bec74b 2203
9c600a84
EH		 2204 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2205 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
87f8b626
AR		 2206 if (has_msr_mcg_ext_ctl) {
2207 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2208 }
c34d440a 2209 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2210 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
57780495
MT		 2211 }
2212 }
1a03675d 2213
d71b62a1 2214 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
48e1a45c
PB		 2215 if (ret < 0) {
2216 return ret;
2217 }
05330448 2218
c70b11d1
EH		 2219 if (ret < cpu->kvm_msr_buf->nmsrs) {
2220 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2221 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2222 (uint32_t)e->index, (uint64_t)e->data);
2223 }
2224
9c600a84 2225 assert(ret == cpu->kvm_msr_buf->nmsrs);
48e1a45c 2226 return 0;
05330448
AL		 2227}
2228
2229
1bc22652 2230static int kvm_get_fpu(X86CPU *cpu)
05330448 2231{
1bc22652 2232 CPUX86State *env = &cpu->env;
05330448
AL		 2233 struct kvm_fpu fpu;
2234 int i, ret;
2235
1bc22652 2236 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
b9bec74b 2237 if (ret < 0) {
05330448 2238 return ret;
b9bec74b 2239 }
05330448
AL		 2240
2241 env->fpstt = (fpu.fsw >> 11) & 7;
2242 env->fpus = fpu.fsw;
2243 env->fpuc = fpu.fcw;
42cc8fa6
JK		 2244 env->fpop = fpu.last_opcode;
2245 env->fpip = fpu.last_ip;
2246 env->fpdp = fpu.last_dp;
b9bec74b
JK		 2247 for (i = 0; i < 8; ++i) {
2248 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2249 }
05330448 2250 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
bee81887 2251 for (i = 0; i < CPU_NB_REGS; i++) {
19cbd87c
EH		 2252 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2253 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
bee81887 2254 }
05330448
AL		 2255 env->mxcsr = fpu.mxcsr;
2256
2257 return 0;
2258}
2259
1bc22652 2260static int kvm_get_xsave(X86CPU *cpu)
f1665b21 2261{
1bc22652 2262 CPUX86State *env = &cpu->env;
5b8063c4 2263 X86XSaveArea *xsave = env->xsave_buf;
86a57621 2264 int ret;
f1665b21 2265
28143b40 2266 if (!has_xsave) {
1bc22652 2267 return kvm_get_fpu(cpu);
b9bec74b 2268 }
f1665b21 2269
1bc22652 2270 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
0f53994f 2271 if (ret < 0) {
f1665b21 2272 return ret;
0f53994f 2273 }
86a57621 2274 x86_cpu_xrstor_all_areas(cpu, xsave);
f1665b21 2275
f1665b21 2276 return 0;
f1665b21
SY		 2277}
2278
1bc22652 2279static int kvm_get_xcrs(X86CPU *cpu)
f1665b21 2280{
1bc22652 2281 CPUX86State *env = &cpu->env;
f1665b21
SY		 2282 int i, ret;
2283 struct kvm_xcrs xcrs;
2284
28143b40 2285 if (!has_xcrs) {
f1665b21 2286 return 0;
b9bec74b 2287 }
f1665b21 2288
1bc22652 2289 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
b9bec74b 2290 if (ret < 0) {
f1665b21 2291 return ret;
b9bec74b 2292 }
f1665b21 2293
b9bec74b 2294 for (i = 0; i < xcrs.nr_xcrs; i++) {
f1665b21 2295 /* Only support xcr0 now */
0fd53fec
PB		 2296 if (xcrs.xcrs[i].xcr == 0) {
2297 env->xcr0 = xcrs.xcrs[i].value;
f1665b21
SY		 2298 break;
2299 }
b9bec74b 2300 }
f1665b21 2301 return 0;
f1665b21
SY		 2302}
2303
1bc22652 2304static int kvm_get_sregs(X86CPU *cpu)
05330448 2305{
1bc22652 2306 CPUX86State *env = &cpu->env;
05330448 2307 struct kvm_sregs sregs;
0e607a80 2308 int bit, i, ret;
05330448 2309
1bc22652 2310 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
b9bec74b 2311 if (ret < 0) {
05330448 2312 return ret;
b9bec74b 2313 }
05330448 2314
0e607a80
JK		 2315 /* There can only be one pending IRQ set in the bitmap at a time, so try
2316 to find it and save its number instead (-1 for none). */
2317 env->interrupt_injected = -1;
2318 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2319 if (sregs.interrupt_bitmap[i]) {
2320 bit = ctz64(sregs.interrupt_bitmap[i]);
2321 env->interrupt_injected = i * 64 + bit;
2322 break;
2323 }
2324 }
05330448
AL		 2325
2326 get_seg(&env->segs[R_CS], &sregs.cs);
2327 get_seg(&env->segs[R_DS], &sregs.ds);
2328 get_seg(&env->segs[R_ES], &sregs.es);
2329 get_seg(&env->segs[R_FS], &sregs.fs);
2330 get_seg(&env->segs[R_GS], &sregs.gs);
2331 get_seg(&env->segs[R_SS], &sregs.ss);
2332
2333 get_seg(&env->tr, &sregs.tr);
2334 get_seg(&env->ldt, &sregs.ldt);
2335
2336 env->idt.limit = sregs.idt.limit;
2337 env->idt.base = sregs.idt.base;
2338 env->gdt.limit = sregs.gdt.limit;
2339 env->gdt.base = sregs.gdt.base;
2340
2341 env->cr[0] = sregs.cr0;
2342 env->cr[2] = sregs.cr2;
2343 env->cr[3] = sregs.cr3;
2344 env->cr[4] = sregs.cr4;
2345
05330448 2346 env->efer = sregs.efer;
cce47516
JK		 2347
2348 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
35b1b927 2349 x86_update_hflags(env);
05330448
AL		 2350
2351 return 0;
2352}
2353
1bc22652 2354static int kvm_get_msrs(X86CPU *cpu)
05330448 2355{
1bc22652 2356 CPUX86State *env = &cpu->env;
d71b62a1 2357 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
9c600a84 2358 int ret, i;
fcc35e7c 2359 uint64_t mtrr_top_bits;
05330448 2360
d71b62a1
EH		 2361 kvm_msr_buf_reset(cpu);
2362
9c600a84
EH		 2363 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2364 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2365 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2366 kvm_msr_entry_add(cpu, MSR_PAT, 0);
c3a3a7d3 2367 if (has_msr_star) {
9c600a84 2368 kvm_msr_entry_add(cpu, MSR_STAR, 0);
b9bec74b 2369 }
c3a3a7d3 2370 if (has_msr_hsave_pa) {
9c600a84 2371 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
b9bec74b 2372 }
c9b8f6b6 2373 if (has_msr_tsc_aux) {
9c600a84 2374 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
c9b8f6b6 2375 }
f28558d3 2376 if (has_msr_tsc_adjust) {
9c600a84 2377 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
f28558d3 2378 }
aa82ba54 2379 if (has_msr_tsc_deadline) {
9c600a84 2380 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
aa82ba54 2381 }
21e87c46 2382 if (has_msr_misc_enable) {
9c600a84 2383 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
21e87c46 2384 }
fc12d72e 2385 if (has_msr_smbase) {
9c600a84 2386 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
fc12d72e 2387 }
e13713db
LA		 2388 if (has_msr_smi_count) {
2389 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2390 }
df67696e 2391 if (has_msr_feature_control) {
9c600a84 2392 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
df67696e 2393 }
79e9ebeb 2394 if (has_msr_bndcfgs) {
9c600a84 2395 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
79e9ebeb 2396 }
18cd2c17 2397 if (has_msr_xss) {
9c600a84 2398 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
18cd2c17 2399 }
a33a2cfe
PB		 2400 if (has_msr_spec_ctrl) {
2401 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2402 }
cfeea0c0
KRW		 2403 if (has_msr_virt_ssbd) {
2404 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2405 }
b8cc45d6 2406 if (!env->tsc_valid) {
9c600a84 2407 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
1354869c 2408 env->tsc_valid = !runstate_is_running();
b8cc45d6
GC		 2409 }
2410
05330448 2411#ifdef TARGET_X86_64
25d2e361 2412 if (lm_capable_kernel) {
9c600a84
EH		 2413 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2414 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2415 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2416 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
25d2e361 2417 }
05330448 2418#endif
9c600a84
EH		 2419 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2420 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
55c911a5 2421 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
9c600a84 2422 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
c5999bfc 2423 }
55c911a5 2424 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
9c600a84 2425 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
bc9a839d 2426 }
55c911a5 2427 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
9c600a84 2428 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
917367aa 2429 }
0b368a10
JD		 2430 if (has_architectural_pmu_version > 0) {
2431 if (has_architectural_pmu_version > 1) {
2432 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2433 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2434 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2435 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2436 }
2437 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
9c600a84 2438 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
0d894367 2439 }
0b368a10 2440 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
9c600a84
EH		 2441 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2442 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
0d894367
PB		 2443 }
2444 }
1a03675d 2445
57780495 2446 if (env->mcg_cap) {
9c600a84
EH		 2447 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2448 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
87f8b626
AR		 2449 if (has_msr_mcg_ext_ctl) {
2450 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2451 }
b9bec74b 2452 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
9c600a84 2453 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
b9bec74b 2454 }
57780495 2455 }
57780495 2456
1c90ef26 2457 if (has_msr_hv_hypercall) {
9c600a84
EH		 2458 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2459 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
1c90ef26 2460 }
2d384d7c 2461 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VAPIC)) {
9c600a84 2462 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
5ef68987 2463 }
2d384d7c 2464 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_TIME)) {
9c600a84 2465 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
48a5f3bc 2466 }
2d384d7c 2467 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_REENLIGHTENMENT)) {
ba6a4fd9
VK		 2468 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2469 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2470 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2471 }
f2a53c9e
AS		 2472 if (has_msr_hv_crash) {
2473 int j;
2474
5e953812 2475 for (j = 0; j < HV_CRASH_PARAMS; j++) {
9c600a84 2476 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
f2a53c9e
AS		 2477 }
2478 }
46eb8f98 2479 if (has_msr_hv_runtime) {
9c600a84 2480 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
46eb8f98 2481 }
2d384d7c 2482 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_SYNIC)) {
866eea9a
AS		 2483 uint32_t msr;
2484
9c600a84 2485 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
9c600a84
EH		 2486 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2487 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
866eea9a 2488 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
9c600a84 2489 kvm_msr_entry_add(cpu, msr, 0);
866eea9a
AS		 2490 }
2491 }
ff99aa64
AS		 2492 if (has_msr_hv_stimer) {
2493 uint32_t msr;
2494
2495 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2496 msr++) {
9c600a84 2497 kvm_msr_entry_add(cpu, msr, 0);
ff99aa64
AS		 2498 }
2499 }
1eabfce6 2500 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
9c600a84
EH		 2501 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2502 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2503 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2504 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2505 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2506 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2507 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2508 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2509 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2510 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2511 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2512 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
d1ae67f6 2513 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
9c600a84
EH		 2514 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2515 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
d1ae67f6
AW		 2516 }
2517 }
5ef68987 2518
b77146e9
CP		 2519 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2520 int addr_num =
2521 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2522
2523 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2524 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2525 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2526 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2527 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2528 for (i = 0; i < addr_num; i++) {
2529 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2530 }
2531 }
2532
d71b62a1 2533 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
b9bec74b 2534 if (ret < 0) {
05330448 2535 return ret;
b9bec74b 2536 }
05330448 2537
c70b11d1
EH		 2538 if (ret < cpu->kvm_msr_buf->nmsrs) {
2539 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2540 error_report("error: failed to get MSR 0x%" PRIx32,
2541 (uint32_t)e->index);
2542 }
2543
9c600a84 2544 assert(ret == cpu->kvm_msr_buf->nmsrs);
fcc35e7c
DDAG		 2545 /*
2546 * MTRR masks: Each mask consists of 5 parts
2547 * a 10..0: must be zero
2548 * b 11 : valid bit
2549 * c n-1.12: actual mask bits
2550 * d 51..n: reserved must be zero
2551 * e 63.52: reserved must be zero
2552 *
2553 * 'n' is the number of physical bits supported by the CPU and is
2554 * apparently always <= 52. We know our 'n' but don't know what
2555 * the destinations 'n' is; it might be smaller, in which case
2556 * it masks (c) on loading. It might be larger, in which case
2557 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2558 * we're migrating to.
2559 */
2560
2561 if (cpu->fill_mtrr_mask) {
2562 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2563 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2564 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2565 } else {
2566 mtrr_top_bits = 0;
2567 }
2568
05330448 2569 for (i = 0; i < ret; i++) {
0d894367
PB		 2570 uint32_t index = msrs[i].index;
2571 switch (index) {
05330448
AL		 2572 case MSR_IA32_SYSENTER_CS:
2573 env->sysenter_cs = msrs[i].data;
2574 break;
2575 case MSR_IA32_SYSENTER_ESP:
2576 env->sysenter_esp = msrs[i].data;
2577 break;
2578 case MSR_IA32_SYSENTER_EIP:
2579 env->sysenter_eip = msrs[i].data;
2580 break;
0c03266a
JK		 2581 case MSR_PAT:
2582 env->pat = msrs[i].data;
2583 break;
05330448
AL		 2584 case MSR_STAR:
2585 env->star = msrs[i].data;
2586 break;
2587#ifdef TARGET_X86_64
2588 case MSR_CSTAR:
2589 env->cstar = msrs[i].data;
2590 break;
2591 case MSR_KERNELGSBASE:
2592 env->kernelgsbase = msrs[i].data;
2593 break;
2594 case MSR_FMASK:
2595 env->fmask = msrs[i].data;
2596 break;
2597 case MSR_LSTAR:
2598 env->lstar = msrs[i].data;
2599 break;
2600#endif
2601 case MSR_IA32_TSC:
2602 env->tsc = msrs[i].data;
2603 break;
c9b8f6b6
AS		 2604 case MSR_TSC_AUX:
2605 env->tsc_aux = msrs[i].data;
2606 break;
f28558d3
WA		 2607 case MSR_TSC_ADJUST:
2608 env->tsc_adjust = msrs[i].data;
2609 break;
aa82ba54
LJ		 2610 case MSR_IA32_TSCDEADLINE:
2611 env->tsc_deadline = msrs[i].data;
2612 break;
aa851e36
MT		 2613 case MSR_VM_HSAVE_PA:
2614 env->vm_hsave = msrs[i].data;
2615 break;
1a03675d
GC		 2616 case MSR_KVM_SYSTEM_TIME:
2617 env->system_time_msr = msrs[i].data;
2618 break;
2619 case MSR_KVM_WALL_CLOCK:
2620 env->wall_clock_msr = msrs[i].data;
2621 break;
57780495
MT		 2622 case MSR_MCG_STATUS:
2623 env->mcg_status = msrs[i].data;
2624 break;
2625 case MSR_MCG_CTL:
2626 env->mcg_ctl = msrs[i].data;
2627 break;
87f8b626
AR		 2628 case MSR_MCG_EXT_CTL:
2629 env->mcg_ext_ctl = msrs[i].data;
2630 break;
21e87c46
AK		 2631 case MSR_IA32_MISC_ENABLE:
2632 env->msr_ia32_misc_enable = msrs[i].data;
2633 break;
fc12d72e
PB		 2634 case MSR_IA32_SMBASE:
2635 env->smbase = msrs[i].data;
2636 break;
e13713db
LA		 2637 case MSR_SMI_COUNT:
2638 env->msr_smi_count = msrs[i].data;
2639 break;
0779caeb
ACL		 2640 case MSR_IA32_FEATURE_CONTROL:
2641 env->msr_ia32_feature_control = msrs[i].data;
df67696e 2642 break;
79e9ebeb
LJ		 2643 case MSR_IA32_BNDCFGS:
2644 env->msr_bndcfgs = msrs[i].data;
2645 break;
18cd2c17
WL		 2646 case MSR_IA32_XSS:
2647 env->xss = msrs[i].data;
2648 break;
57780495 2649 default:
57780495
MT		 2650 if (msrs[i].index >= MSR_MC0_CTL &&
2651 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2652 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
57780495 2653 }
d8da8574 2654 break;
f6584ee2
GN		 2655 case MSR_KVM_ASYNC_PF_EN:
2656 env->async_pf_en_msr = msrs[i].data;
2657 break;
bc9a839d
MT		 2658 case MSR_KVM_PV_EOI_EN:
2659 env->pv_eoi_en_msr = msrs[i].data;
2660 break;
917367aa
MT		 2661 case MSR_KVM_STEAL_TIME:
2662 env->steal_time_msr = msrs[i].data;
2663 break;
0d894367
PB		 2664 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2665 env->msr_fixed_ctr_ctrl = msrs[i].data;
2666 break;
2667 case MSR_CORE_PERF_GLOBAL_CTRL:
2668 env->msr_global_ctrl = msrs[i].data;
2669 break;
2670 case MSR_CORE_PERF_GLOBAL_STATUS:
2671 env->msr_global_status = msrs[i].data;
2672 break;
2673 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2674 env->msr_global_ovf_ctrl = msrs[i].data;
2675 break;
2676 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2677 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2678 break;
2679 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2680 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2681 break;
2682 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2683 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2684 break;
1c90ef26
VR		 2685 case HV_X64_MSR_HYPERCALL:
2686 env->msr_hv_hypercall = msrs[i].data;
2687 break;
2688 case HV_X64_MSR_GUEST_OS_ID:
2689 env->msr_hv_guest_os_id = msrs[i].data;
2690 break;
5ef68987
VR		 2691 case HV_X64_MSR_APIC_ASSIST_PAGE:
2692 env->msr_hv_vapic = msrs[i].data;
2693 break;
48a5f3bc
VR		 2694 case HV_X64_MSR_REFERENCE_TSC:
2695 env->msr_hv_tsc = msrs[i].data;
2696 break;
f2a53c9e
AS		 2697 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2698 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2699 break;
46eb8f98
AS		 2700 case HV_X64_MSR_VP_RUNTIME:
2701 env->msr_hv_runtime = msrs[i].data;
2702 break;
866eea9a
AS		 2703 case HV_X64_MSR_SCONTROL:
2704 env->msr_hv_synic_control = msrs[i].data;
2705 break;
866eea9a
AS		 2706 case HV_X64_MSR_SIEFP:
2707 env->msr_hv_synic_evt_page = msrs[i].data;
2708 break;
2709 case HV_X64_MSR_SIMP:
2710 env->msr_hv_synic_msg_page = msrs[i].data;
2711 break;
2712 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2713 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
ff99aa64
AS		 2714 break;
2715 case HV_X64_MSR_STIMER0_CONFIG:
2716 case HV_X64_MSR_STIMER1_CONFIG:
2717 case HV_X64_MSR_STIMER2_CONFIG:
2718 case HV_X64_MSR_STIMER3_CONFIG:
2719 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2720 msrs[i].data;
2721 break;
2722 case HV_X64_MSR_STIMER0_COUNT:
2723 case HV_X64_MSR_STIMER1_COUNT:
2724 case HV_X64_MSR_STIMER2_COUNT:
2725 case HV_X64_MSR_STIMER3_COUNT:
2726 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2727 msrs[i].data;
866eea9a 2728 break;
ba6a4fd9
VK		 2729 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2730 env->msr_hv_reenlightenment_control = msrs[i].data;
2731 break;
2732 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2733 env->msr_hv_tsc_emulation_control = msrs[i].data;
2734 break;
2735 case HV_X64_MSR_TSC_EMULATION_STATUS:
2736 env->msr_hv_tsc_emulation_status = msrs[i].data;
2737 break;
d1ae67f6
AW		 2738 case MSR_MTRRdefType:
2739 env->mtrr_deftype = msrs[i].data;
2740 break;
2741 case MSR_MTRRfix64K_00000:
2742 env->mtrr_fixed[0] = msrs[i].data;
2743 break;
2744 case MSR_MTRRfix16K_80000:
2745 env->mtrr_fixed[1] = msrs[i].data;
2746 break;
2747 case MSR_MTRRfix16K_A0000:
2748 env->mtrr_fixed[2] = msrs[i].data;
2749 break;
2750 case MSR_MTRRfix4K_C0000:
2751 env->mtrr_fixed[3] = msrs[i].data;
2752 break;
2753 case MSR_MTRRfix4K_C8000:
2754 env->mtrr_fixed[4] = msrs[i].data;
2755 break;
2756 case MSR_MTRRfix4K_D0000:
2757 env->mtrr_fixed[5] = msrs[i].data;
2758 break;
2759 case MSR_MTRRfix4K_D8000:
2760 env->mtrr_fixed[6] = msrs[i].data;
2761 break;
2762 case MSR_MTRRfix4K_E0000:
2763 env->mtrr_fixed[7] = msrs[i].data;
2764 break;
2765 case MSR_MTRRfix4K_E8000:
2766 env->mtrr_fixed[8] = msrs[i].data;
2767 break;
2768 case MSR_MTRRfix4K_F0000:
2769 env->mtrr_fixed[9] = msrs[i].data;
2770 break;
2771 case MSR_MTRRfix4K_F8000:
2772 env->mtrr_fixed[10] = msrs[i].data;
2773 break;
2774 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2775 if (index & 1) {
fcc35e7c
DDAG		 2776 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2777 mtrr_top_bits;
d1ae67f6
AW		 2778 } else {
2779 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2780 }
2781 break;
a33a2cfe
PB		 2782 case MSR_IA32_SPEC_CTRL:
2783 env->spec_ctrl = msrs[i].data;
2784 break;
cfeea0c0
KRW		 2785 case MSR_VIRT_SSBD:
2786 env->virt_ssbd = msrs[i].data;
2787 break;
b77146e9
CP		 2788 case MSR_IA32_RTIT_CTL:
2789 env->msr_rtit_ctrl = msrs[i].data;
2790 break;
2791 case MSR_IA32_RTIT_STATUS:
2792 env->msr_rtit_status = msrs[i].data;
2793 break;
2794 case MSR_IA32_RTIT_OUTPUT_BASE:
2795 env->msr_rtit_output_base = msrs[i].data;
2796 break;
2797 case MSR_IA32_RTIT_OUTPUT_MASK:
2798 env->msr_rtit_output_mask = msrs[i].data;
2799 break;
2800 case MSR_IA32_RTIT_CR3_MATCH:
2801 env->msr_rtit_cr3_match = msrs[i].data;
2802 break;
2803 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2804 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2805 break;
05330448
AL		 2806 }
2807 }
2808
2809 return 0;
2810}
2811
1bc22652 2812static int kvm_put_mp_state(X86CPU *cpu)
9bdbe550 2813{
1bc22652 2814 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
9bdbe550 2815
1bc22652 2816 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
9bdbe550
HB		 2817}
2818
23d02d9b 2819static int kvm_get_mp_state(X86CPU *cpu)
9bdbe550 2820{
259186a7 2821 CPUState *cs = CPU(cpu);
23d02d9b 2822 CPUX86State *env = &cpu->env;
9bdbe550
HB		 2823 struct kvm_mp_state mp_state;
2824 int ret;
2825
259186a7 2826 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
9bdbe550
HB		 2827 if (ret < 0) {
2828 return ret;
2829 }
2830 env->mp_state = mp_state.mp_state;
c14750e8 2831 if (kvm_irqchip_in_kernel()) {
259186a7 2832 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
c14750e8 2833 }
9bdbe550
HB		 2834 return 0;
2835}
2836
1bc22652 2837static int kvm_get_apic(X86CPU *cpu)
680c1c6f 2838{
02e51483 2839 DeviceState *apic = cpu->apic_state;
680c1c6f
JK		 2840 struct kvm_lapic_state kapic;
2841 int ret;
2842
3d4b2649 2843 if (apic && kvm_irqchip_in_kernel()) {
1bc22652 2844 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
680c1c6f
JK		 2845 if (ret < 0) {
2846 return ret;
2847 }
2848
2849 kvm_get_apic_state(apic, &kapic);
2850 }
2851 return 0;
2852}
2853
1bc22652 2854static int kvm_put_vcpu_events(X86CPU *cpu, int level)
a0fb002c 2855{
fc12d72e 2856 CPUState *cs = CPU(cpu);
1bc22652 2857 CPUX86State *env = &cpu->env;
076796f8 2858 struct kvm_vcpu_events events = {};
a0fb002c
JK		 2859
2860 if (!kvm_has_vcpu_events()) {
2861 return 0;
2862 }
2863
31827373
JK		 2864 events.exception.injected = (env->exception_injected >= 0);
2865 events.exception.nr = env->exception_injected;
a0fb002c
JK		 2866 events.exception.has_error_code = env->has_error_code;
2867 events.exception.error_code = env->error_code;
2868
2869 events.interrupt.injected = (env->interrupt_injected >= 0);
2870 events.interrupt.nr = env->interrupt_injected;
2871 events.interrupt.soft = env->soft_interrupt;
2872
2873 events.nmi.injected = env->nmi_injected;
2874 events.nmi.pending = env->nmi_pending;
2875 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2876
2877 events.sipi_vector = env->sipi_vector;
68c6efe0 2878 events.flags = 0;
a0fb002c 2879
fc12d72e
PB		 2880 if (has_msr_smbase) {
2881 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2882 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2883 if (kvm_irqchip_in_kernel()) {
2884 /* As soon as these are moved to the kernel, remove them
2885 * from cs->interrupt_request.
2886 */
2887 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2888 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2889 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2890 } else {
2891 /* Keep these in cs->interrupt_request. */
2892 events.smi.pending = 0;
2893 events.smi.latched_init = 0;
2894 }
fc3a1fd7
DDAG		 2895 /* Stop SMI delivery on old machine types to avoid a reboot
2896 * on an inward migration of an old VM.
2897 */
2898 if (!cpu->kvm_no_smi_migration) {
2899 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2900 }
fc12d72e
PB		 2901 }
2902
ea643051 2903 if (level >= KVM_PUT_RESET_STATE) {
4fadfa00
PH		 2904 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2905 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2906 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2907 }
ea643051 2908 }
aee028b9 2909
1bc22652 2910 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
a0fb002c
JK		 2911}
2912
1bc22652 2913static int kvm_get_vcpu_events(X86CPU *cpu)
a0fb002c 2914{
1bc22652 2915 CPUX86State *env = &cpu->env;
a0fb002c
JK		 2916 struct kvm_vcpu_events events;
2917 int ret;
2918
2919 if (!kvm_has_vcpu_events()) {
2920 return 0;
2921 }
2922
fc12d72e 2923 memset(&events, 0, sizeof(events));
1bc22652 2924 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
a0fb002c
JK		 2925 if (ret < 0) {
2926 return ret;
2927 }
31827373 2928 env->exception_injected =
a0fb002c
JK		 2929 events.exception.injected ? events.exception.nr : -1;
2930 env->has_error_code = events.exception.has_error_code;
2931 env->error_code = events.exception.error_code;
2932
2933 env->interrupt_injected =
2934 events.interrupt.injected ? events.interrupt.nr : -1;
2935 env->soft_interrupt = events.interrupt.soft;
2936
2937 env->nmi_injected = events.nmi.injected;
2938 env->nmi_pending = events.nmi.pending;
2939 if (events.nmi.masked) {
2940 env->hflags2 |= HF2_NMI_MASK;
2941 } else {
2942 env->hflags2 &= ~HF2_NMI_MASK;
2943 }
2944
fc12d72e
PB		 2945 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2946 if (events.smi.smm) {
2947 env->hflags |= HF_SMM_MASK;
2948 } else {
2949 env->hflags &= ~HF_SMM_MASK;
2950 }
2951 if (events.smi.pending) {
2952 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2953 } else {
2954 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2955 }
2956 if (events.smi.smm_inside_nmi) {
2957 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2958 } else {
2959 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2960 }
2961 if (events.smi.latched_init) {
2962 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2963 } else {
2964 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2965 }
2966 }
2967
a0fb002c 2968 env->sipi_vector = events.sipi_vector;
a0fb002c
JK		 2969
2970 return 0;
2971}
2972
1bc22652 2973static int kvm_guest_debug_workarounds(X86CPU *cpu)
b0b1d690 2974{
ed2803da 2975 CPUState *cs = CPU(cpu);
1bc22652 2976 CPUX86State *env = &cpu->env;
b0b1d690 2977 int ret = 0;
b0b1d690
JK		 2978 unsigned long reinject_trap = 0;
2979
2980 if (!kvm_has_vcpu_events()) {
2981 if (env->exception_injected == 1) {
2982 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2983 } else if (env->exception_injected == 3) {
2984 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2985 }
2986 env->exception_injected = -1;
2987 }
2988
2989 /*
2990 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2991 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2992 * by updating the debug state once again if single-stepping is on.
2993 * Another reason to call kvm_update_guest_debug here is a pending debug
2994 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2995 * reinject them via SET_GUEST_DEBUG.
2996 */
2997 if (reinject_trap ||
ed2803da 2998 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
38e478ec 2999 ret = kvm_update_guest_debug(cs, reinject_trap);
b0b1d690 3000 }
b0b1d690
JK		 3001 return ret;
3002}
3003
1bc22652 3004static int kvm_put_debugregs(X86CPU *cpu)
ff44f1a3 3005{
1bc22652 3006 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3007 struct kvm_debugregs dbgregs;
3008 int i;
3009
3010 if (!kvm_has_debugregs()) {
3011 return 0;
3012 }
3013
3014 for (i = 0; i < 4; i++) {
3015 dbgregs.db[i] = env->dr[i];
3016 }
3017 dbgregs.dr6 = env->dr[6];
3018 dbgregs.dr7 = env->dr[7];
3019 dbgregs.flags = 0;
3020
1bc22652 3021 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
ff44f1a3
JK		 3022}
3023
1bc22652 3024static int kvm_get_debugregs(X86CPU *cpu)
ff44f1a3 3025{
1bc22652 3026 CPUX86State *env = &cpu->env;
ff44f1a3
JK		 3027 struct kvm_debugregs dbgregs;
3028 int i, ret;
3029
3030 if (!kvm_has_debugregs()) {
3031 return 0;
3032 }
3033
1bc22652 3034 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
ff44f1a3 3035 if (ret < 0) {
b9bec74b 3036 return ret;
ff44f1a3
JK		 3037 }
3038 for (i = 0; i < 4; i++) {
3039 env->dr[i] = dbgregs.db[i];
3040 }
3041 env->dr[4] = env->dr[6] = dbgregs.dr6;
3042 env->dr[5] = env->dr[7] = dbgregs.dr7;
ff44f1a3
JK		 3043
3044 return 0;
3045}
3046
20d695a9 3047int kvm_arch_put_registers(CPUState *cpu, int level)
05330448 3048{
20d695a9 3049 X86CPU *x86_cpu = X86_CPU(cpu);
05330448
AL		 3050 int ret;
3051
2fa45344 3052 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
dbaa07c4 3053
48e1a45c 3054 if (level >= KVM_PUT_RESET_STATE) {
6bdf863d
JK		 3055 ret = kvm_put_msr_feature_control(x86_cpu);
3056 if (ret < 0) {
3057 return ret;
3058 }
3059 }
3060
36f96c4b
HZ		 3061 if (level == KVM_PUT_FULL_STATE) {
3062 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3063 * because TSC frequency mismatch shouldn't abort migration,
3064 * unless the user explicitly asked for a more strict TSC
3065 * setting (e.g. using an explicit "tsc-freq" option).
3066 */
3067 kvm_arch_set_tsc_khz(cpu);
3068 }
3069
1bc22652 3070 ret = kvm_getput_regs(x86_cpu, 1);
b9bec74b 3071 if (ret < 0) {
05330448 3072 return ret;
b9bec74b 3073 }
1bc22652 3074 ret = kvm_put_xsave(x86_cpu);
b9bec74b 3075 if (ret < 0) {
f1665b21 3076 return ret;
b9bec74b 3077 }
1bc22652 3078 ret = kvm_put_xcrs(x86_cpu);
b9bec74b 3079 if (ret < 0) {
05330448 3080 return ret;
b9bec74b 3081 }
1bc22652 3082 ret = kvm_put_sregs(x86_cpu);
b9bec74b 3083 if (ret < 0) {
05330448 3084 return ret;
b9bec74b 3085 }
ab443475 3086 /* must be before kvm_put_msrs */
1bc22652 3087 ret = kvm_inject_mce_oldstyle(x86_cpu);
ab443475
JK		 3088 if (ret < 0) {
3089 return ret;
3090 }
1bc22652 3091 ret = kvm_put_msrs(x86_cpu, level);
b9bec74b 3092 if (ret < 0) {
05330448 3093 return ret;
b9bec74b 3094 }
4fadfa00
PH		 3095 ret = kvm_put_vcpu_events(x86_cpu, level);
3096 if (ret < 0) {
3097 return ret;
3098 }
ea643051 3099 if (level >= KVM_PUT_RESET_STATE) {
1bc22652 3100 ret = kvm_put_mp_state(x86_cpu);
b9bec74b 3101 if (ret < 0) {
680c1c6f
JK		 3102 return ret;
3103 }
ea643051 3104 }
7477cd38
MT		 3105
3106 ret = kvm_put_tscdeadline_msr(x86_cpu);
3107 if (ret < 0) {
3108 return ret;
3109 }
1bc22652 3110 ret = kvm_put_debugregs(x86_cpu);
b9bec74b 3111 if (ret < 0) {
b0b1d690 3112 return ret;
b9bec74b 3113 }
b0b1d690 3114 /* must be last */
1bc22652 3115 ret = kvm_guest_debug_workarounds(x86_cpu);
b9bec74b 3116 if (ret < 0) {
ff44f1a3 3117 return ret;
b9bec74b 3118 }
05330448
AL		 3119 return 0;
3120}
3121
20d695a9 3122int kvm_arch_get_registers(CPUState *cs)
05330448 3123{
20d695a9 3124 X86CPU *cpu = X86_CPU(cs);
05330448
AL		 3125 int ret;
3126
20d695a9 3127 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
dbaa07c4 3128
4fadfa00 3129 ret = kvm_get_vcpu_events(cpu);
b9bec74b 3130 if (ret < 0) {
f4f1110e 3131 goto out;
b9bec74b 3132 }
4fadfa00
PH		 3133 /*
3134 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3135 * KVM_GET_REGS and KVM_GET_SREGS.
3136 */
3137 ret = kvm_get_mp_state(cpu);
b9bec74b 3138 if (ret < 0) {
f4f1110e 3139 goto out;
b9bec74b 3140 }
4fadfa00 3141 ret = kvm_getput_regs(cpu, 0);
b9bec74b 3142 if (ret < 0) {
f4f1110e 3143 goto out;
b9bec74b 3144 }
4fadfa00 3145 ret = kvm_get_xsave(cpu);
b9bec74b 3146 if (ret < 0) {
f4f1110e 3147 goto out;
b9bec74b 3148 }
4fadfa00 3149 ret = kvm_get_xcrs(cpu);
b9bec74b 3150 if (ret < 0) {
f4f1110e 3151 goto out;
b9bec74b 3152 }
4fadfa00 3153 ret = kvm_get_sregs(cpu);
b9bec74b 3154 if (ret < 0) {
f4f1110e 3155 goto out;
b9bec74b 3156 }
4fadfa00 3157 ret = kvm_get_msrs(cpu);
680c1c6f 3158 if (ret < 0) {
f4f1110e 3159 goto out;
680c1c6f 3160 }
4fadfa00 3161 ret = kvm_get_apic(cpu);
b9bec74b 3162 if (ret < 0) {
f4f1110e 3163 goto out;
b9bec74b 3164 }
1bc22652 3165 ret = kvm_get_debugregs(cpu);
b9bec74b 3166 if (ret < 0) {
f4f1110e 3167 goto out;
b9bec74b 3168 }
f4f1110e
RH		 3169 ret = 0;
3170 out:
3171 cpu_sync_bndcs_hflags(&cpu->env);
3172 return ret;
05330448
AL		 3173}
3174
20d695a9 3175void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
05330448 3176{
20d695a9
AF		 3177 X86CPU *x86_cpu = X86_CPU(cpu);
3178 CPUX86State *env = &x86_cpu->env;
ce377af3
JK		 3179 int ret;
3180
276ce815 3181 /* Inject NMI */
fc12d72e
PB		 3182 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3183 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3184 qemu_mutex_lock_iothread();
3185 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3186 qemu_mutex_unlock_iothread();
3187 DPRINTF("injected NMI\n");
3188 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3189 if (ret < 0) {
3190 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3191 strerror(-ret));
3192 }
3193 }
3194 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3195 qemu_mutex_lock_iothread();
3196 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3197 qemu_mutex_unlock_iothread();
3198 DPRINTF("injected SMI\n");
3199 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3200 if (ret < 0) {
3201 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3202 strerror(-ret));
3203 }
ce377af3 3204 }
276ce815
LJ		 3205 }
3206
15eafc2e 3207 if (!kvm_pic_in_kernel()) {
4b8523ee
JK		 3208 qemu_mutex_lock_iothread();
3209 }
3210
e0723c45
PB		 3211 /* Force the VCPU out of its inner loop to process any INIT requests
3212 * or (for userspace APIC, but it is cheap to combine the checks here)
3213 * pending TPR access reports.
3214 */
3215 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
fc12d72e
PB		 3216 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3217 !(env->hflags & HF_SMM_MASK)) {
3218 cpu->exit_request = 1;
3219 }
3220 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3221 cpu->exit_request = 1;
3222 }
e0723c45 3223 }
05330448 3224
15eafc2e 3225 if (!kvm_pic_in_kernel()) {
db1669bc
JK		 3226 /* Try to inject an interrupt if the guest can accept it */
3227 if (run->ready_for_interrupt_injection &&
259186a7 3228 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
db1669bc
JK		 3229 (env->eflags & IF_MASK)) {
3230 int irq;
3231
259186a7 3232 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
db1669bc
JK		 3233 irq = cpu_get_pic_interrupt(env);
3234 if (irq >= 0) {
3235 struct kvm_interrupt intr;
3236
3237 intr.irq = irq;
db1669bc 3238 DPRINTF("injected interrupt %d\n", irq);
1bc22652 3239 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
ce377af3
JK		 3240 if (ret < 0) {
3241 fprintf(stderr,
3242 "KVM: injection failed, interrupt lost (%s)\n",
3243 strerror(-ret));
3244 }
db1669bc
JK		 3245 }
3246 }
05330448 3247
db1669bc
JK		 3248 /* If we have an interrupt but the guest is not ready to receive an
3249 * interrupt, request an interrupt window exit. This will
3250 * cause a return to userspace as soon as the guest is ready to
3251 * receive interrupts. */
259186a7 3252 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
db1669bc
JK		 3253 run->request_interrupt_window = 1;
3254 } else {
3255 run->request_interrupt_window = 0;
3256 }
3257
3258 DPRINTF("setting tpr\n");
02e51483 3259 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
4b8523ee
JK		 3260
3261 qemu_mutex_unlock_iothread();
db1669bc 3262 }
05330448
AL		 3263}
3264
4c663752 3265MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
05330448 3266{
20d695a9
AF		 3267 X86CPU *x86_cpu = X86_CPU(cpu);
3268 CPUX86State *env = &x86_cpu->env;
3269
fc12d72e
PB		 3270 if (run->flags & KVM_RUN_X86_SMM) {
3271 env->hflags |= HF_SMM_MASK;
3272 } else {
f5c052b9 3273 env->hflags &= ~HF_SMM_MASK;
fc12d72e 3274 }
b9bec74b 3275 if (run->if_flag) {
05330448 3276 env->eflags |= IF_MASK;
b9bec74b 3277 } else {
05330448 3278 env->eflags &= ~IF_MASK;
b9bec74b 3279 }
4b8523ee
JK		 3280
3281 /* We need to protect the apic state against concurrent accesses from
3282 * different threads in case the userspace irqchip is used. */
3283 if (!kvm_irqchip_in_kernel()) {
3284 qemu_mutex_lock_iothread();
3285 }
02e51483
CF		 3286 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3287 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
4b8523ee
JK		 3288 if (!kvm_irqchip_in_kernel()) {
3289 qemu_mutex_unlock_iothread();
3290 }
f794aa4a 3291 return cpu_get_mem_attrs(env);
05330448
AL		 3292}
3293
20d695a9 3294int kvm_arch_process_async_events(CPUState *cs)
0af691d7 3295{
20d695a9
AF		 3296 X86CPU *cpu = X86_CPU(cs);
3297 CPUX86State *env = &cpu->env;
232fc23b 3298
259186a7 3299 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
ab443475
JK		 3300 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3301 assert(env->mcg_cap);
3302
259186a7 3303 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
ab443475 3304
dd1750d7 3305 kvm_cpu_synchronize_state(cs);
ab443475
JK		 3306
3307 if (env->exception_injected == EXCP08_DBLE) {
3308 /* this means triple fault */
cf83f140 3309 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
fcd7d003 3310 cs->exit_request = 1;
ab443475
JK		 3311 return 0;
3312 }
3313 env->exception_injected = EXCP12_MCHK;
3314 env->has_error_code = 0;
3315
259186a7 3316 cs->halted = 0;
ab443475
JK		 3317 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3318 env->mp_state = KVM_MP_STATE_RUNNABLE;
3319 }
3320 }
3321
fc12d72e
PB		 3322 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3323 !(env->hflags & HF_SMM_MASK)) {
e0723c45
PB		 3324 kvm_cpu_synchronize_state(cs);
3325 do_cpu_init(cpu);
3326 }
3327
db1669bc
JK		 3328 if (kvm_irqchip_in_kernel()) {
3329 return 0;
3330 }
3331
259186a7
AF		 3332 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3333 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
02e51483 3334 apic_poll_irq(cpu->apic_state);
5d62c43a 3335 }
259186a7 3336 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
4601f7b0 3337 (env->eflags & IF_MASK)) ||
259186a7
AF		 3338 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3339 cs->halted = 0;
6792a57b 3340 }
259186a7 3341 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
dd1750d7 3342 kvm_cpu_synchronize_state(cs);
232fc23b 3343 do_cpu_sipi(cpu);
0af691d7 3344 }
259186a7
AF		 3345 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3346 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
dd1750d7 3347 kvm_cpu_synchronize_state(cs);
02e51483 3348 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
d362e757
JK		 3349 env->tpr_access_type);
3350 }
0af691d7 3351
259186a7 3352 return cs->halted;
0af691d7
MT		 3353}
3354
839b5630 3355static int kvm_handle_halt(X86CPU *cpu)
05330448 3356{
259186a7 3357 CPUState *cs = CPU(cpu);
839b5630
AF		 3358 CPUX86State *env = &cpu->env;
3359
259186a7 3360 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
05330448 3361 (env->eflags & IF_MASK)) &&
259186a7
AF		 3362 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3363 cs->halted = 1;
bb4ea393 3364 return EXCP_HLT;
05330448
AL		 3365 }
3366
bb4ea393 3367 return 0;
05330448
AL		 3368}
3369
f7575c96 3370static int kvm_handle_tpr_access(X86CPU *cpu)
d362e757 3371{
f7575c96
AF		 3372 CPUState *cs = CPU(cpu);
3373 struct kvm_run *run = cs->kvm_run;
d362e757 3374
02e51483 3375 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
d362e757
JK		 3376 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3377 : TPR_ACCESS_READ);
3378 return 1;
3379}
3380
f17ec444 3381int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9 3382{
38972938 3383 static const uint8_t int3 = 0xcc;
64bf3f4e 3384
f17ec444
AF		 3385 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3386 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
e22a25c9 3387 return -EINVAL;
b9bec74b 3388 }
e22a25c9
AL		 3389 return 0;
3390}
3391
f17ec444 3392int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
e22a25c9
AL		 3393{
3394 uint8_t int3;
3395
f17ec444
AF		 3396 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3397 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
e22a25c9 3398 return -EINVAL;
b9bec74b 3399 }
e22a25c9
AL		 3400 return 0;
3401}
3402
3403static struct {
3404 target_ulong addr;
3405 int len;
3406 int type;
3407} hw_breakpoint[4];
3408
3409static int nb_hw_breakpoint;
3410
3411static int find_hw_breakpoint(target_ulong addr, int len, int type)
3412{
3413 int n;
3414
b9bec74b 3415 for (n = 0; n < nb_hw_breakpoint; n++) {
e22a25c9 3416 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
b9bec74b 3417 (hw_breakpoint[n].len == len || len == -1)) {
e22a25c9 3418 return n;
b9bec74b
JK		 3419 }
3420 }
e22a25c9
AL		 3421 return -1;
3422}
3423
3424int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3425 target_ulong len, int type)
3426{
3427 switch (type) {
3428 case GDB_BREAKPOINT_HW:
3429 len = 1;
3430 break;
3431 case GDB_WATCHPOINT_WRITE:
3432 case GDB_WATCHPOINT_ACCESS:
3433 switch (len) {
3434 case 1:
3435 break;
3436 case 2:
3437 case 4:
3438 case 8:
b9bec74b 3439 if (addr & (len - 1)) {
e22a25c9 3440 return -EINVAL;
b9bec74b 3441 }
e22a25c9
AL		 3442 break;
3443 default:
3444 return -EINVAL;
3445 }
3446 break;
3447 default:
3448 return -ENOSYS;
3449 }
3450
b9bec74b 3451 if (nb_hw_breakpoint == 4) {
e22a25c9 3452 return -ENOBUFS;
b9bec74b
JK		 3453 }
3454 if (find_hw_breakpoint(addr, len, type) >= 0) {
e22a25c9 3455 return -EEXIST;
b9bec74b 3456 }
e22a25c9
AL		 3457 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3458 hw_breakpoint[nb_hw_breakpoint].len = len;
3459 hw_breakpoint[nb_hw_breakpoint].type = type;
3460 nb_hw_breakpoint++;
3461
3462 return 0;
3463}
3464
3465int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3466 target_ulong len, int type)
3467{
3468 int n;
3469
3470 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
b9bec74b 3471 if (n < 0) {
e22a25c9 3472 return -ENOENT;
b9bec74b 3473 }
e22a25c9
AL		 3474 nb_hw_breakpoint--;
3475 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3476
3477 return 0;
3478}
3479
3480void kvm_arch_remove_all_hw_breakpoints(void)
3481{
3482 nb_hw_breakpoint = 0;
3483}
3484
3485static CPUWatchpoint hw_watchpoint;
3486
a60f24b5 3487static int kvm_handle_debug(X86CPU *cpu,
48405526 3488 struct kvm_debug_exit_arch *arch_info)
e22a25c9 3489{
ed2803da 3490 CPUState *cs = CPU(cpu);
a60f24b5 3491 CPUX86State *env = &cpu->env;
f2574737 3492 int ret = 0;
e22a25c9
AL		 3493 int n;
3494
3495 if (arch_info->exception == 1) {
3496 if (arch_info->dr6 & (1 << 14)) {
ed2803da 3497 if (cs->singlestep_enabled) {
f2574737 3498 ret = EXCP_DEBUG;
b9bec74b 3499 }
e22a25c9 3500 } else {
b9bec74b
JK		 3501 for (n = 0; n < 4; n++) {
3502 if (arch_info->dr6 & (1 << n)) {
e22a25c9
AL		 3503 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3504 case 0x0:
f2574737 3505 ret = EXCP_DEBUG;
e22a25c9
AL		 3506 break;
3507 case 0x1:
f2574737 3508 ret = EXCP_DEBUG;
ff4700b0 3509 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3510 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3511 hw_watchpoint.flags = BP_MEM_WRITE;
3512 break;
3513 case 0x3:
f2574737 3514 ret = EXCP_DEBUG;
ff4700b0 3515 cs->watchpoint_hit = &hw_watchpoint;
e22a25c9
AL		 3516 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3517 hw_watchpoint.flags = BP_MEM_ACCESS;
3518 break;
3519 }
b9bec74b
JK		 3520 }
3521 }
e22a25c9 3522 }
ff4700b0 3523 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
f2574737 3524 ret = EXCP_DEBUG;
b9bec74b 3525 }
f2574737 3526 if (ret == 0) {
ff4700b0 3527 cpu_synchronize_state(cs);
48405526 3528 assert(env->exception_injected == -1);
b0b1d690 3529
f2574737 3530 /* pass to guest */
48405526
BS		 3531 env->exception_injected = arch_info->exception;
3532 env->has_error_code = 0;
b0b1d690 3533 }
e22a25c9 3534
f2574737 3535 return ret;
e22a25c9
AL		 3536}
3537
20d695a9 3538void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
e22a25c9
AL		 3539{
3540 const uint8_t type_code[] = {
3541 [GDB_BREAKPOINT_HW] = 0x0,
3542 [GDB_WATCHPOINT_WRITE] = 0x1,
3543 [GDB_WATCHPOINT_ACCESS] = 0x3
3544 };
3545 const uint8_t len_code[] = {
3546 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3547 };
3548 int n;
3549
a60f24b5 3550 if (kvm_sw_breakpoints_active(cpu)) {
e22a25c9 3551 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
b9bec74b 3552 }
e22a25c9
AL		 3553 if (nb_hw_breakpoint > 0) {
3554 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3555 dbg->arch.debugreg[7] = 0x0600;
3556 for (n = 0; n < nb_hw_breakpoint; n++) {
3557 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3558 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3559 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
95c077c9 3560 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
e22a25c9
AL		 3561 }
3562 }
3563}
4513d923 3564
2a4dac83
JK		 3565static bool host_supports_vmx(void)
3566{
3567 uint32_t ecx, unused;
3568
3569 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3570 return ecx & CPUID_EXT_VMX;
3571}
3572
3573#define VMX_INVALID_GUEST_STATE 0x80000021
3574
20d695a9 3575int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
2a4dac83 3576{
20d695a9 3577 X86CPU *cpu = X86_CPU(cs);
2a4dac83
JK		 3578 uint64_t code;
3579 int ret;
3580
3581 switch (run->exit_reason) {
3582 case KVM_EXIT_HLT:
3583 DPRINTF("handle_hlt\n");
4b8523ee 3584 qemu_mutex_lock_iothread();
839b5630 3585 ret = kvm_handle_halt(cpu);
4b8523ee 3586 qemu_mutex_unlock_iothread();
2a4dac83
JK		 3587 break;
3588 case KVM_EXIT_SET_TPR:
3589 ret = 0;
3590 break;
d362e757 3591 case KVM_EXIT_TPR_ACCESS:
4b8523ee 3592 qemu_mutex_lock_iothread();
f7575c96 3593 ret = kvm_handle_tpr_access(cpu);
4b8523ee 3594 qemu_mutex_unlock_iothread();
d362e757 3595 break;
2a4dac83
JK		 3596 case KVM_EXIT_FAIL_ENTRY:
3597 code = run->fail_entry.hardware_entry_failure_reason;
3598 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3599 code);
3600 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3601 fprintf(stderr,
12619721 3602 "\nIf you're running a guest on an Intel machine without "
2a4dac83
JK		 3603 "unrestricted mode\n"
3604 "support, the failure can be most likely due to the guest "
3605 "entering an invalid\n"
3606 "state for Intel VT. For example, the guest maybe running "
3607 "in big real mode\n"
3608 "which is not supported on less recent Intel processors."
3609 "\n\n");
3610 }
3611 ret = -1;
3612 break;
3613 case KVM_EXIT_EXCEPTION:
3614 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3615 run->ex.exception, run->ex.error_code);
3616 ret = -1;
3617 break;
f2574737
JK		 3618 case KVM_EXIT_DEBUG:
3619 DPRINTF("kvm_exit_debug\n");
4b8523ee 3620 qemu_mutex_lock_iothread();
a60f24b5 3621 ret = kvm_handle_debug(cpu, &run->debug.arch);
4b8523ee 3622 qemu_mutex_unlock_iothread();
f2574737 3623 break;
50efe82c
AS		 3624 case KVM_EXIT_HYPERV:
3625 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3626 break;
15eafc2e
PB		 3627 case KVM_EXIT_IOAPIC_EOI:
3628 ioapic_eoi_broadcast(run->eoi.vector);
3629 ret = 0;
3630 break;
2a4dac83
JK		 3631 default:
3632 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3633 ret = -1;
3634 break;
3635 }
3636
3637 return ret;
3638}
3639
20d695a9 3640bool kvm_arch_stop_on_emulation_error(CPUState *cs)
4513d923 3641{
20d695a9
AF		 3642 X86CPU *cpu = X86_CPU(cs);
3643 CPUX86State *env = &cpu->env;
3644
dd1750d7 3645 kvm_cpu_synchronize_state(cs);
b9bec74b
JK		 3646 return !(env->cr[0] & CR0_PE_MASK) ||
3647 ((env->segs[R_CS].selector & 3) != 3);
4513d923 3648}
84b058d7
JK		 3649
3650void kvm_arch_init_irq_routing(KVMState *s)
3651{
3652 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3653 /* If kernel can't do irq routing, interrupt source
3654 * override 0->2 cannot be set up as required by HPET.
3655 * So we have to disable it.
3656 */
3657 no_hpet = 1;
3658 }
cc7e0ddf 3659 /* We know at this point that we're using the in-kernel
614e41bc 3660 * irqchip, so we can use irqfds, and on x86 we know
f3e1bed8 3661 * we can use msi via irqfd and GSI routing.
cc7e0ddf 3662 */
614e41bc 3663 kvm_msi_via_irqfd_allowed = true;
f3e1bed8 3664 kvm_gsi_routing_allowed = true;
15eafc2e
PB		 3665
3666 if (kvm_irqchip_is_split()) {
3667 int i;
3668
3669 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3670 MSI routes for signaling interrupts to the local apics. */
3671 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
d1f6af6a 3672 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
15eafc2e
PB		 3673 error_report("Could not enable split IRQ mode.");
3674 exit(1);
3675 }
3676 }
3677 }
3678}
3679
3680int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3681{
3682 int ret;
3683 if (machine_kernel_irqchip_split(ms)) {
3684 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3685 if (ret) {
df3c286c 3686 error_report("Could not enable split irqchip mode: %s",
15eafc2e
PB		 3687 strerror(-ret));
3688 exit(1);
3689 } else {
3690 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3691 kvm_split_irqchip = true;
3692 return 1;
3693 }
3694 } else {
3695 return 0;
3696 }
84b058d7 3697}
b139bd30
JK		 3698
3699/* Classic KVM device assignment interface. Will remain x86 only. */
3700int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3701 uint32_t flags, uint32_t *dev_id)
3702{
3703 struct kvm_assigned_pci_dev dev_data = {
3704 .segnr = dev_addr->domain,
3705 .busnr = dev_addr->bus,
3706 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3707 .flags = flags,
3708 };
3709 int ret;
3710
3711 dev_data.assigned_dev_id =
3712 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3713
3714 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3715 if (ret < 0) {
3716 return ret;
3717 }
3718
3719 *dev_id = dev_data.assigned_dev_id;
3720
3721 return 0;
3722}
3723
3724int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3725{
3726 struct kvm_assigned_pci_dev dev_data = {
3727 .assigned_dev_id = dev_id,
3728 };
3729
3730 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3731}
3732
3733static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3734 uint32_t irq_type, uint32_t guest_irq)
3735{
3736 struct kvm_assigned_irq assigned_irq = {
3737 .assigned_dev_id = dev_id,
3738 .guest_irq = guest_irq,
3739 .flags = irq_type,
3740 };
3741
3742 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3743 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3744 } else {
3745 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3746 }
3747}
3748
3749int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3750 uint32_t guest_irq)
3751{
3752 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3753 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3754
3755 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3756}
3757
3758int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3759{
3760 struct kvm_assigned_pci_dev dev_data = {
3761 .assigned_dev_id = dev_id,
3762 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3763 };
3764
3765 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3766}
3767
3768static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3769 uint32_t type)
3770{
3771 struct kvm_assigned_irq assigned_irq = {
3772 .assigned_dev_id = dev_id,
3773 .flags = type,
3774 };
3775
3776 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3777}
3778
3779int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3780{
3781 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3782 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3783}
3784
3785int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3786{
3787 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3788 KVM_DEV_IRQ_GUEST_MSI, virq);
3789}
3790
3791int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3792{
3793 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3794 KVM_DEV_IRQ_HOST_MSI);
3795}
3796
3797bool kvm_device_msix_supported(KVMState *s)
3798{
3799 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3800 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3801 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3802}
3803
3804int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3805 uint32_t nr_vectors)
3806{
3807 struct kvm_assigned_msix_nr msix_nr = {
3808 .assigned_dev_id = dev_id,
3809 .entry_nr = nr_vectors,
3810 };
3811
3812 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3813}
3814
3815int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3816 int virq)
3817{
3818 struct kvm_assigned_msix_entry msix_entry = {
3819 .assigned_dev_id = dev_id,
3820 .gsi = virq,
3821 .entry = vector,
3822 };
3823
3824 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3825}
3826
3827int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3828{
3829 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3830 KVM_DEV_IRQ_GUEST_MSIX, 0);
3831}
3832
3833int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3834{
3835 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3836 KVM_DEV_IRQ_HOST_MSIX);
3837}
9e03a040
FB		 3838
3839int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
dc9f06ca 3840 uint64_t address, uint32_t data, PCIDevice *dev)
9e03a040 3841{
8b5ed7df
PX		 3842 X86IOMMUState *iommu = x86_iommu_get_default();
3843
3844 if (iommu) {
3845 int ret;
3846 MSIMessage src, dst;
3847 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3848
0ea1472d
JK		 3849 if (!class->int_remap) {
3850 return 0;
3851 }
3852
8b5ed7df
PX		 3853 src.address = route->u.msi.address_hi;
3854 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3855 src.address |= route->u.msi.address_lo;
3856 src.data = route->u.msi.data;
3857
3858 ret = class->int_remap(iommu, &src, &dst, dev ? \
3859 pci_requester_id(dev) : \
3860 X86_IOMMU_SID_INVALID);
3861 if (ret) {
3862 trace_kvm_x86_fixup_msi_error(route->gsi);
3863 return 1;
3864 }
3865
3866 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3867 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3868 route->u.msi.data = dst.data;
3869 }
3870
9e03a040
FB		 3871 return 0;
3872}
1850b6b7 3873
38d87493
PX		 3874typedef struct MSIRouteEntry MSIRouteEntry;
3875
3876struct MSIRouteEntry {
3877 PCIDevice *dev; /* Device pointer */
3878 int vector; /* MSI/MSIX vector index */
3879 int virq; /* Virtual IRQ index */
3880 QLIST_ENTRY(MSIRouteEntry) list;
3881};
3882
3883/* List of used GSI routes */
3884static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3885 QLIST_HEAD_INITIALIZER(msi_route_list);
3886
e1d4fb2d
PX		 3887static void kvm_update_msi_routes_all(void *private, bool global,
3888 uint32_t index, uint32_t mask)
3889{
a56de056 3890 int cnt = 0, vector;
e1d4fb2d
PX		 3891 MSIRouteEntry *entry;
3892 MSIMessage msg;
fd563564
PX		 3893 PCIDevice *dev;
3894
e1d4fb2d
PX		 3895 /* TODO: explicit route update */
3896 QLIST_FOREACH(entry, &msi_route_list, list) {
3897 cnt++;
a56de056 3898 vector = entry->vector;
fd563564 3899 dev = entry->dev;
a56de056
PX		 3900 if (msix_enabled(dev) && !msix_is_masked(dev, vector)) {
3901 msg = msix_get_message(dev, vector);
3902 } else if (msi_enabled(dev) && !msi_is_masked(dev, vector)) {
3903 msg = msi_get_message(dev, vector);
3904 } else {
3905 /*
3906 * Either MSI/MSIX is disabled for the device, or the
3907 * specific message was masked out. Skip this one.
3908 */
fd563564
PX		 3909 continue;
3910 }
fd563564 3911 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
e1d4fb2d 3912 }
3f1fea0f 3913 kvm_irqchip_commit_routes(kvm_state);
e1d4fb2d
PX		 3914 trace_kvm_x86_update_msi_routes(cnt);
3915}
3916
38d87493
PX		 3917int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3918 int vector, PCIDevice *dev)
3919{
e1d4fb2d 3920 static bool notify_list_inited = false;
38d87493
PX		 3921 MSIRouteEntry *entry;
3922
3923 if (!dev) {
3924 /* These are (possibly) IOAPIC routes only used for split
3925 * kernel irqchip mode, while what we are housekeeping are
3926 * PCI devices only. */
3927 return 0;
3928 }
3929
3930 entry = g_new0(MSIRouteEntry, 1);
3931 entry->dev = dev;
3932 entry->vector = vector;
3933 entry->virq = route->gsi;
3934 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3935
3936 trace_kvm_x86_add_msi_route(route->gsi);
e1d4fb2d
PX		 3937
3938 if (!notify_list_inited) {
3939 /* For the first time we do add route, add ourselves into
3940 * IOMMU's IEC notify list if needed. */
3941 X86IOMMUState *iommu = x86_iommu_get_default();
3942 if (iommu) {
3943 x86_iommu_iec_register_notifier(iommu,
3944 kvm_update_msi_routes_all,
3945 NULL);
3946 }
3947 notify_list_inited = true;
3948 }
38d87493
PX		 3949 return 0;
3950}
3951
3952int kvm_arch_release_virq_post(int virq)
3953{
3954 MSIRouteEntry *entry, *next;
3955 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3956 if (entry->virq == virq) {
3957 trace_kvm_x86_remove_msi_route(virq);
3958 QLIST_REMOVE(entry, list);
01960e6d 3959 g_free(entry);
38d87493
PX		 3960 break;
3961 }
3962 }
9e03a040
FB		 3963 return 0;
3964}
1850b6b7
EA		 3965
3966int kvm_arch_msi_data_to_gsi(uint32_t data)
3967{
3968 abort();
3969}
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